AT28HC256F-70PI

Features • Fast Read Access Time – 70 ns • Automatic Page Write Operation – Internal Address and Data Latches for 64 Bytes – Internal Control Timer Fast Write Cycle Times – Page Write Cycle Time: 3 ms or 10 ms Maximum – 1 to 64-byte Page Write Operation Low Power Dissipation – 80 mA Active Current – 3 mA Standby Current Hardware and Software Data Protection DATA Polling for End of Write Detection High Reliability CMOS Technology – Endurance: 104 or 105 Cycles – Data Retention: 10 Years Single 5V ± 10% Supply CMOS and TTL Compatible Inputs and Outputs JEDEC Approved Byte-wide Pinout Full Military and Industrial Temperature Ranges Green (Pb/Halide-free) Packaging Option • • • • • 256 (32K x 8) High-speed Parallel EEPROM AT28HC256 • • • • • 1. Description The AT28HC256 is a high-performance electrically erasable and programmable readonly memory. Its 256K of memory is organized as 32,768 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the AT28HC256 offers access times to 70 ns with power dissipation of just 440 mW. When the AT28HC256 is deselected, the standby current is less than 5 mA. The AT28HC256 is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the address and 1 to 64 bytes of data are internally latched, freeing the addresses and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA Polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin. Atmel’s 28HC256 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. 0007L–PEEPR–03/08 2. Pin Configurations Pin Name A0 - A14 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect 2.1 28-lead TSOP Top View OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 2.3 32-pad LCC, 32-lead PLCC Top View A7 A12 A14 DC VCC WE A13 Note: PLCC package pins 1 and 17 are Don’t Connect. 2.2 28-lead PGA Top View 2.4 28-lead Cerdip/PDIP/Flatpack/SOIC – Top View A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 2 AT28HC256 0007L–PEEPR–03/08 I/O1 I/O2 GND DC I/O3 I/O4 I/O5 14 15 16 17 18 19 20 A6 A5 A4 A3 A2 A1 A0 NC I/O0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A11 NC OE A10 CE I/O7 I/O6 AT28HC256 3. Block Diagram 4. Device Operation 4.1 Read The AT28HC256 is accessed like a Static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their system. 4.2 Byte Write A low pulse on the WE or CE input with CE or WE low (respectively) and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. 4.3 Page Write The page write operation of the AT28HC256 allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write; the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 150 µs (tBLC) of the previous byte. If the tBLC limit is exceeded the AT28C256 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 - A14 inputs. That is, for each WE high to low transition during the page write operation, A6 - A14 must be the same. The A0 to A5 inputs are used to specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written; unnecessary cycling of other bytes within the page does not occur. 4.4 DATA Polling The AT28HC256 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. 3 0007L–PEEPR–03/08 4.5 Toggle Bit In addition to DATA Polling the AT28HC256 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Testing the toggle bit may begin at any time during the write cycle. 4.6 Data Protection If precautions are not taken, inadvertent writes to any 5-volt-only nonvolatile memory may occur during transition of the host system power supply. Atmel® has incorporated both hardware and software features that will protect the memory against inadvertent writes. 4.6.1 Hardware Protection Hardware features protect against inadvertent writes to the AT28HC256 in the following ways: (a) VCC sense – if VCC is below 3.8V (typical) the write function is inhibited; (b) VCC power-on delay – once VCC has reached 3.8V the device will automatically time out 5 ms typical) before allowing a write; (c) write inhibit – holding any one of OE low, CE high or WE high inhibits write cycles; and (d) noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a write cycle. Software Data Protection A software controlled data protection feature has been implemented on the AT28HC256. When enabled, the software data protection (SDP), will prevent inadvertent writes. The SDP feature may be enabled or disabled by the user; the AT28HC256 is shipped from Atmel with SDP disabled. SDP is enabled by the host system issuing a series of three write commands; three specific bytes of data are written to three specific addresses (refer to “Software Data Protection” algorithm). After writing the 3-byte command sequence and after tWC the entire AT28HC256 will be protected against inadvertent write operations. It should be noted, that once protected the host may still perform a byte or page write to the AT28HC256. This is done by preceding the data to be written by the same 3-byte command sequence. Once set, SDP will remain active unless the disable command sequence is issued. Power transitions do not disable SDP and SDP will protect the AT28HC256 during power-up and power-down conditions. All command sequences must conform to the page write timing specifications. It should also be noted that the data in the enable and disable command sequences is not written to the device and the memory addresses used in the sequence may be written with data in either a byte or page write operation. After setting SDP, any attempt to write to the device without the three byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, read operations will effectively be polling operations. 4.6.2 4.7 Device Identification An extra 64 bytes of EEPROM memory are available to the user for device identification. By raising A9 to 12V ± 0.5V and using address locations 7FC0H to 7FFFH the additional bytes may be written to or read from in the same manner as the regular memory array. 4.8 Optional Chip Erase Mode The entire device can be erased using a 6-byte software code. Please see “Software Chip Erase” application note for details. 4 AT28HC256 0007L–PEEPR–03/08 AT28HC256 5. DC and AC Operating Range AT28HC256-70 Operating Temperature (Case) VCC Power Supply Ind. Mil. 5V ± 10% -40°C - 85°C AT28HC256-90 -40°C - 85°C -55°C - 125°C 5V ± 10% AT28HC256-12 -40°C - 85°C -55°C - 125°C 5V ± 10% 6. Operating Modes Mode Read Write (2) CE VIL VIL VIH X X X VIL OE VIL VIH X(1) X VIL VIH VH(3) WE VIH VIL X VIH X X VIL I/O DOUT DIN High Z Standby/Write Inhibit Write Inhibit Write Inhibit Output Disable Chip Erase Notes: 1. X can be VIL or VIH. 2. Refer to AC programming waveforms. 3. VH = 12.0V ± 0.5V. High Z High Z 7. Absolute Maximum Ratings* Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability 8. DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current TTL VCC Standby Current CMOS VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 6.0 mA IOH = -4 mA 2.4 2.0 0.45 Condition VIN = 0V to VCC + 1V VI/O = 0V to VCC CE = 2.0V to VCC CE = VCC - 0.3V to VCC f = 5 MHz; IOUT = 0 mA AT28HC256-90, -12 AT28HC256-70 AT28HC256-90, -12 Min Max 10 10 3 60 300 80 0.8 Units µA µA mA mA µA mA V V V V 5 0007L–PEEPR–03/08 9. AC Read Characteristics AT28HC256-70 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first 0 0 0 Min Max 70 70 35 35 0 0 0 AT28C256-90 Min Max 90 90 40 40 0 0 0 AT28HC256-12 Min Max 120 120 50 50 Units ns ns ns ns ns 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 6 AT28HC256 0007L–PEEPR–03/08 AT28HC256 11. Input Test Waveforms and Measurement Level tR, tF < 5 ns 12. Output Test Load 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 1. This parameter is characterized and is not 100% tested. 7 0007L–PEEPR–03/08 14. AC Write Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tDV Note: Parameter Address, OE Setup Time Address Hold Time Chip Select Setup Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Setup Time Data, OE Hold Time Time to Data Valid 1. NR = No Restriction. Min 0 50 0 0 100 50 0 NR(1) Max Units ns ns ns ns ns ns ns 15. AC Write Waveforms 15.1 WE Controlled 15.2 CE Controlled 8 AT28HC256 0007L–PEEPR–03/08 AT28HC256 16. Page Mode Write Characteristics Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter AT28HC256 Write Cycle Time (option available) AT28HC256F Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 50 0 50 50 0 100 150 2 3 ms ns ns ns ns ns µs ns Min Typ 5 Max 10 Units ms 17. Page Mode Write Waveforms(1)(2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE). 2. OE must be high only when WE and CE are both low. 18. Chip Erase Waveforms tS = tH = 5 µsec (min.) tW = 10 msec (min.) VH = 12.0V ± 0.5V 9 0007L–PEEPR–03/08 19. Software Data Protection Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 20. Software Data Protection Disable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED(2) LOAD DATA 80 TO ADDRESS 5555 LOAD DATA XX TO ANY ADDRESS(4) LOAD DATA AA TO ADDRESS 5555 LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE LOAD DATA 55 TO ADDRESS 2AAA Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Write Protect state will be activated at end of write even if no other data is loaded. 3. Write Protect state will be deactivated at end of write period even if no other data is loaded. 4. 1 to 64 bytes of data are loaded. LOAD DATA 20 TO ADDRESS 5555 EXIT DATA PROTECT STATE(3) LOAD DATA XX TO ANY ADDRESS(4) LOAD LAST BYTE TO LAST ADDRESS 21. Software Protected Write Cycle Waveforms(1)(2) Notes: 1. A6 through A14 must specify the same page address during each high to low transition of WE (or CE) after the software code has been entered. 2. OE must be high only when WE and CE are both low. 10 AT28HC256 0007L–PEEPR–03/08 AT28HC256 22. Data Polling Characteristics(1) Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Min 0 0 Typ Max Units ns ns ns Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 6. 0 ns 23. Data Polling Waveforms 24. Toggle Bit Characteristics(1) Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See “AC Read Characteristics” on page 6. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns 25. Toggle Bit Waveforms Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 11 0007L–PEEPR–03/08 26. Normalized ICC Graphs 12 AT28HC256 0007L–PEEPR–03/08 AT28HC256 27. Ordering Information(1) 27.1 tACC (ns) Standard Package ICC (mA) Active Standby Ordering Code AT28HC256(E,F)-70JI AT28HC256(E,F)-70PI AT28HC256(E,F)-70SI AT28HC256(E,F)-70TI AT28HC256(E,F)-90JI AT28HC256(E,F)-90PI AT28HC256(E,F)-90SI AT28HC256(E,F)-90TI AT28HC256(E,F)-90DM/883 AT28HC256(E,F)-90FM/883 AT28HC256(E,F)-90LM/883 AT28HC256(E,F)-90UM/883 AT28HC256(E,F)-12JI AT28HC256(E,F)-12PI AT28HC256(E,F)-12SI AT28HC256(E,F)-12TI AT28HC256(E,F)-12DM/883 AT28HC256(E,F)-12FM/883 AT28HC256(E,F)-12LM/883 AT28HC256(E,F)-12UM/883 Package 32J 28P6 28S 28T 32J 28P6 28S 28T 28D6 28F 32L 28U 32J 28P6 28S 28T 28D6 28F 32L 28U Operation Range 70 80 0.3 Industrial (-40° C to 85° C) 90 80 0.3 Military/883C Class B, Fully Compliant (-55° C to 125° C) Industrial (-40° C to 85° C) 120 80 0.3 Military/883C Class B, Fully Compliant (-55° C to 125° C) Package Type 28D6 28F 32J 32L 28P6 28S 28T 28U 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack) 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC) 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28-lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC) 28-lead, Plastic Thin Small Outline Package (TSOP) 28-pin, Ceramic Pin Grid Array (PGA) Options Blank E F Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms High Endurance Option: Endurance = 100K Write Cycles Fast Write Option: Write Time = 3 ms 13 0007L–PEEPR–03/08 27.1 tACC (ns) Standard Package (Continued) ICC (mA) Active Standby Ordering Code 5962-88634 03 UX 5962-88634 03 XX 5962-88634 03 YX 5962-88634 03 ZX 5962-88634 04 UX 5962-88634 04 XX 5962-88634 04 YX 5962-88634 04 ZX 5962-88634 01 UX 5962-88634 01 XX 5962-88634 01 YX 5962-88634 01 ZX 5962-88634 02 UX 5962-88634 02 XX 5962-88634 02 YX 5962-88634 02 ZX Package 28U 28D6 32L 28F 28U 28D6 32L 28F 28U 28D6 32L 28F 28U 28D6 32L 28F Operation Range Military/883C Class B, Fully Compliant (-55° C to 125° C) Military/883C Class B, Fully Compliant (-55° C to 125° C) Military/883C Class B, Fully Compliant (-55° C to 125° C) Military/883C Class B, Fully Compliant (-55° C to 125° C) 80 90 80 0.3 0.3 80 120 80 0.3 0.3 Note: 1. See “Valid Part Numbers” on page 16. Package Type 28D6 28F 32J 32L 28P6 28S 28T 28U 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (Flatpack) 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32-pad, Non-windowed, Ceramic Leadless Chip Carrier (LCC) 28-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 28-lead, 0.300" Wide Plastic Gull Wing Small Outline (SOIC) 28-lead, Plastic Thin Small Outline Package (TSOP) 28-pin, Ceramic Pin Grid Array (PGA) Options Blank E F Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms High Endurance Option: Endurance = 100K Write Cycles Fast Write Option: Write Time = 3 ms 14 AT28HC256 0007L–PEEPR–03/08 AT28HC256 27.2 tACC (ns) 70 Green Package Option (Pb/Halide-free) ICC (mA) Active 80 Standby 0.3 Ordering Code AT28HC256(E, F)-70JU AT28HC256(E, F)-70SU AT28HC256(E, F)-70TU AT28HC256(E, F)-90JU AT28HC256(E, F)-90SU AT28HC256(E, F)-90TU AT28HC256(E, F)-12JU AT28HC256(E, F)-12SU AT28HC256(E, F)-12TU Package 32J 28S 28T 32J 28S 28T 32J 28S 28T Industrial (-40° C to 85° C) Operation Range 90 80 0.3 120 80 0.3 Package Type 32J 28S 28T 32-lead, Plastic J-leaded Chip Carrier (PLCC) 28-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 28-lead, Plastic Thin Small Outline Package (TSOP) 15 0007L–PEEPR–03/08 Options Blank F Standard Device: Endurance = 10K Write Cycles; Write Time = 10 ms Fast Write Option: Write Time = 3 ms 28. Ordering Information Note Previous datasheets included the low power suffixes L, LE and LF on the AT28HC256 for 120 ns and 90 ns speeds. The low power parameters are now standard; therefore, the L, LE and LF suffixes are no longer required. 29. Valid Part Numbers The following table lists standard Atmel products that can be ordered: Device Numbers AT28HC256 AT28HC256 AT28HC256E AT28HC256F AT28HC256 AT28HC256E AT28HC256F Speed 70 90 90 90 12 12 12 Package and Temperature Combinations JI, JU, PI, PU, SI, SU, TI, TU JI, JU, PI, SI, SU, TI, TU, DM/883, FM/883, LM/883, UM/883 JI, JU, PI, PU, SI, SU, TI, TU, DM/883, FM/883, LM/883, UM/883 JI, JU, PI, SU, TI, TU, DM/883, FM/883, LM/883, UM/883 JI, JU, PI, SU, TI, TU, DM/883, FM/883, LM/883, UM/883 JI, JU, PI, PU, SI, SU, TI, TU, DM/883, FM/883, LM/883, UM/883 JI, JU, PI, SU, TI, TU, DM/883, FM/883, LM/883, UM/883 30. Die Products Reference Section: Parallel EEPROM Die Products 16 AT28HC256 0007L–PEEPR–03/08 AT28HC256 31. Packaging Information 31.1 28D6 – Cerdip Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 D-10 Config A (Glass Sealed) 37.85(1.490) 36.58(1.440) PIN 1 15.49(0.610) 12.95(0.510) 33.02(1.300) REF 5.72(0.225) MAX SEATING PLANE 5.08(0.200) 3.18(0.125) 2.54(0.100)BSC 1.65(0.065) 1.14(0.045) 15.70(0.620) 15.00(0.590) 0.46(0.018) 0.20(0.008) 0.127(0.005)MIN 1.52(0.060) 0.38(0.015) 0.66(0.026) 0.36(0.014) 0º~ 15º REF 17.80(0.700) MAX 10/23/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 28D6, 28-lead, 0.600" Wide, Non-windowed, Ceramic Dual Inline Package (Cerdip) DRAWING NO. 28D6 REV. B R 17 0007L–PEEPR–03/08 31.2 28F – Flatpack Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 F-12 Config B PIN #1 ID 9.40(0.370) 6.35(0.250) 0.56(0.022) 0.38(0.015) 1.27(0.050) BSC 18.49(0.728) 18.08(0.712) 1.14(0.045) MAX 10.57(0.416) 9.75(0.384) 0.23(0.009) 0.10(0.004) 3.02(0.119) 2.29(0.090) 1.96(0.077) 1.09(0.043) 7.26(0.286) 6.96(0.274) 1.14(0.045) 0.660(0.026) 10/21/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 28F, 28-lead, Non-windowed, Ceramic Bottom-brazed Flat Package (FlatPack) DRAWING NO. 28F REV. B R 18 AT28HC256 0007L–PEEPR–03/08 AT28HC256 31.3 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 B E B1 E2 e D1 D A A2 A1 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D2 MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330 NOM – – – – – – – – – – – 1.270 TYP MAX 3.556 2.413 – 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533 NOTE A A1 A2 D D1 D2 Note 2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E E1 E2 B B1 e Note 2 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B R 19 0007L–PEEPR–03/08 31.4 32L – LCC Dimensions in Millimeters and (Inches). Controlling dimension: Inches. MIL-STD 1835 C-12 11.63(0.458) 11.23(0.442) 2.54(0.100) 2.16(0.085) 14.22(0.560) 13.72(0.540) PIN 1 1.40(0.055) 1.14(0.045) 1.91(0.075) 1.40(0.055) 2.41(0.095) 1.91(0.075) INDEX CORNER 0.635(0.025) X 45˚ 0.381(0.015) 0.305(0.012) RADIUS 0.178(0.007) 10.16(0.400) BSC 0.737(0.029) 0.533(0.021) 1.27(0.050) TYP 1.02(0.040) X 45˚ 2.16(0.085) 1.65(0.065) 7.62(0.300) BSC 10/21/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 32L, 32-pad, Non-windowed, Ceramic Lid, Leadless Chip Carrier (LCC) DRAWING NO. 32L REV. B R 20 AT28HC256 0007L–PEEPR–03/08 AT28HC256 31.5 28P6 – PDIP D PIN 1 E1 A SEATING PLANE L B1 e E B A1 C eB 0º ~ 15º REF SYMBOL A A1 D E E1 B COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.381 36.703 15.240 13.462 0.356 1.041 3.048 0.203 15.494 NOM – – – – – – – – – – 2.540 TYP MAX 4.826 – 37.338 15.875 13.970 0.559 1.651 3.556 0.381 17.526 Note 2 Note 2 NOTE Notes: 1. This package conforms to JEDEC reference MS-011, Variation AB. 2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). B1 L C eB e 09/28/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 28P6, 28-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) DRAWING NO. 28P6 REV. B R 21 0007L–PEEPR–03/08 31.6 28S – SOIC Dimensions in Millimeters and (Inches). Controlling dimension: Millimeters. 0.51(0.020) 0.33(0.013) 7.60(0.2992) 10.65(0.419) 7.40(0.2914) 10.00(0.394) PIN 1 1.27(0.50) BSC TOP VIEW 18.10(0.7125) 17.70(0.6969) 2.65(0.1043) 2.35(0.0926) 0.30(0.0118) 0.10(0.0040) SIDE VIEWS 0º ~ 8º 0.32(0.0125) 0.23(0.0091) 1.27(0.050) 0.40(0.016) 8/4/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 28S, 28-lead, 0.300" Body, Plastic Gull Wing Small Outline (SOIC) JEDEC Standard MS-013 DRAWING NO. 28S REV. B R 22 AT28HC256 0007L–PEEPR–03/08 AT28HC256 31.7 28T – TSOP PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L e b L1 E A2 A SEATING PLANE GAGE PLANE A1 SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.05 0.90 13.20 11.70 7.90 0.50 NOM – – 1.00 13.40 11.80 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 – 0.55 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 13.60 11.90 8.10 0.70 Note 2 Note 2 NOTE 12/06/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 28T REV. C R 23 0007L–PEEPR–03/08 31.8 28U – PGA Dimensions in Millimeters and (Inches). Controlling dimension: Inches. 7.26(0.286) 6.50(0.256) 13.74(0.540) 13.36(0.526) 2.57(0.101) 2.06(0.081) 1.40(0.055) 1.14(0.045) 15.24(0.600) 14.88(0.586) 0.58(0.023) 0.43(0.017) 3.12(0.123) 2.62(0.103) 1.83(0.072) 1.57(0.062) 14.17(0.558) 13.77(0.542) 2.54(0.100) TYP 16.71(0.658) 16.31(0.642) 12.70(0.500) TYP 2.54(0.100) TYP 10.41(0.410) 9.91(0.390) 10/21/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 28U, 28-pin, Ceramic Pin Grid Array (PGA) DRAWING NO. 28U REV. B R 24 AT28HC256 0007L–PEEPR–03/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support p_eeprom@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. 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