AT29LV512-12JU

Features • • • • Single Supply Voltage, Range 3V to 3.6V 3-volt Only Read and Write Operation Software Protected Programming Low-power Dissipation – 15 mA Active Current – 50 µA CMOS Standby Current Fast Read Access Time – 120 ns Sector Program Operation – Single-cycle Reprogram (Erase and Program) – 512 Sectors (128 Bytes/Sector) – Internal Address and Data Latches for 128 Bytes Fast Sector Program Cycle Time – 20 ms Max Internal Program Control and Timer DATA Polling for End of Program Detection Typical Endurance > 10,000 Cycles CMOS and TTL Compatible Inputs and Outputs Green (Pb/Halide-free) Packaging Option • • • • • • • • 512K (64K x 8) 3-volt Only Flash Memory AT29LV512 1. Description The AT29LV512 is a 3-volt-only in-system Flash programmable erasable read-only memory (PEROM). Its 512K of memory is organized as 65,536 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 120 ns with power dissipation of just 54 mW over the industrial temperature range. When the device is deselected, the CMOS standby current is less than 50 µA. The device endurance is such that any sector can typically be written to in excess of 10,000 times. To allow for simple in-system reprogrammability, the AT29LV512 does not require high input voltages for programming. Three-volt-only commands determine the operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT29LV512 is performed on a sector basis; 128 bytes of data are loaded into the device and then simultaneously programmed. During a reprogram cycle, the address locations and 128 bytes of data are captured at microprocessor speed and internally latched, freeing the address and data bus for other operations. Following the initiation of a program cycle, the device will automatically erase the sector and then program the latched data using an internal control timer. The end of a program cycle can be detected by DATA polling of I/O7. Once the end of a program cycle has been detected, a new access for a read or program can begin. 0177O–FLASH–9/08 2. Pin Configurations Pin Name A0 - A15 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect 2.1 32-lead PLCC Top View A12 A15 NC NC VCC WE NC 2.2 32-lead TSOP (Type 1) Top View A11 A9 A8 A13 A14 NC WE VCC NC NC A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 2 AT29LV512 0177O–FLASH–9/08 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 14 15 16 17 18 19 20 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 AT29LV512 3. Block Diagram 4. Device Operation 4.1 Read The AT29LV512 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE o r OE i s high. This dualline control gives designers flexibility in preventing bus contention. 4.2 Software Data Protection Programming The AT29LV512 has 512 individual sectors, each 128 bytes. Using the software data protection feature, byte loads are used to enter the 128 bytes of a sector to be programmed. The AT29LV512 can only be programmed or reprogrammed using the software data protection feature. The device is programmed on a sector basis. If a byte of data within the sector is to be changed, data for the entire 128-byte sector must be loaded into the device. The AT29LV512 automatically does a sector erase prior to loading the data into the sector. An erase command is not required. Software data protection protects the device from inadvertent programming. A series of three program commands to specific addresses with specific data must be presented to the device before programming may occur. After writing the three-byte command sequence (and after tWC), the entire device is protected. The same three program commands must begin each program operation. All software program commands must obey the sector program timing specifications. Power transitions will not reset the software data protection feature; however, the software feature will guard against inadvertent program cycles during power transitions. Any attempt to write to the device without the 3-byte command sequence will start the internal write timers. No data will be written to the device; however, for the duration of tWC, a read operation will effectively be a polling operation. After the software data protection’s 3-byte command code is given, a byte load is performed by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. 3 0177O–FLASH–9/08 The 128 bytes of data must be loaded into each sector. Any byte that is not loaded during the programming of its sector will be erased to read FFh. Once the bytes of a sector are loaded into the device, they are simultaneously programmed during the internal programming period. After the first data byte has been loaded into the device, successive bytes are entered in the same manner. Each new byte to be programmed must have its high-to-low transition on WE (or CE) within 150 µs of the low-to-high transition of WE (or CE) of the preceding byte. If a high-to-low transition is not detected within 150 µs of the last low-to-high transition, the load period will end and the internal programming period will start. A7 to A15 specify the sector address. The sector address must be valid during each high-to-low transition of WE (or CE). A0 to A6 specify the byte address within the sector. The bytes may be loaded in any order; sequential loading is not required. Once a programming operation has been initiated, and for the duration of tWC, a read operation will effectively be a polling operation. 4.3 Hardware Data Protection Hardware features protect against inadvertent programs to the AT29LV512 in the following ways: (a) VCC sense – if VCC is below 1.8V (typical), the program function is inhibited; (b) VCC power on delay – once VCC has reached the VCC sense level, the device will automatically time out 10 ms (typical) before programming; (c) Program inhibit – holding any one of OE low, CE high or WE high inhibits program cycles; and (d) Noise filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. 4.4 Input Levels While operating with a 3.3V ±10% power supply, the address inputs and control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to 3.6 volts. 4.5 Product Identification The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. In addition, users may wish to use the software product identification mode to identify the part (i.e., using the device code), and have the system software use the appropriate sector size for program operations. In this manner, the user can have a common board design for 256K to 4-megabit densities and, with each density’s sector size in a memory map, have the system software apply the appropriate sector size. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. 4.6 DATA Polling The AT29LV512 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. 4 AT29LV512 0177O–FLASH–9/08 AT29LV512 4.7 Toggle Bit In addition to DATA polling, the AT29LV512 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. 4.8 Optional Chip Erase Mode The entire device can be erased by using a 6-byte software code. Please see Software Chip Erase application note for details. 5. Absolute Maximum Ratings* Temperature Under Bias............................... -55° C to +125° C Storage Temperature .................................... -65° C to +150° C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on A9 (including NC Pins) with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability 5 0177O–FLASH–9/08 6. DC and AC Operating Range AT29LV512-12 Operating Temperature (Case) VCC Power Supply Notes: (1) Industrial -40°C - 85°C 3.3V ± 0.3V 1. After power is applied and VCC is at the minimum specified data sheet value, the system should wait 20 ms before an operational mode is started. 7. Operating Modes Mode Read Program (2) CE VIL VIL VIH X X X OE VIL VIH X (1) WE VIH VIL X VIH X X Ai Ai Ai X I/O DOUT DIN High Z Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification Hardware X VIL VIH High Z VIL VIL VIH A1 - A15 = VIL, A9 = VH(3), A0 = VIL A1 - A15 = VIL, A9 = VH(3), A0 = VIH A0 = VIL A0 = VIH Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) Software(5) Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V ± 0.5V. 4. Manufacturer Code is 1F. The Device Code is 3D. 5. See details under Software Product Identification Entry/Exit. 8. DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA; VCC = 3.0V IOH = -100 µA; VCC = 3.0V 2.4 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA; VCC = 3.6V Min Max 1 1 50 1 15 0.6 Units µA µA µA mA mA V V V V 6 AT29LV512 0177O–FLASH–9/08 AT29LV512 9. AC Read Characteristics AT29LV512-12 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first 0 0 0 Min Max 120 120 50 30 Units ns ns ns ns ns 10. AC Read Waveforms(1)(2)(3)(4) Notes: 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. 3. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). 4. This parameter is characterized and is not 100% tested. 11. Input Test Waveforms and Measurement Level tR, tF < 5 ns 12. Output Test Load 7 0177O–FLASH–9/08 13. Pin Capacitance f = 1 MHz, T = 25°C(1) Symbol CIN COUT Note: Typ 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 1. These parameters are characterized and not 100% tested. 14. AC Byte Load Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 100 0 0 200 100 10 200 Max Units ns ns ns ns ns ns ns ns 15. AC Byte Load Waveforms(1)(2) 15.1 WE Controlled 15.2 CE Controlled 8 AT29LV512 0177O–FLASH–9/08 AT29LV512 16. Program Cycle Characteristics Symbol tWC tAS tAH tDS tDH tWP tBLC tWPH Parameter Write Cycle Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High 200 0 100 100 10 200 150 Min Max 20 Units ms ns ns ns ns ns µs ns 17. Software Protected Program Waveform(1)(2)(3) Notes: 1. OE must be high when WE and CE are both low. 2. A7 through A15 must specify the sector address during each high-to-low transition of WE (or CE) after the software code has been entered. 3. All bytes that are not loaded within the sector being programmed will be indeterminate. 18. Programming Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA A0 TO ADDRESS 5555 WRITES ENABLED LOAD DATA TO SECTOR (128 BYTES)(3) ENTER DATA PROTECT STATE(2) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Data Protect state will be re-activated at end of program cycle. 3. 128 bytes of data MUST BE loaded. 9 0177O–FLASH–9/08 19. Data Polling Characteristics(1) Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Min 10 10 Typ Max Units ns ns ns Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 0 ns 20. Data Polling Waveforms 21. Toggle Bit Characteristics(1) Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns 22. Toggle Bit Waveforms(1)(3) Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 10 AT29LV512 0177O–FLASH–9/08 AT29LV512 23. Software Product Identification Entry(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 PAUSE 20 mS ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) Notes: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A15 = VIL. Manufacturer Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code is 1F. The Device Code is 3D. 24. Software Product Identification Exit(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 PAUSE 20 mS EXIT PRODUCT IDENTIFICATION MODE(4) 11 0177O–FLASH–9/08 25. Ordering Information 25.1 tACC (ns) 120 Green Package Option (Pb/Halide-free) ICC (mA) Active 15 Standby 0.05 Ordering Code AT29LV512-12JU AT29LV512-12TU Package 32J 32T Operation Range Industrial (-40° to 85° C) Package Type 32J 32T 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32-lead, Thin Small Outline Package (TSOP) 12 AT29LV512 0177O–FLASH–9/08 AT29LV512 26. Packaging Information 26.1 32J – PLCC 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.318(0.0125) 0.191(0.0075) E1 B E B1 E2 e D1 D A A2 A1 0.51(0.020)MAX 45˚ MAX (3X) COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D2 MIN 3.175 1.524 0.381 12.319 11.354 9.906 14.859 13.894 12.471 0.660 0.330 NOM – – – – – – – – – – – 1.270 TYP MAX 3.556 2.413 – 12.573 11.506 10.922 15.113 14.046 13.487 0.813 0.533 NOTE A A1 A2 D D1 D2 Note 2 Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. E E1 E2 B B1 e Note 2 10/04/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) DRAWING NO. 32J REV. B R 13 0177O–FLASH–9/08 26.2 32T – TSOP PIN 1 0º ~ 8º c Pin 1 Identifier D1 D L e b L1 E A2 A SEATING PLANE GAGE PLANE A1 SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.05 0.95 19.80 18.30 7.90 0.50 NOM – – 1.00 20.00 18.40 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 – 0.50 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 20.20 18.50 8.10 0.70 Note 2 Note 2 NOTE 10/18/01 2325 Orchard Parkway San Jose, CA 95131 TITLE 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 32T REV. B R 14 AT29LV512 0177O–FLASH–9/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support Flash@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. A tmel ®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 0177O–FLASH–9/08