AT32AP7002-CTUT

Features • High Performance, Low Power AVR®32 32-Bit Microcontroller – 210 DMIPS throughput at 150 MHz – 16 KB instruction cache and 16 KB data caches – Memory Management Unit enabling use of operating systems – Single-cycle RISC instruction set including SIMD and DSP instructions – Java Hardware Acceleration Pixel Co-Processor – Pixel Co-Processor for video acceleration through color-space conversion (YUVRGB), image scaling and filtering, quarter pixel motion compensation Multi-hierarchy bus system – High-performance data transfers on separate buses for increased performance Data Memories – 32KBytes SRAM External Memory Interface – SDRAM, DataFlash™, SRAM, Multi Media Card (MMC), Secure Digital (SD), – Compact Flash, Smart Media, NAND Flash Direct Memory Access Controller – External Memory access without CPU intervention Interrupt Controller – Individually maskable Interrupts – Each interrupt request has a programmable priority and autovector address System Functions – Power and Clock Manager – Crystal Oscillator with Phase-Lock-Loop (PLL) – Watchdog Timer – Real-time Clock 6 Multifunction timer/counters – Three external clock inputs, I/O pins, PWM, capture and various counting capabilities 4 Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – 115.2 kbps IrDA Modulation and Demodulation – Hardware and software handshaking 3 Synchronous Serial Protocol controllers – Supports I2S, SPI and generic frame-based protocols Two-Wire Interface – Sequential Read/Write Operations, Philips’ I2C© compatible Liquid Crystal Display (LCD) interface – Supports TFT displays – Configurable pixel resolution supporting QCIF/QVGA/VGA/SVGA configurations. Image Sensor Interface – 12-bit Data Interface for CMOS cameras Universal Serial Bus (USB) 2.0 High Speed (480 Mbps) Device – On-chip Transceivers with physical interface 16-bit stereo audio bitstream DAC° – Sample rates up to 50 kHz On-Chip Debug System – Nexus Class 3 – Full speed, non-intrusive data and program trace – Runtime control and JTAG interface Package/Pins – AT32AP7002: 196-ball CTBGA Power supplies – 1.65V to1.95V VDDCORE – 3.0V to 3.6V VDDIO • • • • AVR®32 32-bit Microcontroller AT32AP7002 Preliminary • • • • • • • • • • • • • • 32054F-AVR32-09/09 AT32AP7002 1. Part Description The AT32AP7002 is a complete System-on-chip application processor with an AVR32 RISC processor achieving 210 DMIPS running 150 MHz. AVR32 is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high application performance. AT32AP7002 implements a Memory Management Unit (MMU) and a flexible interrupt controller supporting modern operating systems and real-time operating systems. The processor also includes a rich set of DSP and SIMD instructions, specially designed for multimedia and telecom applications. AT32AP7002 incorporates SRAM memories on-chip for fast and secure access. For applications requiring additional memory, external 16-bit SRAM is accessible. Additionally, an SDRAM controller provides off-chip volatile memory access as well as controllers for all industry standard off-chip non-volatile memories, like Compact Flash, Multi Media Card (MMC), Secure Digital (SD)-card, SmartCard, NAND Flash and Atmel DataFlash™. The Direct Memory Access controller for all the serial peripherals enables data transfer between memories without processor intervention. This reduces the processor overhead when transferring continuous and large data streams between modules in the MCU. The Timer/Counters includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. AT32AP7002 also features an onboard LCD Controller, supporting single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method. This method is also used in color STN displays to generate up to 4096 colors. The LCD Controller is programmable for supporting resolutions up to 2048 x 2048 with a pixel depth from 1 to 24 bits per pixel. A pixel co-processor provides color space conversions for images and video, in addition to a wide variety of hardware filter support The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC modules provides on-chip solutions for network-connected devices. Synchronous Serial Controllers provide easy access to serial communication protocols, audio standards like I2S and frame-based protocols. The Java hardware acceleration implementation in AVR32 allows for a very high-speed Java byte-code execution. AVR32 implements Java instructions in hardware, reusing the existing RISC data path, which allows for a near-zero hardware overhead and cost with a very high performance. The Image Sensor Interface supports cameras with up to 12-bit data buses. PS2 connectivity is provided for standard input devices like mice and keyboards. 2 32054F–AVR32–09/09 AT32AP7002 AT32AP7002 integrates a class 3 Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. The C-compiler is closely linked to the architecture and is able to utilize code optimization features, both for size and speed. 3 32054F–AVR32–09/09 AT32AP7002 2. Signals Description The following table gives details on the signal name classified by peripheral. The pinout multiplexing of these signals is given in the Peripheral Muxing table in the Peripherals chapter. Table 2-1. Signal Name Signal Description List Function Power Type Active Level Comments AVDDPLL AVDDUSB AVDDOSC VDDCORE VDDIO AGNDPLL AGNDUSB AGNDOSC GND PLL Power Supply USB Power Supply Oscillator Power Supply Core Power Supply I/O Power Supply PLL Ground USB Ground Oscillator Ground Ground Power Power Power Power Power Ground Ground Ground Ground Clocks, Oscillators, and PLL’s 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 1.65 to 1.95 V 3.0 to 3.6V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 PLL0, PLL1 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output PLL 0,1 Filter Pin JTAG Analog Analog Analog TCK TDI TDO TMS TRST_N Test Clock Test Data In Test Data Out Test Mode Select Test Reset Input Input Output Input Input Auxiliary Port - AUX Low MCKO MDO0 - MDO5 MSEO0 - MSEO1 EVTI_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Output Output Output Input Low 4 32054F–AVR32–09/09 AT32AP7002 Table 2-1. Signal Name EVTO_N Signal Description List Function Event Out Type Output Power Manager - PM Active Level Low Comments GCLK0 - GCLK4 OSCEN_N RESET_N WAKE_N Generic Clock Pins Oscillator Enable Reset Pin Wake Pin Output Input Input Input External Interrupt Controller - EIC Low Low Low EXTINT0 - EXTINT3 NMI_N External Interrupt Pins Non-Maskable Interrupt Pin Input Input AC97 Controller - AC97C Low SCLK SDI SDO SYNC AC97 Clock Signal AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal Input Output Output Input Audio Bitstream DAC - ABDAC DATA0 - DATA1 DATAN0 - DATAN1 D/A Data Out D/A Inverted Data Out Output Output External Bus Interface - EBI PX0 - PX53 ADDR0 - ADDR25 CAS CFCE1 CFCE2 CFRNW DATA0 - DATA31 NANDOE NANDWE NCS0 - NCS5 I/O Controlled by EBI Address Bus Column Signal Compact Flash 1 Chip Enable Compact Flash 2 Chip Enable Compact Flash Read Not Write Data Bus NAND Flash Output Enable NAND Flash Write Enable Chip Select I/O Output Output Output Output Output I/O Output Output Output Low Low Low Low Low Low 5 32054F–AVR32–09/09 AT32AP7002 Table 2-1. Signal Name NRD NWAIT NWE0 NWE1 NWE3 RAS SDA10 SDCK SDCKE SDWE Signal Description List Function Read Signal External Wait Signal Write Enable 0 Write Enable 1 Write Enable 3 Row Signal SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Write Enable Type Output Input Output Output Output Output Output Output Output Output Image Sensor Interface - ISI Low Active Level Low Low Low Low Low Low Comments DATA0 - DATA11 HSYNC PCLK VSYNC Image Sensor Data Horizontal Synchronization Image Sensor Data Clock Vertical Synchronization Input Input Input Input LCD Controller - LCDC CC DATA0 - DATA23 DVAL GPL0 - GPL7 HSYNC MODE PCLK PWR VSYNC LCD Contrast Control LCD Data Bus LCD Data Valid LCD General Purpose Lines LCD Horizontal Synchronization LCD Mode LCD Clock LCD Power LCD Vertical Synchronization Output Input Output Output Output Output Output Output Output MultiMedia Card Interface - MCI CLK CMD0 - CMD1 Multimedia Card Clock Multimedia Card Command Output I/O 6 32054F–AVR32–09/09 AT32AP7002 Table 2-1. Signal Name DATA0 - DATA7 Signal Description List Function Multimedia Card Data Type I/O Active Level Comments Parallel Input/Output - PIOA, PIOB, PIOC, PIOD PA0 - PA31 PB0 - PB30 PC20 - PC23/ PC28 - PC31 PD0 - PD17 Parallel I/O Controller PIOA Parallel I/O Controller PIOB Parallel I/O Controller PIOC Parallel I/O Controller PIOD PS2 Interface - PSIF CLOCK0 - CLOCK1 DATA0 - DATA1 PS2 Clock PS2 Data Input I/O Serial Peripheral Interface - SPI0, SPI1 MISO MOSI NPCS0 - NPCS3 SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC0, SSC1, SSC2 RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O DMA Controller - DMACA DMARQ0 - DMARQ3 DMA Requests Input Timer/Counter - TIMER0, TIMER1 A0 A1 A2 B0 Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B I/O I/O I/O I/O Low I/O I/O I/O I/O 7 32054F–AVR32–09/09 AT32AP7002 Table 2-1. Signal Name B1 B2 CLK0 CLK1 CLK2 Signal Description List Function Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input Type I/O I/O Input Input Input Active Level Comments Two-wire Interface - TWI SCL SDA Serial Clock Serial Data I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS RTS RXD TXD Clock Clear To Send Request To Send Receive Data Transmit Data I/O Input Output Input Output Pulse Width Modulator - PWM PWM0 - PWM3 PWM Output Pins Output USB Interface - USBA HSDM FSDM HSDP FSDP High Speed USB Interface Data Full Speed USB Interface Data High Speed USB Interface Data + Full Speed USB Interface Data + Analog Analog Analog Analog Connected to a 6810 Ohm ± 0.5% resistor to gound and a 10 pF capacitor to ground. VBG USB bandgap Analog 8 32054F–AVR32–09/09 AT32AP7002 3. Power Considerations 3.1 Power Supplies The AT32AP7002 has several types of power supply pins: • • • • • VDDCORE pins: Power the core, memories, and peripherals. Voltage is 1.8V nominal. VDDIO pins: Power I/O lines. Voltage is 3.3V nominal. VDDPLL pin: Powers the PLL. Voltage is 1.8V nominal. VDDUSB pin: Powers the USB. Voltage is 1.8V nominal. VDDOSC pin: Powers the oscillators. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDPLL is GNDPLL, and the GND pin for VDDOSC is GNDOSC. See ”Electrical Characteristics” on page 862 for power consumption on the various supply pins. 3.2 Power Supply Connections Special considerations should be made when connecting the power and ground pins on a PCB. Figure 3-1 shows how this should be done. Figure 3-1. Connecting analog power supplies C54 0.10u AVDDUSB AVDDPLL AVDDOSC AGNDUSB AGNDPLL AGNDOSC C56 0.10u C55 0.10u 3.3uH VDDCORE VCC_1V8 9 32054F–AVR32–09/09 AT32AP7002 3.3 Package and PinoutAVR32AP7002 196 CTBGA Pinout Figure 3-2. TOP VIEW Ball A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A B C D E F G H J K L M N P BOTTOM VIEW 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P AVR32 Table 3-1. 1 A PX49 B PX50 C PX51 D PX32 E PX33 F PX01 G PD05 H TMS J PA01 K PA05 L PB25 M PA13 N PA15 P PA17 CTBGA196 Package Pinout A1..T8 2 PX48 GND PD01 PD00 PX00 PX03 PD08 TRST_N PA03 PA11 PA21 PA22 PA20 PA24 3 PX47 VDDIO PX05 VDDIO PX04 VDDCORE PD06 TCK PA00 PA12 PA19 PA23 PD12 PD13 4 AVDDPLL PLL0 GND PX02 GND PD04 TDO EVTI_N VDDIO PA16 GND PD17 PD15 PD14 5 PC28 PLL1 AGNDPLL XIN0 PD07 PD09 PA04 PB24 GND GND VDDIO AVDDUSB PD16 XIN1 6 PC23 XIN32 XOUT32 XOUT0 AVDDOSC TDI PA02 PA10 PA09 GND VDDIO VDDCORE AGNDUSB XOUT1 7 PC20 PC22 PC29 AGNDOSC OSCEN_N RESET_N PA08 PA14 PA18 PA26 PA25 VBG FSDP FSDM 8 PB22 PB23 PC21 PC30 PC31 VDDCORE PX22 PX38 GND WAKE_N PA29 PA30 HSDP HSDM 10 32054F–AVR32–09/09 AT32AP7002 Table 3-2. 9 A B C D E F G H J K L M N P PB18 PB21 PA06 VDDIO PA07 PX42 PX30 PA28 PB27 PB28 PX41 PX53 PB26 PA27 CTBGA196 Package Pinout A9..T16 10 PB16 PB17 PB19 PB20 GND GND PX25 PX20 PX37 PX15 GND PX06 VDDIO PA31 11 PB11 PB12 PB14 PB15 PB00 GND PX31 PX28 PX23 PX36 PX07 PX11 PX09 PX52 12 PB08 PB09 PB10 PB13 PX44 PX43 VDDIO PX29 PX27 PX19 VDDIO PX12 PB29 PX08 13 PB05 PB06 PB07 GND VDDIO PX46 VDDCORE VDDCORE PX21 PX34 GND PX17 PX16 PX10 14 PB04 PB03 PB02 PB01 PX45 PX40 PX39 PX26 PX24 PX18 PX35 PX14 PX13 PB30 11 32054F–AVR32–09/09 AT32AP7002 4. Blockdiagram Figure 4-1. Blockdiagram TRST_N TCK TDO TDI TMS JTAG INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N NEXUS CLASS 3 OCD AP CPU MEMORY MANAGEMENT UNIT PIXEL COPROCESSOR INSTR CACHE PBB DATA CACHE D+ D- USB INTERFACE DMA DATA[11..0] HSYNC VSYNC PCLK LCD CONTRO LLER S M DMA IMAGE SENSOR INTERFACE INTRAM0 INTRAM1 S M M M M M VSYNC, HSYNC, PWR, PCLK, MODE, DVAL, CC, DATA[22..0], GPL[7..0] RAS, CAS, SDWE, NANDOE, NANDWE, SDCK, SDCKE, NWE3, NWE1, NWE0, NRD, NCS[3,1,0], ADDR[22..0] DATA[15..0] NWAIT NCS[5,4,2] CFRNW, CFCE1, CFCE2, ADDR[23..25] DATA[31..16] HIGH SPEED BUS MATRIX S S MM S CONFIGURATION PB HS B HSB S REGISTERS BUS M HSB-PB BRIDGE B HSB-PB BRIDGE A PB PBA HSB-HSB BRIDGE PERIPHERAL DMA CONTROLLER Parallel Input/Output Controllers DMA CONTROLLER PA PB PC PD PE DATA0N DATA1N CLK CMD DATA[7..0] SCLK SDI SSYNC SDO DMA DATA0 DATA1 Parallel Input/Output Controllers AUDIO BITSTREAM DAC MULTIMEDIA CARD INTERFACE USART0 USART1 USART2 USART3 SERIAL PERIPHERAL INTERFACE 0/1 SYNCHRONOUS SERIAL CONTROLLER 0/1/2 EXTERNAL BUS INTERFACE (SDRAM & STATIC MEMORY CONTROLLER & ECC) S RXD TXD CLK RTS, CTS SCK MISO, MOSI NPCS0 NPCS[3..1] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA PA PB PC PD PE POWER MANAGER XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 PLL0 PLL1 PDC AC97 CONTROLLER DMA DMA PDC PDC 32 KHz OSC OSC0 OSC1 PLL0 PLL1 GCLK[3..0] OSCEN_N RESET_N A[2..0] B[2..0] CLK[2..0] TWO-WIRE INTERFACE SCL SDA CLOCK GENERATOR CLOCK[1..0] CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER PS2 INTERFACE DATA[1..0] REAL TIME COUNTER WATCHDOG TIMER INTERRUPT CONTROLLER PULSE WIDTH MODULATION CONTROLLER PWM0 PWM1 PWM2 PWM3 TIMER/COUNTER 0/1 EXTINT[7..0] KPS[7..0] NMI_N EXTERNAL INTERRUPT CONTROLLER 12 32054F–AVR32–09/09 AT32AP7002 4.0.1 AVR32AP CPU • 32-bit load/store AVR32B RISC architecture. Up to 15 general-purpose 32-bit registers. 32-bit Stack Pointer, Program Counter and Link Register reside in register file. Fully orthogonal instruction set. Privileged and unprivileged modes enabling efficient and secure Operating Systems. Innovative instruction set together with variable instruction length ensuring industry leading code density. – DSP extention with saturating arithmetic, and a wide variety of multiply instructions. – SIMD extention for media applications. 7 stage pipeline allows one instruction per clock cycle for most instructions. – Java Hardware Acceleration. – Byte, half-word, word and double word memory access. – Unaligned memory access. – Shadowed interrupt context for INT3 and multiple interrupt priority levels. – Dynamic branch prediction and return address stack for fast change-of-flow. – Coprocessor interface. Full MMU allows for operating systems with memory protection. 16Kbyte Instruction and 16Kbyte data caches. – Virtually indexed, physically tagged. – 4-way associative. – Write-through or write-back. Nexus Class 3 On-Chip Debug system. – Low-cost NanoTrace supported. – – – – – • • • • 4.0.2 Pixel Coprocessor (PICO) • Coprocessor coupled to the AVR32 CPU Core through the TCB Bus. • – Coprocessor number one on the TCB bus. Three parallel Vector Multiplication Units (VMU) where each unit can: – Multiply three pixel components with three coefficients. – Add the products from the multiplications together. – Accumulate the result or add an offset to the sum of the products. Can be used for accelerating: – Image Color Space Conversion. • Configurable Conversion Coefficients. • Supports packed and planar input and output formats. • Supports subsampled input color spaces (i.e 4:2:2, 4:2:0). – Image filtering/scaling. • Configurable Filter Coefficients. • Throughput of one sample per cycle for a 9-tap FIR filter. • Can use the built-in accumulator to extend the FIR filter to more than 9-taps. • Can be used for bilinear/bicubic interpolations. – MPEG-4/H.264 Quarter Pixel Motion Compensation. Flexible input Pixel Selector. – Can operate on numerous different image storage formats. Flexible Output Pixel Inserter. – Scales and saturates the results back to 8-bit pixel values. – Supports packed and planar output formats. • • • 13 32054F–AVR32–09/09 AT32AP7002 • Configurable coefficients with flexible fixed-point representation. 4.0.3 Debug and Test system • • • • • • • IEEE1149.1 compliant JTAG and boundary scan Direct memory access and programming capabilities through JTAG interface Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 3 Auxiliary port for high-speed trace information Hardware support for 6 Program and 2 data breakpoints Unlimited number of software breakpoints supported Advanced Program, Data, Ownership, and Watchpoint trace supported 4.0.4 DMA Controller • 2 HSB Master Interfaces • 3 Channels • Software and Hardware Handshaking Interfaces – 11 Hardware Handshaking Interfaces • Memory/Non-Memory Peripherals to Memory/Non-Memory Peripherals Transfer • Single-block DMA Transfer • Multi-block DMA Transfer – Linked Lists – Auto-Reloading – Contiguous Blocks • DMA Controller is Always the Flow Controller • Additional Features – Scatter and Gather Operations – Channel Locking – Bus Locking – FIFO Mode – Pseudo Fly-by Operation 4.0.5 Peripheral DMA Controller • Transfers from/to peripheral to/from any memory space without intervention of the processor. • Next Pointer Support, forbids strong real-time constraints on buffer management. • Eighteen channels – Two for each USART – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface 4.0.6 Bus system • HSB bus matrix with 10 Masters and 8 Slaves handled – Handles Requests from the CPU Icache, CPU Dcache, HSB bridge, HISI, USB 2.0 Controller, LCD Controller, DMA Controller 0, DMA Controller 1, and to internal SRAM 0, internal SRAM 1, PB A, PB B, EBI and, USB. 14 32054F–AVR32–09/09 AT32AP7002 – Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) – Burst Breaking with Slot Cycle Limit – One Address Decoder Provided per Master • 2 Peripheral buses allowing each bus to run on different bus speeds. – PB A intended to run on low clock speeds, with peripherals connected to the PDC. – PB B intended to run on higher clock speeds, with peripherals connected to the DMACA. • HSB-HSB Bridge providing a low-speed HSB bus running at the same speed as PBA – Allows PDC transfers between a low-speed PB bus and a bus matrix of higher clock speeds An overview of the bus system is given in Figure 4-1 on page 12. All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the HSB bus, and which DMA controller is connected to which peripheral. 15 32054F–AVR32–09/09 AT32AP7002 5. I/O Line Considerations 5.1 JTAG pins The TMS, TDI and TCK pins have pull-up resistors. TDO is an output, driven at up to VDDIO, and have no pull-up resistor. The TRST_N pin is used to initialize the embedded JTAG TAP Controller when asserted at a low level. It is a schmitt input and integrates permanent pull-up resistor to VDDIO, so that it can be left unconnected for normal operations. 5.2 WAKE_N pin The WAKE_N pin is a schmitt trigger input integrating a permanent pull-up resistor to VDDIO. 5.3 RESET_N pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 5.4 EVTI_N pin The EVTI_N pin is a schmitt input and integrates a non-programmable pull-up resistor to VDDIO. 5.5 TWI pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as PIO pins. 5.6 PIO pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, I/O lines default as inputs with pull-up resistors enabled, except when indicated otherwise in the column “Reset State” of the PIO Controller multiplexing tables. 16 32054F–AVR32–09/09 AT32AP7002 6. AVR32 AP CPU Rev.: 1.0.0.0 This chapter gives an overview of the AVR32 AP CPU. AVR32 AP is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, caches and MMU is presented. For further details, see the AVR32 Architecture Manual and the AVR32 AP Technical Reference Manual. 6.1 AVR32 Architecture AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for costsensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and half-word data types without penalty in code size and performance. Memory load and store operations are provided for byte, half-word, word and double word data with automatic sign- or zero extension of half-word and byte data. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 6.2 The AVR32 AP CPU AVR32 AP targets high-performance applications, and provides an advanced OCD system, efficient data and instruction caches, and a full MMU. Figure 6-1 on page 18 displays the contents of AVR32 AP. 17 32054F–AVR32–09/09 AT32AP7002 Figure 6-1. Overview of the AVR32 AP CPU Interrupt controller interface Reset interface JTAG interface OCD interface OCD system JTAG control Reset control Tightly Coupled Bus AVR32 CPU pipeline with Java accelerator BTB RAM interface MMU 8-entry uTLB Cache RAM interface 4-entry uTLB 32-entry TLB Dcache controller HSB master High Speed Bus Icache controller HSB master High Speed Bus Cache RAM interface 6.2.1 Pipeline Overview AVR32 AP is a pipelined processor with seven pipeline stages. The pipeline has three subpipes, namely the Multiply pipe, the Execute pipe and the Data pipe. These pipelines may execute different instructions in parallel. Instructions are issued in order, but may complete out of order (OOO) since the subpipes may be stalled individually, and certain operations may use a subpipe for several clock cycles. Figure 6-2 on page 19 shows an overview of the AVR32 AP pipeline stages. 18 32054F–AVR32–09/09 AT32AP7002 Figure 6-2. The AVR32 AP Pipeline M1 M2 Multiply pipe IF1 IF2 ID IS A1 A2 WB ALU pipe Prefetch unit Decode unit DA D Load-store pipe .The follwing abbreviations are used in the figure: •IF1, IF2 - Instruction Fetch stage 1 and 2 •ID - Instruction Decode •IS - Instruction Issue •A1, A2 - ALU stage 1 and 2 •M1, M2 - Multiply stage 1 and 2 •DA - Data Address calculation stage •D - Data cache access •WB - Writeback 6.2.2 AVR32B Microarchitecture Compliance AVR32 AP implements an AVR32B microarchitecture. The AVR32B microarchitecture is targeted at applications where interrupt latency is important. The AVR32B therefore implements dedicated registers to hold the status register and return address for interrupts, exceptions and supervisor calls. This information does not need to be written to the stack, and latency is therefore reduced. Additionally, AVR32B allows hardware shadowing of the registers in the register file. The scall, rete and rets instructions use the dedicated return status registers and return address registers in their operation. No stack accesses are performed by these instructions. 6.2.3 Java Support AVR32 AP provides Java hardware acceleration in the form of a Java Virtual Machine hardware implementation. Refer to the AVR32 Java Technical Reference Manual for details. 6.2.4 Memory management AVR32 AP implements a full MMU as specified by the AVR32 architecture. The page sizes provided are 1K, 4K, 64K and 1M. A 32-entry fully-associative common TLB is implemented, as well as a 4-entry micro-ITLB and 8-entry micro-DTLB. Instruction and data accesses perform lookups in the micro-TLBs. If the access misses in the micro-TLBs, an access in the common TLB is performed. If this access misses, a page miss exception is issued. 19 32054F–AVR32–09/09 AT32AP7002 6.2.5 Caches and write buffer AVR32 AP implements 16K data and 16K instruction caches. The caches are 4-way set associative. Each cache has a 32-bit System Bus master interface connecting it to the bus. The instruction cache has a 32-bit interface to the fetch pipeline stage, and the data cache has a 64bit interface to the load-store pipeline. The caches use a least recently used allocate-on-readmiss replacement policy. The caches are virtually tagged, physically indexed, avoiding the need to flush them on task switch. The caches provide locking on a per-line basis, allowing code and data to be permanently locked in the caches for timing-critical code. The data cache also allows prefetching of data using the pref instruction. Accesses to the instruction and data caches are tagged as cacheable or uncacheable on a perpage basis by the MMU. Data cache writes are tagged as write-through or writeback on a perpage basis by the MMU. The data cache has a 32-byte combining write buffer, to avoid stalling the CPU when writing to external memory. Writes are tagged as bufferable or unbufferable on a per-page basis by the MMU. Bufferable writes to sequential addresses are placed in the buffer, allowing for example a sequence of byte writes from the CPU to be combined into word transfers on the bus. A sync instruction is provided to explicitly flush the write buffer. 6.2.6 Unaligned reference handling AVR32 AP has hardware support for performing unaligned memory accesses. This will reduce the memory footprint needed by some applications, as well as speed up other applications operating on unaligned data. AVR32 AP is able to perform certain word-sized load and store instructions of any alignment, and word-aligned st.d and ld.d. Any other unaligned memory access will cause an MMU address exception. All coprocessor memory access instructions require word-aligned pointers. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two wordsized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Accessing an unaligned address may require several clock cycles, refer to the AVR32 AP Technical Reference Manual for details. Table 6-1. Instruction ld.w st.w lddsp lddpc stdsp ld.d st.d All coprocessor memory access instruction Instructions with unaligned reference support Supported alignment Any Any Any Any Any Word Word Word 20 32054F–AVR32–09/09 AT32AP7002 6.2.7 Unimplemented instructions The following instructions are unimplemented in AVR32 AP, and will cause an Unimplemented Instruction Exception if executed: •mems •memc •memt 6.2.8 Exceptions and Interrupts AVR32 AP incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. Each priority class has dedicated registers to keep the return address and status register thereby removing the need to perform time-consuming memory operations to save this information. There are four levels of external interrupt requests, all executing in their own context. The INT3 context provides dedicated shadow registers ensuring low latency for these interrupts. An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU. The addresses and priority of simultaneous events are shown in Table 6-2 on page 22. 21 32054F–AVR32–09/09 AT32AP7002 Table 6-2. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Priority and handler addresses for events Handler Address 0xA000_0000 Provided by OCD system EVBA+0x00 EVBA+0x04 EVBA+0x08 EVBA+0x0C EVBA+0x10 Autovectored Autovectored Autovectored Autovectored EVBA+0x14 EVBA+0x50 EVBA+0x18 EVBA+0x1C EVBA+0x20 EVBA+0x24 EVBA+0x28 EVBA+0x2C EVBA+0x30 EVBA+0x100 EVBA+0x34 EVBA+0x38 EVBA+0x60 EVBA+0x70 EVBA+0x3C EVBA+0x40 EVBA+0x44 Name Reset OCD Stop CPU Unrecoverable exception TLB multiple hit Bus error data fetch Bus error instruction fetch NMI Interrupt 3 request Interrupt 2 request Interrupt 1 request Interrupt 0 request Instruction Address ITLB Miss ITLB Protection Breakpoint Illegal Opcode Unimplemented instruction Privilege violation Floating-point Coprocessor absent Supervisor call Data Address (Read) Data Address (Write) DTLB Miss (Read) DTLB Miss (Write) DTLB Protection (Read) DTLB Protection (Write) DTLB Modified Event source External input OCD system Internal Internal signal Data bus Data bus External input External input External input External input External input ITLB ITLB ITLB OCD system Instruction Instruction Instruction FP Hardware Instruction Instruction DTLB DTLB DTLB DTLB DTLB DTLB DTLB Stored Return Address Undefined First non-completed instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC(Supervisor Call) +2 PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction 22 32054F–AVR32–09/09 AT32AP7002 6.3 6.3.1 Programming Model Register file configuration The AVR32B architecture specifies that the exception contexts may have a different number of shadowed registers in different implementations. Figure 6-3 on page 23 shows the model used in AVR32 AP. Figure 6-3. Application Bit 31 Bit 0 The AVR32 AP Register File Supervisor Bit 31 Bit 0 INT0 Bit 31 Bit 0 INT1 Bit 31 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Exception Bit 31 Bit 0 NMI Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_SUP RAR_SUP PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_INT0 RAR_INT0 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_INT1 RAR_INT1 PC LR SP_SYS R12 R11 R10 R9 R8 R7 R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_INT2 RAR_INT2 PC LR_INT3 SP_SYS R12_INT3 R11_INT3 R10_INT3 R9_INT3 R8_INT3 R7 R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_INT3 RAR_INT3 PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_EX RAR_EX PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR RSR_NMI RAR_NMI 6.3.2 Status register configuration The Status Register (SR) is splitted into two halfwords, one upper and one lower, see Figure 6-4 on page 23 and Figure 6-5 on page 24. The lower word contains the C, Z, N, V and Q condition code flags and the R, T and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 6-4. Bit 31 The Status Register High Halfword Bit 16 - LC 1 0 H J DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM Bit name Initial value Global Interrupt Mask Interrupt Level 0 Mask Interrupt Level 1 Mask Interrupt Level 2 Mask Interrupt Level 3 Mask Exception Mask Mode Bit 0 Mode Bit 1 Mode Bit 2 Reserved Debug State Debug State Mask Java State Java Handle Reserved Reserved 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 23 32054F–AVR32–09/09 AT32AP7002 Figure 6-5. Bit 15 The Status Register Low Halfword Bit 0 R 0 T 0 0 0 0 0 0 0 0 0 L 0 Q 0 V 0 N 0 Z 0 C 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Register Remap Enable 6.3.3 6.3.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 6-3 on page 24. Table 6-3. Priority 1 2 3 4 5 6 N/A N/A Overview of execution modes, their priorities and privilege levels. Mode Non Maskable Interrupt Exception Interrupt 3 Interrupt 2 Interrupt 1 Interrupt 0 Supervisor Application Security Privileged Privileged Privileged Privileged Privileged Privileged Privileged Unprivileged Description Non Maskable high priority interrupt mode Execute exceptions General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode Runs supervisor calls Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 6.3.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. 24 32054F–AVR32–09/09 AT32AP7002 All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32 AP Technical Reference Manual. Debug state is exited by the retd instruction. 6.3.3.3 Java State AVR32 AP implements a Java Extension Module (JEM). The processor can be set in a Java State where normal RISC operations are suspended. Refer to the AVR32 Java Technical Reference Manual for details. 25 32054F–AVR32–09/09 AT32AP7002 7. Pixel Coprocessor (PICO) Rev.: 1.0.0.0 7.1 Features • Coprocessor coupled to the AVR32 CPU Core through the TCB Bus. • Three parallel Vector Multiplication Units (VMU) where each unit can: – Multiply three pixel components with three coefficients. – Add the products from the multiplications together. – Accumulate the result or add an offset to the sum of the products. Can be used for accelerating: – Image Color Space Conversion. • Configurable Conversion Coefficients. • Supports packed and planar input and output formats. • Supports subsampled input color spaces (i.e 4:2:2, 4:2:0). – Image filtering/scaling. • Configurable Filter Coefficients. • Throughput of one sample per cycle for a 9-tap FIR filter. • Can use the built-in accumulator to extend the FIR filter to more than 9-taps. • Can be used for bilinear/bicubic interpolations. – MPEG-4/H.264 Quarter Pixel Motion Compensation. Flexible input Pixel Selector. – Can operate on numerous different image storage formats. Flexible Output Pixel Inserter. – Scales and saturates the results back to 8-bit pixel values. – Supports packed and planar output formats. Configurable coefficients with flexible fixed-point representation. • • • • 7.2 Description The Pixel Coprocessor (PICO) is a coprocessor coupled to the AVR32 CPU through the TCB (Tightly Coupled Bus) interface. The PICO consists of three Vector Multiplication Units (VMU0, VMU1, VMU2), an Input Pixel Selector and an Output Pixel Inserter. Each VMU can perform a vector multiplication of a 1x3 12-bit coefficient vector with a 3x1 8-bit pixel vector. In addition a 12-bit offset can be added to the result of this vector multiplication. The PICO can be used for transforming the pixel components in a given color space (i.e. RGB, YCrCb, YUV) to any other color space as long as the transformation is linear. The flexibility of the Input Pixel Selector and Output Pixel Insertion logic makes it easy to efficiently support different pixel storage formats with regards to issues such as byte ordering of the color components, if the color components constituting an image are packed/interleaved or stored as separate images or if any of the color components are subsampled. The three Vector Multiplication Units can also be connected together to form one large vector multiplier which can perform a vector multiplication of a 1x9 12-bit coefficient vector with a 9x1 8bit pixel vector. This can be used to implement FIR filters, bilinear interpolations filters for smoothing/scaling images etc. By allowing the outputs from the Vector Multiplication units to accumulate it is also possible to extend the order of the filter to more than 9-taps. The results from the VMUs are scaled and saturated back to unsigned 8-bit pixel values in the Output Pixel Inserter. 26 32054F–AVR32–09/09 AT32AP7002 The PICO is divided into three pipeline stages with a throughput of one operation per cpu clock cycle. 7.3 Block Diagram Pixel Coprocessor Block Diagram INPIX0 INPIX1 INPIX2 Figure 7-1. Pipeline Stage 1 Input Pixel Selector VMU0_IN0 VMU0_IN1 VMU0_IN2 VMU1_IN0 VMU1_IN1 VMU1_IN2 VMU2_IN0 VMU2_IN1 VMU2_IN2 COEFF0_0 COEFF0_1 COEFF0_2 VMU0 COEFF1_0 COEFF1_1 COEFF1_2 VMU1 COEFF2_0 COEFF2_1 COEFF2_2 VMU2 OFFSET0 VMU0_OUT OFFSET1 VMU1_OUT OFFSET2 VMU2_OUT Pipeline Stage 2 ADD Output Pixel Inserter Pipeline Stage 3 OUTPIX0 OUTPIX1 OUTPIX2 27 32054F–AVR32–09/09 AT32AP7002 7.4 Vector Multiplication Unit (VMU) Each VMU consists of three multipliers used for multiplying unsigned 8-bit pixel components with signed 12-bit coefficients.The result from each multiplication is a 20-bit signed number that is input to a 22-bit vector adder along with an offset as shown in Figure 7-2 on page 28. The operation is equal to the offsetted vector multiplication given in the following equation: vmu_in0 vmu_out = coeff0 coeff1 coeff2 vmu_in1 + offset vmu_in2 Figure 7-2. Inside VMUn (n ∈ {0,1,2}) coeffn_0 vmun_in0 coeffn_1 vmun_in1 coeffn_2 vmun_in2 Multiply Multiply Multiply offsetn Vector Adder VMUn vmun_out 7.5 Input Pixel Selector The Input Pixel Selector uses the ISM (Input Selection Mode) field in the CONFIG register and the three input pixel source addresses given in the PICO operation instructions to decide which pixels to select for inputs to the VMUs. 7.5.1 Transformation Mode When the Input Selection Mode is set to Transformation Mode the input pixel source addresses INx, INy and INz directly maps to three pixels in the INPIXn registers. These three pixels are then input to each of the VMUs. The following expression then represents what is computed by the VMUs in Transformation Mode: VMU0_OUT COEFF0_0 COEFF0_1 COEFF0_2 INx OFFSET0 or VMU0_OUT VMU1_OUT = COEFF1_0 COEFF1_1 COEFF1_2 INy + OFFSET1 or VMU1_OUT VMU2_OUT COEFF2_0 COEFF2_1 COEFF2_2 INz OFFSET2 or VMU2_OUT 7.5.2 Horizontal Filter Mode In Horizontal Filter Mode the input pixel source addresses INx, INy and INz represents the base pixel address of a pixel triplet. The pixel triplet {IN(x), IN(x+1), IN(x+2)} is input to VMU0, the pixel triplet {IN(y), IN(y+1), IN(y+2)} is input to VMU1 and the pixel triplet {IN(z), IN(z+1), IN(z+2)} 28 32054F–AVR32–09/09 AT32AP7002 is input to VMU2. Figure 7-3 on page 29 shows how the pixel triplet is found by taking the pixel addressed by the base address and following the arrow to find the next two pixels which makes up the triplet. Figure 7-3. Horizontal Filter Mode Pixel Addressing INPIX0 INPIX1 INPIX2 IN0 IN4 IN8 IN1 IN5 IN9 IN2 IN6 IN10 IN3 IN7 IN11 The following expression represents what is computed by the VMUs in Horizontal Filter Mode: IN(x+0) VMU0_OUT = COEFF0_0 COEFF0_1 COEFF0_2 IN(x+1) + ( OFFSET0 or VMU0_OUT ) IN(x+2) IN(y+0) VMU1_OUT = COEFF1_0 COEFF1_1 COEFF1_2 IN(y+1) + ( OFFSET1 or VMU1_OUT ) IN(y+2) IN(z+0) VMU2_OUT = COEFF2_0 COEFF2_1 COEFF2_2 IN(z+1) + ( OFFSET2 or VMU2_OUT ) IN(z+2) 7.5.3 Vertical Filter Mode In Vertical Filter Mode the input pixel source addresses INx, INy and INz represent the base of a pixel triplet found by following the vertical arrow shown in Figure 7-4 on page 29. The pixel triplet {IN(x), IN((x+4)%11), IN((x+8)%11)} is input to VMU0, the pixel triplet {IN(y), IN((y+4)%11), IN((y+8)%11)} is input to VMU1 and the pixel triplet {IN(z), IN((z+4)%11), IN((z+8)%11)} is input to VMU2. Figure 7-4. Vertical Filter Mode Pixel Addressing INPIX0 INPIX1 INPIX2 IN0 IN4 IN8 IN1 IN5 IN9 IN2 IN6 IN10 IN3 IN7 IN11 29 32054F–AVR32–09/09 AT32AP7002 The following expression represents what is computed by the VMUs in Vertical Filter Mode: IN((x+0)%11) VMU0_OUT = COEFF0_0 COEFF0_1 COEFF0_2 IN((x+4)%11) + ( OFFSET0 or VMU0_OUT ) IN((x+8)%11) IN((y+0)%11) VMU1_OUT = COEFF1_0 COEFF1_1 COEFF1_2 IN((y+4)%11) + ( OFFSET1 or VMU1_OUT ) IN((y+8)%11) IN((z+0)%11) VMU2_OUT = COEFF2_0 COEFF2_1 COEFF2_2 IN((z+4)%11) + ( OFFSET2 or VMU2_OUT ) IN((z+8)%11) 7.6 Output Pixel Inserter The Output Pixel Inserter uses the OIM (Output Insertion Mode) field in the CONFIG register and the destination pixel address given in the PICO operation instructions to decide which three of the twelve possible OUTn pixels to write back the scaled and saturated results from the VMUs to. The 22-bit results from each VMU is first scaled by performing an arithmetical right shift by COEFF_FRAC_BITS in order to remove the fractional part of the results and obtain the integer part. The integer part is then saturated to an unsigned 8-bit number in the range 0 to 255. 7.6.1 Planar Insertion Mode In Planar Insertion Mode the destination pixel address OUTd specifies which pixel in each of the registers OUTPIX0, OUTPIX1 and OUTPIX2 will be updated. VMUn writes to OUTPIXn. This can be seen in Figure 7-5 on page 30 and Table 7-2 on page 48. This mode is useful when transforming from one color space to another where the resulting color components should be stored in separate images. Figure 7-5. Planar Pixel Insertion = VMU0 = VMU1 = VMU2 OUTPIX0 OUTPIX1 OUTPIX2 OUT0 OUT4 OUT8 OUT1 OUT5 OUT9 OUT2 OUT6 OUT10 OUT3 OUT7 OUT11 d=0 d=1 d=2 d=3 30 32054F–AVR32–09/09 AT32AP7002 7.6.2 Packed Insertion Mode In Packed Insertion Mode the three output registers OUTPIX0, OUTPIX1 and OUTPIX2 are divided into four pixel triplets as seen in Figure 7-6 on page 31 and Table 7-2 on page 48. The destination pixel address is then the address of the pixel triplet. VMUn writes to pixel n of the pixel triplet.This mode is useful when transforming from one color space to another where the resulting color components should be packed together. Packed Pixel Insertion. Figure 7-6. = VMU0 = VMU1 = VMU2 OUTPIX0 OUTPIX1 OUTPIX2 OUT0 OUT1 OUT2 OUT3 OUT4 OUT5 OUT6 OUT7 OUT8 OUT9 OUT10 OUT11 d=0 d=1 d=2 d=3 31 32054F–AVR32–09/09 AT32AP7002 7.7 User Interface The PICO uses the TCB interface to communicate with the CPU and the user can read from or write to the PICO Register File by using the PICO load/store/move instructions which maps to generic coprocessor instructions. 7.7.1 Register File The PICO register file can be accessed from the CPU by using the picomv.x, picold.x, picost.x, picoldm and picostm instructions. Table 7-1. Cp Reg # cr0 cr1 cr2 cr3 cr4 cr5 cr6 cr7 cr8 cr9 cr10 cr11 cr12 cr13 cr14 cr15 PICO Register File Register Input Pixel Register 2 Input Pixel Register 1 Input Pixel Register 0 Output Pixel Register 2 Output Pixel Register 1 Output Pixel Register 0 Coefficient Register A for VMU0 Coefficient Register B for VMU0 Coefficient Register A for VMU1 Coefficient Register B for VMU1 Coefficient Register A for VMU2 Coefficient Register B for VMU2 Output from VMU0 Output from VMU1 Output from VMU2 PICO Configuration Register Name INPIX2 INPIX1 INPIX0 OUTPIX2 OUTPIX1 OUTPIX0 COEFF0_A COEFF0_B COEFF1_A COEFF1_B COEFF2_A COEFF2_B VMU0_OUT VMU1_OUT VMU2_OUT CONFIG Access Read/Write Read/Write Read/Write Read Only Read Only Read Only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 32 32054F–AVR32–09/09 AT32AP7002 7.7.1.1 Input Pixel Register 0 Register Name: INPIX0 Access Type: Read/Write 31 30 29 28 IN0 23 22 21 20 IN1 15 14 13 12 IN2 7 6 5 4 IN3 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 • IN0: Input Pixel 0 Input Pixel number 0 to the Input Pixel Selector Unit. • IN1: Input Pixel 1 Input Pixel number 1 to the Input Pixel Selector Unit. • IN2: Input Pixel 2 Input Pixel number 2 to the Input Pixel Selector Unit. • IN3: Input Pixel 3 Input Pixel number 3 to the Input Pixel Selector Unit. 33 32054F–AVR32–09/09 AT32AP7002 7.7.1.2 Input Pixel Register 1 Register Name: INPIX1 Access Type: Read/Write 31 30 29 28 IN4 23 22 21 20 IN5 15 14 13 12 IN6 7 6 5 4 IN7 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 • IN0: Input Pixel 4 Input Pixel number 4 to the Input Pixel Selector Unit. • IN1: Input Pixel 5 Input Pixel number 5 to the Input Pixel Selector Unit. • IN2: Input Pixel 6 Input Pixel number 6 to the Input Pixel Selector Unit. • IN3: Input Pixel 7 Input Pixel number 7 to the Input Pixel Selector Unit. 34 32054F–AVR32–09/09 AT32AP7002 7.7.1.3 Input Pixel Register 2 Register Name: INPIX2 Access Type: Read/Write 31 30 29 28 IN8 23 22 21 20 IN9 15 14 13 12 IN10 7 6 5 4 IN11 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 • IN0: Input Pixel 8 Input Pixel number 8 to the Input Pixel Selector Unit. • IN1: Input Pixel 9 Input Pixel number 9 to the Input Pixel Selector Unit. • IN2: Input Pixel 10 Input Pixel number 10 to the Input Pixel Selector Unit. • IN3: Input Pixel 11 Input Pixel number 11 to the Input Pixel Selector Unit. 35 32054F–AVR32–09/09 AT32AP7002 7.7.1.4 Output Pixel Register 0 Register Name: OUTPIX0 Access Type: Read 31 30 29 28 OUT0 23 22 21 20 OUT1 15 14 13 12 OUT2 7 6 5 4 OUT3 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 • OUT0: Output Pixel 0 Output Pixel number 0 from the Output Pixel Inserter Unit. • OUT1: Output Pixel 1 Output Pixel number 1 from the Output Pixel Inserter Unit. • OUT2: Output Pixel 2 Output Pixel number 2 from the Output Pixel Inserter Unit. • OUT3: Output Pixel 3 Output Pixel number 3 from the Output Pixel Inserter Unit. 36 32054F–AVR32–09/09 AT32AP7002 7.7.1.5 Output Pixel Register 1 Register Name: OUTPIX1 Access Type: Read 31 30 29 28 OUT4 23 22 21 20 OUT5 15 14 13 12 OUT6 7 6 5 4 OUT7 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 • OUT4: Output Pixel 4 Output Pixel number 4 from the Output Pixel Inserter Unit. • OUT5: Output Pixel 5 Output Pixel number 5 from the Output Pixel Inserter Unit. • OUT6: Output Pixel 6 Output Pixel number 6 from the Output Pixel Inserter Unit. • OUT7: Output Pixel 7 Output Pixel number 7 from the Output Pixel Inserter Unit. 37 32054F–AVR32–09/09 AT32AP7002 7.7.1.6 Output Pixel Register 2 Register Name: OUTPIX2 Access Type: Read 31 30 29 28 OUT8 23 22 21 20 OUT9 15 14 13 12 OUT10 7 6 5 4 OUT11 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 • OUT8: Output Pixel 8 Output Pixel number 8 from the Output Pixel Inserter Unit. • OUT9: Output Pixel 9 Output Pixel number 9 from the Output Pixel Inserter Unit. • OUT10: Output Pixel 10 Output Pixel number 10 from the Output Pixel Inserter Unit. • OUT11: Output Pixel 11 Output Pixel number 11 from the Output Pixel Inserter Unit. 38 32054F–AVR32–09/09 AT32AP7002 7.7.1.7 Coefficient Register A for VMU0 Register Name: COEFF0_A Access Type: Read/Write 31 23 30 22 29 21 28 20 COEFF0_0 15 7 14 6 13 5 12 4 COEFF0_1 11 10 COEFF0_1 3 2 1 0 9 8 27 26 COEFF0_0 19 18 17 16 25 24 • COEFF0_0: Coefficient 0 for VMU0 Coefficient 0 input to VMU0. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF0_0 ⁄ 2 , where the COEFF0_0 value is interpreted as a 2’s complement integer. When reading this register, COEFF0_0 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register. • COEFF0_1: Coefficient 1 for VMU0 Coefficient 1 input to VMU0. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF0_1 ⁄ 2 , where the COEFF0_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF0_1 is signextended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 39 32054F–AVR32–09/09 AT32AP7002 7.7.1.8 Coefficient Register B for VMU0 Register Name: COEFF0_B Access Type: Read/Write 31 23 30 22 29 21 28 20 COEFF0_2 15 7 14 6 13 5 12 4 OFFSET0 11 10 OFFSET0 3 2 1 0 9 8 27 26 COEFF0_2 19 18 17 16 25 24 • COEFF0_2: Coefficient 2 for VMU0 Coefficient 2 input to VMU0. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF0_2 ⁄ 2 , where the COEFF0_2 value is interpreted as a 2’s complement integer. When reading this register, COEFF0_2 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register. • OFFSET0: Offset for VMU0 Offset input to VMU0 in case of non-accumulating operations. A signed 12-bit fixed-point number where the number of fractional bits is given by the OFFSET_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to OFFSET_FRAC_BITS , where the OFFSET0 value is interpreted as a 2’s complement integer. When reading this regOFFSET0 ⁄ 2 ister, OFFSET0 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 40 32054F–AVR32–09/09 AT32AP7002 7.7.1.9 Coefficient Register A for VMU1 Register Name: COEFF1_A Access Type: Read/Write 31 23 30 22 29 21 28 20 COEFF1_0 15 7 14 6 13 5 12 4 COEFF1_1 11 10 COEFF1_1 3 2 1 0 9 8 27 26 COEFF1_0 19 18 17 16 25 24 • COEFF1_0: Coefficient 0 for VMU1 Coefficient 0 input to VMU1. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF1_0 ⁄ 2 , where the COEFF1_0 value is interpreted as a 2’s complement integer. When reading this register, COEFF1_0 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register. • COEFF1_1: Coefficient 1 for VMU1 Coefficient 1 input to VMU0. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF1_1 ⁄ 2 , where the COEFF1_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF1_1 is signextended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 41 32054F–AVR32–09/09 AT32AP7002 7.7.1.10 Coefficient Register B for VMU1 Register Name: COEFF1_B Access Type: Read/Write 31 23 30 22 29 21 28 20 COEFF1_2 15 7 14 6 13 5 12 4 OFFSET1 11 10 OFFSET1 3 2 1 0 9 8 27 26 COEFF1_2 19 18 17 16 25 24 • COEFF1_2: Coefficient 2 for VMU1 Coefficient 2 input to VMU1. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF1_2 ⁄ 2 , where the COEFF1_2 value is interpreted as a 2’s complement integer. When reading this register, COEFF1_2 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register. • OFFSET1: Offset for VMU1 Offset input to VMU1 in case of non-accumulating operations. A signed 12-bit fixed-point number where the number of fractional bits is given by the OFFSET_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to OFFSET_FRAC_BITS , where the OFFSET1 value is interpreted as a 2’s complement integer. When reading this regOFFSET1 ⁄ 2 ister, OFFSET1 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 42 32054F–AVR32–09/09 AT32AP7002 7.7.1.11 Coefficient Register A for VMU2 Register Name: COEFF2_A Access Type: Read/Write 31 23 30 22 29 21 28 20 COEFF2_0 15 7 14 6 13 5 12 4 COEFF2_1 11 10 COEFF2_1 3 2 1 0 9 8 27 26 COEFF2_0 19 18 17 16 25 24 • COEFF2_0: Coefficient 0 for VMU2 Coefficient 0 input to VMU2. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF2_0 ⁄ 2 , where the COEFF2_0 value is interpreted as a 2’s complement integer. When reading this register, COEFF2_0 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register. • COEFF2_1: Coefficient 1 for VMU2 Coefficient 1 input to VMU2. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF2_1 ⁄ 2 , where the COEFF2_1 value is interpreted as a 2’s complement integer. When reading this register, COEFF2_1 is signextended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 43 32054F–AVR32–09/09 AT32AP7002 7.7.1.12 Coefficient Register B for VMU2 Register Name: COEFF2_B Access Type: Read/Write 31 23 30 22 29 21 28 20 COEFF2_2 15 7 14 6 13 5 12 4 OFFSET2 11 10 OFFSET2 3 2 1 0 9 8 27 26 COEFF2_2 19 18 17 16 25 24 • COEFF2_2: Coefficient 2 for VMU2 Coefficient 2 input to VMU2. A signed 12-bit fixed-point number where the number of fractional bits is given by the COEFF_FRAC_BITS COEFF_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to COEFF2_2 ⁄ 2 , where the COEFF2_2 value is interpreted as a 2’s complement integer. When reading this register, COEFF2_2 is signextended to 16-bits in order to fill in the unused bits in the upper halfword of this register. • OFFSET2: Offset for VMU2 Offset input to VMU2 in case of non-accumulating operations. A signed 12-bit fixed-point number where the number of fractional bits is given by the OFFSET_FRAC_BITS field in the CONFIG register. The actual fractional number is equal to OFFSET_FRAC_BITS , where the OFFSET2 value is interpreted as a 2’s complement integer. When reading this regOFFSET2 ⁄ 2 ister, OFFSET2 is sign-extended to 16-bits in order to fill in the unused bits in the lower halfword of this register. 44 32054F–AVR32–09/09 AT32AP7002 7.7.1.13 VMU0 Output Register Register Name: VMU0_OUT Access Type: Read/Write 31 23 15 30 22 14 29 21 28 20 27 19 VMU0_OUT 13 12 VMU0_OUT 7 6 5 4 VMU0_OUT 3 2 1 0 11 10 9 8 26 18 25 17 24 16 • VMU0_OUT: Output from VMU0 This register is used for directly accessing the output from VMU0 or for setting the initial value of the accumulator for accumulating operations. The output from VMU0 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is signextended to 32-bits. 45 32054F–AVR32–09/09 AT32AP7002 7.7.1.14 VMU1 Output Register Register Name: VMU1_OUT Access Type: Read/Write 31 23 15 30 22 14 29 21 28 20 27 19 VMU1_OUT 13 12 VMU1_OUT 7 6 5 4 VMU1_OUT 3 2 1 0 11 10 9 8 26 18 25 17 24 16 • VMU1_OUT: Output from VMU1 This register is used for directly accessing the output from VMU1 or for setting the initial value of the accumulator for accumulating operations. The output from VMU1 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is signextended to 32-bits. 46 32054F–AVR32–09/09 AT32AP7002 7.7.1.15 VMU2 Output Register Register Name: VMU2_OUT Access Type: Read/Write 31 23 15 30 22 14 29 21 28 20 27 19 VMU2_OUT 13 12 VMU2_OUT 7 6 5 4 VMU2_OUT 3 2 1 0 11 10 9 8 26 18 25 17 24 16 • VMU2_OUT: Output from VMU2 This register is used for directly accessing the output from VMU2 or for setting the initial value of the accumulator for accumulating operations. The output from VMU2 is a signed 22-bit fixed-point number where the number of fractional bits are given by the COEFF_FRAC_BITS field in the CONFIG register. When reading this register the signed 22-bit value is signextended to 32-bits. 47 32054F–AVR32–09/09 AT32AP7002 7.7.1.16 PICO Configuration Register Register Name: CONFIG Access Type: Read/Write 31 23 15 7 30 22 14 29 21 13 28 20 12 4 27 19 11 3 26 18 10 OIM 25 17 9 ISM 0 24 16 8 6 5 OFFSET_FRAC_BITS 2 1 COEFF_FRAC_BITS • OIM: Output Insertion Mode The OIM bit specifies the semantics of the OUTd output pixel address parameter to the pico(s)v(mul/mac) instructions. The OIM together with the output pixel address parameter specify which of the 12 output bytes (OUTn) of the OUTPIXn registers will be updated with the results from the VMUs. Table 7-2 on page 48 describes the different Output Insertion Modes. See Section 7.6 ”Output Pixel Inserter” on page 30 for a description of the Output Pixel Inserter. Table 7-2. OIM Mode Output Insertion Modes Description {OUTPIX0, OUTPIX1, OUTPIX2} is treated as one large register containing 4 sequential 24bit pixel triplets. The DST_ADR field specifies which of the sequential triplets will be updated. 0 Packed Insertion Mode OUT(d*3 + 0) ← Scaled and saturated output from VMU0 OUT(d*3 + 1) ← Scaled and saturated output from VMU1 OUT(d*3 + 2) ← Scaled and saturated output from VMU2 Each of the OUTPIXn registers will get one of the resulting pixels. The triplet address specifies what byte in each of the OUTPIXn registers the results will be written to. 1 Planar Insertion Mode OUT(d + 0) ← Scaled and saturated output from VMU0 OUT(d+ 4) ← Scaled and saturated output from VMU1 OUT(d + 8) ← Scaled and saturated output from VMU2 • ISM: Input Selection Mode The ISM field specifies the semantics of the input pixel address parameters INx, INy and INz to the pico(s)v(mul/mac) instructions. Together with the three input pixel addresses the ISM field specifies to the Input Pixel Selector which of the input pixels (INn) that should be selected as inputs to the VMUs.Table 7-3 on page 49 describes the 48 32054F–AVR32–09/09 AT32AP7002 different Input Selection Modes. See Section 7.5 ”Input Pixel Selector” on page 28 for a description of the Input Pixel Table 7-3. ISM 0 0 1 1 0 1 0 1 Input Selection Modes Mode Transformation Mode Horizontal Filter Mode Vertical Filter Mode Reserved VMU0, VMU1 and VMU2 get the same pixel inputs. These three pixels can be freely selected from the INPIXn registers. Pixel triplets are selected for input to each of the VMUs by addressing horizontal pixel triplets from the INPIXn registers. Pixel triplets are selected for input to each of the VMUs by addressing vertical pixel triplets from the INPIXn registers. N.A Selector. • OFFSET_FRAC_BITS: Offset Fractional Bits Specifies the number of fractional bits in the fixed-point offsets input to each VMU. Must be in the range from 0 to COEFF_FRAC_BITS. Other values gives undefined results.This value is used for scaling the OFFSETn values before being input to VMUn so that the offset will have the same fixed-point format as the outputs from the multiplication stages before performing the vector addition in the VMU. • COEFF_FRAC_BITS: Coefficient Fractional Bits Specifies the number of fractional bits in the fixed-point coefficients input to each VMU. Must be in the range from 0 to 11, since at least one bit of the coefficient must be used for the sign. Other values gives undefined results. COEFF_FRAC_BITS is used in the Output Pixel Inserter to scale the fixed-point results from the VMUs back to unsigned 8bit integers. 49 32054F–AVR32–09/09 AT32AP7002 7.8 7.8.1 PICO Instructions PICO Instructions Nomenclature 7.8.1.1 Registers and Operands R{d, s, …} The uppercase ‘R’ denotes a 32-bit (word) register. Rd Rs Rb Ri Rp IN{x, y, z} INx INy INz OUTd OUTd Pr PrHi:PrLo The lowercase ‘d’ denotes the destination register number. The lowercase ‘s’ denotes the source register number. The lowercase ‘b’ denotes the base register number for indexed addressing modes. The lowercase ‘i’ denotes the index register number for indexed addressing modes. The lowercase ‘p’ denotes the pointer register number. The uppercase ‘IN’ denotes a pixel in the INPIXn registers. The lowercase ‘x’ denotes the first input pixel number for the PICO operation instructions. The lowercase ‘y’ denotes the second input pixel number for the PICO operation instructions. The lowercase ‘z’ denotes the third input pixel number for the PICO operation instructions. The uppercase ‘OUT’ denotes a pixel in the OUTPIXn registers. The lowercase ‘d’ denotes the destination pixel number for the PICO operation instructions. PICO register. See Section 7.7.1 ”Register File” on page 32 for a complete list of registers. PICO register pair. Only register pairs corresponding to valid coprocessor double registers are valid. E.g. INPIX1:INPIX2 (cr1:cr0). The low part must correspond to an even coprocessor register number n and the high part must then correspond to coprocessor register n+1. See Table 7-1 on page 32 for a mapping between PICO register names and coprocessor register numbers. Program Counter, equal to R15 Link Register, equal to R14 Stack Pointer, equal to R13 PC LR SP PICORegList disp sa [i] [i:j] Register List used in the picoldm and picostm instructions. See instruction description for which register combinations are allowed in the register list. Displacement Shift amount Denotes bit i in a immediate value. Example: imm6[4] denotes bit 4 in an 6-bit immediate value. Denotes bit i to j in an immediate value. Some instructions access or use doubleword operands. These operands must be placed in two consecutive register addresses where the first register must be an even register. The even register contains the least significant part and the odd register contains the most significant part. This ordering is reversed in comparison with how data is organized in memory (where the most significant part would receive the lowest address) and is intentional. 50 32054F–AVR32–09/09 AT32AP7002 The programmer is responsible for placing these operands in properly aligned register pairs. This is also specified in the "Operands" section in the detailed description of each instruction. Failure to do so will result in an undefined behavior. 7.8.1.2 Operations ASR(x, n) SE(x, Bits(x) + n) >> n SATSU(x, n) Signed to Unsigned Saturation ( x is treated as a signed value ): If (x > (2n-1)) then (2n-1-1); elseif ( x < 0 ) then 0; else x; SE(x, n) 7.8.1.3 .d .w Sign Extend x to an n-bit value Data Type Extensions Double (64-bit) operation. Word (32-bit) operation. 51 32054F–AVR32–09/09 AT32AP7002 7.8.2 PICO Instruction Summary Table 7-4. PICO instruction summary Operands / Syntax E E E E E picold.d E E E picold.w E E picoldm E E picomv.d E E picomv.w E E picost.d E E E picost.w E E picostm E Pr, Rd Rp[disp], PrHi:PrLo Rp++, PrHi:PrLo Rb[Ri