AT32UC3A3256S-CTUT

Features • High Performance, Low Power AVR®32 UC 32-Bit Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing 1.49DMIPS/MHz • Up to 91DMIPS Running at 66MHz from Flash (1 Wait-State) • Up to 54 DMIPS Running at 36MHz from Flash (0 Wait-State) – Memory Protection Unit Multi-Layer Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral Communication – 4 generic DMA Channels for High Bandwidth Data Paths Internal High-Speed Flash – 256KBytes, 128KBytes, 64KBytes versions – Single-Cycle Flash Access up to 36MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4 ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM – 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus – 64KBytes on the Multi-Layer Bus System Interrupt Controller – Autovectored Low Latency Interrupt Service with Programmable Priority System Functions – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator – Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), – Watchdog Timer, Real-Time Clock Timer External Memories – Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash – Up to 66 MHz External Storage device support – MultiMediaCard (MMC), Secure-Digital (SD), SDIO V1.1 – CE-ATA, FastSD, SmartMedia, Compact Flash – Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities Universal Serial Bus (USB) – High-Speed USB (480Mbit/s) Device/MiniHost with On-The-Go (OTG) – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-Chip Transceivers Including Pull-Ups One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Two Three-Channel 16-bit Timer/Counter (TC) Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independent Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces • • AVR®32 32-Bit Microcontroller AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 • • • Preliminary • • • • • • • 32072A–AVR32–03/09 AT32UC3A3 – Support for Hardware Handshaking, RS485 Interfaces and Modem Line • Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals • One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols • Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible • On-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace • 110 General Purpose Input/Output (GPIOs) – Standard or High Speed mode – Toggle capability: up to 66MHz • 144-pin TBGA and LQFP • Single 3.3V Power Supply 2 32072A–AVR32–03/09 AT32UC3A3 1. Description The AT32UC3A3 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions. The AT32UC3A3 incorporates on-chip Flash and SRAM memories for secure and fast access. The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between peripherals and memories without processor involvement. The PDCA drastically reduces processing overhead when transferring continuous and large data streams. The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high speed peripherals (USB, External Memories, MMC, SDIO, ...) and through high speed internal features (AES, internal memories). The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The Device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. 16-bit channels are combined to operate as 32-bit channels. The AT32UC3A3 also features many communication interfaces for communication intensive applications like UART, SPI or TWI. Additionally, a flexible Synchronous Serial Controller (SSC) and an USB are available. The SSC provides easy access to serial communication protocols and audio standards like I2S. The High-Speed (480 MBit/s) USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich Endpoint configuration. The On-The-Go (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. AT32UC3A3 integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. 3 32072A–AVR32–03/09 AT32UC3A3 2. Overview 2.1 Block Diagram Figure 2-1. Block Diagram MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N VBG VBUS DH+,DL+ DH-,DLID VBOF NEXUS CLASS 2+ OCD UC CPU MEMORY PROTECTION UNIT MEMORY INTERFACE TCK TDO TDI TMS JTAG INTERFACE LOCAL BUS INTERFACE FAST GPIO INSTR INTERFACE PBB DATA INTERFACE 64 KB SRAM FLASH CONTROLLER USB HS INTERFACE DMA S M M M M M S S 512/256/ 128/64 KB FLASH DMACA M S EXTERNAL BUS INTERFACE (SDRAM, STATIC MEMORY, COMPACT FLASH & NAND FLASH) HIGH SPEED BUS MATRIX DATA[15..0] ADDR[23..0] NCS[5..0] NRD NWAIT NWE0 NWE1 NWE3 RAS CAS SDA10 SDCK SDCKE SDCS1 SDWE CFCE1 CFCE2 CFRW NANDOE NANDWE AES GENERAL PURPOSE IOs 32KB RAM 3 2KB RAM DMA S S HRAM S S CONFIGURATION S REGISTERS BUS M PB HSB-PB BRIDGE B HS B HSB HSB-PB BRIDGE A PB PBA PERIPHERAL DMA CONTROLLER CLK CMD[1..0] PA PB PC PX DATA[15..0] DMA PDC USART1 GENERAL PURPOSE IOs MULTIMEDIA CARD & MEMORY STICK INTERFACE RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS EXTINT[7..0] KPS[7..0] NMI_N PDC EXTERNAL INTERRUPT CONTROLLER PDC INTERRUPT CONTROLLER PA PB PC PX USART0 USART2 RXD USART3 TXD CLK REAL TIME COUNTER PDC SERIAL PERIPHERAL INTERFACE 0/1 SYNCHRONOUS SERIAL CONTROLLER SCK MISO, MOSI NPCS0 NPCS[3..1] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA WATCHDOG TIMER 115 kHz RCOSC XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 PDC POWER MANAGER CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER PDC PDC 32 KHz OSC OSC0 OSC1 PLL0 PLL1 TWO-WIRE INTERFACE 0/1 SCL SDA ANALOG TO DIGITAL CONVERTER AUDIO BITSTREAM DAC PDC AD[7..0] ADVREF DATA[1..0] DATAN[1..0] RESET_N GCLK[3..0] A[2..0] B[2..0] CLK[2..0] TIMER/COUNTER 0/1 4 32072A–AVR32–03/09 AT32UC3A3 3. Configuration Summary The table below lists all AT32UC3A3 memory and package configurations: Table 3-1. Device AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 Memory and Package Configurations Flash 256KB 256KB 128KB 128KB 64KB 64KB SRAM 128KB 128KB 128KB 128KB 128KB 128KB AES Yes No Yes No Yes No Package 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 144 balls TBGA/ 144 lead LQFP 5 32072A–AVR32–03/09 AT32UC3A3 4. Package and Pinout 4.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. Figure 4-1. TBGA144 Pinout (top view) 1 A B C D E F G H J K L M 2 3 4 5 6 7 8 9 10 11 12 Table 4-1. 1 A B C D E F G H J K L M PX40 PX10 PX09 PX08 PX38 PX39 PX00 PX01 PX04 PX03 PX11 PX22 BGA144 Package Pinout A1..M8 2 PB00 PB11 PX35 PX37 VDDIO PX07 PX05 VDDIO PX02 PX44 GNDIO PX41 3 PA28 PA31 GNDIO PX36 PX54 PX06 PX59 PX58 PX34 GNDIO PX45 PX42 4 PA27 PB02 PB01 PX47 PX53 PX49 PX50 PX57 PX56 PX46 PX20 PX14 5 PB03 VDDIO PX16 PX19 VDDIO PX48 PX51 VDDIO PX55 PC00 VDDIO PX21 6 PA29 PB04 PX13 PX12 PX15 GNDIO GNDIO PC01 PA14 PX17 PX18 PX23 7 PC02 PC03 PA30 PB10 PB09 GNDIO GNDIO PA17 PA15 PX52 PX43 PX24 8 PC04 VDDIO PB08 PA02 VDDIN PA06 PA23 VDDIO PA19 PA18 ONREG PX25 9 PC05 USB_ VBIAS DPFS PA26 PA25 PA04 PA24 PA21 PA20 PX27 PX26 PX32 10 DPHS DMFS GNDCORE PA11 PA07 PA05 PA03 PA22 TMS GNDIO PX28 PX31 11 DMHS GNDPLL PA08 PB07 VDDCORE PA13 PA00 VDDANA TDO PX29 GNDANA PX30 12 USB_VBUS PA09 PA10 PB06 PA12 PA16 PA01 PB05 RESET_N TCK TDI PX33 6 32072A–AVR32–03/09 AT32UC3A3 Figure 4-2. LQFP144 Pinout 108 109 73 72 144 1 Table 4-2. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 37 36 Package Pinout USB_VBUS VDDIO USB_VBIAS GNDIO DMHS DPHS GNDIO DMFS DPFS VDDIO PB08 PC05 PC04 PA30 PA02 PB10 PB09 PC02 PC03 GNDIO VDDIO PB04 PA29 PB03 PB02 PA27 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 PX10 PX35 PX47 PX15 PX48 PX53 PX49 PX36 PX37 PX54 GNDIO VDDIO PX09 PX08 PX38 PX39 PX06 PX07 PX00 PX59 PX58 PX05 PX01 PX04 PX34 PX02 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 PX20 PX46 PX50 PX57 PX51 PX56 PX55 PX21 VDDIO GNDIO PX17 PX18 PX23 PX24 PX52 PX43 PX27 PX26 PX28 PX25 PX32 PX29 PX33 PX30 PX31 PC00 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 PA21 PA22 PA23 PA24 PA20 PA19 PA18 PA17 GNDANA VDDANA PA25 PA26 PB05 PA00 PA01 PA05 PA03 PA04 PA06 PA16 PA13 VDDIO GNDIO PA12 PA07 PB06 7 32072A–AVR32–03/09 AT32UC3A3 Table 4-2. 27 28 29 30 31 32 33 34 35 36 Package Pinout PB01 PA28 PA31 PB00 PB11 PX16 PX13 PX12 PX19 PX40 63 64 65 66 67 68 69 70 71 72 PX03 VDDIO GNDIO PX44 PX11 PX14 PX42 PX45 PX41 PX22 99 100 101 102 103 104 105 106 107 108 PC01 PA14 PA15 GNDIO VDDIO TMS TDO RESET_N TCK TDI 135 136 137 138 139 140 141 142 143 144 PB07 PA11 PA08 PA10 PA09 GNDCORE VDDCORE VDDIN ONREG GNDPLL 4.2 Peripheral Multiplexing on I/O lines Each GPIO line can be assigned to one of 4 peripheral functions; A, B, C, or D. The following table define how the I/O lines on the peripherals A, B, C, or D are multiplexed by the GPIO. Table 4-3. BGA144 G11 G12 D8 G10 F9 F10 F8 E10 C11 B12 C12 D10 E12 F11 J6 J7 F12 H7 K8 J8 GPIO Controller Function Multiplexing QFP144 122 123 15 125 126 124 127 133 137 139 138 136 132 129 100 101 128 116 115 114 PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 GPIO Pin GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 Function A USART0 - RTS USART0 - CTS USART0 - CLK USART0 - RXD USART0 - TXD USART1 - RXD USART1 - TXD SPI0 - NPCS[3] SPI0 - SCK SPI0 - NPCS[0] SPI0 - MOSI SPI0 - MISO USART1 - CTS USART1 - RTS SPI0 - NPCS[1] MCI - CMD[1] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] Function B TC0 - CLK1 TC0 - A1 TC0 - B1 EIC - EXTINT[4] EIC - EXTINT[5] TC1 - CLK0 TC1 - CLK1 DAC - DATAN[0] DAC - DATA[0] EIC - EXTINT[6] USB USB_VBOF USB - USB_ID SPI0 - NPCS[2] SPI0 - NPCS[1] TWIMS0 TWALM SPI1 - SCK SPI1 - MOSI SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - MISO Function C SPI1 - NPCS[3] USART2 - RTS SPI0 - NPCS[0] DAC - DATA[0] DAC - DATAN[0] USB - USB_ID USB - USB_VBOF USART1 - CLK TC1 - B1 TC1 - A1 TC1 - B0 TC1 - A2 TC1 - A0 EIC - EXTINT[7] TWIMS1 - TWCK TWIMS1 - TWD TC1 - CLK2 ADC - AD[7] ADC - AD[6] ADC - AD[5] ] Function D 8 32072A–AVR32–03/09 AT32UC3A3 Table 4-3. GPIO Controller Function Multiplexing SSC RX_FRAME_SYN C EIC - EXTINT[0] EIC - EXTINT[1] EIC - EXTINT[2] EIC - EXTINT[3] TWIMS1 TWALM USART2 - CTS SSC - RX_DATA SSC RX_CLOCK USART3 - TXD USART3 - CLK USART2 - RXD USART2 - TXD DAC - DATA[1] DAC - DATAN[1] USART2 - CLK USART3 - RXD TC0 - A0 TC0 - B0 SSC TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC RX_FRAME_SYN C SSC TX_FRAME_SYN C J9 H9 H10 G8 G9 E9 D9 A4 A3 A6 C7 B3 A2 C4 B4 A5 B6 H12 D12 D11 C8 E7 113 109 110 111 112 119 120 26 28 23 14 29 30 27 25 24 22 121 134 135 11 17 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 EIC - EXTINT[8] ADC - AD[0] ADC - AD[1] ADC - AD[2] ADC - AD[3] TWIMS0 - TWD TWIMS0 - TWCK MCI - CLK MCI - CMD[0] MCI - DATA[0] MCI - DATA[1] MCI - DATA[2] MCI - DATA[3] MCI - DATA[4] MCI - DATA[5] MCI - DATA[6] MCI - DATA[7] USB - USB_ID USB USB_VBOF SPI1 - SCK SPI1 - MISO SPI1 - NPCS[0] ADC - AD[4] USB - USB_ID USB - USB_VBOF DAC - DATA[1] DAC - DATAN[1] USART1 - DCD USART1 - DSR USART3 - RTS USART3 - CTS TC0 - CLK0 DMACA DMAACK[0] DMACA DMARQ[0] ADC - TRIGGER EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] EBI - NCS[4] MSI - SCLK MSI - BS MSI - DATA[0] MSI - DATA[1] MSI - DATA[2] MSI - DATA[3] MSI - INS D7 16 PB10 GPIO 42 SPI1 - MOSI EBI - NCS[5] B2 K5 H6 A7 B7 A8 A9 G1 H1 31 98 99 18 19 13 12 55 59 PB11 PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 GPIO 43 GPIO 45 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 USART1 - RXD PM - GCLK[1] EBI - DATA[10] EBI - DATA[9] USART0 - RXD USART0 - TXD USART1 - RI USART1 - DTR 9 32072A–AVR32–03/09 AT32UC3A3 Table 4-3. J2 K1 J1 G2 F3 F2 D1 C1 B1 L1 D6 C6 M4 E6 C5 K6 L6 D5 L4 M5 M1 M6 M7 M8 GPIO Controller Function Multiplexing 62 63 60 58 53 54 50 49 37 67 34 33 68 40 32 83 84 35 73 80 72 85 86 92 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 PX23 PX24 PX25 GPIO 53 GPIO 54 GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 68 GPIO 69 GPIO 70 GPIO 71 GPIO 72 GPIO 73 GPIO 74 GPIO 75 GPIO 76 EBI - DATA[8] EBI - DATA[7] EBI - DATA[6] EBI - DATA[5] EBI - DATA[4] EBI - DATA[3] EBI - DATA[2] EBI - DATA[1] EBI - DATA[0] EBI - NWE1 EBI - NWE0 EBI - NRD EBI - NCS[1] EBI - ADDR[19] EBI - ADDR[18] EBI - ADDR[17] EBI - ADDR[16] EBI - ADDR[15] EBI - ADDR[14] EBI - ADDR[13] EBI - ADDR[12] EBI - ADDR[11] EBI - ADDR[10] EBI - ADDR[9] USART3 - RTS USART3 - CTS DMACA DMARQ[1] DMACA DMAACK[1] EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] USART0 - CTS USART0 - RTS USART1 - RXD USART1 - TXD USART1 - CTS USART1 - RTS USART3 - RXD USART3 - TXD USART2 - RXD USART2 - TXD USART2 - CTS USART2 - RTS TC0 - A0 TC0 - B0 TC0 - A1 TC0 - B1 TC0 - A2 TC0 - B2 TC0 - CLK0 TC0 - CLK1 TC0 - CLK2 SSC - TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC RX_FRAME_SYN C SSC TX_FRAME_SYNC SSC - RX_CLOCK PM - GCLK[0] L9 K9 L10 K11 M11 M10 M9 M12 J3 C2 D3 D2 90 89 91 94 96 97 93 95 61 38 44 45 PX26 PX27 PX28 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 GPIO 77 GPIO 78 GPIO 79 GPIO 80 GPIO 81 GPIO 82 GPIO 83 GPIO 84 GPIO 85 GPIO 86 GPIO 87 GPIO 88 EBI - ADDR[8] EBI - ADDR[7] EBI - ADDR[6] EBI - ADDR[5] EBI - ADDR[4] EBI - ADDR[3] EBI - ADDR[2] EBI - ADDR[1] EBI - ADDR[0] EBI - DATA[15] EBI - DATA[14] EBI - DATA[13] EIC - SCAN[7] SPI0 - MISO SPI0 - MOSI SPI0 - SCK SPI0 - NPCS[0] SPI0 - NPCS[1] SPI0 - NPCS[2] SPI0 - NPCS[3] SPI1 - MISO SPI1 - MOSI SPI1 - SCK SPI1 - NPCS[0] PM - GCLK[0] PM - GCLK[1] PM - GCLK[2] PM - GCLK[3] 10 32072A–AVR32–03/09 AT32UC3A3 Table 4-3. E1 F1 A1 M2 M3 L7 K2 L3 K4 D4 F5 F4 G4 G5 K7 E4 E3 J5 J4 H4 H3 G3 GPIO Controller Function Multiplexing 51 52 36 71 69 88 66 70 74 39 41 43 75 77 87 42 46 79 78 76 57 56 PX38 PX39 PX40 PX41 PX42 PX43 PX44 PX45 PX46 PX47 PX48 PX49 PX50 PX51 PX52 PX53 PX54 PX55 PX56 PX57 PX58 PX59 GPIO 89 GPIO 90 GPIO 91 GPIO 92 GPIO 93 GPIO 94 GPIO 95 GPIO 96 GPIO 97 GPIO 98 GPIO 99 GPIO 100 GPIO 101 GPIO 102 GPIO 103 GPIO 104 GPIO 105 GPIO 106 GPIO 107 GPIO 108 GPIO 109 GPIO 110 EBI - DATA[12] EBI - DATA[11] EBI - SDCS EBI - CAS EBI - RAS EBI - SDA10 EBI - SDWE EBI - SDCK EBI - SDCKE EBI - NANDOE EBI - ADDR[23] EBI - CFRNW EBI - CFCE2 EBI - CFCE1 EBI - NCS[3] EBI - NCS[2] EBI - NWAIT EBI - ADDR[22] EBI - ADDR[21] EBI - ADDR[20] EBI - NCS[0] EBI - NANDWE USART3 - TXD EIC - SCAN[3] EIC - SCAN[2] EIC - SCAN[1] EIC - SCAN[0] ADC - TRIGGER USB USB_VBOF USB - USB_ID TC1 - B2 DMACA DMAACK[0] DMACA DMARQ[0] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] MCI - DATA[15] MCI - DATA[14] MCI - DATA[13] MCI - DATA[12] USART2 - RXD USART2 - TXD USART3 - RXD USART3 - TXD MCI - CMD[1] USART1 - RI USART1 - DTR SPI1 - NPCS[1] SPI1 - NPCS[2] USART1 - DCD USART1 - DSR 4.2.1 Oscillator Pinout Table 4-4. pin A7 A8 K5 B7 A9 H6 Oscillator Pinout pin 18 13 98 19 12 99 Pad PC02 PC04 PC00 PC03 PC05 PC01 Oscillator pin xin0 xin1 xin32 xout0 xout1 xout32 11 32072A–AVR32–03/09 AT32UC3A3 4.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 4-5. Signal Name Signal Description List Function Power Type Active Level Comments VDDIO VDDANA VDDIN ONREG I/O Power Supply Analog Power Supply Voltage Regulator Input Supply Voltage Regulator ON/OFF Power Power Power Power Control Power Output Ground Ground Ground Ground Clocks, Oscillators, and PLL’s 1 3.0 to 3.6V 3.0 to 3.6V 2.7 to 3.6V 2.7 to 3.6 V VDDCORE GNDANA GNDIO GNDCORE GNDPLL Voltage Regulator Output for Digital Supply Analog Ground I/O Ground DIgital Ground PLL Ground 1.65 to 1.95 V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG Analog Analog TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input Auxiliary Port - AUX MCKO MDO[5:0] MSEO[1:0] EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Output Output Power Manager - PM Low Low 12 32072A–AVR32–03/09 AT32UC3A3 Table 4-5. Signal Name GCLK[2:0] RESET_N Signal Description List Function Generic Clock Pins Reset Pin Type Output Input DMA Controller - DMACA (optional) Low Active Level Comments DMAACK[1:0] DMARQ[1:0] DMA Acknowledge DMA Requests Output Input External Interrupt Module - EIM EXTINT[7:0] KPS0 - KPS7 NMI_N External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin Input Output Input Low General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] PB[11:0] PC[5:0] PX[59:0] Parallel I/O Controller GPIO port A Parallel I/O Controller GPIO port B Parallel I/O Controller GPIO port C Parallel I/O Controller GPIO port X I/O I/O I/O I/O External Bus Interface - EBI ADDR[23:0] CAS CFCE1 CFCE2 CFRNW DATA[15:0] NANDOE NANDWE NCS[5:0] NRD NWAIT NWE0 NWE1 Address Bus Column Signal Compact Flash 1 Chip Enable Compact Flash 2 Chip Enable Compact Flash Read Not Write Data Bus NAND Flash Output Enable NAND Flash Write Enable Chip Select Read Signal External Wait Signal Write Enable 0 Write Enable 1 Output Output Output Output Output I/O Output Output Output Output Input Output Output Low Low Low Low Low Low Low Low Low Low 13 32072A–AVR32–03/09 AT32UC3A3 Table 4-5. Signal Name RAS SDA10 SDCK SDCKE SDCS SDWE Signal Description List Function Row Signal SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Chip Select SDRAM Write Enable Type Output Output Output Output Output Output MultiMedia Card Interface - MCI Low Low Active Level Low Comments CLK CMD[1:0] DATA[15:0] Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O Serial Peripheral Interface - SPI0 MISO MOSI NPCS[3:0] SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC Low RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O Timer/Counter - TC0, TC1 A0 A1 A2 B0 B1 Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B Channel 1 Line B I/O I/O I/O I/O I/O 14 32072A–AVR32–03/09 AT32UC3A3 Table 4-5. Signal Name B2 CLK0 CLK1 CLK2 Signal Description List Function Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input Type I/O Input Input Input Active Level Comments Two-wire Interface - TWI0, TWI1 SCL SDA Serial Clock Serial Data I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS DCD DSR DTR RI RTS RXD RXDN TXD TXDN Clock Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Inverted Receive Data Transmit Data Inverted Transmit Data Output Input Input Output Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input Audio Bitstream DAC (ABDAC) DATA0-DATA1 DATAN0-DATAN1 D/A Data out D/A Data inverted out Output Output Universal Serial Bus Device - USB FSDM FSDP HSDM USB Full Speed Data USB Full Speed Data + USB High Speed Data Analog Analog Analog Low Low I/O Input Only USART1 Only USART1 Only USART1 Only USART1 15 32072A–AVR32–03/09 AT32UC3A3 Table 4-5. Signal Name HSDP USB_VBIAS USB_VBUS Signal Description List Function USB High Speed Data + USB VBIAS reference USB VBUS for OTG feature Type Analog Analog Output Connect to the ground through a 6810 ohms (+/- 0.5%) resistor Active Level Comments 4.3.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 4.3.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 4.3.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 4.3.4 GPIO Pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the I/O Controller. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset State” of the I/O Controller multiplexing tables. 16 32072A–AVR32–03/09 AT32UC3A3 4.4 4.4.1 Power Considerations Power Supplies The AT32UC3A3 has several types of power supply pins: • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC Voltage and provides the ADVREF voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pins GNDCORE are common to VDDCORE and VDDIN. The ground pin for VDDANA is GNDANA. The ground pin for VDDIO is GNDIO. Refer to Electrical Characteristics chapter for power consumption on the various supply pins. 4.4.2 Voltage Regulator The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDCORE and powers the core, memories and peripherals. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE and GNDCORE: • One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the chip as possible. • One external 2.2µF (or 3.3µF) X7R capacitor (COUT2). Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be used in parallel (100nF NPO and 4.7µF X7R). 3.3V CIN2 CIN1 VDDIN ONREG 1.8V Regulator 1.8V COUT2 COUT1 VDDCORE ONREG input must be tied to VDDIN. 17 32072A–AVR32–03/09 AT32UC3A3 5. Processor and Architecture Rev: 1.4.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 5.1 Features • 32-bit load/store AVR32A RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extention with saturating arithmetic, and a wide variety of multiply instructions • 3-stage pipeline allows one instruction per clock cycle for most instructions – Byte, halfword, word and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection – – – – – 5.2 AVR32 Architecture AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for costsensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 18 32072A–AVR32–03/09 AT32UC3A3 The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 5.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the Memories chapter of this data sheet. Figure 5-1 on page 20 displays the contents of AVR32UC. 19 32072A–AVR32–03/09 AT32UC3A3 Figure 5-1. Interrupt controller interface Overview of the AVR32UC CPU Reset interface OCD interface OCD system Power/ Reset control AVR32UC CPU pipeline MPU Instruction memory controller High Speed Bus master High Speed Bus Data memory controller High Speed Bus slave High Speed Bus High Speed Bus master High Speed Bus 5.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 5-2 on page 21 shows an overview of the AVR32UC pipeline stages. CPU Local Bus Data RAM interface CPU Local Bus master 20 32072A–AVR32–03/09 AT32UC3A3 Figure 5-2. The AVR32UC Pipeline MUL Multiply unit IF ID Regf ile Read A LU Regf ile w rite A LU unit Pref etch unit Decode unit Load-store unit LS 5.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 5.3.3 Java Support AVR32UC does not provide Java hardware acceleration. 5.3.4 Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. 5.3.5 21 32072A–AVR32–03/09 AT32UC3A3 The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 5-1. Instruction ld.d st.d Instructions with Unaligned Reference Support Supported alignment Word Word 5.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: • All SIMD instructions • All coprocessor instructions if no coprocessors are present • retj, incjosp, popjc, pushjc • tlbr, tlbs, tlbw • cache 5.3.7 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The device described in this datasheet uses CPU revision 3. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 22 32072A–AVR32–03/09 AT32UC3A3 5.4 5.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 5-3. Application Bit 31 Bit 0 Bit 31 The AVR32UC Register File INT0 Bit 31 Bit 0 Supervisor Bit 0 INT1 Bit 31 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Exception Bit 31 Bit 0 NMI Bit 31 Bit 0 Secure Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 5.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 5-4 on page 23 and Figure 5-5 on page 24. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 5-4. Bit 31 The Status Register High Halfword Bit 16 SS LC 1 0 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM Bit name Initial value Global Interrupt Mask Interrupt Level 0 Mask Interrupt Level 1 Mask Interrupt Level 2 Mask Interrupt Level 3 Mask Exception Mask Mode Bit 0 Mode Bit 1 Mode Bit 2 Reserved Debug State Debug State Mask Reserved Secure State 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 23 32072A–AVR32–03/09 AT32UC3A3 Figure 5-5. Bit 15 The Status Register Low Halfword Bit 0 0 T 0 0 0 0 0 0 0 0 0 L 0 Q 0 V 0 N 0 Z 0 C 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 5.4.3 5.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 5-2 on page 24. Table 5-2. Priority 1 2 3 4 5 6 N/A N/A Overview of Execution Modes, their Priorities and Privilege Levels. Mode Non Maskable Interrupt Exception Interrupt 3 Interrupt 2 Interrupt 1 Interrupt 0 Supervisor Application Security Privileged Privileged Privileged Privileged Privileged Privileged Privileged Unprivileged Description Non Maskable high priority interrupt mode Execute exceptions General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode Runs supervisor calls Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 5.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. 24 32072A–AVR32–03/09 AT32UC3A3 All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 5.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 5-3. Reg # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 System Registers Address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 Name SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 JAVA_LV1 JAVA_LV2 Function Status Register Exception Vector Base Address Application Call Base Address CPU Control Register Exception Cause Register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Status Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Address Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC 25 32072A–AVR32–03/09 AT32UC3A3 Table 5-3. Reg # 26 27 28 29 30 31 32 33-63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 System Registers (Continued) Address 104 108 112 116 120 124 128 132-252 256 260 264 268 272 276 280 284 288 292 296 300 304 308 312 316 320 324 328 332 336 340 344 348 352 356 360 364 Name JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA JBCR Reserved CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 MPUPSR0 MPUPSR1 MPUPSR2 MPUPSR3 Function Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Reserved for future use Configuration register 0 Configuration register 1 Cycle Counter register Compare register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Bus Error Address Register MPU Address Register region 0 MPU Address Register region 1 MPU Address Register region 2 MPU Address Register region 3 MPU Address Register region 4 MPU Address Register region 5 MPU Address Register region 6 MPU Address Register region 7 MPU Privilege Select Register region 0 MPU Privilege Select Register region 1 MPU Privilege Select Register region 2 MPU Privilege Select Register region 3 26 32072A–AVR32–03/09 AT32UC3A3 Table 5-3. Reg # 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 System Registers (Continued) Address 368 372 376 380 384 388 392 396 400 404 408 412 416 420 424 428 432 436 440 444 448-764 768-1020 Name MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR Reserved IMPL Function MPU Privilege Select Register region 4 MPU Privilege Select Register region 5 MPU Privilege Select Register region 6 MPU Privilege Select Register region 7 Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC MPU Access Permission Register A MPU Access Permission Register B MPU Control Register Secure State Status Register Secure State Address Flash Register Secure State Address RAM Register Secure State Address 0 Register Secure State Address 1 Register Secure State Stack Pointer System Register Secure State Stack Pointer Application Register Secure State Return Address Register Secure State Return Status Register Reserved for future use IMPLEMENTATION DEFINED 5.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a welldefined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution control is passed to an event handler at an address specified in Table 5-4 on page 30. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All external interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception 27 32072A–AVR32–03/09 AT32UC3A3 code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including external interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU. 5.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 5.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 5-4, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete i nstruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 5.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of 28 32072A–AVR32–03/09 AT32UC3A3 code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 5.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The mode bits in the status register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 5.5.5 Entry Points for Events Several different event handler entry points exists. In AVR32UC, the reset address is 0x8000_0000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All external interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an external Interrupt Controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 5-4. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 5-4. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-point unit. 29 32072A–AVR32–03/09 AT32UC3A3 Table 5-4. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Priority and Handler Addresses for Events Handler Address 0x8000_0000 Provided by OCD system EVBA+0x00 EVBA+0x04 EVBA+0x08 EVBA+0x0C EVBA+0x10 Autovectored Autovectored Autovectored Autovectored EVBA+0x14 EVBA+0x50 EVBA+0x18 EVBA+0x1C EVBA+0x20 EVBA+0x24 EVBA+0x28 EVBA+0x2C EVBA+0x30 EVBA+0x100 EVBA+0x34 EVBA+0x38 EVBA+0x60 EVBA+0x70 EVBA+0x3C EVBA+0x40 EVBA+0x44 Name Reset OCD Stop CPU Unrecoverable exception TLB multiple hit Bus error data fetch Bus error instruction fetch NMI Interrupt 3 request Interrupt 2 request Interrupt 1 request Interrupt 0 request Instruction Address ITLB Miss ITLB Protection Breakpoint Illegal Opcode Unimplemented instruction Privilege violation Floating-point Coprocessor absent Supervisor call Data Address (Read) Data Address (Write) DTLB Miss (Read) DTLB Miss (Write) DTLB Protection (Read) DTLB Protection (Write) DTLB Modified Event source External input OCD system Internal MPU Data bus Data bus External input External input External input External input External input CPU MPU MPU OCD system Instruction Instruction Instruction UNUSED Instruction Instruction CPU CPU MPU MPU MPU MPU UNUSED PC of offending instruction PC of offending instruction PC of offending instruction PC(Supervisor Call) +2 PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction PC of offending instruction Stored Return Address Undefined First non-completed instruction PC of offending instruction 30 32072A–AVR32–03/09 AT32UC3A3 6. Memories 6.1 Embedded Memories • Internal High-Speed Flash – 256KBytes (AT32UC3A3256/S) – 128Kbytes (AT32UC3A3128/S) – 64Kbytes (AT32UC3A364/S) • 0 wait state access at up to 36MHz in worst case conditions • 1 wait state access at up to 66MHz in