AT32UC3A3256S_11

Features • High Performance, Low Power 32-bit AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performing up to 1.51DMIPS/MHz • Up to 92DMIPS Running at 66MHz from Flash (1 Wait-State) • Up to 54 DMIPS Running at 36MHz from Flash (0 Wait-State) – Memory Protection Unit Multi-Layer Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral Communication – 4 generic DMA Channels for High Bandwidth Data Paths Internal High-Speed Flash – 256KBytes, 128KBytes, 64KBytes versions – Single-Cycle Flash Access up to 36MHz – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4 ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM – 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus – 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System Interrupt Controller – Autovectored Low Latency Interrupt Service with Programmable Priority System Functions – Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator – Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL), – Watchdog Timer, Real-Time Clock Timer External Memories – Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash – Up to 66 MHz External Storage device support – MultiMediaCard (MMC V4.3), Secure-Digital (SD V2.0), SDIO V1.1 – CE-ATA V1.1, FastSD, SmartMedia, Compact Flash – Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro – IDE Interface One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S, AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S – 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications – Buffer Encryption/Decryption Capabilities Universal Serial Bus (USB) – High-Speed USB 2.0 (480Mbit/s) Device and Embedded Host – Flexible End-Point Configuration and Management with Dedicated DMA Channels – On-Chip Transceivers Including Pull-Ups One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs. Two Three-Channel 16-bit Timer/Counter (TC) Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Fractionnal Baudrate Generator • 32-bit AVR® Microcontroller AT32UC3A3256S AT32UC3A3256 AT32UC3A3128S AT32UC3A3128 AT32UC3A364S AT32UC3A364 AT32UC3A4256S AT32UC3A4256 AT32UC3A4128S AT32UC3A4128 AT32UC3A464S AT32UC3A464 • • • • • • Summary • • • • • 32072G–11/2011 AT32UC3A3/A4 – Support for SPI and LIN – Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller – Supports I2S and Generic Frame-Based Protocols Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible 16-bit Stereo Audio Bitstream – Sample Rate Up to 50 KHz QTouch® Library Support – Capacitive Touch Buttons, Sliders, and Wheels QTouch® and QMatrix® AcquisitionOn-Chip Debug System (JTAG interface) – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace 110 General Purpose Input/Output (GPIOs) – Standard or High Speed mode – Toggle capability: up to 66MHz Packages – 144-ball TFBGA, 11x11 mm, pitch 0.8 mm – 144-pin LQFP, 22x22 mm, pitch 0.5 mm – 100-ball VFBGA, 7x7 mm, pitch 0.65 mm Single 3.3V Power Supply • • • • • • • • • 2 32072G–11/2011 AT32UC3A3/A4 1. Description The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions. The AT32UC3A3/A4 incorporates on-chip Flash and SRAM memories for secure and fast access. 64 KBytes of SRAM are directly coupled to the AVR32 UC for performances optimization. Two blocks of 32 Kbytes SRAM are independently attached to the High Speed Bus Matrix, allowing real ping-pong management. The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between peripherals and memories without processor involvement. The PDCA drastically reduces processing overhead when transferring continuous and large data streams. The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. 16-bit channels are combined to operate as 32-bit channels. The AT32UC3A3/A4 also features many communication interfaces for communication intensive applications like UART, SPI or TWI. The USART supports different communication modes, like SPI Mode and LIN Mode. Additionally, a flexible Synchronous Serial Controller (SSC) is available. The SSC provides easy access to serial communication protocols and audio standards like I2S. The AT32UC3A3/A4 includes a powerfull External Bus Interface to interface all standard memory device like SRAM, SDRAM, NAND Flash or parallel interfaces like LCD Module. The peripheral set includes a High Speed MCI for SDIO/SD/MMC and a hardware encryption module based on AES algorithm. The device embeds a 10-bit ADC and a Digital Audio bistream DAC. The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high speed peripherals (USB, External Memories, MMC, SDIO, ...) and through high speed internal features (AES, internal memories). The High-Speed (480MBit/s) USB 2.0 Device and Host interface supports several USB Classes at the same time thanks to the rich Endpoint configuration. The Embedded Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. This periphal has its own dedicated DMA and is perfect for Mass Storage application. AT32UC3A3/A4 integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control. 3 32072G–11/2011 AT32UC3A3/A4 2. Overview 2.1 Block Diagram Figure 2-1. TCK TDO TDI TMS Block Diagram PBB ID VBOF FLASH CONTROLLER USB_VBIAS USB_VBUS DMFS, DMHS DPFS, DPHS MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N NEXUS CLASS 2+ OCD MEMORY PROTECTION UNIT MEMORY INTERFACE JTAG INTERFACE AVR32UC CPU INSTR INTERFACE DATA INTERFACE LOCAL BUS INTERFACE FAST GPIO 64 KB SRAM USB HS INTERFACE DMA 32KB RAM 32KB RAM HRAM0/1 S M S S M M M M M S S 256/128/64 KB FLASH DMACA GENERAL PURPOSE IOs S EXTERNAL BUS INTERFACE (SDRAM, STATIC MEMORY, COMPACT FLASH & NAND FLASH) HIGH SPEED BUS MATRIX DATA[15..0] ADDR[23..0] NCS[5..0] NRD NWAIT NWE0 NWE1 NWE3 RAS CAS SDA10 SDCK SDCKE SDWE CFCE1 CFCE2 CFRW NANDOE NANDWE AES DMA S S CONFIGURATION S REGISTERS BUS M PB HSB HSB HSB-PB BRIDGE B HSB-PB BRIDGE A PB PBA PERIPHERAL DMA CONTROLLER CLK DMA CMD[1..0] PA PB PC PX DATA[15..0] DMA GENERAL PURPOSE IOs MULTIMEDIA CARD & MEMORY STICK INTERFACE USART1 RXD TXD CLK RTS, CTS DSR, DTR, DCD, RI RXD TXD CLK RTS, CTS EXTINT[7..0] SCAN[7..0] NMI DMA EXTERNAL INTERRUPT CONTROLLER REAL TIME COUNTER DMA INTERRUPT CONTROLLER PA PB PC PX USART0 USART2 RXD USART3 TXD CLK VDDIN GNDCORE VDDCORE 1V8 Regulator SERIAL PERIPHERAL INTERFACE 0/1 SYNCHRONOUS SERIAL CONTROLLER SPCK MISO, MOSI NPCS0 NPCS[3..1] TX_CLOCK, TX_FRAME_SYNC TX_DATA RX_CLOCK, RX_FRAME_SYNC RX_DATA WATCHDOG TIMER DMA 115 kHz RCSYS XIN32 XOUT32 XIN0 XOUT0 XIN1 XOUT1 POWER MANAGER DMA DMA 32 KHz OSC OSC0 OSC1 PLL0 PLL1 TWCK CLOCK GENERATOR CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER TWO-WIRE INTERFACE 0/1 TWD TWALM ANALOG TO DIGITAL CONVERTER AUDIO BITSTREAM DAC DMA AD[7..0] DMA DATA[1..0] DATAN[1..0] RESET_N GCLK[3..0] A[2..0] B[2..0] CLK[2..0] TIMER/COUNTER 0/1 4 32072G–11/2011 AT32UC3A3/A4 2.2 Configuration Summary The table below lists all AT32UC3A3/A4 memory and package configurations: Table 2-1. Feature Flash SRAM HSB RAM EBI GPIO Configuration Summary AT32UC3A3256/128/64 AT32UC3A4256/128/64 256/128/64 KB 64 KB 64 KB Full 110 8 2 4 8 4 2 2 MMC/SD slots 1 1 1 1 6 1 1 1 PLL 80-240 MHz (PLL0/PLL1) Crystal Oscillators 0.4-20 MHz (OSC0/OSC1) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 115 kHz (RCSYS) 1 8 1 66 MHz LQFP144, TFBGA144 VFBGA100 1 MMC/SD slot + 1 SD slot Nand flash only 70 External Interrupts TWI USART Peripheral DMA Channels Generic DMA Channels SPI MCI slots High Speed USB AES (S option) SSC Audio Bitstream DAC Timer/Counter Channels Watchdog Timer Real-Time Clock Timer Power Manager Oscillators 10-bit ADC number of channels JTAG Max Frequency Package 5 32072G–11/2011 AT32UC3A3/A4 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multiplexing on I/O Line section. Figure 3-1. TFBGA144 Pinout (top view) 1 A PX40 2 PB00 3 PA28 4 PA27 5 PB03 6 PA29 7 PC02 8 PC04 9 PC05 10 11 12 DPHS DMHS USB_VBUS B PX10 PB11 PA31 PB02 VDDIO PB04 PC03 VDDIO USB_VBIAS DMFS GNDPLL PA09 C PX09 PX35 GNDIO PB01 PX16 PX13 PA30 PB08 DPFS GNDCORE PA08 PA10 D E PX08 PX37 PX36 PX47 PX19 PX12 PB10 PA02 PA26 PA11 PB07 PB06 PX38 VDDIO PX54 PX53 VDDIO PX15 PB09 VDDIN PA25 PA07 VDDCORE PA12 F G PX39 PX07 PX06 PX49 PX48 GNDIO GNDIO PA06 PA04 PA05 PA13 PA16 PX00 PX05 PX59 PX50 PX51 GNDIO GNDIO PA23 PA24 PA03 PA00 PA01 H PX01 VDDIO PX58 PX57 VDDIO PC01 PA17 VDDIO PA21 PA22 VDDANA PB05 J K L M PX04 PX02 PX34 PX56 PX55 PA14 PA15 PA19 PA20 TMS TDO RESET_N PX03 PX44 GNDIO PX46 PC00 PX17 PX52 PA18 PX27 GNDIO PX29 TCK PX11 GNDIO PX45 PX20 VDDIO PX18 PX43 VDDIN PX26 PX28 GNDANA TDI PX22 PX41 PX42 PX14 PX21 PX23 PX24 PX25 PX32 PX31 PX30 PX33 6 32072G–11/2011 AT32UC3A3/A4 Figure 3-2. LQFP144 Pinout TDI TCK RESET_N TDO TMS VDDIO GNDIO PA15 PA14 PC01 PC00 PX31 PX30 PX33 PX29 PX32 PX25 PX28 PX26 PX27 PX43 PX52 PX24 PX23 PX18 PX17 GNDIO VDDIO PX21 PX55 PX56 PX51 PX57 PX50 PX46 PX20 PA21 PA22 PA23 PA24 PA20 PA19 PA18 PA17 GNDANA VDDANA PA25 PA26 PB05 PA00 PA01 PA05 PA03 PA04 PA06 PA16 PA13 VDDIO GNDIO PA12 PA07 PB06 PB07 PA11 PA08 PA10 PA09 GNDCORE VDDCORE VDDIN VDDIN GNDPLL 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PX40 PX19 PX12 PX13 PX16 PB11 PB00 PA31 PA28 PB01 PA27 PB02 PB03 PA29 PB04 VDDIO GNDIO PC03 PC02 PB09 PB10 PA02 PA30 PC04 PC05 PB08 VDDIO DPFS DMFS GNDIO DPHS DMHS GNDIO USB_VBIAS VDDIO USB_VBUS 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 PX22 PX41 PX45 PX42 PX14 PX11 PX44 GNDIO VDDIO PX03 PX02 PX34 PX04 PX01 PX05 PX58 PX59 PX00 PX07 PX06 PX39 PX38 PX08 PX09 VDDIO GNDIO PX54 PX37 PX36 PX49 PX53 PX48 PX15 PX47 PX35 PX10 7 32072G–11/2011 AT32UC3A3/A4 Figure 3-3. VFBGA100 Pinout (top view) 1 A B C D E F G H J K PA28 2 PA27 3 PB04 4 PA30 5 PC02 6 PC03 7 PC05 8 DPHS 9 10 DMHS USB_VBUS PB00 PB01 PB02 PA29 VDDIO VDDIO PC04 DPFS DMFS GNDPLL PB11 PA31 GNDIO PB03 PB09 PB08 USB_VBIAS GNDIO PA11 PA10 PX12 PX10 PX13 PX16/ PX53(1) PB10 PB07 PB06 PA09 VDDIN VDDIN PA02/ PX47(1) GNDIO PX08 PX09 VDDIO GNDIO PA16 PA06/ PA13(1) PA04 VDDCORE PX19/ PX59(1) VDDIO PX06 PX07 GNDIO VDDIO PA26/ PB05(1) PA08 PA03 GNDCORE PX05 PX01 PX02 PX00 PX30 PA23/ PX46(1) PA12/ PA25(1) PA00/ PA18(1) PA05 PA01/ PA17(1) PX04 PX21 GNDIO PX25 PX31 PA22/ PX20(1) TMS GNDANA PA20/ PX18(1) PA07/ PA19(1) PX03 PX24 PX26 PX29 VDDIO VDDANA PA15/ PX45(1) TDO RESET_N PA24/ PX17(1) PX23 PX27 PX28 PX15/ PX32(1) PC00/ PX14(1) PC01 PA14/ PX11(1) TDI TCK PA21/ PX22(1) Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict 8 32072G–11/2011 AT32UC3A3/A4 3.2 3.2.1 Peripheral Multiplexing on I/O lines Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1. GPIO Controller Function Multiplexing G P PIN Type Supply VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDAN A VDDAN A VDDAN A VDDAN A VDDAN A VDDAN A VDDAN A VDDAN A VDDIO VDDIO VDDIO (2) GPIO function BGA 144 G11 G12 D8 G10 F9 F10 F8 E10 C11 B12 C12 D10 E12 F11 J6 J7 F12 H7 K8 J8 J9 H9 H10 G8 G9 E9 D9 A4 QFP 144 122 123 15 125 126 124 127 133 137 139 138 136 132 129 100 101 128 116 115 114 113 109 110 111 112 119 120 26 BGA 100 G8 (1) (1) I PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 O 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 A USART0 - RTS USART0 - CTS USART0 - CLK USART0 - RXD USART0 - TXD USART1 - RXD USART1 - TXD SPI0 - NPCS[3] SPI0 - SPCK SPI0 - NPCS[0] SPI0 - MOSI SPI0 - MISO USART1 - CTS USART1 - RTS SPI0 - NPCS[1] MCI - CMD[1] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] EIC - NMI ADC - AD[0] ADC - AD[1] ADC - AD[2] ADC - AD[3] TWIMS0 - TWD TWIMS0 - TWCK MCI - CLK B TC0 - CLK1 TC0 - A1 TC0 - B1 EIC - EXTINT[4] EIC - EXTINT[5] TC1 - CLK0 TC1 - CLK1 ABDAC - DATAN[0] ABDAC - DATA[0] EIC - EXTINT[6] USB - VBOF USB - ID SPI0 - NPCS[2] SPI0 - NPCS[1] TWIMS0 - TWALM SPI1 - SPCK SPI1 - MOSI SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - MISO SSC - RX_FRAME_SYNC EIC - EXTINT[0] EIC - EXTINT[1] EIC - EXTINT[2] EIC - EXTINT[3] TWIMS1 - TWALM USART2 - CTS SSC - RX_DATA C SPI1 - NPCS[3] USART2 - RTS SPI0 - NPCS[0] ABDAC - DATA[0] ABDAC - DATAN[0] USB - ID USB - VBOF USART1 - CLK TC1 - B1 TC1 - A1 TC1 - B0 TC1 - A2 TC1 - A0 EIC - EXTINT[7] TWIMS1 - TWCK TWIMS1 - TWD TC1 - CLK2 ADC - AD[7] ADC - AD[6] ADC - AD[5] ADC - AD[4] USB - ID USB - VBOF ABDAC - DATA[1] ABDAC - DATAN[1] USART1 - DCD USART1 - DSR USART3 - RTS D x3 x1 x1 x1 x1 x1 x1 x1 x3 x2 x2 x2 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x2 G10 E1 (1) F9 E9 G9 E8 (1) H10(1) F8 D8 C10 C9 G7 E8 (1) (1) (1) K7 J7(1) E7 G10(1) G8(1) H10(1) H9(1) K10(1) H6(1) G6(1) J10(1) G7 (1) F7 ) A2 (1) MSI - SCLK 9 32072G–11/2011 AT32UC3A3/A4 Table 3-1. GPIO Controller Function Multiplexing G P BGA 144 A3 A6 C7 B3 A2 C4 B4 A5 B6 H12 D12 D11 C8 E7 D7 B2 K5 H6 A7 B7 A8 A9 G1 H1 J2 K1 J1 G2 F3 F2 D1 C1 B1 L1 D6 C6 GPIO function PIN Type Supply VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO (2) QFP 144 28 23 14 29 30 27 25 24 22 121 134 135 11 17 16 31 98 99 18 19 13 12 55 59 62 63 60 58 53 54 50 49 37 67 34 33 BGA 100 A1 B4 A4 C2 B1 B2 B3 C4 A3 F7 (1) I PIN PA28 PA29 PA30 PA31 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 O 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 A MCI - CMD[0] MCI - DATA[0] MCI - DATA[1] MCI - DATA[2] MCI - DATA[3] MCI - DATA[4] MCI - DATA[5] MCI - DATA[6] MCI - DATA[7] USB - ID USB - VBOF SPI1 - SPCK SPI1 - MISO SPI1 - NPCS[0] SPI1 - MOSI USART1 - RXD B SSC - RX_CLOCK USART3 - TXD USART3 - CLK USART2 - RXD USART2 - TXD ABDAC - DATA[1] ABDAC - DATAN[1] USART2 - CLK USART3 - RXD TC0 - A0 TC0 - B0 SSC - TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC - RX_FRAME_SYNC SSC - TX_FRAME_SYNC C USART3 - CTS TC0 - CLK0 DMACA - DMAACK[0] DMACA - DMARQ[0] ADC - TRIGGER EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] EBI - NCS[4] EBI - NCS[5] PM - GCLK[1] D MSI - BS MSI DATA[0] MSI DATA[1] MSI DATA[2] MSI DATA[3] MSI - INS x1 x1 x1 x1 x1 x1 x1 x1 x1 x3 x1 x3 x2 x2 x2 x1 x1 x1 x1 x1 x1 x1 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 D7 D6 C6 C5 D5 C1 K5(1) K6 A5 A6 B7 A7 G4 G2 G3 J1 H1 G1 F3 F4 E3 E4 D2 K7 (1) EBI - DATA[10] EBI - DATA[9] EBI - DATA[8] EBI - DATA[7] EBI - DATA[6] EBI - DATA[5] EBI - DATA[4] EBI - DATA[3] EBI - DATA[2] EBI - DATA[1] EBI - DATA[0] EBI - NWE1 EBI - NWE0 EBI - NRD USART0 - RXD USART0 - TXD USART0 - CTS USART0 - RTS USART1 - RXD USART1 - TXD USART1 - CTS USART1 - RTS USART3 - RXD USART3 - TXD USART2 - RXD USART2 - TXD USART2 - CTS USART2 - RTS USART1 - RI USART1 - DTR PM - GCLK[0] D1 D3 MCI - CLK MCI - CLK 10 32072G–11/2011 AT32UC3A3/A4 Table 3-1. GPIO Controller Function Multiplexing G P BGA 144 M4 E6 C5 K6 L6 D5 L4 M5 M1 M6 M7 M8 L9 K9 L10 K11 M11 M10 M9 M12 J3 C2 D3 D2 E1 F1 A1 M2 M3 L7 K2 L3 K4 D4 F5 F4 G4 G5 GPIO function PIN Type Supply VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO (2) QFP 144 68 40 32 83 84 35 73 80 72 85 86 92 90 89 91 94 96 97 93 95 61 38 44 45 51 52 36 71 69 88 66 70 74 39 41 43 75 77 BGA 100 K5 K4 D4 (1) (1) (1) I PIN PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 PX23 PX24 PX25 PX26 PX27 PX28 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 PX38 PX39 PX40 PX41 PX42 PX43 PX44 O 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 A EBI - NCS[1] EBI - ADDR[19] EBI - ADDR[18] EBI - ADDR[17] EBI - ADDR[16] EBI - ADDR[15] EBI - ADDR[14] EBI - ADDR[13] EBI - ADDR[12] EBI - ADDR[11] EBI - ADDR[10] EBI - ADDR[9] EBI - ADDR[8] EBI - ADDR[7] EBI - ADDR[6] EBI - ADDR[5] EBI - ADDR[4] EBI - ADDR[3] EBI - ADDR[2] EBI - ADDR[1] EBI - ADDR[0] EBI - DATA[15] EBI - DATA[14] EBI - DATA[13] EBI - DATA[12] EBI - DATA[11] B C TC0 - A0 D x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x2 x3 x2 x2 x2 x2 x2 x2 USART3 - RTS USART3 - CTS DMACA - DMARQ[1] DMACA - DMAACK[1] EIC - SCAN[0] EIC - SCAN[1] EIC - SCAN[2] EIC - SCAN[3] EIC - SCAN[4] EIC - SCAN[5] EIC - SCAN[6] EIC - SCAN[7] SPI0 - MISO SPI0 - MOSI SPI0 - SPCK SPI0 - NPCS[0] SPI0 - NPCS[1] SPI0 - NPCS[2] SPI0 - NPCS[3] SPI1 - MISO SPI1 - MOSI SPI1 - SPCK SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2] MCI - CLK TC0 - B0 TC0 - A1 TC0 - B1 TC0 - A2 TC0 - B2 TC0 - CLK0 TC0 - CLK1 TC0 - CLK2 SSC - TX_CLOCK SSC - TX_DATA SSC - RX_DATA SSC - RX_FRAME_SYNC SSC - TX_FRAME_SYNC SSC - RX_CLOCK J10(1) H9(1) F1 (1) (1) H6 H2 K10 (1) K1 J2 H4 J3 K2 K3 J4 G5 H5 K4 (1) PM - GCLK[0] PM - GCLK[1] PM - GCLK[2] PM - GCLK[3] USART1 - DCD USART1 - DSR EBI - CAS EBI - RAS EBI - SDA10 EBI - SDWE EBI - SDCK EBI - SDCKE EBI - NANDOE EBI - ADDR[23] EBI - CFRNW EBI - CFCE2 EBI - CFCE1 ADC - TRIGGER USB - VBOF USB - ID TC1 - B2 DMACA - DMAACK[0] MCI - DATA[11] MCI - DATA[10] MCI - DATA[9] MCI - DATA[8] MCI - DATA[15] USART1 - RI USART1 - DTR J7(1) G6(1) E1 (1) PX45 PX46 PX47 PX48 PX49 PX50 PX51 11 32072G–11/2011 AT32UC3A3/A4 Table 3-1. GPIO Controller Function Multiplexing G P BGA 144 K7 E4 E3 J5 J4 H4 H3 G3 GPIO function PIN Type Supply VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO (2) QFP 144 87 42 46 79 78 76 57 56 BGA 100 PIN PX52 D4 (1) I O 103 104 105 106 107 108 109 110 A EBI - NCS[3] EBI - NCS[2] EBI - NWAIT EBI - ADDR[22] EBI - ADDR[21] EBI - ADDR[20] EBI - NCS[0] EBI - NANDWE B DMACA - DMARQ[0] C MCI - DATA[14] MCI - DATA[13] D x2 x2 x2 x2 x2 x2 x2 x2 PX53 PX54 PX55 PX56 PX57 PX58 USART3 - TXD EIC - SCAN[3] EIC - SCAN[2] EIC - SCAN[1] EIC - SCAN[0] MCI - DATA[12] USART2 - RXD USART2 - TXD USART3 - RXD USART3 - TXD MCI - CMD[1] F1(1) PX59 Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict. 2. Refer to ”Electrical Characteristics” on page 40 for a description of the electrical properties of the pad types used. 3. GPIO 44 is physically implemented in silicon but must be kept unused and configured in input mode. 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the same pin. Table 3-2. Function GPIO Controller Function multiplexing Nexus OCD AUX port connections JTAG port connections Oscillators Peripheral Functions Description GPIO and GPIO peripheral selection A to D OCD trace system JTAG debug port OSC0, OSC1, OSC32 3.2.3 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the Power Mananger (PM). Please refer to the PM chapter for more information about this. 12 32072G–11/2011 AT32UC3A3/A4 Table 3-3.Oscillator Pinout TFBGA144 A7 B7 A8 A9 K5 H6 Note: QFP144 18 19 13 12 98 99 VFBGA100 A5 A6 B7 A7 K5 (1) Pin name PC02 PC03 PC04 PC05 PC00 PC01 Oscillator pin XIN0 XOUT0 XIN1 XOUT1 XIN32 XOUT32 K6 1. This ball is physically connected to 2 GPIOs. Software must managed carrefully the GPIO configuration to avoid electrical conflict 3.2.4 JTAG port connections Table 3-4. TFBGA144 K12 L12 J11 J10 JTAG Pinout QFP144 107 108 105 104 VFBGA100 K9 K8 J8 H7 Pin name TCK TDI TDO TMS JTAG pin TCK TDI TDO TMS 3.2.5 Nexus OCD AUX port connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespective of the GPIO configuration. Three differents OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 3-5. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] MSEO[1] MSEO[0] MCKO EVTO_N Nexus OCD AUX port connections AXS=0 PB05 PA00 PA01 PA03 PA16 PA13 PA12 PA10 PA11 PB07 PB06 AXS=1 PA08 PX56 PX57 PX58 PA24 PA23 PA22 PA07 PX55 PX00 PB06 AXS=2 PX00 PX06 PX05 PX04 PX03 PX02 PX01 PX08 PX07 PB09 PB06 13 32072G–11/2011 AT32UC3A3/A4 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-6. Signal Name Signal Description List Function Power Type Active Level Comments VDDIO VDDANA VDDIN VDDCORE GNDANA GNDIO GNDCORE GNDPLL I/O Power Supply Analog Power Supply Voltage Regulator Input Supply Voltage Regulator Output for Digital Supply Analog Ground I/O Ground Digital Ground PLL Ground Power Power Power Power Output Ground Ground Ground Ground Clocks, Oscillators, and PLL’s 3.0 to 3.6V 3.0 to 3.6V 3.0 to 3.6V 1.65 to 1.95 V XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32 Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG Analog Analog TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input Auxiliary Port - AUX MCKO MDO[5:0] MSEO[1:0] EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Input Output Power Manager - PM Low Low GCLK[3:0] Generic Clock Pins Output 14 32072G–11/2011 AT32UC3A3/A4 Table 3-6. Signal Name RESET_N Signal Description List Function Reset Pin Type Input DMA Controller - DMACA (optional) Active Level Low Comments DMAACK[1:0] DMARQ[1:0] DMA Acknowledge DMA Requests Output Input External Interrupt Controller - EIC EXTINT[7:0] SCAN[7:0] NMI External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin Input Output Input Low General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX PA[31:0] PB[11:0] PC[5:0] PX[59:0] Parallel I/O Controller GPIO port A Parallel I/O Controller GPIO port B Parallel I/O Controller GPIO port C Parallel I/O Controller GPIO port X I/O I/O I/O I/O External Bus Interface - EBI ADDR[23:0] CAS CFCE1 CFCE2 CFRNW DATA[15:0] NANDOE NANDWE NCS[5:0] NRD NWAIT NWE0 NWE1 RAS Address Bus Column Signal Compact Flash 1 Chip Enable Compact Flash 2 Chip Enable Compact Flash Read Not Write Data Bus NAND Flash Output Enable NAND Flash Write Enable Chip Select Read Signal External Wait Signal Write Enable 0 Write Enable 1 Row Signal Output Output Output Output Output I/O Output Output Output Output Input Output Output Output Low Low Low Low Low Low Low Low Low Low Low 15 32072G–11/2011 AT32UC3A3/A4 Table 3-6. Signal Name SDA10 SDCK SDCKE SDWE Signal Description List Function SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Write Enable Type Output Output Output Output MultiMedia Card Interface - MCI Low Active Level Comments CLK CMD[1:0] DATA[15:0] Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O Memory Stick Interface - MSI SCLK BS DATA[3:0] Memory Stick Clock Memory Stick Command Multimedia Card Data Output I/O I/O Serial Peripheral Interface - SPI0, SPI1 MISO MOSI NPCS[3:0] SPCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC RX_CLOCK RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC SSC Receive Clock SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync I/O Input I/O I/O Output I/O Timer/Counter - TC0, TC1 A0 A1 A2 Channel 0 Line A Channel 1 Line A Channel 2 Line A I/O I/O I/O Low 16 32072G–11/2011 AT32UC3A3/A4 Table 3-6. Signal Name B0 B1 B2 CLK0 CLK1 CLK2 Signal Description List Function Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input Type I/O I/O I/O Input Input Input Active Level Comments Two-wire Interface - TWI0, TWI1 TWCK TWD TWALM Serial Clock Serial Data SMBALERT signal I/O I/O I/O Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS DCD DSR DTR RI RTS RXD TXD Clock Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Transmit Data Output Input Output Analog to Digital Converter - ADC AD0 - AD7 Analog input pins Analog input Audio Bitstream DAC (ABDAC) DATA0-DATA1 DATAN0-DATAN1 D/A Data out D/A Data inverted out Output Output Universal Serial Bus Device - USB DMFS DPFS USB Full Speed Data USB Full Speed Data + Analog Analog I/O Input Only USART1 Only USART1 Only USART1 Only USART1 17 32072G–11/2011 AT32UC3A3/A4 Table 3-6. Signal Name DMHS DPHS Signal Description List Function USB High Speed Data USB High Speed Data + Type Analog Analog Connect to the ground through a 6810 ohms (+/- 1%) resistor in parallel with a 10pf capacitor. If USB hi-speed feature is not required, leave this pin unconnected to save power Active Level Comments USB_VBIAS USB VBIAS reference Analog USB_VBUS VBOF ID USB VBUS signal USB VBUS on/off bus power control port ID Pin fo the USB bus Output Output Input 18 32072G–11/2011 AT32UC3A3/A4 3.4 3.4.1 I/O Line Considerations JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has no pull-up resistor. 3.4.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. 3.4.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 3.4.4 GPIO Pins All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the I/O Controller. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset State” of the I/O Controller multiplexing tables. 19 32072G–11/2011 AT32UC3A3/A4 3.5 3.5.1 Power Considerations Power Supplies The AT32UC3A3 has several types of power supply pins: • • • • VDDIO: Powers I/O lines. Voltage is 3.3V nominal VDDANA: Powers the ADC. Voltage is 3.3V nominal VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the core, memories, and peripherals. Voltage is 1.8V nominal The ground pin GNDCORE is common to VDDCORE and VDDIN. The ground pin for VDDANA is GNDANA. The ground pins for VDDIO are GNDIO. Refer to Electrical Characteristics chapter for power consumption on the various supply pins. 3.5.2 Voltage Regulator The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up to 100 mA. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDCORE and powers the core, memories and peripherals. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDCORE and GNDCORE: • One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the chip as possible. • One external 2.2µF (or 3.3µF) X7R capacitor (COUT2). Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip, e.g., two capacitors can be used in parallel (1nF NPO and 4.7µF X7R). 3.3V CIN2 CIN1 VDDIN 1.8V Regulator VDDCORE 1.8V COUT2 COUT1 For decoupling recommendations for VDDIO and VDDANA please refer to the Schematic checklist. 20 32072G–11/2011 AT32UC3A3/A4 4. Processor and Architecture Rev: 1.4.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.1 Features • 32-bit load/store AVR32A RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure Operating Systems Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extention with saturating arithmetic, and a wide variety of multiply instructions • 3-stage pipeline allows one instruction per clock cycle for most instructions – Byte, halfword, word and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection – – – – – 4.2 AVR32 Architecture AVR32 is a high-performance 32-bit RISC microprocessor architecture, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 21 32072G–11/2011 AT32UC3A3/A4 The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the Memories chapter of this data sheet. Figure 4-1 on page 23 displays the contents of AVR32UC. 22 32072G–11/2011 AT32UC3A3/A4 Figure 4-1. Interrupt controller interface Overview of the AVR32UC CPU Reset interface OCD interface OCD system Power/ Reset control AVR32UC CPU pipeline MPU Instruction memory controller High Speed Bus master High Speed Bus Data memory controller High Speed Bus slave High Speed Bus High Speed Bus master High Speed Bus 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 4-2 on page 24 shows an overview of the AVR32UC pipeline stages. CPU Local Bus Data RAM interface CPU Local Bus master 23 32072G–11/2011 AT32UC3A3/A4 Figure 4-2. The AVR32UC Pipeline MUL Multiply unit IF ID Regf ile Read A LU Regf ile w rite A LU unit Pref etch unit Decode unit Load-store unit LS 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 4.3.3 Java Support AVR32UC does not provide Java hardware acceleration. 4.3.4 Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. 4.3.5 24 32072G–11/2011 AT32UC3A3/A4 The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d Instructions with Unaligned Reference Support Supported alignment Word Word 4.3.6 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: • All SIMD instructions • All coprocessor instructions if no coprocessors are present • retj, incjosp, popjc, pushjc • tlbr, tlbs, tlbw • cache 4.3.7 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 25 32072G–11/2011 AT32UC3A3/A4 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit 0 Bit 31 The AVR32UC Register File INT0 Bit 31 Bit 0 Supervisor Bit 0 INT1 Bit 31 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Exception Bit 31 Bit 0 NMI Bit 31 Bit 0 Secure Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 4.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4 on page 26 and Figure 4-5 on page 27. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 4-4. Bit 31 The Status Register High Halfword Bit 16 - LC 1 0 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM Bit name Initial value Global Interrupt Mask Interrupt Level 0 Mask Interrupt Level 1 Mask Interrupt Level 2 Mask Interrupt Level 3 Mask Exception Mask Mode Bit 0 Mode Bit 1 Mode Bit 2 Reserved Debug State Debug State Mask Reserved 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 26 32072G–11/2011 AT32UC3A3/A4 Figure 4-5. Bit 15 The Status Register Low Halfword Bit 0 0 T 0 0 0 0 0 0 0 0 0 L 0 Q 0 V 0 N 0 Z 0 C 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 4.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2 on page 27. Table 4-2. Priority 1 2 3 4 5 6 N/A N/A Overview of Execution Modes, their Priorities and Privilege Levels. Mode Non Maskable Interrupt Exception Interrupt 3 Interrupt 2 Interrupt 1 Interrupt 0 Supervisor Application Security Privileged Privileged Privileged Privileged Privileged Privileged Privileged Unprivileged Description Non Maskable high priority interrupt mode Execute exceptions General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode Runs supervisor calls Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 4.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. 27 32072G–11/2011 AT32UC3A3/A4 All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 4-3. Reg # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 System Registers Address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 100 Name SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 JAVA_LV1 JAVA_LV2 Function Status Register Exception Vector Base Address Application Call Base Address CPU Control Register Exception Cause Register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Status Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Address Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC 28 32072G–11/2011 AT32UC3A3/A4 Table 4-3. Reg # 26 27 28 29 30 31 32 33-63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 System Registers (Continued) Address 104 108 112 116 120 124 128 132-252 256 260 264 268 272 276 280 284 288 292 296 300 304 308 312 316 320 324 328 332 336 340 344 348 352 356 360 364 Name JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA JBCR Reserved CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 MPUPSR0 MPUPSR1 MPUPSR2 MPUPSR3 Function Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Reserved for future use Configuration register 0 Configuration register 1 Cycle Counter register Compare register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Bus Error Address Register MPU Address Register region 0 MPU Address Register region 1 MPU Address Register region 2 MPU Address Register region 3 MPU Address Register region 4 MPU Address Register region 5 MPU Address Register region 6 MPU Address Register region 7 MPU Privilege Select Register region 0 MPU Privilege Select Register region 1 MPU Privilege Select Register region 2 MPU Privilege Select Register region 3 29 32072G–11/2011 AT32UC3A3/A4 Table 4-3. Reg # 92 93 94 95 96 97 98 99 100 101 102 103-191 192-255 System Registers (Continued) Address 368 372 376 380 384 388 392 396 400 404 408 448-764 768-1020 Name MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR Reserved IMPL Function MPU Privilege Select Register region 4 MPU Privilege Select Register region 5 MPU Privilege Select Register region 6 MPU Privilege Select Register region 7 Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC MPU Access Permission Register A MPU Access Permission Register B MPU Control Register Reserved for future use IMPLEMENTATION DEFINED 4.5 Exceptions and Interrupts AVR32UC incorporates a powerful exception handling scheme. The different exception sources, like Illegal Op-code and external interrupt requests, have different priority levels, ensuring a welldefined behavior when multiple exceptions are received simultaneously. Additionally, pending exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution control is passed to an event handler at an address specified in Table 4-4 on page 33. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All external interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including external interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the external interrupts and provides the autovector offset to the CPU. 4.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. 30 32072G–11/2011 AT32UC3A3/A4 The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 4.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 4-4, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete i nstruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 4.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the 31 32072G–11/2011 AT32UC3A3/A4 status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The mode bits in the status register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 4.5.5 Entry Points for Events Several different event handler entry points exists. In AVR32UC, the reset address is 0x8000_0000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All external interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an external Interrupt Controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 4-4. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floating-point unit. 32 32072G–11/2011 AT32UC3A3/A4 Table 4-4. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Priority and Handler Addresses for Events Handler Address 0x8000_0000 Provided by OCD system EVBA+0x00 EVBA+0x04 EVBA+0x08 EVBA+0x0C EVBA+0x10 Autovectored Autovectored Autovectored Autovectored EVBA+0x14 EVBA+0x50 EVBA+0x18 EVBA+0x1C EVBA+0x20 EVBA+0x24 EVBA+0x28 EVBA+0x2C EVBA+0x30 EVBA+0x100 EVBA+0x34 EVBA+0x38 EVBA+0x60 EVBA+0x70 EVBA+0x3C EVBA+0x40 EVBA+0x44 Name Reset OCD Stop CPU Unrecoverable exception TLB multiple hit Bus error data fetch Bus error instruction fetch NMI Interrupt 3 request Interrupt 2 request Interrupt 1 request Interrupt 0 request Instruction Address ITLB Miss ITLB Protection Breakpoint Illegal Opcode Unimplemented instruction Privilege violation Floating-point Coprocessor absent Supervisor call Data Address (Read) Data Address (Write) DTLB Miss (Read) DTLB Miss (Write) DTLB Protection (Read) DTLB Protection (Write) DTLB Modified Event source External input OCD system Internal MPU Data bus Data bus External input External input External input External input External input CPU MPU MPU OCD system Instruction Instruction Instruction UNUSED Instruction Instruction CPU CPU MPU MPU MPU MPU UNUSED PC of offending instruction PC of offending instruction PC of offending instruction PC(Supervisor Call) +2 PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction PC of offending instruction Stored Return Address Undefined First non-completed instruction PC of offending instruction 33 32072G–11/2011 AT32UC3A3/A4 5. Memories 5.1 Embedded Memories • Internal High-Speed Flash – 256KBytes (AT32UC3A3256/S) – 128Kbytes (AT32UC3A3128/S) – 64Kbytes (AT32UC3A364/S) • 0 wait state access at up to 36MHz in worst case conditions • 1 wait state access at up to 66MHz in worst case conditions • Pipelined Flash architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access • Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation • 100 000 write cycles, 15-year data retention capability • Sector lock capabilities, Bootloader protection, Security Bit • 32 Fuses, Erased During Chip Erase • User page for data to be preserved during Chip Erase • Internal High-Speed SRAM – 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the High Speed Bud (HSB) matrix – 2x32KBytes, accessible independently through the High Speed Bud (HSB) matrix 5.2 Physical Memory Map The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32UC Technical Architecture Manual. The 32-bit physical address space is mapped as follows: Table 5-1. AT32UC3A3A4 Physical Memory Map Size Device Start Address AT32UC3A3256S AT32UC3A3256 AT32UC3A4256S AT32UC3A4256 64KByte 256KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Size AT32UC3A3128S AT32UC3A3128 AT32UC3A4128S AT32UC3A4128 64KByte 128KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Size AT32UC3A364S AT32UC3A364 AT32UC3A464S AT32UC3A464 64KByte 64KByte 16MByte 16MByte 16MByte 16MByte 16MByte 128MByte 64KByte Embedded CPU SRAM Embedded Flash EBI SRAM CS0 EBI SRAM CS2 EBI SRAM CS3 EBI SRAM CS4 EBI SRAM CS5 EBI SRAM CS1 /SDRAM CS0 USB Data 0x00000000 0x80000000 0xC0000000 0xC8000000 0xCC000000 0xD8000000 0xDC000000 0xD0000000 0xE0000000 34 32072G–11/2011 AT32UC3A3/A4 Table 5-1. AT32UC3A3A4 Physical Memory Map Size Device Start Address AT32UC3A3256S AT32UC3A3256 AT32UC3A4256S AT32UC3A4256 32KByte 32KByte 64KByte 64KByte Size AT32UC3A3128S AT32UC3A3128 AT32UC3A4128S AT32UC3A4128 32KByte 32KByte 64KByte 64KByte Size AT32UC3A364S AT32UC3A364 AT32UC3A464S AT32UC3A464 32KByte 32KByte 64KByte 64KByte HRAMC0 HRAMC1 HSB-PB Bridge A HSB-PB Bridge B 0xFF000000 0xFF008000 0xFFFF0000 0xFFFE0000 5.3 Peripheral Address Map Peripheral Address Mapping Address 0xFF100000 Table 5-2. Peripheral Name DMACA AES USB HMATRIX FLASHC SMC SDRAMC ECCHRS BUSMON MCI MSI PDCA INTC DMA Controller - DMACA Advanced Encryption Standard - AES USB 2.0 Device and Host Interface - USB HSB Matrix - HMATRIX Flash Controller - FLASHC Static Memory Controller - SMC SDRAM Controller - SDRAMC Error code corrector Hamming and Reed Solomon ECCHRS Bus Monitor module - BUSMON Mulitmedia Card Interface - MCI Memory Stick Interface - MSI Peripheral DMA Controller - PDCA Interrupt controller - INTC 0xFFFD0000 0xFFFE0000 0xFFFE1000 0xFFFE1400 0xFFFE1C00 0xFFFE2000 0xFFFE2400 0xFFFE2800 0xFFFE4000 0xFFFE8000 0xFFFF0000 0xFFFF0800 35 32072G–11/2011 AT32UC3A3/A4 Table 5-2. Peripheral Address Mapping 0xFFFF0C00 PM RTC WDT EIC GPIO USART0 USART1 USART2 USART3 SPI0 SPI1 TWIM0 TWIM1 SSC TC0 ADC ABDAC TC1 Power Manager - PM Real Time Counter - RTC Watchdog Timer - WDT External Interrupt Controller - EIC General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART3 Serial Peripheral Interface - SPI0 Serial Peripheral Interface - SPI1 Two-wire Master Interface - TWIM0 Two-wire Master Interface - TWIM1 Synchronous Serial Controller - SSC Timer/Counter - TC0 Analog to Digital Converter - ADC Audio Bitstream DAC - ABDAC Timer/Counter - TC1 0xFFFF0D00 0xFFFF0D30 0xFFFF0D80 0xFFFF1000 0xFFFF1400 0xFFFF1800 0xFFFF1C00 0xFFFF2000 0xFFFF2400 0xFFFF2800 0xFFFF2C00 0xFFFF3000 0xFFFF3400 0xFFFF3800 0xFFFF3C00 0xFFFF4000 0xFFFF4400 36 32072G–11/2011 AT32UC3A3/A4 Table 5-2. Peripheral Address Mapping 0xFFFF5000 TWIS0 TWIS1 Two-wire Slave Interface - TWIS0 Two-wire Slave Interface - TWIS1 0xFFFF5400 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. The following GPIO registers are mapped on the local bus: Table 5-3. Port 0 Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000040 0x40000044 0x40000048 0x4000004C 0x40000050 0x40000054 0x40000058 0x4000005C 0x40000060 0x40000140 0x40000144 0x40000148 0x4000014C 0x40000150 0x40000154 0x40000158 0x4000015C 0x40000160 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) 1 Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 37 32072G–11/2011 AT32UC3A3/A4 Table 5-3. Port 2 Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000240 0x40000244 0x40000248 0x4000024C 0x40000250 0x40000254 0x40000258 0x4000025C 0x40000260 0x40000340 0x40000344 0x40000348 0x4000034C 0x40000350 0x40000354 0x40000358 0x4000035C 0x40000360 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) 3 Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 38 32072G–11/2011 AT32UC3A3/A4 6. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after powerup is controlled by the Power Manager. For specific details, refer to Section 7. ”Power Manager (PM)” on page 86. 6.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system receives a clock with the same frequency as the internal RC Oscillator. 6.2 Fetching of Initial Instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The internal Flash uses VDDIO voltage during read and write operations. It is recommended to use the BOD33 to monitor this voltage and make sure the VDDIO is above the minimum level (3.0V). The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. When powering up the device, there may be a delay before the voltage has stabilized, depending on the rise time of the supply used. The CPU can start executing code as soon as the supply is above the POR threshold, and before the supply is stable. Before switching to a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above the minimumlevel (1.62V). 39 32072G–11/2011 AT32UC3A3/A4 7. Electrical Characteristics 7.1 Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Operating Temperature.................................... -40°C to +85°C Storage Temperature ..................................... -60°C to +150°C Voltage on Input Pin with respect to Ground ........................................-0.3V to 3.6V Maximum Operating Voltage (VDDCORE) ..................... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V Total DC Output Current on all I/O Pin for TQFP144 package ................................................. 370 mA for TFBGA144 package ............................................... 370 mA 40 32072G–11/2011 AT32UC3A3/A4 7.2 DC Characteristics The following characteristics are applicable to the operating temperature range: T A = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up toTJ = 100°C. Table 7-1. Symbol VVDDIO VVDDANA DC Characteristics Parameter DC Supply Peripheral I/Os DC Analog Supply All I/O pins except TWCK, TWD, RESET_N, TCK, TDI Conditions Min. 3.0 3.0 -0.3 VVDDIO x0.7 +0.8V 2.0 3.6 Typ. Max. 3.6 3.6 +0.8 VVDDIO +0.5 Unit V V V V V V V 0.4 V VIL Input Low-level Voltage TWCK, TWD RESET_N, TCK, TDI VIH Input High-level Voltage All I/O pins except TWCK, TWD TWCK, TWD IOL = -2mA for Pin drive x1 IOL = -4mA for Pin drive x2 IOL = -8mA for Pin drive x3 IOH = 2mA for Pin drive x1 IOH = 4mA for Pin drive x2 IOH = 8mA for Pin drive x3 Pullup resistors disabled VOL Output Low-level Voltage VOH ILEAK CIN RPULLUP Output High-level Voltage Input Leakage Current Input Capacitance Pull-up Resistance Output Current Pin drive 1x Pin drive 2x Pin drive 3x Static Current VVDDIO -0.4 0.05 7 1 V µA pF 25 25 2.0 4.0 8.0 KΩ KΩ All I/O pins except RESET_N, TCK, TDI, TMS RESET_N, TCK, TDI, TMS 9 5 15 IO mA ISC On VVDDIN = 3.3V, CPU in static mode TA = 25°C TA = 85°C 30 175 µA µA 41 32072G–11/2011 AT32UC3A3/A4 7.2.1 I/O Pin Output Level Typical Characteristics Figure 7-1. 1,8 1,6 1,4 1,2 Voltage [V] 1 0,8 0,6 0,4 0,2 0 I/O Pin drive x2 Output Low Level Voltage (VOL) vs. Source Current VddIo = 3.3V 90 25 -45 0 5 10 Load current [mA] 15 20 Figure 7-2. I/O Pin drive x2 Output High Level Voltage (VOH) vs. Source Current VddIo = 3.3V 3,5 3 2,5 Voltage [V] 2 1,5 1 0,5 0 0 5 10 Load current [mA] 15 20 -45 25 90 7.3 I/O pin Characteristics These parameters are given in the following conditions: • VDDCORE = 1.8V • VDDIO = 3.3V • Ambient Temperature = 25°C 42 32072G–11/2011 AT32UC3A3/A4 Table 7-2. Symbol Normal I/O Pin Characteristics Parameter Conditions 10pf drive x2 40 18.2 7.5 2.7 6.9 13.4 3.2 8.6 16.5 drive x2 66 35.7 18.5 1.4 3.5 6.7 1.7 4.3 8.3 drive x3 100 61.6 36.3 0.9 1.9 3.5 0.9 2.26 4.3 Unit MHz MHz MHz ns ns ns ns ns ns fMAX Output frequency 30pf 60pf 10pf tRISE Rise time 30pf 60pf 10pf tFALL Fall time 30pf 60pf 7.4 Regulator characteristics Electrical Characteristics Parameter Supply voltage (input) Supply voltage (output) Maximum DC output current VVDDIN = 3.3V Conditions Min. 3.0 1.75 Typ. 3.3 1.85 Max. 3.6 1.95 100 Unit V V mA Table 7-3. Symbol VVDDIN VVDDCORE IOUT Table 7-4. Symbol CIN1 CIN2 COUT1 COUT2 Decoupling Requirements Parameter Input Regulator Capacitor 1 Input Regulator Capacitor 2 Output Regulator Capacitor 1 Output Regulator Capacitor 2 Conditions Typ. 1 4.7 470 2.2 Technology NPO X7R NPO X7R Unit nF µF pF µF 43 32072G–11/2011 AT32UC3A3/A4 7.5 7.5.1 Table 7-5. Symbol VVDDANA Analog characteristics ADC Electrical Characteristics Parameter Analog Power Supply Conditions Min. 3.0 Typ. Max. 3.6 Unit V Table 7-6. Symbol CVDDANA Decoupling Requirements Parameter Power Supply Capacitor Conditions Typ. 100 Technology NPO Unit nF 7.5.2 Table 7-7. Symbol BOD 1.8V BOD Level Values Parameter Value 00 1111b Conditions Min. Typ. 1.79 1.70 1.61 1.52 Max. Unit V V V V BODLEVEL 01 0111b 01 1111b 10 0111b Table 7-7 describes the values of the BODLEVEL field in the flash FGPFR register. Table 7-8. Symbol 3.3V BOD Level Values Parameter Value Reset value 1011 1010 1001 1000 0111 Conditions Min. Typ. 2.71 2.27 2.37 2.46 2.56 2.66 2.76 2.86 2.96 3.06 3.15 3.25 3.35 Max. Unit V V V V V V V V V V V V V BOD33LEVEL 0110 0101 0100 0011 0010 0001 0000 Table 7-8 describes the values of the BOD33.LEVEL field in the PM module 44 32072G–11/2011 AT32UC3A3/A4 Table 7-9. Symbol TBOD BOD Timing Parameter Minimum time with VDDCORE < VBOD to detect power failure Conditions Falling VDDCORE from 1.8V to 1.1V Min. Typ. 300 Max. 800 Unit ns 7.5.3 Reset Sequence Electrical Characteristics Parameter VDDIN/VDDIO rise rate to ensure power-on-reset Rising threshold voltage: voltage up to which device is kept under reset by POR on rising VDDIN Falling threshold voltage: voltage when POR resets device on falling VDDIN On falling VDDIN, voltage must go down to this value before supply can rise again to ensure reset signal is released at VPOR+ Time for Cold System Startup: Time for CPU to fetch its first instruction (RCosc not calibrated) Time for Hot System Startup: Time for CPU to fetch its first instruction (RCosc calibrated) Rising VDDIN: VRESTART -> VPOR+ Conditions Min. 0.8 Typ. Max. Unit V/ms Table 7-10. Symbol VDDRR VPOR+ 2.7 V VPOR- Falling VDDIN: 3.3V -> VPOR- 2.7 V VRESTART Falling VDDIN: 3.3V -> VRESTART 0.2 V TSSU1 480 960 µs TSSU2 420 µs 45 32072G–11/2011 AT32UC3A3/A4 Figure 7-3. VDDIN VDDIO MCU Cold Start-Up VBOD33LEVEL VRESTART VBOD33LEVEL RESET_N Internal BOD33 Reset TSSU1 Internal MCU Reset Figure 7-4. VDDIN VDDIO MCU Cold Start-Up RESET_N Externally Driven VBOD33LEVEL VRESTART VBOD33LEVEL RESET_N Internal BOD33 Reset TSSU1 Internal MCU Reset Figure 7-5. VDDIN VDDIO MCU Hot Start-Up RESET_N BOD Reset WDT Reset TSSU2 Internal MCU Reset 46 32072G–11/2011 AT32UC3A3/A4 7.5.4 RESET_N Characteristics RESET_N Waveform Parameters Parameter RESET_N minimum pulse width Conditions Min. 10 Typ. Max. Unit ns Table 7-11. Symbol tRESET 47 32072G–11/2011 AT32UC3A3/A4 7.6 Power Consumption The values in Table 7-12 and Table 7-13 on page 50 are measured values of power consumption with operating conditions as follows: •VDDIO = 3.3V •TA = 25°C •I/Os are configured in input, pull-up enabled. Figure 7-6. Measurement Setup VDDANA VDDIO Amp0 VDDIN Internal Voltage Regulator VDDCORE GNDCORE GNDPLL These figures represent the power consumption measured on the power supplies 48 32072G–11/2011 AT32UC3A3/A4 7.6.1 Power Consumtion for Different Sleep Modes Power Consumption for Different Sleep Modes Conditions(1) - CPU running a recursive Fibonacci Algorithm from flash and clocked from PLL0 at f MHz. - Voltage regulator is on. - XIN0: external clock. Xin1 Stopped. XIN32 stopped. - All peripheral clocks activated with a division by 8. - GPIOs are inactive with internal pull-up, JTAG unconnected with external pullup and Input pins are connected to GND Same conditions at 60 MHz Idle See Active mode conditions Same conditions at 60 MHz Frozen See Active mode conditions Same conditions at 60 MHz Standby See Active mode conditions Same conditions at 60 MHz - CPU running in sleep mode - XIN0, Xin1 and XIN32 are stopped. - All peripheral clocks are desactived. - GPIOs are inactive with internal pull-up, JTAG unconnected with external pullup and Input pins are connected to GND. See Stop mode conditions TA = 25 °C CPU is in static mode GPIOs on internal pull-up All peripheral clocks de-activated DM and DP pins connected to ground XIN0, Xin1 and XIN32 are stopped 1. Core frequency is generated from XIN0 using the PLL. Typ. Unit Table 7-12. Mode Active 0.626xf(MHz)+2.257 mA/MHz 40 0.349xf(MHz)+0.968 21.8 0.098xf(MHz)+1.012 6.6 0.066xf(MHz)+1.010 4.6 mA mA/MHz mA mA/MHz mA mA/MHz mA Stop 96 µA Deepstop 54 µA Static on Amp0 31 µA Notes: 49 32072G–11/2011 AT32UC3A3/A4 Table 7-13. Peripheral ADC AES ABDAC DMACA EBI EIC GPIO INTC MCI MSI PDCA SDRAM SMC SPI SSC RTC TC TWIM TWIS USART USBB WDT Typical Cuurent Consumption by Peripheral Typ. 7 80 10 70 23 0.5 37 3 40 10 20 5 9 6 10 5 8 2 2 10 90 2 µA/MHz Unit 50 32072G–11/2011 AT32UC3A3/A4 7.7 System Clock Characteristics These parameters are given in the following conditions: • VDDCORE = 1.8V • Ambient Temperature = 25°C 7.7.1 CPU/HSB Clock Characteristics Core Clock Waveform Parameters Parameter CPU Clock Frequency CPU Clock Period 15,15 Conditions Min. Typ. Max. 66 Unit MHz ns Table 7-14. Symbol 1/(tCPCPU) tCPCPU 7.7.2 PBA Clock Characteristics PBA Clock Waveform Parameters Parameter PBA Clock Frequency PBA Clock Period 15.15 Conditions Min. Typ. Max. 66 Unit MHz ns Table 7-15. Symbol 1/(tCPPBA) tCPPBA 7.7.3 PBB Clock Characteristics PBB Clock Waveform Parameters Parameter PBB Clock Frequency PBB Clock Period 15.15 Conditions Min. Typ. Max. 66 Unit MHz ns Table 7-16. Symbol 1/(tCPPBB) tCPPBB 51 32072G–11/2011 AT32UC3A3/A4 7.8 Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. 7.8.1 Slow Clock RC Oscillator RC Oscillator Frequency Parameter Conditions Calibration point: TA = 85°C FRC RC Oscillator Frequency TA = 25°C TA = -40°C 105 Min. Typ. 115.2 112 108 Max. 116 Unit KHz KHz KHz Table 7-17. Symbol 7.8.2 32 KHz Oscillator 32 KHz Oscillator Characteristics Parameter Oscillator Frequency Equivalent Load Capacitance Crystal Equivalent Series Resistance Startup Time XIN32 Clock High Half-period XIN32 Clock Low Half-period XIN32 Input Capacitance Current Consumption 1. CL is the equivalent load capacitance. Active mode Standby mode CL = 6pF CL = 12.5pF(1) 0.4 tCP 0.4 tCP (1) Table 7-18. Symbol 1/(tCP32KHz) CL ESR tST tCH tCL CIN IOSC Note: Conditions External clock on XIN32 Crystal Min. Typ. Max. 30 Unit MHz Hz 32 768 6 12.5 100 600 1200 0.6 tCP 0.6 tCP 5 1.8 0.1 pF KΩ ms pF µA µA 52 32072G–11/2011 AT32UC3A3/A4 7.8.3 Main Oscillators Main Oscillators Characteristics Parameter Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Crystal Equivalent Series Resistance Duty Cycle f = 400 KHz f = 8 MHz f = 16 MHz f = 20 MHz 0.4 tCP 0.4 tCP 7 Active mode at 400 KHz. Gain = G0 Active mode at 8 MHz. Gain = G1 Active mode at 16 MHz. Gain = G2 Active mode at 20 MHz. Gain = G3 30 45 95 205 40 50 25 4 1.4 1 0.6 tCP 0.6 tCP pF Conditions External clock on XIN Crystal 0.4 7 75 60 Min. Typ. Max. 50 20 Unit MHz MHz pF Ω % Table 7-19. Symbol 1/(tCPMAIN) CL1, CL2 ESR tST tCH tCL CIN IOSC Startup Time ms XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance Current Consumption µA 7.8.4 Phase Lock Loop PLL Characteristics Parameter VCO Output Frequency Input Frequency (after input divider) Current Consumption Active mode (Fout=80 MHz) Active mode (Fout=240 MHz) Conditions Min. 80 4 250 600 Typ. Max. 240 16 Unit MHz MHz µA µA Table 7-20. Symbol FOUT FIN IPLL 53 32072G–11/2011 AT32UC3A3/A4 7.9 ADC Characteristics Channel Conversion Time and ADC Clock Conditions 10-bit resolution mode 8-bit resolution mode Return from Idle Mode 600 ADC Clock = 5 MHz ADC Clock = 8 MHz ADC Clock = 5 MHz ADC Clock = 8 MHz 2 1.25 384 (1) 533 (2) Min. Typ. Max. 5 8 20 Unit MHz MHz µs ns µs µs kSPS kSPS Table 7-21. Parameter ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Throughput Rate 1. Corresponds to 13 clock cycles: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. 2. Corresponds to 15 clock cycles: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. Table 7-22. Parameter Current Consumption on VDDANA (1) ADC Power Consumption Conditions On 13 samples with ADC clock = 5 MHz Min. Typ. Max. 1.25 Unit mA 1. Including internal reference input current Table 7-23. Parameter Analog Inputs Conditions Min. 0 Typ. Max. VDDANA 1 7 350 850 Unit V µA pF Ohm Input Voltage Range Input Leakage Current Input Capacitance Input Resistance Table 7-24. Parameter Resolution Transfer Characteristics in 8-bit mode Conditions ADC Clock = 5 MHz ADC Clock = 8 MHz ADC Clock = 5 MHz ADC Clock = 8 MHz ADC Clock = 5 MHz ADC Clock = 8 MHz ADC Clock = 5 MHz ADC Clock = 5 MHz -0.5 -0.5 0.35 0.5 0.3 0.5 Min. Typ. 8 0.8 1.5 0.5 1.0 0.5 1.0 0.5 0.5 Max. Unit Bit LSB LSB LSB LSB LSB LSB LSB LSB Absolute Accuracy Integral Non-linearity Differential Non-linearity Offset Error Gain Error 54 32072G–11/2011 AT32UC3A3/A4 Table 7-25. Parameter Resolution Absolute Accuracy Integral Non-linearity Differential Non-linearity Offset Error Gain Error ADC Clock = 5 MHz ADC Clock = 5 MHz ADC Clock = 5 MHz ADC Clock = 2.5 MHz ADC Clock = 5 MHz ADC Clock = 5 MHz -2 -2 1.5 1 0.6 Transfer Characteristics in 10-bit mode Conditions Min. Typ. 10 3 2 2 1 2 2 Max. Unit Bit LSB LSB LSB LSB LSB LSB 7.10 7.10.1 USB Transceiver Characteristics Electrical Characteristics Electrical Parameters Parameter Recommended External USB Series Resistor VBIAS External Resistor (1) VBIAS External Capcitor Conditions In series with each USB pin with ±5% ±1% Min. Typ. 39 6810 10 Max. Unit Ω Ω pF Table 7-26. Symbol REXT RBIAS CBIAS 1. The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within the USB 2.0 electrical specifications. 7.10.2 Static Power Consumption Static Power Consumption Parameter Bias current consumption on VBG HS Transceiver and I/O current consumption Conditions Min. Typ. Max. 1 8 If cable is connected, add 200µA (typical) due to Pull-up/Pull-down current consumption Unit µA µA Table 7-27. Symbol IBIAS IVDDUTMI FS/HS Transceiver and I/O current consumption 3 µA 7.10.3 Dynamic Power Consumption Dynamic Power Consumption Parameter Bias current consumption on VBG Conditions Min. Typ. 0.7 Max. 0.8 Unit mA Table 7-28. Symbol IBIAS 55 32072G–11/2011 AT32UC3A3/A4 Table 7-28. Symbol Dynamic Power Consumption Parameter HS Transceiver current consumption HS Transceiver current consumption FS/HS Transceiver current consumption FS/HS Transceiver current consumption FS/HS Transceiver current consumption Conditions HS transmission HS reception FS transmission 0m cable (1) FS transmission 5m cable FS reception Min. Typ. 47 18 4 26 3 Max. 60 27 6 30 4.5 Unit mA mA mA mA mA IVDDUTMI 1. Including 1 mA due to Pull-up/Pull-down current consumption. 34.5.5 USB High Speed Design Guidelines In order to facilitate hardware design, Atmel provides an application note on www.atmel.com. 56 32072G–11/2011 AT32UC3A3/A4 7.11 7.11.1 EBI Timings SMC Signals These timings are given for worst case process, T = 85 ⋅ C, VDDIO = 3V and 40 pF load capacitance. Table 7-29. Symbol 1/(tCPSMC) Note: SMC Clock Signal Parameter SMC Controller Clock Frequency Max.(1) 1/(tcpcpu) Unit MHz 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB. Table 7-30. Symbol SMC Read Signals with Hold Settings Parameter NRD Controlled (READ_MODE = 1) Min. Unit SMC1 SMC2 SMC3 SMC4 SMC5 SMC7 SMC8 SMC9 SMC10 SMC11 SMC12 SMC13 SMC14 SMC16 SMC17 SMC18 Note: Data Setup before NRD High Data Hold after NRD High NRD High to NBS0/A0 Change(1) NRD High to NBS1 Change (1) (1) 12 0 nrd hold length * tCPSMC - 1.3 ns ns ns ns ns ns ns ns nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 (nrd hold length - ncs rd hold length) * tCPSMC - 2.3 nrd pulse length * tCPSMC - 1.4 NRD Controlled (READ_MODE = 0) 11.5 0 (1) (1) NRD High to NBS2/A1 Change NRD High to A2 - A23 Change(1) NRD High to NCS Inactive NRD Pulse Width (1) Data Setup before NCS High Data Hold after NCS High NCS High to NBS0/A0 Change NCS High to NBS0/A0 Change ns ns ns ns ns ns ns ns ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 4 ncs rd hold length - nrd hold length)* tCPSMC - 1.3 ncs rd pulse length * tCPSMC - 3.6 NCS High to NBS2/A1 Change(1) NCS High to A2 - A23 Change(1) NCS High to NRD Inactive NCS Pulse Width (1) 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”. 57 32072G–11/2011 AT32UC3A3/A4 Table 7-31. Symbol SMC Read Signals with no Hold Settings Parameter NRD Controlled (READ_MODE = 1) Min. Unit SMC19 SMC20 SMC21 SMC22 Data Setup before NRD High Data Hold after NRD High NRD Controlled (READ_MODE = 0) Data Setup before NCS High Data Hold after NCS High 13.7 1 ns ns 13.3 0 ns ns Table 7-32. Symbol SMC Write Signals with Hold Settings Parameter NRD Controlled (READ_MODE = 1) Min. Unit SMC23 SMC24 SMC25 SMC26 SMC29 SMC31 SMC32 SMC33 SMC34 SMC35 SMC36 Note: Data Out Valid before NWE High Data Out Valid after NWE High(1) NWE High to NBS0/A0 Change NWE High to NBS1 Change NWE High to A1 Change (1) (1) (1) (nwe pulse length - 1) * tCPSMC - 0.9 nwe hold length * tCPSMC - 6 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.7 (nwe hold length - ncs wr hold length)* tCPSMC - 2.9 nwe pulse length * tCPSMC - 0.9 ns ns ns ns ns ns ns ns NWE High to A2 - A23 Change(1) NWE High to NCS Inactive NWE Pulse Width (1) NRD Controlled (READ_MODE = 0) Data Out Valid before NCS High Data Out Valid after NCS High(1) NCS High to NWE Inactive (1) (ncs wr pulse length - 1)* tCPSMC - 4.6 ncs wr hold length * tCPSMC - 5.8 (ncs wr hold length - nwe hold length)* tCPSMC - 0.6 ns ns ns 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “nwe hold length" Table 7-33. Symbol SMC37 SMC38 SMC39 SMC40 SMC41 SMC42 SMC Write Signals with No Hold Settings (NWE Controlled only) Parameter NWE Rising to A2-A25 Valid NWE Rising to NBS0/A0 Valid NWE Rising to NBS1 Change NWE Rising to A1/NBS2 Change NWE Rising to NBS3 Change NWE Rising to NCS Rising Min. 5.4 5 5 5 5 5.1 Unit ns ns ns ns ns ns 58 32072G–11/2011 AT32UC3A3/A4 Table 7-33. Symbol SMC43 SMC44 SMC45 SMC Write Signals with No Hold Settings (NWE Controlled only) Parameter Data Out Valid before NWE Rising Data Out Valid after NWE Rising NWE Pulse Width Min. (nwe pulse length - 1) * tCPSMC - 1.2 5 nwe pulse length * tCPSMC - 0.9 Unit ns ns ns Figure 7-7. SMC Signals for NCS Controlled Accesses. SMC16 SMC16 SMC16 A2-A25 SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15 A0/A1/NBS[3:0] NRD SMC17 SMC17 NCS SMC18 SMC22 SMC18 SMC18 SMC21 SMC10 SMC11 SMC34 SMC35 D0 - D15 SMC36 NWE 59 32072G–11/2011 AT32UC3A3/A4 Figure 7-8. A2-A25 SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 SMC25 SMC26 SMC29 SMC30 SMC Signals for NRD and NRW Controlled Accesses. SMC7 SMC37 SMC7 SMC31 A0/A1/NBS[3:0] SMC42 SMC8 SMC32 NCS SMC8 NRD SMC9 SMC9 SMC19 SMC20 SMC43 SMC44 SMC1 SMC2 SMC23 SMC24 D0 - D15 SMC45 SMC33 NWE 7.11.2 SDRAM Signals These timings are given for 10 pF load on SDCK and 40 pF on other signals. SDRAM Clock Signal. Parameter SDRAM Controller Clock Frequency Conditions Min. Max.(1) 1/(tcpcpu) Unit MHz Table 7-34. Symbol 1/(tCPSDCK) Note: 1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB. Table 7-35. Symbol SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 SDRAMC9 SDRAMC10 SDRAMC11 SDRAMC12 SDRAM Clock Signal Parameter SDCKE High before SDCK Rising Edge SDCKE Low after SDCK Rising Edge SDCKE Low before SDCK Rising Edge SDCKE High after SDCK Rising Edge SDCS Low before SDCK Rising Edge SDCS High after SDCK Rising Edge RAS Low before SDCK Rising Edge RAS High after SDCK Rising Edge SDA10 Change before SDCK Rising Edge SDA10 Change after SDCK Rising Edge Address Change before SDCK Rising Edge Address Change after SDCK Rising Edge Conditions Min. 7.4 3.2 7 2.9 7.5 1.6 7.2 2.3 7.6 1.9 6.2 2.2 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns 60 32072G–11/2011 AT32UC3A3/A4 Table 7-35. Symbol SDRAMC13 SDRAMC14 SDRAMC15 SDRAMC16 SDRAMC17 SDRAMC18 SDRAMC19 SDRAMC20 SDRAMC23 SDRAMC24 SDRAMC25 SDRAMC26 SDRAM Clock Signal Parameter Bank Change before SDCK Rising Edge Bank Change after SDCK Rising Edge CAS Low before SDCK Rising Edge CAS High after SDCK Rising Edge DQM Change before SDCK Rising Edge DQM Change after SDCK Rising Edge D0-D15 in Setup before SDCK Rising Edge D0-D15 in Hold after SDCK Rising Edge SDWE Low before SDCK Rising Edge SDWE High after SDCK Rising Edge D0-D15 Out Valid before SDCK Rising Edge D0-D15 Out Valid after SDCK Rising Edge Conditions Min. 6.3 2.4 7.4 1.9 6.4 2.2 9 0 7.6 1.8 7.1 1.5 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns 61 32072G–11/2011 AT32UC3A3/A4 Figure 7-9. SDRAMC Signals relative to SDCK. SDCK SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDCKE SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDCS SDRAMC7 SDRAMC8 RAS SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16 CAS SDRAMC23 SDRAMC24 SDWE SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDA10 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 A0 - A9, A11 - A13 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 BA0/BA1 SDRAMC17 SDRAMC18 SDRAMC17 SDRAMC18 DQM0 DQM3 SDRAMC19 SDRAMC20 D0 - D15 Read SDRAMC25 SDRAMC26 D0 - D15 to Write 62 32072G–11/2011 AT32UC3A3/A4 7.12 7.12.1 JTAG Characteristics JTAG Interface Signals JTAG Interface Timing Specification Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time TCK to Device Outputs Valid Conditions (1) Min. 6 3 9 1 0 4 6 Max. Unit ns ns ns ns ns ns ns ns ns ns ns Table 7-36. Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF 63 32072G–11/2011 AT32UC3A3/A4 Figure 7-10. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8 Device Outputs JTAG9 JTAG10 7.13 SPI Characteristics Figure 7-11. SPI Master mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK SPI0 MISO SPI1 SPI2 MOSI 64 32072G–11/2011 AT32UC3A3/A4 Figure 7-12. SPI Master mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK SPI3 MISO SPI4 SPI5 MOSI Figure 7-13. SPI Slave mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK SPI6 MISO SPI7 MOSI SPI8 Figure 7-14. SPI Slave mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK SPI9 MISO SPI10 MOSI SPI11 65 32072G–11/2011 AT32UC3A3/A4 Table 7-37. Symbol SPI0 SPI1 SPI2 SPI3 SPI4 SPI5 SPI6 SPI7 SPI8 SPI9 SPI10 SPI11 SPI Timings Parameter MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) SPCK rising to MOSI Delay (master) MISO Setup time before SPCK falls (master) MISO Hold time after SPCK falls (master) SPCK falling to MOSI Delay master) SPCK falling to MISO Delay (slave) MOSI Setup time before SPCK rises (slave) MOSI Hold time after SPCK rises (slave) SPCK rising to MISO Delay (slave) MOSI Setup time before SPCK falls (slave) MOSI Hold time after SPCK falls (slave) Conditions (1) 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 0 1 0 1.5 27 22 + (tCPMCK)/2 (3) 0 7 26.5 Min. 22 + (tCPMCK)/2 (2) 0 7 Max. Unit ns ns ns ns ns ns ns ns ns ns ns ns 1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF 2. tCPMCK: Master Clock period in ns. 3. tCPMCK: Master Clock period in ns. 7.14 MCI The High Speed MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V4.2, the SD Memory Card Specification V2.0, the SDIO V1.1 specification and CE-ATA V1.1. 66 32072G–11/2011 AT32UC3A3/A4 7.15 Flash Memory Characteristics The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory. Flash operating frequency equals the CPU/HSB frequency. Table 7-38. Symbol FFOP Flash Operating Frequency Parameter Flash Operating Frequency Conditions FWS = 0 FWS = 1 Min. Typ. Max. 36 66 Unit MHz MHz Table 7-39. Symbol TFPP TFFP TFCE Parts Programming Time Parameter Page Programming Time Fuse Programming Time Chip erase Time Conditions Min. Typ. 5 0.5 8 Max. Unit ms ms ms Table 7-40. Symbol NFARRAY NFFUSE TFDR Flash Parameters Parameter Flash Array Write/Erase cycle General Purpose Fuses write cycle Flash Data Retention Time 15 Conditions Min. Typ. Max. 100K 1000 Unit cycle cycle year 67 32072G–11/2011 AT32UC3A3/A4 8. Mechanical Characteristics 8.1 8.1.1 Thermal Considerations Thermal Data Table 8-1 summarizes the thermal resistance data depending on the package. Table 8-1. Symbol θJA θJC θJA θJC θJA θJC Thermal Resistance Data Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance Still Air Still Air Condition Still Air Package TQFP144 TQFP144 TFBGA144 TFBGA144 VFBGA100 VFBGA100 Typ 40.3 9.5 28.5 6.9 31.1 6.9 Unit °C/W °C/W °C/W 8.1.2 Junction Temperature The average chip-junction temperature, TJ, in °C can be obtained from the following: 1. 2. T J = T A + ( P D × θ JA ) T J = T A + ( P D × ( θ HEATSINK + θ JC ) ) where: • θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 8-1 on page 68. • θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 8-1 on page 68. • θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet. • PD = device power consumption (W) estimated from data provided in the section ”Regulator characteristics” on page 43. • TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. 68 32072G–11/2011 AT32UC3A3/A4 8.2 Package Drawings Figure 8-1. TFBGA 144 package drawing 69 32072G–11/2011 AT32UC3A3/A4 Figure 8-2. LQFP-144 package drawing Table 8-2. 1300 Device and Package Maximum Weight mg Table 8-3. Package Characteristics MSL3 Moisture Sensitivity Level Table 8-4. Package Reference MS-026 E3 JEDEC Drawing Reference JESD97 Classification 70 32072G–11/2011 AT32UC3A3/A4 Figure 8-3. VFBGA-100 package drawing 71 32072G–11/2011 AT32UC3A3/A4 8.3 Soldering Profile Table 8-5 gives the recommended soldering profile from J-STD-20. Table 8-5. Soldering Profile Green Package 3°C/Second max 150-200°C 60-150 seconds 30 seconds 260 (+0/-5°C) 6°C/Second max. 8 minutes max Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Time Maintained Above 217°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature Note: It is recommended to apply a soldering temperature higher than 250°C. A maximum of three reflow passes is allowed per component. 72 32072G–11/2011 AT32UC3A3/A4 9. Ordering Information Device AT32UC3A3256S Ordering Code AT32UC3A3256S-ALUT AT32UC3A3256S-ALUR AT32UC3A3256S-CTUT AT32UC3A3256S-CTUR AT32UC3A3256 AT32UC3A3256-ALUT AT32UC3A3256-ALUR AT32UC3A3256-CTUT AT32UC3A3256-CTUR AT32UC3A3128S AT32UC3A3128S-ALUT AT32UC3A3128S-ALUR AT32UC3A3128S-CTUT AT32UC3A3128S-CTUR AT32UC3A3128 AT32UC3A3128-ALUT AT32UC3A3128-ALUR AT32UC3A3128-CTUT AT32UC3A3128-CTUR AT32UC3A364S AT32UC3A364S-ALUT AT32UC3A364S-ALUR AT32UC3A364S-CTUT AT32UC3A364S-CTUR AT32UC3A364 AT32UC3A364-ALUT AT32UC3A364-ALUR AT32UC3A364-CTUT AT32UC3A364-CTUR AT32UC3A4256S AT32UC3A4256 AT32UC3A4128S AT32UC3A4128 AT32UC3A464S AT32UC3A464 AT32UC3A4256S-C1UT AT32UC3A4256S-C1UR AT32UC3A4256-C1UT AT32UC3A4256-C1UR AT32UC3A4128S-C1UT AT32UC3A4128S-C1UR AT32UC3A4128-C1UT AT32UC3A4128-C1UR AT32UC3A464S-C1UT AT32UC3A464S-C1UR AT32UC3A464-C1UT AT32UC3A464-C1UR Package 144-lead LQFP 144-lead LQFP 144-ball TFBGA 144-ball TFBGA 144-lead LQFP 144-lead LQFP 144-ball TFBGA 144-ball TFBGA 144-lead LQFP 144-lead LQFP 144-ball TFBGA 144-ball TFBGA 144-lead LQFP 144-lead LQFP 144-ball TFBGA 144-ball TFBGA 144-lead LQFP 144-lead LQFP 144-ball TFBGA 144-ball TFBGA 144-lead LQFP 144-lead LQFP 144-ball TFBGA 144-ball TFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA 100-ball VFBGA Conditioning Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Tray Reels Temperature Operating Range Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) Industrial (-40⋅C to 85⋅C) 73 32072G–11/2011 AT32UC3A3/A4 10. Errata 10.1 10.1.1 Rev. H General DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal CTLx.DST_TR_WIDTH Fix/Workaround For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH. to 10.1.2 Processor and Architecture LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock and not PBA Clock / 128. Fix/Workaround None. MPU Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. Fix/Workaround Make a DTLB Protection (Write) exception handler which permits the interrupt request to be handled in privileged mode. 10.1.3 USB UPCFGn.INTFRQ is irrelevant for isochronous pipe As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or every 125uS (High Speed). Fix/Workaround For higher polling time, the software must freeze the pipe for the desired period in order to prevent any "extra" token. 74 32072G–11/2011 AT32UC3A3/A4 10.1.4 ADC Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 10.1.5 USART ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None. The LIN ID is not transmitted in mode PDCM='0' Fix/Workaround Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first address of the transmit buffer is not used. The LINID must be written in the LINIR register, after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register will start the transfer whenever the PDCA transfer is ready. The LINID interrupt is only available for the header reception and not available for the header transmission Fix/Workaround None. USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set to 1 If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never starts. Fix/Workaround Only use PDCM=0 configuration with the PDCA transfer. SPI SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. 75 32072G–11/2011 AT32UC3A3/A4 Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. Power Manager Clock sources will not be stopped in STATIC sleep mode if the difference between CPU and PBx division factor is too high If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going to a sleep mode where the system RC oscillator is turned off, then high speed clock sources will not be turned off. This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where the system RC oscillator is stopped, make sure that the factor between the CPU/HSB and PBx frequencies is less than or equal to 4. 10.1.6 PDCA PCONTROL.CHxRES is non-functional PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be reset by software. Fix/Workaround Software needs to keep history of performance counters. Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface. Fix/Workaround Disable and then enable the peripheral after the transfer error. AES URAD (Unspecified Register Access Detection Status) does not detect read accesses to the write-only KEYW[5..8]R registers Fix/Workaround None. 10.1.7 HMATRIX In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers. Fix/Workaround Mask undefined bits when reading PRAS and PRBS. 76 32072G–11/2011 AT32UC3A3/A4 10.1.8 TWIM TWIM SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This does not cause any problem just by itself, but can cause a problem if software waits for SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS. Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP condition will not be transmitted correctly. Fix/Workaround If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there must be a software delay of at least two TWCK periods between the detection of SR.IDLE==1 and the disabling of the TWIM. TWIM TWALM polarity is wrong The TWALM signal in the TWIM is active high instead of active low. Fix/Workaround Use an external inverter to invert the signal going into the TWIM. When using both TWIM and TWIS on the same pins, the TWALM cannot be used. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. TWIS Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. TWIS stretch on Address match error When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD at the same time. This can cause a TWI timing violation. Fix/Workaround None. SSC Frame Synchro and Frame Synchro Data are delayed by one clock cycle The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when: - Clock is CKDIV - The START is selected on either a frame synchro edge or a level - Frame synchro data is enabled - Transmit clock is gated on output (through CKO field) Fix/Workaround Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START condition is performed on a generated frame synchro. 77 32072G–11/2011 AT32UC3A3/A4 10.1.9 FLASHC Corrupted read in flash may happen after fuses write or erase operations (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands) After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI. After these commands, read 3 times one flash page initialized to 00h. Disable the flash high speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the flash. 10.2 10.2.1 Rev. E General Increased Power Consumption in VDDIO in sleep modes If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is disabled, this will lead to an increased power consumption in VDDIO. Fix/Workaround Disable the OSC0 through the System Control Interface (SCIF) before going to any sleep mode where the OSC0 is disabled, or pull down or up XIN0 and XOUT0 with 1 Mohm resistor. Power consumption in static mode The power consumption in static mode can be up to 330µA on some parts (typical at 25°C) Fix/Workaround Set to 1b bit CORRS4 of the ECCHRS mode register (MD). In C-code: *((volatile int*) (0xFFFE2404))= 0x400. DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal CTLx.DST_TR_WIDTH Fix/Workaround For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH. 3.3V supply monitor is not available FGPFRLO[30:29] are reserved and should not be used by the application. Fix/Workaround None. Service access bus (SAB) can not access DMACA registers Fix/Workaround None. Processor and Architecture LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. to 78 32072G–11/2011 AT32UC3A3/A4 Fix/Workaround None. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock and not PBA Clock / 128. Fix/Workaround None. MPU Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. Fix/Workaround Make a DTLB Protection (Write) exception handler which permits the interrupt request to be handled in privileged mode. 10.2.2 USB UPCFGn.INTFRQ is irrelevant for isochronous pipe As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or every 125uS (High Speed). Fix/Workaround For higher polling time, the software must freeze the pipe for the desired period in order to prevent any "extra" token. 10.2.3 ADC Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 10.2.4 USART ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None. The LIN ID is not transmitted in mode PDCM='0' Fix/Workaround Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first address of the transmit buffer is not used. The LINID must be written in the LINIR register, 79 32072G–11/2011 AT32UC3A3/A4 after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register will start the transfer whenever the PDCA transfer is ready. The LINID interrupt is only available for the header reception and not available for the header transmission Fix/Workaround None. USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set to 1 If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never starts. Fix/Workaround Only use PDCM=0 configuration with the PDCA transfer. The RTS output does not function correctly in hardware handshaking mode The RTS signal is not generated properly when the USART receives data in hardware handshaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output should go high, but it will stay low. Fix/Workaround Do not use the hardware handshaking mode of the USART. If it is necessary to drive the RTS output high when the Peripheral DMA receive buffer becomes full, use the normal mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the USART Control Register (CR). This will drive the RTS output high. After the next DMA transfer is started and a receive buffer is available, write a one to the RTSEN bit in the USART CR so that RTS will be driven low. ISO7816 Mode T1: RX impossible after any TX RX impossible after any TX. Fix/Workaround SOFT_RESET on RX+ Config US_MR + Config_US_CR. SPI SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. 80 32072G–11/2011 AT32UC3A3/A4 Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. Power Manager Clock sources will not be stopped in STATIC sleep mode if the difference between CPU and PBx division factor is too high If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going to a sleep mode where the system RC oscillator is turned off, then high speed clock sources will not be turned off. This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where the system RC oscillator is stopped, make sure that the factor between the CPU/HSB and PBx frequencies is less than or equal to 4. 10.2.5 PDCA PCONTROL.CHxRES is non-functional PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be reset by software. Fix/Workaround Software needs to keep history of performance counters. Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface. Fix/Workaround Disable and then enable the peripheral after the transfer error. AES URAD (Unspecified Register Access Detection Status) does not detect read accesses to the write-only KEYW[5..8]R registers Fix/Workaround None. 10.2.6 HMATRIX In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers. Fix/Workaround Mask undefined bits when reading PRAS and PRBS. 81 32072G–11/2011 AT32UC3A3/A4 10.2.7 TWIM TWIM SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This does not cause any problem just by itself, but can cause a problem if software waits for SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS. Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP condition will not be transmitted correctly. Fix/Workaround If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there must be a software delay of at least two TWCK periods between the detection of SR.IDLE==1 and the disabling of the TWIM. TWIM TWALM polarity is wrong The TWALM signal in the TWIM is active high instead of active low. Fix/Workaround Use an external inverter to invert the signal going into the TWIM. When using both TWIM and TWIS on the same pins, the TWALM cannot be used. SMBALERT bit may be set after reset The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after system reset. Fix/Workaround After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer. TWIS Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. TWIS stretch on Address match error When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD at the same time. This can cause a TWI timing violation. Fix/Workaround None. MCI MCI_CLK features is not available on PX12, PX13 and PX40 Fix/Workaround MCI_CLK feature is available on PA27 only. The busy signal of the responses R1b is not taken in account (excepting for CMD12 STOP_TRANSFER) It is not possible to know the busy status of the card during the response (R1b) for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56. 82 32072G–11/2011 AT32UC3A3/A4 Fix/Workaround The card busy line should be polled through the GPIO pin for commands CMD7, CMD28, CMD29, CMD38, CMD42 and CMD56. The GPIO alternate configuration should be restored after. SSC Frame Synchro and Frame Synchro Data are delayed by one clock cycle The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when: - Clock is CKDIV - The START is selected on either a frame synchro edge or a level - Frame synchro data is enabled - Transmit clock is gated on output (through CKO field) Fix/Workaround Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START condition is performed on a generated frame synchro. 10.2.8 FLASHC Corrupted read in flash may happen after fuses write or erase operations (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands) After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI. After these commands, read 3 times one flash page initialized to 00h. Disable the flash high speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the flash. 10.3 10.3.1 Rev. D General DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal CTLx.DST_TR_WIDTH Fix/Workaround For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH. 3.3V supply monitor is not available FGPFRLO[30:29] are reserved and should not be used by the application. Fix/Workaround None. Service access bus (SAB) can not access DMACA registers Fix/Workaround None. Processor and Architecture to 83 32072G–11/2011 AT32UC3A3/A4 LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. Hardware breakpoints may corrupt MAC results Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC instruction. Fix/Workaround Place breakpoints on earlier or later instructions. When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock and not PBA Clock / 128. Fix/Workaround None. RETE instruction does not clear SREG[L] from interrupts The RETE instruction clears SREG[L] as expected from exceptions. Fix/Workaround When using the STCOND instruction, clear SREG[L] in the stacked value of SR before returning from interrupts with RETE. RETS behaves incorrectly when MPU is enabled RETS behaves incorrectly when MPU is enabled and MPU is configured so that system stack is not readable in unprivileged mode. Fix/Workaround Make system stack readable in unprivileged mode, or return from supervisor mode using rete instead of rets. This requires: 1. Changing the mode bits from 001 to 110 before issuing the instruction. Updating the mode bits to the desired value must be done using a single mtsr instruction so it is done atomically. Even if this step is generally described as not safe in the UC technical reference manual, it is safe in this very specific case. 2. Execute the RETE instruction. In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers. Fix/Workaround Mask undefined bits when reading PRAS and PRBS. Multiply instructions do not work on RevD All the multiply instructions do not work. Fix/Workaround Do not use the multiply instructions. MPU Privilege violation when using interrupts in application mode with protected system stack If the system stack is protected by the MPU and an interrupt occurs in application mode, an MPU DTLB exception will occur. 84 32072G–11/2011 AT32UC3A3/A4 Fix/Workaround Make a DTLB Protection (Write) exception handler which permits the interrupt request to be handled in privileged mode. 10.3.2 USB UPCFGn.INTFRQ is irrelevant for isochronous pipe As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or every 125uS (High Speed). Fix/Workaround For higher polling time, the software must freeze the pipe for the desired period in order to prevent any "extra" token. 10.3.3 ADC Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 10.3.4 USART ISO7816 info register US_NER cannot be read The NER register always returns zero. Fix/Workaround None. The LIN ID is not transmitted in mode PDCM='0' Fix/Workaround Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first address of the transmit buffer is not used. The LINID must be written in the LINIR register, after the configuration and start of the PDCA transfer. Writing the LINID in the LINIR register will start the transfer whenever the PDCA transfer is ready. The LINID interrupt is only available for the header reception and not available for the header transmission Fix/Workaround None. USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set to 1 If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never starts. Fix/Workaround Only use PDCM=0 configuration with the PDCA transfer. The RTS output does not function correctly in hardware handshaking mode The RTS signal is not generated properly when the USART receives data in hardware handshaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output should go high, but it will stay low. Fix/Workaround Do not use the hardware handshaking mode of the USART. If it is necessary to drive the RTS output high when the Peripheral DMA receive buffer becomes full, use the normal 85 32072G–11/2011 AT32UC3A3/A4 mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when the receive buffer is full. In the interrupt handler code, write a one to the RTSDIS bit in the USART Control Register (CR). This will drive the RTS output high. After the next DMA transfer is started and a receive buffer is available, write a one to the RTSEN bit in the USART CR so that RTS will be driven low. ISO7816 Mode T1: RX impossible after any TX RX impossible after any TX. Fix/Workaround SOFT_RESET on RX+ Config US_MR + Config_US_CR. SPI SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0 When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI module will not start a data transfer. Fix/Workaround Disable mode fault detection by writing a one to MR.MODFDIS. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. Power Manager Clock sources will not be stopped in STATIC sleep mode if the difference between CPU and PBx division factor is too high If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going to a sleep mode where the system RC oscillator is turned off, then high speed clock sources will not be turned off. This will result in a significantly higher power consumption during the sleep mode. Fix/Workaround Before going to sleep modes where the system RC oscillator is stopped, make sure that the factor between the CPU/HSB and PBx frequencies is less than or equal to 4. 86 32072G–11/2011 AT32UC3A3/A4 10.3.5 PDCA PCONTROL.CHxRES is non-functional PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be reset by software. Fix/Workaround Software needs to keep history of performance counters. Transfer error will stall a transmit peripheral handshake interface If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral handshake of the active channel will stall and the PDCA will not do any more transfers on the affected peripheral handshake interface. Fix/Workaround Disable and then enable the peripheral after the transfer error. AES URAD (Unspecified Register Access Detection Status) does not detect read accesses to the write-only KEYW[5..8]R registers Fix/Workaround None. 10.3.6 HMATRIX In the PRAS and PRBS registers, the MxPR fields are only two bits In the PRAS and PRBS registers, the MxPR fields are only two bits wide, instead of four bits. The unused bits are undefined when reading the registers. Fix/Workaround Mask undefined bits when reading PRAS and PRBS. 10.3.7 TWIM TWIM SR.IDLE goes high immediately when NAK is received When a NAK is received and there is a non-zero number of bytes to be transmitted, SR.IDLE goes high immediately and does not wait for the STOP condition to be sent. This does not cause any problem just by itself, but can cause a problem if software waits for SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS. Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP condition will not be transmitted correctly. Fix/Workaround If possible, do not disable the TWIM. If it is absolutely necessary to disable the TWIM, there must be a software delay of at least two TWCK periods between the detection of SR.IDLE==1 and the disabling of the TWIM. TWIM TWALM polarity is wrong The TWALM signal in the TWIM is active high instead of active low. Fix/Workaround Use an external inverter to invert the signal going into the TWIM. When using both TWIM and TWIS on the same pins, the TWALM cannot be used. TWIS TWIS Version Register reads zero TWIS Version Register (VR) reads zero instead of 0x112. 87 32072G–11/2011 AT32UC3A3/A4 Fix/Workaround None. 10.3.8 MCI The busy signal of the responses R1b is not taken in account (excepting for CMD12 STOP_TRANSFER) It is not possible to know the busy status of the card during the response (R1b) for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56. Fix/Workaround The card busy line should be polled through the GPIO pin for commands CMD7, CMD28, CMD29, CMD38, CMD42 and CMD56. The GPIO alternate configuration should be restored after. 10.3.9 SSC Frame Synchro and Frame Synchro Data are delayed by one clock cycle The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when: - Clock is CKDIV - The START is selected on either a frame synchro edge or a level - Frame synchro data is enabled - Transmit clock is gated on output (through CKO field) Fix/Workaround Transmit or receive CLOCK must not be gated (by the mean of CKO field) when START condition is performed on a generated frame synchro. 10.3.10 FLASHC Corrupted read in flash may happen after fuses write or erase operations (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands) After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI. After these commands, read 3 times one flash page initialized to 00h. Disable the flash high speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the flash. 88 32072G–11/2011 AT32UC3A3/A4 11. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 11.1 Rev. G– 11/11 1. Add recommandation for MCI connection with more than 1 slot 11.2 Rev. F – 08/11 1. Final version 11.3 Rev. E – 06/11 1. 2. Updated Errata for E and D Updated FLASHC chapter with HSEN and HSDIS commands 11.4 Rev. D – 04/11 1. 2. 3. 4. Updated Errata for revision H and E Updated Reset Sequence Updated Peripherals’ current consumption and others minor electrical charateristics Updated Peripherals chapters 11.5 Rev. C – 03/10 1. Updated the datasheet with new revision H features. 11.6 Rev. B – 08/09 1. Updated the datasheet with new device AT32UC3A4. 11.7 Rev. A – 03/09 1. Initial revision. 89 32072G–11/2011 AT32UC3A3/A4 1 2 Description ............................................................................................... 3 Overview ................................................................................................... 4 2.1 2.2 Block Diagram ...................................................................................................4 Configuration Summary .....................................................................................5 3 Package and Pinout ................................................................................. 6 3.1 3.2 3.3 3.4 3.5 Package .............................................................................................................6 Peripheral Multiplexing on I/O lines ...................................................................9 Signal Descriptions ..........................................................................................14 I/O Line Considerations ...................................................................................19 Power Considerations .....................................................................................20 4 Processor and Architecture .................................................................. 21 4.1 4.2 4.3 4.4 4.5 Features ..........................................................................................................21 AVR32 Architecture .........................................................................................21 The AVR32UC CPU ........................................................................................22 Programming Model ........................................................................................26 Exceptions and Interrupts ................................................................................30 5 Memories ................................................................................................ 34 5.1 5.2 5.3 5.4 Embedded Memories ......................................................................................34 Physical Memory Map .....................................................................................34 Peripheral Address Map ..................................................................................35 CPU Local Bus Mapping .................................................................................37 6 Boot Sequence ....................................................................................... 39 6.1 6.2 Starting of Clocks ............................................................................................39 Fetching of Initial Instructions ..........................................................................39 7 Electrical Characteristics ...................................................................... 40 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 Absolute Maximum Ratings* ...........................................................................40 DC Characteristics ...........................................................................................41 I/O pin Characteristics .....................................................................................42 Regulator characteristics .................................................................................43 Analog characteristics .....................................................................................44 Power Consumption ........................................................................................48 System Clock Characteristics ..........................................................................51 Oscillator Characteristics .................................................................................52 ADC Characteristics ........................................................................................54 90 32072G–11/2011 AT32UC3A3/A4 7.10 7.11 7.12 7.13 7.14 7.15 USB Transceiver Characteristics .....................................................................55 EBI Timings .....................................................................................................57 JTAG Characteristics .......................................................................................63 SPI Characteristics ..........................................................................................64 MCI ..................................................................................................................66 Flash Memory Characteristics .........................................................................67 8 Mechanical Characteristics ................................................................... 68 8.1 8.2 8.3 Thermal Considerations ..................................................................................68 Package Drawings ...........................................................................................69 Soldering Profile ..............................................................................................72 9 Ordering Information ............................................................................. 73 10 Errata ....................................................................................................... 74 10.1 10.2 10.3 Rev. H ..............................................................................................................74 Rev. E ..............................................................................................................78 Rev. D ..............................................................................................................83 11 Datasheet Revision History .................................................................. 89 11.1 11.2 11.3 11.4 11.5 11.6 11.7 Rev. G– 11/11 .................................................................................................89 Rev. F – 08/11 .................................................................................................89 Rev. E – 06/11 .................................................................................................89 Rev. D – 04/11 .................................................................................................89 Rev. C – 03/10 .................................................................................................89 Rev. B – 08/09 .................................................................................................89 Rev. A – 03/09 .................................................................................................89 91 32072G–11/2011