AT32UC3L016-AUT

Features • High Performance, Low Power AVR®32 UC 32-bit Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instructions – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performance • Up to 64 DMIPS Running at 50MHz from Flash (1 Flash Wait State) • Up to 36 DMIPS Running at 25MHz from Flash (0 Flash Wait State) – Memory Protection Unit picoPower™ Technology for Ultra-Low Power Consumption Multi-Hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 12 Peripheral DMA Channels Improve Speed for Peripheral Communication Internal High-Speed Flash – 64Kbytes, 32Kbytes, and 16Kbytes Versions – Single-Cycle Access up to 25MHz – FlashVault™ Technology Allows Pre-programmed Secure Library Support for End User Applications – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 4ms Page Programming Time and 8ms Full-Chip Erase Time – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM, Single-Cycle Access at Full Speed – 16Kbytes (64Kbytes and 32Kbytes Flash), or 8Kbytes (16Kbytes Flash) Interrupt Controller (INTC) – Autovectored Low Latency Interrupt Service with Programmable Priority External Interrupt Controller (EIC) Peripheral Event System for Direct Peripheral to Peripheral Communication System Functions – Power and Clock Manager – SleepWalking™ Power Saving Control – Internal System RC Oscillator (RCSYS) – 32 KHz Oscillator – Multipurpose Oscillator and Digital Frequency Locked Loop (DFLL) Windowed Watchdog Timer (WDT) Asynchronous Timer (AST) with Real-Time Clock Capability – Counter or Calendar Mode Supported Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency Six 16-bit Timer/Counter (TC) Channels – External Clock Inputs, PWM, Capture and Various Counting Capabilities PWM Channels on All I/O Pins (PWMA) – 8-bit PWM up to 150MHz Source Clock Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independent Baudrate Generator, Support for SPI – Support for Hardware Handshaking One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals – Up to 15 SPI Slaves can be Addressed Two Master and Two Slave Two-Wire Interfaces (TWI), 400kbit/s I2C-compatible One 9-channel Analog-To-Digital Converter (ADC) with up to 12 Bits Resolution – Internal Temperature Sensor • • • AVR®32 32-bit Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary • • • • • • • • • • • • • • 32099A–AVR32–06/09 AT32UC3L • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module • – Support QTouch™ and QMatrix™ Capture from Capacitive Touch Sensors On-Chip Non-Intrusive Debug System – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace – aWire™ Single-Pin Programming Trace and Debug Interface Muxed with Reset Pin – NanoTrace™ Provides Trace Capabilities through JTAG or aWire Interface 48-pin TQFP/QFN/TLLGA (36 GPIO Pins) Five High-Drive I/O Pins Single 1.62-3.6V Power Supply • • • 2 32099A–AVR32–06/09 AT32UC3L 1. Description The AT32UC3L is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capability is achieved using a rich set of DSP instructions. The AT32UC3L embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active power as low as 0.5mW/MHz, and leakage down to 100nA while still retaining a bank of backup registers. The device allows a wide range of trade-offs between functionality and power consumption, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application. The Peripheral Direct Memory Access (DMA) controller enables data transfers between peripherals and memories without processor involvement. The Peripheral DMA controller drastically reduces processing overhead when transferring continuous and large data streams. The AT32UC3L incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. The secure libraries can be executed while the CPU is in Secure State, but not read by non-secure software in the device. The device can thus be shipped to end costumers, who will be able to program their own code into the device, accessing the secure libraries, but without risk of compromising the proprietary secure code. The Peripheral Event System allows peripherals to receive, react to, and send peripheral events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low power sleep modes. The Power Manager improves design flexibility and security. The Power Manager supports SleepWalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. Power monitoring is supported by on-chip Power-On Reset (POR), Brown-Out Detector (BOD), and Supply Monitor (SM). The device features several oscillators, such as Digital Frequency Locked Loop (DFLL), Oscillator 0 (OSC0), and system RC oscillator (RCSYS). Either of these oscillators can be used as source for the system clock. The DFLL is a programmable internal oscillator from 20 to 150MHz. It can be tuned to a high accuracy if an accurate oscillator is running, e.g. the 32KHz crystal oscillator. The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable. The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in counter mode or calendar mode. The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it to a known reference clock. The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. 3 32099A–AVR32–06/09 AT32UC3L The Pulse Width Modulation controller (PWMA) provides 8-bit PWM channels which can be synchronized and controlled from a common timer. One PWM channel is available for each I/O pin on the device, enabling applications that require multiple PWM outputs, such as LCD backlight control. The PWM channels can operate independently, with duty cycles set independently from each other, or in interlinked mode, with multiple channels changed at the same time. The AT32UC3L also features many communication interfaces for communication intensive applications like USART, SPI, or TWI. A general purpose 9-channel ADC is provided, as well as eight analog comparators (AC). The ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel. The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using the QTouch technology. Capacitive touch sensors use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. The CAT module allows up to 17 touch sensors, or up to 18 by 8 matrix sensors to be interfaced. One touch sensor can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. The AT32UC3L integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access, in addition to basic runtime control. The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin aWire interface allows all features available through the JTAG interface to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals. 4 32099A–AVR32–06/09 AT32UC3L 2. Overview 2.1 Block Diagram Figure 2-1. Block Diagram MEMORY INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N TCK TDO TDI TMS RESET_N LOCAL BUS INTERFACE LOCAL BUS JTAG INTERFACE aWire NEXUS CLASS 2+ OCD UC CPU MEMORY PROTECTION UNIT INSTR INTERFACE DATA INTERFACE 16 KB SRAM M M M S FLASH CONTROLLER HIGH SPEED BUS MATRIX S 64 KB FLASH S CONFIGURATION S REGISTERS BUS M HSB-PB BRIDGE B HSB-PB BRIDGE A PERIPHERAL DMA CONTROLLER GENERALPURPOSE I/Os POWER MANAGER DMA CSA[16:0] PA PB CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER CAPACITIVE TOUCH MODULE CSB[16:0] SMP SYNC USART0 USART1 USART2 USART3 RXD TXD CLK RTS, CTS SCK DMA DMA R CSYS RC32K NPCS[3..0] TWCK DMA GENERAL PURPOSE I/Os GCLK[4..0] SPI MISO, MOSI RC120M XIN32 XOUT32 XIN0 XOUT0 OSC32K OSC0 DFLL BOD SYSTEM CONTROL INTERFACE TWI MASTER 0 TWI MASTER 1 TWD TWALM TWCK PA PB TWI SLAVE 0 TWI SLAVE 1 DMA TWD TWALM DMA INTERRUPT CONTROLLER EXTINT[5..1] NMI 9-CHANNEL ADC INTERFACE AD[8..0] ADVREF EXTERNAL INTERRUPT CONTROLLER TIMER/COUNTER 0 TIMER/COUNTER 1 A[2..0] B[2..0] PWM[35..0] PWM CONTROLLER ASYNCHRONOUS TIMER WATCHDOG TIMER FREQUENCY METER CLK[2..0] AC INTERFACE ACBP[3..0] ACBN[3..0] ACAP[3..0] ACAN[3..0] ACREFN GLUE LOGIC CONTROLLER OUT[1:0] IN[7..0] 5 32099A–AVR32–06/09 AT32UC3L 2.2 Configuration Summary Table 2-1. Feature Flash SRAM GPIO Hi-drive pins External Interrupts TWI USART Peripheral DMA Channels Peripheral Event System SPI Asynchronous Timers Timer/Counter Channels PWM channels Frequency Meter Watchdog Timer Power Manager Configuration Summary AT32UC3L0 64KB 16KB AT32UC3L1 32KB 16KB 36 5 8 2 4 12 1 1 1 6 36 1 1 1 Digital Frequency Locked Loop 20-150 MHz (DFLL) Crystal Oscillator 3-16 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115 kHz (RCSYS) RC Oscillator 32 kHz (RC32K) 9 channel 10-bit 1 8 1 1 1 50 MHz TQFP48/QFN48/TLLGA48 AT32UC3L2 16KB 8KB Oscillators ADC Temperature Sensor Analog Comparators Capacitive Touch Module JTAG aWire Max Frequency Package 6 32099A–AVR32–06/09 AT32UC3L 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2. Figure 3-1. TQFP48/QFN48/TLLGA48 Pinout PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 37 38 39 40 41 42 43 44 45 46 47 48 12 11 10 9 8 7 6 5 4 3 2 1 PA05 PA00 PA06 PA22 PB03 PB02 PB00 PB12 PA03 PA08 PA09 GND 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 PA21 PB10 RESET_N PB04 PB05 GND VDDCORE VDDIN PB01 PA07 PA01 PA02 3.2 3.2.1 Peripheral Multiplexing on I/O lines Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. 7 32099A–AVR32–06/09 AT32UC3L Table 3-1. Q F P 48 11 14 13 4 28 GPIO Controller Function Multiplexing GPIO Function G PI O 0 1 2 3 4 PIN PA00 PA01 PA02 PA03 PA04 Supply VDDIO VDDIO VDDIO VDDIO VDDIO Pad Type Normal I/O Normal I/O Highdrive I/O Normal I/O Normal I/O TWI, Normal I/O Highdrive I/O, 5V tolerant TWI, Normal I/O Highdrive I/O Highdrive I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O TWI, Normal I/O Normal I/O Normal I/O Normal I/O A USART0TXD USART0RXD USART0RTS USART0CTS SPI-MISO B USART1RTS USART1CTS ADCIFBTRIGGER SPINPCS[1] TWIMS0TWCK TWIMS1TWCK C SPINPCS[2] SPINPCS[3] USART2TXD USART2TXD USART1RXD USART1TXD D E PWMAPWMA[0] F G SCIFGCLK[0] H CAT-CSA[2] CAT-CSA[1] CAT-CSA[3] CAT-CSB[3] CAT-CSA[7] USART1CLK TC0-A0 TC0-B0 TC0-B1 PWMAPWMA[1] PWMAPWMA[2] PWMAPWMA[3] PWMAPWMA[4] PWMAPWMA[5] ACIFBACAP[0] ACIFBACBP[0] ACIFBACBN[3] ACIFBACBP[1] ACIFBACBN[0] TWIMS0TWALM USART0CLK USART0CLK 12 PA05 5 VDDIO SPI-MOSI TC0-A1 TWIMS0TWD CAT-CSB[7] 10 PA06 6 VDDIO SPI-SCK USART2TXD USART1CLK TC0-B0 PWMAPWMA[6] SCIFGCLK[1] CAT-CSB[1] 15 PA07 7 VDDIO SPINPCS[0] USART1TXD USART1RXD TWIMS0TWD USART2RXD SPINPCS[2] SPINPCS[3] TWIMS1TWALM TC0-A2 TC0-B2 TC0-A0 TWIMS0TWCK ADCIFBADP[0] ADCIFBADP[1] PWMAPWMA[7] PWMAPWMA[8] PWMAPWMA[9] PWMAPWMA[10] PWMAPWMA[11] ACIFBACAN[0] EICEXTINT[0] CAT-CSB[2] 3 2 46 27 47 26 36 37 38 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 8 9 10 11 12 13 14 15 16 VDDIO VDDIO VDDIO VDDIN VDDIO VDDIN VDDIO VDDIO VDDIO CAT-CSA[4] SCIF-GCLK[2] ACIFBACAP[1] EICEXTINT[1] SCIFGCLK[2] CAT-CSB[4] CAT-CSA[5] ADCIFBPRND GLOCOUT[0] ADCIFBAD[0] ADCIFBAD[1] ADCIFBAD[2] ADCIFBAD[3] ADCIFBAD[4] ADCIFBAD[5] USART2TXD USART2CLK GLOC-IN[7] TC0-CLK2 TC0-CLK1 TC0-CLK0 TC0-CLK1 TC0-A0 USART2RTS CAT-SMP SCIFGCLK[2] CAT-SMP GLOC-IN[6] GLOC-IN[5] PWMAPWMA[12] PWMAPWMA[13] PWMAPWMA[14] PWMAPWMA[15] PWMAPWMA[16] PWMAPWMA[17] PWMAPWMA[18] PWMAPWMA[19] PWMAPWMA[20] ACIFBACAN[1] CAT-SMP SCIFGCLK[3] EICEXTINT[2] SCIFGCLK[4] CAT-CSB[5] CAT-CSA[0] CAT-CSA[6] CAT-CSB[6] CAT-CSA[8] CAT-SYNC ACIFBACREFN CAT-SMP EICEXTINT[3] EICEXTINT[4] CAT-DIS EICEXTINT[5] CAT-SYNC 39 PA17 17 VDDIO TC0-A1 USART2CTS TWIMS1TWD GLOC-IN[4] CAT-CSB[8] 41 40 25 PA18 PA19 PA20 18 19 20 VDDIO VDDIO VDDIN TC0-B1 TC0-A2 TWIMS0TWCK TC0-A1 CAT-SYNC CAT-CSB[0] CATCSA[10] CATCSA[12] TWIMS1TWALM GLOC-IN[3] SCIFRC32OUT 8 32099A–AVR32–06/09 AT32UC3L Table 3-1. GPIO Controller Function Multiplexing TWI, 5V tolerant, SMBus, Normal I/O Normal I/O Normal I/O Highdrive I/O Normal I/O Normal I/O TWI, 5V tolerant, SMBus, Normal I/O TWI, 5V tolerant, SMBus, Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O USART2RXD TWIMS0TWD ADCIFBTRIGGER PWMAPWMA[21] PWMAPWMAOD[21] SCIFGCLK[0] 24 PA21 21 VDDIN TC0-B1 CAT-SMP 9 6 16 7 8 PA22 PB00 PB01 PB02 PB03 22 32 33 34 35 VDDIO VDDIO VDDIO VDDIO VDDIO USART0CTS USART3TXD USART3RXD USART3RTS USART3CTS USART2CLK ADCIFBADP[0] ADCIFBADP[1] USART3CLK USART3CLK TC0-B2 SPINPCS[0] SPI-SCK SPI-MISO SPI-MOSI CAT-SMP TC0-A1 TC0-B1 TC0-A2 TC0-B2 PWMAPWMA[22] PWMAPWMA[23] PWMAPWMA[24] PWMAPWMA[25] PWMAPWMA[26] ACIFBACBN[2] ACIFBACAP[2] TC1-A0 TC1-A1 ACIFBACAN[2] ACIFBACBP[2] SCIFGCLK[1] TC1-A2 CATCSB[10] CAT-CSA[9] CAT-CSB[9] CATCSB[11] CATCSA[11] 21 PB04 36 VDDIN TC1-A0 USART1RTS USART1CLK TWIMS0TWALM PWMAPWMA[27] PWMAPWMAOD[27] TWIMS1TWCK CATCSA[14] 20 PB05 37 VDDIN TC1-B0 USART1CTS USART1CLK TWIMS0TWCK PWMAPWMA[28] PWMAPWMAOD[28] SCIFGCLK[3] CATCSB[14] 30 31 32 29 23 44 5 PB06 PB07 PB08 PB09 PB10 PB11 PB12 38 39 40 41 42 43 44 VDDIO VDDIO VDDIO VDDIO VDDIN VDDIO VDDIO TC1-A1 TC1-B1 TC1-A2 TC1-B2 TC1-CLK0 TC1-CLK1 TC1-CLK2 USART3TXD USART3RXD USART3RTS USART3CTS USART1TXD USART1RXD ADCIFBAD[6] ADCIFBAD[7] ADCIFBAD[8] USART3CLK USART3CLK GLOC-IN[2] GLOC-IN[1] GLOC-IN[0] PWMAPWMA[29] PWMAPWMA[30] PWMAPWMA[31] PWMAPWMA[32] ACIFBACAN[3] ACIFBACAP[3] CAT-SYNC ACIFBACBN[1] EICEXTINT[0] EICEXTINT[1] EICEXTINT[2] EICEXTINT[3] EICEXTINT[4] CATCSB[13] CATCSA[13] CATCSB[12] CATCSB[15] CATCSB[16] CATCSA[16] CATCSA[15] GLOCOUT[1] ADCIFBTRIGGER PWMAPWMA[33] PWMAPWMA[34] PWMAPWMA[35] CAT-VDIVEN ACIFBACBP[3] EICEXTINT[5] SCIFGCLK[4] TWIMS1TWALM CAT-SYNC See Section 3.3 for a description of the various peripheral signals. Signals are prioritized according to the function priority listed in Table 3-2 on page 10 if multiple functions are enabled simultaneously. Refer to ”Electrical Characteristics” on page 786 for a description of the electrical properties of the pad types used. 9 32099A–AVR32–06/09 AT32UC3L 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled. Table 3-2. Function A B C D E F G H Peripheral Functions Description GPIO peripheral selection A GPIO peripheral selection B GPIO peripheral selection C GPIO peripheral selection D GPIO peripheral selection E GPIO peripheral selection F GPIO peripheral selection G GPIO peripheral selection H 3.2.3 JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespective of the I/O Controller configuration. Table 3-3. JTAG Pinout Pin name PA00 PA01 PA02 PA03 JTAG pin TCK TMS TDO TDI 48TQFP/QFN pin 11 14 13 4 3.2.4 Nexus OCD AUX Port Connections If the OCD trace system is enabled, the trace system will take control over a number of pins, respectively of the I/O Controller configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 3-4. Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N Nexus OCD AUX Port Connections AXS=1 PA05 PA10 PA18 PA17 PA16 PA15 PA14 PA04 AXS=0 PB08 PB00 PB04 PB05 PB03 PB02 PB09 PA04 10 32099A–AVR32–06/09 AT32UC3L Table 3-4. Pin MCKO MSEO[1] MSEO[0] Nexus OCD AUX Port Connections AXS=1 PA06 PA07 PA11 AXS=0 PB01 PB11 PB12 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. Oscillator Pinout Pin PA08 PA10 PA13 PA09 PA12 PA20 Oscillator Function XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 48TQFP/QFN/TLLGA 3 46 26 2 47 25 3.2.6 Other Functions The functions listed in Table 3-6 are not mapped to the normal GPIO functions.The aWire DATA pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be actice after the aWire is enabled and the full duplex command has been sent. The WAKE_N pin is always enabled. Please refer to Section 3.5.4 on page 20 for constraints on the WAKE_N pin. Table 3-6. Other Functions Pin PA11 RESET_N PA00 Function WAKE_N aWire DATA aWire DATAOUT 48TQFP/TQFN/TLLGA 27 22 11 11 32099A–AVR32–06/09 AT32UC3L 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Name Signal Descriptions List Function Type Analog Comparator Interface - ACIFB Active Level Comments ACAN3 - ACAN0 ACAP3 - ACAP0 ACBN3 - ACBN0 ACBP3 - ACBP0 ACREFN Negative inputs for comparators "A" Positive inputs for comparators "A" Negative inputs for comparators "B" Positive inputs for comparators "B" Common negative reference Analog Analog Analog Analog Analog ADC Interface - ADCIFB AD8 - AD0 ADP1 - ADP0 PRND TRIGGER Analog Signal Drive Pin for touch screen Pseudorandom output signal External trigger aWire - AW DATA DATAOUT aWire data aWire data output for full duplex mode I/O I/O Analog Output Output Input Capacitive Touch Module - CAT CSA16 - CSA0 CSB16 - CSB0 SMP SYNC VDIVEN Capacitive Sense A Capacitive Sense B SMP signal Synchronize signal Voltage divider enable I/O I/O Output Input Output External Interrupt Controller - EIC NMI EXTINT5 - EXTINT1 Non-Maskable Interrupt External interrupt Input Input Glue Logic Controller - GLOC IN7 - IN0 OUT1 - OUT0 Inputs to lookup tables Outputs from lookup tables Input Output JTAG module - JTAG TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input 12 32099A–AVR32–06/09 AT32UC3L Table 3-7. Signal Descriptions List Power Manager - PM RESET_N Reset Input Low Basic Pulse Width Modulation Controller - PWMA PWMA35 - PWMA0 PWMAOD35 PWMAOD0 PWMA channel waveforms PWMA channel waveforms, open drain mode Output Output Not all channels support open drain mode System Control Interface - SCIF GCLK4 - GCLK0 RC32OUT XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 Generic Clock Output RC32K output at startup Crystal 0 Input Crystal 32 Input (primary location) Crystal 32 Input (secondary location) Crystal 0 Output Crystal 32 Output (primary location) Crystal 32 Output (secondary location) Output Output Analog/ Digital Analog/ Digital Analog/ Digital Analog Analog Analog Serial Peripheral Interface - SPI MISO MOSI NPCS3 - NPCS0 SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O I/O Timer/Counter - TC0, TC1 A0 A1 A2 B0 B1 B2 CLK0 CLK1 CLK2 Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input I/O I/O I/O I/O I/O I/O Input Input Input Low Two-wire Interface - TWIMS0, TWIMS1 TWALM TWCK TWD SMBus SMBALERT Two-wire Serial Clock Two-wire Serial Data I/O I/O I/O Low Universal Synchronous/Asynchronous Receiver/Transmitter - USART0, USART1, USART2, USART3 13 32099A–AVR32–06/09 AT32UC3L Table 3-7. CLK CTS RTS RXD TXD Signal Descriptions List Clock Clear To Send Request To Send Receive Data Transmit Data I/O Input Output Input Output Low Low Table 3-8. Signal Name Signal Description List, continued Function Power Type Active Level Comments VDDCORE Core Power Supply / Voltage Regulator Output Power Input/Output 1.62 V to 1.98 V 1.62 V to 3.6 V. VDDIO should always be equal to or lower than VDDIN. 1.62 V to 1.98 V TBD to 1.98 V 1.62 V to 3.6V (1) VDDIO I/O Power Supply Power Input VDDANA ADVREFP VDDIN GNDANA GND Analog Power Supply Analog Reference Voltage Voltage Regulator Input Analog Ground Ground Power Input Power Input Power Input Ground Ground Auxiliary Port - AUX MCKO MDO5 - MDO0 MSEO1 - MSEO0 EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Input Output Low Low General Purpose I/O pin - GPIOA, GPIOB PA22 - PA0 PB12 - PB0 1. See Section 3.5 Parallel I/O Controller GPIOA Parallel I/O Controller GPIOB I/O I/O 14 32099A–AVR32–06/09 AT32UC3L 3.4 3.4.1 I/O Line Considerations JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. TDO pin is an output, driven at VDDIO, and has no pull-up resistor. These JTAG pins can be used as GPIO pins and muxed with peripherals when the JTAG is disabled. 3.4.2 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debugging, it must not be driven by the application. 3.4.3 TWI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as GPIO pins. 3.4.4 GPIO Pins All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except PA00. 3.4.5 ADC Input Pins These pins are regular I/O pins powered from the VDDIO. However, when these pins are used for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range. 3.5 3.5.1 Power Considerations Power Supplies The AT32UC3L has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. • VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal. • VDDANA: Powers the ADC. Voltage is 1.8V nominal. • VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDANA is GNDANA. Refer to ”Electrical Characteristics” on page 786 for power consumption on the various supply pins. 15 32099A–AVR32–06/09 AT32UC3L 3.5.2 Voltage Regulator The AT32UC3L embeds a voltage regulator that converts from 3.3V nominal to 1.8V with a load of up to 60 mA. The regulator supplies the output voltage on VDDCORE. VDDCORE should be externally connected to the 1.8V domains. See Section 3.5.3 for regulator connection figures. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallell between VDDCORE and GND as close to the chip as possible. Please refer to Section 32.9.1 for decoupling capacitors values and regulator characteristics. Figure 3-2. Supply Decoupling 3.3V CIN2 CIN1 VDDIN 1.8V Regulator VDDCORE 1.8V COUT2 COUT1 3.5.3 Regulator Connection The AT32UC3L supports three power supply configurations: •3.3V single supply mode •1.8V single supply mode •3.3V supply mode, with 1.8V regulated I/O lines 3.5.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. Figure 3-3 shows the power schematics to be used for 3.3V single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). 16 32099A–AVR32–06/09 AT32UC3L Figure 3-3. 3.3V Single Power Supply mode + TBD-3.6V - VDDIN VDDIO GND I/O Pins Linear VDDCORE I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL VDDANA ADC GNDANA 17 32099A–AVR32–06/09 AT32UC3L 3.5.3.2 1.8V Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in Figure 3-4. All I/O lines will be powered by the same power (VDDIN = VDDIO = VDDCORE). Figure 3-4. 1.8V Single Power Supply Mode. + 1.62-1.98V - VDDIN VDDIO GND I/O Pins Linear VDDCORE I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL VDDANA ADC GNDANA 18 32099A–AVR32–06/09 AT32UC3L 3.5.3.3 3.3V Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in Figure 3-5. This configuration is required in order to use Shutdown mode. Figure 3-5. 3.3V Power with 1.8V Regulated I/O Lines TBD-3.6V + VDDIN - VDDIO GND I/O Pins Linear VDDCORE I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL VDDANA ADC GNDANA In this mode, some I/O lines are powered by VDDIN while others I/O lines are powered by VDDIO. Refer to Table 1-1 on page 8 for description of power supply for each I/O line. Important note: As the regulator has a maximum output current of 60mA, this mode can only be used in applications where the maximum I/O current is known and compatible with the core and peripheral power consumption. Typically, great care must be used to ensure that only a few I/O lines are toggling at the same time and drive very small loads. 19 32099A–AVR32–06/09 AT32UC3L 3.5.4 3.5.4.1 Power-up Sequence Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 32-3 on page 787. Recommended order for power supplies is also described in this table. 3.5.4.2 Minimum Rise Rate The integrated Power-Reset circuitry monitoring the VDDIN powering supply requires a minimum rise rate for the VDDIN power supply. See Table 32-3 on page 787 for the minimum rise rate value. If the application can not ensure that the minimum rise rate condition for the VDDIN power supply is met, one of the following configuration can be used: •A logic “0” value is applied during power-up on pin PA11 until VDDIN rises above 1.2V. •A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V. 20 32099A–AVR32–06/09 AT32UC3L 4. Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.1 Features • 32-bit load/store AVR32A RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure operating systems Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extention with saturating arithmetic, and a wide variety of multiply instructions • 3-stage pipeline allowing one instruction per clock cycle for most instructions – Byte, halfword, word, and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection • Secure State for supporting FlashVaultTM technology – – – – – 4.2 AVR32 Architecture AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for costsensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 21 32099A–AVR32–06/09 AT32UC3L The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced On-Chip Debug (OCD) system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and I/O controller ports. This local bus has to be enabled by writing a one to the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the CPU Local Bus section in the Memories chapter. Figure 4-1 on page 23 displays the contents of AVR32UC. 22 32099A–AVR32–06/09 AT32UC3L Figure 4-1. Overview of the AVR32UC CPU Reset interface OCD interface Interrupt controller interface OCD system Power/ Reset control AVR32UC CPU pipeline MPU Instruction memory controller High Speed Bus master High Speed Bus Data memory controller High Speed Bus slave High Speed Bus High Speed Bus master CPU Local Bus master CPU Local Bus CPU RAM 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 4-2 on page 24 shows an overview of the AVR32UC pipeline stages. High Speed Bus 23 32099A–AVR32–06/09 AT32UC3L Figure 4-2. The AVR32UC Pipeline MUL Multiply unit IF ID Regfile Read ALU Regfile write ALU unit Prefetch unit Decode unit Load-store unit LS 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Interrupt Handling Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 4.3.2.1 4.3.2.2 Java Support AVR32UC does not provide Java hardware acceleration. Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. 4.3.2.3 4.3.2.4 24 32099A–AVR32–06/09 AT32UC3L The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d Instructions with Unaligned Reference Support Supported Alignment Word Word 4.3.2.5 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: • All SIMD instructions • All coprocessor instructions if no coprocessors are present • retj, incjosp, popjc, pushjc • tlbr, tlbs, tlbw • cache 4.3.2.6 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The device described in this datasheet uses CPU revision 3. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 25 32099A–AVR32–06/09 AT32UC3L 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit 0 Bit 31 The AVR32UC Register File INT0 Bit 31 Bit 0 Supervisor Bit 0 INT1 Bit 31 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Exception Bit 31 Bit 0 NMI Bit 31 Bit 0 Secure Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 4.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4 and Figure 4-5. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 4-4. Bit 31 The Status Register High Halfword Bit 16 SS LC 1 0 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM Bit name Initial value Global Interrupt Mask Interrupt Level 0 Mask Interrupt Level 1 Mask Interrupt Level 2 Mask Interrupt Level 3 Mask Exception Mask Mode Bit 0 Mode Bit 1 Mode Bit 2 Reserved Debug State Debug State Mask Reserved Secure State 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 26 32099A–AVR32–06/09 AT32UC3L Figure 4-5. Bit 15 The Status Register Low Halfword Bit 0 0 T 0 0 0 0 0 0 0 0 0 L 0 Q 0 V 0 N 0 Z 0 C 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 4.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Table 4-2. Priority 1 2 3 4 5 6 N/A N/A Overview of Execution Modes, their Priorities and Privilege Levels. Mode Non Maskable Interrupt Exception Interrupt 3 Interrupt 2 Interrupt 1 Interrupt 0 Supervisor Application Security Privileged Privileged Privileged Privileged Privileged Privileged Privileged Unprivileged Description Non Maskable high priority interrupt mode Execute exceptions General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode Runs supervisor calls Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 4.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. 27 32099A–AVR32–06/09 AT32UC3L Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. The rest of the code can not access resources reserved for this secure code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Technical Reference Manual for details. System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 4-3. Reg # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4.4.4 System Registers Address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 Name SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 Function Status Register Exception Vector Base Address Application Call Base Address CPU Control Register Exception Cause Register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Status Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Address Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC 28 32099A–AVR32–06/09 AT32UC3L Table 4-3. Reg # 24 25 26 27 28 29 30 31 32 33-63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 System Registers (Continued) Address 96 100 104 108 112 116 120 124 128 132-252 256 260 264 268 272 276 280 284 288 292 296 300 304 308 312 316 320 324 328 332 336 340 344 348 352 356 Name JAVA_LV1 JAVA_LV2 JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA JBCR Reserved CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 MPUPSR0 MPUPSR1 Function Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Reserved for future use Configuration register 0 Configuration register 1 Cycle Counter register Compare register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Bus Error Address Register MPU Address Register region 0 MPU Address Register region 1 MPU Address Register region 2 MPU Address Register region 3 MPU Address Register region 4 MPU Address Register region 5 MPU Address Register region 6 MPU Address Register region 7 MPU Privilege Select Register region 0 MPU Privilege Select Register region 1 29 32099A–AVR32–06/09 AT32UC3L Table 4-3. Reg # 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 System Registers (Continued) Address 360 364 368 372 376 380 384 388 392 396 400 404 408 412 416 420 424 428 432 436 440 444 448-764 768-1020 Name MPUPSR2 MPUPSR3 MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR Reserved IMPL Function MPU Privilege Select Register region 2 MPU Privilege Select Register region 3 MPU Privilege Select Register region 4 MPU Privilege Select Register region 5 MPU Privilege Select Register region 6 MPU Privilege Select Register region 7 Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC MPU Access Permission Register A MPU Access Permission Register B MPU Control Register Secure State Status Register Secure State Address Flash Register Secure State Address RAM Register Secure State Address 0 Register Secure State Address 1 Register Secure State Stack Pointer System Register Secure State Stack Pointer Application Register Secure State Return Address Register Secure State Return Status Register Reserved for future use IMPLEMENTATION DEFINED 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as a common term for exceptions and interrupts. AVR32UC incorporates a powerful event handling scheme. The different event sources, like Illegal Op-code and interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple events are received simultaneously. Additionally, pending events of a higher priority class may preempt handling of ongoing events of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution is passed to an event handler at an address specified in Table 4-4 on page 34. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address 30 32099A–AVR32–06/09 AT32UC3L relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the interrupts and provides the autovector offset to the CPU. 4.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 4.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 4-4 on page 34, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete i nstruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 31 32099A–AVR32–06/09 AT32UC3L 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 4.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the status register. Upon entry into Debug mode, hardware sets the SR.D bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The Mode bits in the Status Register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 4.5.5 Entry Points for Events Several different event handler entry points exist. In AVR32UC, the reset address is 0x80000000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an interrupt controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 4-4 on page 34. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority 32 32099A–AVR32–06/09 AT32UC3L than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 34. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit. 33 32099A–AVR32–06/09 AT32UC3L Table 4-4. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Priority and Handler Addresses for Events Handler Address 0x80000000 Provided by OCD system EVBA+0x00 EVBA+0x04 EVBA+0x08 EVBA+0x0C EVBA+0x10 Autovectored Autovectored Autovectored Autovectored EVBA+0x14 EVBA+0x50 EVBA+0x18 EVBA+0x1C EVBA+0x20 EVBA+0x24 EVBA+0x28 EVBA+0x2C EVBA+0x30 EVBA+0x100 EVBA+0x34 EVBA+0x38 EVBA+0x60 EVBA+0x70 EVBA+0x3C EVBA+0x40 EVBA+0x44 Name Reset OCD Stop CPU Unrecoverable exception TLB multiple hit Bus error data fetch Bus error instruction fetch NMI Interrupt 3 request Interrupt 2 request Interrupt 1 request Interrupt 0 request Instruction Address ITLB Miss ITLB Protection Breakpoint Illegal Opcode Unimplemented instruction Privilege violation Floating-point Coprocessor absent Supervisor call Data Address (Read) Data Address (Write) DTLB Miss (Read) DTLB Miss (Write) DTLB Protection (Read) DTLB Protection (Write) DTLB Modified Event source External input OCD system Internal MPU Data bus Data bus External input External input External input External input External input CPU MPU MPU OCD system Instruction Instruction Instruction UNUSED Instruction Instruction CPU CPU MPU MPU MPU MPU UNUSED PC of offending instruction PC(Supervisor Call) +2 PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction Stored Return Address Undefined First non-completed instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction 34 32099A–AVR32–06/09 AT32UC3L 5. Memories 5.1 Embedded Memories • Internal High-Speed Flash – 64Kbytes (AT32UC3L064) – 32Kbytes (AT32UC3L032) – 16Kbytes (AT32UC3L016) • - 0 Wait State Access at up to 25 MHz in Worst Case Conditions • - 1 Wait State Access at up to 50 MHz in Worst Case Conditions • - Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access • - Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation to only 8% compared to 0 wait state operation • - 100 000 Write Cycles, 15-year Data Retention Capability • - 4ms Page Programming Time, 8 ms Chip Erase Time • - Sector Lock Capabilities, Bootloader Protection, Security Bit • - 32 Fuses, Erased During Chip Erase • - User Page For Data To Be Preserved During Chip Erase • Internal High-Speed SRAM, Single-cycle access at full speed – 16Kbytes (AT32UC3L064, AT32UC3L032) – 8Kbytes (AT32UC3L016) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows: Table 5-1. Device AT32UC3L Physical Memory Map Start Address 0x00000000 0x80000000 0xFFFE0000 0xFFFF0000 Size AT32UC3L064 AT32UC3L032 AT32UC3L016 Embedded SRAM Embedded Flash HSB-PB Bridge B HSB-PB Bridge A 16 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 16 Kbytes 32 Kbytes 64 kBytes 64 Kbytes 8 Kbytes 16 Kbytes 64 Kbytes 64 Kbytes Table 5-2. Flash Memory Parameters Part Number AT32UC3L064 AT32UC3L032 AT32UC3L016 Flash Size (FLASH_PW) 64 Kbytes 32 Kbytes 16 Kbytes Number of pages (FLASH_P) 256 128 64 Page size (FLASH_W) 64 words 64 words 64 words 35 32099A–AVR32–06/09 AT32UC3L 5.3 Peripheral Address Map Peripheral Address Mapping Address 0xFFFE0000 Table 5-3. Peripheral Name FLASHCDW Flash Controller - FLASHCDW Bus 0xFFFE0400 HMATRIX 0xFFFE0800 HSB Matrix - HMATRIX SAU 0xFFFF0000 Secure Access Unit - SAU PDCA 0xFFFF1000 Peripheral DMA Controller - PDCA INTC 0xFFFF1400 Interrupt controller - INTC PM 0xFFFF1800 Power Manager - PM SCIF 0xFFFF1C00 System Control Interface - SCIF AST 0xFFFF2000 Asynchronous Timer - AST WDT 0xFFFF2400 Watchdog Timer - WDT EIC 0xFFFF2800 External Interrupt Controller - EIC FREQM 0xFFFF2C00 Frequency Meter - FREQM GPIO 0xFFFF3000 General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART3 Serial Peripheral Interface - SPI USART0 0xFFFF3400 USART1 0xFFFF3800 USART2 0xFFFF3C00 USART3 0xFFFF4000 SPI 0xFFFF4400 TWIM0 Two-wire Master Interface - TWIM0 36 32099A–AVR32–06/09 AT32UC3L Table 5-3. Peripheral Address Mapping 0xFFFF4800 TWIM1 0xFFFF4C00 Two-wire Master Interface - TWIM1 TWIS0 0xFFFF5000 Two-wire Slave Interface - TWIS0 TWIS1 0xFFFF5400 Two-wire Slave Interface - TWIS1 PWMA 0xFFFF5800 Basic Pulse Width Modulation Controller - PWMA TC0 0xFFFF5C00 Timer/Counter - TC0 TC1 0xFFFF6000 Timer/Counter - TC1 ADCIFB 0xFFFF6400 ADC Interface - ADCIFB ACIFB 0xFFFF6800 Analog Comparator Interface - ACIFB CAT 0xFFFF6C00 Capacitive Touch Module - CAT GLOC 0xFFFF7000 Glue Logic Controller - GLOC AW aWire - AW 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. 37 32099A–AVR32–06/09 AT32UC3L The following GPIO registers are mapped on the local bus: Table 5-4. Port A Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000040 0x40000044 0x40000048 0x4000004C 0x40000050 0x40000054 0x40000058 0x4000005C 0x40000060 0x40000240 0x40000244 0x40000248 0x4000024C 0x40000250 0x40000254 0x40000258 0x4000025C 0x40000260 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) B Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 38 32099A–AVR32–06/09 AT32UC3L 6. Boot Sequence This chapter summarizes the boot sequence of the AT32UC3L. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry for a short time to allow the power to stabilize throughout the device. After reset, the device will use the System RC Oscillator (RCSYS) as clock source. Please refer to Table 32-20 on page 795 for the frequency for this oscillotor. On system start-up, the DFLL is disabled. All clocks to all modules are running. No clocks have a divided frequency; all parts of the system receive a clock with the same frequency as the System RC Oscillator. 6.2 Fetching of Initial Instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x80000000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the DFLL, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 6.3 RC32K Clock Output at Startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on I/O line PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by the system to start other devices or to clock a switching regulator to rise the power supply voltage up to an acceptable value. The clock will be available on I/O line PA20 until one of the following conditions are true: • PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT) • PA20 is configured as a General Purpose Input/Output (GPIO) • The bit FRC32 in the Power Manager PPCR register is cleared (see Power Manager chapter) The maximum amplitude of the clock signal will be defined by VDDIN. 39 32099A–AVR32–06/09 AT32UC3L 7. Flash Controller (FLASHCDW) Rev: 1.0.2.0 7.1 Features • • • • • • • • • • • • • Controls on-chip flash memory Supports 0 and 1 wait state bus access Buffers reducing penalty of wait state in sequential code or loops Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per clock cycle for sequential reads Supports AVR32 Secure State 32-bit HSB interface for reads from flash and writes to page buffer 32-bit PB interface for issuing commands to and configuration of the controller Flash memory is divided into 16 regions can be individually protected or unprotected Additional protection of the Boot Loader pages Supports reads and writes of general-purpose NVM bits Supports reads and writes of additional NVM pages Supports device protection through a security bit Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing flash and clearing security bit 7.2 Overview The Flash Controller (FLASHCDW) interfaces the on-chip flash memory with the 32-bit internal HSB bus. The controller manages the reading, writing, erasing, locking, and unlocking sequences. 7.3 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 7.3.1 Power Management If the CPU enters a sleep mode that disables clocks used by the FLASHCDW, the FLASHCDW will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The FLASHCDW has two bus clocks connected: One High Speed Bus clock (CLK_FLASHCDW_HSB) and one Peripheral Bus clock (CLK_FLASHCDW_PB). These clocks are generated by the Power Manager. Both clocks are enabled at reset, and can be disabled by writing to the Power Manager. The user has to ensure that CLK_FLASHCDW_HSB is not turned off before reading the flash or writing the pagebuffer and that CLK_FLASHCDW_PB is not turned off before accessing the FLASHCDW configuration and control registers. Failing to do so may deadlock the bus. 7.3.2 7.3.3 Interrupts The FLASHCDW interrupt request lines are connected to the interrupt controller. Using the FLASHCDW interrupts requires the interrupt controller to be programmed first. 40 32099A–AVR32–06/09 AT32UC3L 7.3.4 Debug Operation When an external debugger forces the CPU into debug mode, the FLASHCDW continues normal operation. If the FLASHCDW is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 7.4 7.4.1 Functional Description Bus Interfaces The FLASHCDW has two bus interfaces, one High Speed Bus (HSB) interface for reads from the flash memory and writes to the page buffer, and one Peripheral Bus (PB) interface for issuing commands and reading status from the controller. 7.4.2 Memory Organization The flash memory is divided into a set of pages. A page is the basic unit addressed when programming the flash. A page consists of several words. The pages are grouped into 16 regions of equal size. Each of these regions can be locked by a dedicated fuse bit, protecting it from accidental modification. • p pages (FLASH_P) • 256 bytes in each page and in the page buffer (FLASH_W) • pw bytes in total (FLASH_PW) • f general-purpose fuse bits (FLASH_F), used as region lock bits and for other devicespecific purposes • 1 security fuse bit • 1 User page 7.4.3 User Page The User page is an additional page, outside the regular flash array, that can be used to store various data, such as calibration data and serial numbers. This page is not erased by regular chip erase. The User page can only be written and erased by a special set of commands. Read accesses to the User page are performed just as any other read accesses to the flash. The address map of the User page is given in Figure 7-1 on page 43. 7.4.4 Read Operations The on-chip flash memory is typically used for storing instructions to be executed by the CPU. The CPU will address instructions using the HSB bus, and the FLASHCDW will access the flash memory and return the addressed 32-bit word. In systems where the HSB clock period is slower than the access time of the flash memory, the FLASHCDW can operate in 0 wait state mode, and output one 32-bit word on the bus per clock cycle. If the clock frequency allows, the user should use 0 wait state mode, because this gives the highest performance as no stall cycles are encountered. The FLASHCDW can also operate in systems where the HSB bus clock period is faster than the access speed of the flash memory. Wait state support and a read granularity of 64 bits ensure efficiency in such systems. Performance for systems with high clock frequency is increased since the internal read word width of the flash memory is 64 bits. When a 32-bit word is to be addressed, the word itself 41 32099A–AVR32–06/09 AT32UC3L and also the other word in the same 64-bit location is read. The first word is output on the bus, and the other word is put into an internal buffer. If a read to a sequential address is to be performed in the next cycle, the buffered word is output on the bus, while the next 64-bit location is read from the flash memory. Thus, latency in 1 wait state mode is hidden for sequential fetches. The programmer can select the wait states required by writing to the FWS field in the Flash Control Register (FCR). It is the responsibility of the programmer to select a number of wait states compatible with the clock frequency and timing characteristics of the flash memory. In 0ws mode, no wait states are encountered on any flash read operations. In 1 ws mode, one stall cycle is encountered on the first access in a single or burst transfer. In 1 ws mode, if the first access in a burst access is to an address that is not 64-bit aligned, an additional stall cycle is also encountered when reading the second word in the burst. All subsequent words in the burst are accessed without any stall cycles. The Flash Controller provides two sets of buffers that can be enabled in order to speed up instruction fetching. These buffers can be enabled by writing a one to the FCR.SEQBUF and FCR.BRBUF bits. The SEQBUF bit enables buffering hardware optimizing sequential instruction fetches. The BRBUF bit enables buffering hardware optimizing tight inner loops. These buffers are never used when the flash is in 0 wait state mode. Usually, both these buffers should be enabled when operating in 1 wait state mode. Some users requiring absolute cycle determinism may want to keep the buffers disabled. The Flash Controller address space is displayed in Figure 7-1. The memory space between address pw and the User page is reserved, and reading addresses in this space returns an undefined result. The User page is permanently mapped to an offset of 0x00800000 from the start address of the flash memory. Table 7-1. Memory type Main array User User Page Addresses Start address, byte sized 0 0x00800000 Size pw words = 4pw bytes 64 words = 256 bytes 42 32099A–AVR32–06/09 AT32UC3L Figure 7-1. Memory Map for the Flash Memories Offset from base address Reserved User Page 0x0080 0000 pw 0 Flash data array Flash base address Flash with User Page All addresses are byte addresses 7.4.5 High Speed Read Mode The flash provides a High Speed Read Mode, offering slightly higher flash read speed at the cost of higher power consumption. Two dedicated commands, High Speed Read Mode Enable (HSEN) and High Speed Read Mode Disable (HSDIS) control the speed mode. The High Speed Mode (HSMODE) bit in the Flash Status Register (FSR) shows which mode the flash is in. After reset, the High Speed Mode is disabled, and must be manually enabled if the user wants to. Refer to the Electrical Characteristics chapter at the end of this datasheet for details on the maximum clock frequencies in Normal and High Speed Read Mode. Reserved 43 32099A–AVR32–06/09 AT32UC3L Figure 7-2. High Speed Mode Frequency 1 wait state 0 wait state Frequency limit for 0 wait state operation Speed mode or N al m H h ig 7.4.6 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result is placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR). The QPR command is useful to check that a page is in an erased state. The QPR instruction is much faster than performing the erased-page check using a regular software subroutine. Page Buffer Operations The flash memory has a write and erase granularity of one page; data is written and erased in chunks of one page. When programming a page, the user must first write the new data into the Page Buffer. The contents of the entire Page Buffer is copied into the desired page in flash memory when the user issues the Write Page command, Refer to Section 7.5.1 on page 47. In order to program data into flash page Y, write the desired data to locations Y0 to Y31 in the regular flash memory map. Writing to an address A in the flash memory map will not update the flash memory, but will instead update location A%32 in the page buffer. The PAGEN field in the Flash Command (FCMD) register will at the same time be updated with the value A/32. 7.4.7 44 32099A–AVR32–06/09 AT32UC3L Figure 7-3. Mapping from Page Buffer to Flash Flash All locations are doubleword locations Z31 Z27 Z23 Z19 Z15 Z11 Z7 Z3 Y31 Y27 Y23 Y19 Y15 Y11 Y7 Y3 X31 X27 X23 X19 X15 X11 X7 X3 Z30 Z29 Z26 Z25 Z22 Z21 Z18 Z17 Page Z Z14 Z13 Z10 Z9 Z6 Z5 Z2 Z1 Y30 Y29 Y26 Y25 Y22 Y21 Y18 Y17 Page Y Y14 Y13 Y10 Y9 Y6 Y5 Y2 Y1 X30 X29 X26 X25 X22 X21 X18 X17 Page X X14 X13 X10 X9 X6 X5 X2 X1 Z28 Z24 Z20 Z16 Z12 Z8 Z4 Z0 Y28 Y24 Y20 Y16 Y12 Y8 Y4 Y0 X28 X24 X20 X16 X12 X8 X4 X0 Page Buffer 64-bit data 31 27 23 19 15 11 7 3 30 26 22 18 14 10 6 2 29 25 21 17 13 9 5 1 28 24 20 16 12 8 4 0 Internally, the flash memory stores data in 64-bit doublewords. Therefore, the native data size of the Page Buffer is also a 64-bit doubleword. All locations shown in Figure 7-3 are therefore doubleword locations. Since the HSB bus only has a 32-bit data width, two 32-bit HSB transfers must be performed to write a 64-bit doubleword into the Page Buffer. The FLASHCDW has logic to combine two 32-bit HSB transfers into a 64-bit data before writing this 64-bit data into the Page Buffer. This logic requires the word with the low address to be written to the HSB bus before the word with the high address. To exemplify, to write a 64-bit value to doubleword X0 residing in page X, first write a 32-bit word to the byte address pointing to address X0, thereafter write a word to the byte address pointing to address (X0+4). The page buffer is word-addressable and should only be written with aligned word transfers, never with byte or halfword transfers. The page buffer can not be read. The page buffer is also used for writes to the User page. Page buffer write operations are performed with 4 wait states. Any accesses attempted to the FLASHCDW on the HSB bus during these cycles will be automatically stalled. Writing to the page buffer can only change page buffer bits from one to zero, i.e. writing 0xAAAAAAAA to a page buffer location that has the value 0x00000000 will not change the page buffer value. The only way to change a bit from zero to one is to erase the entire page buffer with the Clear Page Buffer command. 45 32099A–AVR32–06/09 AT32UC3L The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded with data to be stored to the flash page. 7.4.8 Writing Words to a Page that is not Completely Erased This can be used for EEPROM emulation, i.e. writes with granularity of one word instead of an entire page. Note that “one word” for the FLASCHDW is actually 64 bits. Only words that are in a completely erased state (0xFFFFFFFFFFFFFFFF) can be changed. The procedure is as follows: 1. Clear page buffer. 2. Write to the page buffer the result of the logical bitwise AND operation between the contents of the flash page and the new data to write. Only bits that were in an erased state can be changed from the original page. 3. Write Page. 7.5 Flash Commands The FLASHCDW offers a command set to manage programming of the flash memory, locking and unlocking of regions, and full flash erasing. See Section 7.8.2 for a complete list of commands. To run a command, the CMD field in the Flash Command Register (FCMD) has to be written with the command number. As soon as the FCMD register is written, the FRDY bit in the Flash Status Register (FSR) is automatically cleared. Once the current command is complete, the FSR.FRDY bit is automatically set. If an interrupt has been enabled by writing a one to FCR.FRDY, the interrupt request line of the Flash Controller is activated. All flash commands except for Quick Page Read (QPR) will generate an interrupt request upon completion if FCR.FRDY is one. Any HSB bus transfers attempting to read flash memory when the FLASHCDW is busy executing a flash command will be stalled, and allowed to continue when the flash command is complete. After a command has been written to FCMD, the programming algorithm should wait until the command has been executed before attempting to read instructions or data from the flash or writing to the page buffer, as the flash will be busy. The waiting can be performed either by polling the Flash Status Register (FSR) or by waiting for the flash ready interrupt. The command written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHCDW is IDLE. The user must make sure that the access pattern to the FLASHCDW HSB interface contains an IDLE cycle so that the command is allowed to start. Make sure that no bus masters such as DMA controllers are performing endless burst transfers from the flash. Also, make sure that the CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter sleep mode after writing to FCMD, or by polling FSR for command completion. This polling will result in an access pattern with IDLE HSB cycles. All the commands are protected by the same keyword, which has to be written in the eight highest bits of the FCMD register. Writing FCMD with data that does not contain the correct key and/or with an invalid command has no effect on the flash memory; however, the PROGE bit is set in the Flash Status Register (FSR). This bit is automatically cleared by a read access to the FSR register. 46 32099A–AVR32–06/09 AT32UC3L Writing a command to FCMD while another command is being executed has no effect on the flash memory; however, the PROGE bit is set in the Flash Status Register (FSR). This bit is automatically cleared by a read access to the FSR register. If the current command writes or erases a page in a locked region, or a page protected by the BOOTPROT fuses, the command has no effect on the flash memory; however, the LOCKE bit is set in the FSR register. This bit is automatically cleared by a read access to the FSR register. 7.5.1 Write/Erase Page Operation Flash technology requires that an erase must be done before programming. The entire flash can be erased by an Erase All command. Alternatively, pages can be individually erased by the Erase Page command. The User page can be written and erased using the mechanisms described in this chapter. After programming, the page can be locked to prevent miscellaneous write or erase sequences. Locking is performed on a per-region basis, so locking a region locks all pages inside the region. Additional protection is provided for the lowermost address space of the flash. This address space is allocated for the Boot Loader, and is protected both by the lock bit(s) corresponding to this address space, and the BOOTPROT[2:0] fuses. Data to be written is stored in an internal buffer called the page buffer. The page buffer contains w words. The page buffer wraps around within the internal memory area address space and appears to be repeated by the number of pages in it. Writing of 8-bit and 16-bit data to the page buffer is not allowed and may lead to unpredictable data corruption. Data must be written to the page buffer before the programming command is written to the Flash Command Register (FCMD). The sequence is as follows: • Reset the page buffer with the Clear Page Buffer command. • Fill the page buffer with the desired contents as described in Section 7.4.7 on page 44. • Programming starts as soon as the programming key and the programming command are written to the Flash Command Register. The PAGEN field in the Flash Command Register (FCMD) must contain the address of the page to write. PAGEN is automatically updated when writing to the page buffer, but can also be written to directly. The FRDY bit in the Flash Status Register (FSR) is automatically cleared when the page write operation starts. • When programming is completed, the FRDY bit in the Flash Status Register (FSR) is set. If an interrupt was enabled by writing FCR.FRDY to one, an interrupt request is generated. Two errors can be detected in the FSR register after a programming sequence: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: Can have two different causes: – The page to be programmed belongs to a locked region. A command must be executed to unlock the corresponding region before programming can start. – A bus master without secure status attempted to program a page requiring secure privileges. 7.5.2 Erase All Operation The entire memory is erased if the Erase All command (EA) is written to the Flash Command Register (FCMD). Erase All erases all bits in the flash array. The User page is not erased. All 47 32099A–AVR32–06/09 AT32UC3L flash memory locations, the general-purpose fuse bits, and the security bit are erased (reset to 0xFF) after an Erase All. The EA command also ensures that all volatile memories, such as register file and RAMs, are erased before the security bit is erased. Erase All operation is allowed only if no regions are locked, and the BOOTPROT fuses are configured with a BOOTPROT region size of 0. Thus, if at least one region is locked, the bit LOCKE in FSR is set and the command is cancelled. If the LOCKE bit in FCR is one, an interrupt request is set generated. When the command is complete, the FRDY bit in the Flash Status Register (FSR) is set. If an interrupt has been enabled by writing FCR.FRDY to one, an interrupt request is generated. Two errors can be detected in the FSR register after issuing the command: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: At least one lock region is protected, or BOOTPROT is different from 0. The erase command has been aborted and no page has been erased. A “Unlock region containing given page” (UP) command must be executed to unlock any locked regions. 7.5.3 Region Lock Bits The flash memory has p pages, and these pages are grouped into 16 lock regions, each region containing p/16 pages. Each region has a dedicated lock bit preventing writing and erasing pages in the region. After production, the device may have some regions locked. These locked regions are reserved for a boot or default application. Locked regions can be unlocked to be erased and then programmed with another application or other data. To lock or unlock a region, the commands Lock Region Containing Page (LP) and Unlock Region Containing Page (UP) are provided. Writing one of these commands, together with the number of the page whose region should be locked/unlocked, performs the desired operation. One error can be detected in the FSR register after issuing the command: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that lock bits can also be set/cleared using the commands for writing/erasing general-purpose fuse bits, see Section 7.6. The general-purpose bit being in an erased (1) state means that the region is unlocked. The lowermost pages in the flash can additionally be protected by the BOOTPROT fuses, see Section 7.6. 7.6 General-purpose Fuse Bits The flash memory has a number of general-purpose fuse bits that the application programmer can use freely. The fuse bits can be written and erased using dedicated commands, and read 48 32099A–AVR32–06/09 AT32UC3L through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions: Table 7-2. GeneralPurpose fuse number 15:0 General-purpose Fuses with Special Functions Name LOCK Usage Region lock bits. External Privileged Fetch Lock. Used to prevent the CPU from fetching instructions from external memories when in privileged mode. This bit can only be changed when the security bit is cleared. The address range corresponding to external memories is device-specific, and not known to the Flash Controller. This fuse bit is simply routed out of the CPU or bus system, the Flash Controller does not treat this fuse in any special way, except that it can not be altered when the security bit is set. If the security bit is set, only an external JTAG or aWire Chip Erase can clear EPFL. No internal commands can alter EPFL if the security bit is set. When the fuse is erased (i.e. "1"), the CPU can execute instructions fetched from external memories. When the fuse is programmed (i.e. "0"), instructions can not be executed from external memories. This fuse has no effect in devices with no External Memory Interface (EBI). Used to select one of eight different bootloader sizes. Pages included in the bootloader area can not be erased or programmed except by a JTAG or aWire chip erase. BOOTPROT can only be changed when the security bit is cleared. If the security bit is set, only an external JTAG or aWire Chip Erase can clear BOOTPROT, and thereby allow the pages protected by BOOTPROT to be programmed. No internal commands can alter BOOTPROT or the pages protected by BOOTPROT if the security bit is set. Used to configure secure state and secure state debug capabilities. Decoded into SSE and SSDE signals as shown in Table 7-4. Refer to the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual for more details on SSE and SSDE. If programmed (i.e. “0”), the JTAG USER PROTECTION feature is enabled. If this fuse is programmed some HSB addresses will be accessible by JTAG access even if the flash security fuse is programmed. Refer to the JTAG documentation for more information on this functionality. This bit can only be changed when the security bit is cleared. 16 EPFL 19:17 BOOTPROT 21:20 SECURE 22 UPROT 49 32099A–AVR32–06/09 AT32UC3L The BOOTPROT fuses protects the following address space for the Boot Loader: Table 7-3. BOOTPROT 7 6 5 4 3 2 1 0 Boot Loader Area Specified by BOOTPROT Pages protected by BOOTPROT None 0-1 0-3 0-7 0-15 0-31 0-63 0-127 Size of protected memory 0 512 byte 1Kbyte 2Kbyte 4Kbyte 8Kbyte 16Kbyte 32Kbyte The SECURE fuses have the following functionality: Table 7-4. SECURE 00 01 10 11 Secure State Configuration Functionality Secure state disabled Secure enabled, secure state debug enabled Secure enabled, secure state debug disabled Secure state disabled SSE 0 1 1 0 SSDE 0 1 0 0 To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit (WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these commands, together with the number of the fuse to write/erase, performs the desired operation. An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse Byte (PGPFB) instruction. A PGPFB to GP fuse byte 2 is not allowed if the flash is locked by the security bit. The PFB command is issued with a parameter in the PAGEN field: • PAGEN[2:0] - byte to write • PAGEN[10:3] - Fuse value to write All general-purpose fuses can be erased by the Erase All General-Purpose fuses (EAGP) command. An EAGP command is not allowed if the flash is locked by the security bit. Two errors can be detected in the FSR register after issuing these commands: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: – A write or erase of the BOOTPROT or EPFL or UPROT fuse bits was attempted while the flash is locked by the security bit. – A write or erase of the SECURE fuse bits was attempted when SECURE mode was enabled. 50 32099A–AVR32–06/09 AT32UC3L The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that the 16 lowest general-purpose fuse bits can also be written/erased using the commands for locking/unlocking regions, see Section 7.5.3. 7.7 Security Bit The security bit allows the entire chip to be locked from external JTAG, aWire, or other debug access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through the JTAG or aWire Chip Erase command. Once the security bit is set, the following Flash Controller commands will be unavailable and return a lock error if attempted: • Write General-Purpose Fuse Bit (WGPB) to BOOTPROT or EPFL fuses • Erase General-Purpose Fuse Bit (EGPB) to BOOTPROT or EPFL fuses • Program General-Purpose Fuse Byte (PGPFB) of fuse byte 2 • Erase All General-Purpose Fuses (EAGPF) One error can be detected in the FSR register after issuing the command: • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. 51 32099A–AVR32–06/09 AT32UC3L 7.8 User Interface FLASHCDW Register Memory Map Register Flash Control Register Flash Command Register Flash Status Register Flash Parameter Register Flash Version Register Flash General Purpose Fuse Register Hi Flash General Purpose Fuse Register Lo Register Name FCR FCMD FSR FPR FVR FGPFRHI FGPFRLO Access Read/Write Read/Write Read/Write Read-only Read-only Read-only Read-only Reset 0x00000000 0x00000000 -(1) -(3) -(3) -(2) -(2) Table 7-5. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 Note: 1. The value of the Lock bits depend on their programmed state. All other bits in FSR are 0. 2. All bits in FGPRHI/LO are dependent on the programmed stae of the fuses they map to. Any bits in these registers not mapped to a fuse read as 0. 3. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 52 32099A–AVR32–06/09 AT32UC3L 7.8.1 Name: Flash Control Register FCR Read/Write 0x00 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 BRBUF 9 SEQBUF 8 - 7 - 6 FWS 5 - 4 - 3 PROGE 2 LOCKE 1 - 0 FRDY • BRBUF: Branch Target Instruction Buffer Enable 0: The Branch Target Instruction Buffer is disabled. 1: The Branch Target Instruction Buffer is enabled. • SEQBUF: Sequential Instruction Fetch Buffer Enable 0: The Sequential Instruction Fetch Buffer is disabled. 1: The Sequential Instruction Fetch Buffer is enabled. • FWS: Flash Wait State 0: The flash is read with 0 wait states. 1: The flash is read with 1 wait state. • PROGE: Programming Error Interrupt Enable 0: Programming Error does not generate an interrupt request. 1: Programming Error generates an interrupt request. • LOCKE: Lock Error Interrupt Enable 0: Lock Error does not generate an interrupt request. 1: Lock Error generates an interrupt request. • FRDY: Flash Ready Interrupt Enable 0: Flash Ready does not generate an interrupt request. 1: Flash Ready generates an interrupt request. 53 32099A–AVR32–06/09 AT32UC3L 7.8.2 Name: Flash Command Register FCMD Read/Write 0x04 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit in FSR to be set. 31 30 29 28 KEY 27 26 25 24 Access Type: Offset: Reset Value: 23 22 21 20 PAGEN [15:8] 19 18 17 16 15 14 13 12 PAGEN [7:0] 11 10 9 8 7 - 6 - 5 4 3 CMD 2 1 0 • KEY: Write protection key This field should be written with the value 0xA5 to enable the command defined by the bits of the register. If the field is written with a different value, the write is not performed and no action is started. This field always reads as 0. • PAGEN: Page number The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify programming, the PAGEN field is automatically updated every time the page buffer is written to. For every page buffer write, the PAGEN field is updated with the page number of the address being written to. Hardware automatically masks writes to the PAGEN field so that only bits representing valid page numbers can be written, all other bits in PAGEN are always 0. As an example, in a flash with 1024 pages (page 0 - page 1023), bits 15:10 will always be 0. Table 7-6. Command No operation Write Page Semantic of PAGEN field in different commands PAGEN description Not used The number of the page to write Not used Page number whose region should be locked Page number whose region should be unlocked Not used GPFUSE # GPFUSE # Not used Clear Page Buffer Lock region containing given Page Unlock region containing given Page Erase All Write General-Purpose Fuse Bit Erase General-Purpose Fuse Bit Set Security Bit 54 32099A–AVR32–06/09 AT32UC3L Table 7-6. Command Program GP Fuse Byte Erase All GP Fuses Quick Page Read Write User Page Erase User Page Quick Page Read User Page High Speed Mode Enable High Speed Mode Disable Semantic of PAGEN field in different commands PAGEN description WriteData[7:0], ByteAddress[2:0] Not used Page number Not used Not used Not used Not used Not used • CMD: Command This field defines the flash command. Issuing any unused command will cause the Programming Error bit in FSR to be set, and the corresponding interrupt to be requested if the PROGE bit in FCR is one. Table 7-7. Command No operation Write Page Erase Page Set of commands Value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 16-31 Mnemonic NOP WP EP CPB LP UP EA WGPB EGPB SSB PGPFB EAGPF QPR WUP EUP QPRUP HSEN HSDIS Clear Page Buffer Lock region containing given Page Unlock region containing given Page Erase All Write General-Purpose Fuse Bit Erase General-Purpose Fuse Bit Set Security Bit Program GP Fuse Byte Erase All GPFuses Quick Page Read Write User Page Erase User Page Quick Page Read User Page High Speed Mode Enable High Speed Mode Disable RESERVED 55 32099A–AVR32–06/09 AT32UC3L 7.8.3 Name: Flash Status Register FSR Read/Write 0x08 0x00000000(*) 30 LOCK14 29 LOCK13 28 LOCK12 27 LOCK11 26 LOCK10 25 LOCK9 24 LOCK8 Access Type: Offset: Reset Value: 31 LOCK15 23 LOCK7 22 LOCK6 21 LOCK5 20 LOCK4 19 LOCK3 18 LOCK2 17 LOCK1 16 LOCK0 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 HSMODE 5 QPRR 4 SECURITY 3 PROGE 2 LOCKE 1 - 0 FRDY • LOCKx: Lock Region x Lock Status 0: The corresponding lock region is not locked. 1: The corresponding lock region is locked. • HSMODE: High-Speed Mode 0: High-speed mode disabled. 1: High-speed mode enabled. • QPRR: Quick Page Read Result 0: The result is zero, i.e. the page is not erased. 1: The result is one, i.e. the page is erased. • SECURITY: Security Bit Status 0: The security bit is inactive. 1: The security bit is active. • PROGE: Programming Error Status Automatically cleared when FSR is read. 0: No invalid commands and no bad keywords were written in the Flash Command Register FCMD. 1: An invalid command and/or a bad keyword was/were written in the Flash Command Register FCMD. • LOCKE: Lock Error Status Automatically cleared when FSR is read. 0: No programming of at least one locked lock region has happened since the last read of FSR. 1: Programming of at least one locked lock region has happened since the last read of FSR. • FRDY: Flash Ready Status 0: The Flash Controller is busy and the application must wait before running a new command. 1: The Flash Controller is ready to run a new command. 56 32099A–AVR32–06/09 AT32UC3L 7.8.4 Name: Flash Parameter Register FPR Read-only 0x0C 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 10 PSZ 9 8 7 - 6 - 5 - 4 - 3 2 FSZ 1 0 • PSZ: Page Size The size of each flash page. Table 7-8. PSZ 0 1 2 3 4 5 6 7 Flash Page Size Page Size 32 Byte 64 Byte 128 Byte 256 Byte 512 Byte 1024 Byte 2048 Byte 4096 Byte 57 32099A–AVR32–06/09 AT32UC3L • FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 7-9. FSZ 0 1 2 3 4 5 6 7 Flash Size Flash Size 4 Kbyte 8 Kbyte 16 Kbyte 32 Kbyte 48 Kbyte 64 Kbyte 96 Kbyte 128 Kbyte FSZ 8 9 10 11 12 13 14 15 Flash Size 192 Kbyte 256 Kbyte 384 Kbyte 512 Kbyte 768 Kbyte 1024 Kbyte 2048 Kbyte Reserved 58 32099A–AVR32–06/09 AT32UC3L 7.8.5 Name: Flash Version Register FVR Read-only 0x10 0x00000000(*) 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 59 32099A–AVR32–06/09 AT32UC3L 7.8.6 Name: Flash General Purpose Fuse Register High FGPFRHI Read-only 0x14 30 GPF62 29 GPF61 28 GPF60 27 GPF59 26 GPF58 25 GPF57 24 GPF56 Access Type: Offset: Reset Value: 31 GPF63 23 GPF55 22 GPF54 21 GPF53 20 GPF52 19 GPF51 18 GPF50 17 GPF49 16 GPF48 15 GPF47 14 GPF46 13 GPF45 12 GPF44 11 GPF43 10 GPF42 9 GPF41 8 GPF40 7 GPF39 6 GPF38 5 GPF37 4 GPF36 3 GPF35 2 GPF34 1 GPF33 0 GPF32 This register is only used in systems with more than 32 GP fuses. • GPFxx: General Purpose Fuse xx 0: The fuse has a written/programmed state. 1: The fuse has an erased state. 60 32099A–AVR32–06/09 AT32UC3L 7.8.7 Name: Flash General Purpose Fuse Register Low FGPFRLO Read-only 0x18 30 GPF30 29 GPF29 28 GPF28 27 GPF27 26 GPF26 25 GPF25 24 GPF24 Access Type: Offset: Reset Value: 31 GPF31 23 GPF23 22 GPF22 21 GPF21 20 GPF20 19 GPF19 18 GPF18 17 GPF17 16 GPF16 15 GPF15 14 GPF14 13 GPF13 12 GPF12 11 GPF11 10 GPF10 9 GPF09 8 GPF08 7 GPF07 6 GPF06 5 GPF05 4 GPF04 3 GPF03 2 GPF02 1 GPF01 0 GPF00 • GPFxx: General Purpose Fuse xx 0: The fuse has a written/programmed state. 1: The fuse has an erased state. 61 32099A–AVR32–06/09 AT32UC3L 62 32099A–AVR32–06/09 AT32UC3L 7.9 Fuse Settings The flash block contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO). The Flash General Purpose Fuse Register High (FGPFRHI) is not used. Some of these fuses have defined meanings outside the flash controller and are described in this section. In addition to the General Purpose fuses, parts of the flash user row can have a defined meaning outside the flash controller and are described in this section. The general purpose fuses are erased by a JTAG or aWire chip erase. 7.9.1 31 BODEN Flash General Purpose Fuse Register Low (FGPFRLO) 30 29 BODHYST 28 27 26 BODLEVEL[5:1] 25 24 23 BODLEVEL[0] 22 UPROT 21 SECURE 20 19 18 BOOTPROT 17 16 EPFL 15 14 13 12 LOCK[15:8] 11 10 9 8 7 6 5 4 LOCK[7:0] 3 2 1 0 BODEN: Brown Out Detector Enable BODEN 00 01 10 11 Description BOD disabled BOD enabled, BOD reset enabled BOD enabled, BOD reset disabled Reserved BODHYST: Brown Out Detector Hysteresis 0: The Brown out detector hysteresis is disabled 1: The Brown out detector hysteresis is enabled BODLEVEL: Brown Out Detector Trigger Level This controls the voltage trigger level for the Brown out detector. Refer to ”Electrical Characteristics” on page 786. UPROT, SECURE, BOOTPROT, EPFL, LOCK These are Flash Controller fuses and are described in the FLASHCDW section. 63 32099A–AVR32–06/09 AT32UC3L 7.9.1.1 Default Fuse Value The devices are shipped with the FGPFRLO register value: 0xE077FFFF: • BODEN fuses set to 11. BOD is disabled. • BODHYST fuse set to 1. The BOD hysteresis is enabled. • BODLEVEL fuses set to 000000. This is the minimum voltage trigger level for BOD. • UPROT fuse set to 1. • SECURE fuse set to 11. • BOOTPROT fuses set to 011. The bootloader protected size is 8KBytes. • EPFL fuse set to 1. External privileged fetch is not locked. • LOCK fuses set to 1111111111111111. No region locked. After the JTAG or aWire chip erase command, the FGPFR register value is 0xFFFFFFFF. 7.9.2 31 - First Word of the User Row (Address 0x80800000) 30 29 28 27 26 25 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 WDTAUTO WDTAUTO: WatchDog Timer Auto Enable at Startup 0: The WDT is automatically enabled at startup. 1: The WDT is not automatically enabled at startup. Please refer to the WDT chapter for detail about timeout settings when the WDT is automatically enabled. 7.9.2.1 Default user row first word value The devices are shipped with the User row erased (all bits 1): • WDTAUTO set to 1, WDT disabled. 64 32099A–AVR32–06/09 AT32UC3L 7.9.3 31 Second Word of the User Row (Address 0x80800004) 30 29 28 SSADRR[15:8] 27 26 25 24 23 22 21 20 SSADRR[7:0] 19 18 17 16 15 14 13 12 SSADRF[15:8] 11 10 9 8 7 6 5 4 SSADRF[7:0] 3 2 1 0 SSADRR: Secure State End Address for the RAM SSADRF: Secure State End Address for the Flash 7.9.3.1 Default user row second word value The devices are shipped with the User row erased (all bits 1). 7.10 Module Configuration The specific configuration for each FLASHCDW instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 7-10. Feature Flash size Number of pages Page size Module Configuration AT32UC3L064 64Kbytes 256 256 bytes AT32UC3L032 32Kbytes 128 256 bytes AT32UC3L016 16Kbytes 64 256 bytes Table 7-11. Module Name FLASHCDW Module Clock Name Clock Name CLK_FLASHCDW_HSB Clock Name CLK_FLASHCDW_PB Table 7-12. Register FVR FPR Register Reset Values Reset Value 0x00000102 0x00000305 65 32099A–AVR32–06/09 AT32UC3L 8. HSB Bus Matrix (HMATRIX) Rev: 1.3.0.3 8.1 Features • • • • • • • User Interface on peripheral bus Configurable number of masters (up to 16) Configurable number of slaves (up to 16) One decoder for each master Three different memory mappings for each master (internal and external boot, remap) One remap function for each master Programmable arbitration for each slave – Round-Robin – Fixed priority Programmable default master for each slave – No default master – Last accessed default master – Fixed default master One cycle latency for the first access of a burst Zero cycle latency for default master One special function register for each slave (not dedicated) • • • • 8.2 Overview The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency). The Bus Matrix provides 16 Special Function Registers (SFR) that allow the Bus Matrix to support application specific features. 8.3 Product Dependencies In order to configure this module by accessing the user registers, other parts of the system must be configured correctly, as described below. 8.3.1 Clocks The clock for the HMATRIX bus interface (CLK_HMATRIX) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. 8.4 Functional Description 8.4.1 Special Bus Granting Mechanism The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mechanism reduces latency at first access of a burst or single transfer. This bus granting mechanism sets a different default master for every slave. At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can be associated with three kinds of default masters: no default master, last access master, and fixed default master. 66 32099A–AVR32–06/09 AT32UC3L To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface description. 8.4.1.1 No Default Master At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits low-power mode. Last Access Master At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access request. Fixed Default Master At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master, the fixed master does not change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related SCFG). Arbitration The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or more masters try to access the same slave at the same time. One arbiter per HSB slave is provided, thus arbitrating each slave differently. The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types for each slave: 1. Round-Robin Arbitration (default) 2. Fixed Priority Arbitration This is selected by the ARBT field in the Slave Configuration Registers (SCFG). Each algorithm may be complemented by selecting a default master configuration for each slave. When a re-arbitration must be done, specific conditions apply. This is described in “Arbitration Rules” . 8.4.2.1 Arbitration Rules Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently accessing it. 2. Single Cycles: When a slave is currently doing a single access. 3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. This is described below. 4. Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master access is too long and must be broken. This is described below. 8.4.1.2 8.4.1.3 8.4.2 67 32099A–AVR32–06/09 AT32UC3L • Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected among the following five possibilities: 1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken. 2. One beat bursts: Predicted end of burst is generated at each single transfer inside the INCP transfer. 3. Four beat bursts: Predicted end of burst is generated at the end of each four beat boundary inside INCR transfer. 4. Eight beat bursts: Predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer. 5. Sixteen beat bursts: Predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer. This selection can be done through the ULBT field in the Master Configuration Registers (MCFG). • Slot Cycle Limit Arbitration The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave Configuration Register (SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, halfword, or word transfer. 8.4.2.2 Round-Robin Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner. If two or more master requests arise at the same time, the master with the lowest number is first serviced, then the others are serviced in a round-robin manner. There are three round-robin algorithms implemented: 1. Round-Robin arbitration without default master 2. Round-Robin arbitration with last default master 3. Round-Robin arbitration with fixed default master • Round-Robin Arbitration without Default Master This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for masters that perform significant bursts. • Round-Robin Arbitration with Last Default Master This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. At the end of the cur68 32099A–AVR32–06/09 AT32UC3L rent transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses. • Round-Robin Arbitration with Fixed Default Master This is another biased round-robin algorithm. It allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master. Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will still get one latency cycle. This technique can be used for masters that mainly perform single accesses. 8.4.2.3 Fixed Priority Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master requests are active at the same time, the master with the highest priority number is serviced first. If two or more master requests with the same priority are active at the same time, the master with the highest number is serviced first. For each slave, the priority of each master may be defined through the Priority Registers for Slaves (PRAS and PRBS). 8.4.3 Slave and Master assignation The index number assigned to Bus Matrix slaves and masters are described in the Module Configuration section at the end of this chapter. 69 32099A–AVR32–06/09 AT32UC3L 8.5 User Interface HMATRICX Register Memory Map Register Master Configuration Register 0 Master Configuration Register 1 Master Configuration Register 2 Master Configuration Register 3 Master Configuration Register 4 Master Configuration Register 5 Master Configuration Register 6 Master Configuration Register 7 Master Configuration Register 8 Master Configuration Register 9 Master Configuration Register 10 Master Configuration Register 11 Master Configuration Register 12 Master Configuration Register 13 Master Configuration Register 14 Master Configuration Register 15 Slave Configuration Register 0 Slave Configuration Register 1 Slave Configuration Register 2 Slave Configuration Register 3 Slave Configuration Register 4 Slave Configuration Register 5 Slave Configuration Register 6 Slave Configuration Register 7 Slave Configuration Register 8 Slave Configuration Register 9 Slave Configuration Register 10 Slave Configuration Register 11 Slave Configuration Register 12 Slave Configuration Register 13 Slave Configuration Register 14 Slave Configuration Register 15 Priority Register A for Slave 0 Priority Register B for Slave 0 Priority Register A for Slave 1 Name MCFG0 MCFG1 MCFG2 MCFG3 MCFG4 MCFG5 MCFG6 MCFG7 MCFG8 MCFG9 MCFG10 MCFG11 MCFG12 MCFG13 MCFG14 MCFG15 SCFG0 SCFG1 SCFG2 SCFG3 SCFG4 SCFG5 SCFG6 SCFG7 SCFG8 SCFG9 SCFG10 SCFG11 SCFG12 SCFG13 SCFG14 SCFG15 PRAS0 PRBS0 PRAS1 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000002 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000010 0x00000000 0x00000000 0x00000000 Table 8-1. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 0x007C 0x0080 0x0084 0x0088 70 32099A–AVR32–06/09 AT32UC3L Table 8-1. Offset 0x008C 0x0090 0x0094 0x0098 0x009C 0x00A0 0x00A4 0x00A8 0x00AC 0x00B0 0x00B4 0x00B8 0x00BC 0x00C0 0x00C4 0x00C8 0x00CC 0x00D0 0x00D4 0x00D8 0x00DC 0x00E0 0x00E4 0x00E8 0x00EC 0x00F0 0x00F4 0x00F8 0x00FC 0x0110 0x0114 0x0118 0x011C 0x0120 0x0124 0x0128 HMATRICX Register Memory Map (Continued) Register Priority Register B for Slave 1 Priority Register A for Slave 2 Priority Register B for Slave 2 Priority Register A for Slave 3 Priority Register B for Slave 3 Priority Register A for Slave 4 Priority Register B for Slave 4 Priority Register A for Slave 5 Priority Register B for Slave 5 Priority Register A for Slave 6 Priority Register B for Slave 6 Priority Register A for Slave 7 Priority Register B for Slave 7 Priority Register A for Slave 8 Priority Register B for Slave 8 Priority Register A for Slave 9 Priority Register B for Slave 9 Priority Register A for Slave 10 Priority Register B for Slave 10 Priority Register A for Slave 11 Priority Register B for Slave 11 Priority Register A for Slave 12 Priority Register B for Slave 12 Priority Register A for Slave 13 Priority Register B for Slave 13 Priority Register A for Slave 14 Priority Register B for Slave 14 Priority Register A for Slave 15 Priority Register B for Slave 15 Special Function Register 0 Special Function Register 1 Special Function Register 2 Special Function Register 3 Special Function Register 4 Special Function Register 5 Special Function Register 6 Name PRBS1 PRAS2 PRBS2 PRAS3 PRBS3 PRAS4 PRBS4 PRAS5 PRBS5 PRAS6 PRBS6 PRAS7 PRBS7 PRAS8 PRBS8 PRAS9 PRBS9 PRAS10 PRBS10 PRAS11 PRBS11 PRAS12 PRBS12 PRAS13 PRBS13 PRAS14 PRBS14 PRAS15 PRBS15 SFR0 SFR1 SFR2 SFR3 SFR4 SFR5 SFR6 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 – – – – – – – 71 32099A–AVR32–06/09 AT32UC3L Table 8-1. Offset 0x012C 0x0130 0x0134 0x0138 0x013C 0x0140 0x0144 0x0148 0x014C HMATRICX Register Memory Map (Continued) Register Special Function Register 7 Special Function Register 8 Special Function Register 9 Special Function Register 10 Special Function Register 11 Special Function Register 12 Special Function Register 13 Special Function Register 14 Special Function Register 15 Name SFR7 SFR8 SFR9 SFR10 SFR11 SFR12 SFR13 SFR14 SFR15 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset Value – – – – – – – – – 72 32099A–AVR32–06/09 AT32UC3L 8.5.1 Name: Master Configuration Registers MCFG0...MCFG15 Read/Write 0x00 - 0x3C 0x00000002 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 25 – 17 – 9 – 1 ULBT 24 – 16 – 8 – 0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – • ULBT: Undefined Length Burst Type Table 8-2. ULBT 000 001 010 011 100 Undefined Length Burst Type Undefined Length Burst Type Inifinite Length Burst Single-Access 4 Beat Burst 8 Beat Burst 16 Beat Burst Description No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken. The undefined length burst is treated as a succession of single accesses, allowing rearbitration at each beat of the INCR burst. The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end. The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end. The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end. 73 32099A–AVR32–06/09 AT32UC3L 8.5.2 Name: Slave Configuration Registers SCFG0...SCFG15 Read/Write 0x40 - 0x7C 0x00000010 30 – 22 – 14 – 6 13 – 5 29 – 21 28 – 20 27 – 19 26 – 18 25 – 17 24 ARBT 16 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 FIXED_DEFMSTR 12 – 4 SLOT_CYCLE 11 – 3 10 – 2 DEFMSTR_TYPE 9 – 1 8 – 0 • ARBT: Arbitration Type 0: Round-Robin Arbitration 1: Fixed Priority Arbitration • FIXED_DEFMSTR: Fixed Default Master This is the number of the Default Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master which is not connected to the selected slave is equivalent to setting DEFMSTR_TYPE to 0. • DEFMSTR_TYPE: Default Master Type 0: No Default Master At the end of the current slave access, if no other master request is pending, the slave is disconnected from all masters. This results in a one cycle latency for the first access of a burst transfer or for a single access. 1: Last Default Master At the end of the current slave access, if no other master request is pending, the slave stays connected to the last master having accessed it. This results in not having one cycle latency when the last master tries to access the slave again. 2: Fixed Default Master At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master the number that has been written in the FIXED_DEFMSTR field. This results in not having one cycle latency when the fixed master tries to access the slave again. • SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave. This limit has been placed to avoid locking a very slow slave when very long bursts are used. This limit must not be very small. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE. 74 32099A–AVR32–06/09 AT32UC3L 8.5.3 Bus Matrix Priority Registers A For Slaves Register Name: PRAS0...PRAS15 Access Type: Offset: Reset Value: 31 Read/Write 0x00000000 30 M7PR 29 28 27 26 M6PR 21 M5PR 20 19 18 M4PR 13 M3PR 12 11 10 M2PR 5 M1PR 4 3 2 M0PR 1 0 9 8 17 16 25 24 23 22 15 14 7 6 • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 75 32099A–AVR32–06/09 AT32UC3L 8.5.4 Name: Priority Registers B For Slaves PRBS0...PRBS15 Read/Write 0x00000000 30 M15PR 23 22 M13PR 15 14 M11PR 7 6 M9PR 5 4 3 2 M8PR 13 12 11 10 M10PR 1 0 21 20 19 18 M12PR 9 8 29 28 27 26 M14PR 17 16 25 24 Access Type: Offset: Reset Value: 31 • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority. 76 32099A–AVR32–06/09 AT32UC3L 8.5.5 Name: Special Function Registers SFR0...SFR15 Read/Write 0x110 - 0x14C 30 29 28 SFR 23 22 21 20 SFR 15 14 13 12 SFR 7 6 5 4 SFR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Access Type: Offset: Reset Value: 31 • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used. 77 32099A–AVR32–06/09 AT32UC3L 8.6 8.6.1 Module Configuration Bus Matrix Connections The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0 register is associated with the CPU Data master interface. Table 8-3. Master 0 Master 1 Master 2 Master 3 Master 4 High Speed Bus Masters CPU Data CPU Instruction CPU SAB PDCA SAU Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is associated with the Internal SRAM Slave Interface. Accesses to unused areas returns an error result to the master requesting such an access. Table 8-4. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 High Speed Bus Slaves Internal Flash HSB-PB Bridge 0 HSB-PB Bridge 1 Internal SRAM SAU 78 32099A–AVR32–06/09 AT32UC3L Figure 8-1. HMatrix Master / Slave Connections HMATRIX SLAVES Internal SRAM Internal Flash HSB-PB Bridge 0 HSB-PB Bridge 1 0 1 2 3 CPU Data 0 HMATRIX MASTERS CPU Instruction 1 CPU SAB 2 PDCA 3 SAU 4 SAU 4 79 32099A–AVR32–06/09 AT32UC3L 9. Secure Access Unit (SAU) Rev 1.1.0.0 9.1 Features • Remaps registers in memory regions protected by the MPU to regions not protected by the MPU • Programmable physical address for each channel • Two modes of operation: Locked and Open – In Locked Mode, access to a channel must be preceded by an unlock action • An unlocked channel remains open only for a specific amount of time, if no access is performed during this time, the channel is relocked • Only one channel can be open at a time, opening a channel while another one is open locks the first one • Access to a locked channel is denied, a bus error and optionally an interrupt is returned • If a channel is relocked due to an unlock timeout, an interrupt can optionally be generated – In Open Mode, all channels are permanently unlocked 9.2 Overview In many systems, erroneous access to peripherals can lead to catastrophic failure. An example of such a peripheral is the Pulse Width Modulator (PWM) used to control electric motors. The PWM outputs a pulse train that controls the motor. If the control registers of the PWM module are inadvertently updated with wrong values, the motor can start operating out of control, possibly causing damage to the application and the surrounding environment. However, sometimes the PWM control registers must be updated with new values, for example when modifying the pulse train to accelerate the motor. A mechanism must be used to protect the PWM control registers from inadvertent access caused by for example: • Errors in the software code • Transient errors in the CPU caused by for example electrical noise altering the execution path of the program To improve the security in a computer system, the AVR32UC3 implements a Memory Protection Unit (MPU). The MPU can be set up to limit the accesses that can be performed to specific memory addresses. The MPU divides the memory space into regions, and assigns a set of access restrictions on each region. Access restrictions can for example be read/write if the CPU is in supervisor mode, and read-only if the CPU is in application mode. The regions can be of different size, but each region is usually quite large, e.g. protecting 1 kilobyte of address space or more. Furthermore, access to each region is often controlled by the execution state of the CPU, i.e. supervisor or application mode. Such a simple control mechanism is often too inflexible (too coarse-grained chunks) and with too much overhead (often requiring system calls to access protected memory locations) for simple or real-time systems such as embedded microcontrollers. Usually, the Secure Access Unit (SAU) is used together with the MPU to provide the required security and integrity. The MPU is set up to protect regions of memory, while the SAU is set up to provide a secure channel into specific memory locations that are protected by the MPU. These specific locations can be thought of as fine-grained overrides of the general coarsegrained protection provided by the MPU. 80 32099A–AVR32–06/09 AT32UC3L 9.3 Block Diagram Figure 9-1 presents the SAU integrated in an example system with a CPU, some memories, some peripherals, and a bus system. The SAU is connected to both the Peripheral Bus (PB) and the High Speed Bus (HSB). Configuration of the SAU is done via the PB, while memory accesses are done via the HSB. The SAU receives an access on its HSB slave interface, remaps it, checks that the channel is unlocked, and if so, initiates a transfer on its HSB master interface to the remapped address. The thin arrows in Figure 9-1 exemplifies control flow when using the SAU. The CPU wants to read the RX Buffer in the USART. The MPU has been configured to protect all registers in the USART from user mode access, while the SAU has been configured to remap the RX Buffer into a memory space that is not protected by the MPU. This unprotected memory space is mapped into the SAU HSB slave space. When the CPU reads the appropriate address in the SAU, the SAU will perform an access to the desired RX buffer register in the USART, and thereafter return the read results to the CPU. The return data flow will follow the opposite direction of the control flow arrows in Figure 9-1. Figure 9-1. SAU Block Diagram CPU MPU Flash RAM Bus master Bus slave Bus slave High Speed Bus Bus slave Bus master Bus slave Bus bridge SAU Channel SAU Configuration SAU Interrupt request PWM Peripheral Bus USART 81 32099A–AVR32–06/09 AT32UC3L 9.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 9.4.1 Power Management If the CPU enters a sleep mode that disables clocks used by the SAU, the SAU will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The SAU has two bus clocks connected: One High Speed Bus clock (CLK_SAU_HSB) and one Peripheral Bus clock (CLK_SAU_PB). These clocks are generated by the Power Manager. Both clocks are enabled at reset, and can be disabled by writing to the Power Manager. The user has to ensure that CLK_SAU_HSB is not turned off before accessing the SAU. Likewise, the user must ensure that no bus access is pending in the SAU before disabling CLK_SAU_HSB. Failing to do so may deadlock the High Speed Bus. 9.4.3 Interrupt The SAU interrupt request line is connected to the interrupt controller. Using the SAU interrupt requires the interrupt controller to be programmed first. 9.4.4 Debug Operation When an external debugger forces the CPU into debug mode, the SAU continues normal operation. If the SAU is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 9.4.2 9.5 9.5.1 Functional Description Enabling the SAU The SAU is enabled by writing a one to the Enable (EN) bit in the Control Register (CR). This will set the SAU Enabled (EN) bit in the Status Register (SR). Configuring the SAU Channels The SAU has a set of channels, mapped in the HSB memory space. These channels can be configured by a Remap Target Register (RTR), located at the same memory address. When the SAU is in normal mode, the SAU channel is addressed, and when the SAU is in setup mode, the RTR can be addressed. Before the SAU can be used, the channels must be configured and enabled. To configure a channel, the corresponding RTR must be programmed with the Remap Target Address. To do this, make sure the SAU is in setup mode by writing a one to the Setup Mode Enable (SEN) bit in CR. This makes sure that a write to the RTR address accesses the RTR, not the SAU channel. Thereafter, the RTR is written with the address to remap to, typically the address of a specific PB register. When all channels have been configured, return to normal mode by writing a one to the Setup Mode Disable (SDIS) in CR. The channels can now be enabled by writing ones to the corresponding bits in the Channel Enable Registers (CERH/L). The SAU is only able to remap addresses above 0xFFFC0000. 9.5.2 82 32099A–AVR32–06/09 AT32UC3L 9.5.2.1 Protecting SAU configuration registers In order to prevent the SAU configuration registers to be changed by malicious or runaway code, they should be protected by the MPU as soon as they have been configured. Maximum security is provided in the system if program memory does not contain any code to unprotect the configuration registers in the MPU. This guarantees that runaway code can not accidentally unprotect and thereafter change the SAU configuration registers. Lock Mechanism The SAU can be configured to use two different access mechanisms: Open and Locked. In Open Mode, SAU channels can be accessed freely after they have been configured and enabled. In order to prevent accidental accesses to remapped addresses, it is possible to configure the SAU in Locked Mode. Writing a one to the Open Mode bit in the CONFIG register (CONFIG.OPEN) will enable Open Mode. Writing a zero to CONFIG.OPEN will enable Locked Mode. When using Locked Mode, the lock mechanism must be configured by writing a user defined key value to the Unlock Key (UKEY) field in the Configuration Register (CONFIG). The number of CLK_SAU_HSB cycles the channel remains unlocked must be written to the Unlock Number of Clock Cycles (UCYC) field in CONFIG. Access control to the SAU channels is enabled by means of the Unlock Register (UR), which resides in the same address space as the SAU channels. Before a channel can be accessed, the unlock key value must be written to UR.KEY, and the channel number to UR.CHANNEL. Access to the channel is then permitted for the next CONFIG.UCYC clock cycles, or until a successful access to the unlocked channel has been made. Only one channel can be unlocked at a time. If any other channel is unlocked at the time of writing UR, this channel will be automatically locked before the channel addressed by the UR write is unlocked. An attempted access to a locked channel will be aborted, and the Channel Access Unsuccessful bit (SR.CAU) will be set. Any pending errors bits in SR must be cleared before it is possible to access UR. The following SR bits are defined as error bits: EXP, CAU, URREAD, URKEY, URES, MBERROR, RTRADR. If any of these bits are set while writing to UR, the write is aborted and the Unlock Register Error Status (URES) bit in SR is set. 9.5.4 Normal Operation The following sequence must be used in order to access a SAU channel in normal operation (CR.SEN=0): 1. If not in Open Mode, write the unlock key to UR.KEY and the channel number to UR.CHANNEL. 2. Perform the read or write operation to the SAU channel. If not in Open Mode, this must be done within CONFIG.UCYC clock cycles of unlocking the channel. The SAU will use its HSB master interface to remap the access to the target address pointed to by the corresponding RTR. 3. To confirm that the access was successful, wait for the IDLE transfer status bit (SR.IDLE) to indicate the operation is completed. Then check SR for possible error conditions. The SAU can be configured to generate interrupt requests or a Bus Error Exception if the access failed. 9.5.3 83 32099A–AVR32–06/09 AT32UC3L 9.5.4.1 Operation example Figure 9-2 shows a typical memory map, consisting of some memories, some simple peripherals, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU has been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has no way of accessing for example the Transmit Holding register in the UART, present on address X on the bus. Note that the SAU RTRs are not protected by the MPU, thus the RTRs can be accessed. If for example RTR0 is configured to point to address X, an access to RTR0 will be remapped by the SAU to address X according to the algorithm presented above. By programming the SAU RTRs, specific addresses in modules that have generally been protected by the MPU can be performed. Figure 9-2. Example Memory Map for a System with SAU SAU CONFIG UART Receive Holding Transmit Holding Baudrate Control Address X UR RTR62 SAU CHANNEL ... Channel 1 RTR1 RTR0 Address Z 9.5.5 Interrupts The SAU can generate an interrupt request to signal different events. All events that can generate an interrupt request have dedicated bits in the Status Register (SR). An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a one to the corresponding bit in the Interrupt Clear Register (ICR). The following SR bits are used for signalling the result of SAU accesses: • RTR Address Error (RTRADR) is set if an illegal address is written to the RTRs. Only addresses in the range 0xFFFC0000-0xFFFFFFFF are allowed. • Master Interface Bus Error (MBERROR) is set if any of the conditions listed in Section 9.5.7 occurred. 84 32099A–AVR32–06/09 AT32UC3L • Unlock Register Error Status (URES) is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits in SR were set (see Section 9.5.6). The unlock operation was aborted. • Unlock Register Key Error (URKEY) is set if the Unlock Register was attempted written with an invalid key. • Unlock Register Read (URREAD) is set if the Unlock Register was attempted read. • Channel Access Unsuccessful (CAU) is set if the channel access was unsuccessful. • Channel Access Successful (CAS) is set if the channel access was successful. • Channel Unlock Expired (EXP) is set if the channel lock expired, with no channel being accessed after the channel was unlocked. 9.5.6 Error bits If error bits are set when attempting to unlock a channel, SR.URES will be set. The following SR bits are considered error bits: • EXP • CAU • URREAD • URKEY • URES • MBERROR • RTRADR 9.5.7 Bus Error Responses By writing a one to the Bus Error Response Enable bit (CR.BERREN), serious access errors will be configured to return a bus error to the CPU. This will cause the CPU to execute its Bus Error Data Fetch exception routine. The conditions that can generate a bus error response are: • Reading the Unlock Register • Trying to access a locked channel • The SAU HSB master receiving a bus error response from its addressed slave 9.5.8 Disabling the SAU To disable the SAU, the user must first ensure that no SAU bus operations are pending. This can be done by checking that the STATUS.IDLE bit is set. The SAU may then be disabled by writing a one to the Disable (DIS) bit in CR. 85 32099A–AVR32–06/09 AT32UC3L 9.6 User Interface The following addresses are used by SAU channel configuration registers. All offsets are relative to the SAU’s PB base address. Table 9-1. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 Note: SAU Configuration Register Memory Map Register Control Register Configuration Register Channel Enable Register High Channel Enable Register Low Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Clear Register Parameter Register Version Register Register Name CR CONFIG CERH CERL SR IER IDR IMR ICR PARAMETER VERSION Access Write-only Write-only Read/Write Read/Write Read-only Write-only Write-only Read-only Write-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) -(1) 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. The following addresses are used by SAU channel registers. All offsets are relative to the SAU’s HSB base address. The number of channels implemented is device specific, refer to the Module Configuration section at the end of this chapter. Table 9-2. Offset 0x00 0x04 0x08 ... 0x04*n 0xFC SAU Channel Register Memory Map Register Remap Target Register 0 Remap Target Register 1 Remap Target Register 2 ... Remap Target Register n Unlock Register Register Name RTR0 RTR1 RTR2 ... RTRn UR Access Read/Write Read/Write Read/Write ... Read/Write Write-only Reset N/A N/A N/A ... N/A N/A 86 32099A–AVR32–06/09 AT32UC3L 9.6.1 Name: Control Register CR Write-only 0x00 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 BERRDIS 4 BERREN 3 SDIS 2 SEN 1 DIS 0 EN • BERRDIS: Bus Error Response Disable Writing a zero to this bit has no effect. Writing a one to this bit disables Bus Error Response from the SAU. • BERREN: Bus Error Response Enable Writing a zero to this bit has no effect. Writing a one to this bit enables Bus Error Response from the SAU. • SDIS: Setup Mode Disable Writing a zero to this bit has no effect. Writing a one to this bit exits setup mode. • SEN: Setup Mode Enable Writing a zero to this bit has no effect. Writing a one to this bit enters setup mode. • DIS: SAU Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the SAU. • EN: SAU Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the SAU. 87 32099A–AVR32–06/09 AT32UC3L 9.6.2 Name: Configuration Register CONFIG Write-only 0x04 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 UCYC 11 10 9 8 7 6 5 4 UKEY 3 2 1 0 • UCYC: Unlock Number of Clock Cycles Once a channel has been unlocked, it remains unlocked for this amount of CLK_SAU_HSB clock cycles or until one access to a channel has been made. • UKEY: Unlock Key The value in this register must be written into UR.KEY to unlock a channel. 88 32099A–AVR32–06/09 AT32UC3L 9.6.3 Name: Channel Enable Register High CERH Read/Write 0x08 0x00000000 30 29 28 CERH[24:30] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 CERH[23:16] 19 18 17 16 15 14 13 12 CERH[15:8] 11 10 9 8 7 6 5 4 CERH[7:0] 3 2 1 0 • CERH[n]: Channel Enable Register High 0: Channel (n+32) is not enabled. 1: Channel (n+32) is enabled. 89 32099A–AVR32–06/09 AT32UC3L 9.6.4 Name: Channel Enable Register Low CERL Read/Write 0x0C 0x00000000 30 29 28 CERL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 CERL[23:16] 19 18 17 16 15 14 13 12 CERL[15:8] 11 10 9 8 7 6 5 4 CERL[7:0] 3 2 1 0 • CERL[n]: Channel Enable Register Low 0: Channel n is not enabled. 1: Channel n is enabled. 90 32099A–AVR32–06/09 AT32UC3L 9.6.5 Name: Status Register SR Read-only 0x10 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 SEN 8 EN 7 RTRADR 6 MBERROR 5 URES 4 URKEY 3 URREAD 2 CAU 1 CAS 0 EXP • SEN: SAU Setup Mode Enable This bit is cleared when the SAU exits setup mode. This bit is set when the SAU enters setup mode. • EN: SAU Enabled This bit is cleared when the SAU is disabled. This bit is set when the SAU is enabled. • RTRADR: RTR Address Error This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if, in the configuration phase, an RTR was written with an illegal address, i.e. the upper 16 bits in the address were different from 0xFFFC, 0xFFFD, 0xFFFE or 0xFFFF. • MBERROR: Master Interface Bus Error This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if a channel access generated a transfer on the master interface that received a bus error response from the addressed slave. • URES: Unlock Register Error Status This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits were set in SR. The unlock operation was aborted. • URKEY: Unlock Register Key Error This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if the Unlock Register was attempted written with an invalid key. • URREAD: Unlock Register Read This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if the Unlock Register was read. • CAU: Channel Access Unsuccessful This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel access was unsuccessful, i.e. an access was attempted to a locked or disabled channel. 91 32099A–AVR32–06/09 AT32UC3L • CAS: Channel Access Successful This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel access successful, i.e. one access was made after the channel was unlocked. • EXP: Channel Unlock Expired This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel unlock has expired, i.e. no access being made after the channel was unlocked. 92 32099A–AVR32–06/09 AT32UC3L 9.6.6 Name: Interrupt Enable Register IER Write-only 0x14 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 RTRADR 6 MBERROR 5 URES 4 URKEY 3 URREAD 2 CAU 1 CAS 0 EXP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 93 32099A–AVR32–06/09 AT32UC3L 9.6.7 Name: Interrupt Disable Register IDR Write-only 0x18 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 RTRADR 6 MBERROR 5 URES 4 URKEY 3 URREAD 2 CAU 1 CAS 0 EXP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 94 32099A–AVR32–06/09 AT32UC3L 9.6.8 Name: Interrupt Mask Register IMR Read-only 0x1C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 RTRADR 6 MBERROR 5 URES 4 URKEY 3 URREAD 2 CAU 1 CAS 0 EXP 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 95 32099A–AVR32–06/09 AT32UC3L 9.6.9 Name: Interrupt Clear Register ICR Write-only 0x20 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 RTRADR 6 MBERROR 5 URES 4 URKEY 3 URREAD 2 CAU 1 CAS 0 EXP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and any corresponding interrupt request. 96 32099A–AVR32–06/09 AT32UC3L 9.6.10 Name: Parameter Register PARAMETER Read-only 0x24 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 4 3 CHANNELS 2 1 0 • CHANNELS: Number of channels implemented 97 32099A–AVR32–06/09 AT32UC3L 9.6.11 Name: Version Register VERSION Write-only 0x28 - Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 26 18 VARIANT 25 17 24 16 11 10 9 8 VERSION[11:8] 3 VERSION[7:0] 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 98 32099A–AVR32–06/09 AT32UC3L 9.6.12 Name: Remap Target Register n RTRn Read/Write n*4 0x00000000 30 29 28 RTR[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 RTR[23:16] 19 18 17 16 15 14 13 12 RTR[15:8] 11 10 9 8 7 6 5 4 RTR[7:0] 3 2 1 0 • RTR: Remap Target Address for Channel n RTR[31:16] must have one of the following values, any other value will result in UNDEFINED behavior: 0xFFFC 0xFFFD 0xFFFE 0xFFFF RTR[1:0] must be written to 0, any other value will result in UNDEFINED behavior. 99 32099A–AVR32–06/09 AT32UC3L 9.6.13 Name: Unlock Register UR Write-only 0xFC 0x00000000 30 29 28 27 26 25 24 Access Type : Offset: Reset Value: 31 23 22 21 20 - 19 18 17 16 15 14 13 12 KEY 11 10 9 8 7 - 6 - 5 4 3 CHANNEL 2 1 0 • KEY The correct key must be written in order to unlock a channel. The key value written must correspond to the key value defined in CONFIG.UKEY. • CHANNEL Number of the channel to unlock. 100 32099A–AVR32–06/09 AT32UC3L 101 32099A–AVR32–06/09 AT32UC3L 102 32099A–AVR32–06/09 AT32UC3L 9.7 Module Configuration The specific configuration for each SAU instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 9-3. Feature SAU Channels Module configuration SAU 16 Table 9-4. Module name SAU SAU Module clock name Clock name CLK_SAU_HSB CLK_SAU_PB Table 9-5. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000110 0x00000010 103 32099A–AVR32–06/09 AT32UC3L 10. Peripheral DMA Controller (PDCA) Rev: 1.2.2.0 10.1 Features • • • • • • Multiple channels Generates transfers to/from peripherals such as USARTand SPI Two address pointers/counters per channel allowing double buffering Performance monitors to measure average and maximum transfer latency Optional synchronizing of data transfers with extenal peripheral events Ring buffer functionality 10.2 Overview The Peripheral DMA Controller (PDCA) transfers data between on-chip peripheral modules such as USART, SPI and memories (those memories may be on- and off-chip memories). Using the PDCA avoids CPU intervention for data transfers, improving the performance of the microcontroller. The PDCA can transfer data from memory to a peripheral or from a peripheral to memory. The PDCA consists of multiple DMA channels. Each channel has: • A Peripheral Select Register • A 32-bit memory pointer • A 16-bit transfer counter • A 32-bit memory pointer reload value • A 16-bit transfer counter reload value The PDCA communicates with the peripheral modules over a set of handshake interfaces. The peripheral signals the PDCA when it is ready to receive or transmit data. The PDCA acknowledges the request when the transmission has started. When a transmit buffer is empty or a receive buffer is full, an optional interrupt request can be generated. 104 32099A–AVR32–06/09 AT32UC3L 10.3 Block Diagram Figure 10-1. PDCA Block Diagram Peripheral 0 HSB to PB Bridge HSB Peripheral Bus Peripheral 1 High Speed Bus Matrix HSB Peripheral 2 Peripheral DMA Controller (PDCA) Interrupt Controller IRQ Peripheral (n-1) Handshake Interfaces ... 10.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 10.4.1 Power Management If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The PDCA has two bus clocks connected: One High Speed Bus clock (CLK_PDCA_HSB) and one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Manager. Both clocks are enabled at reset, and can be disabled by writing to the Power Manager. It is recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in an undefined state. 10.4.2 10.4.3 Interrupts The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA interrupts requires the interrupt controller to be programmed first. 105 32099A–AVR32–06/09 AT32UC3L 10.4.4 Peripheral Events The PDCA peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 10.5 10.5.1 Functional Description Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer. In this section the steps necessary to configure one PDCA channel is outlined. The peripheral to transfer data to or from must be configured correctly in the Peripheral Select Register (PSR). This is performed by writing the Peripheral Identity (PID) value for the corresponding peripheral to the PID field in the PSR register. The PID also encodes the transfer direction, i.e. memory to peripheral or peripheral to memory. See Section 10.5.6. The transfer size must be written to the Transfer Size field in the Mode Register (MR.SIZE). The size must match the data size produced or consumed by the selected peripheral. See Section 10.5.7. The memory address to transfer to or from, depending on the PSR, must be written to the Memory Address Register (MAR). For each transfer the memory address is increased by either a one, two or four, depending on the size set in MR. See Section 10.5.2. The number of data items to transfer is written to the TCR register. If the PDCA channel is enabled, a transfer will start immediately after writing a non-zero value to TCR or the reload version of TCR, TCRR. After each transfer the TCR value is decreased by one. Both MAR and TCR can be read while the PDCA channel is active to monitor the DMA progress. See Section 10.5.3. The channel must be enabled for a transfer to start. A channel is enable by writing a one to the EN bit in the Control Register (CR). 10.5.2 Memory Pointer Each channel has a 32-bit Memory Address Register (MAR). This register holds the memory address for the next transfer to be performed. The register is automatically updated after each transfer. The address will be increased by either one, two or four depending on the size of the DMA transfer (byte, halfword or word). The MAR can be read at any time during transfer. Transfer Counter Each channel has a 16-bit Transfer Counter Register (TCR). This register must be programmed with the number of transfers to be performed. The TCR register should contain the number of data items to be transferred independently of the transfer size. The TCR can be read at any time during transfer to see the number of remaining transfers. Reload Registers Both the MAR and the TCR have a reload register, respectively Memory Address Reload Register (MARR) and Transfer Counter Reload Register (TCRR). These registers provide the possibility for the PDCA to work on two memory buffers for each channel. When one buffer has completed, MAR and TCR will be reloaded with the values in MARR and TCRR. The reload logic is always enabled and will trigger if the TCR reaches zero while TCRR holds a non-zero value. 10.5.3 10.5.4 106 32099A–AVR32–06/09 AT32UC3L If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the value written in TCRR and MARR. 10.5.5 Ring Buffer When Ring Buffer mode is enabled the TCRR and MARR registers will not be cleared when TCR and MAR registers reload. This allows the PDCA to read or write to the same memory region over and over again until the transfer is actively stopped by the user. Ring Buffer mode is enabled by writing a one to the Ring Buffer bit in the Mode Register (MR.RING). 10.5.6 Peripheral Selection The Peripheral Select Register (PSR) decides which peripheral should be connected to the PDCA channel. A peripheral is selected by writing the corresponding Peripheral Identity (PID) to the PID field in the PST register. Writing the PID will both select the direction of the transfer (memory to peripheral or peripheral to memory), which handshake interface to use, and the address of the peripheral holding register. Refer to the Peripheral Identity (PID) table in the Module Configuration section for the peripheral PID values. Transfer Size The transfer size can be set individually for each channel to be either byte, halfword or word (8bit, 16-bit or 32-bit respectively). Transfer size is set by writing the desired value to the Transfer Size field in the Mode Register (MR.SIZE). When the PDCA moves data between peripherals and memory, data is automatically sized and aligned. When memory is accessed, the size specified in MR.SIZE and system alignment is used. When a peripheral register is accessed the data to be transferred is converted to a word where bit n in the data corresponds to bit n in the peripheral register. If the transfer size is byte or halfword, bits greater than 8 and16 respectively are set to zero. Refer to the Module Configuration section for information regarding what peripheral registers are used for the differen peripherals and then to the peripheral specific chapter for information about the size option available for the different registers. 10.5.8 Enabling and Disabling Each DMA channel is enabled by writing a one to the Transfer Enable bit in the Control Register (CR.TEN) and disabled by writing a one to the Transfer Disable bit (CR.TDIS). The current status can be read from the Status Register (SR). While the PDCA channel is enabled all DMA request will be handled as long the TCR and TCRR is not zero. 10.5.9 Interrupts Interrupts can be enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The Interrupt Mask Register (IMR) can be read to see whether an interrupt is enabled or not. The current status of an interrupt source can be read through the Interrupt Status Register (ISR). The PDCA has three interrupt sources: • Reload Counter Zero - The TCRR register is zero. • Transfer Finished - Both the TCR and TCRR registers are zero. • Transfer Error - An error has occurred in accessing memory. 10.5.7 107 32099A–AVR32–06/09 AT32UC3L 10.5.10 Priority If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest priority. 10.5.11 Error Handling If the Memory Address Register (MAR) is set to point to an invalid location in memory, an error will occur when the PDCA tries to perform a transfer. When an error occurs, the Transfer Error bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the error will be stopped. In order to restart the channel, the user must program the Memory Address Register to a valid address and then write a one to the Error Clear bit in the Control Register (CR.ECLR). If the Transfer Error interrupt is enabled, an interrupt request will be generated when an transfer error occurs. 10.5.12 Peripheral Event Trigger Peripheral events can be used to trigger PDCA channel transfers. Peripheral Event synchronizations are enabled by writing a one to the Event Trigger bit in the Mode Register (MR.ETRIG). When set, all DMA requests will be blocked until an peripheral event is received. For each peripheral event received, only one data item is transferred. If no DMA requests are pending when a peripheral event is received, the PDCA will start a transfer as soon as a peripheral event is detected. If multiple events arrive while the PDCA channel is busy transferring data, an overflow condition will be signaled in the Peripheral Event System. Refer to the Peripheral Event System chapter for more information. 10.6 Performance Monitors Two performance monitors allow the user to measure the activity and stall cycles for PDCA transfers. To monitor a PDCA channel, the corresponding channel number must be written to one of the MONnCH fields in the Performance Control Register (PCONTROL) and a one must be written to the corresponding CHnEN bit in the same register. Due to performance monitor hardware resource sharing, the two monitor channels should NOT be programmed to monitor the same PDCA channel. This may result in UNDEFINED performance monitor behavior. 10.6.1 Measuring mechanisms Three different parameters can be measured by each channel: • The number of data transfer cycles since last channel reset, both for read and write • The number of stall cycles since last channel reset, both for read and write • The maximum latency since last channel reset, both for read and write These measurements can be extracted by software and used to generate indicators for bus latency, bus load, and maximum bus latency. Each of the counters has a fixed width, and may therefore overflow. When an overflow is encountered in either the Performance Channel Data Read/Write Cycle registers (PRDATAn and PWDATAn) or the Performance Channel Read/Write Stall Cycles registers (PRSTALLn and PWSTALLn) of a channel, all registers in the channel are reset. This behavior is altered if the Channel Overflow Freeze bit is one in the Performance Control register (PCONTROL.CHnOVF). If this bit is one, the channel registers are frozen when either DATA or STALL reaches its maximum value. This simplifies one-shot readout of the counter values. 108 32099A–AVR32–06/09 AT32UC3L The registers can also be manually reset by writing a one to the Channel Reset bit in the PCONTROL register (PCONTROL.CHnRES). The Performance Channel Read/Write Latency registers (PRLATn and PWLATn) are saturating when their maximum count value is reached. The PRLATn and PWLATn registers are reset only by writing a one to the CHnRES in PCONTROL. A counter must manually be enabled by writing a one to the Channel Enable bit in the Performance Control Register (PCONTROL.CHnEN). 109 32099A–AVR32–06/09 AT32UC3L 10.7 10.7.1 User Interface Memory Map Overview PDCA Register Memory Map Contents DMA channel 0 configuration registers DMA channel 1 configuration registers ... DMA channel m configuration registers Performance Monitor registers Version register Table 10-1. Address Range 0x000 - 0x03F 0x040 - 0x07F ... (0x000 - 0x03F)+m*0x040 0x800-0x830 0x834 10.7.2 Channel Memory Map PDCA Channel Configuration Registers Register Memory Address Register Peripheral Select Register Transfer Counter Register Memory Address Reload Register Transfer Counter Reload Register Control Register Mode Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Register Name MAR PSR TCR MARR TCRR CR MR SR IER IDR IMR ISR Access Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Read/Write Read-only Write-only Write-only Read-only Read-only Reset 0x00000000 - (1) 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 10-2. Offset 0x000 + n*0x040 0x004 + n*0x040 0x008 + n*0x040 0x00C + n*0x040 0x010 + n*0x040 0x014 + n*0x040 0x018 + n*0x040 0x01C + n*0x040 0x020 + n*0x040 0x024 + n*0x040 0x028 + n*0x040 0x02C + n*0x040 10.7.3 Performance Monitor Memory Map PDCA Performance Monitor Registers Register Performance Control Register Channel0 Read Data Cycles Channel0 Read Stall Cycles Channel0 Read Max Latency Channel0 Write Data Cycles Channel0 Write Stall Cycles Channel0 Write Max Latency Register Name PCONTROL PRDATA0 PRSTALL0 PRLAT0 PWDATA0 PWSTALL0 PWLAT0 Access Read/Write Read-only Read-only Read-only Read-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 10-3. Offset 0x800 0x804 0x808 0x80C 0x810 0x814 0x818 110 32099A–AVR32–06/09 AT32UC3L Table 10-3. Offset 0x81C 0x820 0x824 0x828 0x82C 0x830 PDCA Performance Monitor Registers Register Channel1 Read Data Cycles Channel1 Read Stall Cycles Channel1 Read Max Latency Channel1 Write Data Cycles Channel1 Write Stall Cycles Channel1 Write Max Latency Register Name PRDATA1 PRSTALL1 PRLAT1 PWDATA1 PWSTALL1 PWLAT1 Access Read-only Read-only Read-only Read-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 10.7.4 Version Register Memory Map PDCA Version Register Memory Map Register Version Register Register Name VERSION Access Read-only Reset - (1) Table 10-4. Offset 0x834 Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 111 32099A–AVR32–06/09 AT32UC3L 10.7.5 Name: Memory Address Register MAR Read/Write 0x000 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 MADDR[31:24] 23 22 21 20 19 18 17 16 MADDR[23:16] 15 14 13 12 MADDR[15:8] 11 10 9 8 7 6 5 4 MADDR[7:0] 3 2 1 0 • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA. During transfer, MADDR will point to the next memory location to be read/written. 112 32099A–AVR32–06/09 AT32UC3L 10.7.6 Name: Peripheral Select Register PSR Read/Write 0x004 + n*0x040 - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 PID 3 2 1 0 • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel. Writing a PID will select both which handshake interface to use, the direction of the transfer and also the address of the Receive/Transfer Holding Register for the peripheral. See the module configuration section of PDCA for details. The width of the PID field is device specific and dependent on the number of peripheral modules in the device. 113 32099A–AVR32–06/09 AT32UC3L 10.7.7 Name: Transfer Counter Register TCR Read/Write 0x008 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 TCV[15:8] 11 10 9 8 7 6 5 4 TCV[7:0] 3 2 1 0 • TCV: Transfer Counter Value Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made. During transfer, TCV contains the number of remaining transfers to be done. 114 32099A–AVR32–06/09 AT32UC3L 10.7.8 Name: Memory Address Reload Register MARR Read/Write 0x00C + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 MARV[31:24] 27 26 25 24 23 22 21 20 MARV[23:16] 19 18 17 16 15 14 13 12 MARV[15:8] 11 10 9 8 7 6 5 4 MARV[7:0] 3 2 1 0 • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a nonzero value. 115 32099A–AVR32–06/09 AT32UC3L 10.7.9 Name: Transfer Counter Reload Register TCRR Read/Write 0x010 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 TCRV[15:8] 11 10 9 8 7 6 5 4 TCRV[7:0] 3 2 1 0 • TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value. If TCRV is zero, no more transfers will be performed for the channel. When TCR is reloaded, the TCRR register is cleared. 116 32099A–AVR32–06/09 AT32UC3L 10.7.10 Name: Control Register CR Write-only 0x014 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 ECLR 7 - 6 - 5 - 4 - 3 - 2 - 1 TDIS 0 TEN • ECLR: Transfer Error Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the Transfer Error bit in the Status Register (SR.TERR). Clearing the SR.TERR bit will allow the channel to transmit data. The memory address must first be set to point to a valid location. • TDIS: Transfer Disable Writing a zero to this bit has no effect. Writing a one to this bit will disable transfer for the DMA channel. • TEN: Transfer Enable Writing a zero to this bit has no effect. Writing a one to this bit will enable transfer for the DMA channel. 117 32099A–AVR32–06/09 AT32UC3L 10.7.11 Name: Mode Register MR Read/Write 0x018 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 RING 2 ETRIG 1 SIZE 0 • RING: Ring Buffer 0:The Ring buffer functionality is disabled. 1:The Ring buffer functionality is enabled. When enabled, the reload registers, MARR and TCRR will not be cleared after reload. • ETRIG: Event Trigger 0:Start transfer when the peripheral selected in Peripheral Select Register (PSR) requests a transfer. 1:Start transfer only when or after a peripheral event is received. • SIZE: Size of Transfer Table 10-5. SIZE 0 1 2 3 Size of Transfer Size of Transfer Byte Halfword Word Reserved 118 32099A–AVR32–06/09 AT32UC3L 10.7.12 Name: Status Register SR Read-only 0x01C + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 TEN • TEN: Transfer Enabled This bit is cleared when the TDIS bit in CR is written to one. This bit is set when the TEN bit in CR is written to one. 0: Transfer is disabled for the DMA channel. 1: Transfer is enabled for the DMA channel. 119 32099A–AVR32–06/09 AT32UC3L 10.7.13 Name: Interrupt Enable Register IER Write-only 0x020 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TERR 1 TRC 0 RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 120 32099A–AVR32–06/09 AT32UC3L 10.7.14 Name: Interrupt Disable Register IDR Write-only 0x024 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TERR 1 TRC 0 RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 121 32099A–AVR32–06/09 AT32UC3L 10.7.15 Name: Interrupt Mask Register IMR Read-only 0x028 + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TERR 1 TRC 0 RCZ 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 122 32099A–AVR32–06/09 AT32UC3L 10.7.16 Name: Interrupt Status Register ISR Read-only 0x02C + n*0x040 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TERR 1 TRC 0 RCZ • TERR: Transfer Error This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR. This bit is set when one or more transfer errors has occurred since reset or the last write to CR.ECLR. • TRC: Transfer Complete This bit is cleared when the TCR and/or the TCRR holds a non-zero value. This bit is set when both the TCR and the TCRR are zero. • RCZ: Reload Counter Zero This bit is cleared when the TCRR holds a non-zero value. This bit is set when TCRR is zero. 123 32099A–AVR32–06/09 AT32UC3L 10.7.17 Name: Performance Control Register PCONTROL Read/Write 0x800 0x00000000 30 29 28 27 MON1CH 26 25 24 Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 20 19 MON0CH 18 17 16 15 - 14 - 13 - 12 - 11 - 10 - 9 CH1RES 8 CH0RES 7 - 6 - 5 CH1OF 4 CH0OF 3 - 2 - 1 CH1EN 0 CH0EN • MON1CH: Performance Monitor Channel 1 • MON0CH: Performance Monitor Channel 0 The PDCA channel number to monitor with counter n Due to performance monitor hardware resource sharing, the two performance monitor channels should NOT be programmed to monitor the same PDCA channel. This may result in UNDEFINED monitor behavior. • CH1RES: Performance Channel 1 Counter Reset Writing a zero to this bit has no effect. Writing a one to this bit will reset the counter in performance channel 1. This bit always reads as zero. • CH0RES: Performance Channel 0 Counter Reset Writing a zero to this bit has no effect. Writing a one to this bit will reset the counter in performance channel 0. This bit always reads as zero. • CH1OF: Performance Channel 1 Overflow Freeze 0: The performance channel registers are reset if DATA or STALL overflows. 1: All performance channel registers are frozen just before DATA or STALL overflows. • CH1OF: Performance Channel 0 Overflow Freeze 0: The performance channel registers are reset if DATA or STALL overflows. 1: All performance channel registers are frozen just before DATA or STALL overflows. • CH1EN: Performance Channel 1 Enable 0: Performance channel 1 is disabled. 1: Performance channel 1 is enabled. • CH0EN: Performance Channel 0 Enable 0: Performance channel 0 is disabled. 1: Performance channel 0 is enabled. 124 32099A–AVR32–06/09 AT32UC3L 10.7.18 Name: Performance Channel 0 Read Data Cycles PRDATA0 Read-only 0x804 0x00000000 30 29 28 DATA[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 125 32099A–AVR32–06/09 AT32UC3L 10.7.19 Name: Performance Channel 0 Read Stall Cycles PRSTALL0 Read-only 0x808 0x00000000 30 29 28 STALL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 126 32099A–AVR32–06/09 AT32UC3L 10.7.20 Name: Performance Channel 0 Read Max Latency PRLAT0 Read/Write 0x80C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one. 127 32099A–AVR32–06/09 AT32UC3L 10.7.21 Name: Performance Channel 0 Write Data Cycles PWDATA0 Read-only 0x810 0x00000000 30 29 28 DATA[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 128 32099A–AVR32–06/09 AT32UC3L 10.7.22 Name: Performance Channel 0 Write Stall Cycles PWSTALL0 Read-only 0x814 0x00000000 30 29 28 STALL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 129 32099A–AVR32–06/09 AT32UC3L 10.7.23 Name: Performance Channel 0 Write Max Latency PWLAT0 Read/Write 0x818 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one. 130 32099A–AVR32–06/09 AT32UC3L 10.7.24 Name: Performance Channel 1 Read Data Cycles PRDATA1 Read-only 0x81C 0x00000000 30 29 28 DATA[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 131 32099A–AVR32–06/09 AT32UC3L 10.7.25 Name: Performance Channel 1 Read Stall Cycles PRSTALL1 Read-only 0x820 0x00000000 30 29 28 STALL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 132 32099A–AVR32–06/09 AT32UC3L 10.7.26 Name: Performance Channel 1 Read Max Latency PLATR1 Read/Write 0x824 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one. 133 32099A–AVR32–06/09 AT32UC3L 10.7.27 Name: Performance Channel 1 Write Data Cycles PWDATA1 Read-only 0x828 0x00000000 30 29 28 DATA[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 • DATA: Data Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 134 32099A–AVR32–06/09 AT32UC3L 10.7.28 Name: Performance Channel 1 Write Stall Cycles PWSTALL1 Read-only 0x82C 0x00000000 30 29 28 STALL[31:24] 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 STALL[23:16] 19 18 17 16 15 14 13 12 STALL[15:8] 11 10 9 8 7 6 5 4 STALL[7:0] 3 2 1 0 • STALL: Stall Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock 135 32099A–AVR32–06/09 AT32UC3L 10.7.29 Name: Performance Channel 1 Write Max Latency PWLAT1 Read/Write 0x830 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 LAT[15:8] 11 10 9 8 7 6 5 4 LAT[7:0] 3 2 1 0 • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one. 136 32099A–AVR32–06/09 AT32UC3L 10.7.30 Name: PDCA Version Register VERSION Read-only 0x834 - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 137 32099A–AVR32–06/09 AT32UC3L 10.8 Module Configuration The specific configuration for each PDCA instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 10-6. Feature PDCA Configuration PDCA 12 Number of channels Table 10-7. Module name PDCA Module Clock Name PB Clock Name CLK_PDCA_PB HSB Clock Name CLK_PDCA_HSB Table 10-8. Register PSR CH 0 PSR CH 1 PSR CH 2 PSR CH 3 PSR CH 4 PSR CH 5 PSR CH 6 PSR CH 7 PSR CH 8 PSR CH 9 PSR CH 10 PSR CH 11 VERSION Register Reset Values Reset Value 0 1 2 3 4 5 6 7 8 9 10 11 122 The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as observed from the memory, so RX means transfers from peripheral to memory and TX means from memory to peripheral. Table 10-9. PID 0 1 2 3 4 5 Peripheral Identity Values Direction RX RX RX RX RX RX Peripheral Instance USART0 USART1 USART2 USART3 SPI TWIM0 Peripheral Register THR THR THR THR TDR THR 138 32099A–AVR32–06/09 AT32UC3L Table 10-9. PID 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Peripheral Identity Values Direction RX RX RX RX RX RX TX TX TX TX TX TX TX TX TX TX TX Peripheral Instance TWIM1 TWIS0 TWIS1 ADCIFB AW CAT USART0 USART1 USART2 USART3 SPI TWIM0 TWIM1 TWIS0 TWIS1 AW CAT Peripheral Register THR THR THR LCDR THR MBLEN RHR RHR RHR RHR RDR RHR RHR RHR RHR RHR ACOUNT 139 32099A–AVR32–06/09 AT32UC3L 11. Peripheral Event System Rev: 1.0.0.0 11.1 Features • • • • Direct peripheral to peripheral communication system Allows peripherals to receive, react to, and send peripheral events without CPU intervention Cycle deterministic event communication Asynchronous interrupts allow advanced peripheral operation in low power sleep modes 11.2 Overview Several peripheral modules can be configured to emit or respond to signals known as peripheral events. The exact condition to trigger a peripheral event, or the action taken upon receiving a peripheral event, is specific to each module. Peripherals that respond to peripheral events are called peripheral event users and peripherals that emit peripheral events are called peripheral event generators. A single module can be both a peripheral event generator and user. The peripheral event generators and users are interconnected by a network known as the Peripheral Event System. This allows low latency peripheral-to-peripheral signaling without CPU intervention, and without consuming system resources such as bus or RAM bandwidth. This offloads the CPU and system resources compared to a traditional interrupt-based software driven system. 11.3 Peripheral Event System Block Diagram Figure 11-1. Peripheral Event System Block Diagram Generator Generator Peripheral Event System User Generator/ User 11.4 11.4.1 Functional Description Configuration The Peripheral Event System in the AT32UC3L has a fixed mapping of peripheral events between generators and users, as described in Table 11-1. Thus, the user does not need to con- 140 32099A–AVR32–06/09 AT32UC3L figure the interconnection between the modules, although each peripheral event can be enabled or disabled at the generator or user side as described in the peripheral chapter for each module. Table 11-1. Generator GPIO.pin_change[0] GPIO.pin_change[1] GPIO.pin_change[2] Peripheral Event Generators and Users Interconnection User TC[0].a0.capture TC[0].a1.capture TC[0].a2.capture Asynchronous N N N GPIO.pin_change[3] GPIO.pin_change[4] GPIO.pin_change[5] TC[1].a0.capture TC[1].a1.capture TC[1].a2.capture N N N AST.event AST.event AST.event ACIFB.trig ADCIFB.trig CAT.capsense Y Y Y ACIFB.compare[15:0] ACIFB PWMA.adjust[15:0] CAT N N PWMA.channel_0 PWMA.channel_0 Note: ACIFB.trig ADCIFB.trig N N There are six pin-change interrupts in the AT32UC3L, where pin-change interrupt 3 corresponds to PA24-31. These pins are non-existing on the AT32UC3L, and thus this pin-change interrupt can never be triggered. Pin change peripheral events are mapped in the same manner as pin-change interrupts, and thus the pin-change peripheral event 3 can never be triggered. The TC[1].a0.capture can still be reached by selecting the peripheral function in the I/O Controller. 11.4.2 Peripheral Event Connections Each generated peripheral event is connected to one or more users. If a peripheral event is connected to multiple users, the peripheral event can trigger actions in multiple modules. A peripheral event user can likewise be connected to one or more peripheral event generators. If a peripheral event user is connected to multiple generators, the peripheral events are OR’ed together to a single peripheral event. This means that peripheral events from either one of the generators will result in a peripheral event to the user. To configure a peripheral event, the peripheral event must be enabled at both the generator and user side. Even if a generator is connected to multiple users, only the users with the peripheral event enabled will trigger on the peripheral event. 11.4.3 Low Power Operation As the peripheral events do not require CPU intervention, they are available in Idle mode. They are also available in deeper sleep modes if both the generator and user remain clocked in that mode. 141 32099A–AVR32–06/09 AT32UC3L Certain events are known as asynchronous peripheral events, as identified in Table 11-1 on page 141. These can be issued even when the system clock is stopped, and revive unclocked user peripherals. The clock will be restarted for this module only, without waking the system from sleep mode. The clock remains active only as long as required by the triggered function, before being switched off again, and the system remains in the original sleep mode. The CPU and system will only be woken up if the user peripheral generates an interrupt as a result of the operation. This concept is known as SleepWalking™ and is described in further detail in the Power Manager chapter. Note that asynchronous peripheral events may be associated with a delay due to the need to restart the system clock source if this has been stopped in the sleep mode. 11.5 Application Example This application example shows how the Peripheral Event System can be used to program the ADC Interface to perform ADC conversions at selected intervals. Conversions of the active analog channels are started with a software or a hardware trigger. One of the possible hardware triggers is a peripheral event trigger, allowing the Peripheral Event System to synchronize conversion with some configured peripheral event source. From Table 11-1 on page 141, it can be read that this peripheral event source can be either an AST peripheral event, or an event from the PWM Controller. The AST can generate periodic peripheral events at selected intervals, among other types of peripheral events. The Peripheral Event System can then be used to set up the ADC Interface to sample an analog signal at regular intervals. The user must enable peripheral events in the AST and in the ADC Interface to accomplish this. The periodic peripheral event in the AST is enabled by writing a one to the corresponding bit in the AST Event Enable Register (EVE). To select the peripheral event trigger for the ADC Interface, the user must write the value 0x7 to the Trigger Mode (TRGMOD) field in the ADC Interface Trigger Register (TRGR). When the peripheral events are enabled, the AST will generate peripheral events at the selected intervals, and the Peripheral Event System will route the peripheral events to the ADC Interface, which will perform ADC conversions at the selected intervals. Figure 11-2. Application Example AST Periodic peripheral Peripheral event Event System ADC Interface Since the AST peripheral event is asynchronous, the description above will also work in sleep modes where the ADC clock is stopped. In this case, the ADC clock (and clock source, if needed) will be restarted during the ADC conversion. After the conversion, the ADC clock and clock source will return to the sleep state, unless the ADC generates an interrupt, which in turn will wake up the system. Using asynchronous interrupts thus allows ADC operation in much lower power states than would otherwise be possible. 142 32099A–AVR32–06/09 AT32UC3L 12. Interrupt Controller (INTC) Rev: 1.0.0.4 12.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • Up to 64 groups of interrupts with up to 32 interrupt requests in each group 12.2 Overview The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU. The AVR32 architecture supports 4 priority levels for regular, maskable interrupts, and a Non-Maskable Interrupt (NMI). The INTC supports up to 64 groups of interrupts. Each group can have up to 32 interrupt request lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register (IPR) and an Interrupt Request Register (IRR). The IPRs are used to assign a priority level and an autovector to each group, and the IRRs are used to identify the active interrupt request within each group. If a group has only one interrupt request line, an active interrupt group uniquely identifies the active interrupt request line, and the corresponding IRR is not needed. The INTC also provides one Interrupt Cause Register (ICR) per priority level. These registers identify the group that has a pending interrupt of the corresponding priority level. If several groups have a pending interrupt of the same level, the group with the lowest number takes priority. 12.3 Block Diagram Figure 12-1 gives an overview of the INTC. The grey boxes represent registers that can be accessed via the user interface. The interrupt requests from the peripherals (IREQn) and the NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of the figure. 143 32099A–AVR32–06/09 AT32UC3L Figure 12-1. INTC Block Diagram Interrupt Controller NMIREQ CPU Masks OR IRRn IREQ63 IREQ34 IREQ33 IREQ32 GrpReqN ValReqN IPRn SREG Masks I[3-0]M GM . . . GrpReq1 OR IRR1 Request Masking ValReq1 IPR1 INT_level, offset . . . INT_level, offset . . . INTLEVEL Prioritizer AUTOVECTOR IREQ31 IREQ2 IREQ1 IREQ0 OR IRR0 IRR Registers GrpReq0 ValReq0 IPR0 INT_level, offset IPR Registers ICR Registers 12.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 12.4.1 Power Management If the CPU enters a sleep mode that disables clocks used by the INTC, the INTC will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The clock for the INTC bus interface (CLK_INTC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. 12.4.2 12.4.3 Debug Operation When an external debugger forces the CPU into debug mode, the INTC continues normal operation. 12.5 Functional Description All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that is active. If several IREQs within the same group are active, the interrupt service routine must prioritize between them. All of the input lines in each group are logically ORed together to form the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group. The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted. 144 32099A–AVR32–06/09 AT32UC3L Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Interrupt Mask (GM). An interrupt request is masked if either the GM or the corresponding interrupt level mask bit is set. The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the pending interrupt of the highest priority. If an NMI interrupt request is pending, it automatically gets the highest priority of any pending interrupt. If several interrupt groups of the highest pending interrupt level have pending interrupts, the interrupt group with the highest number is selected. The INTLEVEL and handler autovector offset (AUTOVECTOR) of the selected interrupt are transmitted to the CPU for interrupt handling and context switching. The CPU does not need to know which interrupt is requesting handling, but only the level and the offset of the handler address. The IRR registers contain the interrupt request lines of the groups and can be read via user interface registers for checking which interrupts of the group are actually active. 12.5.1 Non-Maskable Interrupts A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vector address defined by the AVR32 architecture, so AUTOVECTOR is undefined when INTLEVEL indicates that an NMI is pending. CPU Response When the CPU receives an interrupt request it checks if any other exceptions are pending. If no exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt handling, the corresponding interrupt mask bit is set automatically for this and lower levels in status register. E.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits I3M, I2M, I1M, and I0M are set in status register. If an interrupt of level 1 is approved, the masking bits I1M and I0M are set in status register. The handler address is calculated by adding AUTOVECTOR to the CPU system register Exception Vector Base Address (EVBA). The CPU will then jump to the calculated address and start executing the interrupt handler. Setting the interrupt mask bits prevents the interrupts from the same and lower levels to be passed through the interrupt controller. Setting of the same level mask bit prevents also multiple requests of the same interrupt to happen. It is the responsibility of the handler software to clear the interrupt request that caused the interrupt before returning from the interrupt handler. If the conditions that caused the interrupt are not cleared, the interrupt request remains active. 12.5.3 Clearing an Interrupt Request Clearing of the interrupt request is done by writing to registers in the corresponding peripheral module, which then clears the corresponding NMIREQ/IREQ signal. The recommended way of clearing an interrupt request is a store operation to the controlling peripheral register, followed by a dummy load operation from the same register. This causes a pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared. 12.5.2 145 32099A–AVR32–06/09 AT32UC3L 12.6 User Interface INTC Register Memory Map Register Interrupt Priority Register 0 Interrupt Priority Register 1 ... Interrupt Priority Register 63 Interrupt Request Register 0 Interrupt Request Register 1 ... Interrupt Request Register 63 Interrupt Cause Register 3 Interrupt Cause Register 2 Interrupt Cause Register 1 Interrupt Cause Register 0 Register Name IPR0 IPR1 ... IPR63 IRR0 IRR1 ... IRR63 ICR3 ICR2 ICR1 ICR0 Access Read/Write Read/Write ... Read/Write Read-only Read-only ... Read-only Read-only Read-only Read-only Read-only Reset 0x00000000 0x00000000 ... 0x00000000 N/A N/A ... N/A N/A N/A N/A N/A Table 12-1. Offset 0x000 0x004 ... 0x0FC 0x100 0x104 ... 0x1FC 0x200 0x204 0x208 0x20C 146 32099A–AVR32–06/09 AT32UC3L 12.6.1 Interrupt Priority Registers Register Name: IPR0...IPR63 Access Type: Offset: Reset Value: Read/Write 0x000 - 0x0FC 0x00000000 29 21 13 28 20 12 27 19 26 18 25 17 9 24 16 8 31 30 INTLEVEL[1:0] 23 15 7 22 14 6 11 10 AUTOVECTOR[13:8] 2 5 4 3 AUTOVECTOR[7:0] 1 0 • INTLEVEL: Interrupt Level Indicates the EVBA-relative offset of the interrupt handler of the corresponding group: 00: INT0 01: INT1 10: INT2 11: INT3 • AUTOVECTOR: Autovector Address Handler offset is used to give the address of the interrupt handler. The least significant bit should be written to zero to give halfword alignment. 147 32099A–AVR32–06/09 AT32UC3L 12.6.2 Name: Interrupt Request Registers IRR0...IRR63 Read-only 0x0FF - 0x1FC N/A 30 IRR[32*x+30] 22 IRR[32*x+22] 14 IRR[32*x+14] 6 IRR[32*x+6] 29 IRR[32*x+29] 21 IRR[32*x+21] 13 IRR[32*x+13] 5 IRR[32*x+5] 28 IRR[32*x+28] 20 IRR[32*x+20] 12 IRR[32*x+12] 4 IRR[32*x+4] 27 IRR[32*x+27] 19 IRR[32*x+19] 11 IRR[32*x+11] 3 IRR[32*x+3] 26 IRR[32*x+26] 18 IRR[32*x+18] 10 IRR[32*x+10] 2 IRR[32*x+2] 25 IRR[32*x+25] 17 IRR[32*x+17] 9 IRR[32*x+9] 1 IRR[32*x+1] 24 IRR[32*x+24] 16 IRR[32*x+16] 8 IRR[32*x+8] 0 IRR[32*x+0] Access Type: Offset: Reset Value: 31 IRR[32*x+31] 23 IRR[32*x+23] 15 IRR[32*x+15] 7 IRR[32*x+7] • IRR: Interrupt Request line This bit is cleared when no interrupt request is pending on this input request line. This bit is set when an interrupt request is pending on this input request line. The are 64 IRRs, one for each group. Each IRR has 32 bits, one for each possible interrupt request, for a total of 2048 possible input lines. The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The IRRs are sampled continuously, and are read-only. 148 32099A–AVR32–06/09 AT32UC3L 12.6.3 Interrupt Cause Registers Register Name: ICR0...ICR3 Access Type: Offset: Reset Value: 31 23 15 7 - Read-only 0x200 - 0x20C N/A 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 3 CAUSE 26 18 10 2 25 17 9 1 24 16 8 0 • CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least one interrupt of level n is pending. 149 32099A–AVR32–06/09 AT32UC3L 12.7 Module Configuration The specific configuration for each INTC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 12-2. Module Name INTC INTC Clock Name Clock Name CLK_INTC 12.7.1 Interrupt Request Signal Map The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. The table below shows how the interrupt request signals are connected to the INTC. Table 12-3. Group 0 Interrupt Request Signal Map Line 0 0 Module AVR32 UC3 Core AVR32 UC3 Core AVR32 UC3 Core Flash Controller Secure Access Unit Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Power Manager System Control Interface Asynchronous Timer Signal SYSBLOCK COMPARE OCD DCEMU_DIRTY OCD DCCPU_READ FLASHCDW SAU PDCA 0 PDCA 1 PDCA 2 PDCA 3 PDCA 4 PDCA 5 PDCA 6 PDCA 7 PDCA 8 PDCA 9 PDCA 10 PDCA 11 PM SCIF AST ALARM 1 1 2 3 0 0 0 1 4 2 3 0 1 5 2 3 0 1 6 2 3 7 8 9 0 0 0 150 32099A–AVR32–06/09 AT32UC3L Table 12-3. Interrupt Request Signal Map 0 1 10 2 3 0 1 11 2 3 12 13 0 0 0 1 2 14 3 4 5 15 16 17 18 19 20 21 22 23 24 0 0 0 0 0 0 0 0 0 0 0 25 1 2 0 26 1 2 27 0 General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Serial Peripheral Interface Two-wire Master Interface Two-wire Master Interface Two-wire Slave Interface Two-wire Slave Interface Basic Pulse Width Modulation Controller Timer/Counter Timer/Counter Timer/Counter Timer/Counter Timer/Counter Timer/Counter ADC Interface GPIO 3 GPIO 4 GPIO 5 USART0 USART1 USART2 USART3 SPI TWIM0 TWIM1 TWIS0 TWIS1 PWMA TC00 TC01 TC02 TC10 TC11 TC12 ADCIFB External Interrupt Controller External Interrupt Controller External Interrupt Controller Frequency Meter General Purpose Input/Output Controller General Purpose Input/Output Controller General Purpose Input/Output Controller EIC 3 EIC 4 EIC 5 FREQM GPIO 0 GPIO 1 GPIO 2 Asynchronous Timer Asynchronous Timer External Interrupt Controller External Interrupt Controller AST READY AST CLKREADY EIC 1 EIC 2 Asynchronous Timer Asynchronous Timer AST PER AST OVF 151 32099A–AVR32–06/09 AT32UC3L Table 12-3. 28 29 30 Interrupt Request Signal Map 0 0 0 Analog Comparator Interface Capacitive Touch Module aWire ACIFB CAT AW 152 32099A–AVR32–06/09 AT32UC3L 13. Power Manager (PM) Rev: 4.1.1.0 13.1 Features • • • • • • • Generates clocks and resets for digital logic On-the-fly frequency change of CPU, HSB and PBx clocks Sleep modes allow simple disabling of logic clocks and clock sources Module-level clock gating through maskable peripheral clocks Wake-up from internal or external interrupts Automatic identification of reset sources Support advanced Shutdown sleep mode 13.2 Overview The Power Manager (PM) provides synchronous clocks used to clock the main digital logic in the device, namely the CPU, and the modules and peripherals connected to the High Speed Bus (HSB) and the Periperal Buses (PBx). The PM also contains advanced power-saving features, allowing the user to optimize the power consumption for an application. The synchronous clocks are divided into a number of clock domains, one for the CPU and HSB and one for each PBx. The clocks can run at different speeds, so the user can save power by running peripherals at a relatively low clock, while maintaining a high CPU performance. Additionally, the clocks can be independently changed on-thefly, without halting any peripherals. This enables the user to adjust the speed of the CPU and memories to the dynamic load of the application, without disturbing or re-configuring active peripherals. Each module also has a separate clock, enabling the user to switch off the clock for inactive modules, to save further power. Additionally, clocks and oscillators can be automatically switched off during idle periods by using the sleep instruction on the CPU. The system will return to normal operation on occurrence of interrupts. To get maximum power savings, a special sleep mode, called Shutdown is available, where power on all internal logic (CPU, peripherals) and most of the I/O lines is removed, reducing leakage. Only a small amount of logic, including 32KHz crystal oscillator and AST is left powered. The Power Manager also contains a Reset Controller, which collects all possible reset sources, generates hard and soft resets, and allows the reset source to be identified by software. 153 32099A–AVR32–06/09 AT32UC3L 13.3 Block Diagram Figure 13-1. PM Block Diagram Synchronous clocks CPU, HSB, PBx Main Clock Sources Synchronous Clock Generator Interrupts Sleep Controller Sleep Instruction Reset Sources Power-On Detector External Reset Pad Reset Controller Resets 13.4 I/O Lines Description I/O Lines Description Description Reset Type Input Active Level Low Table 13-1. Name RESET_N 13.5 13.5.1 Product Dependencies Interrupt The PM interrupt line is connected to one of the internal sources of the interrupt controller. Using the PM interrupt requires the interrupt controller to be programmed first. 13.5.2 Clock Implementation In AT32UC3L, the HSB shares the source clock with the CPU. This means that writing to the HSBSEL register has no effect. This register will always read the same value as CPUSEL. Power Considerations The Shutdown mode is only available for the “3.3V supply mode, with 1.8V regulated I/O lines“ power configuration. 13.5.3 154 32099A–AVR32–06/09 AT32UC3L 13.6 13.6.1 Functional Description Synchronous Clocks The System RC Oscillatro (RCSYS) or a set of other clock sources provide the source for the main clock, which is the common root for the synchronous clocks for the CPU/HSB and PBx modules. For details about the other main clock sources, please refer to the register description of the Main Clock Control Register (MCCTRL). The main clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from any tapping of this prescaler, or the undivided main clock, as long as fCPU ≥ fPBx,. The synchronous clock source can be changed onthe fly, responding to varying load in the application. The clock domains can be shut down in sleep mode, as described in Section 13.6.3. Additionally, the clocks for each module in the four domains can be individually masked, to avoid power consumption in inactive modules. Figure 13-2. Synchronous Clock Generation Sleep Instruction Sleep Controller 0 Main Clock Mask CPUMASK CPU Clocks HSB Clocks PBx Clocks Main Clock Sources 1 Prescaler CPUDIV MCSEL CPUSEL 13.6.1.1 Selecting the main clock source The common main clock can be connected to RCSYS or a set of other clock sources. For details about the other main clock sources, please refer to the register description of the Main Clock Control Register (MCCTRL). By default, the main clock will be connected to RCSYS. The user can connect the main clock to an other source by writing the MCSEL field in the MCCTRL register. This must only be done after that unit has been enabled, otherwise a deadlock will occur. Care should also be taken that the new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain. Selecting synchronous clock division ratio The main clock feeds an 8-bit prescaler, which can be used to generate the synchronous clocks. By default, the synchronous clocks run on the undivided main clock. The user can select a prescaler division for the CPU clock by writing CPUDIV in CPUSEL register to 1 and CPUSEL in CPUSEL register to the value, resulting in a CPU clock frequency: fCPU = fmain / 2(CPUSEL+1) 155 13.6.1.2 32099A–AVR32–06/09 AT32UC3L Similarly, the clock for the PBx can be divided by writing their respective registers. To ensure correct operation, frequencies must be selected so that fCPU ≥ fPBx. Also, frequencies must never exceed the specified maximum frequency for each clock domain. CPUSEL and PBxSEL can be written without halting or disabling peripheral modules. Writing CPUSEL and PBxSEL allows a new clock setting to be written to all synchronous clocks at the same time. It is possible to keep one or more clocks unchanged by only writing to one of the registers. This way, it is possible to, e.g., scale CPU and HSB speed according to the required performance, while keeping the PBx frequency constant. 13.6.1.3 Clock Ready flag There is a slight delay from CPUSEL and PBxSEL is written and the new clock setting becomes effective. During this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If CKRDY in the IER register is written to 1, the Power Manager interrupt can be triggered when the new clock setting is effective. CKSEL must not be re-written while CKRDY is 0, or the system may become unstable or hang. Peripheral Clock Masking By default, the clock for all modules are enabled, regardless of which modules are actually being used. It is possible to disable the clock for a module in the CPU, HSB or PBx clock domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBx) to 0. When a module is not clocked, it will cease operation, and its registers cannot be read or written. The module can be re-enabled later by writing the corresponding mask bit to 1. A module may be connected to several clock domains, in which case it will have several mask bits. Table 13-9 on page 169 contains a list of implemented maskable clocks. 13.6.2.1 Cautionary note Note that clocks should only be switched off if it is certain that the module will not be used. Switching off the clock for the flash controller will cause a problem if the CPU needs to read from the flash. Switching off the clock to the Power Manager (PM), which contains the mask registers, or the corresponding PBx bridge, will make it impossible to write the mask registers again. In this case, they can only be re-enabled by a system reset. Sleep Modes In normal operation, all clock domains are active, allowing software execution and peripheral operation. When the CPU is idle, it is possible to switch off the CPU clock and optionally other clock domains to save power. This is activated by the sleep instruction, which takes the sleep mode index number as argument. 13.6.3.1 Entering and exiting sleep modes The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains. The modules will be halted regardless of the bit settings of the mask registers. Clock sources can also be switched off to save power. Some of these have a relatively long start-up time, and are only switched off when very low power consumption is required. The CPU and affected modules are restarted when the sleep mode is exited. This occurs when an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if the source module is not clocked. 13.6.2 13.6.3 156 32099A–AVR32–06/09 AT32UC3L 13.6.3.2 Supported sleep modes The following sleep modes are supported. These are detailed in Table 13-2 on page 157. • Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any interrupts. • Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up sources are any interrupts from PB modules. • Standby: All synchronous clocks are stopped, but the clock sources are running, allowing quick wake-up to normal mode. Wake-up sources are AST, WDT, external interrupts, external reset or any asynchronous interrupts from PB modules. • Stop: As Standby, but oscillators, and other clock sources are stopped. 32 KHz (if enabled), RC oscillators, AST and WDT will still operate. Wake-up sources are the same as for Standby mode. • DeepStop: All synchronous clocks and clock sources are stopped. 32 KHz oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference and BOD is turned off. Wake-up sources are the same as for Standby mode. • Static: All clock sources, including RC oscillator are stopped. 32 KHz oscillator can run if enabled. Bandgap voltage reference BOD detector is turned off. Wake-up sources are AST, external interrupts, external reset or any asynchronous interrupts from PB modules. • Shutdown: All clock sources, including RC oscillator are stopped. 32 KHz oscillator can run if enabled. Bandgap voltage reference BOD detector is turned off. Voltage regulator is turned off. Wake-up sources are external reset or external wake-up pin. This mode can only be used in the “3.3V supply mode, with 1.8V regulated I/O lines“ configuration (described in Power Considerations chapter). See Section 13.6.4 for more details. Table 13-2. Index 0 1 2 3 4 5 6 Sleep Modes Sleep Mode Idle Frozen Standby Stop DeepStop Static Shutdown CPU Stop Stop Stop Stop Stop Stop Stop HSB Run Stop Stop Stop Stop Stop Stop PBA,B GCLK Run Run Stop Stop Stop Stop Stop Clock sources Run Run Run Stop Stop Stop Stop Osc32 Run Run Run Run Run Run Run RCSYS Run Run Run Run Run Stop Stop BOD & Bandgap On On On On Off Off Off Voltage Regulator Full power Full power Full power Low power Low power Low power Off The power level of the internal voltage regulator is also adjusted according to the sleep mode to reduce the internal regulator power consumption. 13.6.3.3 SleepWalking™ In all sleep modes where the PBx clocks are stopped, except for Shutdown mode, the chip can wake partially up if a PBx module asynchronously discovers that it needs its clock. Only the requested clocks and clock sources needed will be started, and all other clocks will be masked to zero. E.g. if the main clock source is OSC0, only OSC0 will be started even if other clock sources were enabled in normal mode. Also generic clocks can be started in a similar way. The state where only requested clocks are running is referred to as SleepWalking. 157 32099A–AVR32–06/09 AT32UC3L The time spent to start the requested clock is mostly limited by the startup time of the given clock source. This allows PBx modules to handle incoming requests, while still keeping the power consumption at a minimum. When the chip is SleepWalking any asynchronous interrupt can wake up the chip at any time without stopping the requested PBx clock. The request to start the clock can come from the module itself or through the event system, please refer to the event system and module chapters for details. All requests to start clocks can be masked by writing to the Peripheral Power Control Register (PPCR), all requests are enabled at reset. 13.6.3.4 Precautions when entering sleep mode Modules communicating with external circuits should normally be disabled before entering a sleep mode that will stop the module operation. This prevents erratic behavior when entering or exiting sleep mode. Please refer to the relevant module documentation for recommended actions. Communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. This means that bus transactions are not allowed between clock domains affected by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus transaction. The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary. When entering a sleep mode (except Idle mode), all HSB masters must be stopped before entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete, the CPU should perform a read operation from any register on the PB bus before executing the sleep instruction. This will stall the CPU while waiting for any pending PB operations to complete. The Shutdown sleep mode requires extra care. Please refer to Section 13.6.4. 13.6.4 13.6.4.1 Shutdown Sleep Mode Description The Shutdown sleep mode is available only when the chip is used in the “3.3V supply mode, with 1.8V regulated I/O lines“ configuration (see Power Considerations chapter). In this configuration, the voltage regulator supplies both VDDCORE and VDDIO power supplies. When the device enters Shutdown mode, the regulator is turned off and only the following logic is kept powered by VDDIN: – 2nd 32KHz crystal oscillator (available on PA13/PA20) – AST core logic (internal counter and alarm detection logic) – I/O lines PA11,PA13,PA20,PA21,PB04,PB05,PB10 – RESET_N line 158 32099A–AVR32–06/09 AT32UC3L The table gives the possible usage of the I/O lines that stay powered during the Shutdown sleep mode. If no special function are used, then the I/O lines will keep its settings before entering the sleep mode Table 13-3. Pin PA11 PA13 PA20 PA21 PB04 PB05 PB10 RESET_N Reset pin I/O Lines Usage During Shutdown Mode Possible Usage During Shutdown Sleep Mode WAKE_N signal (active low wake-up) XIN32_2 (2nd 32KHz crystal oscillator) XOUT32_2 13.6.4.2 Entering Shutdown sleep mode Before entering the Shutdown sleep mode, a few actions are required: – All modules should normally be disabled before entering Shutdown sleep mode (see Section 13.6.3.4) – The POR33 (see System Control Interface “SCIF” chapter) must be disabled to save power and masked to avoid any spurious reset when the power is back. The following pseudo-code shows how to performs this operation: // Turn on RC32 oscillator (if not already on) Set bit ‘en’ in SCIF.RC32CR register to 1 // Disable POR33 Set bit ‘por33en’ in SCIF.VREGCR register to 0 Wait for bit ‘por33en’ is read as 0 // Mask POR33 Set bit ‘por33mask’ in SCIF.VREGCR register to 1 Wait for bit ‘por33mask’ is read as 1 // Turn off RC32 oscillator - save some power Set bit ‘en’ in SCIF.RC32CR register to 0 // Go to sleep sleep AVR32_PM_SMODE_SHUTDOWN Note: the unlocking of SCIF registers is not shown in the example above. As soon as the Shutdown sleep mode is entered, all CPU and peripherals are reset to ensure a consistent state. 159 32099A–AVR32–06/09 AT32UC3L 13.6.4.3 Leaving Shutdown sleep mode Exiting the Shutdown sleep mode can be done using the events described in Table 13-4 on page 160. Table 13-4. Source PA11 (WAKE_N) RESET_N Events That Can Wake-Up The Device From Shutdown Mode How Pulling-down PA11 will wake-up the device Pulling-down RESET_N pin will wake-up the device The device is kept under reset until RESET_N is tied high again 32KHz Crystal oscillator must be set-up to use alternate pinout (XIN32_2 and XOUT32_2) See SCIF Chapter AST must be configured to use the clock from the 32KHz crystal oscillator AST must be configured to allow alarm,periodic or overflow wake-up AST When a wake-up event occurs, the regulator is turned-on again and the device will wait for VDDCORE power to be valid again before starting again. The bit SLEEP is then set in the RCAUSE register. This allows software running on the device to distinguish between the first power-up and a wake-up from Shutdown mode. 13.6.5 Divided PB Clocks The clock generator in the Power Manager provides divided PBx clocks for use by peripherals that require a prescaled PBx clock. This is described in the documentation for the relevant modules. The divided clocks are directly maskable, and are stopped in sleep modes where the PBx clocks are stopped. 13.6.6 Reset Controller The Reset Controller collects the various reset sources in the system and generates hard and soft resets for the digital logic. The device contains a Power-On Detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pull-up, and does not need to be driven externally when negated. Table 13-5 on page 161 lists these and other reset sources supported by the Reset Controller. 160 32099A–AVR32–06/09 AT32UC3L Figure 13-3. Reset Controller Block Diagram RC_RCAUSE RESET_N Power-On Detector Brownout Detector SM33 Detector JTAG AWIRE OCD Watchdog Reset CPU, HSB, PBx Reset Controller OCD, AST, WDT, Clock Generator In addition to the listed reset types, the JTAG & AWIRE can keep parts of the device statically reset. See JTAG and AWIRE documentation for details. Table 13-5. Reset source Power-on Reset External Reset Brownout Reset SM33 Reset Watchdog Timer OCD Reset Description Description Supply voltage below the power-on reset detector threshold voltage RESET_N pin asserted Supply voltage on VDDCORE below the brownout reset detector threshold voltage Supply voltage on VDDCORE below the brownout reset detector threshold voltage See watchdog timer documentation. See On-Chip Debug documentation When a Reset occurs, some parts of the chip are not necessarily reset, depending on the reset source. Only the Power On Reset (POR) will force a reset of the whole chip. 161 32099A–AVR32–06/09 AT32UC3L Table 2-6 on page 11 lists parts of the device that are reset, depending on the reset source. Table 13-6. Effect of the Different Reset Events Power-On Reset CPU/HSB/PBx (excluding Power Manager) 32 KHz oscillator AST control register Watchdog control register Voltage Calibration register RC Oscillator Calibration register SM33 control register BOD control register Bandgap control register Clock control registers OSC control registers DFLL control registers OCD system and OCD registers Y Y Y Y Y Y Y Y Y Y Y Y Y External Reset Y N N Y N N Y Y Y Y Y Y Y Watchdog Reset Y N N N N N Y Y Y Y Y Y N BOD Reset Y N N Y N N Y N N Y Y Y Y SM33 Reset Y N N Y N N Y Y Y Y Y Y Y OCD Reset Y N N Y N N Y Y Y Y Y Y N JTAG Reset Y N N Y N N Y Y Y Y Y Y Y The cause of the last reset can be read from the RCAUSE register. This register contains one bit for each reset source, and can be read during the boot sequence of an application to determine the proper action to be taken. 13.6.6.1 Power-On Detector The Power-On Detector monitors the VDDCORE supply pin and generates a reset when the device is powered on. The reset is active until the supply voltage from the linear regulator is above the power-on threshold level. The reset will be re-activated if the voltage drops below the power-on threshold level. See Electrical Characteristics for parametric details. External Reset The external reset detector monitors the state of the RESET_N pin. By default, a low level on this pin will generate a reset. Clock Failure Detector This mechanism allows switching the main clock to the safe RCSYS clock, when the main clock source is considered off. This may happen when a external crystal is selected as the clock source of the main clock but the cyrstal is not mounted on the board. The mechanism is to detect, during a RCSYS period, at least one rising edge of the main clock. If no rising edge is seen the clock is considered failed. Example: * RCSYS = 115khz => Failure detected if the main clock is < 115 kHz 13.6.6.2 13.6.7 162 32099A–AVR32–06/09 AT32UC3L As soon as the detector is enabled, the clock failure detector will monitor the divided main clock. Note that the detector does not monitor if the RCSYS is the source of the main clock, or if the main clock is temporarily not available (startup-time after a wake-up, switching timing etc.), or in sleep mode where the main clock is driven by the RCSYS (Stop and DeepStop mode). When a clock failure is detected, the main clock automatically switches to the RCSYS clock and the CFD interrupt is generated if enabled. The MCCTRL register that selects the source clock of the main clock is changed by hardware to indicate that the main clock comes from RCSYS. 13.6.8 Interrupts The PM has a number of interrupts: • AE: Access Error, set if a lock protected register is written without first beeing unlocked. • CKRDY: Clock Ready, set when new CKSEL setings are effective. • CFD: Clock Failure Detected, set if the system detects that the main clock is not running. 163 32099A–AVR32–06/09 AT32UC3L 13.7 User Interface PM Register Memory Map Register Main Clock Control CPU Clock Select HSB Clock Select PBA Clock Select PBB Clock Select Reserved CPU Mask HSB Mask PBA Mask PBB Mask Reserved PBA Divided Mask Reserved Clock Failure Detector Control Unlock Register Reserved PM Interrupt Enable Register PM Interrupt Disable Register PM Interrupt Mask Register PM Interrupt Status Register PM Interrupt Clear Register Status Register Reserved Peripheral Power Control Register Reserved Reset Cause Register Wake Cause Register Asyncronous Wake Enable Reserved Configuration Register Version Register CONFIG VERSION Read-only Read-only 0x00000043 -(1) RCAUSE WCAUSE AWEN Read-only Read-only Read/Write -(2) -(3) 0x00000000 PPCR Read/Write 0x00000002 IER IDR IMR ISR ICR SR Write-only Write-only Read-only Read-only Write-only Read-only 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 CFDCTRL UNLOCK Read/Write Write-only 0x00000000 0x00000000 PBADIVMASK Read/Write 0x000000FF CPUMASK HSBMASK PBAMASK PBBMASK Read/Write Read/Write Read/Write Read/Write 0x00000003 0x0000007F 0x00007FFF 0x0000003F Register Name MCCTRL CPUSEL HSBSEL PBASEL PBBSEL Access Read/Write Read/Write Read-only Read/Write Read/Write Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 13-7. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 - 0x01C 0x020 0x024 0x028 0x02C 0x030- 0x03C 0x040 0x044 - 0x050 0x054 0x058 0x05C - 0x0BC 0x0C0 0x0C4 0x0C8 0x0CC 0x0D0 0x0D4 0x0D8 - 0x15C 0x160 0x164 - 0x17C 0x180 0x184 0x188 0x18C - 0x3F4 0x3F8 0x3FC Note: 1. The reset value is device specific. Please refer to the Module Configuration section at the end of this chapter. 2. Latest Reset Source. 3. Latest Wake Source. 164 32099A–AVR32–06/09 AT32UC3L 13.7.1 Name: Access Type: Offset: Reset Value: Main Clock Control MCCTRL Read/Write 0x000 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 1 MCSEL 0 • MCSEL: Main Clock Select Table 13-8. Main clocks in AT32UC3L. Main clock source System RC oscillator (RCSYS) Oscillator0 (OSC0) DFLL 120 MHz RC oscillator (RC120M) MCSEL[2:0] 0 1 2 3 Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refere to the UNLOCK register description for details. 165 32099A–AVR32–06/09 AT32UC3L 13.7.2 Name: Access Type: Offset: Reset Value: CPU Clock Select CPUSEL Read/Write 0x004 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 CPUDIV 6 - 5 - 4 - 3 - 2 1 CPUSEL 0 • CPUDIV, CPUSEL: CPU Division and Clock Select CPUDIV = 0: CPU clock equals main clock. CPUDIV = 1: CPU clock equals main clock divided by 2(CPUSEL+1). Note that if CPUDIV is written to 0, CPUSEL should also be written to 0 to ensure correct operation. Also note that writing this register clears POSCSR.CKRDY. The register must not be re-written until CKRDY goes high. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refere to the UNLOCK register description for details. 166 32099A–AVR32–06/09 AT32UC3L 13.7.3 Name: Access Type: Offset: Reset Value: HSB Clock Select HSBSEL Read 0x008 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 HSBDIV 6 - 5 - 4 - 3 - 2 1 HSBSEL 0 This register is read-only and its content is always equal to CPUSEL 167 32099A–AVR32–06/09 AT32UC3L 13.7.4 Name: Access Type: Offset: Reset Value: PBx Clock Select PBxSEL Read/Write 0x008-0x00C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 PBDIV 6 - 5 - 4 - 3 - 2 1 PBSEL 0 • PBDIV, PBSEL: PBx Division and Clock Select PBDIV = 0: PBx clock equals main clock. PBDIV = 1: PBx clock equals main clock divided by 2(PBSEL+1). Note that if PBDIV is written to 0, PBSEL should also be written to 0 to ensure correct operation. Also note that writing this register clears SR.CKRDY. The register must not be re-written until SR.CKRDY goes high. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refere to the UNLOCK register description for details. 168 32099A–AVR32–06/09 AT32UC3L 13.7.5 Name: Access Type: Offset: Reset Value: Clock Mask CPUMASK/HSBMASK/PBAMASK/PBBMASK Read/Write 0x020-0x02C - 31 30 29 28 MASK[31:24] 27 26 25 24 23 22 21 20 MASK[23:16] 19 18 17 16 15 14 13 12 MASK[15:8] 11 10 9 8 7 6 5 4 MASK[7:0] 3 2 1 0 • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by each bit, is shown in Table 13-9. Table 13-9. Bit 0 1 2 3 4 5 6 7 8 9 10 11 Maskable Module Clocks in AT32UC3L. CPUMASK OCD HSBMASK PDCA FLASHCDW SAU PBB bridge PBA bridge Peripheral Event System PBAMASK PDCA INTC PM SCIF AST WDT EIC FREQM GPIO USART0 USART1 USART2 PBBMASK FLASHCDW HMATRIX SAU - 169 32099A–AVR32–06/09 AT32UC3L Table 13-9. Bit 12 13 14 15 16 17 18 19 20 21 22 23 24 25 31:25 Maskable Module Clocks in AT32UC3L. CPUMASK HSBMASK PBAMASK USART3 SPI TWIM0 TWIM1 TWIS0 TWIS1 PWMA TC0 TC1 ADCIFB ACIFB CAT GLOC AW PBBMASK - Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refere to the UNLOCK register description for details. 170 32099A–AVR32–06/09 AT32UC3L 13.7.6 Name: Access Type: Offset: Reset Value: Divided Clock Mask PBADIVMASK Read/Write 0x040 0x000000FF 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 5 4 3 MASK[6:0] 2 1 0 • MASK: Clock Mask If bit n is cleared, the clock divided by 2(MASK+1) is stopped. If bit n is set, the clock divided by 2(MASK+1) is enabled according to the current power mode. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refere to the UNLOCK register description for details. 171 32099A–AVR32–06/09 AT32UC3L 13.7.7 Name: Access Type: Offset: Reset Value: Clock Failure Detector Control Register CFDCTRL Read/Write 0x054 0x00000000 31 SFV 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 OCPEN 24 16 8 0 CFDEN • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes. • OCPEN: Over Clock Protection Enable 0: Over Clock Protection is disabled 1: Over Clock Protection is enabled • CFDEN: Clock Failure Detection Enable 0: Clock Failure Detector is disabled 1: Clock Failure Detector is enabled Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refere to the UNLOCK register description for details. 172 32099A–AVR32–06/09 AT32UC3L 13.7.8 Name: Access Type: Offset: Reset Value: PM Unlock Register UNLOCK Write-Only 0x058 0x00000000 31 30 29 28 KEY 27 26 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 ADDR[9:8] 8 7 6 5 4 ADDR[7:0] 3 2 1 0 To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field. Then, in the next PB access write to the register specified in the ADDR field. • KEY: Unlock Key Write this bit field to 0xAA to enable unlock. • ADDR: Unlock Address Write the address of the register to unlock to this field. 173 32099A–AVR32–06/09 AT32UC3L 13.7.9 Name: Access Type: Offset: Reset Value: Interrupt Enable Register IER Write-only 0x0C0 0x00000000 31 AE 23 15 7 - 30 22 14 6 - 29 21 13 5 CKRDY 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 174 32099A–AVR32–06/09 AT32UC3L 13.7.10 Name: Access Type: Offset: Reset Value: Interrupt Disable Register IDR Write-only 0x0C4 0x00000000 31 AE 23 15 7 - 30 22 14 6 - 29 21 13 5 CKRDY 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 175 32099A–AVR32–06/09 AT32UC3L 13.7.11 Name: Access Type: Offset: Reset Value: Interrupt Mask Register IMR Read-only 0x0C8 0x00000000 31 AE 23 15 7 - 30 22 14 6 - 29 21 13 5 CKRDY 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 176 32099A–AVR32–06/09 AT32UC3L 13.7.12 Name: Access Type: Offset: Reset Value: Interrupt Status Register ISR Read-only 0x0CC 0x00000000 31 AE 23 15 7 - 30 22 14 6 - 29 21 13 5 CKRDY 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding interrupt occurs. 177 32099A–AVR32–06/09 AT32UC3L 13.7.13 Name: Access Type: Offset: Reset Value: Interrupt Clear Register ICR Write-only 0x0D0 0x00000000 31 AE 23 15 7 - 30 22 14 6 - 29 21 13 5 CKRDY 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR. 178 32099A–AVR32–06/09 AT32UC3L 13.7.14 Name: Access Type: Offset: Reset Value: Status Register SR Read-only 0x0D4 0x00000000 31 AE 23 15 7 - 30 22 14 6 - 29 21 13 5 CKRDY 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 - • AE: Access Error 0: No access error has occured. 1: A write to lock protected register without unlocking it has occured. • CKRDY: Clock Ready 0: The CKSEL register has been written, and the new clock setting is not yet effective. 1: The synchronous clocks have frequencies as indicated in the CKSEL register. • OCP: Over Clock 0: Main clock is running at a legal frequency. 1: Illegal frequency detected on main clock. Main clock is now running on RC osc. • CFD: Clock Failure Detected 0: Main clock is running corretly. 1: Failure on main clock detected. Main clock is now running on RC osc. 179 32099A–AVR32–06/09 AT32UC3L 13.7.15 Name: Access Type: Offset: Reset Value: Peripheral Power Control Register PPCR Read/Write 0x004 0x00000000 31 30 29 28 PPC[31:24] 27 26 25 24 23 22 21 20 PPC[23:16] 19 18 17 16 15 14 13 12 PPC[15:8] 11 10 9 8 7 6 5 4 PPC[7:0] 3 2 1 0 Table 13-10. Peripheral Power Control Bit 0 1 2 3 4 5 6 7 8 31:9 Name RSTPUN FRC32 RSTTM CATRCMASK ACIFBCRCMASK ADCIFBRCMASK ASTRCMASK TWIS0RCMASK TWIS1RCMASK - • RSTTM : Reset test mode 0: External reset not in test mode 1: External reset in test mode • FRC32 : Force RC32 out 0: RC32 signal is not forced as output 1: RC32 signal is forced as output • RSTPUN: Reset Pullup, active low 0: Pull-up for external reset on 1: Pull-up for external reset off 180 32099A–AVR32–06/09 AT32UC3L • CATRCMASK : CAT Request Clock Mask 0: CAT Request Clock is disabled 1: CAT Request Clock is enabled • ACIFBRCMASK : ACIFB Request Clock Mask 0: ACIFB Request Clock is disabled 1: ACIFB Request Clock is enabled • ADCIFBRCMASK : ADCIFB Request Clock Mask 0: ADCIFB Request Clock is disabled 1: ADCIFB Request Clock is enabled • ASTRCMASK : AST Request Clock Mask 0: AST Request Clock is disabled 1: AST Request Clock is enabled • TWIS0RCMASK : TWIS0 Request Clock Mask 0: TWIS0 Request Clock is disabled 1: TWIS0 Request Clock is enabled • TWIS1RCMASK : TWIS1 Request Clock Mask 0: TWIS1 Request Clock is disabled 1: TWIS1 Request Clock is enabled Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refere to the UNLOCK register description for details. 181 32099A–AVR32–06/09 AT32UC3L 13.7.16 Name: Access Type: Offset: Reset Value: Reset Cause RCAUSE Read-only 0x180 Latest Reset Source 31 23 15 7 - 30 22 14 6 SLEEP 29 21 13 BOD33 5 - 28 20 12 AWIREHARD 4 JTAG 27 19 11 AWIRE 3 WDT 26 18 10 25 17 9 JTAGHARD 24 16 8 OCDRST 0 POR 2 EXT 1 BOD • BOD33: Brown-out 3.3V reset The CPU was reset due to the supply voltage being lower than the Supply Monitor 3.3V (SM33) threshold level. • AWIREHARD: AWIRE Hard reset The CPU was reset by the AWIRE (reserved for test) • AWIRE: AWIRE reset The CPU was reset by tthe AWIRE • JTAGHARD: JTAG Hard Reset The chip was reset by the JTAG system reset. • OCDRST: OCD Reset The CPU was reset because the RES strobe in the OCD Development Control register has been written to one. • SLEEP: SLEEP reset The CPU was reset because it woke up from Shutdown sleep mode. • JTAG: JTAG reset The chip was reset by the JTAG system reset. • WDT: Watchdog Reset The CPU was reset because of a watchdog time-out. • EXT: External Reset Pin The CPU was reset due to the RESET pin being asserted. • BOD: Brown-out Reset The CPU was reset due to the core supply voltage being lower than the brown-out threshold level. • POR Power-on Reset The CPU was reset due to the core supply voltage being lower than the power-on threshold level. 182 32099A–AVR32–06/09 AT32UC3L 13.7.17 Name: Access Type: Offset: Reset Value: Wake Cause Register WCAUSE Read-only 0x184 Lateset Wake Source 31 30 29 28 27 26 25 24 WCAUSE[31:24] 23 22 21 20 19 18 17 16 WCAUSE[23:16] 15 14 13 12 11 10 9 8 WCAUSE[15:8] 7 6 5 4 WCAUSE[7:0] A bit in this register is set on wake up caused by the peripheral referred to in Table 13-11 on page 183. 3 2 1 0 Table 13-11. Wake Cause Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Wake Cause CAT ACIFB ADCIFB TWI Slave 0 TWI Slave 1 - 183 32099A–AVR32–06/09 AT32UC3L Table 13-11. Wake Cause Bit 16 17 31:18 Wake Cause EIC AST - 184 32099A–AVR32–06/09 AT32UC3L 13.7.18 Name: Access Type: Offset: Reset Value: Asynchronous Wake Up Enable Register AWEN Read/Write 0x188 0x00000000 31 30 29 28 AWEN[31:24] 27 26 25 24 23 22 21 20 AWEN[23:16] 19 18 17 16 15 14 13 12 AWEN[15:8] 11 10 9 8 7 6 5 4 AWEN[7:0] 3 2 1 0 Each bit in this register corresponds to an asynchronous wake up, according to Table 13-12 on page 185. 0: The correcponding wake up is disabled. 1: The corresponding wake up is enabled Table 13-12. Asynchronous Wake Up Bit 0 1 2 3 4 31:5 Asynchronous Wake Up CATWEN ACIFBWEN ADCIFBWEN TWIS0WEN TWIS1WEN - 185 32099A–AVR32–06/09 AT32UC3L 13.7.19 Name: Access Type: Offset: Reset Value: Configuration Register CONFIG Read-Only 0x3F8 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 HSBPEVC 6 OCP 5 - 4 - 3 PBD 2 PBC 1 PBB 0 PBA This register shows the configuration of the PM. • HSBPEVC:HSB PEVC Clock Implemented 0: HSBPEVC not implemented. 1: HSBPEVC implemented. • OCP: Over Clock Protection Implemented 0: OCP not implemented. 1: OCP implemented. • PBD: PBD Implemented 0: PBD not implemented. 1: PBD implemented. • PBC: PBC Implemented 0: PBC not implemented. 1: PBC implemented. • PBB: PBB Implemented 0: PBB not implemented. 1: PBB implemented. • PBA: PBA Implemented 0: PBA not implemented. 1: PBA implemented. 186 32099A–AVR32–06/09 AT32UC3L 13.7.20 Name: Access Type: Offset: Reset Value: Version Register VERSION Read-Only 0x3FC - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 187 32099A–AVR32–06/09 AT32UC3L 13.8 Module Configuration The specific configuration for each PM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the “Synchronous Clocks”, “Peripheral Clock Masking” and “Sleep Modes” sections for details. Table 13-13. Power Manager Clock Name Module Name PM Clock Name CLK_PM Table 13-14. Register Reset Values Register VERSION Reset Value 0x00000411 188 32099A–AVR32–06/09 AT32UC3L 14. System Control Interface (SCIF) Rev: 1.0.2.0 14.1 Features • • • • • • • • • • • • • • Controls integrated oscillators and Digital Frequency Locked Loop (DFLL) Supports crystal oscillator 3-16MHz (OSC0) Supports Digital Frequency Locked Loop 20-150MHz (DFLL) Supports 32KHz ultra-low power oscillator (OSC32K) Supports 32kHz RC oscillator (RC32K) Integrated low-power RC oscillator (RCSYS) Generic clocks (GCLK) with wide frequency range provided Controls bandgap voltage reference through control and calibration registers Controls Brown-out detectors (BOD) and supply monitors Controls Voltage Regulator (VREG) behavior and calibration Controls Temperature Sensor Controls Supply Monitor 33 (SM33) operating modes and calibration Controls 120MHz integrated RC Oscillator (RC120M) Four 32 bit general purpose backup registers 14.2 Overview The System Control Interface (SCIF) controls the Oscillators, DFLL, Generic Clocks, BODs, Temperature Sensor, VREG, and backup registers. 14.3 I/O Lines Description Table 14-1. Pin Name RC32OUT XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 GCLK4-GCLK0 I/O Lines Description Pin Description RC32 output at startup Crystal 0 Input Crystal 32 Input (primary location) Crystal 32 Input (secondary location) Crystal 0 Output Crystal 32 Output (primary location) Crystal 32 Output (secondary location) Generic Clock Output Type Output Analog/Digital Analog/Digital Analog/Digital Analog Analog Analog Output 14.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 14.4.1 I/O Lines The SCIF provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their peripheral function. If the I/O pins of the SCIF are not used by the application, they can be used for other purposes by the GPIO controller. Oscillator pins are also multiplexed 189 32099A–AVR32–06/09 AT32UC3L with GPIO. When oscillators are used, the related pins are controlled directly by the SCIF, overriding GPIO settings. 14.4.2 Interrupt The SCIF interrupt request line is connected to the interrupt controller. Using the SCIF interrupt requires the interrupt controller to be programmed first. 14.4.3 Debug Operation The SCIF module does not interact with debug operations. Clocks The SCIF controls all oscillators on the part. Those oscillators can then be used as sources for for generic clocks (handled by the SCIF) and for the CPU and peripherals. (In this case, selection of source is done by the Power Manager.) 14.4.4 14.5 14.5.1 Functional Description Oscillator (OSC0) operation The main oscillator (OSC0) is designed to be used with an external 3 to 16MHz crystal and two biasing capacitors, as shown in Figure 14-1. The oscillator can be used for the main clock in the device, as described in the Power Manager chapter. The oscillator can be used as source for the generic clocks, as described in “Generic clocks” on page 196. The oscillator is disabled by default after reset. When the oscillator is disabled, the XIN and XOUT pins can be used as general purpose I/Os. When the oscillator is configured to use an external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a general purpose I/O. The oscillator can be enabled by writing to the OSCEN bits in OSCCTRL0. Operation mode (external clock or crystal) is chosen by writing to the MODE field in OSCCTRL0. The oscillator is automatically switched off in certain sleep modes to reduce power consumption, as described in the Power Manager chapter. After a hard reset, or when waking up from a sleep mode that disabled the oscillator, the oscillator may need a certain amount of time to stabilize on the correct frequency. This start-up time can be set in the OSCCTRL0 register. The SCIF masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic. The OSC0RDY bits in PCLKSR are automatically set and cleared according to the status of the oscillators. A zero to one transition on these bits can also be configured to generate an interrupt, as described in Section 14.6.1. 190 32099A–AVR32–06/09 AT32UC3L Figure 14-1. Oscillator connections. C2 XOUT XIN C1 14.5.2 32KHz oscillator (OSC32K) operation he 32KHz oscillator operates as described for the oscillator above. The 32KHz oscillator is used as source clock for the Asynchronous Timer and the Watchdog Timer. The 32KHz oscillator can be used as source for the generic clocks, as described in “Generic clocks” on page 196. The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32. The oscillator is an ultra-low power design and remains enabled in all sleep modes. While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in OSCCTRL32 register), the external clock must be connected to XIN32 while the XOUT32 pin can be used as a general purpose I/O. The startup time of the 32KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY in PCLKSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY. As a crystal oscillator usually requires a very long startup time (up to 1 second), the 32 KHz oscillator will keep running across resets, except Power-On-Reset. The 32 KHz oscillator also has a 1 KHz output. This is enabled by writing to EN1K bit in OSCCTRL32 register. If the 32KHz output clock is not needed when 1K is enabled, this can be disabled by writing zero to EN32K in OSCCTRL32 register. EN32K is set to one after reset. The 32KHz oscillator has two possible set of pins. To select between them write to the PINSEL bit in OSCCTRL32 register. The 32KHz oscillator is not controlled by the sleep controller, and will run in all sleep modes if enabled. 14.5.3 DFLL operation The device contains one Digital Frequency Locked Loop (DFLL). This is disabled by default, but can be enabled to provide a high frequency source clock for synchronous and generic clocks. The DFLL has a very short startup time and supports high frequency multiplication without the jitter associated with a PLL. Features: • Internal oscillator with no external components. 191 32099A–AVR32–06/09 AT32UC3L • 20-150MHz frequency • Short start-up time • Can operate standalone as high frequency programmable oscillator in open loop mode • Can operate as accurate frequency multiplier against a known frequency in closed loop mode. • Optional spread-spectrum clock generation. • Very high frequency multiplication supported - can generate all frequencies from 32KHz. The DFLL provides a high frequency clock with short startup time. The DFLL can operate in both open loop mode and closed loop mode. In closed loop mode a low frequency clock with high accuracy can be used as reference clock to get high accuracy on the output frequency. To prevent unexpected writes due to software bugs, write access to the configuration registers are protected by a locking mechanism, for details please refer to the UNLOCK register description. Figure 14-2. DFLLIF block diagram COARSE 8 DAC FINE 9 V CO CLK_DFLL STEPSIZE 6 MUL 32 FREQUENCY TUNER DFLLLOCKF DFLLLOCKLOSTF DFLLLOCKC DFLLOVERFLOW DFLLLOCKLOSTC DFLLUNDERFLOW CLK_REF 14.5.3.1 Open Loop Operation When operating in open loop mode the output frequency of the DFLL is set by the values written to the COARSE and the FINE fields in the DFLL0CONF register. Take care when setting the value of the COARSE and the FINE fields, the output frequency must not exceed the maximum frequency of the device after the division in the clock generator. To set the DFLLIF in open loop mode set first write one to the EN bit and then write zero to the MODE bit in the DFLL0CONF register. It is possible to change the value of COARSE and FINE fields, and thereby the output frequency of the DFLL, while the DFLL is enabled. 192 32099A–AVR32–06/09 AT32UC3L 14.5.3.2 Closed Loop Operation In closed loop mode the accuracy of the output frequency is limited by the accuracy of the reference clock. Set MODE and EN to one in DFLL0CONF register to enable the DFLL in closed loop mode. The output frequency of the DFLL will be given by: FMUL f VCO = ---------------- f ref 16 2 The COARSE and FINE fields in DFLL0CONF register are Read-only in closed loop mode, and are controlled by the DFLL to meet user specified frequency. The values in the COARSE register when the closed loop mode is enabled is used by the frequency tuner as a starting point for the COARSE value. Setting the COARSE to a value believed to be the correct will reduce the time needed to get a lock on the coarse value. To set up the DFLLIF first enable the DFLL by writing one to EN bit in DFLL0CONF register. Then enable and select a reference clock (CLK_DFLLIF_REF). CLK_DFLLIF_REF is a generic clock, please refer to Generic Clocks chapter for details. Then set the maximum step size allowed in finding the COARSE and FINE values by setting the CSTEP and FSTEP bits in DFLL0STEP register. A small step size will ensure low overshoot on the output frequency, but will typically be slower. A high value might give a big overshoot, but will typically give faster locking. DFLL0STEP.CSTEP and DFLL0STEP.FSTEP should not be set higher than 50% of the maximum value of DFLL0CONF.COARSE and DFLL0CONF.FINE respectively. Setting the max step size to 50% of the max value will give a binary search. Then set the value of FMUL in DFLL0MUL register, care must be taken when choosing FMUL so the output frequency does not exceed the maximum frequency of the device. The locking of the frequency in closed loop mode is divided into three stages. In the COARSE stage the control logic quickly finds the correct value for the COARSE field in DFLL0CONF register and thereby setting the output frequency to a value close to the correct frequency. The DFLL0LOCKC interrupt is issued when this is done. In the FINE stage the control logic tunes the value in the FINE field in the DFLL0CONF register so the output frequency very close to the desired frequency. The DFLL0LOCKF interrupt is issued when this is done. In the ACCURATE stage the DFLL frequency tuning mechanism uses dithering on the FINE bits to obtain an accurate output frequency. When the accurate frequency is obtained the DFLL0LOCKA interrupt is issued. The ACCURATE stage will only be executed if DITHER bit in DFLL0CONF register is set to one. If DITHER is set to zero DFLL0LOCKA will never occur. If dithering is enabled, the frequency of the dithering is decided by a generic clock (CLK_DFLLIF_DITHER). This clock has to be set up correctly before enabling dithering. Please refer to the Generic Clocks chapter for details. The flow for finding the correct settings is shown in Figure 14-3 on page 194. When dithering is enable the accuracy of the average output frequency of the DFLL will be higher. However, the frequency will be alternating between two frequencies. If a fixed frequency is required, the dithering should not be enabled. The frequency tuner will automatically compensate for drift in the output frequency of the VCO without losing either of the locks. If the FINE register overflows or underflows, which should normally not happen, but could occur due to large drift in temperature and voltage, all locks will be lost, and the COARSE and FINE values will be recalibrated as described earlier. When spread spectrum is enabled and the AMPLITUDE is high, an overflow/underflow is more likely to occur. If the reference clock stops, the DFLL0RCS interrupt will be asserted. Note that the detection of the clock stop will take long time. The DFLL will enter open loop mode if it detects that the reference clock has stopped. 193 32099A–AVR32–06/09 AT32UC3L The ratio between the reference clock and the VCO clock is measured automatically by the DFLLIF. The difference between this ratio and DFLL0MUL is stored in the Multiplication Ratio Difference field (RATIODIFF) in the DFLL0RATIO register. To get the result on the same form as DFLL0MUL, the error must be calculated as follows: RATIODIFF error = -------------------------------2 NUMREF where 2 NUMREF is the number of reference clock cycles the DFLLIF is using for calculating the ratio. The DFLL0RATIO register is only updated every time the Synchronization (SYNC) bit in DFLL0SYNC is written to one; refer to DFLL0SYNC register description for details. Figure 14-3. DFLL Closed Loop State Diagram Measure VCO frequency DFLLLOCKC 1 DFLLLOCKF 1 DITHER 1 DFLLLOCKA 1 Compensate for drift 0 0 0 0 Calculate new COARSE value Calculate new FINE value Compensate for drift Calculate new dithering dutycycle Figure 14-4. DFLL Locking in Closed Loop foverflow ffine fcoarse ft fo tcoarse LOCKC tfine LOCKF taccurate LOCKA 14.5.3.3 Enabling the DFLL Before configuring the DFLL, only the EN bit in the DFLL0CONF register should be written to one. Writes to other bits in DFLL0CONF will be ignored. The DFLL is now ready for configuration. 194 32099A–AVR32–06/09 AT32UC3L 14.5.3.4 Spread Spectrum Generator (SSG) When the DFLL is used as the main clock source for the chip, the EMI radiated from the chip will be synchronous to the VCO frequency. To provide better EMC capabilities the DFLL can provide a clock with the energy spread in the frequency domain. This is done by adding or subtracting values from the FINE value. Enable the SSG by writing one to EN bit field in the DFLL0SSG register. A generic clock sets the rate at which the SSG changes the frequency of the DFLL clock to generate a spread spectrum (CLK_DFLLIF_DITHER). This is the same clock used by the dithering mechanism. The frequency of this clock should be higher than CLK_DFLLIF_REF to ensure that the DFLLIF can lock. Please refer to the Generic clocks section for details. Optionally, the clock ticks can be qualified by a pseudorandom binary sequence (PRBS) if the PRBS bit in the DFLL0SSG register is set. This reduces the modulation effect of CLK_DFLLIF_DITHER frequency onto fvco. The amplitude of the frequency variation can be selected by setting the AMPLITUDE field in DFLL0SSG register. If the AMPLITUDE is set to zero the SSG will toggle on the LSB of the FINE value, setting AMPLITUDE to one the SSG will add the sequence {1,-1, 0} to the FINE value on every source clock cycle. The step size of the SSG is set in the STEPSIZE bit field in the DFLL0SSG register. Setting the STEPSIZE to zero or one will result in a step size equal to one. If the step size is set to n the output value from the SSG will be incremented/decremented by n on every tick of the source clock. Figure 14-5. Spread Spectrum Generator Block Diagram. FINE Pseudorandom Binary Sequence To DAC 9 GCLK Spread Spectrum Generator AMPLITUDE, STEPSIZE The Spread Spectrum Generator can operate both in open and closed loop mode. 14.5.3.5 Start-up The DFLL has very short start-up time. When waking up from a sleep mode where the DFLL has been turned off, and the DFLL clock was the main clock before going to sleep, the DFLL will be re-enabled and start running with the same configuration as before going to sleep even if the reference clock is not available. The locks will be lost. When the reference clock has restarted, the COARSE lock will be set quickly since the COARSE value starts close to the correct value. The fine lock will be set as soon as the output clock is running at the correct frequency. 14.5.3.6 Internal synchronization Due to multiple clock domains in the DFLLIF, values in configuration registers need to be synchronized to other clock domains. Thus, before writing to a DFLLIF configuration register check 195 32099A–AVR32–06/09 AT32UC3L that the DFLL0RDY bit in PCLKSR register is high before writing. A write to a configuration register while DFLL0RDY is low will be ignored. 14.5.4 Generic clocks Timers, communication modules, and other modules connected to external circuitry may require specific clock frequencies to operate correctly. The SCIF contains an implementation defined number of generic clocks that can provide a wide range of accurate clock frequencies. Each generic clock module runs from either clock source listed in the table on Table 14-9 on page 234. The selected source can optionally be divided by any even integer up to 512. Each clock can be independently enabled and disabled, and is also automatically disabled along with peripheral clocks by the Sleep Controller in the Power Manager. Figure 14-6. Generic clock generation Sleep Controller 0 Mask Divider OSCSEL DIV 1 Generic Clock DIVEN CEN 14.5.4.1 Enabling a generic clock A generic clock is enabled by writing the CEN bit in GCCTRL to one. Each generic clock can individually select a clock source by setting the OSCSEL bits. The source clock can optionally be divided by writing DIVEN to one and the division factor to DIV, resulting in the output frequency: fGCLK = fSRC / (2*(DIV+1)) 14.5.4.2 Disabling a generic clock The generic clock can be disabled by writing CEN to zero or entering a sleep mode that disables the PB clocks. In either case, the generic clock will be switched off on the first falling edge after the disabling event, to ensure that no glitches occur. If CEN is written to zero, the bit will still read as one until the next falling edge occurs, and the clock is actually switched off. When writing CEN to zero, the other bits in GCCTRL should not be changed until CEN reads as zero, to avoid glitches on the generic clock. When the clock is disabled, both the prescaler and output are reset. 196 32099A–AVR32–06/09 AT32UC3L 14.5.4.3 Changing clock frequency When changing generic clock frequency by writing GCCTRL, the clock should be switched off by the procedure above, before being re-enabled with the new clock source or division setting. This prevents glitches during the transition. Generic clock implementation In AT32UC3L, there are six generic clocks. These are allocated to different functions as shown in Table 14-2. Note that only GCLK4-0 are routed out. Table 14-2. Generic clock allocation Function DFLLIF main reference and GCLK0 pin (CLK_DFLLIF_REF) DFLLIF dithering and ssg reference and GCLK1 pin (CLK_DFLLIF_DITHER) AST and GCLK2 pin PWMA and GCLK3 pin CAT, ACIFB and GCLK4 pin GLOC 14.5.4.4 Clock number 0 1 2 3 4 5 Note: (1) 1. GCLK5 is not routed out. 14.5.5 Brown Out Detection (BOD) The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply voltage to the brown-out detection level, as set in BOD.LEVEL. The BOD is disabled by default, but can be enabled either by software or by flash fuses. The Brown-Out Detector can either generate an interrupt or a reset when the supply voltage is below the brown-out detection level. In any case, the BOD output is available in bit PCLKSR.BODET bit. Note that any change to the BOD.LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt. When turned-on, the BOD output will be masked during one half of a RCOSC clock cycle and two main clocks cycles to avoid false results See Electrical Characteristics for parametric details. Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to those registers. To prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the UNLOCK register description. 14.5.6 Bandgap The Flash memory, the Brown-Out Detector (BOD) and the temperature sensor need a stable voltage reference to operate. This reference voltage is provided by an internal Bandgap voltage reference. This reference is automatically turned on at startup and turned off during DEEPSTOP and STATIC sleep modes to save power. The Bandgap voltage reference is calibrated through the BGCR.CALIB field. This field is loaded after a Power On Reset with default values stored in factory-programmed flash fuses. 197 32099A–AVR32–06/09 AT32UC3L It is not recommended to override default factory settings as it may prevent correct operation of the Flash and BOD. To prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the UNLOCK register description 14.5.7 Voltage Regulator (VREG) The embedded voltage regulator can be used to provide the VDDCORE voltage from the VDDIN. It is controlled by the VREGCR register. The voltage regulator is turned on by default at startup but can be turned off by software if an external power is provided on the VDDCORE The voltage regulator has its own voltage reference that is calibrated through the VREGCR.CALIB field. This field is loaded after a Power On Reset with default values stored in factory-programmed flash fuses. Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to those registers. To prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the UNLOCK register description. The voltage regulator interface also includes control bits for the POR33 (Power-On Reset 3.3V) detector that monitors the VDDIN voltage during power-up. The POR33 is on by default but can be turned off by software to reduce power consumption. The 3.3V Supply Monitor can then be used to monitor the VDDIN power supply (see page 198). The RC32K oscillator must be turned on to disabled the POR33. Once the POR33 had ben disabled, the RC32K oscillator can be turned off again. Note that if the POR33 is re-enabled later, it will generate a reset. 14.5.8 System RC Oscillator (RCSYS) The system RC oscillator (RCSYS) has a 3 cycles startup time, and is always available except in Static mode. The system RC oscillator operates at a nominal frequency of 115 kHz, and is calibrated using the RCCR.CALIB Calibration field. After a Power On Reset, the RCCR.CALIB field is loaded with a factory defined value stored in the Flash fuses. Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to the RCCR.CALIB field. To prevent unexpected writes due to software bugs, write access to this register is protected by a locking mechanism, for details please refer to the UNLOCK register description. 14.5.9 3.3 V Supply Monitor (SM33) The 3.3V supply monitor (SM33) is a specific voltage detector for the VDDIN voltage. It will indicate if the VDDIN voltage is above the minimum required input voltage for the voltage regulator (typically 1.75V). The user can choose to generate either a reset or an interrupt when the VDDIN voltage drops below this limit. In order to reduce power consumption, the SM33 can operate in “sampling mode”. In sampling mode, the SM33 is periodically turned on for a small time (just enough for making the measurement) then it is turned off for a longer time. By default, the SM33 operates in “sampling” mode during DeepStop and Static mode and in continuous mode for other sleep modes. Sampling mode can also be forced during sleep modes other than DeepStop and Static and during normal operation. 198 32099A–AVR32–06/09 AT32UC3L The user can select the period of the checks in “sampling” mode through the SM33.SAMPFREQ. The sampling mode uses the 32kHz RC oscillator (RC32K) as a clock. The 32kHz RC oscillator is turned on automatically with sampling mode is used The POR33 can be turned off by software to reduce power consumption, please refer to the Voltage Regulator section for details. The SM33 can then be used to monitor the VDDIN power supply. 14.5.10 Temperature Sensor The Temperature Sensor is connected to the ADC channel 7. It is enabled by writing one to the EN bit in the TSENS register. Temperature sensor does not have calibration register Please refer to the Electrical Characteristics chapter for Temperature/Voltage curves. 14.5.11 120MHz RC Oscillator (RC120M) The 120MHz RC Oscillator can be used for the main clock in the device, as described in the Power Manager chapter. The oscillator can be used as source for the generic clocks, as described in “Generic clocks” on page 196. The clock is enabled by writing one to EN bit in RC120MCR register and disabled by writing zero to the EN bit. The oscillator is automatically switched off in certain sleep modes to reduce power consumption, as described in the Power Manager chapter. 14.5.12 Backup Registers Four 32-bit registers with are available to keep values when the chip is in Shutdown mode. Those registers will keep their content even when the VDDCORE, VDDIN and VDDIO powers are removed. The backup registers can be accessed by reading and writing BR0, BR1, BR2 and BR3 registers. After writing to one of the backup registers the user must wait until the Backup Register Interface Ready (BRIFARDY) bit in the PCLKSR register is set before writing to another backup register. Writes to the backup register while BRIFARDY is zero will be discarded. The BRIFARDY can also trigger an interrupt if the corresponding bit is set in the IMR register. After powering up the device the Backup Register Interface Valid (BRIFAVALID) bit in the PCLKSR register is cleared, indicating that the contents of the backup registers has not been written and contains the reset value. After writing one of the backup registers the BRIFAVALID bit is set. During writes to the backup registers (when BRIFARDY is zero) BRIFAVALID will be zero. If a reset occurs when the BRIFARDY is zero, BRIFAVALID will be cleared after the reset, indicating that the contents of the backup registers are not valid. If BRIFARDY was one when the reset occurred, BRIFAVALID will be one and the contents are the same as before the reset. The user must ensure that BRIFAVALID and BRIFARDY is both set before reading the backup register values. 14.5.13 32kHz RC Oscillator (RC32K) The 32kHz RC oscillator (RC32K) is enabled by default after reset, and output on PB04. The clock is available on the pad until the bit PM.PPCR.RC32OUT has been cleared in the Power Manager or a different peripheral function has been chosen on port PB04 (port PB04 will start with peripheral function “F” by default). 199 32099A–AVR32–06/09 AT32UC3L The RC32K can be used as source for the generic clocks, as described in “Generic clocks” on page 196. The clock is enabled by writing one to EN bit in RC32KCR register and disabled by writing zero to the EN bit. The oscillator is also automatically turned on when the sampling mode is requested for the SM33. In this case, clearing the EN bit will not stop the RC32K until the sampling mode is no longer requested. 14.5.14 Interrupts The SCIF has 14 separate interrupt sources: • AE - Access Error: – Set when a protected SCIF register was accessed without first being correctly unlocked. • BRIFARDY - Backup Register Interface Ready. – Set on 0 to 1 transition on the PCLKSR.BRIFARDY bit is detected. • DFLL0RCS - DFLL Reference Clock Stopped: – Set on 0 to 1 transition on the PCLKSR.DFLLRCS bit is detected. • DFLL0RDY - DFLL Ready: – Set on 0 to 1 transition on the PCLKSR.DFLLRDY bit is detected. • DFLL0LOCKLOSTA - DFLL lock lost on Accurate value: – Set on 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTA bit is detected. • DFLL0LOCKLOSTF - DFLL lock lost on Fine value: – Set on 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTF bit is detected. • DFLL0LOCKLOSTC - DFLL lock lost on Coarse value: – Set on 0 to 1 transition on the PCLKSR.DFLLLOCKLOSTC bit is detected. • DFLL0LOCKA - DFLL Locked on Accurate value: – Set on 0 to 1 transition on the PCLKSR.DFLLLOCKA bit is detected. • DFLL0LOCKF - DFLL Locked on Fine value: – Set on 0 to 1 transition on the PCLKSR.DFLLLOCKF bit is detected. • DFLL0LOCKC - DFLL Locked on Coarse value: – Set on 0 to 1 transition on the PCLKSR.DFLLLOCKC bit is detected. • BODDET - Brown out detection: – Set on 0 to 1 transition on the PCLKSR.BODDET bit is detected. • SM33DET - Supply Monitor 3.3V Detector: – Set on 0 to 1 transition on the PCLKSR.SM33DET bit is detected. • VREGOK - Voltage Regulator OK: – Set on 0 to 1 transition on the PCLKSR.VREGOK bit is detected. • OSCRDY - OSCReady: – Set on 0 to 1 transition on the PCLKSR.OSCRDY bit is detected. • OSC32RDY - 32KHz Oscillator Ready: – Set on 0 to 1 transition on the PCLKSR.OSC32RDY bit is detected. The interrupt sources will generate a interrupt request if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the 200 32099A–AVR32–06/09 AT32UC3L Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt Status Register (ISR) is cleared by writing a one to the corresponding bit in the Interrupt Clear Register (ICR). 201 32099A–AVR32–06/09 AT32UC3L 14.6 User Interface SCIF Register Memory Map Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Power and Clocks Status Register Unlock Register Oscillator Control Register Oscillator 32 Control Register DFLL Config Register DFLL Multiplier Register DFLL Step Register DFLL Spread Spectrum Generator Control Register DFLL Ratio Register DFLL Synchronization Register BOD Level Register Bandgap Calibration Register Voltage Regulator Calibration Register System RC Oscillator Calibration Register Supply Monitor 33 Calibration Register Temperature Sensor Calibration Register 120MHz RC Oscillator Control Register Backup Registers 32kHz RC Oscillator Control Register Generic Clock Control Oscillator 0 Version Register 32 KHz Oscillator Version Register DFLL Version Register BOD Version Register Voltage Regulator Version Register System RC Oscillator Version Register 3.3V Supply Monitor Version Register Temperature Sensor Version Register Register Name IER IDR IMR ISR ICR PCLKSR UNLOCK OSCCTRL0 OSCCTRL32 DFLL0CONF DFLL0MUL DFLL0STEP DFLL0SSG DFLL0RATIO DFLL0SYNC BOD BGCR VREGCR RCCR SM33 TSENS RC120MCR BR RC32KCR GCCTRL OSC0VERSION OSC32VERSION DFLLIFVERSION BODIFAVERSION VREGIFBVERSION RCOSCIFAVERSION SM33IFAVERSION TSENSIFAVERSION Access Write-only Write-only Read-only Read-only Write-only Read-only Write-only Read/Write Read/Write Read/Write Write-only Write-only Write-only Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000004 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) -(1) -(1) -(1) -(1) -(1) -(1) -(1) Table 14-3. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0058 0x005C-0x0068 0x006C 0x0070-0x0080 0x03C8 0x03CC 0x03D0 0x03D4 0x03D8 0x03DC 0x03E0 0x03E4 202 32099A–AVR32–06/09 AT32UC3L Table 14-3. Offset 0x03EC 0x03F0 0x03F4 0x03F8 0x03FC Note: SCIF Register Memory Map Register 120MHz RC Oscillator Version Register Backup Register Interface Version Register 32kHz RC Oscillator Version Register Generic Clock Version Register SCIF Version Register Register Name RC120MIFAVERSION BRIFAVERSION RC32KIFAVERSION GCLKVERSION VERSION Access Read-only Read-only Read-only Read-only Read-only Reset -(1) -(1) -(1) -(1) -(1) 1. The reset value is device specific. Please refer to the Module Configuration section at the end of this chapter. 203 32099A–AVR32–06/09 AT32UC3L 14.6.1 Name: Access Type: Offset: Reset Value: Interrupt Enable Register IER Write-only 0x0000 0x00000000 31 AE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BRIFARDY 15 DFLL0RCS 14 DFLL0RDY 13 DFLL0LOCK LOSTA 12 DFLL0LOCK LOSTF 11 DFLL0LOCK LOSTC 10 DFLL0LOCK A 9 DFLL0LOCK F 8 DFLL0LOCK C 7 BODDET 6 SM33DET 5 VREGOK 4 - 3 - 2 - 1 OSC0RDY 0 OSC32RDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 204 32099A–AVR32–06/09 AT32UC3L 14.6.2 Name: Access Type: Offset: Reset Value: Interrupt Disable Register IDR Write-only 0x0004 0x00000000 31 AE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BRIFARDY 15 DFLL0RCS 14 DFLL0RDY 13 DFLL0LOCK LOSTA 12 DFLL0LOCK LOSTF 11 DFLL0LOCK LOSTC 10 DFLL0LOCK A 9 DFLL0LOCK F 8 DFLL0LOCK C 7 BODDET 6 SM33DET 5 VREGOK 4 - 3 - 2 - 1 OSC0RDY 0 OSC32RDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 205 32099A–AVR32–06/09 AT32UC3L 14.6.3 Name: Access Type: Offset: Reset Value: Interrupt Mask Register IMR Read-only 0x0008 0x00000000 31 AE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BRIFARDY 15 DFLL0RCS 14 DFLL0RDY 13 DFLL0LOCK LOSTA 12 DFLL0LOCK LOSTF 11 DFLL0LOCK LOSTC 10 DFLL0LOCK A 9 DFLL0LOCK F 8 DFLL0LOCK C 7 BODDET 6 SM33DET 5 VREGOK 4 - 3 - 2 - 1 OSC0RDY 0 OSC32RDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 206 32099A–AVR32–06/09 AT32UC3L 14.6.4 Name: Access Type: Offset: Reset Value: Interrupt Status Register ISR Read-only 0x000C 0x00000000 31 AE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BRIFARDY 15 DFLL0RCS 14 DFLL0RDY 13 DFLL0LOCK LOSTA 12 DFLL0LOCK LOSTF 11 DFLL0LOCK LOSTC 10 DFLL0LOCK A 9 DFLL0LOCK F 8 DFLL0LOCK C 7 BODDET 6 SM33DET 5 VREGOK 4 - 3 - 2 - 1 OSC0RDY 0 OSC32RDY 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding interrupt occurs. 207 32099A–AVR32–06/09 AT32UC3L 14.6.5 Name: Access Type: Offset: Reset Value: Interrupt Clear Register ICR Write-only 0x0010 0x00000000 31 AE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BRIFARDY 15 DFLL0RCS 14 DFLL0RDY 13 DFLL0LOCK LOSTA 12 DFLL0LOCK LOSTF 11 DFLL0LOCK LOSTC 10 DFLL0LOCK A 9 DFLL0LOCK F 8 DFLL0LOCK C 7 BODDET 6 SM33DET 5 VREGOK 4 - 3 - 2 - 1 OSC0RDY 0 OSC32RDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR. 208 32099A–AVR32–06/09 AT32UC3L 14.6.6 Name: Access Type: Offset: Reset Value: Power and Clocks Status Register PCLKSR Read-only 0x0014 0x00000000 31 - 30 BRIFAVALID 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 BRIFARDY 15 DFLL0RCS 14 DFLL0RDY 13 DFLL0LOCK LOSTA 12 DFLL0LOCK LOSTF 11 DFLL0LOCK LOSTC 10 DFLL0LOCK A 9 DFLL0LOCK F 8 DFLL0LOCK C 7 BODDET 6 SM33DET 5 VREGOK 4 - 3 - 2 - 1 OSC0RDY 0 OSC32RDY • BRIFAVALID: Backup Register Interface Valid 0: The values in the backup registers are not valid. 1: The values in the backup registers are valid. • BRIFARDY: Backup Register Interface Ready 0: The backup register interface is busy updating the backup registers. Writes to BRn will be discarded. 1: The backup register interface is ready to accept new writes to the backup registers. • DFLLRCS: DFLL0 Reference Clock Stopped 0: The DFLL0 reference clock is running, or has never been enabled. 1: The DFLL0 reference clock has stopped. • DFLL0RDY: DFLL0 Synchronization Ready 0: Read or write to DFLL0 registers is invalid 1: Read or write to DFLL0 registers is valid • DFLLLOCKLOSTA: DFLL lock lost on Accurate value 0: DFLL has not lost its Accurate lock or has never been enabled. 1: DFLL has lost its Accurate lock, either by disabling the DFLL or due to faulty operation. • DFLLLOCKLOSTF: DFLL lock lost on Fine value 0: DFLL has not lost its Fine lock or has never been enabled. 1: DFLL has lost its Fine lock, either by disabling the DFLL or due to faulty operation. • DFLLLOCKLOSTC: DFLL lock lost on Coarse value 0: DFLL has not lost its Coarse lock or has never been enabled. 1: DFLL has lost its Coarse lock, either by disabling the DFLL or due to faulty operation. • DFLLLOCKA: DFLL Locked on Accurate value 0: DFLL is unlocked on Accurate value. 1: DFLL is locked on Accurate value, and is ready to be selected as clock source with an accurate output clock. • DFLLLOCKF: DFLL Locked on Fine value 209 32099A–AVR32–06/09 AT32UC3L 0: DFLL is unlocked on Fine value. 1: DFLL is locked on Fine value, and is ready to be selected as clock source with a highly accurate output clock. DFLLLOCKC: DFLL Locked on Coarse value 0: DFLL is unlocked on Coarse value. 1: DFLL is locked on Fine value, and is ready to be selected as clock source with medium accuracy on the output clock. BODDET: Brown out detection 0: No BOD Event. 1: BOD has detected that power supply is going below BOD reference value. SM33DET: Supply Monitor 3.3V Detector 0: SM33 not enabled or the supply voltage is above the SM33 threshold. 1: SM33 enabled and the supply voltage is below the SM33 threshold. VREGOK: Voltage Regulator OK 0: Voltage regulator not enabled or not ready. 1: Voltage regulator has reached its output threshold value after being enabled. OSC0RDY: OSC0 Ready 0: Oscillator not enabled or not ready. 1: Oscillator is stable and ready to be used as clock source. OSC32RDY: 32 KHz oscillator Ready 0: Oscillator 32 not enabled or not ready. 1: Oscillator 32 is stable and ready to be used as clock source. • • • • • • 210 32099A–AVR32–06/09 AT32UC3L 14.6.7 Name: Access Type: Offset: Reset Value: Unlock Register UNLOCK Write-only 0x0018 0x00000000 31 30 29 28 KEY 27 26 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 ADDR[9:8] 8 7 6 5 4 ADDR[7:0] 3 2 1 0 To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field. Then, in the next PB access write to the register specified in the ADDR field. • KEY: Unlock Key Write this bit field to 0xAA to enable unlock. • ADDR: Unlock Address Write the address of the register to unlock to this field. 211 32099A–AVR32–06/09 AT32UC3L 14.6.8 Name: Access Type: Offset: Reset Value: Oscillator Control Register OSCCTRL0 Read/Write 0x001C 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 AGC 26 18 10 25 17 9 STARTUP 24 16 OSCEN 8 2 GAIN 1 0 MODE • OSCEN 0: Disable the Oscillator. 1: Enable the Oscillator • STARTUP: Oscillator Startup Time Select startup time for the oscillator. Table 14-4. STARTUP 0 1 2 3 4 5 6 7 Startup time for oscillators 0 and 1 Number of System RC oscillator clock cycle 0 64 128 2048 4096 8192 16384 Reserved Approximative Equivalent time (RCSYS = 115 kHz) 0 560 us 1.1 ms 18 ms 36 ms 71 ms 142 ms Reserved • AGC: Automatic Gain Control For test purposes • GAIN: Gain Set the gain for the oscillator • MODE: Oscillator Mode 0: External clock connected on XIN, XOUT can be used as an I/O (no crystal) 1: Crystal is connected to XIN/XOUT 212 32099A–AVR32–06/09 AT32UC3L Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 213 32099A–AVR32–06/09 AT32UC3L 14.6.9 Name: Access Type: Offset: Reset Value: 32KHz Oscillator Control Register OSCCTRL32 Read/Write 0x0020 0x00000004 31 RESERVED 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 EN1K 26 18 25 17 STARTUP 24 16 10 9 MODE 8 2 EN32K 1 PINSEL 0 OSC32EN Note: This register is only reset by Power-On Reset • RESERVED This bit should always be written to zero. • STARTUP: Oscillator Startup Time Select startup time for 32 KHz oscillator Table 14-5. STARTUP 0 1 2 3 4 5 6 7 Startup time for 32 KHz oscillator Number of RC oscillator clock cycle 0 128 8192 16384 65536 131072 262144 524288 Approximative Equivalent time (RCOsc = 115 kHz) 0 1.1 ms 72.3 ms 143 ms 570 ms 1.1 s 2.3 s 4.6 s 214 32099A–AVR32–06/09 AT32UC3L • MODE: Oscillator Mode Table 14-6. MODE 0 1 2 3 4 5 6 7 Operation mode for 32 KHz oscillator Description External clock connected to XIN32, XOUT32 can be used as I/O (no crystal) Crystal mode. Crystal is connected to XIN32/XOUT32. Reserved Reserved Crystal and high current mode. Crystal is connected to XIN32/XOUT32. Reserved Reserved Reserved • EN1K: Enable the 1 KHz output 0: 1 KHz output is disabled 1: 1 KHz output is enabled • EN32K: Enable the 32 KHz output 0: 32 KHz output is disabled 1: 32 KHz output is enabled • PINSEL: Select pins used for 32 KHz crystal oscillator 0: Default pins 1: Alternate pins: XIN32_2 pin is used instead of XIN32 pin, XOUT32_2 pin is used instead of XOUT32 • OSC32EN: Enable the 32 KHz oscillator 0: 32 KHz Oscillator is disabled 1: 32 KHz Oscillator is enabled 215 32099A–AVR32–06/09 AT32UC3L 14.6.10 Name: Access Type: Offset: Reset Value: DFLL0 Configuration Register DFLL0CONF Read/Write 0x0024 0x00000000 31 30 29 28 COARSE 27 26 25 24 23 15 22 14 21 13 20 12 FINE 19 11 18 10 17 9 16 FINE 8 7 - 6 - 5 - 4 - 3 - 2 DITHER 1 MODE 0 EN • COARSE: Coarse calibration register value Set the value of the coarse calibration register. If in closed loop mode, this field is Read-only. • FINE: FINE calibration register value Set the value of the fine calibration register. If in closed loop mode, this field is Read-only. • DITHER: Enable Dithering 0: The fine LSB input to the VCO is constant 1: The fine LSB input to the VCO is dithered to achieve fractional approximation to the correct multiplication ratio • MODE: Mode Selection 0: DFLL in Open Loop operation. 1: DFLL in Closed Loop operation. • EN: Enable 0: DFLL is disabled. 1: DFLL is enabled. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 216 32099A–AVR32–06/09 AT32UC3L 14.6.11 Name: Access Type: Offset: Reset Value: DFLL0 Multiplier Register DFLL0MUL Read/Write 0x0028 0x00000000 31 30 29 28 27 26 25 24 DFLLMUL[31:24] 23 22 21 20 19 18 17 16 DFLLMUL[23:16] 15 14 13 12 11 10 9 8 DFLLMUL[15:8] 7 6 5 4 DFLLMUL[7:0] • DFLLMUL: DFLL Multiply Factor This field determines the ratio of the DFLL output frequency to the source clock frequency. The 16 most significant bits are used as the integer part, while the 16 least significant bits are used as the fractional part. In open loop mode, writing to this register has no effect. 3 2 1 0 Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 217 32099A–AVR32–06/09 AT32UC3L 14.6.12 Name: Access Type: Offset: Reset Value: DFLL0 Maximum Step Register DFLL0STEP Read-only 0x002C 0x00000000 31 23 30 22 29 21 28 20 FSTEP[7:0] 27 19 26 18 25 17 24 FSTEP[8] 16 15 7 14 6 13 5 12 4 CSTEP[7:0] 11 3 10 2 9 1 8 0 • FSTEP: Fine Maximum Step This indicated the maximum step size during fine adjustment in closed-loop mode. When adjusting to a new frequency, the expected overshoot of that frequency depends on this step size. • CSTEP: Coarse Maximum Step This indicated the maximum step size during coarse adjustment in closed-loop mode. When adjusting to a new frequency, the expected overshoot of that frequency depends on this step size. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 218 32099A–AVR32–06/09 AT32UC3L 14.6.13 Name: Access Type: Offset: Reset Value: DFLL0 Spread Spectrum Generator Control Register DFLL0SSG Read/Write 0x0030 0x00000000 31 30 29 28 RECAL 27 26 25 24 23 15 7 - 22 14 6 - 21 13 5 - 20 19 18 STEPSIZE 17 16 12 11 10 AMPLITUDE 9 8 4 - 3 - 2 - 1 PRBS 0 EN • STEPSIZE: SSG Step Size. Sets the step size of the spread spectrum. If set to zero or one, the value added to the FINE bits will be incremented/decremented with one on every positive edge of the input clock. If set to n, the value added to the FINE bits will be incremented/decremented with n on every positive edge of the input clock. • AMPLITUDE: SSG Amplitude. Sets the amplitude of the spread spectrum. If set to zero, only the LSB of the FINE bits will be affected. If set to one, the sequence {1, 0, -1, 0} will be added to FINE bits, etc. • PRBS: Pseudo Random Bit Sequence 0: Each spread spectrum frequency is applied at constant intervals 1: Each spread spectrum frequency is applied at pseudo-random intervals • EN: Enable 0: SSG is disabled. 1: SSG is enabled. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 219 32099A–AVR32–06/09 AT32UC3L 14.6.14 Name: Access Type: Offset: Reset Value: DFLL0 Ratio Register DFLL0RATIO Read-only 0x0034 0x00000000 31 30 29 28 27 26 25 24 RATIODIFF[15:8] 23 22 21 20 19 18 17 16 RATIODIFF[7:0] 15 7 14 - 13 - 12 - 11 - 10 - 9 - 8 - 6 - 5 - 4 3 2 NUMREF[4:0] 1 0 • RATIODIFF: Multiplication Ratio Difference In closed-loop mode, these fields indicate the error of the ratio between the VCO frequency and the reference clock frequency: error = RATIODIFF >> NUMREF • NUMREF: Numerical Reference 220 32099A–AVR32–06/09 AT32UC3L 14.6.15 Name: Access Type: Offset: Reset Value: DFLL0 Synchronization Register DFLL0SYNC Write-only 0x0038 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 SYNC • SYNC: Synchronization To be able to read the current value of DFLL0CONF or DFLL0RATIO in closed-loop mode, this bit should be written to one. The updated value is available in DFLL0CONF and DFLL0RATIO when PCLKSR.DFLL0RDY goes high. 221 32099A–AVR32–06/09 AT32UC3L 14.6.16 Name: Access Type: Offset: Reset Value: BOD Control Register BOD Read/Write 0x003C 0x00000000 31 SFV 23 15 7 - 30 22 14 6 HYST 29 21 13 5 28 20 12 4 27 19 11 3 LEVEL 26 18 10 2 25 17 9 CTRL 1 24 16 FCD 8 0 • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes. • FCD: BOD Fuse Calibration Done Set to 1 when the CTRL, HYST and LEVEL field has been updated by the Flash fuses after power-on reset or Flash fuses update. If one, the CTRL, HYST and LEVEL values will not be updated again by Flash fuses. Can be cleared to allow subsequent overwriting of the value by Flash fuses. • CTRL: BOD Control Table 14-7. CTRL 0 1 2 3 Operation mode for BOD Description BOD is off BOD is enabled and can reset the chip BOD is enabled and but cannot reset the chip. Only interrupt will be sent to interrupt controller, if enabled in the IMR register. Reserved • HYST: BOD Hysteresis 0: No hysteresis 1: Hysteresis on. • LEVEL: BOD Level This field sets the triggering threshold of the BOD. See Electrical Characteristics for actual voltage levels. Note that any change to the LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset or interrupt. 222 32099A–AVR32–06/09 AT32UC3L Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 223 32099A–AVR32–06/09 AT32UC3L 14.6.17 Name: Access Type: Offset: Reset Value: Bandgap Calibration Register BGCR Read/Write 0x0040 0x00000000 31 SFV 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 25 17 9 1 CALIB 24 16 FCD 8 0 • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes. • FCD: Flash Calibration Done Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero. • CALIB: Calibration value Calibration value for Bandgap. See Electrical Characteristics for voltage values. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 224 32099A–AVR32–06/09 AT32UC3L 14.6.18 Name: Access Type: Offset: Reset Value: Voltage Regulator Calibration Register VREGCR Read/Write 0x0044 0x00000000 31 SFV 23 - 30 INTPD 22 - 29 21 - 28 20 POR33MASK 27 19 POR33STAT US 11 26 18 POR33EN 25 17 DEEPDIS 24 16 FCD 15 7 ON 14 6 VREGOK 13 5 EN 12 4 - 10 CALIB 9 8 3 - 2 1 SELVDD 0 • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes. • INTPD: Internal Pulldown This bit is used for test purposes only. 0: The voltage regulator output is not pulled to ground 1: The voltage regulator output has a pulldown to ground • POR33MASK: Power-On Reset 3.3V output Mask 0: Power-On Reset 3.3V is not masked 1: Power-On Reset 3.3V is masked • POR33STATUS: Power-On Reset 3.3V Status 0: Power-On Reset 3.3V is currently disabled 1: Power-On Reset 3.3V is currently enabled This bit is a read-only bit. Writing to this bit has no effect. • POR33EN: Power-On Reset 3.3V Enable 0: Disable the 3.3V POR detector 1: Enable the 3.3V POR detector • DEEPDIS: Disable Regulator Deep Mode 0: Regulator will enter deep mode in low-power sleep modes for lower power consumption 1: Regulator will stay in full-power mode in all sleep modes for shorter start-up time • FCD: Flash Calibration Done Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero. • CALIB: Calibration value Calibration value for Voltage Regulator. See Electrical Characteristics for voltage values. • ON: Voltage Regulator On Status 225 32099A–AVR32–06/09 AT32UC3L 0: The voltage regulator is currently turned off 1: The voltage regulator is currently turned on This bit is a read-only bit. Writing to this bit has no effect. • VREGOK: Voltage Regulator OK Status 0: The voltage regulator is disabled or has not yet reached a stable output voltage 1: The voltage regulator has reached the output voltage threshold level after being enabled This bit is a read-only bit. Writing to this bit has no effect • EN: Enable the voltage regulator 0: The voltage regulator is disabled 1: The voltage regulator is enabled Note: This bit is set to one after a Power On Reset • SELVDD: Select VDD Output voltage of the Voltage Regulator. See Electrical Characteristics for voltage values. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 226 32099A–AVR32–06/09 AT32UC3L 14.6.19 Name: Access Type: Offset: Reset Value: RC Oscillator Calibration Register RCCR Read/Write 0x0048 0x00000000 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 CALIB[7:0] 27 19 11 3 26 18 10 2 25 17 9 CALIB[9:8] 1 24 16 FCD 8 0 • FCD: Flash Calibration Done Set to 1 when CALIB fields has been updated by the Flash fuses after power-on reset, or after Flash fuses are reprogrammed. The CALIB value will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero. • CALIB: Calibration Value Calibration Value for the RC oscillator. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 227 32099A–AVR32–06/09 AT32UC3L 14.6.20 Name: Access Type: Offset: Reset Value: Supply Monitor 33 Calibration Register SM33 Read/Write 0x004C 0x00000000 31 23 15 7 FS 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 26 SAMPFREQ 25 24 19 11 18 ONSM 10 CALIB 17 SFV 9 16 FCD 8 3 2 CTRL 1 0 • SAMPFREQ: Sampling Frequency Selects the sampling mode frequency of the 3.3V supply monitor. In sampling mode, the SM33 performs a measurement every 2(SAMPFREQ+5) cycles of the internal 32kHz RC oscillator. • ONSM: Supply Monitor On Indicator 0: The supply monitor is off. 1: The supply monitor is on. This bit is read-only. Writing to this bit has no effect. • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes. • FCD: Flash Calibration Done Set to 1 when CALIB fields has been updated by the Flash fuses after power-on reset, or after Flash fuses are reprogrammed. The CALIB value will not be updated again by the Flash fuses until a new power-on reset or the FCD field is written to zero. • CALIB: Calibration Value Calibration Value for the SM33. • FS: Force Sampling Mode 0: Sampling mode is enabled in DeepStop and Static mode only. 1: Sampling mode is always enabled. • CTRL: Supply Monitor Control 228 32099A–AVR32–06/09 AT32UC3L Selects the operating mode for the SM33 Table 14-8. CTRL 0 1 2 3 Operation mode for SM33 Description SM33 is off SM33 is enabled and can reset the chip SM33 is enabled and but cannot reset the chip. Only interrupt will be sent to interrupt controller, if enabled in the IMR register. SM33 is off Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 229 32099A–AVR32–06/09 AT32UC3L 14.6.21 Name: Access Type: Offset: Reset Value: Temperature Sensor Calibration Register TSENS Read/Write 0x0050 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 27 19 11 3 26 18 10 2 - 25 17 9 1 - 24 16 8 0 EN • EN: Temperature Sensor Enable 0: Temperature sensor is disabled 1: Temperature sensor is enabled Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 230 32099A–AVR32–06/09 AT32UC3L 14.6.22 Name: Access Type: Offset: Reset Value: 120MHz RC Oscillator Configuration Register RC120M Read/Write 0x0058 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 EN • EN: RC120M Enable 0: Clock is stopped. 1: Clock is running. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 231 32099A–AVR32–06/09 AT32UC3L 14.6.23 Name: Access Type: Offset: Reset Value: Backup Register n BRn Read/Write 0x005C-0x0068 0x00000000 31 30 29 28 DATA[31:24] 27 26 25 24 23 22 21 20 DATA[23:16] 19 18 17 16 15 14 13 12 DATA[15:8] 11 10 9 8 7 6 5 4 DATA[7:0] 3 2 1 0 This is a set of general purpose read-write registers. Data stored in these registers is retained when the device is shut off. Before writing to these registers the user must ensure that BRIFARDY in the PCLKSR register is not set. Note that this registers are protected by a lock. To write to these registers the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 232 32099A–AVR32–06/09 AT32UC3L 14.6.24 Name: Access Type: Offset: Reset Value: 32kHz RC Oscillator Configuration Register RC32KCR Read/Write 0x006C 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 EN • EN: RC32K Enable 0: Clock is stopped. 1: Clock is running. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details. 233 32099A–AVR32–06/09 AT32UC3L 14.6.25 Name: Access Type: Offset: Reset Value: Generic Clock Control GCCTRL Read/Write 0x0070-0x0080 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 DIV 19 18 17 16 15 14 13 12 11 10 OSCSEL 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 DIVEN 0 CEN There is one GCCTRL register per generic clock in the design. • DIV: Division Factor • OSCSEL: Oscillator Select Table 14-9. OSCSEL 0 1 2 3 4 5 6 7 8 9 10 11 12-15 Generic Clock Sources Clock/Oscillator RCSYS OSC32K DFLL OSC0 RC120M CLK_CPU CLK_HSB CLK_PBA CLK_PBB RC32K Reserved CLK_1K Reserved 1KHz output clock from OSC32K Description System RC oscillator clock Output clock from OSC32K Output clock from DFLL Output clock from Oscillator Output from 120MHz RCOSC The clock the CPU runs on High Speed Bus clock Peripheral Bus A clock Peripheral Bus B clock Output from 32KHz RCOSC • DIVEN: Divide Enable 234 32099A–AVR32–06/09 AT32UC3L 0: The generic clock equals the undivided source clock. 1: The generic clock equals the source clock divided by 2*(DIV+1). • CEN: Clock Enable 0: Clock is stopped. 1: Clock is running. 235 32099A–AVR32–06/09 AT32UC3L 14.6.26 Name: Access Type: Offset: Reset Value: Oscillator 0 Version Register OSC0VERSION Read-only 0x03C8 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 236 32099A–AVR32–06/09 AT32UC3L 14.6.27 Name: Access Type: Offset: Reset Value: 32KHz Oscillator Version Register OSC32VERSION Read-only 0x03CC - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 237 32099A–AVR32–06/09 AT32UC3L 14.6.28 Name: Access Type: Offset: Reset Value: Digital Frequency Locked Loop Version Register DFLLIF VERSION Read-only 0x03D0 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 238 32099A–AVR32–06/09 AT32UC3L 14.6.29 Name: Access Type: Offset: Reset Value: Brown-Out Detector Version Register BODIFAVERSION Read-only 0x03D4 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 239 32099A–AVR32–06/09 AT32UC3L 14.6.30 Name: Access Type: Offset: Reset Value: Voltage Regulator Version Register VREGIFBVERSION Read-only 0x03D8 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 240 32099A–AVR32–06/09 AT32UC3L 14.6.31 Name: Access Type: Offset: Reset Value: RC Oscillator Version Register RCOSCIFAVERSION Read-only 0x03DC - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 241 32099A–AVR32–06/09 AT32UC3L 14.6.32 Name: Access Type: Offset: Reset Value: 3.3V Supply Monitor Version Register SM33IFAVERSION Read-only 0x03E0 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 242 32099A–AVR32–06/09 AT32UC3L 14.6.33 Name: Access Type: Offset: Reset Value: Temperature Sensor Version Register TSENSIFAVERSION Read-only 0x03E4 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 243 32099A–AVR32–06/09 AT32UC3L 14.6.34 Name: Access Type: Offset: Reset Value: 120MHz RC Oscillator Version Register RC120MIFAVERSION Read-only 0x03EC - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 244 32099A–AVR32–06/09 AT32UC3L 14.6.35 Name: Access Type: Offset: Reset Value: Backup Register Interface Version Register BRIFAVERSION Read-only 0x03F0 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 245 32099A–AVR32–06/09 AT32UC3L 14.6.36 Name: Access Type: Offset: Reset Value: 32kHz RC Oscillator Version Register RC32KIFAVERSION Read-only 0x03F4 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 246 32099A–AVR32–06/09 AT32UC3L 14.6.37 Name: Access Type: Offset: Reset Value: Generic Clock Version Register GCLKVERSION Read-only 0x03F8 - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 247 32099A–AVR32–06/09 AT32UC3L 14.6.38 Name: Access Type: Offset: Reset Value: SCIF Version Register VERSION Read-only 0x03FC - 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:0] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 248 32099A–AVR32–06/09 AT32UC3L 14.7 Module Configuration The specific configuration for each SCIF instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 14-10. SCIF Clock Name Module Name SCIF Clock Name CLK_SCIF Table 14-11. Register Reset Values Register OSC0VERSION OSC32VERSION DFLLVIFERSION BODIFAVERSION VREGIFBVERSION RCOSCIFAVERSION SM33IFAVERSION TSENSIFAVERSION RC120MIFAVERSION BRIFAVERSION RC32KIFAVERSION GCLKVERSION VERSION Reset Value 0x00000100 0x00000101 0x00000201 0x00000101 0x00000101 0x00000101 0x00000100 0x00000100 0x00000101 0x00000100 0x00000100 0x00000100 0x00000102 249 32099A–AVR32–06/09 AT32UC3L 15. Asynchronous Timer (AST) Rev: 3.0.0.0 15.1 Features • 32-bit counter with 32-bit prescaler • Clocked Source – System RC oscillator (RCSYS) – 32KHz crystal oscillator (OSC32K) – PB clock – Generic clock (GCLK) – 1KHz clock from 32KHz oscillator Operation and wakeup during shutdown Optional calendar mode supported Digital prescaler tuning for increased accuracy Periodic interrupt(s) and peripheral event(s) supported Alarm interrupt(s) and peripheral event(s) supported – Optional clear on alarm • • • • • 15.2 Overview The Asynchronous Timer (AST) enables periodic interrupts and periodic peripheral events, as well as interrupts and peripheral events at a specified time in the future. The AST consists of a 32-bit prescaler which feeds a 32-bit up-counter. The prescaler can be clocked from five different clock sources, including the low-power 32KHz oscillator, which allows the AST to be used as a real-time timer with a maximum timeout of more than 100 years. Also, the PB clock or a generic clock can be used for high-speed operation, allowing the AST to be used as a general timer. The AST can generate periodic interrupts and peripheral events from output from the prescaler, as well as alarm interrupts and peripheral events, which can trigger at any counter value. Additionally, the timer can trigger an overflow interrupt and peripheral event, and be reset on the occurrence of any alarm. This allows periodic interrupts and peripheral events at very long and accurate intervals. To keep track of time during shutdown the AST can run while the rest of the core is powered off. This will reduce the power consumption when the system is idle. The AST can also wake up the system from shutdown using either the alarm wakeup, periodic wakeup. or overflow wakeup mechanisms. The AST has been designed to meet the system tick and Real Time Clock requirements of most embedded operating systems. 250 32099A–AVR32–06/09 AT32UC3L 15.3 Block Diagram Figure 15-1. Asynchronous Timer Block Diagram CLK_AST WAKE ENABLE REGISTER CLK_AST CSSEL CONTROL REGISTER EN PSEL CLK_AST COUNTER VALUE Wake Control Wake OSC32 RCOSC PB clock GCLK CLK_1K CLK_AST_PRSC 32-bit Prescaler CLK_AST_CNT 32-bit Counter OVF Periodic Interrupts Alarm Interrupts Interrupt Status and Control IRQs Events DIGITAL TUNER REGISTER PERIODIC INTERVAL REGISTER ALARM REGISTER 15.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 15.4.1 Power Management When the AST is enabled, it will remain clocked as long as its selected clock source is running. It can also wake the CPU from the currently active sleep mode. Refer to the Power Manager chapter for details on the different sleep modes. Clocks The clock for the AST bus interface (CLK_AST) is generated by the Power Manager. This clock is turned on by default, and can be enabled and disabled in the Power Manager. A number of clocks can be selected as source for the internal prescaler clock CLK_AST_PRSC. The prescaler, counter, and interrupt will function as long as this selected clock source is active. The selected clock must be enabled in the System Control Interface (SCIF). The following clock sources are available: • System RC oscillator (RCSYS). This oscillator is always enabled, except in some sleep modes. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator. • 32KHz crystal oscillator (OSC32K). This oscillator must be enabled before use. • Peripheral Bus clock (PB clock). This is the clock of the peripheral bus the AST is connected to. 15.4.2 251 32099A–AVR32–06/09 AT32UC3L • Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be enabled before use, and remains enabled in sleep modes when the PB clock is active. • 1KHz clock from the 32KHz oscillator (CLK_1K). This clock is only available in crystal mode, and must be enabled before use. Please refer to the SCIF chapter for details. In Shutdown mode only the 32 KHz oscillator and the 1KHz clock are available, using certain pins. Please refer to the Power Manager chapter for details. 15.4.3 Interrupts The AST interrupt request lines are connected to the interrupt controller. Using the AST interrupts requires the interrupt controller to be programmed first. 15.4.4 Peripheral Events The AST peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. Debug Operation The AST prescaler and counter is frozen during debug operation, unless the Run In Debug bit in the Development Control Register is set and the bit corresponding to the AST is set in the Peripheral Debug Register. Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference Manual for details. If the AST is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 15.4.5 15.5 15.5.1 Functional Description Initialization Before enabling the AST, the internal AST clock CLK_AST_PRSC must be enabled, following the procedure specified in Section 15.5.1.1. The Clock Source Select field in the Clock register (CLOCK.CSSEL) selects the source for this clock. The Clock Enable bit in the Clock register (CLOCK.CEN) enables the CLK_AST_PRSC. When CLK_AST_PRSC is enabled, the AST can be enabled by writing a one to the Enable bit in the Control Register (CR.EN). 15.5.1.1 Enabling and disabling the AST clock The Clock Source Selection field (CLOCK.CSSEL) and the Clock Enable bit (CLOCK.CEN) cannot be changed simultaneously. Special procedures must be followed for enabling and disabling the CLK_AST_PRSC and for changing the source for this clock. To enable CLK_AST_PRSC: • Write the selected value to CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero • Write a one to CLOCK.CEN, without changing CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero To disable the clock: • Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero 252 32099A–AVR32–06/09 AT32UC3L 15.5.1.2 Changing the source clock The CLK_AST_PRSC must be disabled before switching to another source clock. The Clock Busy bit in the Status Register (SR.CLKBUSY) indicates whether the clock is busy or not. This bit is set when the CEN bit in the CLOCK register is changed, and cleared when the CLOCK register can be changed. To change the clock: • Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero • Write the selected value to CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero • Write a one to CLOCK.CEN to enable the clock, without changing the CLOCK.CSSEL • Wait until SR.CLKBUSY reads as zero 15.5.2 15.5.2.1 Basic Operation Prescaler When the AST is enabled, the 32-bit prescaler will increment on the rising edge of CLK_AST_PRSC. The prescaler value cannot be read or written, but it can be reset by writing a one to the Prescaler Clear bit in the Control Register (CR.PCLR). The Prescaler Select field in the Control Register (CR.PSEL) selects the prescaler bit PSEL as source clock for the counter (CLK_AST_CNT). This results in a counter frequency of: f PRSC f CNT = ---------------------PSEL + 1 2 where fPRSC is the frequency of the internal prescaler clock CLK_AST_PRSC. 15.5.2.2 Counter operation When enabled, the AST will increment on every 0-to-1 transition of the selected prescaler tapping. When the Calender bit in the Control Register (CR.CAL) is zero, the counter operates in counter mode. It will increment until it reaches the top value of 0xFFFFFFFF, and then wrap to 0x00000000. This sets the status bit Overflow in the Status Register (SR.OVF). Optionally, the counter can also be reset when an alarm occurs (see Section 15.5.3.2 on page 255. This will also set the OVF bit. The AST counter value can be read from or written to the Counter Value (CV) register. Note that due to synchronization, continuous reading of the CV register with the lowest prescaler setting will skip every third value. In addition, if CLK_AST_PRSC is as fast as, or faster than, the CLK_AST, the prescaler value must be 3 or higher to be able to read the CV without skipping values. 253 32099A–AVR32–06/09 AT32UC3L 15.5.2.3 Calendar operation When the CAL bit in the Control Register is one, the counter operates in calendar mode. Before this mode is enabled, the prescaler should be set up to give a pulse every second. The date and time can then be read from or written to the Calendar Value (CALV) register. Time is reported as seconds, minutes, and hours according to the 24-hour clock format. Date is the numeral date of month (starting on 1). Month is the numeral month of the year (1 = January, 2 = February, etc.). Year is a 6-bit field counting the offset from a software-defined leap year (e.g. 2000). The date is automatically compensated for leap years, assuming every year divisible by 4 is a leap year. All peripheral events and interrupts work the same way in calendar mode as in counter mode. However, the Alarm Register (ARn) must be written in time/date format for the alarm to trigger correctly. 15.5.3 Interrupts The AST can generate five separate interrupt requests: • OVF: OVF • PER: PER0, PER1 • ALARM: ALARM0, ALARM1 • CLKREADY • READY This allows the user to allocate separate handlers and priorities to the different interrupt types. The generation of the PER interrupt is described in Section 15.5.3.1., and the generation of the ALARM interrupt is described in Section 15.5.3.2. The OVF interrupt is generated when the counter overflows, or when the alarm value is reached, if the Clear on Alarm bit in the Control Register is one. The CLKREADY interrupt is generated when SR.CLKBUSY has a 1-to-0 transition, and indicates that the clock synchronization is completed. The READY interrupt is generated when SR.BUSY has a 1-to-0 transition, and indicates that the synchronization described in Section 15.5.8 is completed. An interrupt request will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a one to the corresponding bit in the Status Clear Register (SCR). The AST interrupts can wake the CPU from any sleep mode where the source clock and the interrupt controller is active. 15.5.3.1 Periodic interrupt The AST can generate periodic interrupts. If the PERn bit in the Interrupt Mask Register (IMR) is one, the AST will generate an interrupt request on the 0-to-1 transition of the selected bit in the prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corresponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of where fCS is the frequency of the selected clock source. The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the the prescaler has a 0-to-1 transition. 254 32099A–AVR32–06/09 AT32UC3L f CS f PA = -----------------------INSEL + 1 2 Because of synchronization, the transfer of the INSEL value will not happen immediately. When changing/setting the INSEL value, the user must make sure that the prescaler bit number INSEL will not have a 0-to-1 transition before the INSEL value is transferred to the register. In that case, the first periodic interrupt after the change will not be triggered. 15.5.3.2 Alarm interrupt The AST can also generate alarm interrupts. If the ALARMn bit in IMR is one, the AST will generate an interrupt request when the counter value matches the selected alarm value, when the AST is enabled. The alarm value is selected by writing the value to the VALUE field in the corresponding Alarm Register (ARn.VALUE). The corresponding ALARMn bit in SR will be set when the counter reaches the selected alarm value. Because of synchronization, the transfer of the alarm value will not happen immediately. When changing/setting the alarm value, the user must make sure that the counter will not count the selected alarm value before the value is transferred to the register. In that case, the first alarm interrupt after the change will not be triggered. If the Clear on Alarm bit in the Control Register (CR.CAn) is one, the corresponding alarm interrupt will clear the counter and set the OVF bit in the Status Register. This will generate an overflow interrupt if the OVF bit in IMR is set. 15.5.4 Peripheral events The AST can generate a number of peripheral events: • OVF • PER0 • PER1 • ALARM0 • ALARM1 The PERn peripheral event(s) is generated the same way as the PER interrupt, as described in Section 15.5.3.1. The ALARMn peripheral event(s) is generated the same way as the ALARM interrupt, as described in Section 15.5.3.2. The OVF peripheral event is generated the same way as the OVF interrupt, as described in Section 15.5.3The peripheral event will be generated if the corresponding bit in the Event Mask (EVM) register is set. Bits in EVM register are set by writing a one to the corresponding bit in the Event Enable (EVE) register, and cleared by writing a one to the corresponding bit in the Event Disable (EVD) register. 255 32099A–AVR32–06/09 AT32UC3L 15.5.5 AST wakeup The AST can wake up the CPU directly, without the need to trigger an interrupt. A wakeup can be generated when the counter overflows, when the counter reaches the selected alarm value, or when the selected prescaler bit has a 0-to-1 transition. In this case, the CPU will continue executing from the instruction following the sleep instruction. The AST wakeup is enabled by writing a one to the corresponding bit in the Wake Enable Register (WER). When the CPU wakes from sleep, the wake signal must be cleared by writing a one to the corresponding bit in SCR to clear the internal wake signal to the sleep controller. If the wake signal is not cleared after waking from sleep, the next sleep instruction will have noe effect because the CPU will wake immediately after this sleep instruction. The AST wakeup can wake the CPU from any sleep mode where the source clock is active. The AST wakeup can be configured independently of the interrupt masking. 15.5.6 Shutdown Mode If the AST is configured to use a clock that is available in Shutdown mode, the AST can be used to wake up the system from shutdown. Both the alarm wakeup, periodic wakeup, and overflow wakeup mechanisms can be used in this mode. When waking up from Shutdown mode all control registers will have the same value as before the shutdown was entered, except the Interrupt Mask Register (IMR). IMR will be reset with all interrupts turned off. The software must first reconfigure the interrupt controller and then enable the interrupts in the AST to again receive interrupts from the AST. The CV register will be updated with the current counter value directly after wakeup from shutdown. The SR will show the status of the AST, including the status bits set during shutdown operation. When waking up the system from shutdown the CPU will start executing code from the reset start address. 15.5.7 Digital Tuner The digital tuner adds the possibility to compensate for a too slow or a too fast input clock. The ADD bit in the Digital Tuner Register (DTR.ADD) selects if the tuned frequency should be reduced or increased. The resulting frequency is ⎛ ⎞ ⎜ ⎟ 1 f TUNED = f 0 ⎜ 1 ± -------------------------------------------------------------------- ⎟ 1 ⎜ ⎛ -------------------⎞ ⋅ ( 2 ( EXP + 8 ) ) – 1⎟ ⎝ ⎠ ⎝ VALUE⎠ for VALUE > 0 , where f 0 is the original frequency of the prescaler. VALUE and EXP are chosen by writing the selected value to the corresponding bitfield in DTR. 15.5.8 Synchronization As the prescaler and counter operate asynchronously from the user interface, the AST needs a few clock cycles to synchronize the values written to the CR, CV, SCR, WER, EVE, EVD, PIRn, ARn, and DTR registers. The Busy bit in the Status Register (SR.BUSY) indicates that the synchronization is ongoing. During this time, writes to these registers will be discarded. 256 32099A–AVR32–06/09 AT32UC3L Note that synchronization takes place also if the prescaler is clocked from CLK_AST. 257 32099A–AVR32–06/09 AT32UC3L 15.6 User Interface AST Register Memory Map Register Control Register Counter Value Status Register Status Clear Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Wake Enable Register Alarm Register 0 Alarm Register 1 (2) (2) (2) Table 15-1. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x30 0x34 0x40 0x44 0x48 0x4C 0x50 0x54 0xF0 0xFC Note: Register Name CR CV SR SCR IER IDR IMR WER AR0 AR1 PIR0 PIR1 CLOCK DTR EVE EVD EVM CALV PARAMETER VERSION Access Read/Write Read/Write Read-only Write-only Write-only Write-only Read-only Read/write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read/Write Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) -(1) Periodic Interval Register 0 Periodic Interval Register 1(2) Clock Control Register Digital Tuner Register Event Enable Event Disable Event Mask Calendar Value Parameter Register Version Register 1. The reset values are device specific. Please refer to the Modue Configuration section at the end of this chapter. 2. The number of Alarm and Periodic Interval registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 258 32099A–AVR32–06/09 AT32UC3L 15.6.1 Name: Control Register CR Read/Write 0x00 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 27 19 26 18 PSEL 25 17 24 16 12 4 - 11 3 - 10 2 CAL 9 CA1 1 PCLR 8 CA0 0 EN • PSEL: Prescaler Select Selects prescaler bit PSEL as source clock for the counter. • CAn: Clear on Alarm n 0: The corresponding alarm will not clear the counter. 1: The corresponding alarm will clear the counter. • CAL: Calendar Mode 0: The AST operates in counter mode. 1: The AST operates in calendar mode. • PCLR: Prescaler Clear Writing a zero to this bit has no effect. Writing a one to this bit clears the prescaler. This bit always reads as zero. • EN: Enable 0: The AST is disabled. 1: The AST is enabled. 259 32099A–AVR32–06/09 AT32UC3L 15.6.2 Name: Counter Value CV Read/Write 0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 VALUE[31:24] 23 22 21 20 19 18 17 16 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] • VALUE: AST Value The current value of the AST counter. 3 2 1 0 11 10 9 8 260 32099A–AVR32–06/09 AT32UC3L 15.6.3 Name: Status Register SR Read-only 0x08 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 CLKRDY 21 13 5 - 28 CLKBUSY 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 READY 17 PER1 9 ALARM1 1 - 24 BUSY 16 PER0 8 ALARM0 0 OVF • CLKRDY: Clock Ready This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the SR.CLKBUSY bit has a 1-to-0 transition. • CLKBUSY: Clock Busy 0: The clock is ready and can be changed. 1: CLOCK.CEN has been written and the clock is busy. • READY: AST Ready This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the SR.BUSY bit has a 1-to-0 transition. • BUSY: AST Busy 0: The AST accepts writes to CR, CV, SCR, WER, EVE, EVD, ARn, PIRn, and DTR. 1: The AST is busy and will discard writes to CR, CV, SCR, WER, EVE, EVD, ARn, PIRn, and DTR. • PERn: Periodic n This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the selected bit in the prescaler has a 0-to-1 transition. • ALARMn: Alarm n This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the counter reaches the selected alarm value. • OVF: Overflow This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when an overflow has occurred. 261 32099A–AVR32–06/09 AT32UC3L 15.6.4 Name: Status Clear Register SCR Write-only 0x0C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 CLKRDY 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 READY 17 PER1 9 ALARM1 1 - 24 16 PER0 8 ALARM0 0 OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 262 32099A–AVR32–06/09 AT32UC3L 15.6.5 Name: Interrupt Enable Register IER Write-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 CLKRDY 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 READY 17 PER1 9 ALARM1 1 - 24 16 PER0 8 ALARM0 0 OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 263 32099A–AVR32–06/09 AT32UC3L 15.6.6 Name: Interrupt Disable Register IDR Write-only 0x14 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 CLKRDY 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 READY 17 PER1 9 ALARM1 1 - 24 16 PER0 8 ALARM0 0 OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 264 32099A–AVR32–06/09 AT32UC3L 15.6.7 Name: Interrupt Mask Register IMR Read-only 0x18 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 CLKRDY 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 READY 17 PER1 9 ALARM1 1 - 24 16 PER0 8 ALARM0 0 OVF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 265 32099A–AVR32–06/09 AT32UC3L 15.6.8 Name: Wake Enable Register WER Read/Write 0x1C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 PER1 9 ALARM1 1 - 24 16 PER0 8 ALARM0 0 OVF This register enables the wakeup signal from the AST. • PERn: Periodic n 0: The CPU will not wake up from sleep mode when the selected bit in the prescaler has a 0-to-1 transition. 1: The CPU will wake up from sleep mode when the selected bit in the prescaler has a 0-to-1 transition. • ALARMn: Alarm n 0: The CPU will not wake up from sleep mode when the counter reaches the selected alarm value. 1: The CPU will wake up from sleep mode when the counter reaches the selected alarm value. • OVF: Overflow 0: A counter overflow will not wake up the CPU from sleep mode. 1: A counter overflow will wake up the CPU from sleep mode. 266 32099A–AVR32–06/09 AT32UC3L 15.6.9 Name: Alarm Register 0 AR0 Read/Write 0x20 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 VALUE[31:24] 23 22 21 20 19 18 17 16 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] • VALUE: Alarm Value When the counter reaches this value, an alarm is generated. 3 2 1 0 11 10 9 8 267 32099A–AVR32–06/09 AT32UC3L 15.6.10 Name: Alarm Register 1 AR1 Read/Write 0x24 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 VALUE[31:24] 23 22 21 20 19 18 17 16 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] • VALUE: Alarm Value When the counter reaches this value, an alarm is generated. 3 2 1 0 11 10 9 8 268 32099A–AVR32–06/09 AT32UC3L 15.6.11 Name: Periodic Interval Register 0 PIR0 Read/Write 0x30 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 27 19 11 3 26 18 10 2 INSEL 25 17 9 1 24 16 8 0 • INSEL: Interval Select The PER0 bit in SR will be set when the INSEL bit in the prescaler has a 0-to-1 transition. 269 32099A–AVR32–06/09 AT32UC3L 15.6.12 Name: Periodic Interval Register 1 PIR1 Read/Write 0x34 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 27 19 11 3 26 18 10 2 INSEL 25 17 9 1 24 16 8 0 • INSEL: Interval Select The PER1 bit in SR will be set when the INSEL bit in the prescaler has a 0-to-1 transition. 270 32099A–AVR32–06/09 AT32UC3L 15.6.13 Name: Clock Control Register CLOCK Read/Write 0x40 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 25 17 9 CSSEL 24 16 8 2 - 1 - 0 CEN • CSSEL: Clock Source Selection This field defines the clock source CLK_AST_PRSC for the prescaler: Table 15-2. CSSEL 0 1 2 3 4 Clock Source Selection Clock Source System RC oscillator (RCSYS) 32KHz oscillator (OSC32K) PB clock Generic clock (GCLK) 1KHz clock from 32KHz oscillator (CLK_1K) • CEN: Clock Enable 0: CLK_AST_PRSC is disabled. 1: CLK_AST_PRSC is enabled. 271 32099A–AVR32–06/09 AT32UC3L 15.6.14 Name: Digital Tuner Register DTR Read/Write 0x44 0x00000000 Access Type: Offset: Reset Value: 31 23 15 30 22 14 29 21 13 28 20 12 VALUE 27 19 11 26 18 10 25 17 9 24 16 8 7 • ADD: 6 - 5 ADD 4 3 2 EXP 1 0 0: The resulting frequency is ⎛ ⎞ ⎜ ⎟ 1 f = f 0 ⎜ 1 – --------------------------------------------------------------- ⎟ 1⎜ ⎛ -------------------⎞ ⋅ 2 ( EXP + 8 ) – 1⎟ ⎝ ⎠ ⎝ VALUE⎠ for VALUE > 0 . 1: The resulting frequency is ⎛ ⎞ ⎜ ⎟ 1 f = f 0 ⎜ 1 + --------------------------------------------------------------- ⎟ 1⎜ ⎛ -------------------⎞ ⋅ 2 ( EXP + 8 ) – 1⎟ ⎝ ⎠ ⎝ VALUE⎠ for VALUE > 0 . 272 32099A–AVR32–06/09 AT32UC3L 15.6.15 Name: Event Enable Register EVE Write-only 0x48 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 PER1 9 ALARM1 1 - 24 16 PER0 8 ALARM0 0 OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in EVM. 273 32099A–AVR32–06/09 AT32UC3L 15.6.16 Name: Event Disable Register EVD Write-only 0x4C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 PER1 9 ALARM1 1 - 24 16 PER0 8 ALARM0 0 OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in EVM. 274 32099A–AVR32–06/09 AT32UC3L 15.6.17 Name: Event Mask Register EVM Read-only 0x50 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 PER1 9 ALARM1 1 - 24 16 PER0 8 ALARM0 0 OVF 0: The corresponding peripheral event is disabled. 1: The corresponding peripheral event is enabled. This bit is cleared when the corresponding bit in EVD is written to one. This bit is set when the corresponding bit in EVE is written to one. 275 32099A–AVR32–06/09 AT32UC3L 15.6.18 Name: Calendar Value CALV Read/Write 0x54 0x00000000 Access Type: Offset: Reset Value: 31 30 29 YEAR 28 27 26 25 MONTH[3:2] 24 23 MONTH[1:0] 15 22 21 20 19 DAY 18 17 16 HOUR[4] 14 HOUR[3:0] 13 12 11 10 MIN[5:2] 9 8 7 MIN[1:0] 6 5 4 3 SEC 2 1 0 • YEAR: Year Current year. The year is considered a leap year if YEAR[1:0] = 0. • MONTH: Month 1 = January 2 = February ... 12 = December • DAY: Day Day of month, starting with 1. • HOUR: Hour Hour of day, in 24-hour clock format. Legal values are 0 through 23. • MIN: Minute Minutes, 0 through 59. • SEC: Second Seconds, 0 through 59. 276 32099A–AVR32–06/09 AT32UC3L 15.6.19 Name: Parameter Register PARAMETER Read-only 0xF0 - Access Type: Offset: Reset Value: 31 23 15 PIR1WA 7 - 30 22 14 PIR0WA 6 29 21 13 5 28 27 26 PER1VALUE 25 24 20 19 18 PER0VALUE 17 16 12 NUMPIR 4 DTEXPVALUE 11 3 10 2 9 NUMAR 1 DTEXPWA 8 0 DT • • • • • • • This register gives the configuration used in the specific device. Also refer to the Module Configuration section. DT: Digital Tuner 0: Digital tuner not implemented. 1: Digital tuner implemented. DTREXPWA: Digital Tuner Exponent Writeable 0: Digital tuner exponent is a constant value. Writes to EXP field in DTR will be discarded. 1: Digital tuner exponent is chosen by writing to EXP field in DTR. DTREXPVALUE: Digital Tuner Exponent Value Digital tuner exponent value if DTEXPWA is zero. NUMAR: Number of Alarm Comparators 0: Zero alarm comparators. 1: One alarm comparator. 2: Two alarm comparators. NUMPIR: Number of Periodic Comparators 0: One periodic comparator. 1: Two periodic comparator. PIRnWA: Periodic Interval n Writeable 0: Periodic interval n prescaler tapping is a constant value. Writes to INSEL field in PIRn register will be discarded. 1: Periodic interval n prescaler tapping is chosen by writing to INSEL field in PIRn register. PERnVALUE: Periodic Interval n Value Periodic interval prescaler n tapping if PIRnWA is zero. 277 32099A–AVR32–06/09 AT32UC3L 15.6.20 Name: Version Register VERSION Read-only 0xFC - Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 26 18 VARIANT 25 17 24 16 11 10 9 8 VERSION[11:8] 3 VERSION[7:0] 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 278 32099A–AVR32–06/09 AT32UC3L 15.7 Module Configuration The specific configuration for each AST instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 15-3. Feature Number of alarm comparators Number of periodic comparators Digital tuner Module Configuration AST 1 1 On Table 15-4. Clock Name CLK_AST GCLK PB clock Module Clock Name Description Clock for the AST bus interface The generic clock used for the AST is GCLK2 Peripheral Bus clock from the PBA clock domain Table 15-5. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000300 0x00004103 279 32099A–AVR32–06/09 AT32UC3L 16. Watchdog Timer (WDT) Rev: 4.0.2.0 16.1 Features • • • • • Watchdog Timer counter with 32-bit counter Timing window watchdog Clocked from system RC oscillator or the 32 KHz crystal oscillator Configuration lock WDT may be enabled at reset by a fuse 16.2 Overview The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable. The WDT has an internal counter clocked from the system RC oscillator or the 32 KHz crystal oscillator. The WDT counter must be periodically cleared by software to avoid a watchdog reset. If the WDT timer is not cleared correctly, the device will reset and start executing from the boot vector. 16.3 Block Diagram Figure 16-1. WDT Block Diagram PB Clock Domain PB CLR SR CTRL WDTCLR WINDOW, CLEARED EN, MODE, PSEL, TBAN SYNC RCSYS 0 CLK_CNT OSC32K 1 32-bit Counter CLK_CNT Domain Watchdog Detector Watchdog Reset CEN CSSEL 16.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 280 32099A–AVR32–06/09 AT32UC3L 16.4.1 Power Management When the WDT is enabled, the WDT remains clocked in all sleep modes. It is not possible to enter sleep modes where the source clock of CLK_CNT is stopped. Attempting to do so will result in the chip entering the lowest sleep mode where the source clock is running, leaving the WDT operational. Please refer to the Power Manager chapter for details about sleep modes. After a watchdog reset the WDT bit in the Reset Cause Register (RCAUSE) in the Power Manager will be set. 16.4.2 Clocks The clock for the WDT bus interface (CLK_WDT) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the WDT before disabling the clock, to avoid freezing the WDT in an undefined state. There are two possible clock sources for the Watchdog Timer (CLK_CNT): • System RC oscillator (RCSYS): This oscillator is always enabled when selected as clock source for the WDT. Please refer to the Power Manager chapter for details about the RCSYS and sleep modes. Please refer to the Electrical Characteristics chapter for the characteristic frequency of this oscillator. • 32 KHz crystal oscillator (OSC32K): This oscillator has to be enabled in the System Control Interface before using it as clock source for the WDT. The WDT will not be able to detect if this clock is stopped. 16.4.3 Debug Operation The WDT counter is frozen during debug operation, unless the Run In Debug bit in the Development Control Register is set and the bit corresponding to the WDT is set in the Peripheral Debug Register. Please refer to the On-Chip Debug chapter in the AVR32UC Technical Reference Manual for details. If the WDT counter is not frozen during debug operation it will need periodically clearing to avoid a watchdog reset. Fuses The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse, see Section 16.5.4 for details. Please refer to the Fuse Settings section in the Flash Controller chapter for details about WDTAUTO and how to program the fuses. 16.4.4 16.5 16.5.1 Functional Description Basic Mode WDT Control Register Access To avoid accidental disabling of the watchdog, the Control Register (CTRL) must be written twice, first with the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to do so will cause the write operation to be ignored, and the value in the CTRL Register will not be changed. Changing CLK_CNT Clock Source After any reset, except for watchdog reset, CLK_CNT will be enabled with the RCSYS as source. 16.5.1.1 16.5.1.2 281 32099A–AVR32–06/09 AT32UC3L To change the clock for the WDT the following steps need to be taken. Note that the WDT should always be disabled before changing the CLK_CNT source: 1. Write a zero to the Clock Enable (CEN) bit in the CTRL Register, leaving the other bits as they are in the CTRL Register. This will stop CLK_CNT. 2. Read back the CTRL Register until the CEN bit reads zero. The clock has now been stopped. 3. Modify the Clock Source Select (CSSEL) bit in the CTRL Register with your new clock selection and write it to the CTRL Register. 4. Write a one to the CEN bit, leaving the other bits as they are in the CTRL Register. This will enable the clock. 5. Read back the CTRL Register until the CEN bit reads one. The clock has now been enabled. 16.5.1.3 Configuring the WDT If the MODE bit in the CTRL Register is zero, the WDT is in basic mode. The Time Out Prescale Select (PSEL) field in the CTRL Register selects the WDT timeout period: Ttimeout = Tpsel = 2(PSEL+1) / fclk_cnt 16.5.1.4 Enabling the WDT To enable the WDT write a one to the Enable (EN) bit in the CTRL Register. Due to internal synchronization, it will take some time for the CTRL.EN bit to read back as one. Clearing the WDT Counter The WDT counter is cleared by writing a one to the Watchdog Clear (WDTCLR) bit in the Clear (CLR) Register, at any correct write to the CTRL Register, or when the counter reaches Ttimeout and the chip is reset. In basic mode the CLR.WDTCLR can be written at any time when the WDT Counter Cleared (CLEARED) bit in the Status Register (SR) is one. Due to internal synchronization, clearing the WDT counter takes some time. The SR.CLEARED bit is cleared when writing to CLR.WDTCLR bit and set when the clearing is done. Any write to the CLR.WDTCLR bit while SR.CLEARED is zero will be ignored. Writing to the CLR.WDTCLR bit has to be done in a particular sequence to be valid. The CLR Register must be written twice, first with the KEY field set to 0x55 and WDTCLR set to one, then a second write with the KEY set to 0xAA without changing the WDTCLR bit. Writing to the CLR Register without the correct sequence has no effect. If the WDT counter is periodically cleared within Tpsel no watchdog reset will be issued, see Figure 16-2 on page 283. 16.5.1.5 282 32099A–AVR32–06/09 AT32UC3L Figure 16-2. Basic Mode WDT Timing Diagram, normal operation. t=t0 T psel Timeout Write one to CLR.WDTCLR Watchdog reset If the WDT counter is not cleared within Tpsel a watchdog reset will be issued at the end of Tpsel, see Figure 16-3 on page 283. Figure 16-3. Basic Mode WDT Timing Diagram, no clear within Tpsel. t=t0 T psel Timeout Write one to CLR.WDTCLR Watchdog reset 16.5.1.6 Watchdog Reset A watchdog reset will result in a reset and the code will start executing from the boot vector, please refer to the Power Manager chapter for details. If the Disable After Reset (DAR) bit in the CTRL Register is zero, the WDT counter will restart counting from zero when the watchdog reset is released. If the CTRL.DAR bit is one the WDT will be disabled after a watchdog reset. Only the CTRL.EN bit will be changed after the watchdog reset. However, if WDTAUTO fuse is configured to enable the WDT after a watchdog reset, and the CTRL.FCD bit is zero, writing a one to the CTRL.DAR bit will have no effect. 283 32099A–AVR32–06/09 AT32UC3L 16.5.2 Window Mode The window mode can protect against tight loops of runaway code. This is obtained by adding a ban period to timeout period. During the ban period clearing the WDT counter is not allowed. If the WDT Mode (MODE) bit in the CTRL Register is one, the WDT is in window mode. Note that the CTRL.MODE bit can only be changed when the WDT is disabled (CTRL.EN=0). The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT timeout period Ttimeout = Ttban + Tpsel = (2(TBAN+1) + 2(PSEL+1)) / fclk_cnt where Ttban sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the code will start executing form the boot vector, see Figure 16-5 on page 285. The WDT counter will be cleared. Writing a one to the CLR.WDTCLR bit within the Tpsel period will clear the WDT counter and the counter starts counting from zero (t=t0), entering Ttban, see Figure 16-4 on page 284. If the value in the CTRL Register is changed, the WDT counter will be cleared without a watchdog reset, regardless of if the value in the WDT counter and the TBAN value. If the WDT counter reaches Ttimeout, the counter will be cleared, the device will receive a reset and the code will start executing form the boot vector. Figure 16-4. Window Mode WDT Timing Diagram t=t0 T tban T psel Timeout Write one to CLR.WDTCLR Watchdog reset 284 32099A–AVR32–06/09 AT32UC3L Figure 16-5. Window Mode WDT Timing Diagram, clearing within Ttban, resulting in watchdog reset. t=t0 T tban T psel Timeout Write one to CLR.WDTCLR Watchdog reset 16.5.3 Disabling the WDT The WDT is disabled by writing a zero to the CTRL.EN bit. When disabling the WDT no other bits in the CTRL Register should be changed until the CTRL.EN bit reads back as zero. If the CTRL.CEN bit is written to zero, the CTRL.EN bit will never read back as zero if changing the value from one to zero. Flash Calibration The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse. The WDT will be set in basic mode, RCSYS is set as source for CLK_CNT, and PSEL will be set to a value giving Tpsel above 100 ms. Please refer to the Fuse Settings chapter for details about WDTAUTO and how to program the fuses. If the Flash Calibration Done (FCD) bit in the CTRL Register is zero at a watchdog reset the flash calibration will be redone, and the CTRL.FCD bit will be set when the calibration is done. If CTRL.FCD is one at a watchdog reset, the configuration of the WDT will not be changed during flash calibration. After any other reset the flash calibration will always be done, and the CTRL.FCD bit will be set when the calibration is done. 16.5.5 Special Considerations Care must be taken when selecting the PSEL/TBAN values so that the timeout period is greater than the startup time of the chip. Otherwise a watchdog reset will reset the chip before any code has been run. This can also be avoided by writing the CTRL.DAR bit to one when configuring the WDT. If the Store Final Value (SFV) bit in the CTRL Register is one, the CTRL Register is locked for further write accesses. All writes to the CTRL Register will be ignored. Once the CTRL Register is locked, it can only be unlocked by a reset (e.g. POR, OCD, and WDT). The CTRL.MODE bit can only be changed when the WDT is disabled (CTRL.EN=0). 16.5.4 285 32099A–AVR32–06/09 AT32UC3L 16.6 User Interface WDT Register Memory Map Register Control Register Clear Register Status Register Version Register Register Name CTRL CLR SR VERSION Access Read/Write Write-only Read-only Read-only Reset 0x00010080 0x00000000 0x00000003 -(1) Table 16-1. Offset 0x000 0x004 0x008 0x3FC Note: 1. The reset value for this register is device specific. Please refer to the Module Configuration section at the end of this chapter. 286 32099A–AVR32–06/09 AT32UC3L 16.6.1 Name: Control Register CTRL Read/Write 0x000 0x00010080 Access Type: Offset: Reset Value: 31 30 29 28 KEY 27 26 25 24 23 - 22 21 20 TBAN 19 18 17 CSSEL 16 CEN 15 - 14 - 13 - 12 11 10 PSEL 9 8 7 FCD • KEY 6 - 5 - 4 - 3 SFV 2 MODE 1 DAR 0 EN • • • • • • • This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads as zero. TBAN: Time Ban Prescale Select Counter bit TBAN is used as watchdog “banned” time frame. In this time frame clearing the WDT timer is forbidden, otherwise a watchdog reset is generated and the WDT timer is cleared. CSSEL: Clock Source Select 0: Select the system RC oscillator (RCSYS) as clock source. 1: Select the 32KHz crystal oscillator (OSC32K) as clock source. CEN: Clock Enable 0: The WDT clock is disabled. 1: The WDT clock is enabled. PSEL: Time Out Prescale Select Counter bit PSEL is used as watchdog timeout period. FCD: Flash Calibration Done This bit is set after any reset. 0: The flash calibration will be redone after a watchdog reset. 1: The flash calibration will not be redone after a watchdog reset. SFV: WDT Control Register Store Final Value 0: WDT Control Register is not locked. 1: WDT Control Register is locked. Once locked, the Control Register can not be re-written, only a reset unlocks the SFV bit. MODE: WDT Mode 0: The WDT is in basic mode, only PSEL time is used. 1: The WDT is in window mode. Total timeout period is now TBAN+PSEL. Writing to this bit when the WDT is enabled has no effect. 287 32099A–AVR32–06/09 AT32UC3L • DAR: WDT Disable After Reset 0: After a watchdog reset, the WDT will still be enabled. 1: After a watchdog reset, the WDT will be disabled. • EN: WDT Enable 0: WDT is disabled. 1: WDT is enabled. After writing to this bit the read back value will not change until the WDT is enabled/disabled. This due to internal synchronization. 288 32099A–AVR32–06/09 AT32UC3L 16.6.2 Name: Clear Register CLR Write-only 0x004 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 KEY 27 26 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 WDTCLR When the Watchdog Timer is enabled, this Register must be periodically written within the window time frame or within the watchdog timeout period, to prevent a watchdog reset. • KEY This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. • WDTCLR: Watchdog Clear Writing a zero to this bit has no effect. Writing a one to this bit clears the WDT counter. 289 32099A–AVR32–06/09 AT32UC3L 16.6.3 Name: Status Register SR Read-only 0x008 0x00000003 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 CLEARED 0 WINDOW • CLEARED: WDT Counter Cleared This bit is cleared when writing a one to the CLR.WDTCLR bit. This bit is set when clearing the WDT counter is done. • WINDOW: Within Window This bit is cleared when the WDT counter is inside the TBAN period. This bit is set when the WDT counter is inside the PSEL period. 290 32099A–AVR32–06/09 AT32UC3L 16.6.4 Name: Version Register VERSION Read-only 0x3FC - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 291 32099A–AVR32–06/09 AT32UC3L 16.7 Module Configuration The specific configuration for each WDT instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 16-2. Module name MODULE Module clock name Clock name CLK_WDT Table 16-3. Register VERSION Register Reset Values Reset Value 0x00000402 292 32099A–AVR32–06/09 AT32UC3L 17. External Interrupt Controller (EIC) Rev: 3.0.1.0 17.1 Features • • • • • • • Dedicated interrupt request for each interrupt Individually maskable interrupts Interrupt on rising or falling edge Interrupt on high or low level Asynchronous interrupts for sleep modes without clock Filtering of interrupt lines Maskable NMI interrupt 17.2 Overview The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each external interrupt has its own interrupt request and can be individually masked. Each external interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can also be configured to be asynchronous in order to wake up the part from sleep modes where the CLK_SYNC clock has been disabled. A Non-Maskable Interrupt (NMI) is also supported. This has the same properties as the other external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any other interrupt mode. The EIC can wake up the part from sleep modes without triggering an interrupt. In this mode, code execution starts from the instruction following the sleep instruction. 293 32099A–AVR32–06/09 AT32UC3L 17.3 Block Diagram Figure 17-1. EIC Block Diagram LEVEL MODE EDGE ASYNC EN DIS Polarity control Asynchronus detector LEVEL MODE EDGE ICR CTRL IER IDR Enable EXTINTn NMI CTRL FILTER INTn Mask IRQn Filter Edge/Level Detector ISR IMR CLK_SYNC Wake detect EIC_WAKE 17.4 I/O Lines Description Table 17-1. Pin Name NMI EXTINTn I/O Lines Description Pin Description Non-Maskable Interrupt External Interrupt Type Input Input 17.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 17.5.1 I/O Lines The external interrupt pins (EXTINTn and NMI) may be multiplexed with I/O Controller lines. The programmer must first program the I/O Controller to assign the desired EIC pins to their peripheral function. If I/O lines of the EIC are not used by the application, they can be used for other purposes by the I/O Controller. It is only required to enable the EIC inputs actually in use. If an application requires two external interrupts, then only two I/O lines will be assigned to EIC inputs. 294 32099A–AVR32–06/09 AT32UC3L 17.5.2 Power Management All interrupts are available in all sleep modes as long as the EIC module is powered. However, in sleep modes where CLK_SYNC is stopped, the interrupt must be configured to asynchronous mode. Clocks The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. The filter and synchronous edge/level detector runs on a clock which is stopped in any of the sleep modes where the system RC oscillator (RCSYS) is not running. This clock is referred to as CLK_SYNC. 17.5.4 Interrupts The external interrupt request lines are connected to the interrupt controller. Using the external interrupts requires the interrupt controller to be programmed first. Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed. 17.5.5 Debug Operation When an external debugger forces the CPU into debug mode, the EIC continues normal operation. If the EIC is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 17.5.3 17.6 17.6.1 Functional Description External Interrupts The external interrupts are not enabled by default, allowing the proper interrupt vectors to be set up by the CPU before the interrupts are enabled. Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL registers. Each interrupt has a bit INTn in each of these registers. Writing a zero to the INTn bit in the MODE register enables edge triggered interrupts, while writing a one to the bit enables level triggered interrupts. If INTn is configured as an edge triggered interrupt, writing a zero to the INTn bit in the EDGE register will cause the interrupt to be triggered on a falling edge on EXTINTn, while writing a one to the bit will cause the interrupt to be triggered on a rising edge on EXTINTn. If INTn is configured as a level triggered interrupt, writing a zero to the INTn bit in the LEVEL register will cause the interrupt to be triggered on a low level on EXTINTn, while writing a one to the bit will cause the interrupt to be triggered on a high level on EXTINTn. Each interrupt has a corresponding bit in each of the interrupt control and status registers. Writing a one to the INTn bit in the Interrupt Enable Register (IER) enables the external interrupt from pin EXTINTn to propagate from the EIC to the interrupt controller, while writing a one to INTn bit in the Interrupt Disable Register (IDR) disables this propagation. The Interrupt Mask Register (IMR) can be read to check which interrupts are enabled. When an interrupt triggers, the corresponding bit in the Interrupt Status Register (ISR) will be set. This bit remains set until a one is written to the corresponding bit in the Interrupt Clear Register (ICR) or the interrupt is disabled. 295 32099A–AVR32–06/09 AT32UC3L Writing a one to the INTn bit in the Enable Register (EN) enables the external interrupt on pin EXTINTn, while writing a one to INTn bit in the Disable Register (DIS) disables the external interrupt. The Control Register (CTRL) can be read to check which interrupts are enabled. If a bit in the CTRL register is set, but the corresponding bit in IMR is not set, an interrupt will not propagate to the interrupt controller. However, the corresponding bit in ISR will be set, and EIC_WAKE will be set. Note that an external interrupt should not be enabled before it has been configured correctly. If the CTRL.INTn bit is zero, the corresponding bit in ISR will always be zero. Disabling an external interrupt by writing a one to the DIS.INTn bit will clear the corresponding bit in ISR. Please refer to the Module Configuration section for the number of external interrupts. 17.6.2 Synchronization and Filtering of External Interrupts In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_SYNC, so spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The synchronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the interrupt controller by two cycles of CLK_SYNC, see Figure 17-2 and Figure 17-3 for examples (FILTER off). It is also possible to apply a filter on EXTINTn by writing a one to the INTn bit in the FILTER register. This filter is a majority voter, if the condition for an interrupt is true for more than one of the latest three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propagation of the interrupt to the interrupt controller by one or two cycles of CLK_SYNC, see Figure 17-2 and Figure 17-3 for examples (FILTER on). Figure 17-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on 296 32099A–AVR32–06/09 AT32UC3L Figure 17-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on 17.6.3 Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in Section 17.6.1 should be followed, accessing the NMI bit instead of the INTn bits. The NMI is non-maskable within the CPU in the sense that it can interrupt any other execution mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled by accessing the registers in the EIC. 17.6.4 Asynchronous Interrupts Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC register. This will route the interrupt signal through the asynchronous path of the module. All edge interrupts will be interpreted as level interrupts and the filter is disabled. If an interrupt is configured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted as low level, and a one in EDGE.INTn will be interpreted as high level. EIC_WAKE will be set immediately after the source triggers the interrupt, while the corresponding bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of CLK_SYNC. Please refer to Figure 17-4 on page 298 for details. When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be updated on the first rising edge of CLK_SYNC. 297 32099A–AVR32–06/09 AT32UC3L Figure 17-4. Timing Diagram, Asynchronous Interrupts CLK_SYNC CLK_SYNC EXTINTn/NM I EXTINTn/NMI ISR.INTn: rising EDGE or high LEVEL EIC_W AKE: rising EDGE or high LEVEL ISR.INTn: rising EDGE or high LEVEL EIC_W AKE: rising EDGE or high LEVEL 17.6.5 Wakeup The external interrupts can be used to wake up the part from sleep modes. The wakeup can be interpreted in two ways. If the corresponding bit in IMR is one, then the execution starts at the interrupt handler for this interrupt. If the bit in IMR is zero, then the execution starts from the next instruction after the sleep instruction. 298 32099A–AVR32–06/09 AT32UC3L 17.7 User Interface EIC Register Memory Map Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Mode Register Edge Register Level Register Filter Register Test Register Asynchronous Register Enable Register Disable Register Control Register Version Register Register Name IER IDR IMR ISR ICR MODE EDGE LEVEL FILTER TEST ASYNC EN DIS CTRL VERSION Access Write-only Write-only Read-only Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Write-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 - (1) Table 17-2. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x030 0x034 0x038 0x3CF Note: 1. The reset value is device specific. Please refer to the Module Configuration section at the end of this chapter. 299 32099A–AVR32–06/09 AT32UC3L 17.7.1 Name: Interrupt Enable Register IER Write-only 0x000 0x00000000 Access Type: Offset: Reset Value: 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will set the corresponding bit in IMR. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt rWriting a zero to this bit has no effect. iWrting a one to this bit will set the corresponding bit in IMR. 300 32099A–AVR32–06/09 AT32UC3L 17.7.2 Name: Interrupt Disable Register IDR Write-only 0x004 0x00000000 Access Type: Offset: Reset Value: 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in IMR. 301 32099A–AVR32–06/09 AT32UC3L 17.7.3 Name: Interrupt Mask Register IMR Read-only 0x008 0x00000000 Access Type: Offset: Reset Value: 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is disabled. 1: The Non-Maskable Interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 302 32099A–AVR32–06/09 AT32UC3L 17.7.4 Name: Interrupt Status Register ISR Read-only 0x00C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n 0: An interrupt event has not occurred. 1: An interrupt event has occurred. This bit is cleared by writing a one to the corresponding bit in ICR. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt 0: An interrupt event has not occurred. 1: An interrupt event has occurred. This bit is cleared by writing a one to the corresponding bit in ICR. 303 32099A–AVR32–06/09 AT32UC3L 17.7.5 Name: Interrupt Clear Register ICR Write-only 0x010 0x00000000 Access Type: Offset: Reset Value: 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in ISR. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will clear the corresponding bit in ISR. 304 32099A–AVR32–06/09 AT32UC3L 17.7.6 Name: Mode Register MODE Read/Write 0x014 0x00000000 Access Type: Offset: Reset Value: 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n 0: The external interrupt is edge triggered. 1: The external interrupt is level triggered. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is edge triggered. 1: The Non-Maskable Interrupt is level triggered. 305 32099A–AVR32–06/09 AT32UC3L 17.7.7 Name: Edge Register EDGE Read/Write 0x018 0x00000000 Access Type: Offset: Reset Value: 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n 0: The external interrupt triggers on falling edge. 1: The external interrupt triggers on rising edge. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt triggers on falling edge. 1: The Non-Maskable Interrupt triggers on rising edge. 306 32099A–AVR32–06/09 AT32UC3L 17.7.8 Name: Level Register LEVEL Read/Write 0x01C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n 0: The external interrupt triggers on low level. 1: The external interrupt triggers on high level. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt triggers on low level. 1: The Non-Maskable Interrupt triggers on high level. 307 32099A–AVR32–06/09 AT32UC3L 17.7.9 Name: Access Type: Offset: Reset Value: Filter Register FILTER Read/Write 0x020 0x00000000 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n 0: The external interrupt is not filtered. 1: The external interrupt is filtered. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is not filtered. 1: The Non-Maskable Interrupt is filtered. 308 32099A–AVR32–06/09 AT32UC3L 17.7.10 Name: Access Type: Offset: Reset Value: Test Register TEST Read/Write 0x024 0x00000000 31 TESTEN 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • TESTEN: Test Enable 0: This bit disables external interrupt test mode. 1: This bit enables external interrupt test mode. • INTn: External Interrupt n Writing a zero to this bit will set the input value to INTn to zero, if test mode is enabled. Writing a one to this bit will set the input value to INTn to one, if test mode is enabled. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt Writing a zero to this bit will set the input value to NMI to zero, if test mode is enabled. Writing a one to this bit will set the input value to NMI to one, if test mode is enabled. If TESTEN is 1, the value written to this bit will be the value to the interrupt detector and the value on the pad will be ignored. 309 32099A–AVR32–06/09 AT32UC3L 17.7.11 Name: Access Type: Offset: Reset Value: Asynchronous Register ASYNC Read/Write 0x028 0x00000000 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n 0: The external interrupt is synchronized to CLK_SYNC. 1: The external interrupt is asynchronous. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is synchronized to CLK_SYNC. 1: The Non-Maskable Interrupt is asynchronous. 310 32099A–AVR32–06/09 AT32UC3L 17.7.12 Name: Access Type: Offset: Reset Value: Enable Register EN Write-only 0x030 0x00000000 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will enable the corresponding external interrupt. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will enable the Non-Maskable Interrupt. 311 32099A–AVR32–06/09 AT32UC3L 17.7.13 Name: Access Type: Offset: Reset Value: Disable Register DIS Write-only 0x034 0x00000000 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n Writing a zero to this bit has no effect. Writing a one to this bit will disable the corresponding external interrupt. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt Writing a zero to this bit has no effect. Writing a one to this bit will disable the Non-Maskable Interrupt. 312 32099A–AVR32–06/09 AT32UC3L 17.7.14 Name: Access Type: Offset: Reset Value: Control Register CTRL Read-only 0x038 0x00000000 31 - 30 INT30 29 INT29 28 INT28 27 INT27 26 INT26 25 INT25 24 INT24 23 INT23 22 INT22 21 INT21 20 INT20 19 INT19 18 INT18 17 INT17 16 INT16 15 INT15 14 INT14 13 INT13 12 INT12 11 INT11 10 INT10 9 INT9 8 INT8 7 INT7 6 INT6 5 INT5 4 INT4 3 INT3 2 INT2 1 INT1 0 NMI • INTn: External Interrupt n 0: The corresponding external interrupt is disabled. 1: The corresponding external interrupt is enabled. Please refer to the Module Configuration section for the number of external interrupts. • NMI: Non-Maskable Interrupt 0: The Non-Maskable Interrupt is disabled. 1: The Non-Maskable Interrupt is enabled. 313 32099A–AVR32–06/09 AT32UC3L 17.7.15 Name: Version Register VERSION Read-only 0x3FC - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VERSION: Version number Version number of the module. No functionality associated. 314 32099A–AVR32–06/09 AT32UC3L 17.8 Module Configuration The specific configuration for each EIC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 17-3. Feature Number of external interrupts, including NMI Module Configuration EIC 6 Table 17-4. Module Name EIC Module Clock Name Clock Name CLK_EIC Table 17-5. Register VERSION Register Reset Values Reset Value 0x00000301 315 32099A–AVR32–06/09 AT32UC3L 18. Frequency Meter (FREQM) Rev: 3.0.1.0 18.1 Features • • • • Accurately measures a clock frequency Selectable reference clock A selectable clock can be measured Ratio can be measured with 24-bit accuracy 18.2 Overview The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 18.3 Block Diagram Figure 18-1. Frequency Meter Block Diagram CLKSEL START CLK_MSR Counter VALUE CLK_REF Timer REFNUM, START Trigger ISR REFSEL 18.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 18.4.1 Power Management The device can enter a sleep mode while a measurement is ongoing. However, make sure that neither CLK_MSR nor CLK_REF is stopped in the actual sleep mode. FREQM interrupts can wake up the device from sleep modes when the measurement is done, but only from sleep modes where CLK_FREQM is running. Please refer to the Power Manager chapter for details. 316 32099A–AVR32–06/09 AT32UC3L 18.4.2 Clocks The clock for the FREQM bus interface (CLK_FREQM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the FREQM before disabling the clock, to avoid freezing the FREQM ia an undefined state. A set of clocks can be selected as reference (CLK_REF) and another set of clocks can be selected for measurement (CLK_MSR). Please refer to the CLKSEL and REFSEL tables in the Module Configuration chapter for details. 18.4.3 Debug Operation When an external debugger forces the CPU into debug mode, the FREQM continues normal operation. If the FREQM is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. Interrupts The FREQM interrupt request line is connected to the internal source of the interrupt controller. Using the FREQM interrupt requires the interrupt controller to be programmed first. 18.4.4 18.5 Functional Description The FREQM accuratly measures the frequency of a clock by comparing the frequency to a known frequency: fCLK_MSR = (VALUE/REFNUM)*fCLK_REF 18.5.1 Reference Clock The Reference Clock Selection (REFSEL) field in the Mode Register (MODE) selects the clock source for CLK_REF. The reference clock is enabled by writing a one to the Reference Clock Enable (REFCEN) bit in the Mode Register. This clock should have a known frequency. CLK_REF needs to be disabled before switching to another clock. The RCLKBUSY bit in the Status Register (SR) indicates whether the clock is busy or not. This bit is set when the MODE.REFCEN bit is written. To change CLK_REF: • Write a zero to the MODE.REFCEN bit to disable the clock, without changing the other bits/fields in the Mode Register. • Wait until the SR.RCLKBUSY bit reads as zero. • Change the MODE.REFSEL field. • Write a one to the MODE.REFCEN bit to enable the clock, without changing the other bits/fields in the Mode Register. • Wait until the SR.RCLKBUSY bit reads as zero. To enable CLK_REF: • Write the correct value to the MODE.REFSEL field. • Write a one to the MODE.REFCEN to enable the clock, without changing the other bits/fields in the Mode Register. • Wait until the SR.RCLKBUSY bit reads as zero. To disable CLK_REF: 317 32099A–AVR32–06/09 AT32UC3L • Write a zero to the MODE.REFCEN to disable he clock, without changing the other bits/fields in the Mode register. • Wait until the SR.RCLKBUSY bit reads as zero. 18.5.2 Measurement In the Mode Register the Clock Source Selection (CLKSEL) field selects CLK_MSR and the Number of Reference Clock Cycles (REFNUM) field selects the duration of the measurement. The duration is given in number of CLK_REF periodes. Writing a one to the START bit in the Control Register (CTRL) starts the measurement. The BUSY bit in SR is cleared when the measurement is done. The result of the measurement can be read from the Value Register (VALUE). The frequency of the measured clock CLK_MSR is then: fCLK_MSR = (VALUE/REFNUM)*fCLK_REF 18.5.3 Interrupts The FREQM has two interrupt sources: • DONE: A frequency measurement is done • RCLKRDY: The reference clock is ready These will generate an interrupt request if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER) and cleared by writing a one to this bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in the Interrupt Status Register (ISR) is cleared by writing a one to this bit in the Interrupt Clear Register (ICR). 318 32099A–AVR32–06/09 AT32UC3L 18.6 User Interface FREQM Register Memory Map Register Control Register Mode Register Status Register Value Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Version Register Register Name CTRL MODE STATUS VALUE IER IDR IMR ISR ICR VERSION Access Write-only Read/Write Read-only Read-only Write-only Write-only Read-only Read-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) Table 18-1. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x3FC Note: 1. The reset value for this register is device specific. Please refer to the Module Configuration section at the end of this chapter. 319 32099A–AVR32–06/09 AT32UC3L 18.6.1 Name: Control Register CTRL Write-only 0x000 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 START • START Writing a zero to this bit has no effect. Writing a one to this bit will start a measurement. 320 32099A–AVR32–06/09 AT32UC3L 18.6.2 Name: Mode Register MODE Read/Write 0x004 0x00000000 Access Type: Offset: Reset Value: 31 REFCEN 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 19 18 CLKSEL 17 16 15 14 13 12 REFNUM 11 10 9 8 7 - 6 - 5 - 4 - 3 - 2 1 REFSEL 0 • REFCEN: Reference Clock Enable 0: The reference clock is disabled 1: The reference clock is enabled • CLKSEL: Clock Source Selection Selects the source for CLK_MSR. See table in Module Configuration chapter for details. • REFNUM: Number of Reference Clock Cycles Setects the duration of a measurement, given in number of CLK_REF cycles. • REFSEL: Reference Clock Selection Selects the source for CLK_REF. See table in Module Configuration chapter for details. 321 32099A–AVR32–06/09 AT32UC3L 18.6.3 Name: Access Type: Offset: Reset Value: Status Register STATUS Read-only 0x008 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 RCLKBUSY 0 BUSY • RCLKBUSY: FREQM Reference Clock Status 0: The FREQM ref clk is ready, so a measurement can start. 1: The FREQM ref clk is not ready, so a measurement should not be started. • BUSY: FREQM Status 0: The Frequency Meter is idle. 1: Frequency measurement is on-going. 322 32099A–AVR32–06/09 AT32UC3L 18.6.4 Name: Access Type: Offset: Reset Value: Value Register VALUE Read-only 0x00C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 22 21 20 19 18 17 16 VALUE[23:16] 15 14 13 12 VALUE[15:8] 11 10 9 8 7 6 5 4 VALUE[7:0] 3 2 1 0 • VALUE: Result from measurement. 323 32099A–AVR32–06/09 AT32UC3L 18.6.5 Name: Access Type: Offset: Reset Value: Interrupt Enable Register IER Write-only 0x010 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 RCLKRDY 0 DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 324 32099A–AVR32–06/09 AT32UC3L 18.6.6 Name: Access Type: Offset: Reset Value: Interrupt Disable Register IDR Write-only 0x014 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 RCLKRDY 0 DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 325 32099A–AVR32–06/09 AT32UC3L 18.6.7 Name: Access Type: Offset: Reset Value: Interrupt Mask Register IMR Read-only 0x018 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 RCLKRDY 0 DONE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 326 32099A–AVR32–06/09 AT32UC3L 18.6.8 Name: Access Type: Offset: Reset Value: Interrupt Status Register ISR Read-only 0x01C 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 RCLKRDY 0 DONE 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending. A bit in this register is set when the corresponding bit in STATUS has a one to zero transition. A bit in this register is cleared when the corresponding bit in ICR is written to one. 327 32099A–AVR32–06/09 AT32UC3L 18.6.9 Name: Access Type: Offset: Reset Value: Interrupt Clear Register ICR Write-only 0x020 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 RCLKRDY 0 DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. 328 32099A–AVR32–06/09 AT32UC3L 18.6.10 Name: Version Register VERSION Read-only 0x3FC - Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 329 32099A–AVR32–06/09 AT32UC3L 18.7 Module Configuration The specific configuration for each FREQM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 18-2. Module Name Module Clock Name Clock Name CLK_FREQM Description Bus interface clock Measured clock Reference clock FREQM CLK_MSR CLK_REF Table 18-3. Register VERSION Register Reset Values Reset Value 0x00000301 Table 18-4. CLKSEL 0 1 2 3 4 5 6 7 8 9-14 15 16 17 18-31 Clock Sources for CLK_MSR Clock/Oscillator CLK_CPU CLK_HSB CLK_PBA CLK_PBB OSC0 OSC32K RCSYS DFLL0 Reserved GCLK0-5 RC120M AW clock RC120M RC32K Reserved Generic clock 0 through 5 Output clock from RC120M to AW Output clock from RC120M to main clock mux Output clock from RC32K Description The clock the CPU runs on High Speed Bus clock Peripheral Bus A clock Peripheral Bus B clock Output clock from Oscillator 0 Output clock from OSC32K Output clock from RCSYS Oscillator Output clock from DFLL0 Table 18-5. REFSEL 0 1 2-7 Clock Sources for CLK_REF Clock/Oscillator RCSYS OSC32K Reserved Description System RC oscillator clock Output clock form OSC32K 330 32099A–AVR32–06/09 AT32UC3L 19. General-Purpose Input/Output Controller (GPIO) Version: 2.1.1.4 19.1 Features • Each GPIO line features: – – – – – – – – – – – – – Configurable pin-change, rising-edge, or falling-edge interrupt Configurable peripheral event generator Glitch filter providing rejection of pulses shorter than one clock cycle Open Drain mode allowing an I/O pin to be shared between the MCU and external components Input visibility and output control Multiplexing of peripheral functions on I/O pins Programmable internal pull-up resistor Programmable internal pull-down resistor Programmable internal buskeeper Programmable output driver strength Programmable internal input Schmitt trigger Programmable output slew rate Optional locking of configuration to avoid accidental reconfiguration 19.2 Overview The General Purpose Input/Output Controller (GPIO) controls the I/O pins of the microcontroller. Each GPIO pin may be used as a general-purpose I/O or be assigned to a function of an embedded peripheral. The GPIO is configured using the Peripheral Bus (PB). Some registers can also be configured using the low latency CPU Local Bus. See Section 19.6.2.10 for details. 331 32099A–AVR32–06/09 AT32UC3L 19.3 Block Diagram Figure 19-1. GPIO Block Diagram Configuration Interface Interrupt Controller GPIO Interrupt Request PIN General Purpose Input/Output - GPIO PIN PIN PIN PIN MCU I/O Pins Power Manager CLK_GPIO Embedded Peripheral Pin Control Signals 19.4 IO Lines Description Description GPIO pin n Type Digital Pin Name GPIOn 332 32099A–AVR32–06/09 AT32UC3L 19.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 19.5.1 Power Management If the CPU enters a sleep mode that disables clocks used by the GPIO, the GPIO will stop functioning and resume operation after the system wakes up from sleep mode. If a peripheral function is configured for a GPIO pin, the peripheral will be able to control the GPIO pin even if the GPIO clock is stopped. 19.5.2 Clocks The GPIO is connected to a Peripheral Bus clock (CLK_GPIO). This clock is generated by the Power Manager. CLK_GPIO is enabled at reset, and can be disabled by writing to the Power Manager. CLK_GPIO must be enabled in order to access the configuration registers of the GPIO or to use the GPIO interrupts. After configuring the GPIO, the CLK_GPIO can be disabled by writing to the Power Manager if interrupts are not used. If the CPU Local Bus is used to access the configuration interface of the GPIO, the CLK_GPIO must be equal to the CPU clock to avoid data loss. 19.5.3 Interrupts The GPIO interrupt request lines are connected to the interrupt controller. Using the GPIO interrupts requires the interrupt controller to be programmed first. 19.5.4 Peripheral Events The GPIO peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 19.5.5 Debug Operation When an external debugger forces the CPU into debug mode, the GPIO continues normal operation. If the GPIO is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 333 32099A–AVR32–06/09 AT32UC3L 19.6 Functional Description The GPIO controls the I/O pins of the microcontroller. The control logic associated with each pin is shown in Figure 19-2. Figure 19-2. Overview of the GPIO PDER* PUER* ODER 1 0 Periph. Func. A Periph.Func. B Periph. Func. C 1 Output 0 Pullup, Pulldown and buskeeper 32099A–AVR32–06/09 .... GPER PMRn GPIO_ODMER Output Enable 0 0 OVR 1 PIN 1 OSRRn* ODCRn* Drive strength and slew rate control Input Schmitt trigger PVR STER* IER 0 Edge Detector 1 1 IFR 0 Interrupt Request Glitch Filter IMR1 GFER IMR0 *) Register value is overrided if a peripheral function that support this function is enabled 334 AT32UC3L 19.6.1 19.6.1.1 Basic Operation Module Configuration The GPIO user interface registers are organized into ports and each port controls 32 different GPIO pins. Most of the registers supports bit wise access operations such as set, clear and toggle in addition to the standard word access. For details regarding interface registers, refer to Section 19.7. Available Features Most of the GPIO features are configurable for each product. The programmer must refer to the Module Configuration section and the GPIO Function Multiplexing section in the Package and Pinout chapter for the configuration used in this product. Product specific settings includes: • • • • 19.6.1.3 Inputs The level on each GPIO pin can be read through the Pin Value Register (PVR). This register indicates the level of the GPIO pins regardless of the pins being driven by the GPIO or by an external component. Note that due to power saving measures, the PVR register will only be updated when the corresponding bit in GPER is one or if an interrupt is enabled for the pin, i.e. IER is one for the corresponding pin. 19.6.1.4 Output Control When the GPIO pin is assigned to a peripheral function, i.e. the corresponding bit in GPER is zero, the peripheral determines whether the pin is driven or not. When the GPIO pin is controlled by the GPIO, the value of Output Driver Enable Register (ODER) determines whether the pin is driven or not. When a bit in this register is one, the corresponding GPIO pin is driven by the GPIO. When the bit is zero, the GPIO does not drive the pin. The level driven on a GPIO pin can be determined by writing the value to the corresponding bit in the Output Value Register (OVR). 19.6.1.5 Peripheral Muxing The GPIO allows a single GPIO pin to be shared by multiple peripheral pins and the GPIO itself. Peripheral pins sharing the same GPIO pin are arranged into peripheral functions that can be selected one at a time. Peripheral functions are configured by writing the selected function value to the Peripheral Mux Registers (PMRn). To allow a peripheral pin access to the shared GPIO pin, GPIO control must be disabled for that pin, i.e. the corresponding bit in GPER must read zero. A peripheral function value is set by writing bit zero to PMR0 and bit one to the same index position in PMR1 and so on. In a system with 4 peripheral functions A,B,C, and D, peripheral function C for GPIO pin four is selected by writing a zero to bit four in PMR0 and a one to the same bit index in PMR1. Refer to the GPIO Function Multiplexing chapter for details regarding pin function configuration for each GPIO pin. Number of GPIO pins Functions implemented on each pin Peripheral function(s) multiplexed on each GPIO pin Reset state of registers 19.6.1.2 335 32099A–AVR32–06/09 AT32UC3L 19.6.2 19.6.2.1 Advanced Operation Peripheral I/O Pin Control When a GPIO pin is assigned to a peripheral function, i.e. the corresponding bit in GPER is zero, output and output enable is controlled by the selected peripheral pin. In addition the peripheral may control some or all of the other GPIO pin functions listed in Table 19-1, if the peripheral supports those features. All pin features not controlled by the selected peripheral is controlled by the GPIO. Refer to the Module Configuration section for details regarding implemented GPIO pin functions and to the Peripheral chapter for details regarding I/O pin function control. Table 19-1. I/O Pin function Control GPIO mode OVR ODER PUER PDER PUER&PDER ODCRn OSRRn ODMR STER Peripheral mode Peripheral Peripheral Peripheral if supported, else GPIO Peripheral if supported, else GPIO Peripheral if supported, else GPIO Peripheral if supported, else GPIO Peripheral if supported, else GPIO Peripheral if supported, else GPIO Peripheral if supported, else GPIO Function name Output Output enable Pull-up Pull-down Buskeeper Drive strength Slew rate Open drain Schmitt trigger 19.6.2.2 Pull-up Resistor, Pull-down Resistor and Buskeeper Control Pull-up, pull-down, and buskeeper can be configured for each GPIO pin. Pull-up allows the pin and any connected net to be pulled up to VDD if the net is not driven. Pull-down pulls the net to GND, while buskeeper keeps the current logic level if the net becomes undriven. Pull-up and pull-down are useful for detecting if a pin is unconnected or if a mechanical button is pressed, for various communication protocols and to keep unconnected pins from floating. Pull-up can be enabled and disabled by writing a one and a zero respectively to the corresponding bit in the Pull-up Enable Register (PUER). Pull-down can be enabled and disabled by writing a one and a zero respectively to the corresponding bit in the Pull-down Enable Register (PDER). To enable the buskeeper for a pin, the corresponding bit in PUER and PDER must be written to one. 19.6.2.3 Output Pin Timings Figure 19-3 shows the timing of the GPIO pin when writing to the Output Value Register (OVR). The same timing applies when performing a ‘set’ or ‘clear’ access, i.e. writing to OVRS or OVRC. The timing of PVR is also shown. 336 32099A–AVR32–06/09 AT32UC3L Figure 19-3. Output Pin Timings CLK_GPIO Write OVR to 1 PB Access Write OVR to 0 PB Access OVR / I/O Line PVR 19.6.2.4 Pin Output Driver Control The GPIO has registers for controlling output drive properties of each pin, such as output driving capability and slew rate control. The driving capability is controlled by the Output Driving Capability Registers (ODCRn) and the slew rate settings are controlled by the Output Slew Rate Registers (OSRRn). For a GPIO pin with four different slew rate settings, a slew rate of two can be selected by writing a zero to the OSRR0 register at the bit position corresponding to the GPIO pin, and a one to the OSRR1 at the same bit position. The ODCRn registers are configured in the same way. 19.6.2.5 19.6.2.6 Open Drain Mode Each GPIO pin can be independently configured to operate in Open Drain mode. This permits several drivers to be connected on the same GPIO pin. The drivers should only actively drive the pin low. An external pull-up resistor (or enabling the internal one) is generally required to guarantee a high level on the pin when no driver is active. The Open Drain mode is controlled by the Open Drain Mode Enable Register (ODMER)Input Schmitt Trigger Each GPIO pin can be configured with an input Schmitt trigger. An input Schmitt trigger filters input signal using an hysteresis function, stopping noise from propagation into the system. The input Schmitt trigger can be enabled and disabled by writing a one and a zero respectively to the Schmitt Trigger Enable Register (STER). Interrupts The GPIO can be configured to generate an interrupt when it detects a change on a GPIO pin. Interrupts on a pin are enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER). The module can be configured to generate an interrupt whenever a pin changes value, or only on rising or falling edges. This is controlled by the Interrupt Mode Registers (IMRn). Interrupts on a pin can be enabled regardless of the GPIO pin being controlled by the GPIO or assigned to a peripheral function. An interrupt can be generated on each GPIO pin. These interrupt generators are further grouped into groups of eight and connected to the interrupt controller. An interrupt request from any of the GPIO pin generators in the group will result in an interrupt request from that group to the interrupt controller if the corresponding bit for the GPIO pin in the IER is set. By grouping interrupt generators into groups of eight, four different interrupt handlers can be installed for each GPIO port. 19.6.2.7 337 32099A–AVR32–06/09 AT32UC3L The Interrupt Flag Register (IFR) can be read by software to determine which pin(s) caused the interrupt. The interrupt flag must be manually cleared by writing a zero to the corresponding bit in IFR. GPIO interrupts will only be generated when CLK_GPIO is enabled. 19.6.2.8 Input Glitch Filter Input glitch filters can be enabled on each GPIO pin. When the glitch filter is enabled, a glitch with duration of less than 1 CLK_GPIO cycle is automatically rejected, while a pulse with duration of 2 CLK_GPIO cycles or more is accepted. For pulse durations between 1 and 2 CLK_GPIO cycles, the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be guaranteed visible it must exceed 2 CLK_GPIO cycles, whereas for a glitch to be reliably filtered out, its duration must not exceed 1 CLK_GPIO cycle. The filter introduces 2 clock cycles latency. The glitch filters are controlled by the Glitch Filter Enable Register (GFER). When a bit in GFER is one, the glitch filter on the corresponding pin is enabled. The glitch filter affects only interrupt inputs. Inputs to peripherals or the value read through PVR are not affected by the glitch filters. 19.6.2.9 Interrupt Timings Figure 19-4 shows the timing for rising edge (or pin-change) interrupts when the glitch filter is disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In this example, this is not the case for the first pulse. The second pulse is sampled on a rising edge and will trigger an interrupt request. Figure 19-4. Interrupt Timing with Glitch Filter Disabled CLK_GPIO Pin Level IFR Figure 19-5 shows the timing for rising edge (or pin-change) interrupts when the glitch filter is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges. In the example, the first pulse is rejected while the second pulse is accepted and causes an interrupt request. Figure 19-5. Interrupt Timing with Glitch Filter Enabled CLK_GPIO Pin Level IFR 338 32099A–AVR32–06/09 AT32UC3L 19.6.2.10 CPU Local Bus The CPU Local Bus can be used for application where low latency read and write access to the Output Value Register (OVR) and Output Drive Enable Register (ODER) is required. The CPU Local Bus allows the CPU to configure the mentioned GPIO registers directly, bypassing the shared Peripheral Bus (PB). To avoid data loss when using the CPU Local Bus, the CLK_GPIO must run at the same frequency as the CLK_CPU. See Section 19.5.2 for details. The CPU Local Bus is mapped to a different base address than the GPIO but the OVER and ODER offsets are the same. See the CPU Local Bus Mapping section in the Memories chapter for details. 19.6.2.11 Peripheral Events Peripheral events allow direct peripheral to peripheral communication of specified events. See the Peripheral Event System chapter for more information. The GPIO can be programmed to output peripheral events whenever an interrupt condition is detected, such as pin value change, or only when a rising or falling edge is detected. Peripheral event on a pin is enabled by writing a one to the corresponding bit in the Event Enable Register (EVER). The Peripheral Event trigger mode is shared with the interrupt trigger and is configured by writing to the IMR0 and IMR1 registers. Interrupt does not need to be enabled on a pin when peripheral events are enabled. Peripheral Events are also affected by the Input Glitch Filter settings. See Section 19.6.2.8 for more information. A peripheral event can be generated on each GPIO pin. Each port can then have up to 32 peripheral event generators. Groups of eight peripheral event generators in each port are ORed together to form a peripheral event line, so that each port has four peripheral event lines connected to the Peripheral Event System. 339 32099A–AVR32–06/09 AT32UC3L 19.7 User Interface The GPIO controller manages all the GPIO pins on the AVR32 microcontroller. The pins are managed as 32-bit ports that are configurable through a Peripheral Bus (PB) interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports is product specific. Figure 19-6. Port Configuration Registers 0x0000 Port 0 Configuration Registers 0x0200 Port 1 Configuration Registers 0x0400 Port 2 Configuration Registers …. n*0x200 Port n Configuration Registers In the peripheral muxing table in the Package and Pinout chapter each GPIO pin has a unique number. Note that the PA, PB, PC and PX ports do not directly correspond to the GPIO ports. To find the corresponding port and pin the following formulas can be used: GPIO port = floor((GPIO number) / 32), example: floor((36)/32) = 1 GPIO pin = GPIO number % 32, example: 36 % 32 = 4 Figure 19-6 on page 340 shows the configuration registers for one port. Addresses shown are relative to the port address offset. The specific address of a configuration register is found by adding the register offset and the port offset to the GPIO start address. One bit in each of the configuration registers corresponds to a GPIO pin. 19.7.1 Access Types Most configuration register can be accessed in four different ways. The first address location can be used to write the register directly. This address can also be used to read the register value. The following addresses facilitate three different types of write access to the register. Performing a “set” access, all bits written to one will be set. Bits written to zero will be unchanged by the operation. Performing a “clear” access, all bits written to one will be cleared. Bits written to zero will be unchanged by the operation. Finally, a toggle access will toggle the value of all bits writ- 340 32099A–AVR32–06/09 AT32UC3L ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g. IFR), not all access methods are permitted. Note that for ports with less than 32 bits, the corresponding control registers will have unused bits. This is also the case for features that are not implemented for a specific pin. Writing to an unused bit will have no effect. Reading unused bits will always return 0. 19.7.2 Configuration Protection In order to protect the configuration of individual GPIO pins from software failure, configuration bits for individual GPIO pins may be locked by writing a one to the corresponding bit in the LOCK register. While this bit is one, any write to the same bit position in any lockable GPIO register will not have an effect. The registers required to clear bits in the LOCK register are protected by the access protection mechanism described in Section 19.7.3, ensuring the LOCK mechanism itself is robust against software failure. 19.7.3 Access Protection In order to protect critical registers from software failure, some registers are protected by a key protection mechanism. These registers can only be changed by first writing the UNLOCK register, then the protected register. Protected registers are indicated in Table 19-2. The UNLOCK register contains a key field which must always be written to 0xAA, and an OFFSET field corresponding to the offset of the register to be modified. The next write operation resets the UNLOCK register, so if the register is to be modified again, the UNLOCK register must be written again. Attempting to write to a protected register without first writing the UNLOCK register results in the write operation being discarded, and the Access Error bit in the Access Status Register (ASR.AE) will be set. Table 19-2. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C GPIO Register Memory Map Register GPIO Enable Register GPIO Enable Register GPIO Enable Register GPIO Enable Register Peripheral Mux Register 0 Peripheral Mux Register 0 Peripheral Mux Register 0 Peripheral Mux Register 0 Peripheral Mux Register 1 Peripheral Mux Register 1 Peripheral Mux Register 1 Peripheral Mux Register 1 Function Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Set Clear Toggle Register Name GPER GPERS GPERC GPERT PMR0 PMR0S PMR0C PMR0T PMR1 PMR1S PMR1C PMR1T Access Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only (1) (1) Reset (1) Configuration Protection Y Y Y Y Y Y Y Y Y Y Y Y Access Protection N N N N N N N N N N N N 341 32099A–AVR32–06/09 AT32UC3L Table 19-2. Offset 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05c GPIO Register Memory Map Register Peripheral Mux Register 2 Peripheral Mux Register 2 Peripheral Mux Register 2 Peripheral Mux Register 2 Output Driver Enable Register Output Driver Enable Register Output Driver Enable Register Output Driver Enable Register Output Value Register Output Value Register Output Value Register Output Value Register Function Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Set Clear Toggle Register Name PMR2 PMR2S PMR2C PMR2T ODER ODERS ODERC ODERT OVR OVRS OVRC OVRT Access Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Depen ding on pin states (1) (1) Reset (1) Configuration Protection Y Y Y Y Y Y Y Y N N N N Access Protection N N N N N N N N N N N N 0x060 Pin Value Register Read PVR Read-only N N 0x064 0x068 0x06c 0x070 0x074 0x078 0x07C 0x080 0x084 0x088 0x08C 0x090 0x094 0x098 0x09C 0x0A0 0x0A4 0x0A8 0x0AC 0x0B0 Pin Value Register Pin Value Register Pin Value Register Pull-up Enable Register Pull-up Enable Register Pull-up Enable Register Pull-up Enable Register Pull-down Enable Register Pull-down Enable Register Pull-down Enable Register Pull-down Enable Register Interrupt Enable Register Interrupt Enable Register Interrupt Enable Register Interrupt Enable Register Interrupt Mode Register 0 Interrupt Mode Register 0 Interrupt Mode Register 0 Interrupt Mode Register 0 Interrupt Mode Register 1 Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read/Write PUER PUERS PUERC PUERT PDER PDERS PDERC PDERT IER IERS IERC IERT IMR0 IMR0S IMR0C IMR0T IMR1 Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write (1) (1) (1) (1) (1) N N N Y Y Y Y Y Y Y Y N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 342 32099A–AVR32–06/09 AT32UC3L Table 19-2. Offset 0x0B4 0x0B8 0x0BC 0x0C0 0x0C4 0x0C8 0x0CC 0x0D0 0x0D4 0x0D8 0x0DC 0x0E0 0x0E4 0x0E8 0x0EC 0x0F00x0FC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x1200x12C 0x130 0x134 0x138 0x13C 0x1400x15C 0x160 GPIO Register Memory Map Register Interrupt Mode Register 1 Interrupt Mode Register 1 Interrupt Mode Register 1 Glitch Filter Enable Register Glitch Filter Enable Register Glitch Filter Enable Register Glitch Filter Enable Register Interrupt Flag Register Interrupt Flag Register Interrupt Flag Register Interrupt Flag Register Open Drain Mode Enable Register Open Drain Mode Enable Register Open Drain Mode Enable Register Open Drain Mode Enable Register RESERVED Function Set Clear Toggle Read/Write Set Clear Toggle Read Clear Read/Write Set Clear Toggle Read/Write Set Clear Toggle Read Set Clear Toggle Read Set Clear Toggle Read Register Name IMR1S IMR1C IMR1T GFER GFERS GFERC GFERT IFR IFRC ODMER ODMER S ODMER C ODMER T ODCR0 ODCR0S ODCR0C ODCR0T ODCR1 ODCR1S ODCR1C ODCR1T OSRR0 OSRR0S OSRR0C OSRR0T STER Access Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read-only Write-only Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write (1) Y N Y Y Y Y N N N N (1) (1) Y Y Y Y Y Y Y Y N N N N N N N N (1) (1) (1) Reset Configuration Protection N N N N N N N N N N N Y Y Y Y Access Protection N N N N N N N N N N N N N N N Output Driving Capability Register 0 Output Driving Capability Register 0 Output Driving Capability Register 0 Output Driving Capability Register 0 Output Driving Capability Register 1 Output Driving Capability Register 1 Output Driving Capability Register 1 Output Driving Capability Register 1 RESERVED Output Slew Rate Register 0 Output Slew Rate Register 0 Output Slew Rate Register 0 Output Slew Rate Register 0 RESERVED Schmitt Trigger Enable Register 343 32099A–AVR32–06/09 AT32UC3L Table 19-2. Offset 0x164 0x168 0x16C 0x1700x17C 0x180 0x184 0x188 0x18C 0x1900x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B00x1DC 0x1E0 0x1E4 0x1E80x1F4 0x1F8 0x1FC 1. GPIO Register Memory Map Register Schmitt Trigger Enable Register Schmitt Trigger Enable Register Schmitt Trigger Enable Register RESERVED Event Enable Register Event Enable Register Event Enable Register Event Enable Register RESERVED Lock Register Lock Register Lock Register Lock Register RESERVED Unlock Register Access Status Register RESERVED Parameter Register Version Register Function Set Clear Toggle Read Set Clear Toggle Read/Write Set Clear Toggle Read/Write Read/Write Read Read Register Name STERS STERC STERT EVER EVERS EVERC EVERT LOCK LOCKS LOCKC LOCKT UNLOCK ASR PARAME TER VERSIO N Access Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Read/Write Write-only Write-only Write-only Write-only Read/Write Read-only Read-only - (1) -(1) N N N N N N N (1) N N N N Y N Y Y (1) N N N N N N N N Reset Configuration Protection Y Y Y Access Protection N N N The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 344 32099A–AVR32–06/09 AT32UC3L 19.7.4 Name: Access: Offset: Reset Value: 31 GPIO Enable Register GPER Read/Write, Set, Clear, Toggle 0x000, 0x004, 0x008, 0x00C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: GPIO Enable 0: A peripheral function controls the corresponding pin. 1: The GPIO controls the corresponding pin. 345 32099A–AVR32–06/09 AT32UC3L 19.7.5 Name: Access: Offset: Reset Value: 31 Peripheral Mux Register 0 PMR0 Read/Write, Set, Clear, Toggle 0x010, 0x014, 0x018, 0x01C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Peripheral Multiplexer Select bit 0 346 32099A–AVR32–06/09 AT32UC3L 19.7.6 Name: Access: Offset: Reset Value: 31 Peripheral Mux Register 1 PMR1 Read/Write, Set, Clear, Toggle 0x020, 0x024, 0x028, 0x02C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Peripheral Multiplexer Select bit 1 347 32099A–AVR32–06/09 AT32UC3L 19.7.7 Name: Access: Offset: Reset Value: 31 Peripheral Mux Register 2 PMR2 Read/Write, Set, Clear, Toggle 0x030, 0x034, 0x038, 0x03C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Peripheral Multiplexer Select bit 2 {PMR2, PMR1, PMR0} 000 001 010 011 100 101 110 111 Selected Peripheral Function A B C D E F G H 348 32099A–AVR32–06/09 AT32UC3L 19.7.8 Name: Access: Offset: Reset Value: 31 Output Driver Enable Register ODER Read/Write, Set, Clear, Toggle 0x040, 0x044, 0x048, 0x04C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Driver Enable 0: The output driver is disabled for the corresponding pin. 1: The output driver is enabled for the corresponding pin. 349 32099A–AVR32–06/09 AT32UC3L 19.7.9 Name: Access: Offset: Reset Value: 31 Output Value Register OVR Read/Write, Set, Clear, Toggle 0x050, 0x054, 0x058, 0x05C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Value 0: The value to be driven on the GPIO pin is 0. 1: The value to be driven on the GPIO pin is 1. 350 32099A–AVR32–06/09 AT32UC3L 19.7.10 Name: Access: Offset: Reset Value: 31 Pin Value Register PVR Read-only 0x060, 0x064, 0x068, 0x06C Depending on pin states 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pin Value 0: The GPIO pin is at level zero. 1: The GPIO pin is at level one. Note that the level of a pin can only be read when the corresponding pin in GPER is one or interrupt is enabled for the pin. 351 32099A–AVR32–06/09 AT32UC3L 19.7.11 Name: Access: Offset: Reset Value: 31 Pull-up Enable Register PUER Read/Write, Set, Clear, Toggle 0x070, 0x074, 0x078, 0x07C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pull-up Enable 352 32099A–AVR32–06/09 AT32UC3L 19.7.12 Name: Access: Offset: Reset Value: 31 Pull-down Enable Register PDER Read/Write, Set, Clear, Toggle 0x080, 0x084, 0x088, 0x08C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pull-down Enable {PUER, PDER} 00 01 10 11 Selected Function Disabled Pull-down enabled Pull-up enabled Buskeeper enabled 353 32099A–AVR32–06/09 AT32UC3L 19.7.13 Name: Access: Offset: Reset Value: 31 Interrupt Enable Register IER Read/Write, Set, Clear, Toggle 0x090, 0x094, 0x098, 0x09C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Enable 0: Interrupt is disabled for the corresponding pin. 1; Interrupt is enabled for the corresponding pin. 354 32099A–AVR32–06/09 AT32UC3L 19.7.14 Name: Access: Offset: Reset Value: 31 Interrupt Mode Register 0 IMR0 Read/Write, Set, Clear, Toggle 0x0A0, 0x0A4, 0x0A8, 0x0AC 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Mode Bit 0 355 32099A–AVR32–06/09 AT32UC3L 19.7.15 Name: Access: Offset: Reset Value: 31 Interrupt Mode Register 1 IMR1 Read/Write, Set, Clear, Toggle 0x0B0, 0x0B4, 0x0B8, 0x0BC 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Mode Bit 1 {IMR1, IMR0} 00 01 10 11 Interrupt Mode Pin Change Rising Edge Falling Edge Reserved 356 32099A–AVR32–06/09 AT32UC3L 19.7.16 Name: Access: Offset: Reset Value: 31 Glitch Filter Enable Register GFER Read/Write, Set, Clear, Toggle 0x0C0, 0x0C4, 0x0C8, 0x0CC 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Glitch Filter Enable 0: Glitch filter is disabled for the corresponding pin. 1: Glitch filter is enabled for the corresponding pin. NOTE! The value of this register should only be changed when the corresponding bit in IER is zero. Updating GFER while interrupt on the corresponding pin is enabled can cause an unintentional interrupt to be triggered. 357 32099A–AVR32–06/09 AT32UC3L 19.7.17 Name: Access: Offset: Reset Value: 31 Interrupt Flag Register IFR Read, Clear 0x0D0, 0x0D8 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Flag 0: An interrupt condition has been detected on the corresponding pin. 1: No interrupt condition has been detected on the corresponding pin. The number of interrupt request lines depends on the number of GPIO pins on the MCU. Refer to the product specific data for details. Note also that a bit in the Interrupt Flag register is only valid if the corresponding bit in IER is one. 358 32099A–AVR32–06/09 AT32UC3L 19.7.18 Name: Access: Offset: Reset Value: 31 Open Drain Mode Enable Register ODMER Read/Write, Set, Clear, Toggle 0x0E0, 0x0E4, 0x0E8, 0x0EC 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Open Drain Mode Enable 0: Open Drain mode is disabled for the corresponding pin. 359 32099A–AVR32–06/09 AT32UC3L 19.7.19 Name: Access: Offset: Reset Value: 31 1: Open Drain mode is enabled for the corresponding pin.Output Driving Capability Register 0 ODCR0 Read/Write, Set, Clear, Toggle 0x100, 0x104, 0x108, 0x10C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Driving Capability Register Bit 0 360 32099A–AVR32–06/09 AT32UC3L 19.7.20 Name: Access: Offset: Reset Value: 31 Output Driving Capability Register 1 ODCR1 Read/Write, Set, Clear, Toggle 0x110, 0x114, 0x118, 0x11C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Driving Capability Bit 1 {ODCR1, ODCR0} 00 01 10 11 Interrupt Mode Lowest drive strength ... ... Highest drive strength For the actual drive strength of the pin, please refer to the Electrical Characteristics chapter. 361 32099A–AVR32–06/09 AT32UC3L 19.7.21 Name: Access: Offset: Reset Value: 31 Output Slew Rate Register 0 OSRR0 Read/Write, Set, Clear, Toggle 0x130, 0x134, 0x138, 0x13C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Slew Rate Control Enable 0: Slew rate control is disabled for the corresponding pin. 1: Slew rate control is enabled for the corresponding pin. 362 32099A–AVR32–06/09 AT32UC3L 19.7.22 Name: Access: Offset: Reset Value: 31 Schmitt Trigger Enable Register STER Read/Write, Set, Clear, Toggle 0x160, 0x164, 0x168, 0x16C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Schmitt Trigger Enable 0: Schmitt trigger is disabled for the corresponding pin. 1: Schmitt trigger is enabled for the corresponding pin. 363 32099A–AVR32–06/09 AT32UC3L 19.7.23 Name: Access: Offset: Reset Value: 31 Event Enable Register EVER Read/Write, Set, Clear, Toggle 0x180, 0x184, 0x188, 0x18C 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Event Enable 0: Peripheral Event is disabled for the corresponding pin. 1: Peripheral Event is enabled for the corresponding pin. 364 32099A–AVR32–06/09 AT32UC3L 19.7.24 Name: Access: Offset: Reset Value: 31 Lock Register LOCK Read/Write, Set, Clear, Toggle 0x1A0, 0x1A4, 0x1A8, 0x1AC 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Lock State 0: Pin is unlocked. The corresponding bit can be changed in any GPIO register for this port. 1: Pin is locked. The corresponding bit can not be changed in any GPIO register for this port. The LOCK, LOCKC, and LOCKT registers are protected, which means they can only be written immediately after a write to the UNLOCK register with the proper KEY and OFFSET. LOCKS is not protected, and can be written at any time. 365 32099A–AVR32–06/09 AT32UC3L 19.7.25 Name: Access: Offset: Reset Value: 31 Unlock Register UNLOCK Write-only 0x1E0 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 OFFSET 0 OFFSET • OFFSET: Register Offset This field must be written with the register offset value of the register to unlock. Note that the two LSBs of this register will always read as zero. • KEY: Unlocking Key This bitfield must be written to 0xAA for a write to this register to have an effect. This register always reads as zero. 366 32099A–AVR32–06/09 AT32UC3L 19.7.26 Name: Access: Offset: Reset Value: 31 Access Status Register ASR Read/Write 0x1E4 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - AE • AE: Access Error This bit is set when a write to a locked register occurs. This bit can be written to 0 by software. 367 32099A–AVR32–06/09 AT32UC3L 19.7.27 Name: Parameter Register PARAMETER Read-only 0x1F8 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 PARAMETER 23 22 21 20 19 18 17 16 PARAMETER 15 14 13 12 11 10 9 8 PARAMETER 7 6 5 4 3 2 1 0 PARAMETER • PARAMETER: 0: This pin is not implemented in this GPIO port. 1: This pin is implemented in this GPIO port. There is one PARAMETER register per GPIO port. 368 32099A–AVR32–06/09 AT32UC3L 19.7.28 Name: VERSION Register VERSION Read-only 0x1FC 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 VERSION[11:8] 1 0 VERSION[7:0] • VERSION: Version Number Version number of the module. No functionality associated. 369 32099A–AVR32–06/09 AT32UC3L 19.8 Module Configuration The specific configuration for each GPIO instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 19-3. Feature Number of GPIO ports Number of peripheral functions Module Configuration GPIO 2 8 Table 19-4. Pin Function Pull-up Pull-down Buskeeper Drive strength Slew rate Open drain Schmitt trigger Implemented Pin Functions Implemented Yes No No No No No No Notes Controlled by PUER or peripheral Writing to PDER has no effect Writing a one to PUER and PDER only enabled Pull-up Writing to ODCRn has no effect Writing to OSRRn has no effect Writing to ODMR has no effect Writing to STER has no effect Table 19-5. Module Name GPIO Module Clock Name Clock Name CLK_GPIO The reset values for all GPIO registers are zero, with the following exceptions: Table 19-6. Port 0 0 0 0 1 1 1 1 Register Reset Values Register GPER PUER PARAMETER VERSION GPER PUER PARAMETER VERSION Reset Value 0x0026FFAF 0x00000001 0x0EFFFFFF 0x00000211 0x00001FCF 0x00000000 0x00001FFF 0x00000211 370 32099A–AVR32–06/09 AT32UC3L 20. Universal Synchronous Asynchronous Receiver Transmitter (USART) Rev.4.4.0.3 20.1 Features • Programmable Baud Rate Generator • 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications – 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode – Parity Generation and Error Detection – Framing Error Detection, Overrun Error Detection – MSB- or LSB-first – Optional Break Generation and Detection – By 8 or by 16 Over-sampling Receiver Frequency – Optional Hardware Handshaking RTS-CTS – Receiver Time-out and Transmitter Timeguard – Optional Multidrop Mode with Address Generation and Detection SPI Mode – Master or Slave – Serial Clock Programmable Phase and Polarity – SPI Serial Clock (CLK) Frequency up to Internal Clock Frequency CLK_USART/4 LIN Mode – Compliant with LIN 1.3 and LIN 2.0 specifications – Master or Slave – Processing of frames with up to 256 data bytes – Response Data length can be configurable or defined automatically by the Identifier – Self synchronization in Slave node configuration – Automatic processing and verification of the “Synch Break” and the “Synch Field” – The “Synch Break” is detected even if it is partially superimposed with a data byte – Automatic Identifier parity calculation/sending and verification – Parity sending and verification can be disabled – Automatic Checksum calculation/sending and verification – Checksum sending and verification can be disabled – Support both “Classic” and “Enhanced” checksum types – Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal Test Modes – Remote Loopback, Local Loopback, Automatic Echo Supports Connection of Two Peripheral DMA Controller Channels (PDCA) – Offers Buffer Transfer without Processor Intervention • • • • 20.2 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. 371 32099A–AVR32–06/09 AT32UC3L The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485, LIN and SPI buses, with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDCA provides chained buffer management without any intervention of the processor. 20.3 Block Diagram Figure 20-1. USART Block Diagram Peripheral DMA Controller Channel Channel USART I/O Controller RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS CLK_USART CLK_USART/DIV BaudRate Generator CLK Power Manager DIV User Interface Peripheral bus 372 32099A–AVR32–06/09 AT32UC3L Table 20-1. PIN RXD TXD RTS CTS SPI Operating Mode USART RXD TXD RTS CTS SPI Slave MOSI MISO – CS SPI Master MISO MOSI CS – 20.4 Application Block Diagram Figure 20-2. Application Block Diagram PPP Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver LIN Driver SPI Driver USART RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers LIN Transceiver SPI Bus Serial Port Differential Bus 373 32099A–AVR32–06/09 AT32UC3L 20.5 I/O Lines Description I/O Lines Description Description Serial Clock Transmit Serial Data or Master Out Slave In (MOSI) in SPI Master Mode or Master In Slave Out (MISO) in SPI Slave Mode Receive Serial Data or Master In Slave Out (MISO) in SPI Master Mode or Master Out Slave In (MOSI) in SPI Slave Mode Clear to Send or Slave Select (NSS) in SPI Slave Mode Request to Send or Slave Select (NSS) in SPI Master Mode Type I/O Output Active Level Table 20-2. Name CLK TXD RXD Input CTS RTS Input Output Low Low 374 32099A–AVR32–06/09 AT32UC3L 20.6 20.6.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the I/O Controller lines. The programmer must first program the I/O Controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the I/O Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled. 20.6.2 Clocks The clock for the USART bus interface (CLK_USART) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the USART before disabling the clock, to avoid freezing the USART in an undefined state. 20.6.3 Interrupts The USART interrupt request line is connected to the interrupt controller. Using the USART interrupt requires the interrupt controller to be programmed 375 32099A–AVR32–06/09 AT32UC3L first. 376 32099A–AVR32–06/09 AT32UC3L 20.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.5 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling receiver frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication • High-speed 5- to 9-bit full-duplex synchronous serial communication – MSB- or LSB-first – 1 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication • RS485 with driver control signal • ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • SPI Mode – Master or Slave – Serial Clock Programmable Phase and Polarity – SPI Serial Clock (CLK) Frequency up to Internal Clock Frequency CLK_USART/4 • LIN Mode – Compliant with LIN 1.3 and LIN 2.0 specifications – Master or Slave – Processing of frames with up to 256 data bytes – Response Data length can be configurable or defined automatically by the Identifier – Self synchronization in Slave node configuration – Automatic processing and verification of the “Synch Break” and the “Synch Field” – The “Synch Break” is detected even if it is partially superimposed with a data byte – Automatic Identifier parity calculation/sending and verification – Parity sending and verification can be disabled – Automatic Checksum calculation/sending and verification – Checksum sending and verification can be disabled – Support both “Classic” and “Enhanced” checksum types – Full LIN error checking and reporting – Frame Slot Mode: the Master allocates slots to the scheduled frames automatically. – Generation of the Wakeup signal • Test modes 377 32099A–AVR32–06/09 AT32UC3L – Remote loopback, local loopback, automatic echo 20.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (MR) between: • CLK_USART • a division of CLK_USART, the divider being product dependent, but generally set to 8 • the external clock, available on the CLK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external CLK clock is selected, the duration of the low and high levels of the signal provided on the CLK pin must be longer than a CLK_USART period. The frequency of the signal provided on CLK must be at least 4.5 times lower than CLK_USART. Figure 20-3. Baud Rate Generator USCLKS CD CD 0 1 2 3 0 CLK_USART CLK_USART/DIV CLK Reserved CLK 16-bit Counter >1 1 0 1 1 SYNC USCLKS= 3 Sampling Clock OVER 0 Sampling Divider 0 BaudRate Clock FIDI SYNC 20.7.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over ) CD ) 378 32099A–AVR32–06/09 AT32UC3L This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is the highest possible clock and that OVER is programmed at 1. 20.7.1.2 Baud Rate Calculation Example Table 20-3 on page 379 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Baud Rate Example (OVER = 0) Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 97.66 6 8 8 12 13 20 20 23 24 30 39 40 40 52 53 54 65 81 98 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 38 265.31 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% 0.35% Error Table 20-3. Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 60 000 000 The baud rate is calculated with the following formula: BaudRate = ( CLKUSART ) ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 – ⎛ --------------------------------------------------⎞ ⎝ ActualBaudRate ⎠ 379 32099A–AVR32–06/09 AT32UC3L 20.7.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = ---------------------------------------------------------------⎛ 8 ( 2 – Over ) ⎛ CD + FP⎞ ⎞ -----⎝ ⎝ 8 ⎠⎠ The modified architecture is presented below: Figure 20-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP CD CLK FIDI >1 1 0 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 Sampling Divider 0 BaudRate Clock OVER SYNC CLK_USART CLK_USART/DIV CLK Reserved 0 1 16-bit Counter 2 3 glitch-free logic 20.7.1.4 Baud Rate in Synchronous Mode or SPI Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in BRGR. BaudRate = SelectedClock ------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART CLK pin. No division is active. The value written in BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. 380 32099A–AVR32–06/09 AT32UC3L When either the external clock CLK or the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the CLK pin. If the internal clock CLK_USART is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the CLK pin, even if the value programmed in CD is odd. 20.7.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- × f Fi where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 20-4 on page 381. Table 20-4. DI field Di (decimal) Binary and Decimal Values for Di 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 20-5 on page 381. Table 20-5. FI field Fi (decimal Binary and Decimal Values for Fi 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 20-6 on page 381 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 20-6. Fi/Di 1 2 4 8 16 32 12 20 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (BRGR). The resulting clock can be provided to the CLK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in MR. 381 32099A–AVR32–06/09 AT32UC3L This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 20-5 on page 382 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 20-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on CLK ISO7816 I/O Line on TXD 1 ETU 20.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (THR). If a timeguard is programmed, it is handled normally. 20.7.3 20.7.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two 382 32099A–AVR32–06/09 AT32UC3L stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in MR. The 1.5 stop bit is supported in asynchronous mode only. Figure 20-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (THR). The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmitter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the characters written in THR have been processed. When the current character processing is completed, the last character written in THR is transferred into the Shift Register of the transmitter and THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in THR while TXRDY is low has no effect and the written character is lost. Figure 20-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY 20.7.3.2 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (MR). 383 32099A–AVR32–06/09 AT32UC3L The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 20-8 on page 384 and Figure 20-9 on page 384 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 20-8. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 20-9. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 384 32099A–AVR32–06/09 AT32UC3L 20.7.3.3 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 20-10 on page 385 illustrates a character reception in synchronous mode. Figure 20-10. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 20.7.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. Figure 20-11. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write CR Read RHR RXRDY OVRE 385 32099A–AVR32–06/09 AT32UC3L 20.7.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 387. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 20-7 on page 386 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 20-7. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (CSR). The PARE bit can be cleared by writing the Control Register (CR) with the RSTSTA bit at 1. Figure 20-12 on page 387 illustrates the parity bit status setting and clearing. 386 32099A–AVR32–06/09 AT32UC3L Figure 20-12. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write CR PARE RXRDY 20.7.3.6 Multidrop Mode If the PAR field in the Mode Register (MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to CR. In this case, the next byte written to THR is transmitted as an address. Any character written in THR without having written the command SENDA is transmitted normally with the parity at 0. 20.7.3.7 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 20-13 on page 388, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 387 32099A–AVR32–06/09 AT32UC3L Figure 20-13. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write THR TXRDY TXEMPTY Table 20-8 on page 388 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 20-8. Maximum Timeguard Length Depending on Baud Rate Bit time µs 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 20.7.3.8 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at 0. Otherwise, the receiver loads a counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: • Stop the counter clock until a new character is received. This is performed by writing the Control Register (CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to 388 32099A–AVR32–06/09 AT32UC3L handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 20-14 on page 389 shows the block diagram of the Receiver Time-out feature. Figure 20-14. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 20-9 on page 389 gives the maximum time-out period for some standard baud rates. Table 20-9. Maximum Time-out Period Bit Time µs 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 389 32099A–AVR32–06/09 AT32UC3L Table 20-9. Maximum Time-out Period (Continued) Bit Time 18 17 5 Time-out 1 170 1 138 328 Baud Rate 56000 57600 200000 20.7.3.9 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. Figure 20-15. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write CR FRAME RXRDY 20.7.3.10 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 390 32099A–AVR32–06/09 AT32UC3L The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 20-16 on page 391 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 20-16. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write CR TXRDY TXEMPTY 20.7.3.11 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in CSR. This bit may be cleared by writing the Control Register (CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 20.7.3.12 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 20-17 on page 392. 391 32099A–AVR32–06/09 AT32UC3L Figure 20-17. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the MODE field in the Mode Register (MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDCA channel for reception. The transmitter can handle hardware handshaking in any case. Figure 20-18 on page 392 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDCA channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDCA clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 20-18. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write CR RTS RXBUFF RXDIS = 1 Figure 20-19 on page 392 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 20-19. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 392 32099A–AVR32–06/09 AT32UC3L 20.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the MODE field in the Mode Register (MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 20.7.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 378). The USART connects to a smart card as shown in Figure 20-20 on page 393. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the CLK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 20-20. Connection of a Smart Card to the USART USART CLK CLK Smart Card TXD I/O When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “Mode Register” on page 426 and “PAR: Parity Type” on page 427. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (THR) or after reading it in the Receive Holding Register (RHR). 20.7.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 20-21 on page 394. 393 32099A–AVR32–06/09 AT32UC3L If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 20-22 on page 394. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (RHR). It appropriately sets the PARE bit in the Status Register (SR) so that the software can handle the error. Figure 20-21. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 20-22. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 20.7.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (NER) register. The NB_ERRORS field can record up to 255 errors. Reading NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (SR). The INACK bit can be cleared by writing the Control Register (CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 20.7.4.4 20.7.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. 394 32099A–AVR32–06/09 AT32UC3L When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in CSR can be cleared by writing the Control Register with the RSIT bit at 1. 20.7.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (CSR). RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 20-23 on page 395. Figure 20-23. Typical Connection to a RS485 Bus USART 20.7.4.7 20.7.5 RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the MODE field in the Mode Register (MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 20-24 on page 396 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. 395 32099A–AVR32–06/09 AT32UC3L Figure 20-24. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write THR TXRDY TXEMPTY RTS 396 32099A–AVR32–06/09 AT32UC3L 20.7.6 SPI Mode The Serial Peripheral Interface (SPI) Mode is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master” which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turns being masters and one master may simultaneously shift data into multiple slaves. (Multiple Master Protocol is the opposite of Single Master Protocol, where one CPU is always the master while all of the others are always slaves.) However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when its NSS signal is asserted by the master. The USART in SPI Master mode can address only one SPI Slave because it can generate only one NSS signal. The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input of the slave. • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. • Serial Clock (CLK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates. The CLK line cycles once for each bit that is transmitted. • Slave Select (NSS): This control line allows the master to select or deselect the slave. 20.7.6.1 Modes of Operation The USART can operate in Master Mode or in Slave Mode. Operation in SPI Master Mode is programmed by writing at 0xE the MODE field in the Mode Register. In this case the SPI lines must be connected as described below: • the MOSI line is driven by the output pin TXD • the MISO line drives the input pin RXD • the CLK line is driven by the output pin CLK • the NSS line is driven by the output pin RTS Operation in SPI Slave Mode is programmed by writing at 0xF the MODE field in the Mode Register. In this case the SPI lines must be connected as described below: • the MOSI line drives the input pin RXD • the MISO line is driven by the output pin TXD • the CLK line drives the input pin CLK • the NSS line drives the input pin CTS In order to avoid unpredicted behavior, any change of the SPI Mode must be followed by a software reset of the transmitter and of the receiver (except the initial configuration after a hardware reset). (See Section 20.7.7.2 on page 402). 397 32099A–AVR32–06/09 AT32UC3L 20.7.6.2 Baud Rate In SPI Mode, the baudrate generator operates in the same way as in USART synchronous mode: See “Baud Rate in Synchronous Mode or SPI Mode” on page 380. However, there are some restrictions: In SPI Master Mode: • the external clock CLK must not be selected (USCLKS … 0x3), and the bit CLKO must be set to “1” in the Mode Register (MR), in order to generate correctly the serial clock on the CLK pin. • to obtain correct behavior of the receiver and the transmitter, the value programmed in CD of must be superior or equal to 4. • if the internal clock divided (CLK_USART/DIV) is selected, the value programmed in CD must be even to ensure a 50:50 mark/space ratio on the CLK pin, this value can be odd if the internal clock is selected (CLK_USART). In SPI Slave Mode: • the external clock (CLK) selection is forced regardless of the value of the USCLKS field in the Mode Register (MR). Likewise, the value written in BRGR has no effect, because the clock is provided directly by the signal on the USART CLK pin. • to obtain correct behavior of the receiver and the transmitter, the external clock (CLK) frequency must be at least 4 times lower than the system clock. 398 32099A–AVR32–06/09 AT32UC3L 20.7.6.3 Data Transfer Up to 9 data bits are successively shifted out on the TXD pin at each rising or falling edge (depending of CPOL and CPHA) of the programmed serial clock. There is no Start bit, no Parity bit and no Stop bit. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (MR). The 9 bits are selected by setting the MODE 9 bit regardless of the CHRL field. The MSB data bit is always sent first in SPI Mode (Master or Slave). Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Mode Register. The clock phase is programmed with the CPHA bit. These two parameters determine the edges of the clock signal upon which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 20-10. SPI Bus Protocol Mode SPI Bus Protocol Mode 0 1 2 3 CPOL 0 0 1 1 CPHA 1 0 1 0 399 32099A–AVR32–06/09 AT32UC3L Figure 20-25. SPI Transfer Format (CPHA=1, 8 bits per transfer) CLK cycle (for reference) CLK (CPOL= 0) 1 2 3 4 5 6 7 8 CLK (CPOL= 1) MOSI SPI Master ->TXD SPI Slave ->RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master ->RXD SPI Slave ->TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master ->RTS SPI Slave ->CTS Figure 20-26. SPI Transfer Format (CPHA=0, 8 bits per transfer) CLK cycle (for reference) CLK (CPOL= 0) 1 2 3 4 5 6 7 8 CLK (CPOL= 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 400 32099A–AVR32–06/09 AT32UC3L 20.7.6.4 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 382. Character Transmission The characters are sent by writing in the Transmit Holding Register (THR). The transmitter reports two status bits in the Channel Status Register (CSR): TXRDY (Transmitter Ready), which indicates that THR is empty and TXEMPTY, which indicates that all the characters written in THR have been processed. When the current character processing is completed, the last character written in THR is transferred into the Shift Register of the transmitter and THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in THR while TXRDY is low has no effect and the written character is lost. If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (THR) is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time. The UNRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit before the transmission of the MSB bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line (NSS) can be forced at low level by writing the Control Register (CR) with the RTSEN bit at 1. The slave select line (NSS) can be released at high level only by writing the Control Register (CR) with the RTSDIS bit at 1 (for example, when all data have been transferred to the slave device). In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a character transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. 20.7.6.6 Character Reception When a character reception is completed, it is transferred to the Receive Holding Register (RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (CR) with the RSTSTA (Reset Status) bit at 1. To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit. 20.7.6.7 Receiver Timeout Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is impossible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (RTOR). 20.7.6.5 401 32099A–AVR32–06/09 AT32UC3L 20.7.7 LIN Mode The LIN Mode provides Master node and Slave node connectivity on a LIN bus. The LIN (Local Interconnect Network) is a serial communication protocol which efficiently supports the control of mechatronic nodes in distributed automotive applications. The main properties of the LIN bus are: • Single Master/Multiple Slaves concept • Low cost silicon implementation based on common UART/SCI interface hardware, an equivalent in software, or as a pure state machine. • Self synchronization without quartz or ceramic resonator in the slave nodes • Deterministic signal transmission • Low cost single-wire implementation • Speed up to 20 kbit/s LIN provides cost efficient bus communication where the bandwidth and versatility of CAN are not required. The LIN Mode enables processing LIN frames with a minimum of action from the microprocessor. 20.7.7.1 Modes of operation The USART can act either as a LIN Master node or as a LIN Slave node. The node configuration is chosen by setting the MODE field in the USART3 Mode register (MR): • LIN Master Node (MODE=0xA) • LIN Slave Node (MODE=0xB) In order to avoid unpredicted behavior, any change of the LIN node configuration must be followed by a software reset of the transmitter and of the receiver (except the initial node configuration after a hardware reset). (See Section 20.7.7.2 on page 402) 20.7.7.2 Receiver and Transmitter Control See “Receiver and Transmitter Control” on page 382. Character Transmission See “Transmitter Operations” on page 382. Character Reception See “Receiver Operations” on page 385. 20.7.7.3 20.7.7.4 402 32099A–AVR32–06/09 AT32UC3L 20.7.7.5 Header Transmission (Master Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. So in Master node configuration, the frame handling starts with the sending of the header. The header is transmitted as soon as the identifier is written in the LIN Identifier register (LINIR). At this moment the flag TXRDY falls. The Break Field, the Synch Field and the Identifier Field are sent automatically one after the other. The Break Field consists of 13 dominant bits and 1 recessive bit, the Synch Field is the character 0x55 and the Identifier corresponds to the character written in the LIN Identifier Register (LINIR). The Identifier parity bits can be automatically computed and sent (see Section 20.7.7.8 on page 406). The flag TXRDY rises when the identifier character is transferred into the Shift Register of the transmitter. Figure 20-27. Header Transmission Baud Rate Clock TXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit Write LINIR LINIR TXRDY ID 403 32099A–AVR32–06/09 AT32UC3L 20.7.7.6 Header Reception (Slave Node Configuration) All the LIN Frames start with a header which is sent by the master node and consists of a Synch Break Field, Synch Field and Identifier Field. In Slave node configuration, the frame handling starts with the reception of the header. The USART uses a break detection threshold of 11 nominal bit times at the actual baud rate. At any time, if 11 consecutive recessive bits are detected on the bus, the USART detects a Break Field. As long as a Break Field has not been detected, the USART stays idle and the received data are not taken in account. When a Break Field has been detected, the USART expects the Synch Field character to be 0x55. This field is used to update the actual baud rate in order to stay synchronized (see Section 20.7.7.7 on page 404). If the received Synch character is not 0x55, an Inconsistent Synch Field error is generated (see Section 20.7.8 on page 411). After receiving the Synch Field, the USART expects to receive the Identifier Field. When the Identifier has been received, the flag LINID is set to “1”. At this moment the field IDCHR in the LIN Identifier register (LINIR) is updated with the received character. The Identifier parity bits can be automatically computed and checked (see Section 20.7.7.8 on page 406). Figure 20-28. Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 1 0 Stop Stop Start ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit Synch Byte = 0x55 LINID US_LINIR Write US_CR With RSTSTA=1 20.7.7.7 Slave Node Synchronization The synchronization is done only in Slave node configuration. The procedure is based on time measurement between falling edges of the Synch Field. The falling edges are available in distances of 2, 4, 6 and 8 bit times. Figure 20-29. Synch Field Synch Field 8 Tbit 2 Tbit 2 Tbit 2 Tbit 2 Tbit Start bit Stop bit The time measurement is made by a 19-bit counter clocked by the sampling clock (see Section 20.7.1 on page 378). 404 32099A–AVR32–06/09 AT32UC3L When the start bit of the Synch Field is detected the counter is reset. Then during the next 8 Tbits of the Synch Field, the counter is incremented. At the end of these 8 Tbits, the counter is stopped. At this moment, the 16 most significant bits of the counter (value divided by 8) gives the new clock divider (CD) and the 3 least significant bits of this value (the remainder) gives the new fractional part (FP). When the Synch Field has been received, the clock divider (CD) and the fractional part (FP) are updated in the Baud Rate Generator register (BRGR). Figure 20-30. Slave Node Synchronization Baud Rate Clock RXD Break Field 13 dominant bits (at 0) Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 Synch Byte = 0x55 1 0 Stop Start Stop ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit LINIDRX Reset Synchro Counter BRGR Clcok Divider (CD) BRGR Fractional Part (FP) Initial CD Initial FP 000_0011_0001_0110_1101 0000_0110_0010_1101 101 The accuracy of the synchronization depends on several parameters: • The nominal clock frequency (FNom) (the theoretical slave node clock frequency) • The Baudrate • The oversampling (Over=0 => 16X or Over=0 => 8X) The following formula is used to compute the deviation of the slave bit rate relative to the master bit rate after synchronization (FSLAVE is the real slave node clock frequency). [ α × 8 × ( 2 – Over ) + β ] × Baudrate Baudrate_deviation = ⎛ 100 × --------------------------------------------------------------------------------------------⎞ % ⎝ ⎠ 8 × F SLAVE ⎛ ⎞ ⎜ [ α × 8 × ( 2 – Over ) + β ] × Baudrate⎟ Baudrate_deviation = ⎜ 100 × --------------------------------------------------------------------------------------------⎟ % F TOL_UNSYNCH ⎜ ⎟ ⎛ -------------------------------------- ⎞ xF 8× ⎝ ⎠ ⎝ ⎠ Nom 100 – 0.5 ≤ α ≤ +0.5 -1 < β < +1 FTOL_UNSYNCH is the deviation of the real slave node clock from the nominal clock frequency. The LIN Standard imposes that it must not exceed ±15%. The LIN Standard imposes also that for communication between two nodes, their bit rate must not differ by more than ±2%. This means that the Baudrate_deviation must not exceed ±1%. It follows from that, a minimum value for the nominal clock frequency: 405 32099A–AVR32–06/09 AT32UC3L ⎛ ⎞ ⎜ [ 0.5 × 8 × ( 2 – Over ) + 1 ] × Baudrate⎟ F NOM ( min ) = ⎜ 100 × ----------------------------------------------------------------------------------------------- ⎟ Hz – 15 ⎜ ⎟ 8 × ⎛ --------- + 1⎞ × 1% ⎝ ⎠ ⎝ 100 ⎠ Examples: • Baudrate = 20 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 2.64 MHz • Baudrate = 20 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 1.47 MHz • Baudrate = 1 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 132 kHz • Baudrate = 1 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 74 kHz If the fractional baud rate is not used, the accuracy of the synchronization becomes much lower. When the counter is stopped, the 16 most significant bits of the counter (value divided by 8) gives the new clock divider (CD). This value is rounded by adding the first insignificant bit. The equation of the Baudrate deviation is the same as given above, but the constants are as follows: – 4 ≤ α ≤ +4 -1 < β < +1 It follows from that, a minimum value for the nominal clock frequency: ⎛ ⎞ ⎜ [ 4 × 8 × ( 2 – Over ) + 1 ] × Baudrate⎟ F (min) = ⎜ 100 × ------------------------------------------------------------------------------------------ ⎟ Hz NOM – 15 ⎜ ⎟ 8 × ⎛ --------- + 1⎞ × 1% ⎝ ⎠ ⎝ 100 ⎠ Examples: • Baudrate = 20 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 19.12 MHz • Baudrate = 20 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 9.71 MHz • Baudrate = 1 kbit/s, Over=0 (Oversampling 16X) => FNom(min) = 956 kHz • Baudrate = 1 kbit/s, Over=1 (Oversampling 8X) => FNom(min) = 485 kHz 20.7.7.8 Identifier Parity A protected identifier consists of two sub-fields; the identifier and the identifier parity. Bits 0 to 5 are assigned to the identifier and bits 6 and 7 are assigned to the parity. The USART interface can generate/check these parity bits, but this feature can also be disabled. The user can choose between two modes by the PARDIS bit of the LIN Mode register (LINMR): • PARDIS = 0: During header transmission, the parity bits are computed and sent with the 6 least significant bits of the IDCHR field of the LIN Identifier register (LINIR). The bits 6 and 7 of this register are discarded. During header reception, the parity bits of the identifier are checked. If the parity bits are wrong, an Identifier Parity error occurs (see Section 20.7.3.5 on page 386). Only the 6 least significant bits of the IDCHR field are updated with the received Identifier. The bits 6 and 7 are stuck at 0. • PARDIS = 1: During header transmission, all the bits of the IDCHR field of the LIN Identifier register (LINIR) are sent on the bus. During header reception, all the bits of the IDCHR field are updated with the received Identifier. 406 32099A–AVR32–06/09 AT32UC3L 20.7.7.9 Node Action In function of the identifier, the node is concerned, or not, by the LIN response. Consequently, after sending or receiving the identifier, the USART must be configured. There are three possible configurations: • PUBLISH: the node sends the response. • SUBSCRIBE: the node receives the response. • IGNORE: the node is not concerned by the response, it does not send and does not receive the response. This configuration is made by the field, Node Action (NACT), in the LINMR register (see Section 20.8.14 on page 441). Example: a LIN cluster that contains a Master and two Slaves: • Data transfer from the Master to the Slave 1 and to the Slave 2: NACT(Master)=PUBLISH NACT(Slave1)=SUBSCRIBE NACT(Slave2)=SUBSCRIBE • Data transfer from the Master to the Slave 1 only: NACT(Master)=PUBLISH NACT(Slave1)=SUBSCRIBE NACT(Slave2)=IGNORE • Data transfer from the Slave 1 to the Master: NACT(Master)=SUBSCRIBE NACT(Slave1)=PUBLISH NACT(Slave2)=IGNORE • Data transfer from the Slave1 to the Slave2: NACT(Master)=IGNORE NACT(Slave1)=PUBLISH NACT(Slave2)=SUBSCRIBE • Data transfer from the Slave2 to the Master and to the Slave1: NACT(Master)=SUBSCRIBE NACT(Slave1)=SUBSCRIBE NACT(Slave2)=PUBLISH 407 32099A–AVR32–06/09 AT32UC3L 20.7.7.10 Response Data Length The LIN response data length is the number of data fields (bytes) of the response excluding the checksum. The response data length can either be configured by the user or be defined automatically by bits 4 and 5 of the Identifier (compatibility to LIN Specification 1.1). The user can choose between these two modes by the DLM bit of the LIN Mode register (LINMR): • DLM = 0: the response data length is configured by the user via the DLC field of the LIN Mode register (LINMR). The response data length is equal to (DLC + 1) bytes. DLC can be programmed from 0 to 255, so the response can contain from 1 data byte up to 256 data bytes. • DLM = 1: the response data length is defined by the Identifier (IDCHR in LINIR) according to the table below. The DLC field of the LIN Mode register (LINMR) is discarded. The response can contain 2 or 4 or 8 data bytes. Table 20-11. Response Data Length if DLM = 1 IDCHR[5] 0 0 1 1 IDCHR[4] 0 1 0 1 Response Data Length [bytes] 2 2 4 8 Figure 20-31. Response Data Length User configuration: 1 - 256 data fields (DLC+1) Identifier configuration: 2/4/8 data fields Sync Break Sync Field Identifier Field Data Field Data Field Data Field Data Field Checksum Field 408 32099A–AVR32–06/09 AT32UC3L 20.7.7.11 Checksum The last field of a frame is the checksum. The checksum contains the inverted 8- bit sum with carry, over all data bytes or all data bytes and the protected identifier. Checksum calculation over the data bytes only is called classic checksum and it is used for communication with LIN 1.3 slaves. Checksum calculation over the data bytes and the protected identifier byte is called enhanced checksum and it is used for communication with LIN 2.0 slaves. The USART can be configured to: • Send/Check an Enhanced checksum automatically (CHKDIS = 0 & CHKTYP = 0) • Send/Check a Classic checksum automatically (CHKDIS = 0 & CHKTYP = 1) • Not send/check a checksum (CHKDIS = 1) This configuration is made by the Checksum Type (CHKTYP) and Checksum Disable (CHKDIS) fields of the LIN Mode register (LINMR). If the checksum feature is disabled, the user can send it manually all the same, by considering the checksum as a normal data byte and by adding 1 to the response data length (see Section 20.7.7.10 on page 408). 409 32099A–AVR32–06/09 AT32UC3L 20.7.7.12 Frame Slot Mode This mode is useful only for Master nodes. It respects the following rule: each frame slot shall be longer than or equal to TFrame_Maximum. If the Frame Slot Mode is enabled (FSDIS = 0) and a frame transfer has been completed, the TXRDY flag is set again only after TFrame_Maximum delay, from the start of frame. So the Master node cannot send a new header if the frame slot duration of the previous frame is inferior to TFrame_Maximum. If the Frame Slot Mode is disabled (FDIS = 1) and a frame transfer has been completed, the TXRDY flag is set again immediately. The TFrame_Maximum is calculated as below: If the Checksum is sent (CHKDIS = 0): • THeader_Nominal = 34 x TBit • TResponse_Nominal = 10 x (NData + 1) x TBit • TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1)(Note:) • TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1 + 1) + 1) x TBIT • TFrame_Maximum = (77 + 14 x DLC) x TBIT If the Checksum is not sent (CHKDIS = 1): • THeader_Nominal = 34 x TBit • TResponse_Nominal = 10 x NData x TBit • TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1(Note:)) • TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1) + 1) x TBIT • TFrame_Maximum = (63 + 14 x DLC) x TBIT Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specification 1.3) Figure 20-32. Frame Slot Mode Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY Frame Slot Mode Frame Slot Mode Disabled Enabled Write LINID Write THR LINTC Data 1 Data 2 Data 3 Data N 410 32099A–AVR32–06/09 AT32UC3L 20.7.8 20.7.8.1 LIN Errors Bit Error This error is generated when the USART is transmitting and if the transmitted value on the Tx line is different from the value sampled on the Rx line. If a bit error is detected, the transmission is aborted at the next byte border. 20.7.8.2 Inconsistent Synch Field Error This error is generated in Slave node configuration if the Synch Field character received is other than 0x55. Parity Error This error is generated if the parity of the identifier is wrong. This error can be generated only if the parity feature is enabled (PARDIS = 0). 20.7.8.4 Checksum Error This error is set if the received checksum is wrong. This error can be generated only if the checksum feature is enabled (CHKDIS = 0). Slave Not Responding Error This error is set when the USART expects a response from another node (NACT = SUBSCRIBE) but no valid message appears on the bus within the time frame given by the maximum length of the message frame, TFrame_Maximum (see Section 20.7.7.12 on page 410). This error is disabled if the USART does not expect any message (NACT = PUBLISH or NACT = IGNORE). 20.7.8.3 20.7.8.5 411 32099A–AVR32–06/09 AT32UC3L 20.7.9 20.7.9.1 LIN Frame Handling Master Node Configuration • Write TXEN and RXEN in CR to enable both the transmitter and the receiver. • Write MODE in MR to select the LIN mode and the Master Node configuration. • Write CD and FP in BRGR to configure the baud rate. • Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM, FDIS and DLC in LINMR to configure the frame transfer. • Check that TXRDY in CSR is set to “1” • Write IDCHR in LINIR to send the header What comes next depends on the NACT configuration: • Case 1: NACT = PUBLISH, the USART sends the response – Wait until TXRDY in CSR rises – Write TCHR in THR to send a byte – If all the data have not been written, redo the two previous steps – Wait until LINTC in CSR rises – Check the LIN errors • Case 2: NACT = SUBSCRIBE, the USART receives the response – Wait until RXRDY in CSR rises – Read RCHR in RHR – If all the data have not been read, redo the two previous steps – Wait until LINTC in CSR rises – Check the LIN errors • Case 3: NACT = IGNORE, the USART is not concerned by the response – Wait until LINTC in CSR rises – Check the LIN errors 412 32099A–AVR32–06/09 AT32UC3L Figure 20-33. Master Node Configuration, NACT = PUBLISH Frame slot = TFrame_Maximum Frame Header Data3 Response space Interframe space Response Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 RXRDY Write LINIR Write THR LINTC Data 1 Data 2 Data 3 Data N FSDIS=0 Figure 20-34. Master Node Configuration, NACT=SUBSCRIBE Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR Read RHR LINTC Data 1 Data N-2 Data N-1 Data N 413 32099A–AVR32–06/09 AT32UC3L Figure 20-35. Master Node Configuration, NACT=IGNORE Frame slot = TFrame_Maximum Frame Response space Interframe space Response Header Data3 Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 RXRDY Write LINIR LINTC FSDIS=0 20.7.9.2 Slave Node Configuration • Write TXEN and RXEN in CR to enable both the transmitter and the receiver. • Write MODE in MR to select the LIN mode and the Slave Node configuration. • Write CD and FP in BRGR to configure the baud rate. • Wait until LINID in CSR rises • Check LINISFE and LINPE errors • Read IDCHR in RHR • Write NACT, PARDIS, CHKDIS, CHKTYPE, DLCM and DLC in LINMR to configure the frame transfer. IMPORTANT: if the NACT configuration for this frame is PUBLISH, the US_LINMR register, must be write with NACT=PUBLISH even if this field is already correctly configured, that in order to set the TXREADY flag and the corresponding PDC write transfer request. What comes next depends on the NACT configuration: • Case 1: NACT = PUBLISH, the USART sends the response – Wait until TXRDY in CSR rises – Write TCHR in THR to send a byte – If all the data have not been written, redo the two previous steps – Wait until LINTC in CSR rises – Check the LIN errors • Case 2: NACT = SUBSCRIBE, the USART receives the response – Wait until RXRDY in CSR rises – Read RCHR in RHR – If all the data have not been read, redo the two previous steps – Wait until LINTC in CSR rises – Check the LIN errors 414 32099A–AVR32–06/09 AT32UC3L • Case 3: NACT = IGNORE, the USART is not concerned by the response – Wait until LINTC in CSR rises – Check the LIN errors Figure 20-36. Slave Node Configuration, NACT = PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read LINID Write THR LINTC Data 1 Data 2 Data 3 Data N Figure 20-37. Slave Node Configuration, NACT = SUBSCRIBE Break TXRDY RXRDY LINIDRX Read LINID Read RHR LINTC Data 1 Data N-2 Data N-1 Data N Synch Protected Identifier Data 1 Data N-1 Data N Checksum Figure 20-38. Slave Node Configuration, NACT = IGNORE Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum TXRDY RXRDY LINIDRX Read LINID Read RHR LINTC 415 32099A–AVR32–06/09 AT32UC3L 20.7.10 LIN Frame Handling With The Peripheral DMA Controller The USART can be used in association with the Peripheral DMA Controller (PDCA) in order to transfer data directly into/from the on- and off-chip memories without any processor intervention. The PDCA uses the trigger flags, TXRDY and RXRDY, to write or read into the USART. The PDCA always writes in the Transmit Holding register (THR) and it always reads in the Receive Holding register (RHR). The size of the data written or read by the PDCA in the USART is always a byte. 20.7.10.1 Master Node Configuration The user can choose between two PDCA modes by the PDCM bit in the LIN Mode register (LINMR): • PDCM = 1: the LIN configuration is stored in the WRITE buffer and it is written by the PDCA in the Transmit Holding register THR (instead of the LIN Mode register LINMR). Because the PDCA transfer size is limited to a byte, the transfer is split into two accesses. During the first access the bits, NACT, PARDIS, CHKDIS, CHKTYP, DLM and FDIS are written. During the second access the 8-bit DLC field is written. • PDCM = 0: the LIN configuration is not stored in the WRITE buffer and it must be written by the user in the LIN Mode register (LINMR). The WRITE buffer also contains the Identifier and the DATA, if the USART sends the response (NACT = PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT = SUBSCRIBE). Figure 20-39. Master Node with PDCA (PDCM=1) WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS WRITE BUFFER NACT PARDIS CHKDIS CHKTYP DLM FSDIS DLC DLC NODE ACTION = PUBLISH Peripheral bus PDCA (DMA) DATA 0 RXRDY DATA 0 TXRDY USART3 LIN CONTROLLER IDENTIFIER Peripheral bus PDCA (DMA) USART3 LIN CONTROLLER NODE ACTION = SUBSCRIBE IDENTIFIER READ BUFFER RXRDY | | | | | | | | DATA N DATA N 416 32099A–AVR32–06/09 AT32UC3L Figure 20-40. Master Node with PDCA (PDCM=0) WRITE BUFFER WRITE BUFFER IDENTIFIER NODE ACTION = PUBLISH IDENTIFIER NODE ACTION = SUBSCRIBE Peripheral bus READ BUFFER PDCA (DMA) PDCA (DMA) USART3 LIN CONTROLLER DATA 0 Peripheral bus | | | | USART3 LIN CONTROLLER RXRDY DATA 0 RXRDY TXRDY DATA N | | | | DATA N 20.7.10.2 Slave Node Configuration In this configuration, the PDCA transfers only the DATA. The Identifier must be read by the user in the LIN Identifier register (LINIR). The LIN mode must be written by the user in the LIN Mode register (LINMR). The WRITE buffer contains the DATA if the USART sends the response (NACT=PUBLISH). The READ buffer contains the DATA if the USART receives the response (NACT=SUBSCRIBE). IMPORTANT: if the NACT configuration for a frame is PUBLISH, the US_LINMR register, must be write with NACT=PUBLISH even if this field is already correctly configured, that in order to set the TXREADY flag and the corresponding PDC write transfer request. Figure 20-41. Slave Node with PDCA WRITE BUFFER READ BUFFER DATA 0 Peripheral bus PDCA (DMA) TXRDY USART3 LIN CONTROLLER DATA 0 Peripheral Bus | | | | NACT = SUBSCRIBE | | | | PDCA (DMA) RXRDY USART3 LIN CONTROLLER DATA N DATA N 417 32099A–AVR32–06/09 AT32UC3L 20.7.11 Wake-up Request Any node in a sleeping LIN cluster may request a wake-up. In the LIN 2.0 specification, the wakeup request is issued by forcing the bus to the dominant state from 250 µs to 5 ms. For this, it is necessary to send the character 0xF0 in order to impose 5 successive dominant bits. Whatever the baud rate is, this character respects the specified timings. • Baud rate min = 1 kbit/s -> Tbit = 1ms -> 5 Tbits = 5 ms • Baud rate max = 20 kbit/s -> Tbi t= 50 µs -> 5 Tbits = 250 µs In the LIN 1.3 specification, the wakeup request should be generated with the character 0x80 in order to impose 8 successive dominant bits. The user can choose by the WKUPTYP bit in the LIN Mode register (LINMR) either to send a LIN 2.0 wakeup request (WKUPTYP=0) or to send a LIN 1.3 wakeup request (WKUPTYP=1). A wake-up request is transmitted by writing the Control Register (CR) with the LINWKUP bit at 1. Once the transfer is completed, the LINTC flag is asserted in the Status Register (SR). It is cleared by writing the Control Register (CR) with the RSTSTA bit at 1. 418 32099A–AVR32–06/09 AT32UC3L 20.7.12 Bus Idle Time-out If the LIN bus is inactive for a certain duration, the slave nodes shall automatically enter in sleep mode. In the LIN 2.0 specification, this time-out is fixed at 4 seconds. In the LIN 1.3 specification, it is fixed at 25000 Tbits. In Slave Node configuration, the Receiver Time-out detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (CSR) rises and can generate an interrupt, thus indicating to the driver to go into sleep mode. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in CSR remains at 0. Otherwise, the receiver loads a 17-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. If STTTO is performed, the counter clock is stopped until a first character is received. If RETTO is performed, the counter starts counting down immediately from the value TO. Table 20-12. Receiver Time-out programming LIN Specification Baud Rate 1 000 bit/s 2 400 bit/s 2.0 9 600 bit/s 19 200 bit/s 20 000 bit/s 1.3 25 000 Tbits 4s Time-out period TO 4 000 9 600 38 400 76 800 80 000 25 000 419 32099A–AVR32–06/09 AT32UC3L 20.7.13 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 20.7.13.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 20-42. Normal Mode Configuration RXD Receiver TXD Transmitter 20.7.13.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 20-43 on page 420. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 20-43. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 20.7.13.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 20-44 on page 420. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 20-44. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD 420 32099A–AVR32–06/09 AT32UC3L 20.7.13.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 20-45 on page 421. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 20-45. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 421 32099A–AVR32–06/09 AT32UC3L 20.7.14 Write Protection Registers To prevent any single software error that may corrupt USART behavior, certain address spaces can be write-protected by setting the WPEN bit in the USART Write Protect Mode Register (WPMR). If a write access to the protected registers is detected, then the WPVS flag in the USART Write Protect Status Register (WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted. The WPVS flag is reset by writing the USART Write Protect Mode Register (WPMR) with the appropriate access key, WPKEY. The protected registers are: • “Mode Register” on page 426 • “Baud Rate Generator Register” on page 436 • “Receiver Time-out Register” on page 437 • “Transmitter Timeguard Register” on page 438 • “FI DI RATIO Register” on page 439 • “This register can only be written if the WPEN bit is cleared in “Write Protect Mode Register” on page 444.” on page 441 422 32099A–AVR32–06/09 AT32UC3L 20.8 User Interface Table 20-13. USART Register Memory Map Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x0040 0x0044 0x0054 0x0058 0xE4 0xE8 0xFC Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register FI DI Ratio Register Number of Errors Register LIN Mode Register LIN Identifier Register Write Protect Mode Register Write Protect Status Register Version Register Note: Note: Name CR MR IER IDR IMR CSR RHR THR BRGR RTOR TTGR FIDI NER LINMR LINIR WPMR WPSR VERSION Write is possible only in LIN Master node configuration. Values in the Version Register vary with the version of the IP block implementation. Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write Read-write Read-write Read-write Read-only Read-write Read-write (Note:) Reset – 0x00000000 – – 0x00000000 0x00000000 0x00000000 – 0x00000000 0x00000000 0x00000000 0x00000174 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x–(Note:) Read-write Read-only Read-only 423 32099A–AVR32–06/09 AT32UC3L 20.8.1 Name: Control Register CR Write-only 0x0 30 – 22 – 14 RSTNACK 6 TXEN 29 – 21 LINWKUP 13 RSTIT 5 RXDIS 28 – 20 LINABT 12 SENDA 4 RXEN 27 – 19 RTSDIS/RCS 11 STTTO 3 RSTTX 26 – 18 RTSEN/FCS 10 STPBRK 2 RSTRX 25 – 17 – 9 STTBRK 1 – 24 – 16 – 8 RSTSTA 0 – Access Type: Offset: Reset Value: 31 – 23 – 15 RETTO 7 TXDIS • LINWKUP: Send LIN Wakeup Signal 0: No effect: 1: Sends a wakeup signal on the LIN bus. LINABT: Abort LIN Transmission 0: No effect. 1: Abort the current LIN transmission. RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select If USART does not operate in SPI Master Mode (MODE … 0xE): 0: No effect. 1: Drives the pin RTS to 1. If USART operates in SPI Master Mode (MODE = 0xE): RCS = 0: No effect. RCS = 1: Releases the Slave Select Line NSS (RTS pin). RTSEN/FCS: Request to Send Enable/Force SPI Chip Select If USART does not operate in SPI Master Mode (MODE … 0xE): 0: No effect. 1: Drives the pin RTS to 0. If USART operates in SPI Master Mode (MODE = 0xE): FCS = 0: No effect. FCS = 1: Forces the Slave Select Line NSS (RTS pin) to 0, even if USART is no transmitting, in order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer). RETTO: Rearm Time-out 0: No effect 1: Restart Time-out RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in CSR. RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in CSR. No effect if the ISO7816 is not enabled. • • • • • • 424 32099A–AVR32–06/09 AT32UC3L • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the THR is sent with the address bit set. STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in CSR. STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, LINBE, LINSFE, LINIPE, LINCE, LINSNRE and RXBRK in CSR. TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • • • • • • • • • • 425 32099A–AVR32–06/09 AT32UC3L 20.8.2 Name: Mode Register MR Read-write 0x4 30 – 22 – 14 CHMODE 7 CHRL 6 5 USCLKS 29 – 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 – 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Access Type: Offset: Reset Value: 31 – 23 – 15 18 CLKO 10 PAR 2 MODE 16 MSBF/CPOL 8 SYNC/CPHA 0 1 This register can only be written if the WPEN bit is cleared in “Write Protect Mode Register” on page 444. • FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. CLKO: Clock Output Select 0: The USART does not drive the CLK pin. 1: The USART drives the CLK pin if USCLKS does not select the external clock CLK. MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. MSBF/CPOL: Bit Order or SPI Clock Polarity If USART does not operate in SPI Mode (MODE … 0xE and 0xF): MSBF = 0: Least Significant Bit is sent/received first. MSBF = 1: Most Significant Bit is sent/received first. If USART operates in SPI Mode (Slave or Master, MODE = 0xE or 0xF): CPOL = 0: The inactive state value of SPCK is logic level zero. • • • • • • • 426 32099A–AVR32–06/09 AT32UC3L CPOL = 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with CPHA to produce the required clock/data relationship between master and slave devices. • CHMODE: Channel Mode Table 20-14. CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • NBSTOP: Number of Stop Bits Table 20-15. NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved • PAR: Parity Type Table 20-16. PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode • SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase If USART does not operate in SPI Mode (MODE is … 0xE and 0xF): SYNC = 0: USART operates in Asynchronous Mode. SYNC = 1: USART operates in Synchronous Mode. If USART operates in SPI Mode (MODE = 0xE or 0xF): CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. 427 32099A–AVR32–06/09 AT32UC3L • CHRL: Character Length. Table 20-17. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits • USCLKS: Clock Selection Table 20-18. USCLKS 0 0 1 1 0 1 0 1 Selected Clock CLK_USART CLK_USART/DIV (DIV = 8) Reserved CLK • MODE Table 20-19. MODE 0 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 Others 0 0 1 0 1 1 1 1 1 0 1 0 0 0 0 1 0 1 Mode of the USART Normal RS485 Hardware Handshaking IS07816 Protocol: T = 0 IS07816 Protocol: T = 1 LIN Master LIN Slave SPI Master SPI Slave Reserved 20.8.3 Name: Interrupt Enable Register IER Write-only 0x8 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – Access Type: Offset: Reset Value: 31 – 428 32099A–AVR32–06/09 AT32UC3L 23 – 15 LINTC 7 PARE 22 – 14 LINiD 6 FRAME 21 – 13 NACK/LINBK 5 OVRE 20 – 12 RXBUFF 4 – 19 CTSIC 11 – 3 – 18 – 10 ITER/UNRE 2 RXBRK 17 – 9 TXEMPTY 1 TXRDY 16 – 8 TIMEOUT 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 429 32099A–AVR32–06/09 AT32UC3L 20.8.4 Name: Interrupt Disable Register IDR Write-only 0xC 30 – 22 – 14 LINID 6 FRAME 29 LINSNRE 21 – 13 NACK/LINBK 5 OVRE 28 LINCE 20 – 12 RXBUFF 4 – 27 LINIPE 19 CTSIC 11 – 3 – 26 LINISFE 18 – 10 ITER/UNRE 2 RXBRK 25 LINBE 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 – 23 – 15 LINTC 7 PARE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 430 32099A–AVR32–06/09 AT32UC3L 20.8.5 Name: Interrupt Mask Register IMR Read-only 0x10 30 – 22 – 14 LINID 6 FRAME 29 LINSNRE 21 – 13 NACK/LINBK 5 OVRE 28 LINCE 20 – 12 RXBUFF 4 – 27 LINIPE 19 CTSIC 11 – 3 – 26 LINISFE 18 – 10 ITER/UNRE 2 RXBRK 25 LINBE 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 – 23 – 15 LINTC 7 PARE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is cleared when the corresponding bit in IER is written to one. 20.8.6 Name: Channel Status Register CSR Read-only 0x14 30 – 22 – 14 LINID 6 FRAME 29 LINSNRE 21 – 13 NACK/LINBK 5 OVRE 28 LINCE 20 – 12 RXBUFF 4 – 27 LINIPE 19 CTSIC 11 – 3 – 26 LINISFE 18 – 10 ITER/UNRE 2 RXBRK 25 LINBE 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY Access Type: Offset: Reset Value: 31 – 23 CTS 15 LINTC 7 PARE • LINSNRE: LIN Slave Not Responding Error 0: No LIN Slave Not Responding Error has been detected since the last RSTSTA. 1: A LIN Slave Not Responding Error has been detected since the last RSTSTA. 431 32099A–AVR32–06/09 AT32UC3L • LINCE: LIN Checksum Error 0: No LIN Checksum Error has been detected since the last RSTSTA. 1: A LIN Checksum Error has been detected since the last RSTSTA. LINIPE: LIN Identifier Parity Error 0: No LIN Identifier Parity Error has been detected since the last RSTSTA. 1: A LIN Identifier Parity Error has been detected since the last RSTSTA. LINISFE: LIN Inconsistent Synch Field Error 0: No LIN Inconsistent Synch Field Error has been detected since the last RSTSTA 1: The USART is configured as a Slave node and a LIN Inconsistent Synch Field Error has been detected since the last RSTSTA. LINBE: LIN Bit Error 0: No Bit Error has been detected since the last RSTSTA. 1: A Bit Error has been detected since the last RSTSTA. CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of CSR. 1: At least one input change has been detected on the CTS pin since the last read of CSR. LINTC: LIN Transfer Completed 0: The USART is idle or a LIN transfer is ongoing. 1: A LIN transfer has been completed since the last RSTSTA. LINIR: LIN Identifier Received 0: No LIN Identifier Received 1: The USART is configured as a Slave node and a LIN Identifier has been received since the last RSTSTA. NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDCA channel is inactive. 1: The signal Buffer Full from the Receive PDCA channel is active. ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error If USART does not operate in SPI Slave Mode (MODE … 0xF): ITER = 0: Maximum number of repetitions has not been reached since the last RSTSTA. ITER = 1: Maximum number of repetitions has been reached since the last RSTSTA. If USART operates in SPI Slave Mode (MODE = 0xF): UNRE = 0: No SPI underrun error has occurred since the last RSTSTA. UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA. TXEMPTY: Transmitter Empty 0: There are characters in either THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in THR, nor in the Transmit Shift Register. TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in CR). PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • • • • • • • • • • • • • • 432 32099A–AVR32–06/09 AT32UC3L • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. • TXRDY: Transmitter Ready 0: A character is in the THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the THR. • RXRDY: Receiver Ready 0: No complete character has been received since the last read of RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and RHR has not yet been read. 433 32099A–AVR32–06/09 AT32UC3L 20.8.7 Name: Receive Holding Register RHR Read-only 0x18 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 RXCHR 0 Access Type: Offset: Reset Value: 31 – 23 – 15 RXSYNH 7 • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. • RXCHR: Received Character Last character received if RXRDY is set. 434 32099A–AVR32–06/09 AT32UC3L 20.8.8 Name: USART Transmit Holding Register THR Write-only 0x1C 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 TXCHR 0 Access Type: Offset: Reset Value: 31 – 23 – 15 TXSYNH 7 • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 435 32099A–AVR32–06/09 AT32UC3L 20.8.9 Name: Baud Rate Generator Register BRGR Read-write 0x20 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CD 7 6 5 4 CD 3 2 1 0 27 – 19 – 11 26 – 18 25 – 17 FP– 9 24 – 16 Access Type: Offset: Reset Value: 31 – 23 – 15 10 8 This register can only be written if the WPEN bit is cleared in “Write Protect Mode Register” on page 444. • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. • CD: Clock Divider Table 20-20. MODE ≠ ISO7816 SYNC = 1 or MODE = SPI (Master or Slave) OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/16/CD Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO MODE = ISO7816 SYNC = 0 CD 0 1 to 65535 OVER = 0 436 32099A–AVR32–06/09 AT32UC3L 20.8.10 Name: Receiver Time-out Register RTOR Read-write 0x24 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 TO 7 6 5 4 TO 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 TO 8 Access Type: Offset: Reset Value: 31 – 23 – 15 This register can only be written if the WPEN bit is cleared in “Write Protect Mode Register” on page 444. • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 131071: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. Note that the size of the TO counter can change depending of implementation. See the Module Configuration section. 437 32099A–AVR32–06/09 AT32UC3L 20.8.11 Name: Transmitter Timeguard Register TTGR Read-write 0x28 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TG 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 This register can only be written if the WPEN bit is cleared in “Write Protect Mode Register” on page 444. • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 438 32099A–AVR32–06/09 AT32UC3L 20.8.12 Name: FI DI RATIO Register FIDI Read-write 0x40 0x00000174 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FI_DI_RATIO 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 – 9 FI_DI_RATIO 1 24 – 16 – 8 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 2 0 This register can only be written if the WPEN bit is cleared in “Write Protect Mode Register” on page 444. • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on CLK divided by FI_DI_RATIO. 439 32099A–AVR32–06/09 AT32UC3L 20.8.13 Name: Number of Errors Register NER Read-only 0x44 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 NB_ERRORS 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 440 32099A–AVR32–06/09 AT32UC3L This register can only be written if the WPEN bit is cleared in “Write Protect Mode Register” on page 444. 20.8.14 Name: LIN Mode Register LINMR Read-write 0x54 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 DLC 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 PDCM 8 Access Type: Offset: Reset Value: 31 – 23 – 15 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 3 CHKDIS 2 PARDIS 1 NACT 0 • PDCM: PDCA Mode 0: The LIN mode register LINMR is not written by the PDCA. 1: The LIN mode register LINMR (excepting that flag) is written by the PDCA. DLC: Data Length Control 0 - 255: Defines the response data length if DLM=0,in that case the response data length is equal to DLC+1 bytes. WKUPTYP: Wakeup Signal Type 0: setting the bit LINWKUP in the control register sends a LIN 2.0 wakeup signal. 1: setting the bit LINWKUP in the control register sends a LIN 1.3 wakeup signal. FDIS: Frame Slot Mode Disable 0: The Frame Slot Mode is enabled. 1: The Frame Slot Mode is disabled. DLM: Data Length Mode 0: The response data length is defined by the field DLC of this register. 1: The response data length is defined by the bits 5 and 6 of the Identifier (IDCHR in LINIR). CHKTYP: Checksum Type 0: LIN 2.0 “Enhanced” Checksum 1: LIN 1.3 “Classic” Checksum CHKDIS: Checksum Disable 0: In Master node configuration, the checksum is computed and sent automatically. In Slave node configuration, the checksum is checked automatically. 1: Whatever the node configuration is, the checksum is not computed/sent and it is not checked. PARDIS: Parity Disable 0: In Master node configuration, the Identifier Parity is computed and sent automatically. In Master node and Slave node configuration, the parity is checked automatically. 1:Whatever the node configuration is, the Identifier parity is not computed/sent and it is not checked. • • • • • • • 441 32099A–AVR32–06/09 AT32UC3L • NACT: LIN Node Action Table 1. NACT 0 0 1 1 0 1 0 1 Mode Description PUBLISH: The USART transmits the response. SUBSCRIBE: The USART receives the response. IGNORE: The USART does not transmit and does not receive the response. Reserved 442 32099A–AVR32–06/09 AT32UC3L 20.8.15 Name: LIN Identifier Register LINIR Read-write or Read-only 0x58 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IDCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 • IDCHR: Identifier Character If MODE=0xA (Master node configuration): IDCHR is Read-write and its value is the Identifier character to be transmitted. if MODE=0xB (Slave node configuration): IDCHR is Read-only and its value is the last Identifier character that has been received. 443 32099A–AVR32–06/09 AT32UC3L 20.8.16 Write Protect Mode Register Register Name: WPMR Access Type: Offset: Reset Value: 31 Read-write 0xE4 See Table 20-13 on page 423 30 29 28 WPKEY 27 26 25 24 23 22 21 20 WPKEY 19 18 17 16 15 14 13 12 WPKEY 11 10 9 8 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 WPEN • WPKEY: Write Protect KEY Should be written at value 0x858365 ("USA" in ASCII). Writing any other value in this field aborts the write operation of the WPEN bit. Always reads as 0. • WPEN: Write Protect Enable 0 = Disables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ASCII). 1 = Enables the Write Protect if WPKEY corresponds to 0x858365 ("USA" in ASCII). Protects the registers: • “Mode Register” on page 426 • “Baud Rate Generator Register” on page 436 • “Receiver Time-out Register” on page 437 • “Transmitter Timeguard Register” on page 438 • “FI DI RATIO Register” on page 439 • “This register can only be written if the WPEN bit is cleared in “Write Protect Mode Register” on page 444.” on page 441 • “Manchester Configuration Register” on page 91 444 32099A–AVR32–06/09 AT32UC3L 20.8.17 Write Protect Status Register Register Name: WPSR Access Type: Offset: Reset Value: 31 — 23 Read-only 0xE8 See Table 20-13 on page 423 30 — 22 29 — 21 28 — 20 WPVSRC 27 — 19 26 — 18 25 — 17 24 — 16 15 14 13 12 WPVSRC 11 10 9 8 7 — 6 — 5 — 4 — 3 — 2 — 1 — 0 WPVS • WPVSRC: Write Protect Violation Source When WPVS is active, this field indicates the write-protected register (through address offset or code) in which a write access has been attempted. • WPVS: Write Protect Violation Status 0 = No Write Protect Violation has occurred since the last read of the WPSR register. 1 = A Write Protect Violation has occurred since the last read of the WPSR register. If this violation is an unauthorized attempt to write a protected register, the associated violation is reported into field WPVSRC. Note: Reading WPSR automatically clears all fields. 445 32099A–AVR32–06/09 AT32UC3L 20.8.18 Name: Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 Version Register VERSION Read-only 0xFC 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 VERSION 27 – 19 26 – 18 VARIANT 11 10 VERSION 3 2 1 0 9 8 25 – 17 24 – 16 • VARIANT Reserved. No functionality associated. • VERSION Version of the module. No functionality associated. 446 32099A–AVR32–06/09 AT32UC3L 20.9 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 20-21. Module Configuration Feature SPI Logic LIN Logic Manchester Logic Modem Logic IRDA Logic Fractional Baudrate ISO7816 USART0 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented USART1 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented USART2 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented USART3 Implemented Implemented Not Implemented Not Implemented Not Implemented Implemented Not Implemented Table 20-22. Module Clock Name Module Name USART0 USART1 USART2 USART3 Clock Name CLK_USART0 CLK_USART1 CLK_USART2 CLK_USART3 20.9.1 Clock Connections Each USART can be connected to an internally divided clock: Table 20-23. USART Clock Connections USART 0 1 2 3 Source Internal Name CLK_DIV Connection PBA Clock / 8 20.9.2 Register Reset Values Table 20-24. Register VERSION Reset Value 0x00000440 447 32099A–AVR32–06/09 AT32UC3L 21. Serial Peripheral Interface (SPI) Rev. 2.1.1.1 21.1 Features • Compatible with an embedded 32-bit microcontroller • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors – External co-processors • Master or Slave Serial Peripheral Bus Interface – 4 - to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Connection to Peripheral DMA Controller channel capabilities optimizes data transfers – One channel for the receiver, one channel for the transmitter – Next buffer support – Four character FIFO in reception 21.2 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): this data line supplies the output data from the master shifted into the input(s) of the slave(s). • Master In Slave Out (MISO): this data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. • Serial Clock (SPCK): this control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. • Slave Select (NSS): this control line allows slaves to be turned on and off by hardware. 448 32099A–AVR32–06/09 AT32UC3L 21.3 Block Diagram Figure 21-1. SPI Block Diagram Peripheral DMA Controller Peripheral Bus SPCK MISO CLK_SPI Spi Interface I/O Controller MOSI NPCS0/NSS NPCS1 NPCS2 NPCS3 SPI Interrupt Interrupt Control 21.4 Application Block Diagram Figure 21-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI Spi Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO MOSI NSS Slave 1 SPCK MISO MOSI NSS Slave 0 SPCK MISO MOSI NSS Slave 2 449 32099A–AVR32–06/09 AT32UC3L 21.5 I/O Lines Description Table 21-1. I/O Lines Description Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input 21.6 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 21.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. The user must first configure the I/O Controller to assign the SPI pins to their peripheral functions. 21.6.2 Clocks The clock for the SPI bus interface (CLK_SPI) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the SPI before disabling the clock, to avoid freezing the SPI in an undefined state. 21.6.3 Interrupts The SPI interrupt request line is connected to the interrupt controller. Using the SPI interrupt requires the interrupt controller to be programmed first. 21.7 21.7.1 Functional Description Modes of Operation The SPI operates in master mode or in slave mode. Operation in master mode is configured by writing a one to the Master/Slave Mode bit in the Mode Register (MR.MSTR). The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MR.MSTR bit is written to zero, the SPI operates in slave mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in master mode. 450 32099A–AVR32–06/09 AT32UC3L 21.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled. Each of the two bits has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 21-2 on page 451 shows the four modes and corresponding parameter settings. Table 21-2. SPI modes SPI Mode 0 1 2 3 CPOL 0 0 1 1 NCPHA 1 0 1 0 Figure 21-3 on page 451 and Figure 21-4 on page 452 show examples of data transfers. Figure 21-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB *** NSS (to slave) *** Not Defined, but normaly MSB of previous character received 451 32099A–AVR32–06/09 AT32UC3L Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) *** MSB 6 5 4 3 2 1 LSB NSS (to slave) *** Not Defined, but normaly LSB of previous character transmitted 21.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register (TDR) and the Receive Data Register (RDR), and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the TDR register. The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing to the TDR, the Peripheral Chip Select field in TDR (TDR.PCS) must be written in order to select a slave. If new data is written to TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to RDR, the data in TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in TDR in the Shift Register is indicated by the Transmit Data Register Empty bit in the Status Register (SR.TDRE). When new data is written in TDR, this bit is cleared. The SR.TDRE bit is used to trigger the Transmit Peripheral DMA Controller channel. The end of transfer is indicated by the Transmission Registers Empty bit in the SR register (SR.TXEMPTY). If a transfer delay (CSRn.DLYBCT) is greater than zero for the last transfer, SR.TXEMPTY is set after the completion of said delay. The CLK_SPI can be switched off at this time. During reception, received data are transferred from the Shift Register to the reception FIFO. The FIFO can contain up to 4 characters (both Receive Data and Peripheral Chip Select fields). While a character of the FIFO is unread, the Receive Data Register Full bit in SR remains high (SR.RDRF). Characters are read through the RDR register. If the four characters stored in the FIFO are not read and if a new character is stored, this sets the Overrun Error Status bit in the SR register (SR.OVRES). The procedure to follow in such a case is described in Section 21.7.3.8. 452 32099A–AVR32–06/09 AT32UC3L In master mode, if the received data is not read fast enough compared to the transfer rhythm imposed by the write accesses in the TDR, some overrun errors may occur, even if the FIFO is enabled. To insure a perfect data integrity of received data (especially at high data rate), the mode Wait Data Read Before Transfer can be enabled in the MR register (MR.WDRBT). When this mode is activated, no transfer starts while received data remains unread in the RDR. When data is written to the TDR and if unread received data is stored in the RDR, the transfer is paused until the RDR is read. In this mode no overrun error can occur. Please note that if this mode is enabled, it is useless to activate the FIFO in reception. Figure 21-5 on page 453shows a block diagram of the SPI when operating in master mode. Figure 21-6 on page 454 shows a flow chart describing how transfers are handled. 21.7.3.1 Master mode block diagram Figure 21-5. Master Mode Block Diagram CSR0..3 SCBR CLK_SPI Baud Rate Generator SPCK SPI Clock RXFIFOEN RDR RD RDRF OVRES CSR0..3 BITS NCPHA CPOL MISO LSB Shift Register 0 1 MSB 4 – Character FIFO MOSI TDR TD TDRE RXFIFOEN RDR PCS CSR0..3 CSNAAT CSAAT PCSDEC PCS 0 TDR PCS 1 Current Peripheral NPCS2 NPCS1 NPCS0 0 1 4 – Character FIFO NPCS3 PS MR MSTR MODF NPCS0 MODFDIS 453 32099A–AVR32–06/09 AT32UC3L 21.7.3.2 Master mode flow diagram Figure 21-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ? 0 1 CSAAT ? PS ? Variable peripheral yes MR(PCS) = NPCS ? no NPCS = 0xF 0 Fixed peripheral 0 0 PS ? Variable peripheral NPCS = MR(PCS) Fixed peripheral 1 TDR(PCS) = NPCS ? no NPCS = 0xF 1 NPCS = TDR(PCS) Delay DLYBCS Delay DLYBCS NPCS = TDR(PCS) NPCS = MR(PCS), TDR(PCS) Delay DLYBS Serializer = TDR(TD) TDRE = 1 Data Transfer RDR(RD) = Serializer RDRF = 1 Delay DLYBCT 0 TDRE ? 1 1 CSAAT ? 0 NPCS = 0xF Delay DLYBCS 454 32099A–AVR32–06/09 AT32UC3L 21.7.3.3 Clock generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbidden. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. At reset, CSRn.SCBR is zero and the user has to configure it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be configured in the CSRn.SCBR field. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 21.7.3.4 Transfer delays Figure 21-7 on page 455 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be configured to modify the transfer waveforms: • The delay between chip selects, programmable only once for all the chip selects by writing to the Delay Between Chip Selects field in the MR register (MR.DLYBCS). Allows insertion of a delay between release of one chip select and before assertion of a new one. • The delay before SPCK, independently programmable for each chip select by writing the Delay Before SPCK field in the CSRn registers (CSRn.DLYBS). Allows the start of SPCK to be delayed after the chip select has been asserted. • The delay between consecutive transfers, independently programmable for each chip select by writing the Delay Between Consecutive Transfers field in the CSRn registers (CSRn.DLYBCT). Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 21-7. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 455 32099A–AVR32–06/09 AT32UC3L 21.7.3.5 Peripheral selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: • Fixed Peripheral Select: SPI exchanges data with only one peripheral • Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing a zero to the Peripheral Select bit in MR (MR.PS). In this case, the current peripheral is defined by the MR.PCS field and the TDR.PCS field has no effect. Variable Peripheral Select is activated by writing a one to the MR.PS bit . The TDR.PCS field is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the Peripheral DMA Controller is an optimal means, as the size of the data transfer between the memory and the SPI is either 4 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the MR register. Data written to TDR is 32-bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the Peripheral DMA Controller in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the CSRn registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 21.7.3.6 Peripheral chip select decoding The user can configure the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing a one to the Chip Select Decode bit in the MR register (MR.PCSDEC). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the MR register or the TDR register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at one) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, the CRS0 register defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 21.7.3.7 Peripheral deselection When operating normally, as soon as the transfer of the last data written in TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding 456 32099A–AVR32–06/09 AT32UC3L to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. When the CSRn.CSAAT bit is written to qero, the NPCS does not rise in all cases between two transfers on the same peripheral. During a transfer on a Chip Select, the SR.TDRE bit rises as soon as the content of the TDR is transferred into the internal shifter. When this bit is detected the TDR can be reloaded. If this reload occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. This might lead to difficulties for interfacing with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Not Active After Transfer bit (CSRn.CSNAAT) written to one. This allows to de-assert systematically the chip select lines during a time DLYBCS. (The value of the CSRn.CSNAAT bit is taken into account only if the CSRn.CSAAT bit is written to zero for the same Chip Select). Figure 21-8 on page 458 shows different peripheral deselection cases and the effect of the CSRn.CSAAT and CSRn.CSNAAT bits. 21.7.3.8 FIFO management A FIFO has been implemented in Reception FIFO (both in master and in slave mode), in order to be able to store up to 4 characters without causing an overrun error. If an attempt is made to store a fifth character, an overrun error rises. If such an event occurs, the FIFO must be flushed. There are two ways to Flush the FIFO: • By performing four read accesses of the RDR (the data read must be ignored) • By writing a one to the Flush Fifo Command bit in the CR register (CR.FLUSHFIFO). After that, the SPI is able to receive new data. 457 32099A–AVR32–06/09 AT32UC3L Figure 21-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 CSAAT = 1 and CSNAAT= 0 / 1 TDRE DLYBCT A DLYBCS PCS = A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write TDR TDRE DLYBCT A DLYBCS PCS=A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write TDR TDRE NPCS[0..3] DLYBCT A DLYBCS PCS = B B A DLYBCT B DLYBCS PCS = B Write TDR CSAAT = 0 and CSNAAT = 0 DLYBCT TDRE CSAAT = 0 and CSNAAT = 1 DLYBCT NPCS[0..3] A A A DLYBCS A PCS = A Write TDR PCS = A Figure 21-8 on page 458 shows different peripheral deselection cases and the effect of the CSRn.CSAAT and CSRn.CSNAAT bits. 21.7.3.9 Mode fault detection A mode fault is detected when the SPI is configured in master mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the I/O Controller, so that external pull up resistors are needed to guarantee high level. 458 32099A–AVR32–06/09 AT32UC3L When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the Spi Enable bit in the CR register (CR.SPIEN). By default, the mode fault detection circuitry is enabled. The user can disable mode fault detection by writing a one to the Mode Fault Detection bit in the MR register (MR.MODFDIS). 21.7.4 SPI Slave Mode When operating in slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the Bits Per Transfer field of the Chip Select Register 0 (CSR0.BITS). These bits are processed following a phase and a polarity defined respectively by the CSR0.NCPHA and CSR0.CPOL bits. Note that the BITS, CPOL, and NCPHA bits of the other Chip Select Registers have no effect when the SPI is configured in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the SR.RDRF bit rises. If the RDR register has not been read before new data is received, the SR.OVRES bit is set. As long as this bit is set, data is loaded in RDR. The user has to read the SR register to clear the SR.OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the TDR register, the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets to zero. When a first data is written in TDR, it is transferred immediately in the Shift Register and the SR.TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in TDR is transferred in the Shift Register and the SR.TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the TDR. In case no character is ready to be transmitted, i.e. no character has been written in TDR since the last load from TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. In this case the Underrun Error Status bit is set in SR (SR.UNDES). Figure 21-9 on page 460 shows a block diagram of the SPI when operating in slave mode. 459 32099A–AVR32–06/09 AT32UC3L Figure 21-9. Slave Mode Functional Block Diagram SPCK NSS SPIEN SPIENS SPIDIS CSR0 BITS NCPHA CPOL MOSI LSB Shift Register 0 1 MSB 4 - Character FIFO RXFIFOEN RDR RD RDRF OVRES SPI Clock MISO TDR TD UNDES TDRE 460 32099A–AVR32–06/09 AT32UC3L 21.8 User Interface SPI Register Memory Map Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Write Protection Control Register Write Protection Status Register Version Register Register Name CR MR RDR TDR SR IER IDR IMR CSR0 CSR1 CSR2 CSR3 WPCR WPSR VERSION Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x000000F0 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0X00000000 0x00000000 - (1) Table 21-3. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x30 0x34 0x38 0x3C 0x E4 0xE8 0xFC Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 461 32099A–AVR32–06/09 AT32UC3L 21.8.1 Name: Control Register CR Write-only 0x00 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 LASTXFER 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 FLUSHFIFO 7 SWRST 6 - 5 - 4 - 3 - 2 - 1 SPIDIS 0 SPIEN • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 0: Writing a zero to this bit has no effect. • FLUSHFIFO: Flush Fifo Command 1: If The FIFO Mode is enabled (MR.FIFOEN written to one) and if an overrun error has been detected, this command allows to empty the FIFO. 0: Writing a zero to this bit has no effect. • SWRST: SPI Software Reset 1: Writing a one to this bit will reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. Peripheral DMA Controller channels are not affected by software reset. 0: Writing a zero to this bit has no effect. • SPIDIS: SPI Disable 1: Writing a one to this bit will disable the SPI. As soon as SPIDIS is written to one, the SPI finishes its transfer, all pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the CR register is written, the SPI is disabled. 0: Writing a zero to this bit has no effect. • SPIEN: SPI Enable 1: Writing a one to this bit will enable the SPI to transfer and receive data. 0: Writing a zero to this bit has no effect. 462 32099A–AVR32–06/09 AT32UC3L 21.8.2 Name: Mode Register MR Read/Write 0x04 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCS 27 26 25 24 23 - 22 - 21 - 20 - 19 18 PCS 17 16 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 LLB 6 RXFIFOEN 5 WDRBT 4 MODFDIS 3 - 2 PCSDEC 1 PS 0 MSTR • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees nonoverlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default. Otherwise, the following equation determines the delay: Delay Between Chip Selects = D LYBCS ---------------------CLKSPI • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • LLB: Local Loopback Enable 1: Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in master mode only (MISO is internally connected on MOSI). 0: Local loopback path disabled. • RXFIFOEN: FIFO in Reception Enable 1: The FIFO is used in reception (four characters can be stored in the SPI). 463 32099A–AVR32–06/09 AT32UC3L 0: The FIFO is not used in reception (only one character can be stored in the SPI). • WDRBT: Wait Data Read Before Transfer 1: In master mode, a transfer can start only if the RDR register is empty, i.e. does not contain any unread data. This mode prevents overrun error in reception. 0: No Effect. In master mode, a transfer can be initiated whatever the state of the RDR register is. • MODFDIS: Mode Fault Detection 1: Mode fault detection is disabled. 0: Mode fault detection is enabled. • PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The CSRn registers define the characteristics of the 15 chip selects according to the following rules: CSR0 defines peripheral chip select signals 0 to 3. CSR1 defines peripheral chip select signals 4 to 7. CSR2 defines peripheral chip select signals 8 to 11. CSR3 defines peripheral chip select signals 12 to 14. • PS: Peripheral Select 1: Variable Peripheral Select. 0: Fixed Peripheral Select. • MSTR: Master/Slave Mode 1: SPI is in master mode. 0: SPI is in slave mode. 464 32099A–AVR32–06/09 AT32UC3L 21.8.3 Name: Receive Data Register RDR Read-only 0x08 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 PCS 17 16 15 14 13 12 RD[15:8] 11 10 9 8 7 6 5 4 RD[7:0] 3 2 1 0 • PCS: Peripheral Chip Select In master mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. 465 32099A–AVR32–06/09 AT32UC3L 21.8.4 Name: Transmit Data Register TDR Write-only 0x0C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 LASTXFER 23 - 22 - 21 - 20 - 19 18 PCS 17 16 15 14 13 12 TD[15:8] 11 10 9 8 7 6 5 4 TD[7:0] 3 2 1 0 • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 0: Writing a zero to this bit has no effect. This field is only used if Variable Peripheral Select is active (MR.PS = 1). • PCS: Peripheral Chip Select If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS This field is only used if Variable Peripheral Select is active (MR.PS = 1). • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the TDR register in a right-justified format. 466 32099A–AVR32–06/09 AT32UC3L 21.8.5 Name: Status Register SR Read-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 SPIENS 15 - 14 - 13 - 12 - 11 - 10 UNDES 9 TXEMPTY 8 NSSR 7 - 6 - 5 - 4 - 3 OVRES 2 MODF 1 TDRE 0 RDRF • SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled. • UNDES: Underrun Error Status (Slave Mode Only) 1: This bit is set when a transfer begins whereas no data has been loaded in the TDR register. 0: This bit is cleared when the SR register is read. • TXEMPTY: Transmission Registers Empty 1: This bit is set when TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. 0: This bit is cleared as soon as data is written in TDR. • NSSR: NSS Rising 1: A rising edge occurred on NSS pin since last read. 0: This bit is cleared when the SR register is read. • OVRES: Overrun Error Status 1: This bit is set when an overrun has occurred. An overrun occurs when RDR is loaded at least twice from the serializer since the last read of the RDR. 0: This bit is cleared when the SR register is read. • MODF: Mode Fault Error 1: This bit is set when a Mode Fault occurred. 0: This bit is cleared when the SR register is read. • TDRE: Transmit Data Register Empty 1: This bit is set when the last data written in the TDR register has been transferred to the serializer. 0: This bit is cleared when data has been written to TDR and not yet transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. • RDRF: Receive Data Register Full 1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR. 0: No data has been received since the last read of RDR 467 32099A–AVR32–06/09 AT32UC3L 21.8.6 Name: Interrupt Enable Register IER Write-only 0x14 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 UNDES 9 TXEMPTY 8 NSSR 7 - 6 - 5 - 4 - 3 OVRES 2 MODF 1 TDRE 0 RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 468 32099A–AVR32–06/09 AT32UC3L 21.8.7 Name: Interrupt Disable Register IDR Write-only 0x18 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 UNDES 9 TXEMPTY 8 NSSR 7 - 6 - 5 - 4 - 3 OVRES 2 MODF 1 TDRE 0 RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 469 32099A–AVR32–06/09 AT32UC3L 21.8.8 Name: Interrupt Mask Register IMR Read-only 0x1C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 UNDES 9 TXEMPTY 8 NSSR 7 - 6 - 5 - 4 - 3 OVRES 2 MODF 1 TDRE 0 RDRF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 470 32099A–AVR32–06/09 AT32UC3L 21.8.9 Name: Chip Select Register 0 CSR0 Read/Write 0x30 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCT 27 26 25 24 23 22 21 20 DLYBS 19 18 17 16 15 14 13 12 SCBR 11 10 9 8 7 6 BITS 5 4 3 CSAAT 2 CSNAAT 1 NCPHA 0 CPOL • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 × DLYBCT Delay Between Consecutive Transfers = ----------------------------------CLKSPI • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBSDelay Before SPCK = -------------------CLKSPI • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: CLKSPI SPCK Baudrate = --------------------SCBR Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. 471 32099A–AVR32–06/09 AT32UC3L • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 4 5 6 7 Reserved Reserved Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: DLYBCS ---------------------- (if DLYBCT field is different from 0) CLKSPI DLYBCS + 1 (if DLYBCT field equals 0) -------------------------------CLKSPI • NCPHA: Clock Phase 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 472 32099A–AVR32–06/09 AT32UC3L 21.8.10 Name: Chip Select Register 1 CSR1 Read/Write 0x34 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCT 27 26 25 24 23 22 21 20 DLYBS 19 18 17 16 15 14 13 12 SCBR 11 10 9 8 7 6 BITS 5 4 3 CSAAT 2 CSNAAT 1 NCPHA 0 CPOL • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 × DLYBCT Delay Between Consecutive Transfers = ----------------------------------CLKSPI • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBSDelay Before SPCK = -------------------CLKSPI • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: CLKSPI SPCK Baudrate = --------------------SCBR Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. 473 32099A–AVR32–06/09 AT32UC3L • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 4 5 6 7 Reserved Reserved Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: DLYBCS ---------------------- (if DLYBCT field is different from 0) CLKSPI DLYBCS + 1 (if DLYBCT field equals 0) -------------------------------CLKSPI • NCPHA: Clock Phase 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 474 32099A–AVR32–06/09 AT32UC3L 21.8.11 Name: Chip Select Register 2 CSR2 Read/Write 0x38 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCT 27 26 25 24 23 22 21 20 DLYBS 19 18 17 16 15 14 13 12 SCBR 11 10 9 8 7 6 BITS 5 4 3 CSAAT 2 CSNAAT 1 NCPHA 0 CPOL • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 × DLYBCT Delay Between Consecutive Transfers = ----------------------------------CLKSPI • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBSDelay Before SPCK = -------------------CLKSPI • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: CLKSPI SPCK Baudrate = --------------------SCBR Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. 475 32099A–AVR32–06/09 AT32UC3L • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 4 5 6 7 Reserved Reserved Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: DLYBCS ---------------------- (if DLYBCT field is different from 0) CLKSPI DLYBCS + 1 (if DLYBCT field equals 0) -------------------------------CLKSPI • NCPHA: Clock Phase 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 476 32099A–AVR32–06/09 AT32UC3L 21.8.12 Name: Chip Select Register 3 CSR3 Read/Write 0x3C 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DLYBCT 27 26 25 24 23 22 21 20 DLYBS 19 18 17 16 15 14 13 12 SCBR 11 10 9 8 7 6 BITS 5 4 3 CSAAT 2 CSNAAT 1 NCPHA 0 CPOL • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 × DLYBCT Delay Between Consecutive Transfers = ----------------------------------CLKSPI • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBSDelay Before SPCK = -------------------CLKSPI • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: CLKSPI SPCK Baudrate = --------------------SCBR Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results. At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer. 477 32099A–AVR32–06/09 AT32UC3L • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 4 5 6 7 Reserved Reserved Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. 0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved. • CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1) 0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and if the two transfers occur on the same Chip Select. 1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration of: DLYBCS ---------------------- (if DLYBCT field is different from 0) CLKSPI DLYBCS + 1 (if DLYBCT field equals 0) -------------------------------CLKSPI • NCPHA: Clock Phase 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CPOL: Clock Polarity 1: The inactive state value of SPCK is logic level one. 0: The inactive state value of SPCK is logic level zero. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. 478 32099A–AVR32–06/09 AT32UC3L 21.8.13 Write Protection Control Register Register Name: WPCR Access Type: Offset: Reset Value: Read-write 0xE4 0x00000000 31 30 29 28 27 26 25 24 SPIWPKEY[23:16] 23 22 21 20 19 18 17 16 SPIWPKEY[15:8] 15 14 13 12 11 10 9 8 SPIWPKEY[7:0] 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SPIWPEN • SPIWPKEY: SPI Write Protection Key Password If a value is written in SPIWPEN, the value is taken into account only if SPIWPKEY is written with “SPI” (SPI written in ASCII Code, i.e. 0x535049 in hexadecimal). • SPIWPEN: SPI Write Protection Enable 1: The Write Protection is Enabled 0: The Write Protection is Disabled 479 32099A–AVR32–06/09 AT32UC3L 21.8.14 Write Protection Status Register Register Name: WPSR Access Type: Offset: Reset Value: Read-only 0xE8 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 SPIWPVSRC 11 10 9 8 7 - 6 - 5 - 4 - 3 - 2 1 SPIWPVS 0 • SPIWPVSRC: SPI Write Protection Violation Source This Field indicates the Peripheral Bus Offset of the register concerned by the violation (MR or CSRx) • SPIWPVS: SPI Write Protection Violation Status SPIWPVS value 1 2 3 4 Violation Type The Write Protection has blocked a Write access to a protected register (since the last read). Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx). Both Write Protection violation and software reset with Write Protection enabled have occurred since the last read. Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. The Write Protection has blocked a Write access to a protected register and write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. Software Reset has been performed while Write Protection was enabled (since the last read or since the last write access on MR, IER, IDR or CSRx) and some write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. - The Write Protection has blocked a Write access to a protected register. and - Software Reset has been performed while Write Protection was enabled. and - Write accesses have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was active) since the last read. 5 6 7 480 32099A–AVR32–06/09 AT32UC3L 21.8.15 Version Register Register Name: VERSION Access Type: Offset: Reset Value: Read-only 0xFC – 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 14 13 12 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated. 481 32099A–AVR32–06/09 AT32UC3L 21.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 21-4. Module Name SPI SPI Clock Name Clock Name CLK_SPI Table 21-5. Register VERSION Reset Value 0x00000211 482 32099A–AVR32–06/09 AT32UC3L 22. Two-Wire Master Interface (TWIM) Rev 1.0.1.0 22.1 Features • Compatible with I²C standard – Multi-master support – 100 and 400 kbit/s transfer speeds – 7- and 10-bit and General Call addressing Compatible with SMBus standard – Hardware Packet Error Checking (CRC) generation and verification with ACK control – SMBus ALERT interface – 25 ms clock low timeout delay – 10 ms master cumulative clock low extend time – 25 ms slave cumulative clock low extend time Compatible with PMBus Compatible with Atmel Two-Wire Interface Serial Memories DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer • • • • • • 22.2 Overview The Atmel Two-wire Interface Master (TWIM) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial EEPROM and I²C compatible device such as a real rime clock (RTC), dot matrix/graphic LCD controller and temperature sensor, to name a few. TWIM is always a bus master and can transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus is performed internally and relinquishes the bus automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies.Table 22-1 on page 483 lists the compatibility level of the Atmel Twowire Interface in Master Mode and a full I²C compatible device. Table 22-1. I²C Standard Standard Mode Speed (100 KHz) Fast Mode Speed (400 KHz) 7- or 10-bits Slave Addressing START BYTE (1) Atmel TWIM Compatibility with I²C Standard Atmel TWIM Supported Supported Supported Not Supported Supported Supported Supported Supported Repeated Start (Sr) Condition ACK and NACK Management Slope Control and Input Filtering (Fast mode) Clock Stretching Note: 1. START + b000000001 + Ack + Sr 483 32099A–AVR32–06/09 AT32UC3L Table 22-2 on page 484 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus compatible master. Table 22-2. Bus Timeouts Atmel TWIM Compatibility with SMBus Standard Atmel TWIM Supported Supported Supported Supported Supported SMBus Standard Address Resolution Protocol Alert Host Functionality Packet Error Checking 22.3 List of Abbreviations Table 22-3. Abbreviation TWI A NA P S Sr SADR ADR R W Abbreviations Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start Slave Address Any address except SADR Read Write 484 32099A–AVR32–06/09 AT32UC3L 22.4 Block Diagram Figure 22-1. Block Diagram Peripheral Bus Bridge TWCK I/O controller Two-wire Interface CLK_TWIM TWI Interrupt TWD TWALM Power Manager INTC 22.5 Application Block Diagram Figure 22-2. Application Block Diagram VDD Rp TWD TWI Master TWCK Rp Atmel TWI serial EEPROM Slave 1 I²C RTC Slave 2 I²C LCD controller Slave 3 I²C temp. sensor Slave 4 Rp: Pull up value as given by the I²C Standard 22.6 I/O Lines Description I/O Lines Description Pin Description Two-wire Serial Data Two-wire Serial Clock SMBus SMBALERT Type Input/Output Input/Output Input/Output Table 22-4. Pin Name TWD TWCK TWALM 485 32099A–AVR32–06/09 AT32UC3L 22.7 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 22.7.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 22-2 on page 485). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or opencollector to perform the wired-AND function. TWALM is used to implement the optional SMBus SMBALERT signal. TWD, TWCK and TWALM pins may be multiplexed with I/O Controller lines. To enable the TWIM, the programmer must perform the following steps: • Program the I/O Controller to: – Dedicate TWD, TWCK and optionally TWALM as peripheral lines. – Define TWD, TWCK and optionally TWALM as open-drain. 22.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIM, the TWIM will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 22.7.4 Interrupts The TWIM interrupt request lines are connected to the interrupt controller. Using the TWIM interrupts requires the interrupt controller to be programmed first. 22.7.5 Debug Operation When an external debugger forces the CPU into debug mode, the TWIM continues normal operation. If the TWIM is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 22.7.3 486 32099A–AVR32–06/09 AT32UC3L 22.8 22.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 22-4 on page 487). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 22-4 on page 487). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 22-3. START and STOP Conditions TWD TWCK Start Stop Figure 22-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 22.8.2 Operation The TWIM has two modes of operation: • Master transmitter mode • Master receiver mode The master is the device which starts and stops a transfer and generates the TWCK clock. These modes are described in the following chapters. 487 32099A–AVR32–06/09 AT32UC3L 22.8.2.1 Clock Generation The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be programmed so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be selected through the EXP field in CWGR. f clkpb f prescaled = ------------------------( EXP + 1 ) ) 2 CWGR has the following fields: LOW: Prescaled clock cycles in clock low count. Used to time TLOW. and TBUF. HIGH: Prescaled clock cycles in clock high count. Used to time THIGH. STASTO: Prescaled clock cycles in clock high count. Used to time THD_STA, TSU_STA, TSU_STO. DATA: Prescaled clock cycles for data setup and hold count. Used to time THD_DAT, TSU_DAT. EXP: Specifies the clock prescaler setting. Note that the total clock low time generated is the sum of THD_DAT + TSU_DAT + TLOW. Any slave or other bus master taking part in the transfer may extend the TWCK low period at any time. Figure 22-5. Bus Timing Diagram t LOW t HIGH t LOW S t t HD:STA SU:DAT t HD:DAT t t SU:DAT SU:STO P t SU:STA Sr 22.8.2.2 Setting up and Performing a Transfer Operation of TWIM is mainly controlled by the Control Register (CR) and the Command Register (CMDR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by programming the Clock Waveform Generator Register (CWGR). If operating in SMBus mode, the SMBus Timing Register (SMBTR) register must also be configured. 2. If a DMA controller is to be used for the transfers, it must be set up. 3. CMDR or NCMDR must be programmed with a value describing the transfer to be performed. 488 32099A–AVR32–06/09 AT32UC3L The interrupt system can be set up to give interrupt request on specific events or error conditions, for example when the transfer is complete or if arbitration is lost. The controller will refuse to start a new transfer while ANAK, DNAK or ARBLST is set in the Status Register (SR). This is necessary to avoid a race when the software issues a continuation of the current transfer at the same time as one of these errors happen. Also, if ANAK or DNAK occur, a STOP condition is sent automatically. The programmer will have to restart the transmission by clearing the errors bit in SR after resolving the cause for the NACK. After a data or address NACK from the slave, a STOP will be transmitted automatically. Note that the VALID bit in CMDR is NOT cleared in this case. If this transfer is to be discarded, the VALID bit can be cleared manually allowing any command in NCMDR to be copied into CMDR. 22.8.3 Master Transmitter Mode A START condition is transmitted and master transmitter mode is initiated when the bus is free and CMDR has been written with START=1 and READ=0. START and SADR+W will then be transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in the Status Register if no slave acknowledges the address. After the address phase, the following is repeated: while (NBYTES>0) 1. Wait until THR contains a valid data byte, stretching low period of TWCK. SR.TXRDY indicates the state of THR. Software or a DMA controller must write the data byte to THR. 2. Transmit this data byte 3. Decrement NBYTES 4. If (NBYTES==0) and STOP=1, transmit STOP condition Programming CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data bytes, ie START, SADR+W, STOP. TWI transfers require the slave to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable Register (TWIM_IER). TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel. The end of a command is marked by setting the SR.CCOMP bit to one. See Figure 22-6 on page 490 and Figure 22-7 on page 490. 489 32099A–AVR32–06/09 AT32UC3L Figure 22-6. Master Write with One Data Byte TWD S DADR W A DATA A P TCOMP TXRDY Write THR (DATA) NBYTES set to 1 STOP sent automatically (ACK received and NBYTES= 0) Figure 22-7. Master Write with Multiple Data Bytes TWD S DADR W A DATA n A DATA n+5 A DATA n+m A P TCOMP TXRDY Write THR (Data n) NBYTES set to m Write THR (Data n+1) Write THR (Data n+m) Last data sent STOP sent automatically (ACK received and NBYTES= 0) 22.8.4 Master Receiver Mode A START condition is transmitted and master receiver mode is initiated when the bus is free and CMDR has been written with START=1 and READ=1. START and SADR+R will then be transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in the Status Register if no slave acknowledges the address. After the address phase, the following is repeated: while (NBYTES>0) 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or a DMA controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3. Place the received data byte in RHR, set RXRDY. 4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK. 5. Decrement NBYTES 6. If (NBYTES==0) and STOP=1, transmit STOP condition. Programming CMDR with START=STOP=1 and NBYTES=0 will generate a transmission with no data bytes, ie START, DADR+R, STOP The TWI transfers require the master to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the master to pull it down in order to generate the acknowledge. All data bytes except the last are 490 32099A–AVR32–06/09 AT32UC3L acknowledged by the master. Not acknowledging the last byte informs the slave that the transfer is finished. RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 22-8. Master Read with One Data Byte TWD S DADR R A DATA N P TCOMP Write START & STOP Bit, NBYTES=1 RXRDY Read RHR Figure 22-9. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TCOMP Write START + STOP Bit NBYTES=m RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Send STOP when NBYTES=0 Read RHR DATA (n+m) 22.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The programmer can set up ring buffers for the DMA controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 22.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIM (ADR, NBYTES, etc.). 3. Start the transfer by setting the Peripheral DMA Controller TXTEN bit. 4. Wait for the Peripheral DMA Controller end TX flag. 5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller TXDIS bit. 491 32099A–AVR32–06/09 AT32UC3L 22.8.5.2 Data Receive with the Peripheral DMA Controller 1. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIM (ADR, NBYTES, etc.). 3. Start the transfer by setting the Peripheral DMA Controller RXTEN bit. 4. Wait for the Peripheral DMA Controller end RX flag. 5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller RXDIS bit. 22.8.6 Multi-master Mode More than one master may access the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a STOP. The SR.ARBLST flag will be set. When the STOP is detected, the master who lost arbitration may reinitiate the data transfer. Arbitration is illustrated in Figure 22-11 on page 493. If the user starts a transfer and if the bus is busy, TWIM automatically waits for a STOP condition on the bus before initiating the transfer (see Figure 22-10 on page 492). Note: The state of the bus (busy or free) is not indicated in the user interface. Figure 22-10. Programmer Sends Data While the Bus is Busy TWCK STOP sent by the master TWD DATA sent by a master Bus is busy Bus is free TWI DATA transfer Transfer is kept START sent by the TWI DATA sent by the TWI A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated 492 32099A–AVR32–06/09 AT32UC3L Figure 22-11. Arbitration Cases TWCK TWD TWCK Data from a Master Data from TWI TWD S S S 1 1 1 0 0 11 0 1 Arbitration is lost TWI stops sending data P S S 1 1 1 0 1 Arbitration is lost The master stops sending data 0 01 0 01 1 1 Data from the TWI 00 11 Data from the master P S ARBLST Bus is busy Bus is free TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Transfer is stopped Transfer is kept Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated 22.8.7 Combined Transfers CMDR and NCMDR may be used to generate longer sequences of connected transfers, since generation of START and/or STOP conditions is programmable on a per-command basis. Programming NCMDR with START=1 when the previous transfer was programmed with STOP=0 will cause a REPEATED START on the bus. The ability to generate such connected transfers allows arbitrary transfer lengths, since it is legal to program CMDR with both START=0 and STOP=0. If this is done in master receiver mode, the CMDR.ACKLAST bit must also be controlled. As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to the THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see “Using the Peripheral DMA Controller” on page 491 22.8.7.1 Write Followed by Write Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP. To generate this transfer: 1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 493 32099A–AVR32–06/09 AT32UC3L 5. Wait until SR.TXRDY==1, then write third data byte to transfer to THR. 6. Wait until SR.TXRDY==1, then write fourth data byte to transfer to THR. 22.8.7.2 Read Followed by Read Consider the following transfer: START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. To generate this transfer: 1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.RXRDY==1, then read second data byte received from RHR. 5. Wait until SR.RXRDY==1, then read third data byte received from RHR. 6. Wait until SR.RXRDY==1, then read fourth data byte received from RHR. If combining several transfers, without any STOP or REPEATED START between them, remember to set the ACKLAST bit in CMDR to keep from ending each of the partial transfers with a NACK. 22.8.7.3 Write Followed by Read Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+R, DATA+A, DATA+NA, STOP. Figure 22-12. Combining a Write and Read Transfer TWI_THR DATA0 DATA1 TWD S ADR W A DATA0 A DATA1 NA Sr ADR R A DATA2 A DATA3 A DATA3 P TWI_RHR TXRDY RXRDY DATA2 TCOMP To generate this transfer: 1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 5. Wait until SR.RXRDY==1, then read first data byte received from RHR. 6. Wait until SR.RXRDY==1, then read second data byte received from RHR. 22.8.7.4 Read Followed by Write Consider the following transfer: 494 32099A–AVR32–06/09 AT32UC3L START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+W, DATA+A, DATA+A, STOP. Figure 22-13. Combining a Read and Write Transfer TWI_THR DATA2 DATA3 TWD TWI_RHR S SADR R A DATA0 A DATA1 A Sr SADR W A DATA2 A DATA3 NA P DATA0 DATA1 TXRDY RXRDY Read TWI_RHR TCOMP To generate this transfer: 1. Program CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1. 2. Program NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0. 3. Wait until SR.RXRDY==1, then read first data byte received from RHR. 4. Wait until SR.RXRDY==1, then read second data byte received from RHR. 5. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 6. Wait until SR.TXRDY==1, then write second data byte to transfer to THR. 22.8.8 Ten Bit Addressing Setting CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10bit addressing is similar to transfers with 7-bit addresses, except that bits 10:7 of CMDR.ADR must be set appropriately. In Figure 22-14 on page 495 and Figure 22-15 on page 496, the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 22.8.8.1 Master Transmitter To perform a master transmitter transfer, 1. Program CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the desired address and NBYTES value. Figure 22-14. A Write Transfer with 10-bit Addressing 1 S 1 1 1 0 X X 0 RW A1 SLAVE ADDRESS 2nd byte A2 DATA A DATA AA P SLAVE ADDRESS 1st 7 bits 22.8.8.2 Master Receiver When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be controlled. CMDR.REPSAME must be written to one when the address phase of the transfer 495 32099A–AVR32–06/09 AT32UC3L should consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard specifies that such addressing is required when addressing a slave for reads using 10-bit addressing. To perform a master receiver transfer, 1. Program CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0, NBYTES=0 and the desired address. 2. Program NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the desired address and NBYTES value. Figure 22-15. A Read Transfer with 10-bit Addressing 1 S 1 1 1 0 X X 0 RW A1 SLAVE ADDRESS 2nd byte A2 Sr 1 1 1 1 0 X X 1 RW A3 DATA A DATA A P SLAVE ADDRESS 1st 7 bits SLAVE ADDRESS 1st 7 bits 22.8.9 SMBus Mode SMBus mode is enabled and disabled by the SMEN and SMDIS bits in CR. SMBus mode operation is similar to I²C operation with the following exceptions: • Only 7-bit addressing can be used. • The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These timeout values must be programmed into SMBTR. • Transmissions can optionally include a CRC byte, called Packet Error Check (PEC). • A dedicated bus line SMBALERT, allows a slave to get a master’s attention. • A set of addresses have been reserved for protocol handling, such as Alert Response Address (ARA) and Host Header (HH) Address. 22.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing CMDR.PECEN to one enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct. In master transmitter mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the slave will return a NACK value. The DNAK bit in SR reflects the state of the last received ACK/NACK value. Some slaves may not be able to check the received PEC in time to return a NACK if an error occurred. In this case, the slave should always return an ACK after the PEC byte, and some other mechanism must be implemented to verify that the transmission was received correctly. In master receiver mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and the PECERR bit in SR is set. In master receiver mode, the PEC byte is always followed by a NACK transmitted by the master, since it is the last byte in the transfer. 496 32099A–AVR32–06/09 AT32UC3L The PEC byte is automatically inserted in a master transmitter transmission if PEC is enabled when NBYTES reaches zero. The PEC byte is identified in a master receiver transmission if PEC is enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of data bytes in the transmission, including the PEC byte. In combined transfers, the PECEN bit should only be set in the last of the combined transfers. Consider the following transfer: S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P This transfer is generated by writing two commands to the command registers. The first command is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2 and PECEN=1. Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current byte. No PEC byte will be sent in this case. 22.8.9.2 Timeouts The TLOWS and TLOWM fields in SMBTR configure the SMBus timeout values. If a timeout occurs, the master will transmit a STOP condition and leave the bus. The SR.TOUT bit is also set. 22.8.9.3 SMBus ALERT Signal A slave can get the master’s attention by pulling the TWALM line low. SR.SMBAL will then be set. This can be set up to trigger an interrupt, and software can then take the appropriate action, as defined in the SMBus standard. Identifying Bus Events This chapter lists the different bus events, and how these affects bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 22-5. Event Master transmitter has sent a data byte Master receiver has received a data byte 22.8.10 Bus Events Effect SR.THR is cleared. SR.RHR is set. SR.ANAK is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.DNAK is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.ARBLST is set. CMDR.CCOMP not set. CMDR.VALID remains set. TWCK and TWD immediately released to a pulled-up state. Start+Sadr sent, no ack received from slave Data byte sent to slave, no ack received from slave Arbitration lost 497 32099A–AVR32–06/09 AT32UC3L Table 22-5. Event SMBus Alert received Bus Events Effect SR.SMBAL is set. SR.SMBTOUT is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.DNAK is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.PECERR is set. CMDR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus. SR.STOP is set. CMDR.CCOMP set. CMDR.VALID remains set. STOP transmitted on bus after current byte transfer has finished. SMBus timeout received Master transmitter receives SMBus PEC Error Master receiver discovers SMBus PEC Error CR.STOP is written by user 498 32099A–AVR32–06/09 AT32UC3L 22.9 User Interface TWIM Register Memory Map Register Control Clock Waveform Generator SMBus Timing Command Next Command Receive Holding Transmit Holding Status Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Clear Register Parameter Register Version Register Register Name CR CWGR SMBTR CMDR NCMDR RHR THR SR IER IDR IMR SCR PR VR Access Write-only Read/Write Read/Write Read/Write Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Write-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000000 0x00000000 (1) (1) Table 22-6. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 499 32099A–AVR32–06/09 AT32UC3L 22.9.1 Name: Control Register (CR) CR Write-only 0x00 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 STOP 7 SWRST 6 - 5 SMDIS 4 SMEN 3 - 2 - 1 MDIS 0 MEN • STOP: Stop the current transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are additional pending transfers, they will have to be explicitly restarted by software after the STOP condition has been successfully sent. Writing a zero to this bit has no effect. • SWRST: Software Reset Writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly violating the bus semantics. Writing a zero to this bit has no effect. • SMDIS: SMBus Disable Writing a one to this bit disables SMBus mode. Writing a zero to this bit has no effect. • SMEN: SMBus Enable Writing a one to this bit enables SMBus mode. Writing a zero to this bit has no effect. • MDIS: Master Disable Writing a one to this bit disables the master interface. Writing a zero to this bit has no effect. • MEN: Master enable Writing a one to this bit enables the master interface. Writing a zero to this bit has no effect. 500 32099A–AVR32–06/09 AT32UC3L 22.9.2 Name: Clock Waveform Generator Register (CWGR) CWGR Read/Write 0x04 0x00000000 30 29 EXP 28 27 26 DATA 25 24 Access Type: Offset: Reset Value: 31 - 23 22 21 20 STASTO 19 18 17 16 15 14 13 12 HIGH 11 10 9 8 7 6 5 4 LOW 3 2 1 0 • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock. Counters are prescaled according to the following formula f clkpb f prescaled = ---------------------( EXP + 1 ) 2 • DATA: Data Setup and Hold Cycles Clock cycles for data setup and hold count. Prescaled by CWGR.EXP. Used to time THD_DAT, TSU_DAT. • STASTO: START and STOP Cycles Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THD_STA, TSU_STA, TSU_STO • HIGH: Clock High Cycles Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THIGH. • LOW: Clock Low Cycles Clock cycles in clock low count. Prescaled by CWGR.EXP. Used to time TLOW, TBUF. 501 32099A–AVR32–06/09 AT32UC3L 22.9.3 Name: SMBus Timing Register (SMBTR) SMBTR Read/Write 0x08 0x00000000 30 EXP 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 23 22 21 20 THMAX 19 18 17 16 15 14 13 12 TLOWM 11 10 9 8 7 6 5 4 TLOWS 3 2 1 0 • EXP: SMBus Timeout Clock prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR. Counters are prescaled according to the following formula f clkpb f prescaled, SMBus = ---------------------( EXP + 1 ) 2 • THMAX: Clock High maximum cycles Clock cycles in clock high maximum count. Prescaled by SMBTR.EXP. Used for bus free detection. Used to time THIGH:MAX. NOTE: Uses the prescaler specified by CWGR, NOT the prescaler specified by SMBTR. • TLOWM: Master Clock stretch maximum cycles Clock cycles in master maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:MEXT • TLOWS: Slave Clock stretch maximum cycles Clock cycles in slave maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:SEXT. 502 32099A–AVR32–06/09 AT32UC3L 22.9.4 Name: Command Register (CMDR) CMDR Read/Write 0x0C 0x00000000 30 29 28 27 26 25 ACKLAST 24 PECEN Access Type: Offset: Reset Value: 31 - 23 22 21 20 NBYTES 19 18 17 16 15 VALID 14 STOP 13 START 12 REPSAME 11 TENBIT 10 9 SADR[9:7] 8 7 6 5 4 SADR[6:0] 3 2 1 0 READ • ACKLAST: ACK Last Master RX Byte Writing this bit to zero causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the standard way of ending a master receiver transfer. Writing this bit to one causes the last byte in master receive mode (when NBYTES has reached 0) to be ACKed. Used for performing linked transfers in master receiver mode with no STOP or REPEATED START between the subtransfers. This is needed when more than 255 bytes are to be received in one single transmission. • PECEN: Packet Error Checking Enable Writing this bit to zero causes the transfer not to use PEC byte verification. The PEC LFSR is still updated for every bit transmitted or received. Must be used if SMBus mode is disabled. Writing this bit to one causes the transfer to use PEC. PEC byte generation (if master transmitter) or PEC byte verification (if master receiver) will be performed. • NBYTES: Number of data bytes in transfer The number of data bytes in the transfer. After the specified number of bytes have been transferred, a STOP condition is transmitted if CMDR.STOP is set. In SMBus mode, if PEC is used, NBYTES includes the PEC byte, ie there are NBYTES-1 data bytes and a PEC byte. • VALID: CMDR Valid Writing this to zero indicates that CMDR does not contain a valid command. Writing this to one indicates that CMDR contains a valid command. This bit is cleared when the command is finished. • STOP: Send STOP condition Write this bit to zero to not transmit a STOP condition after the data bytes have been transmitted. Write this bit to one to transmit a STOP condition after the data bytes have been transmitted. • START: Send START condition Write this bit to zero if the transfer in CMDR should not commence with a START or REPEATED START condition. Write this bit to one if the transfer in CMDR should commence with a START or REPEATED START condition. If the bus is free when the command is executed, a START condition is used, if the bus is busy, a REPEATED START is used. • REPSAME: Transfer is to same address as previous address Only used in 10-bit addressing mode, always write to 0 in 7-bit addressing mode. 503 32099A–AVR32–06/09 AT32UC3L Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. • TENBIT: Ten Bit Addressing Mode Write this bit to zero to use 7-bit addressing mode. Write this bit to one to use 10-bit addressing mode. Must not be used when TWIM is in SMBus mode. • SADR: Slave Address Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used. • READ: Transfer Direction Write this bit to zero to let the master transmit data. Write this bit to one to let the master receive data. 504 32099A–AVR32–06/09 AT32UC3L 22.9.5 Name: Next Command Register (NCMDR) NCMDR Read/Write 0x10 0x00000000 30 29 28 27 26 25 ACKLAST 24 PECEN Access Type: Offset: Reset Value: 31 - 23 22 21 20 NBYTES 19 18 17 16 15 VALID 14 STOP 13 START 12 REPSAME 11 TENBIT 10 9 SADR[9:7] 8 7 6 5 4 SADR[6:0] 3 2 1 0 READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the contents of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR. If the VALID bit in CMDR is cleared when NCMDR is written, the contents are copied immediately. 505 32099A–AVR32–06/09 AT32UC3L 22.9.6 Name: Receive Holding Register (RHR) RHR Read-only 0x14 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 RXDATA 3 2 1 0 • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is set, this field contains a byte received from the TWI bus. 506 32099A–AVR32–06/09 AT32UC3L 22.9.7 Name: Transmit Holding Register (THR) THR Write-only 0x18 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 TXDATA 3 2 1 0 • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here. 507 32099A–AVR32–06/09 AT32UC3L 22.9.8 Name: Status Register (SR) SR Read-only 0x1C 0x00000002 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 MENB 15 - 14 STOP 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 IDLE 3 CCOMP 2 CRDY 1 TXRDY 0 RXRDY • MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled. • STOP: Stop Request Accepted This bit is set when STOP request caused by setting CR STOP has been accepted, and transfer has stopped. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • PECERR: PEC Error This bit is set when a SMBus PEC error occurred. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • TOUT: Timeout This bit is set when a SMBus timeout occurred. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • SMBALERT: SMBus Alert This bit is set when a SMBus Alert was received. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • ARBLST: Arbitration Lost This bit is set when the actual state of the SDA line did not correspond to the data driven onto it, indicating a higher-priority transmission in progress by a different master. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • DNAK: NAK in Data Phase Received This bit is set when no ACK was received form slave during data transmission. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • ANAK: NAK in Address Phase Received This bit is set when no ACK was received from slave during address phase This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • IDLE: Master Interface is Idle This bit is set when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. 508 32099A–AVR32–06/09 AT32UC3L • CCOMP: Command Complete This bit is set when the current command has completed successfully and STOP has been transmitted. Not set if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR). • CRDY: Ready for More Commands This bit is set when CMDR and/or NCMDR is ready to receive one or more commands. This bit is cleared when this is no longer true. • TXRDY: THR Data Ready This bit is set when THR is ready for one or more data bytes. This bit is cleared when this is no longer true (i.e. THR is full or transmission has stopped). • RXRDY: RHR Data Ready This bit is set when RX data are ready to be read from RHR. This bit is cleared when this is no longer true. 509 32099A–AVR32–06/09 AT32UC3L 22.9.9 Name: Interrupt Enable Register (IER) IER Write-only 0x20 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 STOP 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 IDLE 3 CCOMP 2 CRDY 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR 510 32099A–AVR32–06/09 AT32UC3L 22.9.10 Name: Interrupt Disable Register (IDR) IDR Write-only 0x24 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 STOP 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 IDLE 3 CCOMP 2 CRDY 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR 511 32099A–AVR32–06/09 AT32UC3L 22.9.11 Name: Interrupt Mask Register (IMR) IMR Read-only 0x28 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 STOP 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 IDLE 3 CCOMP 2 CRDY 1 TXRDY 0 RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 512 32099A–AVR32–06/09 AT32UC3L 22.9.12 Name: Status Clear Register (SCR) SCR Write-only 0x2C 0x00000000 30 29 28 27 26 25 24 - Access Type : Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 STOP 13 PECERR 12 TOUT 11 SMBALERT 10 ARBLST 9 DNAK 8 ANAK 7 - 6 - 5 - 4 - 3 CCOMP 2 - 1 - 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 513 32099A–AVR32–06/09 AT32UC3L 22.9.13 Name: Parameter Register (PR) PR Read-only 0x30 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 514 32099A–AVR32–06/09 AT32UC3L 22.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 22-7. Module Name TWIM0 TWIM1 Module Clock Name Clock Name CLK_TWIM0 CLK_TWIM1 Table 22-8. Register VERSION PARAMETER Register Reset Values Reset Value 0x0000 0101 0x0000 0000 515 32099A–AVR32–06/09 AT32UC3L 23. Two-Wire Slave Interface (TWIS) Rev 1.1.2.1 23.1 Features • Compatible with I²C standard – 100 and 400 kbit/s transfer speeds – 7 and 10-bit and General Call addressing Compatible with SMBus standard – Hardware Packet Error Checking (CRC) generation and verification with ACK response – SMBALERT interface – 25 ms clock low timeout delay – 25 ms slave cumulative clock low extend time Compatible with PMBus DMA interface for reducing CPU load Arbitrary transfer lengths, including 0 data bytes Optional clock stretching if transmit or receive buffers not ready for data transfer 32-bit Peripheral Bus interface for configuration of the interface • • • • • • 23.2 Overview The Atmel Two-wire Interface Slave (TWIS) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 kbit/s, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus I²C or SMBus compatible master. TWIS is always a bus slave and can transfer sequential or single bytes. Below, Table 23-1 on page 516 lists the compatibility level of the Atmel Two-wire Slave Interface and a full I²C compatible device. Table 23-1. I²C Standard Standard Mode Speed (100 KHz) Fast Mode Speed (400 KHz) 7 or 10 bits Slave Addressing START BYTE(1) Repeated Start (Sr) Condition ACK and NAK Management Slope control and input filtering (Fast mode) Clock stretching Note: 1. START + b000000001 + Ack + Sr Atmel TWIS Compatibility with I²C Standard Atmel TWIS Supported Supported Supported Not Supported Supported Supported Supported Supported 516 32099A–AVR32–06/09 AT32UC3L Below, Table 23-2 on page 517 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. Table 23-2. Bus Timeouts Address Resolution Protocol Alert Packet Error Checking Atmel TWIS Compatibility with SMBus Standard Atmel TWIS Supported Supported Supported Supported SMBus Standard 23.3 List of Abbreviations Table 23-3. Abbreviation TWI A NA P S Sr SADR ADR R W Abbreviations Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start Slave Address Any address except SADR Read Write 23.4 Block Diagram Figure 23-1. Block Diagram Peripheral Bus Bridge TWCK I/O controller Two-wire Interface CLK_TWIS TWI Interrupt Interrupt Controller TWD TWALM Power Manager 517 32099A–AVR32–06/09 AT32UC3L 23.5 Application Block Diagram Figure 23-2. Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI serial EEPROM Slave 1 I²C RTC Slave 2 I²C LCD controller Slave 3 I²C temp. sensor Slave 4 Rp: Pull up value as given by the I²C Standard 23.6 I/O Lines Description I/O Lines Description Pin Description Two-wire Serial Data Two-wire Serial Clock SMBus SMBALERT Type Input/Output Input/Output Input/Output Table 23-4. Pin Name TWD TWCK TWALM 23.7 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 23.7.1 I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 23-2 on page 518). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or opencollector to perform the wired-AND function. TWALM is used to implement the optional SMBus SMBALERT signal. TWD, TWCK and TWALM pins may be multiplexed with I/O Controller lines. To enable the TWIS, the programmer must perform the following steps: • Program the I/O Controller to: – Dedicate TWD, TWCK and optionally TWALM as peripheral lines. – Define TWD, TWCK and optionally TWALM as open-drain. 518 32099A–AVR32–06/09 AT32UC3L 23.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop functioning and resume operation after the system wakes up from sleep mode. TWIS is able to wake the system from sleep mode upon address match, see Section 23.8.7 on page 526. Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state. 23.7.4 Interrupts The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS interrupts requires the interrupt controller to be programmed first. 23.7.5 Debug Operation When an external debugger forces the CPU into debug mode, the TWIS continues normal operation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 23.7.3 23.8 23.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 23-4 on page 519). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 23-3 on page 519). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 23-3. START and STOP Conditions TWD TWCK Start Stop Figure 23-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 519 32099A–AVR32–06/09 AT32UC3L 23.8.2 Operation TWIS has two modes of operation: • Slave transmitter mode • Slave receiver mode A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 23-5. Typical Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 I²C RTC Slave 2 I²C LCD Controller Slave 3 I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard 23.8.2.1 Bus Timing The Timing Register (TR) is used to control the timing of bus signals driven by TWIS. TR describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling can be selected through TR.EXP. f CLK – TWIS f prescaled = -------------------------( EXP + 1 ) ) 2 TR has the following fields: TLOWS: Prescaled clock cycles used to time SMBUS timeout TLOW:SEXT. TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT. SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT. EXP: Specifies the clock prescaler setting used for the SMBUS timeouts. 520 32099A–AVR32–06/09 AT32UC3L Figure 23-6. Bus Timing Diagram t LOW t HIGH t LOW S t t HD:STA SU:DAT t HD:DAT t t SU:DAT SU:STO P t SU:STA Sr 23.8.2.2 Setting Up and Performing a Transfer Operation of TWIS is mainly controlled by the Control Register (CR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by programming the Timing Register (TR). 2. If a DMA controller is to be used for the transfers, it must be set up. 3. The Control Register (CR) must be configured with information such as the slave address, SMBus mode, Packet Error Checking (PEC), number of bytes to transfer, and which addresses to match. The interrupt system can be set up to give interrupt request on specific events or error conditions, for example when a byte has been received. The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in SMBus mode when PEC is disabled, the NBYTES register is not used, and should be written to 0. NBYTES is updated by hardware, so in order to avoid hazards, software updates of NBYTES can only be done through writes to the NBYTES register. 23.8.2.3 Address Matching TWIS can be set up to match several different addresses. More than one address match may be enabled simultaneously, allowing TWIS to be assigned to several addresses. The address matching phase is initiated after a START or REPEATED START condition. When TWIS receives an address that generates an address match, an ACK is automatically returned to the master. In I²C mode: • The address in CR.ADR is checked for address match if CR.SMATCH is set. • The General Call address is checked for address match if CR.GCMATCH is set. In SMBus mode: 521 32099A–AVR32–06/09 AT32UC3L • The address in CR.ADR is checked for address match if CR.SMATCH is set. • The Alert Response Address is checked for address match if CR.SMAL is set. • The Default Address is checked for address match if CR.SMDA is set. • The Host Header Address is checked for address match if CR.SMHH is set. 23.8.2.4 Clock Stretching Any slave or bus master taking part in a transfer may extend the TWCK low period at any time. TWIS may extend the TWCK low period after each byte transfer if CR.STREN=1 and: • Module is in slave transmitter mode, data should be transmitted, but THR is empty, or • Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but RHR is full, or • Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains stretched until all address match bits in SR have been cleared. If CR.STREN=0 and: • Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit the value present in THR (the last transmitted byte or reset value), and set SR.URUN. • Module is in slave receiver mode, a byte has been received and placed into the internal shifter, but RHR is full: Discard the received byte and set SR.ORUN. 23.8.2.5 Bus Errors If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and TWIS waits for a new START condition. 23.8.3 Slave Transmitter Mode If TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it will enter slave transmitter mode and set SR.TRA After the address phase, the following is done: 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to transmit. This is necessary in order to know when to transmit PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Byte to transmit depends on I²C/SMBus mode and CR.PEC: – If in I²C mode or CR.PEC=0 or NBYTES!=0: TWIS waits until THR contains a valid data byte, possibly stretching low period of TWCK. SR.TXRDY indicates the state of THR. – SMBus mode and CR.PEC=1: If NBYTES=0, the generated PEC byte is automatically transmitted instead of a data byte from THR. TWCK will not be stretched by TWIS. 3. Transmit the correct data byte. Set SR.BTF when done. 4. Update NBYTES. If CR.CUP is set, NBYTES is incremented, otherwise NBYTES is decremented. 5. After each data byte has been transferred, the master transmits an ACK or NAK bit. If a NAK bit is received, transfer is finished, and TWIS will wait for a STOP or REPEATED START. If an ACK bit is received, more data should be transmitted, jump to step 2. 6. If STOP is received, SR.TCOMP and SR.STO will be set. 522 32099A–AVR32–06/09 AT32UC3L 7. If REPEATED START is received, SR.REP will be set. The TWI transfers require the receiver to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the master to pull it down in order to generate the acknowledge. The slave polls the data line during this clock pulse and sets the Not Acknowledge bit (NAK) in the Status Register if the master does not acknowledge the data byte. A NAK means that the master does not wish to receive additional data bytes. As with the other status bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER). TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel. The end of the complete transfer is marked by the SR.TCOMP bit set to one. See Figure 23-7 on page 523 and Figure 23-8 on page 523. Figure 23-7. Slave Transmitter with One Data Byte TWD S DADR W A DATA A P TCOMP TXRDY Write THR (DATA) NBYTES set to 1 STOP sent automatically (ACK received and NBYTES= 0) Figure 23-8. Master Write with Multiple Data Bytes TWD S DADR W A DATA n A DATA n+5 A DATA n+m A P TCOMP TXRDY Write THR (Data n) NBYTES set to m Write THR (Data n+1) Write THR (Data n+m) Last data sent STOP sent automatically (ACK received and NBYTES= 0) 23.8.4 Slave Receiver Mode If TWIS matches an address in which the R/W b it in the TWI address phase transfer is cleared, it will enter slave receiver mode and clear SR.TRA. After the address phase, the following is repeated: 1. If SMBus mode and PEC is used, NBYTES must be set up with the number of bytes to receive. This is necessary in order to know which of the received bytes is the PEC byte. NBYTES can also be used to count the number of bytes received if using DMA. 2. Receive a byte. Set SR.BTF when done. 523 32099A–AVR32–06/09 AT32UC3L 3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise NBYTES is decremented. NBYTES is usually configured to count downwards if PEC is used. 4. After a data byte has been received, the slave transmits an ACK or NAK bit. For ordinary data bytes, the CR.ACK field controls if an ACK or NAK should be returned. If PEC is enabled and the last byte received was a PEC byte (indicated by NBYTES=0), TWIS will automatically return an ACK if the PEC value was correct, otherwise a NAK will be returned. 5. If STOP is received, SR.TCOMP will be set. 6. If REPEATED START is received, SR.REP will be set. The TWI transfers require the receiver to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse. RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 23-9. Slave Receiver with One Data Byte TWD S DADR R A DATA N P TCOMP Write START & STOP Bit, NBYTES=1 RXRDY Read RHR Figure 23-10. Slave Receiver with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TCOMP Write START + STOP Bit NBYTES=m RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Send STOP when NBYTES=0 Read RHR DATA (n+m) 23.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The programmer can set up ring buffers for the DMA controller, containing data to transmit or free buffer space to place received data. By initializing NBYTES to 0 before a transfer, and setting 524 32099A–AVR32–06/09 AT32UC3L CR.CUP, NBYTES is incremented by 1 each time a data has been transmitted or received. This allows the programmer to detect how much data was actually transferred by the DMA system. To assure correct behavior, respect the following programming sequences: 23.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by setting the Peripheral DMA Controller TXTEN bit. 4. Wait for the Peripheral DMA Controller end TX flag. 5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller TXDIS bit. 23.8.5.2 Data Receive with the Peripheral DMA Controller 1. Initialize the receive Peripheral DMA Controller (memory pointers, size - 1, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by setting the Peripheral DMA Controller RXTEN bit. 4. Wait for the Peripheral DMA Controller end RX flag. 5. Disable the Peripheral DMA Controller by setting the Peripheral DMA Controller RXDIS bit. 23.8.6 SMBus Mode SMBus mode is enabled when CR.SMEN is written to one. SMBus mode operation is similar to I²C operation with the following exceptions: • Only 7-bit addressing can be used. • The SMBus standard describes a set of timeout values to ensure progress and throughput on the bus. These timeout values must be programmed into TR. • Transmissions can optionally include a CRC byte, called Packet Error Check (PEC). • A dedicated bus line, SMBALERT, allows a slave to get a master’s attention. • A set of addresses have been reserved for protocol handling, such as Alert Response Address (ARA) and Host Header (HH) Address. Address matching on these addresses can be enabled by configuring CR appropriately. 23.8.6.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CR.PECEN enables automatic PEC handling in the current transfer. The PEC generator is always updated on every bit transmitted or received, so that PEC handling on following linked transfers will be correct. In slave receiver mode, the master calculates a PEC value and transmits it to the slave after all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it to the PEC value it has computed itself. If the values match, the data was received correctly, and the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the slave will return a NAK value. The SR.SMBPECERR bit is set automatically if a PEC error occurred. In slave transmitter mode, the slave calculates a PEC value and transmits it to the master after all data bytes have been transmitted. Upon reception of this PEC byte, the master will com525 32099A–AVR32–06/09 AT32UC3L pare it to the PEC value it has computed itself. If the values match, the data was received correctly. If the PEC values differ, data was corrupted, and the master must take appropriate action. The PEC byte is automatically inserted in a slave transmitter transmission if PEC enabled when NBYTES reaches zero. The PEC byte is identified in a slave receiver transmission if PEC enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of data bytes in the transmission, including the PEC byte. 23.8.6.2 Timeouts The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave will leave the bus. The SR.SMBTOUT bit is also set. 23.8.6.3 SMBALERT A slave can get the master’s attention by pulling the SMBALERT line low. This is done by setting the CR.SMBAL bit. This will also enable address match on the Alert Response Address (ARA). 23.8.7 Wakeup from Sleep Modes by TWI Address Match The TWIS is able to wake the device up from sleep modes upon an address match, including modes where CLK_TWIS is stopped. If a TWI Start condition is received in a sleep mode where CLK_TWIS is stopped, TWIS will stretch TWCK until CLK_TWIS has started. The time required for restarting CLK_TWIS depends on which sleep mode the system was in. When CLK_TWIS has been restarted, the TWCK stretching is released and the slave address will be received on the TWI bus. To save power, only a limited part of the device including TWIS receives a clock at this time. If the address phase causes a TWIS address match, the entire device will be wakened and normal TWIS address match actions performed. Normal TWI transfer will then follow. If the TWIS was not addressed by the transfer, CLK_TWIS will automatically be stopped and the system will go back to the original sleep mode. 23.8.8 Identifying Bus Events This chapter lists the different bus events, and how these affects bits in the TWIS registers. This is intended to help writing drivers for the TWIS. Table 23-5. Event Slave transmitter has sent a data byte Bus Events Effect SR.THR is cleared. SR.BTF is set. The value of the ACK bit sent immediately after the data byte is given by CR.ACK. SR.RHR is set. SR.BTF is set. SR.NAK updated according to value of ACK bit received from master. None. Slave receiver has received a data byte Start+Sadr on bus, but address is to another slave Start+Sadr on bus, current slave is addressed, but address match enable bit in CR is not set None. 526 32099A–AVR32–06/09 AT32UC3L Table 23-5. Event Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set, SR.STREN and SR.SOAM are set. Repeated Start received after being addressed Stop received after being addressed Start, Repeated Start or Stop received in illegal position on bus Data is to be received in slave receiver mode, SR.STREN is set, and RHR is full Data is to be transmitted in slave receiver mode, SR.STREN is set, and THR is empty Data is to be received in slave receiver mode, SR.STREN is cleared, and RHR is full Data is to be transmitted in slave receiver mode, SR.STREN is cleared, and THR is empty SMBus timeout received Slave transmitter in SMBus PEC mode has transmitted a PEC byte, that was not identical to the PEC calculated by the master receiver. Slave receiver discovers SMBus PEC Error Bus Events Effect Correct address match bit in SR is set. SR.TRA updated according to transfer direction. Slave enters appropriate transfer direction mode and data transfer can commence. Correct address match bit in SR is set. SR.TRA updated according to transfer direction. Slave stretches TWCK immediately after transmitting the address ACK bit. TWCK remains stretched until all address match bits in SR have been cleared. Slave the enters appropriate transfer direction mode and data transfer can commence. SR.REP set. SR.TCOMP unchanged. SR.STO set. SR.TCOMP set. SR.BUSERR set. TWCK is stretched until RHR has been read. TWCK is stretched until THR has been written. TWCK is not stretched, read data is discarded. SR.ORUN is set. TWCK is not stretched, previous contents of THR is written to bus. SR.URUN is set. SR.SMBTOUT is set. TWCK and TWD are immediately released. Master receiver will transmit a NAK as usual after the last byte of a master receiver transfer. Master receiver will retry the transfer at a later time. SR.SMBPECERR is set. NAK returned after the data byte. 527 32099A–AVR32–06/09 AT32UC3L 23.9 User Interface TWIS Register Memory Map Register Control Register NBYTES Register Timing Register Receive Holding Register Transmit Holding Register Packet Error Check Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Clear Register Parameter Register Version Register Note: Register Name CR NBYTES TR RHR THR PECR SR IER IDR IMR SCR PR VR Access Read/Write Read/Write Read/Write Read-only Write-only Read-only Read-only Write-only Write-only Read-only Write-only Read-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000002 0x00000000 0x00000000 0x00000000 0x00000000 (1) (1) Table 23-6. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1c 0x20 0x24 0x28 0x2C 0x30 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 528 32099A–AVR32–06/09 AT32UC3L 23.9.1 Name: Control Register CR Read/Write 0x00 0x00000000 30 29 28 27 26 TENBIT 25 ADR[9:8] 24 Access Type: Offset: Reset Value: 31 - 23 22 21 20 ADR[7:0] 19 18 17 16 15 - 14 SOAM 13 CUP 12 ACK 11 PECEN 10 SMHH 9 SMDA 8 SMBALERT 7 SWRST 6 - 5 - 4 STREN 3 GCMATCH 2 SMATCH 1 SMEN 0 SEN • TENBIT: Ten Bit Address Match Write this bit to zero to disable Ten Bit Address Match. Write this bit to one to enable Ten Bit Address Match. • ADR: Slave Address Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise. • SOAM: Stretch Clock on Address Match Writing this bit to zero will not strech bus clock after address match. Writing this bit to one will strech bus clock after address match. • CUP: NBYTES Count Up Writing this bit to zero causes NBYTES to count down (decrement) per byte transferred. Writing this bit to one causes NBYTES to count up (increment) per byte transferred. • ACK: Slave Receiver Data Phase ACK Value Writing this bit to zero causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode. Writing this bit to one causes a high value to be returned in the ACK cycle of the data phase in slave receiver mode. • PECEN: Packet Error Checking Enable Writing this bit to zero disables SMBus PEC (CRC) generation and check. Writing this bit to one enables SMBus PEC (CRC) generation and check. • SMHH: SMBus Host Header Writing this bit to zero causes TWIS not to acknowledge the SMBus Host Header. Writing this bit to one causes TWIS to acknowledge the SMBus Host Header. • SMDA: SMBus Default Address Writing this bit to zero causes TWIS not to acknowledge the SMBus Default Address. Writing this bit to one causes TWIS to acknowledge the SMBus Default Address. • SMBALERT: SMBus Alert Writing this bit to zero causes TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response Address (ARA). Writing this bit to zero causes TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address (ARA). 529 32099A–AVR32–06/09 AT32UC3L • SWRST: Software Reset This bit will always read as 0. Writing a zero to this bit has no effect. Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable Writing this bit to zero disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. Writing this bit to one enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match Writing this bit to zero causes TWIS not to acknowledge the General Call Address. Writing this bit to one causes TWIS to acknowledge the General Call Address. • SMATCH: Slave Address Match Writing this bit to zero causes TWIS not to acknowledge the Slave Address. Writing this bit to one causes TWIS to acknowledge the Slave Address. • SMEN: SMBus Mode Enable Writing this bit to zero disables SMBus mode. Writing this bit to one enables SMBus mode. • SEN: Slave Enable Writing this bit to zero disables the slave interface. Writing this bit to one enables the slave interface. 530 32099A–AVR32–06/09 AT32UC3L 23.9.2 Name: NBYTES Register NBYTES Read/Write 0x04 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 - 19 18 17 16 15 14 13 12 - 11 10 9 8 7 6 5 4 NBYTES 3 2 1 0 • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. Can also be read to to learn the progress of the transfer. Can be incremented or decremented automatically by hardware. 531 32099A–AVR32–06/09 AT32UC3L 23.9.3 Name: Timing Register TR Read/Write 0x08 0x00000000 30 EXP 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 20 SUDAT 19 18 17 16 15 14 13 12 TTOUT 11 10 9 8 7 6 5 4 TLOWS 3 2 1 0 • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter. The counter is prescaled according to the following formula: f clkpb f prescaled = ---------------------( EXP + 1 ) 2 • SUDAT: Data Setup Cycles Non-prescaled clock cycles for data setup count. Used to time TSU_DAT. Data is driven SUDAT cycles after TWCK low detected. This timing is used for timing the ACK/NAK bits, and any data bits driven in slave transmitter mode. • TTOUT: SMBus Ttimeout Cycles Prescaled clock cycles used to time SMBus TTIMEOUT. • TLOWS: SMBus Tlow:sext Cycles Prescaled clock cycles used to time SMBus TLOW:SEXT. 532 32099A–AVR32–06/09 AT32UC3L 23.9.4 Name: Receive Holding Register RHR Read-only 0x0C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 RXDATA 3 2 1 0 • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is set, this field contains a byte received from the TWI bus. 533 32099A–AVR32–06/09 AT32UC3L 23.9.5 Name: Transmit Holding Register THR Write-only 0x10 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 TXDATA 3 2 1 0 • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here. 534 32099A–AVR32–06/09 AT32UC3L 23.9.6 Name: Packet Error Check Register PECR Read-only 0x14 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 6 5 4 PEC 3 2 1 0 • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition. Provided if the user manually wishes to control when the PEC byte is transmitted, or wishes to access the PEC value for other reasons. In ordinary operation, the PEC handling is done automatically by hardware. 535 32099A–AVR32–06/09 AT32UC3L 23.9.7 Name: Status Register SR Read-only 0x18 0x000000002 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 TRA 4 - 3 TCOMP 2 SEN 1 TXRDY 0 RXRDY • BTF: Byte Transfer Finished This bit is set when byte transfer has completed. This bit is cleared when the corresponding bit in SCR is written to one. • REP: Repeated Start Received This bit is set when REPEATED START condition received. This bit is cleared when the corresponding bit in SCR is written to one. • STO: Stop Received This bit is set when STOP condition received. This bit is cleared when the corresponding bit in SCR is written to one. • SMBDAM: SMBus Default Address Match This bit is set when received address matched SMBus Default Address. This bit is cleared when the corresponding bit in SCR is written to one. • SMBHHM: SMBus Host Header Address Match This bit is set when received address matched SMBus Host Header Address. This bit is cleared when the corresponding bit in SCR is written to one. • SMBALERTM: SMBus Alert Response Address Match This bit is set when received address matched SMBus Alert Response Address. This bit is cleared when the corresponding bit in SCR is written to one. • GCM: General Call Match This bit is set when received address matched General Call Address. This bit is cleared when the corresponding bit in SCR is written to one. • SAM: Slave Address Match This bit is set when received address matched Slave Address. This bit is cleared when the corresponding bit in SCR is written to one. • BUSERR: Bus Error This bit is set when a misplaced start or stop condition has occurred. This bit is cleared when the corresponding bit in SCR is written to one. 536 32099A–AVR32–06/09 AT32UC3L • SMBPECERR: SMBus PEC Error This bit is set when SMBus PEC error has occurred. This bit is cleared when the corresponding bit in SCR is written to one. • SMBTOUT: SMBus Timeout This bit is set when SMBus timeout has occurred. This bit is cleared when the corresponding bit in SCR is written to one. • NAK: NAK Received This bit is set when NAK was received from master during slave transmitter operation. This bit is cleared when the corresponding bit in SCR is written to one. • ORUN: Overrun This bit is set when overrun has occurred in slave receiver mode. Can only occur if CR.STREN=0. This bit is cleared when the corresponding bit in SCR is written to one. • URUN: Underrun This bit is set when underrun has occurred in slave transmitter mode. Can only occur if CR.STREN=0. This bit is cleared when the corresponding bit in SCR is written to one. • TRA: Transmitter Mode 0: The slave is in slave receiver mode. 1: The slave is in slave transmitter mode. • TCOMP: Transmission Complete This bit is set when transmission is complete. Set after receiving a STOP after being addressed. This bit is cleared when the corresponding bit in SCR is written to one. • SEN: Slave Enabled 0: The slave interface is disabled. 1: The slave interface is enabled. • TXRDY: TX Buffer Ready 0: The TX buffer is full and should not be written to. 1: The TX buffer is empty, and can accept new data. • RXRDY: RX Buffer Ready 0: No RX data ready in RHR. 1: RX data is ready to be read from RHR. 537 32099A–AVR32–06/09 AT32UC3L 23.9.8 Name: Interrupt Enable Register IER Write-only 0x1C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 - 4 - 3 TCOMP 2 - 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 538 32099A–AVR32–06/09 AT32UC3L 23.9.9 Name: Interrupt Disable Register IDR Write-only 0x20 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 - 4 - 3 TCOMP 2 - 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 539 32099A–AVR32–06/09 AT32UC3L 23.9.10 Name: Interrupt Mask Register IMR Read-only 0x24 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 - 4 - 3 TCOMP 2 - 1 TXRDY 0 RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 540 32099A–AVR32–06/09 AT32UC3L 23.9.11 Name: Status Clear Register SCR Read/Write 0x28 0x00000000 30 29 28 27 26 25 24 Access Type: Offset: Reset Value: 31 23 BTF 22 REP 21 STO 20 SMBDAM 19 SMBHHM 18 SMBALERTM 17 GCM 16 SAM 15 - 14 BUSERR 13 SMBPECERR 12 SMBTOUT 11 - 10 - 9 - 8 NAK 7 ORUN 6 URUN 5 - 4 - 3 TCOMP 2 - 1 - 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 541 32099A–AVR32–06/09 AT32UC3L 23.9.12 Name: Parameter Register PR Read-only 0x2C 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - 542 32099A–AVR32–06/09 AT32UC3L 23.9.13 Name: Version Register (VR) VR Read-only 0x30 Device-specific 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 18 VARIANT 17 16 15 - 14 - 13 - 12 - 11 10 9 8 VERSION [11:8] 7 6 5 4 VERSION [7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 543 32099A–AVR32–06/09 AT32UC3L 544 32099A–AVR32–06/09 AT32UC3L 23.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 23-7. Module Name TWIS0 TWIS1 Module Clock Name Clock Name CLK_TWIS0 CLK_TWIS1 Table 23-8. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000112 0x00000000 545 32099A–AVR32–06/09 AT32UC3L 24. Basic Pulse Width Modulation Controller (PWMA) Rev 1.0.1.0 24.1 Features • Left-aligned non-inverted 8-bit PWM • Common 8-bit timebase counter – Asynchronous clock source supported – Spread-spectrum counter to allow a constantly varying duty cycle Separate 8-bit duty cycle register per channel Synchronized channel updates – No glitches when changing the duty cycles Interlinked operation supported – Multiple channels can be updated with the same duty cycle value at a time – Up to four channels can be updated with different duty cycle values at a time Interrupt on PWM timebase overflow Incoming peripheral events supported – Pre-defined channels support incoming (increase/decrease) peripheral events from the Peripheral Event System – Increase event will increase the duty cycle by one – Decrease event will decrease the duty cycle by one One output peripheral event supported – Connected to channel 0 and asserted when the common timebase counter is equal to the programmed duty cycle for channel 0 Output PWM waveform for each channel Open drain driving on selected pins for 5V PWM operation • • • • • • • • 24.2 Overview The Basic Pulse Width Modulation Controller (PWMA) controls several pulse width modulation (PWM) channels. The number of channels is specific to the device. Each channel controls one square output PWM waveform. Characteristics of the output PWM waveforms such as period and duty cycle are configured through the user interface. All user interface registers are mapped on the peripheral bus. The duty cycle value for each channel can be set independently, while the period is determined by a common timebase counter (TC). The timebase for the counter is selected by using the allocated asynchronous Generic Clock (GCLK). The user interface for the PWMA contains handshake and synchronizing logic to ensure that no glitches occur on the output PWM waveforms while changing the duty cycle values. PWMA duty cycle values can be changed using two approaches, either an interlinked singlevalue mode or an interlinked multi-value mode. In the interlinked single-value mode, any set of channels, up to 32 channels, can be updated simultaneously with the same value while the other channels remain unchanged. In the interlinked multi-value mode, up to 4 selected channels can be updated with 4 different values while the other channels remain unchanged. Some pins can be driven in open drain mode, allowing the PWMA to generate a 5V waveform using an external pullup resistor. 546 32099A–AVR32–06/09 AT32UC3L 24.3 Block Diagram Figure 24-1. PWMA Block Diagram PB IRQ PB Clock Domain CLK_PWMA Control BUSY Interrupt Handling Adjust Channel_0 TOP TCLR SPREAD Duty Cycle Channel Select Sync Spread Spectrum Counter Timebase Counter PWM Blocks Duty Cycle Register TOFL ETV GCLK COMP Channel 0 Channel 1 Channel m GCLK Domain PWMA[m:0] 24.4 I/O Lines Description Each channel outputs one PWM waveform on one external I/O line. Table 24-1. Pin Name PWMA[n] PWMMOD[n] I/O Line Description Pin Description Output PWM waveform for one channel n Output PWM waveform for one channel n, open drain mode Type Output Output 24.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 547 32099A–AVR32–06/09 AT32UC3L 24.5.1 I/O Lines The pins used for interfacing the PWMA may be multiplexed with I/O Controller lines. The programmer must first program the I/O Controller to assign the desired PWMA pins to their peripheral function. It is only required to enable the PWMA outputs actually in use. 24.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the PWMA, the PWMA will stop functioning and resume operation after the system wakes up from sleep mode. 24.5.3 Clocks The clock for the PWMA bus interface (CLK_PWMA) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the PWMA before disabling the clock, to avoid freezing the PWMA in an undefined state. Additionally, the PWMA depends on a dedicated Generic Clock (GCLK). The GCLK can be set to a wide range of frequencies and clock sources and must be enabled in the System Control Interface (SCIF) before the PWMA can be used. 24.5.4 Interrupts The PWMA interrupt request lines are connected to the interrupt controller. Using the PWMA interrupts requires the interrupt controller to be programmed first. 24.5.5 Peripheral Events The PWMA peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 24.5.6 Debug Operation When an external debugger forces the CPU into debug mode, the PWMA continues normal operation. If the PWMA is configured in a way that requires it to be periodically serviced by the CPU through interrupts, improper operation or data loss may result during debugging. 24.6 Functional Description The PWMA embeds a number of PWM channel submodules, each providing an output PWM waveform. Each PWM channel contains a duty cycle register and a comparator. A common timebase counter for all channels determines the frequency and the period for all the PWM waveforms. 24.6.1 Enabling the PWMA Once the GCLK has been enabled, the PWMA is enabled by writing a one to the EN bit in the Control Register (CR). Timebase Counter The top value of the timebase counter defines the period of the PWMA output waveform. The timebase counter starts at zero when the PWMA is enabled and counts upwards until it reaches its effective top value (ETV). The effective top value is defined by specifying the desired number of GCLK clock cycles in the TOP field of CR (CR.TOP) in normal operation (CR.SPREAD is 24.6.2 548 32099A–AVR32–06/09 AT32UC3L zero). When the timebase counter reaches its effective top value, it restarts counting from zero. The period of the PWMA output waveform is then: T PWMA = ( ETV + 1 ) ⋅ T GCLK The timebase counter can be reset by writing a one to the Timebase Clear bit in CR (CR.TCLR). Note that this can cause a glitch to the output PWM waveforms in use. 24.6.3 Spread Spectrum Counter The spread spectrum counter allows the generation of constantly varying duty cycles on the output PWM waveforms. This is achieved by varying the effective top value of the timebase counter in a range defined by the spread spectrum counter value. When CR.SPREAD is not zero, the spread spectrum counter is enabled. Its range is defined by CR.SPREAD. It starts to count from -CR.SPREAD when the PWMA is enabled or after reset and counts upwards. When it reaches CR.SPREAD, it restarts to count from -CR.SPREAD again. The spread spectrum counter will cause the effective top value (ETV) to vary from TOPSPREAD to TOP+SPREAD. Figure 24-2 on page 549 illustrates this. This leads to a constantly varying duty cycle on the PWM output waveforms though the duty cycle values stored are unchanged. Figure 24-2. PWMA Adjusting Top Value for Timebase Counter 0xFF SPREAD TOP -SPREAD Adjusting top value range for the timerbase counter Duty Cycle 0x0 24.6.3.1 Special considerations The maximum value of the timebase counter is 255. If SPREAD is written to a value that will cause the ETV to exceed this value, the spread spectrum counter’s range will be limited to prevent the timebase counter to exceed its maximum value. If SPREAD is written to a value causing (TOP-SPREAD) to be below zero, the spread specturm counter’s range will be limited to prevent the timebase counter to count below zero. In both cases, the SPREAD value read from the Control Register will be the same value as written to the SPREAD field. 549 32099A–AVR32–06/09 AT32UC3L When writing a one to CR.TCLR, the timebase counter and the spread spectrum counter are reset at their lower limit values and the effective top value of the timebase counter will also be reset. 24.6.4 Duty Cycle and Waveform Properties Each PWM channel has its own duty cycle value (DCV) which is write-only and cannot be read out. The duty cycle value can be changed in two approaches as described in Section24.6.5. When the duty cycle value is zero, the PWM output is zero. Otherwise, the PWM output is set when the timebase counter is zero, and cleared when the timebase counter reaches the duty cycle value. This is summarized as: ⎧ low when D CV = 0 or T C > DCV PWM Waveform = ⎨ ⎩ high when T C ≤ DCV and D CV ≠ 0 Note that when increasing the duty cycle value for one channel from 0 to 1, the number of GCLK cycles when the PWM waveform is high will jump from 0 to 2. When incrementing the duty cycle value by one for any other values, the number of GCLK cycle when the waveform is high will increase by one. This is summarized in Table 24-2. Table 24-2. PMW Waveform Duty Cycles #Clock Cycles When Waveform is High 0 2 3 ... ETV ETV+1 #Clock Cycles When Waveform is Low ETV+1 ETV-1 ETV-2 ... 1 0 Duty Cycle Value 0 1 2 ... ETV-1 ETV Every other output PWM waveform toggles on the negative edge of the GCLK instead of the positive edge. This is to avoid too many I/O toggling simultaneously on the output I/O lines. 24.6.5 24.6.5.1 Updating Duty Cycle Values Interlinked Single Value PWM Operation The PWM channels can be interlinked to allow multiple channels to be updated simultaneously with the same duty cycle value. This value must be written to the Interlinked Single Value Duty (ISDUTY) register. Each channel has a corresponding enabling bit in the Interlinked Single Value Channel Set (ISCHSET) register(s). When a bit is written to one in the ISCHSET register, the duty cycle register for the corresponding channel will be updated with the value stored in the ISDUTY register. It can only be updated when the READY bit in the Status Register (SR.READY) is one, indicating that the PWMA is ready for writing. Figure 24-3 on page 551 shows the writing procedure. It is thus possible to update the duty cycle values for up to 32 PWM channels within one ISCHSET register at a time. 550 32099A–AVR32–06/09 AT32UC3L Figure 24-3. Interlinked Single Value PWM Operation Flow ISDUTY ISCHSET Write Enable DUTYm ... DUTY1 DUTY0 24.6.5.2 Interlinked Multiple Value PWM Operation The interlinked multiple value PWM operation allows up to four channels to be updated simultaneously with different duty cycle values. These duty cycle values must be written to the IMDUTY register. The index number of the four channels to be updated is written to the four SEL fields in the Interlinked Multiple Value Channel Select (IMCHSEL) register (IMCHSEL.SEL). When the IMCHSEL register is written, the values stored in the IMDUTY register are synchronized to the duty cycle registers for the channels selected by the SEL fields. Figure 24-4 on page 551 shows the writing procedure. Note that only writes to the implemented channels will be effective. If one of the IMCHSEL.SEL fields points to a non-existing channel, the corresponding value in the IMDUTY register will not be written. If the same channel is specified in multiple IMCHSEL.SEL fields, the channel will be updated with the value stored in the corresponding upper field of the IMDUTY register. Figure 24-4. Interlinked Multiple Value PWM Operation Flow IMDUTY IMCHSEL MUX DUTYm ... DUTY1 DUTY0 24.6.6 Open Drain Mode Some pins can be used in open drain mode, allowing the PWMA waveform to toggle between 0V and up to 5V on these pins. In this mode the PWMA will drive the pin to zero or leave the output open. An external pullup can be used to pull the pin up to the desired voltage. To enable open drain mode on a pin the PWMAOD function must be selected instead of the PWMA function in the I/O Controller. Please refer to the Module Configuration chapter for information about which pins are available in open drain mode. 24.6.7 Synchronization Both the timebase counter and the spread spectrum counter can be reset and the duty cycle registers can be written through the user interface of the module. This requires a synchronization between the PB and GCLK clock domains, which takes a few clock cycles of each clock domain. The BUSY bit in SR indicates when the synchronization is ongoing. Writing to the module while the BUSY bit is set will result in discarding the new value. 551 32099A–AVR32–06/09 AT32UC3L Note that the duty cycle registers will not be updated with the new values until the timebase counter reaches its top value, in order to avoid glitches. The BUSY bit in SR will always be set during this updating and synchronization period. 24.6.8 Interrupts When the timebase counter overflows, the Timebase Overflow bit in the Status Register (SR.TOFL) is set. If the corresponding bit in the Interrupt Mask Register (IMR) is set, an interrupt request will be generated. Since the user needs to wait until the user interface is available between each write due to synchronization, a READY bit is provided in SR, which can be used to generate an interrupt request. The interrupt request will be generated if the corresponding bit in IMR is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in SR is cleared by writing a one to the corresponding bit in the Status Clear Register (SCR). 24.6.9 24.6.9.1 Peripheral Events Input Peripheral Events The pre-defined channels support input peripheral events from the Peripheral Event System. An increase event (event_incr) will increase the duty cycle value by one, and a decrease event (event_decr) will decrease the duty cycle value by one. If an increase event and a decrease event occur at the same time, the duty cycle value will not be changed. The number of channels supporting input peripheral events is device specific. Please refer to the Module Configuration section at the end of this chapter for details. Input peripheral events must be enabled by writing a one to the corresponding bit in the Chanel Event Enable Registers (CHEERs) before peripheral events can be used to control the duty cycle value. Each bit in the register corresponds to one channel, where bit 0 corresponds to channel 0 and so on. Both the increase and decrease events are enabled for the corresponding channel when a bit in the CHEER register is set. 24.6.9.2 Output Peripheral Event The PWMA also supports one output peripheral event (event_ch0) to the Peripheral Event System. This output peripheral event is connected to channel 0 and will be asserted when the timebase counter reaches the duty cycle value for channel 0. This output event is always enabled. 552 32099A–AVR32–06/09 AT32UC3L 24.7 User Interface PWMA Register Memory Map Register Control Register Interlinked Single Value Duty Register Interlinked Multiple Value Duty Register Interlinked Multiple Value Channel Select Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Status Clear Register Parameter Register Version Register Interlinked Single Value Channel Set m Channel Event Enable Register m Register Name CR ISDUTY IMDUTY IMCHSEL IER IDR IMR SR SCR PARAMETER VERSION ISCHSETm CHEERm Access Read/Write Write-only Write-only Write-only Write-only Write-only Read-only Read-only Write-only Read-only Read-only Write-only Read/Write Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 - (1) - (1) 0x00000000 0x00000000 Table 24-3. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x30+m*0x10 0x38+m*0x10 Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 553 32099A–AVR32–06/09 AT32UC3L 24.7.1 Name: Control Register CR Read/Write 0x00 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 19 18 SPREAD 17 16 15 14 13 12 TOP 11 10 9 8 7 - 6 - 5 - 4 - 3 - 2 - 1 TCLR 0 EN • SPREAD: Spread Spectrum Limit Value The spread spectrum limit value, together with the TOP field, defines the range for the spread spectrum counter. It is introduced in order to achieve constant varying duty cycles on the output PWM waveforms. Refer to Section24.6.3 for more information. • TOP: Timebase Counter Top Value The top value for the timebase counter. The effective top value of the timebase counter is defined by both the TOP and the SPREAD fields. Refer to Section24.6.2 for more information. • TCLR: Timebase Clear Writing a zero to this bit has no effect. Writing a one to this bit will clear the timebase counter. This bit is always read as zero. • EN: Module Enable 0: The PWMA is disabled 1: The PWMA is enabled 554 32099A–AVR32–06/09 AT32UC3L 24.7.2 Name: Interlinked Single Value Duty Register ISDUTY Write-only 0x04 0x00000000 30 22 14 6 29 21 13 5 28 20 12 4 DUTY 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 Access Type: Offset: Reset Value: 31 23 15 7 • DUTY: Duty Cycle Value The duty cycle value written to this field is written simultaneously to all channels selected in the ISCHSET registers. If the value zero is written to DUTY all affected channels will be disabled. In this state the output waveform will be zero all the time. 555 32099A–AVR32–06/09 AT32UC3L 24.7.3 Name: Interlinked Multiple Value Duty Register IMDUTY Write-only 0x08 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DUTY3 27 26 25 24 23 22 21 20 DUTY2 19 18 17 16 15 14 13 12 DUTY1 11 10 9 8 7 6 5 4 DUTY0 3 2 1 0 • DUTYn: Duty Cycle The value written to DUTY field n will be written to the PWMA channel selected by the corresponding SEL field in the IMCHSEL register. If the value zero is written to DUTY all affected channels will be disabled. In this state the output waveform will be zero all the time. 556 32099A–AVR32–06/09 AT32UC3L 24.7.4 Name: Interlinked Multiple Value Channel Select IMCHSEL Write-only 0x0C 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 SEL3 27 26 25 24 23 22 21 20 SEL2 19 18 17 16 15 14 13 12 SEL1 11 10 9 8 7 6 5 4 SEL0 3 2 1 0 • SELn: Channel Select The duty cycle of the PWMA channel SELn will be updated with the value in the DUTYn field of the IMDUTY register when IMCHSEL is written. If SELn points to a non-implemented channel, the write will be discarded. Note: The duty registers will be updated with the value stored in the IMDUTY register when the IMCHSEL register is written. Synchronization takes place immeidately when an IMCHSEL register is written. The duty cycle registers will, however, not be updated until the synchronization is completed and the timebase counter reaches its top value in order to avoid glitches. 557 32099A–AVR32–06/09 AT32UC3L 24.7.5 Name: Interrupt Enable Register IER Write-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 READY 25 17 9 1 - 24 16 8 0 TOFL Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR. 558 32099A–AVR32–06/09 AT32UC3L 24.7.6 Name: Access Type: Offset: Reset Value: Interrupt Disable Register IDR Write-only 0x14 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 READY 25 17 9 1 - 24 16 8 0 TOFL Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR. 559 32099A–AVR32–06/09 AT32UC3L 24.7.7 Name: Access Type: Offset: Reset Value: Interrupt Mask Register IMR Read-only 0x18 0x00000000 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 READY 25 17 9 1 - 24 16 8 0 TOFL 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 560 32099A–AVR32–06/09 AT32UC3L 24.7.8 Name: Status Register SR Read-only 0x1C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 BUSY 26 18 10 2 READY 25 17 9 1 - 24 16 8 0 TOFL • BUSY: Interface Busy This bit is automatically cleared when the interface is no longer busy. This bit is set when the user interface is busy and will not respond to new write operations. • READY: Interface Ready This bit is cleared by writing a one to the corresponding bit in the SCR register. This bit is set when the BUSY bit has a 1-to-0 transition. • TOFL: Timebase Overflow This bit is cleared by writing a one to corresponding bit in the SCR register. This bit is set when the timebase counter has wrapped at its top value. 561 32099A–AVR32–06/09 AT32UC3L 24.7.9 Name: Status Clear Register SCR Write-only 0x20 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 1 3 - 26 18 10 2 READY 25 17 9 1 - 24 16 8 0 TOFL Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. This register always reads as zero. 562 32099A–AVR32–06/09 AT32UC3L 24.7.10 Name: Parameter Register PARAMETER Read-only 0x24 - Access Type: Offset: Reset Value: 31 23 15 - 30 22 14 - 29 21 13 - 28 20 12 - 27 19 11 - 26 18 10 - 25 17 9 - 24 16 8 - 7 6 5 4 CHANNELS 3 2 1 0 • CHANNELS: Channels Implemented This field contains the number of channels implemented on the device. 563 32099A–AVR32–06/09 AT32UC3L 24.7.11 Name: Version Register VERSION Read-only 0x28 - Access Type: Offset: Reset Value: 31 23 15 - 30 22 14 - 29 21 13 - 28 20 12 - 27 19 26 18 VARIANT 25 17 24 16 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 564 32099A–AVR32–06/09 AT32UC3L 24.7.12 Name: Interlinked Single Value Channel Set ISCHSETm Write-only 0x30+m*0x10 0x00000000 30 29 28 SET 23 22 21 20 SET 15 14 13 12 SET 7 6 5 4 SET • SET: Single Value Channel Set If the bit n in SET is one, the duty cycle of PWMA channel n will be updated with the value written to ISDUTY. If more than one ISCHSET register is present, ISCHSET0 controls channels 31 to 0 and ISCHSET1 controls channels 63 to 32. Note: The duty registers will be updated with the value stored in the ISDUTY register when any ISCHSETm register is written. Synchronization takes place immeidately when an ISCHSET register is written. The duty cycle registers will, however, not be updated until the synchronization is completed and the timebase counter reaches its top value in order to avoid glitches. 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Access Type: Offset: Reset Value: 31 565 32099A–AVR32–06/09 AT32UC3L 24.7.13 Name: Channel Event Enable Register CHEERm Read/Write 0x38+m*0x10 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 CHEE 27 26 25 24 23 22 21 20 CHEE 19 18 17 16 15 14 13 12 CHEE 11 10 9 8 7 6 5 4 CHEE 3 2 1 0 • CHEE: Channel Event Enable 0: The input peripheral event for the corresponding channel is disabled. 1: The input peripheral event for the corresponding channel is enabled. Both increase and decrease events for channel n are enabled if bit n is one. If more than one CHEER register is present, CHEER0 controls channels 31-0 and CHEER1 controls channels 64-32 and so on. 566 32099A–AVR32–06/09 AT32UC3L 24.8 Module Configuration The specific configuration for each PWMA instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 24-4. Feature Number of PWM channels Channels supporting incoming peripheral events PWMA channels with Open Drain mode PWMA Configuration PWMA 36 0, 6, 8, 9, 11, 14, 19, and 20 21, 27, and 28 Table 24-5. Module Name PWMA PWMA Clock Name Clock Name CLK_PWMA Table 24-6. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000101 0x00000024 567 32099A–AVR32–06/09 AT32UC3L 25. Timer/Counter (TC) Rev: 2.2.3.1.1 25.1 Features • Three 16-bit Timer Counter channels • A wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse width modulation – Up/down capabilities Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals Internal interrupt signal Two global registers that act on all three TC channels Peripheral event input on all A lines in capture mode • • • • 25.2 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs, and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The TC block has two global registers which act upon all three TC channels. The Block Control Register (BCR) allows the three channels to be started simultaneously with the same instruction. The Block Mode Register (BMR) defines the external clock inputs for each channel, allowing them to be chained. 568 32099A–AVR32–06/09 AT32UC3L 25.3 Block Diagram Figure 25-1. TC Block Diagram TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIMER_CLOCK3 TCLK1 TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOA1 TIOA2 XC0 XC1 XC2 TC0XC0S SYNC INT0 Timer/Counter Channel 0 TIOA I/O Contr oller CLK0 CLK1 CLK2 A0 B0 TIOA0 TIOB TIOB0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC INT1 Timer/Counter Channel 1 TIOA TIOB TIOA1 TIOB1 A1 B1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB A2 B2 TIOB2 SYNC INT2 Timer Count er Interrupt Controller 25.4 I/O Lines Description Table 25-1. Pin Name CLK0-CLK2 A0-A2 B0-B2 I/O Lines Description Description External Clock Input I/O Line A I/O Line B Type Input Input/Output Input/Output 25.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 25.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines. The user must first program the I/O Controller to assign the TC pins to their peripheral functions. 569 32099A–AVR32–06/09 AT32UC3L When using the TIOA lines as inputs the user must make sure that no peripheral events are generated on the line. Refer to the Peripheral Event System chapter for details. 25.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TC before disabling the clock, to avoid freezing the TC in an undefined state. 25.5.4 Interrupts The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt requires the interrupt controller to be programmed first. 25.5.5 Peripheral Events The TC peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. Debug Operation The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps peripherals running in debug operation. 25.5.3 25.5.6 25.6 25.6.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Figure 25-3 on page 585. Channel I/O Signals As described in Figure 25-1 on page 569, each Channel has the following I/O signals. Table 25-2. Channel I/O Signals Description Signal Name XC0, XC1, XC2 TIOA Channel Signal TIOB INT SYNC Description External Clock Inputs Capture mode: Timer Counter Input Waveform mode: Timer Counter Output Capture mode: Timer Counter Input Waveform mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal 25.6.1.1 Block/Channel 25.6.1.2 16-bit counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the Counter Overflow Status bit in the Channel n Status Register (SRn.COVFS) is set. 570 32099A–AVR32–06/09 AT32UC3L The current value of the counter is accessible in real time by reading the Channel n Counter Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 25.6.1.3 Clock selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals A0, A1 or A2 for chaining by writing to the BMR register. See Figure 25-2 on page 571. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5. See the Module Configuration Chapter for details about the connection of these clock sources. • External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details about the connection of these clock sources. This selection is made by the Clock Selection field in the Channel n Mode Register (CMRn.TCCLKS). The selected clock can be inverted with the Clock Invert bit in CMRn (CMRn.CLKI). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The Burst Signal Selection field in the CMRn register (CMRn.BURST) defines this signal. Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC. Figure 25-2. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 571 32099A–AVR32–06/09 AT32UC3L 25.6.1.4 Clock control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 25-3 on page 572. • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In Waveform mode, it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare bit in CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions have no effect: only a CLKEN command in CCRn can re-enable the clock. When the clock is enabled, the Clock Enabling Status bit is set in SRn (SRn.CLKSTA). • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. In Capture mode the clock can be stopped by an RB load event if the Counter Clock Stopped with RB Loading bit in CMRn is written to one (CMRn.LDBSTOP). In Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped with RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop commands have effect only if the clock is enabled. Figure 25-3. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 25.6.1.5 TC operating modes Each channel can independently operate in two different modes: • Capture mode provides measurement on signals. • Waveform mode provides wave generation. The TC operating mode selection is done by writing to the Wave bit in the CCRn register (CCRn.WAVE). In Capture mode, TIOA and TIOB are configured as inputs. 572 32099A–AVR32–06/09 AT32UC3L In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 25.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: each channel has a software trigger, available by writing a one to the Software Trigger Command bit in CCRn (CCRn.SWTRG). • SYNC: each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing a one to the Synchro Command bit in the BCR register (BCR.SYNC). • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn (CMRn.CPCTRG) is written to one. The channel can also be configured to have an external trigger. In Capture mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform mode, an external event can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external event can then be programmed to perform a trigger by writing a one to the External Event Trigger Enable bit in CMRn (CMRn.ENETRG). If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 25.6.1.7 Peripheral events on TIOA inputs The TIOA input lines are ored internally with peripheral events from the Peripheral Event System. To capture using events the user must ensure that the corresponding pin functions for the TIOA line are disabled. When capturing on the external TIOA pin the user must ensure that no peripheral events are generated on this pin. Capture Operating Mode This mode is entered by writing a zero to the CMRn.WAVE bit. Capture mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 25-4 on page 575 shows the configuration of the TC channel when programmed in Capture mode. 25.6.2.1 Capture registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. 25.6.2 573 32099A–AVR32–06/09 AT32UC3L The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA edge for the loading of the RB register. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in SRn (SRn.LOVRS). In this case, the old value is overwritten. 25.6.2.2 Trigger conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The TIOA or TIOB External Trigger Selection bit in CMRn (CMRn.ABETRG) selects TIOA or TIOB input signal as an external trigger. The External Trigger Edge Selection bit in CMRn (CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trigger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled. 574 32099A–AVR32–06/09 32099A–AVR32–06/09 TCCLKS CLKI CLKSTA CLKEN CLKDIS TIMER_CLOCK1 Q Q S R R Figure 25-4. Capture Mode TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 S LDBSTOP BURST LDBDIS Register C 1 16-bit Counter CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LD A R LDRB CPCTRG Capture Register A SWTRG Capture Register B Compare RC = SYNC MTIOB TIOB CPCS COVFS LOVRS LDRBS LDRAS ETRGS SR MTIOA If RA is not Loaded or RB is Loaded Edge Detector If RA is Loaded Edge Detector IMR TIOA Timer/Counter Channel INT AT32UC3L 575 AT32UC3L 25.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event. Figure 25-5 on page 577 shows the configuration of the TC channel when programmed in Waveform operating mode. 25.6.3.1 Waveform selection Depending on the Waveform Selection field in CMRn (CMRn.WAVSEL), the behavior of CVn varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 576 32099A–AVR32–06/09 O utput Contr oller EN G ETR SR Edge Detector IMR TIOB BSWTRG Timer/Counter Channel AT32UC3L 577 INT O utput Cont r oller 32099A–AVR32–06/09 TCCLKS CLKSTA CLKDIS CLKI Q R Q R CPCSTOP AEEVT S CPCDIS S ACPA MTIOA CLKEN ACPC TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 Figure 25-5. Waveform Mode TIOA XC2 BURST Register A WAVSEL Register B Register C ASWTRG 1 16-bit Counter CLK OVF Compare RA = Compare RB = Compare RC = SWTRG RESET BCPC T rig BCPB WAVSEL E VT E BEEVT E VTEDG E CPCS CPBS CPAS ETRGS COVFS MTIOB SYNC TIOB AT32UC3L 25.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 25-6 on page 578. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 25-7 on page 579. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 25-6. WAVSEL= 0 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 578 32099A–AVR32–06/09 AT32UC3L Figure 25-7. WAVSEL= 0 With Trigger Counter cleared by compare match with 0xFFFF Counter Value 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples TIOB Time TIOA 25.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 25-8 on page 580. It is important to note that CVn can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 25-9 on page 580. In addition, RC Compare can stop the counter clock (CMRn.CPCSTOP) and/or disable the counter clock (CMRn.CPCDIS = 1). 579 32099A–AVR32–06/09 AT32UC3L Figure 25-8. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 25-9. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 25.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of CVn is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 25-10 on page 581. 580 32099A–AVR32–06/09 AT32UC3L A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 25-11 on page 581. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 25-10. WAVSEL = 1 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 25-11. WAVSEL = 1 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC Counter decremented by compare match with 0xFFFF RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 581 32099A–AVR32–06/09 AT32UC3L 25.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 25-12 on page 582. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 25-13 on page 583. RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 25-12. WAVSEL = 3 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 582 32099A–AVR32–06/09 AT32UC3L Figure 25-13. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 25.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.EEVT) selects the external trigger. The External Event Edge Selection field in CMRn (CMRn.EEVTEDG) defines the trigger edge for each of the possible external triggers (rising, falling or both). If CMRn.EEVTEDG is written to zero, no external event is defined. If TIOB is defined as an external event signal (CMRn.EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by writing a one to the CMRn.ENETRG bit. As in Capture mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the CMRn.WAVSEL field. 25.6.3.7 Output controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: • software trigger • external event • RC compare RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the following fields in CMRn: • RC Compare Effect on TIOB (CMRn.BCPC) 583 32099A–AVR32–06/09 AT32UC3L • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.ACPA) 584 32099A–AVR32–06/09 AT32UC3L 25.7 User Interface TC Register Memory Map Register Channel 0 Control Register Channel 0 Mode Register Channel 0 Counter Value Channel 0 Register A Channel 0 Register B Channel 0 Register C Channel 0 Status Register Interrupt Enable Register Channel 0 Interrupt Disable Register Channel 0 Interrupt Mask Register Channel 1 Control Register Channel 1 Mode Register Channel 1 Counter Value Channel 1 Register A Channel 1 Register B Channel 1 Register C Channel 1 Status Register Channel 1 Interrupt Enable Register Channel 1 Interrupt Disable Register Channel 1 Interrupt Mask Register Channel 2 Control Register Channel 2 Mode Register Channel 2 Counter Value Channel 2 Register A Channel 2 Register B Channel 2 Register C Channel 2 Status Register Channel 2 Interrupt Enable Register Channel 2 Interrupt Disable Register Channel 2 Interrupt Mask Register Block Control Register Block Mode Register Notes: Register Name CCR0 CMR0 CV0 RA0 RB0 RC0 SR0 IER0 IDR0 IMR0 CCR1 CMR1 CV1 RA1 RB1 RC1 SR1 IER1 IDR1 IMR1 CCR2 CMR2 CV2 RA2 RB2 RC2 SR2 IER2 IDR2 IMR2 BCR BMR Access Write-only Read/Write Read-only Read/Write(1) Read/Write(1) Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write Read-only Read/Write Read/Write (1) (1) Table 25-3. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x40 0x44 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x80 0x84 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xC0 0xC4 Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 00x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write Read-only Read/Write(1) Read/Write(1) Read/Write Read-only Write-only Write-only Read-only Write-only Read/Write 1. Read-only if CMRn.WAVE is zero 585 32099A–AVR32–06/09 AT32UC3L 25.7.1 Name: Channel Control Register CCR Write-only 0x00 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 SWTRG 1 CLKDIS 0 CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started. 0: Writing a zero to this bit has no effect. • CLKDIS: Counter Clock Disable Command 1: Writing a one to this bit will disable the clock. 0: Writing a zero to this bit has no effect. • CLKEN: Counter Clock Enable Command 1: Writing a one to this bit will enable the clock if CLKDIS is not one. 0: Writing a zero to this bit has no effect. 586 32099A–AVR32–06/09 AT32UC3L 25.7.2 Name: Channel Mode Register: Capture Mode CMR Read/Write 0x04 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 LDRB 18 17 LDRA 16 15 WAVE 14 CPCTRG 13 - 12 - 11 - 10 ABETRG 9 ETRGEDG 8 7 LDBDIS 6 LDBSTOP 5 BURST 4 3 CLKI 2 1 TCCLKS 0 • LDRB: RB Loading Selection LDRB 0 1 2 3 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • LDRA: RA Loading Selection LDRA 0 1 2 3 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • WAVE 1: Capture mode is disabled (Waveform mode is enabled). 0: Capture mode is enabled. • CPCTRG: RC Compare Trigger Enable 1: RC Compare resets the counter and starts the counter clock. 0: RC Compare has no effect on the counter and its clock. • ABETRG: TIOA or TIOB External Trigger Selection 1: TIOA is used as an external trigger. 587 32099A–AVR32–06/09 AT32UC3L 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG 0 1 2 3 Edge none rising edge falling edge each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. • LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs. • BURST: Burst Signal Selection BURST 0 1 2 3 Burst Signal Selection The clock is not gated by an external signal XC0 is ANDed with the selected clock XC1 is ANDed with the selected clock XC2 is ANDed with the selected clock • CLKI: Clock Invert 1: The counter is incremented on falling edge of the clock. 0: The counter is incremented on rising edge of the clock. • TCCLKS: Clock Selection TCCLKS 0 1 2 3 4 5 6 7 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 588 32099A–AVR32–06/09 AT32UC3L 25.7.3 Name: Channel Mode Register: Waveform Mode CMR Read/Write 0x04 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 BSWTRG 30 29 BEEVT 28 27 BCPC 26 25 BCPB 24 23 ASWTRG 22 21 AEEVT 20 19 ACPC 18 17 ACPA 16 15 WAVE 14 WAVSEL 13 12 ENETRG 11 EEVT 10 9 EEVTEDG 8 7 CPCDIS 6 CPCSTOP 5 BURST 4 3 CLKI 2 1 TCCLKS 0 • BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 1 2 3 Effect none set clear toggle • BEEVT: External Event Effect on TIOB BEEVT 0 1 2 3 Effect none set clear toggle 589 32099A–AVR32–06/09 AT32UC3L • BCPC: RC Compare Effect on TIOB BCPC 0 1 2 3 Effect none set clear toggle • BCPB: RB Compare Effect on TIOB BCPB 0 1 2 3 Effect none set clear toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 1 2 3 Effect none set clear toggle • AEEVT: External Event Effect on TIOA AEEVT 0 1 2 3 Effect none set clear toggle • ACPC: RC Compare Effect on TIOA ACPC 0 1 2 3 Effect none set clear toggle 590 32099A–AVR32–06/09 AT32UC3L • ACPA: RA Compare Effect on TIOA ACPA 0 1 2 3 Effect none set clear toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled). • WAVSEL: Waveform Selection WAVSEL 0 1 2 3 Effect UP mode without automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare • ENETRG: External Event Trigger Enable 1: The external event resets the counter and starts the counter clock. 0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. • EEVT: External Event Selection EEVT 0 1 2 3 Note: Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input(1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • EEVTEDG: External Event Edge Selection EEVTEDG 0 1 2 3 Edge none rising edge falling edge each edge • CPCDIS: Counter Clock Disable with RC Compare 1: Counter clock is disabled when counter reaches RC. 0: Counter clock is not disabled when counter reaches RC. • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 591 32099A–AVR32–06/09 AT32UC3L 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST 0 1 2 3 Burst Signal Selection The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock. 0: Counter is incremented on rising edge of the clock. • TCCLKS: Clock Selection TCCLKS 0 1 2 3 4 5 6 7 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 592 32099A–AVR32–06/09 AT32UC3L 25.7.4 Name: Channel Counter Value Register CV Read-only 0x10 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 CV[15:8] 11 10 9 8 7 6 5 4 CV[7:0] 3 2 1 0 • CV: Counter Value CV contains the counter value in real time. 593 32099A–AVR32–06/09 AT32UC3L 25.7.5 Name: Channel Register A RA Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 0x14 + n * 0X40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RA[15:8] 11 10 9 8 7 6 5 4 RA[7:0] 3 2 1 0 • RA: Register A RA contains the Register A value in real time. 594 32099A–AVR32–06/09 AT32UC3L 25.7.6 Name: Channel Register B RB Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 0x18 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RB[15:8] 11 10 9 8 7 6 5 4 RB[7:0] 3 2 1 0 • RB: Register B RB contains the Register B value in real time. 595 32099A–AVR32–06/09 AT32UC3L 25.7.7 Name: Channel Register C RC Read/Write 0x1C + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 RC[15:8] 11 10 9 8 7 6 5 4 RC[7:0] 3 2 1 0 • RC: Register C RC contains the Register C value in real time. 596 32099A–AVR32–06/09 AT32UC3L 25.7.8 Name: Channel Status Register SR Read-only 0x20 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 MTIOB 17 MTIOA 16 CLKSTA 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts. • MTIOB: TIOB Mirror 1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven high. 0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven low. • MTIOA: TIOA Mirror 1: TIOA is high. If CMRn.WAVE is zero, this means that TIOA pin is high. If CMRn.WAVE is one, this means that TIOA is driven high. 0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven low. • CLKSTA: Clock Enabling Status 1: This bit is set when the clock is enabled. 0: This bit is cleared when the clock is disabled. • ETRGS: External Trigger Status 1: This bit is set when an external trigger has occurred. 0: This bit is cleared when the SR register is read. • LDRBS: RB Loading Status 1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • LDRAS: RA Loading Status 1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • CPCS: RC Compare Status 1: This bit is set when an RC Compare has occurred. 0: This bit is cleared when the SR register is read. 597 32099A–AVR32–06/09 AT32UC3L • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero. 0: This bit is cleared when the SR register is read. • COVFS: Counter Overflow Status 1: This bit is set when a counter overflow has occurred. 0: This bit is cleared when the SR register is read. 598 32099A–AVR32–06/09 AT32UC3L 25.7.9 Name: Channel Interrupt Enable Register IER Write-only 0x24 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 599 32099A–AVR32–06/09 AT32UC3L 25.7.10 Name: Channel Interrupt Disable Register IDR Write-only 0x28 + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 600 32099A–AVR32–06/09 AT32UC3L 25.7.11 Name: Channel Interrupt Mask Register IMR Read-only 0x2C + n * 0x40 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 ETRGS 6 LDRBS 5 LDRAS 4 CPCS 3 CPBS 2 CPAS 1 LOVRS 0 COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 601 32099A–AVR32–06/09 AT32UC3L 25.7.12 Name: Block Control Register BCR Write-only 0xC0 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 0: Writing a zero to this bit has no effect. 602 32099A–AVR32–06/09 AT32UC3L 25.7.13 Name: Block Mode Register BMR Read/Write 0xC4 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 TC2XC2S 4 3 TC1XC1S 2 1 TC0XC0S 0 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 1 2 3 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 1 2 3 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 Signal Connected to XC0 TCLK0 603 32099A–AVR32–06/09 AT32UC3L 1 2 3 none TIOA1 TIOA2 604 32099A–AVR32–06/09 AT32UC3L 25.8 25.8.1 Module Configuration Clock Connections Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 25-4. Module TC0 Timer/Counter Clock Connections Source Internal Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 External XC0 XC1 XC2 Connection 32 KHz oscillator clock (CLK_32K) PBA Clock / 2 PBA Clock / 8 PBA Clock / 32 PBA Clock / 128 See Table 3-1 on page 8 TC1 Internal TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 32 KHz oscillator clock (CLK_32K) PBA Clock / 2 PBA Clock / 8 PBA Clock / 32 PBA Clock / 128 See Table 3-1 on page 8 External XC0 XC1 XC2 TC2 Internal TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 32 KHz oscillator clock (CLK_32K) PBA Clock / 2 PBA Clock / 8 PBA Clock / 32 PBA Clock / 128 See Table 3-1 on page 8 External XC0 XC1 XC2 605 32099A–AVR32–06/09 AT32UC3L 26. ADC Interface (ADCIFB) Rev.:1.0.1.0 26.1 Features • Multi-channel Analog-to-Digital Converter with up to 12-bit resolution • Enhanced Resolution Mode – 11-bit resolution obtained by interpolating 4 samples – 12-bit resolution obtained by interpolating 16 samples Pseudorandom Noise Generator used for Enhanced Resolution Mode Glueless interface with resistive touch screen panel, allowing – Touch Screen position measurement – Pen detection and pen loss detection Integrated enhanced sequencer – ADC Mode – Touch Screen Mode Numerous trigger sources – Software – Embedded 16-bit timer for periodic trigger – Pen detect trigger – Continuous trigger – External trigger, rising, falling or any-edge trigger – Peripheral event trigger ADC Sleep Mode for low power ADC applications Programmable ADC timings – Programmable ADC clock – Programmable startup time • • • • • • 26.2 Overview The ADC Interface (ADCIFB) converts analog input voltages to digital values. The ADCIFB is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). The conversions extend from 0V to ADVREF. The ADCIFB supports 8-bit, 10-bit, 11-bit, or 12-bit resolution mode, and conversion results are reported in a common register for all channels. The 11-bit and 12-bit resolution modes are obtained by interpolating multiple samples to acquire better accuracy. For 11-bit mode 4 samples are used, which gives an effective sample rate of 1/4 of the actual sample frequency. For 12-bit mode 16 samples are used, giving a effective sample rate of 1/16 of actual. This arrangement allows conversion speed to be traded for better accuracy. Conversions can be started for all enabled channels, either by a software trigger, by detection of a level change on the external trigger pin (ADTRG), or by an integrated programmable timer. When the Touch Screen ADC Mode is enabled, an integrated sequencer automatically configures the pad control signals and performs touch screen conversions. The ADCIFB also integrates an ADC Sleep Mode, a Pen-Detect Mode, and an Analog Compare Mode, and connects with one Peripheral DMA Controller channel. These features reduce both power consumption and processor intervention. 606 32099A–AVR32–06/09 AT32UC3L 26.3 Block Diagram Figure 26-1. ADCIFB Block Diagram VDDANA Pseudorandom Noise Generator ADCIFB RND ADTRG Trigger Timer CLK_ADCIFB I/O Controller Touch Screen Sequencer ADC Control Logic DP0 DP1 User Interface Successive Approximation Register Analog-to-Digital Converter DMA Request Peripheral Bus AD1 AD2 AD3 .... ADn Interrupt Request ADVREF Analog Multiplexer AD0 607 32099A–AVR32–06/09 AT32UC3L 26.4 I/O Lines Description I/O Lines Description Description Analog power supply Reference voltage External trigger A pseudorandom output Drive Pin 0 for Touch Screen top channel (Xp) Drive Pin 1 for Touch Screen right channel (Yp) Analog input channels 0 to n Type Power Analog Digital Digital Digital Digital Analog Table 26-1. Pin Name VDDANA ADVREF ADTRG RND DP0 DP1 AD0-ADn 26.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 26.5.1 I/O Lines The analog input pins can be multiplexed with I/O Controller lines. The user must make sure the I/O Controller is configured correctly to allow the ADCIFB access to the AD pins before the ADCIFB is instructed to start converting data. If the user fails to do this the converted data may be wrong. The number of analog inputs is device dependent, please refer to the ADCIFB Module Configuration chapter for the number of available AD inputs on the current device. The VDDANA and ADVREF pins must be connected correctly prior to using the ADCIFB. Failing to do so will result in invalid ADC operation. See the Electrical Characteristics chapter for details. If the ADTRG, RND, DP0, and DP1 pins are to be used in the application, the user must configure the I/O Controller to assign the needed pins to the ADCIFB function. 26.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the ADCIFB, the ADCIFB will stop functioning and resume operation after the system wakes up from sleep mode. If the Periperhal Event System is configured to send asynchronous peripheral events to the ADCIFB and the clock used by the ADCIFB is stopped, a local and temporary clock will automatically be requested so the event can be processed. Refer to Section 26.6.14, Section 26.6.13, and the Peripheral Event System chapter for details. Before entering a sleep mode where the clock to the ADCIFB is stopped, make sure the Analogto-Digital Converter cell is put in an inactive state. Refer to Section 26.6.14 for more information. 26.5.3 Clocks The clock for the ADCIFB bus interface (CLK_ADCIFB) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the ADCIFB before disabling the clock, to avoid freezing the ADCIFB in an undefined state. 608 32099A–AVR32–06/09 AT32UC3L 26.5.4 Interrupts The ADCIFB interrupt request line is connected to the interrupt controller. Using the ADCIFB interrupt request functionality requires the interrupt controller to be programmed first. 26.5.5 Peripheral Events The ADCIFB peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details 26.5.6 Debug Operation When an external debugger forces the CPU into debug mode, this module continues normal operation. If this module is configured in a way that requires it to be periodically serviced by the CPU through interrupt requests or similar, improper operation or data loss may result during debugging. 26.6 Functional Description The ADCIFB embeds a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC supports 8-bit or 10-bit resolutions, which can be extended to 11 or 12 bits by the Enhanced Resolution Mode. The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages converts to digital values (codes) based on a linear conversion. This linear conversion is described in the expression below where M is the number of bits used to represent the analog value, Vin is the voltage of the analog value to convert, Vref is the maximum voltage, and Code is the converted digital value. 2 ⋅ V in Code = ------------------V ref M 26.6.1 Initializing the ADCIFB The ADC Interface is enabled by writing a one to the Enable bit in the Control Register (CR.EN). After the ADC Interface is enabled, the ADC timings needs to be configured by writing the correct values to the RES, PRESCAL, and STARTUP fields in the ADC Configuration Register (ACR). See Section 26.6.6, and Section 26.6.8 for details. Before the ADCIFB can be used, the I/O Controller must be configured correctly and the Reference Voltage (ADVREF) signal must be connected. Refer to Section 26.5.1 for details. Basic Operation To convert analog values to digital values the user must first initialize the ADCIFB as described in Section 26.6.1. When the ADCIFB is initialized the channels to convert must be enabled by writing a one the corresponding bits in the Channel Enable Register (CHER). Enabling channel N instructs the ADCIFB to convert the analog voltage applied to AD pin N at each conversion sequence. Multiple channels can be enabled resulting in multiple AD pins being converted at each conversion sequence. To start converting data the user can either manually start a conversion sequence by writing a one to the START bit in the Control Register (CR.START) or configure an automatic trigger to initiate the conversions. The automatic trigger can be configured to trig on many different conditions. Refer to Section 26.8.1 for details. 609 26.6.2 32099A–AVR32–06/09 AT32UC3L The result of the conversion is stored in the Last Converted Data Register (LCDR) as they become available, overwriting the result from the previous conversion. To avoid data loss if more than one channel is enabled, the user must read the conversion results as they become available either by using an interrupt handler or by using a Peripheral DMA channel to copy the results to memory. Failing to do so will result in an Overrun Error condition, indicated by the OVRE bit in the Status Register (SR). To use an interrupt handler the user must enable the Data Ready (DRDY) interrupt request by writing a one to the corresponding bit in the Interrupt Enable Register (IER). To clear the interrupt after the conversion result is read, the user must write a one to the corresponding bit in the Interrupt Clear Register (ICR). See Section 26.6.12 for details. To use a Peripheral DMA Controller channel the user must configure the Peripheral DMA Controller appropriately. The Peripheral DMA Controller will, when configured, automatically read converted data as they become available. There is no need to manually clear any bits in the Interrupt Status Register as this is performed by the hardware. If an Overrun Error condition happens during DMA operation, the OVRE bit in the SR will be set. 26.6.3 ADC Resolution The Analog-to-Digital Converter cell supports 8-bit or 10-bit resolution natively which can be extended to 11-bit and 12-bit with the Enhanced Resolution Mode. The resolution is selected by writing the selected resolution value to the RES field in the ADC Configuration Register (ACR). See Section 26.9.3. By writing a zero to the RES field, the ADC switches to the lowest resolution and the conversion results can be read in the eight lowest significant bits of the Last Converted Data Register (LCDR). The four highest bits of the Last Converted Data (LDATA) field in the LCDR register reads as zero. Writing a one to the RES field enables 10-bit resolution, the optimal resolution for both sampling speed and accuracy. Writing two or three automatically enables Enhanced Resolution Mode with 11-bit or 12-bit resolution, see Section 26.6.4 for details. When a Peripheral DMA Controller channel is connected to the ADCIFB in 10-bit, 11-bit, or 12bit resolution mode, a transfer size of 16 bits must be used. By writing a zero to the RES field, the destination buffers can be optimized for 8-bit transfers. 26.6.4 Enhanced Resolution Mode The Enhanced Resolution Mode is automatically enabled when 11-bit or 12-bit mode is selected in the ADC Configuration Register (ACR). In this mode the ADCIFB will trade conversion performance for accuracy by averaging multiple samples. To be able to increase the accuracy by averaging multiple samples it is important that some noise is present in the input signal. The noise level should be between one and two LSB peakto-peak to get good averaging performance. The performance cost of enabling 11-bit mode is 4 ADC samples, which reduces the effective ADC performance by a factor 4. For 12-bit mode this factor is 16. For 12-bit mode the effective sample rate is maximum ADC sample rate divided by 16. 26.6.5 Pseudorandom Noise Generator The Pseudorandom Noise Generator generates a random 1-bit signal (RND) which can be used to add noise to the analog input signals. This signal can be muxed out to a pad using the I/O Controller and added to analog input signals through a resistor. By varying the size of the resistor, the noise levels added can be adjusted for optimal performance. 610 32099A–AVR32–06/09 AT32UC3L The Pseudorandom Noise Generator is always enabled when a conversion is in progress, but the line can be multiplexed with other I/O Controller lines. In this case, the user must make sure the I/O Controller is configured correctly to allow the noise signal to propagate out to the RND pin. 26.6.6 ADC Clock The ADCIFB generates an internal clock named CLK_ADC that is used by the Analog-to-Digital Converter cell to perform conversions. The CLK_ADC frequency is selected by writing to the PRESCAL field in the ADC Configuration Register (ACR). The CLK_ADC range is between CLK_ADCIFB/2, if PRESCAL is 0, and CLK_ADCIFB/128, if PRESCAL is 63 (0x3F). A sensible PRESCAL value must be used in order to provide an ADC clock frequency according to the maximum sampling rate parameter given in the Electrical Characteristics section. Failing to do so may result in incorrect Analog-to-Digital Converter operation. 26.6.7 ADC Sleep Mode The ADC Sleep Mode maximizes power saving by automatically deactivating the Analog-to-Digital Converter cell when it is not being used for conversions. The ADC Sleep Mode is enabled by writing a one to the SLEEP bit in the ADC Configuration Register (ACR). When a trigger occurs while the ADC Sleep Mode is enabled, the Analog-to-Digital Converter cell is automatically activated. As the analog cell requires a startup time, the logic waits during this time and then starts the conversion of the enabled channels. When conversions of all enabled channels are complete, the ADC is deactivated until the next trigger. 26.6.8 Startup Time The Analog-to-Digital Converter cell has a minimal startup time when the cell is activated. This startup time is given in the Electrical Characteristics chapter and must be written to the STARTUP field in the ADC Configuration Register (ACR) to get correct conversion results. The STARTUP field expects the startup time to be represented as the number of CLK_ADC cycles between 8 and 1024 and in steps of 8 that is needed to cover the ADC startup time as specified in the Electrical Characteristics chapter. The Analog-to-Digital Converter cell is activated at the first conversion after reset and remains active if ACR.SLEEP is zero. If ACR.SLEEP is one, the Analog-to-Digital Converter cell is automatically deactivated when idle and thus each conversion sequence will have a initial startup time delay. 26.6.9 Sample and Hold Time A minimal Sample and Hold Time is necessary for the ADCIFB to guarantee the best converted final value when switching between ADC channels. This time depends on the input impedance of the analog input, but also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer amplifier. The Sample and Hold time has to be programmed through the SHTIM field in the ADC Configuration Register (ACR). This field can define a Sample and Hold time between 1 and 16 CLK_ADC cycles. 26.6.10 ADC Conversion ADC conversions are performed on all enabled channels when a trigger condition is detected. For details regarding trigger conditions see Section 26.8.1. The term channel is used to identify 611 32099A–AVR32–06/09 AT32UC3L a specific analog input pin so it can be included or excluded in an Analog-to-Digital conversion sequence and to identify which AD pin was used to convert the current value in the Last Converted Data Register (LCDR). Channel number N corresponding to AD pin number N. Channels are enabled by writing a one to the corresponding bit in the Channel Enable Register (CHER), and disabled by writing a one to the corresponding bit in the Channel Disable Register (CHDR). Active channels are listed in the Channel Status Register (CHSR). When a conversion sequence is started, all enabled channels will be converted in one sequence and the result will be placed in the Last Converted Data Register (LCDR) with the channel number used to produce the result. It is important to read out the results while the conversion sequence is ongoing, as new values will automatically overwrite any old value and the old value will be lost if not previously read by the user. If the Analog-to-Digital Converter cell is inactive when starting a conversion sequence, the conversion logic will wait a configurable number of CLK_ADC cycles as defined in the startup time field in the ADC Configuration Register (ACR). After the cell is activated all enabled channels is converted one by one until no more enabled channels exist. The conversion sequence converts each enabled channel in order starting with the channel with the lowest channel number. If the ACR.SLEEP bit is one, the Analog-to-Digital Converter cell is deactivated after the conversion sequence has finished. For each channel converted, the ADCIFB waits a Sample and Hold number of CLK_ADC cycles as defined in the SHTIM field in ACR, and then instructs the Analog-to-Digital Converter cell to start converting the analog voltage. The ADC cell requires 10 CLK_ADC cycles to actually convert the value, so the total time to convert a channel i Sample and Hold + 10 CLK_ADC cycles. 26.6.11 Analog Compare Mode The ADCIFB can test if the converted values, as they become available, are below, above, or inside a specified range and generate interrupt requests based on this information. This is useful for applications where the user wants to monitor some external analog signal and only initiate actions if the value is above, below, or inside some specified range. The Analog Compare mode is enabled by writing a one to the Analog Compare Enable (ACE) bit in the Mode Register (MR). The values to compare must be written to the Low Value (LV) field and the High Value (HV) field in the Compare Value Register (CVR). The Analog Compare mode will, when enabled, check all enabled channels against the pre-programmed high and low values and set status bits. To generate an interrupt request if a converted value is below a limit, write the limit to the CVR.LV field and enable interrupt request on the Compare Lesser Than (CLT) bit by writing a one to the corresponding bit in the Interrupt Enable Register (IER). To generate an interrupt request if a converted value is above a limit, write the limit to the CVR.HV field and enable interrupt for Compare Greater Than (CGT) bit. To generate an interrupt request if a converted value is inside a range, write the low and high limit to the LV and HV fields and enable the Compare Else (CELSE) interrupt. To generate an interrupt request if a value is outside a range, write the LV and HV fields to the low and high limits of the range and enable CGT and CLT interrupts. Note that the values written to LV and HV must match the resolution selected in the ADC Configuration Register (ACR). 612 32099A–AVR32–06/09 AT32UC3L 26.6.12 Interrupt Operation Interrupt requests are enabled by writing a one to the corresponding bit in the Interrupt Enable Register (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). Enabled interrupts can be read from the Interrupt Mask Register (IMR). Active interrupt requests, but potentially masked, are visible in the Interrupt Status Register (ISR). To clear an active interrupt request, write a one to the corresponding bit in the Interrupt Clear Register (ICR). The source for the interrupt requests are the status bits in the Status Register (SR). The SR shows the ADCIFB status at the time the register is read. The Interrupt Status Register (ISR) shows the status since the last write to the Interrupt Clear Register. The combination of ISR and SR allows the user to react to status change conditions but also allows the user to read the current status at any time. 26.6.13 Peripheral Events The Peripheral Event System can be used together with the ADCIFB to allow any peripheral event generator to be used as a trigger source. To enable peripheral events to trigger a conversion sequence the user must write the Peripheral Event Trigger value (0x7) to the Trigger Mode (TRGMOD) field in the Trigger Register (TRGR). Refer to Table 26-4 on page 625. The user must also configure a peripheral event generator to emit peripheral events for the ADCIFB to trigger on. Refer to the Peripheral Event System chapter for details. Sleep Mode Before entering sleep modes the user must make sure the ADCIFB is idle and that the Analogto-Digital Converter cell is inactive. To deactivate the Analog-to-Digital Converter cell the SLEEP bit in the ADC Configuration Register (ACR) must be written to one and the ADCIFB must be idle. To make sure the ADCIFB is idle, write a zero the Trigger Mode (TRGMOD) field in the Trigger Register (TRGR) and wait for the READY bit in the Status Register (SR) to be set. Note that by deactivating the Analog-to-Digital Converter cell, a startup time penalty as defined in the STARTUP field in the ADC Configuration Register (ACR) will apply on the next conversion. 26.6.15 Conversion Performances For performance and electrical characteristics of the ADCIFB, refer to the Electrical Characteristics chapter. 26.6.14 613 32099A–AVR32–06/09 AT32UC3L 26.7 Resisitve Touch Screen The ADCIFB embeds an integrated resistive touch screen sequencer that can be used to calculate contact coordinates on a resistive film touch screen. When instructed to start, the integrated touch screen sequencer automatically applies a sequence of voltage patterns to the touch screen films and the Analog-to-Digital Conversion cell is used to measure the effects. The resulting measurements can be used to calculate the horizontal and vertical contact coordinates. The touch screen film is connected to the ADCIFB using the AD and DP pins. See Section 26.7.3 for details. Touch Screen ADC Mode is enabled by writing a one to the TSAMOD field in the Mode Register (MR). In this mode, channels TSPO+0 though TSPO+3 are automatically enabled where TSPO refers to the Touch Screen Pin Offset field in the Mode Register. For each conversion sequence, all enabled channles before TSPO+0 and after TSPO+3 are converted as ordinary ADC channels, producing 1 conversion result each. When the sequencer enters the TSPO+0 channel the touch screen sequencer will take over control and convert the next 4 channles as described in Section 26.7.4. 26.7.1 Resistive Touch Screen Principles A resistive touch screen is based on two resistive films, each one fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. Between the two, there is a layer that acts as an insulator, but makes a connection when pressure is applied to the screen. This is illustrated in Figure 26-2 on page 614. Figure 26-2. Touch Screen Position Measurement Pen Contact XP YM YP XM XP VDD YP VDD YP XP Volt XM Vertical Position Detection YM Volt GND GND Horizontal Position Detection 26.7.2 Position Measurement Method As shown in Figure 26-2 on page 614, to detect the position of a contact, voltage is first applied to XP (top) and Xm (bottom) leaving Yp and Ym tristated. Due to the linear resistance of the film, there is a voltage gradient from top to bottom on the first film. When a contact is performed on 614 32099A–AVR32–06/09 AT32UC3L the screen, the voltage at the contact point propagates to the second film. If the input impedance on the YP (right) and Ym (left) electrodes are high enough, no current will flow, allowing the voltage at the contact point to be measured at Yp. The value measured represents the vertical position component of the contact point. For the horizontal direction, the same method is used, but by applying voltage from YP (right) to Ym (left) and measuring at XP. In an ideal world (linear, with no loss), the vertical position is equal to: VYP / VDD To compensate for some of the real world imperfections, VXP and VXm can be measured and used to improve accuracy at the cost of two more conversions per axes. The new expression for the vertical position then becomes: (VYP - VXM) / (VXP - VXM) 26.7.3 Touch Screen Pin Connections Table 26-2. ADCIFB Pin DP0 DP1 ADtspo+0 ADtspo+1 ADtspo+2 ADtspo+3 Touch Screen Pin Connections TS Signal, APOE == 0 Xp through a resistor Yp through a resistor Xp Xm Yp Ym TS Signal, APOE == 1 No Connect No Connect Xp Xm Yp Ym The touch screen film signals connects to the ADCIFB using the AD and DP pins. The XP (top) and XM (bottom) film signals are connected to ADtspo+0 and ADtspo+1 pins, and the YP (right) and YM (left) signals are connected to ADtspo+2 and ADtspo+3 pins. The tspo index is configurable through the Touch Screen Pin Offset (TSPO) field in the Mode Register (MR) and allows the user to configure which AD pins to use for touch screen applications. Writing a zero to the TSPO field instructs the ADCIFB to use AD0 through AD3, where AD0 is connected to XP, AD1 is connected to XM and so on. Writing a one to the TSPO field instructs the ADCIFB to use AD1 through AD4 for touch screen sequencing, where AD1 is connected to XP and AD0 is free to be used as an ordinary ADC channel. When the Analog Pin Output Enable (APOE) bit in the Mode Register (MR) is zero, the AD pins are used to measure input voltage and drive the GND sequences, while the DP pins are used to drive the VDD sequences. This arrangement allows the user to reduce the voltage seen at the AD input pins by inserting external resistors between DP0 and XP and DP1 and YP signals which are again directly connected to the AD pins. It is important that the voltages observed at the AD pins are not higher than the maximum allowed ADC input voltage. See Figure 26-3 on page 617 for details regarding how to connect the touch screen films to the AD and DP pins. By adding a resistor between DP0 and XP, and DP1 and YP, the maximum voltage observed at the AD pins can be controlled by the following voltage divider expressions: 615 32099A–AVR32–06/09 AT32UC3L R filmx V ( AD tspo + 0 ) = -------------------------------------------- ⋅ V ( DP 0 ) R filmx + R resistorx R filmY V ( AD tspo + 2 ) = --------------------------------------------- ⋅ V ( DP 1 ) R filmY + R resistorY The Rfilmx parameter is the film resistance obersved when measuring between XP and XM. The Rresistorx parameter is the resistor size inserted between DP0 and XP. The definition of Rfilmy and Rresistory is the same but for DP1, YP, and YM instead. The DP pins are used by default, as the APOE bit is zero after reset. Writing a one to the APOE bit instructs the ADCIFB touch screen sequencer to use the already connected ADtspo+0 and ADtspo+2 pins to drive VDD to XP and YP signals directly. In this mode the DP pins can be used as general purpose I/O pins. Before writing a one to the APOE bit the user must make sure that the I/O voltage is compatible with the ADC input voltage. If the I/O voltage is higher than the maximum input voltage of the ADC, permanent damage may occur. Refer to the Electrical Characteristics chapter for details. 616 32099A–AVR32–06/09 AT32UC3L Figure 26-3. Touch Screen Pin Connections DP0 Analog Pin Output Enable (MR.APOE) == 0 DP1 ADtspo+0 XP YM YP XM ADtspo+3 ADtspo+1 ADtspo+2 NC Analog Pin Output Enable (MR.APOE) == 1 NC DP0 DP1 ADtspo+0 XP YM YP XM ADtspo+3 ADtspo+1 ADtspo+2 26.7.4 Touch Screen Sequencer The touch screen sequencer is responsible for applying voltage to the resistive touch screen films as described in Section 26.7.2. This is done by controlling the output enable and the output value of the DP and AD pins. This allows the touch screen sequencer to add a voltage gradient on one film while keeping the other film floating so a touch can be measured. The Touch Screen Sequencer will when measuring the vertical position, apply VDD and GND to the pins connected to XP and XM. The YP and YM pins are put in tristate mode so the measurement of YP can proceed without interference. To compansate for ADC offset errors and non ideal pad drivers, the actual voltage of XP and XM is measured as well, so the real values for VDD and GND can be used in the contact point calculation to increase accurcy. See second formula in Section 26.7.2. When the vertical values are converted the same setup is applies for the second axes, by setting XP and XM in tristate mode and applying VDD and GND to YP and YM. Refer to Section 26.8.3 for details. 617 32099A–AVR32–06/09 AT32UC3L 26.7.5 Pen Detect If no contact is applied to the touch screen films, any touch screen conversion result will be undefined as the film being measured is floating. This can be avoided by enabling Pen Detect and only trigger touch screen conversions when the Pen Contact (PENCNT) status bit in the Status Register (SR) is one. Pen Detect is enabled by writing a one to the Pen Detect (PENDET) bit in the Mode Register (MR) When Pen Detect is enabled, the ADCIFB grounds the vertical panel by applying GND to XP and XM and polarizes the horizontal panel by enabling pull-up on the pin connected to YP. The YM pin will in this mode be tristated. Since there is no contact, no current is flowing and there is no related power consumption. As soon as a contact occurs, GND will propagate to YM by pulling down YP, allowing the contact to be registered by the ADCIFB. A programmable debouncing filter can be used to filter out false pen detects because of noise. The debouncing filter is programmable from one CLK_ADC period and up to 215 CLK_ADC periods. The debouncer length is set by writing to the PENDBC field in MR. Figure 26-4. Touch Screen Pen Detect Touch Screen Sequencer XP GND XM GND YP Pullup To the ADC YM Tristate PENDBC Debouncer Pen Interrupt The Touch Screen Pen Detect can be used to generate an ADCIFB interrupt request or it can be used to trig a conversion, so that a position can be measured as soon as a contact is detected. The Pen Detect Mode generates two types of status signals, reported in the Status Register (SR): • The bit PENCNT is set when current flows and remains set until current stops. • The bit NOCNT is set when no current flows and remains set until current flows. Before a current change is reflected in the SR, the new status must be stable for the duration of the debouncing time. Both status conditions can generate an interrupt request if the corresponding bit in the Interrupt Mask Register (IMR) is one. Refer to Section 26.6.12 on page 613. 618 32099A–AVR32–06/09 AT32UC3L 26.8 Operating Modes The ADCIFB features two operating modes, each defining a separate conversion sequence: • ADC Mode: At each trigger, all the enabled channels are converted. • Touch Screen ADC Mode: At each trigger, all enabled channels plus the touch screen channels are converted as described in Section 26.8.3. If channels except the dedicated touch screen channels are enabled, they are converted normally before and after the touch screen channels are converted. The operating mode is selected by the TSAMOD field in the Mode Register (MR). 26.8.1 Conversion Triggers A conversion sequence is started either by a software or by a hardware trigger. When a conversion sequence is started, all enabled channels will be converted and made available in the shared Last Converted Register (LCDR). The software trigger is asserted by writing a one to the START field in the Control Register (CR). The hardware trigger can be selected by the TRGMOD field in the Trigger Register (TRGR). Different hardware triggers exist: • External trigger, either rising or falling or any, detected on the external trigger pin ADTRG • Pen detect trigger, depending the PENDET bit in the Mode Register (MR) • Continuous trigger, meaning the ADCIFB restarts the next sequence as soon as it finishes the current one • Periodic trigger, which is defined by the TRGR.TRGPER field • Peripheral event trigger, allowing the Peripheral Event System to synchronize conversion with some configured peripheral event source. Enabling a hardware trigger does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can still be initiated by the software trigger. 26.8.2 ADC Mode In the ADC Mode, the active channels are defined by the Channel Status Register (CHSR). A channel is enabled by writing a one to the corresponding bit in the Channel Enable Register (CHER), and disabled by writing a one to the corresponding bit in the Channel Disable Register (CHDR). The conversion results are stored in the Last Converted Data Register (LCDR) as they become available, overwriting old conversions. At each trigger, the following sequence is performed: 1. If ACR.SLEEP is one, wake up the ADC and wait for the startup time. 2. If Channel 0 is enabled, convert Channel 0 and store result in LCDR. 3. If Channel 1 is enabled, convert Channel 1 and store result in LCDR. 4. If Channel N is enabled, convert Channel N and store result in LCDR. 5. If ACR.SLEEP is one, place the ADC cell in a low-power state. If the Peripheral DMA Controller is enabled, all converted values are transferred continuously into the memory buffer. 26.8.3 Touch Screen ADC Mode Writing a one to the TSAMOD field in the Mode Register (MR) enables Touch Screen ADC Mode. In this mode the channels TSPO+0 to TSPO+3, corresponding to the touch screen 619 32099A–AVR32–06/09 AT32UC3L inputs, are automatically activated. In addition, if any other channels are enabled, they will be converted before and after the touch screen conversion. At each trigger, the following sequence is performed: 1. If ACR.SLEEP is one, wake up the ADC cell and wait for the startup time. 2. Convert all enabled channels before TSPO and store the results in the LCDR. 3. Apply supply on the inputs XP and XM during the Sample and Hold Time. 4. Convert Channel XM and store the result in TMP. 5. Apply supply on the inputs XP and XM during the Sample and Hold Time. 6. Convert Channel XP, subtract TMP from the result and store the subtracted result in LCDR. 7. Apply supply on the inputs XP and XM during the Sample and Hold Time. 8. Convert Channel YP, subtract TMP from the result and store the subtracted result in LCDR. 9. Apply supply on the inputs YP and YM during the Sample and Hold Time. 10. Convert Channel YM and store the result in TMP. 11. Apply supply on the inputs YP and YM during the Sample and Hold Time. 12. Convert Channel YP, subtract TMP from the result and store the subtracted result in LCDR. 13. Apply supply on the inputs YP and YM during the Sample and Hold Time. 14. Convert Channel XP, subtract TMP from the result and store the subtracted result in LCDR. 15. Convert all enabled channels after TSPO + 3 and store results in the LCDR. 16. If ACR.SLEEP is one, place the ADC cell in a low-power state. The resulting buffer structure stored in memory is: 1. XP - XM 2. YP - XM 3. YP - YM 4. XP - YM. The vertical position can be easily calculated by dividing the data at offset 1(XP - XM) by the data at offset 2(YP - XM). The horizontal position can be easily calculated by dividing the data at offset 3(YP - YM) by the data at offset 4(XP - YM). 620 32099A–AVR32–06/09 AT32UC3L 26.9 User Interface ADCIFB Register Memory Map Register Control Register Mode Register ADC Configuration Register Trigger Register Compare Value Register Status Register Interrupt Status Register Interrupt Clear Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Last Converted Data Register Parameter Register Version Register Channel Enable Register Channel Disable Register Channel Status Register Name CR MR ACR TRGR CVR SR ISR ICR IER IDR IMR LCDR PARAMETER VERSION CHER CHDR CHSR Access Write-only Read/Write Read/Write Read/Write Read/Write Read-only Read-only Write-only Write-only Write-only Read-only Read-only Read-only Read-only Write-only Write-only Read-only Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) -(1) 0x00000000 Table 26-3. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x40 0x44 0x48 Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 621 32099A–AVR32–06/09 AT32UC3L 26.9.1 Control Register Register Name: CR Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – Write-only 0x00 0x00000000 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 DIS 1 START 24 – 16 – 8 EN 0 SWRST • DIS: ADCDIFB Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the ADCIFB. Note: Disabling the ADCIFB effectively stops all clocks in the module so the user must make sure the ADCIFB is idle before disabling the ADCIFB. • EN: ADCIFB Enable Writing a zero to this bit has no effect. Writing a one to this bit enables the ADCIFB. Note: The ADCIFB must be enabled before use. • START: Start Conversion Writing a zero to this bit has no effect. Writing a one to this bit starts an Analog-to-Digital conversion. • SWRST: Software Reset Writing a zero to this bit has no effect. Writing a one to this bit resets the ADCIFB, simulating a hardware reset. 622 32099A–AVR32–06/09 AT32UC3L 26.9.2 Name: Mode Register MR Read/Write 0x04 0x00000000 30 PENDBC 23 22 21 20 TSPO 15 – 7 – 14 – 6 APOE 13 – 5 ACE 12 – 4 PENDET 11 – 3 – 10 – 2 – 9 – 1 – 8 – 0 TSAMOD 29 28 27 – 19 26 – 18 25 – 17 24 – 16 Access Type: Offset: Reset Value: 31 • PENDBC: Pen Detect Debouncing Period • Period = 2PENDBC*TCLK_ADC TSPO: Touch Screen Pin Offset The Touch Screen Pin Offset field is used to indicate which AD pins are connected to the resistive touch screen film edges. Only an offset is specified and it is assumed that the touch screen films are connected sequentially from the specified offset pin and up to and including offset + 3 (4 pins). APOE: Analog Pin Output Enable 0: AD pins are not used to drive VDD in Touch Screen sequence. 1: AD pins are used to drive VDD in Touch Screen sequence. Note: If the selected I/O voltage configuration is incompatible with the Analog-to-Digital converter cell voltage specification, this bit must stay cleared to avoid damaging the ADC. In this case the DP pins must be used to drive VDD instead, as described in Section 26.7.3. If the I/O and ADC voltages are compatible, the AD pins can be used directly by writing a one to this bit. In this case the DP pins can be ignored. ACE: Analog Compare Enable 0: The analog compare functionality is disabled. 1: The analog compare functionality is enabled. PENDET: Pen Detect 0: The pen detect functionality is disabled. 1: The pen detect functionality is enabled. TSAMOD: Touch Screen ADC Mode 0: Touch Screen Mode is disabled. 1: Touch Screen Mode is enabled. • • • • 623 32099A–AVR32–06/09 AT32UC3L 26.9.3 Name: ADC Configuration Register ACR Read/Write 0x08 0x00000000 30 – 22 29 – 21 28 – 20 19 STARTUP 11 PRESCAL 5 RES 4 3 – 2 – 1 – 0 SLEEP 18 27 26 SHTIM 17 16 25 24 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 - 14 – 6 – 13 12 10 9 8 • SHTIM: Sample & Hold Time for ADC Channels T SAMPLE & HOLD = SHTIM ⋅ T CLK _ ADC • STARTUP: Startup Time T STARTUP = STARTUP ⋅ 8 ⋅ T CLK _ ADC • PRESCAL: Prescaler Rate Selection T CLK _ ADC = ( PRESCAL + 1 ) ⋅ 2 ⋅ T CLK _ ADCIFB • RES: Resolution Selection 0: 8-bit resolution. 1: 10-bit resolution. 2: 11-bit resolution, interpolated. 3: 12-bit resolution, interpolated. • SLEEP: ADC Sleep Mode 0: ADC Sleep Mode is disabled. 1: ADC Sleep Mode is enabled. 624 32099A–AVR32–06/09 AT32UC3L 26.9.4 Name: Trigger Register TRGR Read/Write 0x0C 0x00000000 30 29 28 27 TRGPER[15:8] 20 TRGPER[7:0] 15 – 7 – 14 – 6 – 13 – 5 – 12 – 4 – 11 – 3 – 10 – 2 9 – 1 TRGMOD 8 – 0 19 26 25 24 Access Type: Offset: Reset Value: 31 23 22 21 18 17 16 • TRGPER: Trigger Period Effective only if TRGMOD defines a Periodic Trigger. Defines the periodic trigger period, with the following equations: Trigger Period = TRGPER *TCLK_ADC • TRGMOD: Trigger Mode Table 26-4. Trigger Modes TRGMOD Selected Trigger Mode 0 1 0 1 0 1 0 1 No trigger, only software trigger can start conversions External Trigger Rising Edge External Trigger Falling Edge External Trigger Any Edge Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touch Screen mode) Periodic Trigger (TRGPER shall be initiated appropriately) Continuous Mode Peripheral Event Trigger 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 625 32099A–AVR32–06/09 AT32UC3L 26.9.5 Name: Compare Value Register CVR Read/Write 0x10 0x00000000 30 – 22 29 – 21 28 – 20 HV[7:0] 15 – 7 14 – 6 13 – 5 12 – 4 LV[7:0] 11 10 LV[11:8] 3 2 1 0 9 8 27 26 HV[11:8] 19 18 17 16 25 24 Access Type: Offset: Reset Value: 31 – 23 • HV: High Value Defines the high value used when comparing analog input. • LV: Low Value Defines the low value used when comparing analog input. 626 32099A–AVR32–06/09 AT32UC3L 26.9.6 Name: Status Register SR Read-only 0x14 0x00000000 30 – 22 – 14 CELSE 6 – 29 – 21 – 13 CGT 5 NOCNT 28 – 20 – 12 CLT 4 PENCNT 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 BUSY 1 OVRE 24 EN 16 – 8 READY 0 DRDY Access Type: Offset: Reset Value: 31 – 23 – 15 7 – • EN: Enable Status 0: The ADCIFB is disabled. 1: The ADCIFB is enabled. CELSE: Compare Else Status 0: Either CLT or CGT detected or compare is disabled. 1: No CLT or CGT detected on last converted data. CGT: Compare Greater Than Status 0: No compare greater than CVR.HV detected on last converted data or compare is disabled. 1: Compare greater than CVR.HV detected on last converted data or compare is disabled. CLT: Compare Lesser Than Status 0: No compare lesser than CVR.LV detected on last converted data or compare is disabled. 1: Compare lesser than CVR.LV detected on last converted data or compare is disabled. BUSY: Busy Status 0: The ADCIFB is ready to perform a conversion sequence. 1: The ADCIFB is busy performing a convention sequence. READY: Ready Status 0: The ADCIFB is busy performing a conversion sequence. 1: The ADCIFB is ready to perform a conversion sequence. NOCNT: No Contact Status 0: No contact loss is detected or pen detect disabled. 1: Contact loss is detected. PENCNT: Pen Contact Status 0: No contact is detected or pen detect disabled. 1: Pen contact is detected. OVRE: Overrun Error Status 0: No Overrun Error has occurred since the start of conversion sequence. 1: One or more Overrun Error has occurred since the start of conversion sequence. DRDY: Data Ready Status 0: No data has been converted since the start of conversion sequence. 1: One or more data has been converted since the start of conversion and is available in LCDR. • • • • • • • • • 627 32099A–AVR32–06/09 AT32UC3L 26.9.7 Name: Interrupt Status Register ISR Read-only 0x18 0x00000000 30 – 22 – 14 CELSE 6 – 29 – 21 – 13 CGT 5 NOCNT 28 – 20 – 12 CLT 4 PENCNT 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 BUSY 1 OVRE 24 – 16 – 8 READY 0 DRDY Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – A bit in this register is cleared by writing a one to the corresponding bit in the Interrupt Clear Register (ISR). A bit in this register is set when the corresponding bit in the Status Register (SR) is set. 628 32099A–AVR32–06/09 AT32UC3L 26.9.8 Name: Interrupt Clear Register ICR Write-only 0x1C 0x00000000 30 – 22 – 14 CELSE 6 – 29 – 21 – 13 CGT 5 NOCNT 28 – 20 – 12 CLT 4 PENCNT 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 BUSY 1 OVRE 24 – 16 – 8 READY 0 DRDY Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request. 629 32099A–AVR32–06/09 AT32UC3L 26.9.9 Name: Interrupt Enable Register IER Write-only 0x20 0x00000000 30 – 22 – 14 CELSE 6 – 29 – 21 – 13 CGT 5 NOCNT 28 – 20 – 12 CLT 4 PENCNT 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 BUSY 1 OVRE 24 – 16 – 8 READY 0 DRDY Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 630 32099A–AVR32–06/09 AT32UC3L 26.9.10 Name: Interrupt Disable Register IDR Write-only 0x24 0x00000000 30 – 22 – 14 CELSE 6 – 29 – 21 – 13 CGT 28 – 20 – 12 CLT 27 – 19 – 11 – 26 – 18 – 10 – 25 – 17 – 9 BUSY 24 – 16 – 8 READY Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – NOCNT PENCNT – – OVRE DRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 631 32099A–AVR32–06/09 AT32UC3L 26.9.11 Name: Interrupt Mask Register IMR Read-only 0x28 0x00000000 30 – 22 – 14 CELSE 6 – 29 – 21 – 13 CGT 28 – 20 – 12 CLT 27 – 19 – 11 – 26 – 18 – 10 – 25 – 17 – 9 BUSY 24 – 16 – 8 READY Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 – NOCNT PENCNT – – OVRE DRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared by writing a one to the corresponding bit in Interrupt Disable Register (IDR). A bit in this register is set by writing a one to the corresponding bit in Interrupt Enable Register (IER). 632 32099A–AVR32–06/09 AT32UC3L 26.9.12 Name: Last Converted Data Register LCDR Read-only 0x2C 0x00000000 30 – 22 29 – 21 28 – 20 LCCH 15 – 7 14 – 6 13 – 5 12 – 4 LDATA[7:0] 11 10 LDATA[11:8] 3 2 1 0 9 8 27 – 19 26 – 18 25 – 17 24 – 16 Access Type: Offset: Reset Value: 31 – 23 • LCCH: Last Converted Channel This field indicates what channel was last converted, i.e. what channel the LDATA represents. • LDATA: Last Data Converted The analog-to-digital conversion data is placed in this register at the end of a conversion on any analog channel and remains until a new conversion on any analog channel is completed. 633 32099A–AVR32–06/09 AT32UC3L 26.9.13 Name: Parameter Register PARAMETER Read-only 0x30 0x00000000 30 CH30 22 CH22 14 CH14 6 CH6 29 CH29 21 CH21 13 CH13 5 CH5 28 CH28 20 CH20 12 CH12 4 CH4 27 CH27 19 CH19 11 CH11 3 CH3 26 CH26 18 CH18 10 CH10 2 CH2 25 CH25 17 CH17 9 CH9 1 CH1 24 CH24 16 CH16 8 CH8 0 CH0 Access Type: Offset: Reset Value: 31 CH31 23 CH23 15 CH15 7 CH7 • CHn: Channel n Implemented 0: The corresponding channel is not implemented. 1: The corresponding channel is implemented. 634 32099A–AVR32–06/09 AT32UC3L 26.9.14 Name: Version Register VERSION Read-only 0x34 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 VERSION[7:0] 27 – 19 26 – 18 VARIANT 11 10 9 VERSION[11:8] 2 1 8 25 – 17 24 – 16 Access Type: Offset: Reset Value: 31 – 23 – 15 – 7 3 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the Module. No functionality associated. 635 32099A–AVR32–06/09 AT32UC3L 26.9.15 Name: Channel Enable Register CHER Write-only 0x40 0x00000000 30 CH30 22 CH22 14 CH14 6 CH6 29 CH29 21 CH21 13 CH13 5 CH5 28 CH28 20 CH20 12 CH12 4 CH4 27 CH27 19 CH19 11 CH11 3 CH3 26 CH26 18 CH18 10 CH10 2 CH2 25 CH25 17 CH17 9 CH9 1 CH1 24 CH24 16 CH16 8 CH8 0 CH0 Access Type: Offset: Reset Value: 31 CH31 23 CH23 15 CH15 7 CH7 • CHn: Channel n Enable Writing a zero to a bit in this register has no effect Writing a one to a bit in this register enables the corresponding channel The number of available channels is device dependent. Please refer to the Module Cconfiguration section at the end of this chapter for information regarding which channels are implemented. 636 32099A–AVR32–06/09 AT32UC3L 26.9.16 Name: Channel Disable Register CHDR Write-only 0x44 0x00000000 30 CH30 22 CH22 14 CH14 6 CH6 29 CH29 21 CH21 13 CH13 5 CH5 28 CH28 20 CH20 12 CH12 4 CH4 27 CH27 19 CH19 11 CH11 3 CH3 26 CH26 18 CH18 10 CH10 2 CH2 25 CH25 17 CH17 9 CH9 1 CH1 24 CH24 16 CH16 8 CH8 0 CH0 Access Type: Offset: Reset Value: 31 CH31 23 CH23 15 CH15 7 CH7 • CHn: Channel N Disable Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion, or if it is disabled and then re-enabled during a conversion, its associated data and its corresponding DRDY and OVRE bits in SR are unpredictable. The number of available channels is device dependent. Please refer to the ModuleCconfiguration section at the end of this chapter for information regarding how many channels are implemented. 637 32099A–AVR32–06/09 AT32UC3L 26.9.17 Name: Channel Status Register CHSR Read-only 0x48 0x00000000 30 CH30 22 CH22 14 CH14 6 CH6 29 CH29 21 CH21 13 CH13 5 CH5 28 CH28 20 CH20 12 CH12 4 CH4 27 CH27 19 CH19 11 CH11 3 CH3 26 CH26 18 CH18 10 CH10 2 CH2 25 CH25 17 CH17 9 CH9 1 CH1 24 CH24 16 CH16 8 CH8 0 CH0 Access Type: Offset: Reset Value: 31 CH31 23 CH23 15 CH15 7 CH7 • CHn: Channel N Status 0: The corresponding channel is disabled. 1: The corresponding channel is enabled. A bit in this register is cleared by writing a one to the corresponding bit in Channel Disable Register (CHDR). A bit in this register is set by writing a one to the corresponding bit in Channel Enable Register (CHER). The number of available channels is device dependent. Please refer to the ModuleCconfiguration section at the end of this chapter for information regarding how many channels are implemented. 638 32099A–AVR32–06/09 AT32UC3L 26.10 Module Configuration The specific configuration for each ADCIFB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 26-5. Feature Module Configuration ADCIFB 10 (9 + 1) Number of ADC channels Table 26-6. Module Name ADCIFB Module Clock Name Clock Name CLK_ADCIFB Table 26-7. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000101 0x000003FF Table 26-8. Channel CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 CH9 ADC Input Channels Input AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 Temperature sensor 639 32099A–AVR32–06/09 AT32UC3L 27. Analog Comparator Interface (ACIFB) Rev: 2.0.2.1 27.1 Features • Controls an array of Analog Comparators • Low power option • • – Single shot mode support Selectable settings for filter option – Filter length and hysteresis Window Mode – Detect inside/outside window – Detect above/below window Interrupt – On comparator result rising edge, falling edge, toggle – Inside window, outside window, toggle – When startup time has passed Can generate events to the peripheral event system • • 27.2 Overview The Analog Comparator Interface (ACIFB) is able to control a number of Analog Comparators (AC) with identical behavior. An Analog Comparator compares two voltages and gives a compare output depending on this comparison. The ACIFB can be configured in normal mode using each comparator independently or in window mode using defined comparator pairs to observe a window. The number of channels implemented is device specific. Refer to the Module Configuration section at the end of this chapter for details. 640 32099A–AVR32–06/09 AT32UC3L 27.3 Block Diagram Figure 27-1. ACIFB Block Diagram Analog Comparators ACTEST0 ACP0 ACIFB Peripheral Bus CLK_ACIFB INP + ACOUT0 FILTER ACN0 INN - AC GCLK AC0_INSELN ……………... INTERRUPT GENERATION ACREFN IRQ ACTEST PERIPHERAL EVENT GENERATION ACPn INP + ACOUTn FILTER TRIGGER EVENTS ACNn INN - AC ACn_INSELN ACTESTn 27.4 I/O Lines Description Table 27-1. I/O Line Description Pin Description Positive reference pin for Analog Comparator n Negative reference pin for Analog Comparator n Reference Voltage for all comparators selectable for INN Type Analog Analog Analog Pin Name ACPn ACNn ACREFN 27.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 27.5.1 I/O Lines The ACIFB pins are multiplexed with other peripherals. The user must first program the I/O Controller to give control of the pins to the ACIFB. 27.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the ACIFB, the ACIFB will stop functioning and resume operation after the system wakes up from sleep mode. 641 32099A–AVR32–06/09 AT32UC3L 27.5.3 Clocks The clock for the ACIFB bus interface (CLK_ACIFB) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the ACIFB before disabling the clock, to avoid freezing the ACIFB in an undefined state. The ACIFB uses a GCLK as clock source for the Analog Comparators. The user must set up this GCLK at the right frequency. The CLK_ACIFB clock of the interface must be at least 4x the GCLK frequency used in the comparators. The GCLK is used both for measuring the startup time of a comparator, and to give a frequency for the comparations done in Continuous Measurement Mode, see Section 27.6. Refer to the Electrical Characteristics chapter for GCLK frequency limitations. 27.5.4 Interrupts The ACIFB interrupt request line is connected to the interrupt controller. Using the ACIFB interrupt requires the interrupt controller to be programmed first. 27.5.5 Peripheral Events The ACIFB peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. Debug Operation When an external debugger forces the CPU into debug mode, the ACIFB continues normal operation. If the ACIFB is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 27.5.6 27.6 Functional Description The ACIFB is enabled by writing a one to the Control Register Enable bit (CTRL.EN). Additionally, the comparators must be individually enabled by programming the MODE field in the AC Configuration Register (CONFn.MODE). The results from the individual comparators can either be used directly (normal mode), or the results from two comparators can be grouped to generate a comparison window (window mode). All comparators need not be in the same mode, some comparators may be in normal mode, while others are in window mode. There are restrictions on which AC channels that can be grouped together in a window pair, see Section 27.6.3. 27.6.1 Analog Comparator Operation Each AC channel can be in one of four different modes, determined by CONFn.MODE: • Off • Continuous Measurement Mode (CM) • User Triggered Single Measurement Mode (UT) • Event Triggered Single Measurement Mode (ET) After being enabled, a startup time defined in CTRL.SUT is required before the result of the comparison is ready. The GCLK is used for measuring the startup time of a comparator, During the startup time the AC output is not available. When the ACn Ready bit in the Status Register (SR.ACRDYn) is one, the output of ACn is ready. In window mode the result is available when both the comparator outputs are ready (SR.ACRDYn=1 and SR.ACRDYn+1=1). 642 32099A–AVR32–06/09 AT32UC3L 27.6.1.1 Continuous Measurement Mode In CM, the Analog Comparator is continuously enabled and performing comparisons. This ensures that the result of the latest comparison is always available in the ACn Current Comparison Status bit in the Status Register (SR.ACCSn). Comparisons are done on every positive edge of GCLK. CM is enabled by writing CONFn.MODE to 1. After the startup time has passed, a comparison is done and SR is updated. Appropriate peripheral events and interrupts are also generated. New comparisons are performed continuously until the CONFn.MODE field is written to 0. 27.6.1.2 User Triggered Single Measurement Mode In the UT mode, the user starts a single comparison by writing a one to the User Start Single Conversion bit (CTRL.USTART). This mode is enabled by writing CONFn.MODE to 2. After the startup time has passed, a single comparison is done and SR is updated. Appropriate peripheral events and interrupts are also generated. No new comparisons will be performed. CTRL.USTART is cleared automatically by hardware when the single comparison has been done. Event Triggered Single Measurement Mode This mode is enabled by writing CONFn.MODE to 3 and Peripheral Event Trigger Enable (CTRL.EVENTEN) to one. The ET mode is similar to the UT mode, the difference is that a peripheral event from another hardware module causes the hardware to automatically set the Peripheral Event Start Single Conversion bit (CTRL.ESTART). After the startup time has passed, a single comparison is done and SR is updated. Appropriate peripheral events and interrupts are also generated. No new comparisons will be performed. CTRL.ESTART is cleared automatically by hardware when the single comparison has been done. Selecting Comparator Inputs Each Analog Comparator has one positive (INP) and one negative (INN) input. The positive input is fed from an external input pin (ACPn). The negative input can either be fed from an external input pin (ACNn) or from a reference voltage common to all ACs (ACREFN). The user selects the input source as follows: • In normal mode with the Negative Input Select and Positive Input Select fields (CONFn.INSELN and CONFn.INSELP). • In window mode with CONFn.INSELN, CONFn.INSELP and CONFn+1.INSELN, CONFn+1,INSELP. The user must configure CONFn.INSELN and CONFn+1.INSELP to the same source. 27.6.2 Normal Mode In normal mode all Analog Comparators are operating independently. 27.6.2.1 Normal Mode Output Each Analog Comparator generates one output ACOUT according to the input voltages on INP (AC positive input) and INN (AC negative input): • ACOUT = 1 if VINP > VINN • ACOUT = 0 if VINP < VINN • ACOUT = 0 if the AC output is not available (SR.ACRDY = 0) The output can optionally be filtered, as described in Section 27.6.4. 27.6.1.3 27.6.1.4 643 32099A–AVR32–06/09 AT32UC3L 27.6.2.2 Normal Mode Interrupt The AC channels can generate interrupts. The Interrupt Settings field in the Configuration Register (CONFn.IS) can be configured to select when the AC will generate an interrupt: • When VINP > VINN • When VINP < VINN • On toggle of the AC output (ACOUT) • When comparison has been done 27.6.2.3 Normal Mode Events The ACIFB can generate peripheral events according to the configuration of CONFn.EVENN and CONFn.EVENP. • When VINP > VINN or • When VINP < VINN or • On toggle of the AC output (ACOUT) 27.6.3 Window Mode In window mode, two ACs (an even and the following odd build up a pair) are grouped. The negative input of ACn (even) and the positive input of ACn+1 (odd) has to be connected together externally to the device and are controlled by the Input Select fields in the AC Configuration Registers (CONFn.INSELN and CONFn+1.INSELP). The positive input of ACn (even) and the negative input of ACn+1 (odd) can still be configured independently by CONFn.INSELP and CONFn+1.INSELN, respectively. Figure 27-2. Analog Comparator Interface in Window Mode ACPn + ACNn ACOUTn AC Filter Interrupt Generator IRQ COMMON Comparator pair Window Module ACWOUT Peripheral Event Generator Window window event + ACPn+1 AC ACNn+1 - ACOUTn+1 SR[WFCSn] Filter SR[ACCSn] 644 32099A–AVR32–06/09 AT32UC3L 27.6.3.1 Window Mode Output When operating in window mode, each channel generates the same ACOUT outputs as in normal mode, see Section 27.6.2.1. Additionally, the ACIFB generates a window mode signal (acwout) according to the common input voltage to be compared: • ACWOUT = 1 if the common input voltage is inside the window, VACN(N+1) < Vcommon < VACP(N) • ACWOUT = 0 if the common input voltage is outside the window, Vcommon < VACN(N+1) or Vcommon > VACP(N) • ACWOUT = 0 if the window mode output is not available (SR.ACRDYn =0 or SR.ACRDYn+1=0) 27.6.3.2 Window Mode Interrupts When operating in window mode, each channel can generate the same interrupts as in normal mode, see Section 27.6.2.2. Additionally, when channels operate in window mode, programming Window Mode Interrupt Settings in the Window Mode Configuration Register (CONFWn.WIS) can cause interrupts to be generated when: • As soon as the common input voltage is inside the window. • As soon as the common input voltage is outside the window. • On toggle of the window compare output (ACWOUT). • When the comparison in both channels in the window pair are ready. 27.6.3.3 Window Mode Events When operating in window mode, each channel can generate the same events as in normal mode, see Section 27.6.2.3. Additionally, when channels operate in window mode, programming Window Mode Event Selection Source (CONFWn.WEVSRC) can cause events to be generated when: • As soon as VACN(N+1) < Vcommon < VACP(N) • As soon as Vcommon < VACN(N+1) or Vcommon > VACP(N) • On toggle of the window compare output (ACWOUT) 27.6.4 Filtering The output of the comparator can be filtered to reduce noise. The filter length is determined by the Filter Length field in the CONFn register (CONFn.FLEN). The filter samples the Analog Comparator output at the GCLK frequency for 2CONFn.FLEN samples. A separate counter (CNT) counts the number of cycles the AC output was one. This filter is deactivated if CONFn.FLEN equals 0. If the filter is enabled, the Hysteresis Value field HYS in the CONFn register (CONFn.HYS) can be used to define a hysteresis value. The hysteresis value should be chosen so that: 2 FLEN --------------- ≥ HYS 2 645 32099A–AVR32–06/09 AT32UC3L The filter function is defined by: 2 FLEN CNT ≥ ⎛ --------------- + HYS⎞ ⇒ comp = 1 ⎝2 ⎠ 2 FLEN ⎛ --------------- + HYS⎞ > CNT ≥ ⎛ 2 --------------- – H YS⎞ ⇒ comp unchanged ⎝2 ⎠ ⎝2 ⎠ FLEN 2 CNT < ⎛ --------------- – H YS⎞ ⇒ comp = 0 ⎝2 ⎠ The filtering algorithm is explained in Figure 27-3. 2FLEN measurements are sampled. If lthe number of measurements that are zero is less than (2FLEN/2 - HYS), the filtered result is zero. If lthe number of measurements that are one is more than (2FLEN/2 + HYS), the filtered result is one. Otherwise, the result is unchanged. Figure 27-3. The Filtering Algorithm 2 FLEN 2 0 ”Result=0" Result = UNCHANGED ”Result=1" 2 FLEN FLEN HYS HYS 27.6.5 Interrupt Generation The interrupt request will be generated if the corresponding bit in the Interrupt Mask Register (IMR) is set. Bits in IMR are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt request remains active until the corresponding bit in ISR is cleared by writing a one to the corresponding bit in the Interrupt Status Clear Register (ICR). Peripheral Event Generation The ACIFB can be set up so that certain conversion results notify other parts of the device via the Peripheral Event system. Refer to Section 27.6.2.3 and Section 27.6.3.3 for information on which conversion results can generate events, and how to configure the ACIFB to achieve this. Zero or one event will be generated per conversion. 27.6.6 27.7 Peripheral Event Triggers Peripheral events from other modules can trigger conversions in the ACIFB. All channels that are set up in Event Triggered Single Measurement Mode will be started simultaneously when a peripheral event is received. Channels that are operating in Continuous Measurement Mode or User Triggered Single Measurement Mode will be unaffected by the received event. The software can still operate these channels independently of channels in Event Triggered Single Measurement Mode. 646 32099A–AVR32–06/09 AT32UC3L A peripheral event will trigger one or more conversions, in normal or window mode. 27.8 AC Test mode By writing the Analog Comparator Test Mode (CR.ACTEST) bit to one, the outputs from the ACs are overridden by the value in the Test Register (TR), see Figure 27-1. This is useful for software development. 647 32099A–AVR32–06/09 AT32UC3L 27.9 User Interface ACIFB Register Memory Map Register Control Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Status Clear Register Test Register Parameter Register Version Register Window0 Configuration Register Window1 Configuration Register Window2 Configuration Register Window3 Configuration Register AC0 Configuration Register AC1 Configuration Register AC2 Configuration Register AC3 Configuration Register AC4 Configuration Register AC5 Configuration Register AC6 Configuration Register AC7 Configuration Register Register Name CTRL SR IER IDR IMR ISR ICR TR PARAMETER VERSION CONFW0 CONFW1 CONFW2 CONFW3 CONF0 CONF1 CONF2 CONF3 CONF4 CONF5 CONF6 CONF7 Access Read/Write Read-only Write-only Write-only Read-only Read-only Write-only Read/Write Read-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) -(1) 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 27-2. Offset 0x00 0x04 0x10 0x14 0x18 0x1C 0x20 0x24 0x30 0x34 0x80 0x84 0x88 0x8C 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this chapter. 648 32099A–AVR32–06/09 AT32UC3L 27.9.1 Name: Control Register CTRL Read/Write 0x00 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 SUT[9:8] 16 15 14 13 12 SUT[7:0] 11 10 9 8 7 ACTEST 6 - 5 ESTART 4 USTART 3 - 2 - 1 EVENTEN 0 EN • SUT: Startup Time SUT Analog Comparator startup time = ---------------- . F GCLK Each time an AC is enabled, the AC comparison will be enabled after the startup time of the AC. • ACTEST: Analog Comparator Test Mode 0: The Analog Comparator outputs feeds the channel logic in ACIFB. 1: The Analog Comparator outputs are bypassed with the AC Test Register. • ESTART: Peripheral Event Start Single Conversion Writing a zero to this bit has no effect. Writing a one to this bit starts a conversion and can be used for test purposes. This bit is cleared when conversion is done. This bit is set when an enabled peripheral event is received. • USTART: User Start Single Conversion Writing a zero to this bit has no effect. Writing a one to this bit starts a Single Measurement Mode conversion. This bit is cleared when conversion is done. • EVENTEN: Peripheral Event Trigger Enable 0: A peripheral event will not trigger a conversion. 1: Enable conversion triggered by a peripheral event. • EN: ACIFB Enable 0: The ACIFB is disabled. 1: The ACIFB is enabled. 649 32099A–AVR32–06/09 AT32UC3L 27.9.2 Name: Status Register SR Read-only 0x04 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 WFCS3 26 WFCS2 25 WFCS1 24 WFCS0 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 ACRDY7 14 ACCS7 13 ACRDY6 12 ACCS6 11 ACRDY5 10 ACCS5 9 ACRDY4 8 ACCS4 7 ACRDY3 6 ACCS3 5 ACRDY2 4 ACCS2 3 ACRDY1 2 ACCS1 1 ACRDY0 0 ACCS0 • WFCSn: Window Mode Current Status This bit is cleared when the common input voltage is outside the window. This bit is set when the common input voltage is inside the window. • ACRDYn: ACn Ready This bit is cleared when the AC output (ACOUT) is not ready. This bit is set when the AC output (ACOUT) is ready, AC is enabled and its startup time is over. • ACCSn: ACn Current Comparison Status This bit is cleared when VINP is currently lower than VINN This bit is set when VINP is currently greater than VINN. 650 32099A–AVR32–06/09 AT32UC3L 27.9.3 Name: Interrupt Enable Register IER Write-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 WFINT3 26 WFINT2 25 WFINT1 24 WFINT0 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 SUTINT7 14 ACINT7 13 SUTINT6 12 ACINT6 11 SUTINT5 10 ACINT5 9 SUTINT4 8 ACINT4 7 SUTINT3 6 ACINT3 5 SUTINT2 4 ACINT2 3 SUTINT1 2 ACINT1 1 SUTINT0 0 ACINT0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 651 32099A–AVR32–06/09 AT32UC3L 27.9.4 Name: Interrupt Disable Register IDR Write-only 0x14 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 WFINT3 26 WFINT2 25 WFINT1 24 WFINT0 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 SUTINT7 14 ACINT7 13 SUTINT6 12 ACINT6 11 SUTINT5 10 ACINT5 9 SUTINT4 8 ACINT4 7 SUTINT3 6 ACINT3 5 SUTINT2 4 ACINT2 3 SUTINT1 2 ACINT1 1 SUTINT0 0 ACINT0 Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 652 32099A–AVR32–06/09 AT32UC3L 27.9.5 Name: Interrupt Mask Register IMR Read-only 0x18 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 WFINT3 26 WFINT2 25 WFINT1 24 WFINT0 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 SUTINT7 14 ACINT7 13 SUTINT6 12 ACINT6 11 SUTINT5 10 ACINT5 9 SUTINT4 8 ACINT4 7 SUTINT3 6 ACINT3 5 SUTINT2 4 ACINT2 3 SUTINT1 2 ACINT1 1 SUTINT0 0 ACINT0 • WFINTn: Window Mode Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. • SUTINTn: ACn Startup Time Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. • ACINTn: ACn Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. This bit is cleared when the corresponding bit in IDR is written to one. This bit is set when the corresponding bit in IER is written to one. 653 32099A–AVR32–06/09 AT32UC3L 27.9.6 Name: Interrupt Status Register ISR Read-only 0x1C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 WFINT3 26 WFINT2 25 WFINT1 24 WFINT0 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 SUTINT7 14 ACINT7 13 SUTINT6 12 ACINT6 11 SUTINT5 10 ACINT5 9 SUTINT4 8 ACINT4 7 SUTINT3 6 ACINT3 5 SUTINT2 4 ACINT2 3 SUTINT1 2 ACINT1 1 SUTINT0 0 ACINT0 • WFINTn: Window Mode Interrupt Status 0: No Window Mode Interrupt is pending. 1: Window Mode Interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding channel pair operating in window mode generated an interrupt. • SUTINTn: ACn Startup Time Interrupt Status 0: No Startup Time Interrupt is pending. 1: Startup Time Interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the startup time of the corresponding AC has passed. • ACINTn: ACn Interrupt Status 0: No Normal Mode Interrupt is pending. 1: Normal Mode Interrupt is pending. This bit is cleared when the corresponding bit in ICR is written to one. This bit is set when the corresponding channel generated an interrupt. 654 32099A–AVR32–06/09 AT32UC3L 27.9.7 Name: Interrupt Status Clear Register ICR Write-only 0x20 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 WFINT3 26 WFINT2 25 WFINT1 24 WFINT0 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 SUTINT7 14 ACINT7 13 SUTINT6 12 ACINT6 11 SUTINT5 10 ACINT5 9 SUTINT4 8 ACINT4 7 SUTINT3 6 ACINT3 5 SUTINT2 4 ACINT2 3 SUTINT1 2 ACINT1 1 SUTINT0 0 ACINT0 Writing a zero to a bit in this register has no effect. Writing a one to a bitin this register will clear the corresponding bit in ISR and the corresponding interrupt request. 655 32099A–AVR32–06/09 AT32UC3L 27.9.8 Name: Test Register TR Read/Write 0x24 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 ACTEST7 30 22 14 6 ACTEST6 29 21 13 5 ACTEST5 28 20 12 4 ACTEST4 27 19 11 3 ACTEST3 26 18 10 2 ACTEST2 25 17 9 1 ACTEST1 24 16 8 0 ACTEST0 • ACTESTn: AC Output Override Value If CTRL.ACTEST is set, the ACn output is overridden with the value of ACTESTn. 656 32099A–AVR32–06/09 AT32UC3L 27.9.9 Name: Parameter Register PARAMETER Read-only 0x30 - Access Type: Offset: Reset Value: 31 23 15 7 ACIMPL7 30 22 14 6 ACIMPL6 29 21 13 5 ACIMPL5 28 20 12 4 ACIMPL4 27 19 WIMPL3 11 3 ACIMPL3 26 18 WIMPL2 10 2 ACIMPL2 25 17 WIMPL1 9 1 ACIMPL1 24 16 WIMPL0 8 0 ACIMPL0 • WIMPLn: Window Pair n Implemented 0: Window Pair not implemented. 1: Window Pair implemented. • ACIMPLn: Analog Comparator n Implemented 0: Analog Comparator not implemented. 1: Analog Comparator implemented. 657 32099A–AVR32–06/09 AT32UC3L 27.9.10 Name: Version Register VERSION Read-only 0x34 - Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 26 18 VARIANT 25 17 24 16 11 10 9 8 VERSION[11:8] 3 VERSION[7:0] 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 658 32099A–AVR32–06/09 AT32UC3L 27.9.11 Name: Window Configuration Register CONFWn Read/Write 0x80,0x84,0x88,0x8C 0x00000000 Access Type: Offset: Reset Value: 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 16 WFEN 8 WEVSRC 0 WIS 23 - 22 - 21 - 20 - 19 - 18 - 17 - 15 - 14 - 13 - 12 - 11 - 10 WEVEN 9 7 - 6 - 5 - 4 - 3 - 2 - 1 • WFEN: Window Mode Enable 0: The window mode is disabled. 1: The window mode is enabled. • WEVEN: Window Event Enable 0: Event from awout is disabled. 1: Event from awout is enabled. • WEVSRC: Event Source Selection for Window Mode 00: Event on acwout rising edge. 01: Event on acwout falling edge. 10: Event on awout rising or falling edge. 11: Reserved. • WIS: Window Mode Interrupt Settings 00: Window interrupt as soon as the input voltage is inside the window. 01: Window interrupt as soon as the input voltage is outside the window. 10: Window interrupt on toggle of window compare output. 11: Window interrupt when evaluation of input voltage is done. 659 32099A–AVR32–06/09 AT32UC3L 27.9.12 Name: AC Configuration Register CONFn Read/Write 0xD0,0xD4,0xD8,0xDC,0xE0,0xE4,0xE8,0xEC 0x00000000 Access Type: Offset: Reset Value: 31 - 30 29 FLEN 28 27 26 HYS 25 24 23 - 22 - 21 - 20 - 19 - 18 - 17 EVENN 16 EVENP 8 INSELN 0 IS 15 - 14 - 13 - 12 - 11 INSELP 10 9 7 - 6 - 5 MODE 4 3 - 2 - 1 • FLEN: Filter Length 000: Filter off. n: Number of samples to be averaged =2n. • HYS: Hysteresis Value 0000: No hysteresis. 1111: Max hysteresis. • EVENN: Event Enable Negative 0: Do not output event when ACOUT is zero. 1: Output event when ACOUT is zero. • EVENP: Event Enable Positive 0: Do not output event when ACOUT is one. 1: Output event when ACOUT is one. • INSELP: Positive Input Select 00: ACPn pin selected. 01: Reserved. 10: Reserved. 11: Reserved. • INSELN: Negative Input Select 00: ACNn pin selected. 01: ACREFN pin selected. 10: Reserved. 11: Reserved. • MODE: Mode 00: Off. 01: Continuous Measurement Mode. 10: User Triggered Single Measurement Mode. 11: Event Triggered Single Measurement Mode. 660 32099A–AVR32–06/09 AT32UC3L • IS: Interrupt Settings 00: Comparator interrupt when as VINP > VINN. 01: Comparator interrupt when as VINP < VINN. 10: Comparator interrupt on toggle of Analog Comparator output. 11: Comparator interrupt when comparison of VINP and VINN is done. 661 32099A–AVR32–06/09 AT32UC3L 27.10 Module Configuration The specific configuration for each ACIFB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 27-3. Feature ACIFB Configuration ACIFB 8 Number of channels Table 27-4. Module Name ACIFB Module Clock Name Clock Name CLK_ACIFB Table 27-5. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000202 0x000F00FF 662 32099A–AVR32–06/09 AT32UC3L 28. Capacitive Touch Module (CAT) Rev: 2.0.0.0 28.1 Features • • • • • • QTouch™ method allows N touch sensors to be implemented using 2N physical pins QMatrix™ method allows X by Y matrix of sensors to be implemented using (X+2Y) physical pins One autonomous QTouch™ sensor operates without CPU intervention Interfaced with peripheral DMA controller to reduce processor overhead External synchronization to reduce 50 or 60 Hz mains interference Spread spectrum sensor drive capability 28.2 Overview The Capacitive Touch Module (CAT) senses touch on external capacitive touch sensors. Capacitive touch sensors use no external mechanical components, and therefore demand less maintenance in the user application. The module implements the QTouch method of capturing signals from capacitive touch sensors. The QTouch method is generally suitable for small numbers of sensors since it requires 2 physical pins per sensor. The module also implements the QMatrix method, which is more appropriate for large numbers of sensors since it allows an X by Y matrix of sensors to be implemented using only (X+2Y) physical pins. The module allows methods to function together, so N touch sensors and an X by Y matrix of sensors can be implemented using (2N+X+2Y) physical pins. In addition, the module allows sensors using the QTouch method to be divided into two groups. Each QTouch group can be configured with different properties. This eases the implementation of multiple kinds of controls such as push buttons, wheels, and sliders. The module also implements one autonomous QTouch sensor that is capable of detecting touch or proximity without CPU intervention. This allows proximity or activation detection in low-power sleep modes. 663 32099A–AVR32–06/09 AT32UC3L 28.3 Block Diagram Figure 28-1. CAT Block Diagram CLK_CAT Capacitive Touch Module (CAT) Peripheral Bus Interface Registers Counters Finite State Machine Capacitor Charge and Discharge Sequence Generator CSAn CSBn SMP VDIVEN I/O Controller Pins GCLK_CAT NOTE: Italicized signals and blocks are used only for QMatrix operation SYNC DIS Discharge Current Sources Yn Peripheral Event System Analog Comparator Interface Analog Comparators 664 32099A–AVR32–06/09 AT32UC3L 28.4 I/O Lines Description Table 28-1. Name CSAn CSBn DIS SMP SYNC VDIVEN I/O Lines Description Description Capacitive sense A line n Capacitive sense B line n Discharge current control (only used for QMatrix) SMP line (only used for QMatrix) Synchronize signal Voltage divider enable (only used for QMatrix) Type I/O I/O Analog Output Input Output 28.5 Product Dependencies In order to use the CAT module, other parts of the system must be configured correctly, as described below. 28.5.1 I/O Lines The CAT pins may be multiplexed with other peripherals. The user must first program the I/O Controller to give control of the pins to the CAT module. In QMatrix mode, the Y lines must be driven by the CAT and analog comparators sense the voltage on the Y lines. Thus, the CAT (not the Analog Comparator Interface) must be the selected function for the Y lines in the I/O Controller. By writing ones and zeros to bits in the Pin Mode Registers (PINMODEx), most of the CAT pins can be individually selected to implement the QTouch method or the QMatrix method. Each pin has a different name and function depending on whether it is implementing the QTouch method or the QMatrix method. The following table shows the pin names for each method and the bits in the PINMODEx registers which control the selection of the QTouch or QMatrix method. Table 28-2. Pin Selection Guide QTouch Method Pin Name SNS0 SNSK0 SNS1 SNSK1 SNS2 SNSK2 SNS3 SNSK3 SNS4 SNSK4 SNS5 QMatrix Method Pin Name X0 X1 Y0 YK0 X2 X3 Y1 YK1 X4 X5 Y2 Selection Bit in PINMODEx Register SP0 SP0 SP1 SP1 SP2 SP2 SP3 SP3 SP4 SP4 SP5 CAT Module Pin Name CSA0 CSB0 CSA1 CSB1 CSA2 CSB2 CSA3 CSB3 CSA4 CSB4 CSA5 665 32099A–AVR32–06/09 AT32UC3L Table 28-2. Pin Selection Guide QTouch Method Pin Name SNSK5 SNS6 SNSK6 SNS7 SNSK7 SNS8 SNSK8 SNS9 SNSK9 SNS10 SNSK10 SNS11 SNSK11 SNS12 SNSK12 SNS13 SNSK13 SNS14 SNSK14 SNS15 SNSK15 SNS16 SNSK16 QMatrix Method Pin Name YK2 X6 X7 Y3 YK3 X8 X9 Y4 YK4 X10 X11 Y5 YK5 X12 X13 Y6 YK6 X14 X15 Y7 YK7 X16 X17 Selection Bit in PINMODEx Register SP5 SP6 SP6 SP7 SP7 SP8 SP8 SP9 SP9 SP10 SP10 SP11 SP11 SP12 SP12 SP13 SP13 SP14 SP14 SP15 SP15 SP16 SP16 CAT Module Pin Name CSB5 CSA6 CSB6 CSA7 CSB7 CSA8 CSB8 CSA9 CSB9 CSA10 CSB10 CSA11 CSB11 CSA12 CSB12 CSA13 CSB13 CSA14 CSB14 CSA15 CSB15 CSA16 CSB16 28.5.2 Clocks The clock for the CAT module, CLK_CAT, is generated by the Power Manager (PM). This clock is turned on by default, and can be enabled and disabled in the PM. The user must ensure that CLK_CAT is enabled before using the CAT module. QMatrix operations also require the CAT generic clock, GCLK_CAT. This generic clock is generated by the System Control Interface (SCIF), and is shared between the CAT and the Analog Comparator Interface. The user must ensure that the GCLK_CAT is enabled in the SCIF before using QMatrix functionality in the CAT module. For proper QMatrix operation, the frequency of GCLK_CAT must be less than half the frequency of CLK_CAT. If only QTouch functionality is used, then GCLK_CAT is unnecessary. 28.5.3 Interrupts The CAT interrupt request line is connected to the interrupt controller. Using CAT interrupts requires the interrupt controller to be programmed first. 666 32099A–AVR32–06/09 AT32UC3L 28.5.4 Peripheral Events The CAT peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 28.5.5 Peripheral Direct Memory Access The CAT module provides handshake capability for a Peripheral DMA Controller. One handshake controls transfers from the Acquired Count Register (ACOUNT) to memory. A second handshake requests burst lengths for each (X,Y) pair to the Matrix Burst Length Register (MBLEN) when using the QMatrix acquisition method. The Peripheral DMA Controller must be configured properly and enabled in order to perform direct memory access transfers to/from the CAT module. 28.5.6 Analog Comparators When the CAT module is performing QMatrix acquisition, it requires that on-chip analog comparators be used as part of the process. These analog comparators are not controlled directly by the CAT module, but by a separate Analog Comparator (AC) Interface. This interface must be configured properly and enabled before the CAT module is used. This includes configuring the generic clock input for the analog comparators to the proper sampling frequency. The CAT will automatically use the negative peripheral events from the AC Interface on every Y pin in QMatrix mode. When QMatrix acquisition is used the analog comparator corresponding to the selected Y pins must be enabled and converting continuously, using the Y pin as the positive reference and the ACREFN as negative reference. 28.5.7 Debug Operation When an external debugger forces the CPU into debug mode, the CAT continues normal operation. If the CAT is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 28.6 28.6.1 Functional Description Acquisition Types The CAT module can perform three types of QTouch acquisition from capacitive touch sensors: autonomous QTouch (one sensor only), QTouch group A, and QTouch group B. The CAT module can also perform QMatrix acquisition. Each type of acquisition has an associated set of pin selection and configuration registers that allow a large degree of flexibility. The following schematic diagrams show typical hardware connections for QTouch and QMatrix sensors, respectively: 667 32099A–AVR32–06/09 AT32UC3L Figure 28-2. CAT Touch Connections SNSKn QTouch Sensor AVR32 Chip Cs (Sense Capacitor) SNSn Figure 28-3. CAT Matrix Connections X2 X3 X6 X7 QMatrix Sensor Array YK0 Cs0 (Sense Capacitor) Y0 YK1 Cs1 (Sense Capacitor) Y1 AVR32 Chip Rsmp1 SMP Rsmp0 DIS Rdis VDIVEN NOTE: If the CAT internal current sources will be enabled, the SMP signal and Rsmp resistors should NOT be included in the design. If the CAT internal current sources will NOT be enabled, the DIS signal and Rdis resistor should NOT be included in the design. Ra ACREFN Rb In order to use the autonomous QTouch detection capability, the user must first set up the Autonomous Touch Pin Select Register (ATPINS) and Autonomous Touch Configuration Registers (ATCFG0 through 3) with appropriate values. The module can then be enabled using the Control Register (CTRL). After the module is enabled, the module will acquire data from the autonomous QTouch sensor and use it to determine whether the sensor is activated. The active/inactive status of the autonomous QTouch sensor is reported in the Status Register (SR), and it is also possible to configure the CAT to generate an interrupt whenever the status changes. The module will continue acquiring autonomous QTouch sensor data and updating autonomous QTouch status until the module is disabled or reset. In order to use the QMatrix, QTouch group A, or QTouch group B acquisition capabilities, it is first necessary to set up the appropriate pin mode registers (PINMODE0 and PINMODE1) and 668 32099A–AVR32–06/09 AT32UC3L configuration registers (MGCFG0, MGCFG1, TGACFG0, TGACFG1, TGBCFG0, and TGBCFG1). The module must then be enabled using the CTRL register. In order to initiate acquisition, it is necessary to perform a write to the Acquisition Initiation and Selection Register (AISR). The specific value written to AISR determines which type of acquisition will be performed: QMatrix, QTouch group A, or QTouch group B. The CPU can initiate acquisition by writing to the AISR. While QMatrix, QTouch group A, or QTouch group B acquisition is in progress, the module collects count values from the sensors and buffers them. Availability of acquired count data is indicated by the Acquisition Ready (ACREADY) bit in the Status Register (SR). The CPU or the Peripheral DMA Controller can then read the acquired counts from the ACOUNT register. Because the CAT module is configured with Peripheral DMA Controller capability that can transfer data from memory to MBLEN and from ACOUNT to memory, the Peripheral DMA Controller can perform long acquisition sequences and store results in memory without CPU intervention. 28.6.2 Prescaler and Charge Length Each QTouch acquisition type (autonomous QTouch, QTouch group A, and QTouch group B) has its own prescaler. Each QTouch prescaler divides down the CLK_CAT clock to an appropriate sampling frequency for its particular acquisition type. Typical frequencies are 1 MHz for QTouch acquisition and 4MHz for QMatrix burst timing control. Each QTouch prescaler is controlled by the DIV field in the appropriate Configuration Register 0 (ATCFG0, TGACFG0, or TGBCFG0). The QMatrix burst timing prescaler is controlled by the DIV field in MGCFG0. Each prescaler uses the following formula to generate the sampling clock: Sampling clock = CLK_CAT / (2(DIV+1)) The capacitive sensor charge length, discharge length, and settle length can be determined for each acquisition type using the CHLEN, DILEN, and SELEN fields in Configuration Registers 0 and 1. The lengths are specified in terms of prescaler clocks. In addition, the QMatrix Cx discharge length can be determined using the CXDILEN field in MGCFG2. For QMatrix acquisition, the duration of CHLEN should not be set to the same value as the period of any periodic signal on any other pin. If the duration of CHLEN is the same as the period of a signal on another pin, it is likely that the other signal will significantly affect measurements due to stray capacitive coupling. For example, if a 1 MHz signal is generated on another pin of the chip, then CHLEN should not be 1 microsecond. For the QMatrix method, burst and capture lengths are set for each (X,Y) pair by writing the desired length values to the MBLEN register. The write must be done before each X line can start its acquisition and is indicated by the status bit MBLREQ in the Status Register (SR). A DMA handshake interface is also connected to this status bit to reduce CPU overhead during QMatrix acquisitions. Four burst lengths (BURST0..3) can be written at one time into the MBLEN register. If the current configuration uses Y lines larger than Y3 the register has to be written a second time. The first write to MBLEN specifies the burst length for Y lines 0 to 3 in the BURST0 to BURST3 fields, respectively. The second write specifies the burst length for Y lines 4 to 7 in fields BURST0 to BURST3, respectively, and so on. The Y and YK pins remain clamped to ground apart from the specified number of burst pulses, when charge is transferred and captured into the sampling capacitor. 669 32099A–AVR32–06/09 AT32UC3L 28.6.3 Capacitive Count Acquisition For the QMatrix, QTouch group A, and QTouch group B types of acquisition, the module acquires count values from the sensors, buffers them, and makes them available for reading in the ACOUNT register. Further processing of the count values must be performed by the CPU. When the module performs QMatrix acquisition using multiple Y lines, it starts the capture for each Y line at the appropriate time in the burst sequence so that all captures finish simultaneously. For example, suppose that an acquisition is performed on Y0 and Y1 with BURST0=53 and BURST1=60. The module will first toggle the X line 7 times while capturing on Y1 while Y0 and YK0 are clamped to ground. The module will then toggle the X line 53 times while capturing on both Y1 and Y0. 28.6.4 Autonomous QTouch For autonomous QTouch, a complete detection algorithm is implemented within the CAT module. The additional parameters needed to control the autonomous QTouch detection algorithm must be specified by the user in the ATCFG2 and ATCFG3 registers. Autonomous QTouch sensitivity and out-of-touch sensitivity can be adjusted with the SENSE and OUTSENS fields, respectively, in ATCFG2. Each field accepts values from one to 255 where 255 is the least sensitive setting. The value in the OUTSENS field should be smaller than the value in the SENSE field. To avoid false positives a detect integration filtering technique can be used. The number of successive detects required is specified in the FILTER field of the ATCFG2 register. To compensate for changes in capacitance the CAT can recalibrate the autonomous QTouch sensor periodically. The timing of this calibration is done with the NDRIFT and PDRIFT fields in the Configuration register, ATCFG3. It is recommended that the PDRIFT value is smaller than the NDRIFT value. The autonomous QTouch sensor will also recalibrate if the count value goes too far positive beyond a threshold. This positive recalibration threshold is specified by the PTHR field in the ATCFG3 register. The following block diagram shows the sequence of acquisition and processing operations used by the CAT module. The AISR written bit is internal and not visible in the user interface. 670 32099A–AVR32–06/09 AT32UC3L Figure 28-4. CAT Acquisition and Processing Sequence Idle AISR written flag set? No Yes Acquire counts Autonomous touch enabled (ATEN)? No Yes Acquire autonomous touch count Wait for all acquired counts to be transferred Update autonomous touch detection algorithm Clear AISR written flag 28.6.5 Spread Spectrum Sensor Drive To reduce electromagnetic compatibility issues, the capacitive sensors can be driven with a spread spectrum signal. To enable spread spectrum drive for a specific acquisition type, the user must write a one to the SPREAD bit in the appropriate Configuration Register 1 (MGCFG1, ATCFG1, TGACFG1, or TGBCFG1). During spread spectrum operation, the length of each pulse within a burst is varied in a deterministic pattern, so that the exact same burst pattern is used for a specific burst length. The maximum spread is determined by the MAXDEV field in the Spread Spectrum Configuration Register (SSCFG) register. The prescaler divisor is varied in a sawtooth pattern from (DIVMAXDEV) to (DIV+MAXDEV) and then back to (DIV-MAXDEV). For example, if DIV is 8 and MAXDEV is 3, the prescaler divisor will have the following sequence: 8,9,10,11,5,6,7,8,9,10,11,5,6,etc. 671 32099A–AVR32–06/09 AT32UC3L 28.6.6 Synchronization To prevent interference from the 50 or 60 Hz mains line the CAT can trigger acquisition on the SYNC signal. The SYNC signal should be derived from the mains line. The acquisition will trigger on a falling edge of this signal. To enable synchronization for a specific acquisition type, the user must write a one to the SYNC bit in the appropriate Configuration Register 1 (MGCFG1, ATCFG1, TGACFG1, or TGBCFG1). For QMatrix acquisition, all X lines must be sampled at a specific phase of the noise signal for the synchronization to be effective. This can be accomplished by the synchronization timer, which is enabled by writing a non-zero value to the SYNCTIM field in the MGCFG2 register. This ensures that the start of the acquisition of each X line is spaced at regular intervals, defined by the SYNCTIM field. 28.6.7 Resistive Drive By default, the CAT pins are driven with normal I/O drive properties. Some of the CSA and CSB pins can optionally drive with a 1k output resistance for improved EMC. The pins that have this capability are listed in the Module Configuration section. Discharge Current Source The device integrates a discharge current source, which can be used to discharge the sampling capacitors during the QMatrix measurement phase. The discharge current source is enabled by writing the EN bits in the Discharge Current Source (DICS) register to one. This enables an internal reference voltage, which can be the internal 1.1V band gap voltage or VDDIO/2, as selected by the INTVREFSEL bit in the DICS register. If the DICS.INTREFSEL bit is one, the reference voltage is applied across an internal resistor. Otherwise the voltage is applied to the DIS pin, and an external resistor must be connected between DIS and ground. This allows the discharge current to be programmed between 2 and 20 uA. The reference current is mirrored to each Y-pin if the corresponding bit is written to one in the DICS.SOURCES field. The reference current can be fine-tuned by writing the trim value to the DICS.TRIM field, allowing the user to compensate e.g. for temperature gradients in the resistance value. 28.6.8 672 32099A–AVR32–06/09 AT32UC3L 28.7 User Interface CAT Register Memory Map Register Control Register Autonomous Touch Pin Selection Register Pin Mode Register 0 Pin Mode Register 1 Autonomous Touch Configuration Register 0 Autonomous Touch Configuration Register 1 Autonomous Touch Configuration Register 2 Autonomous Touch Configuration Register 3 Touch Group A Configuration Register 0 Touch Group A Configuration Register 1 Touch Group B Configuration Register 0 Touch Group B Configuration Register 1 Matrix Group Configuration Register 0 Matrix Group Configuration Register 1 Matrix Group Configuration Register 2 Status Register Status Clear Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Acquisition Initiation and Selection Register Acquired Count Register Matrix Burst Length Register Discharge Current Source Register Spread Spectrum Configuration Register CSA Resistor Control Register CSB Resistor Control Register Autonomous Touch Base Count Register Autonomous Touch Current Count Register Analog Comparator Shift Offset Register 0 Analog Comparator Shift Offset Register 1 Analog Comparator Shift Offset Register 2 Analog Comparator Shift Offset Register 3 Analog Comparator Shift Offset Register 4 Analog Comparator Shift Offset Register 5 Register Name CTRL ATPINS PINMODE0 PINMODE1 ATCFG0 ATCFG1 ATCFG2 ATCFG3 TGACFG0 TGACFG1 TGBCFG0 TGBCFG1 MGCFG0 MGCFG1 MGCFG2 SR SCR IER IDR IMR AISR ACOUNT MBLEN DICS SSCFG CSARES CSBRES ATBASE ATCURR ACSHI0 ACSHI1 ACSHI2 ACSHI3 ACSHI4 ACSHI5 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read-only Write-only Write-only Write-only Read-only Read/Write Read-only Write-only Read/Write Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 Table 28-3. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x80 0x84 0x88 0x8C 0x90 0x94 673 32099A–AVR32–06/09 AT32UC3L Table 28-3. Offset 0x98 0x9C 0xF8 0xFC CAT Register Memory Map Register Analog Comparator Shift Offset Register 6 Analog Comparator Shift Offset Register 7 Parameter Register Version Register Register Name ACSHI6 ACSHI7 PARAMETER VERSION Access Read/Write Read/Write Read-only Read-only Reset 0x00000000 0x00000000 674 32099A–AVR32–06/09 AT32UC3L 28.7.1 Name: Control Register CTRL Read/Write 0x00 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 SWRST 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 EN • SWRST: Software reset Writing a zero to this bit has no effect. Writing a one to this bit resets the module. The module will be disabled after the reset. This bit always reads as zero. • EN: Module enable 0: Module is disabled. 1: Module is enabled. 675 32099A–AVR32–06/09 AT32UC3L 28.7.2 Name: Autonomous Touch Pin Selection Register ATPINS Read/Write 0x04 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 27 19 11 3 26 18 10 2 ATSP 25 17 9 1 24 16 8 ATEN 0 • ATEN: Autonomous Touch Enable 0: Autonomous QTouch acquisition and detection is disabled. 1: Autonomous QTouch acquisition and detection is enabled using the sense pair specified in ATSP. • ATSP: Autonomous Touch Sense Pair Selects the sense pair that will be used by the autonomous QTouch sensor. A value of n will select sense pair n (CSAn and CSBn pins). 676 32099A–AVR32–06/09 AT32UC3L 28.7.3 Name: Pin Mode Registers 0 and 1 PINMODE0 and PINMODE1 Read/Write 0x08, 0x0C 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 - 19 18 17 16 SP[16] 15 14 13 12 SP[15:8] 11 10 9 8 7 6 5 4 SP[7:0] 3 2 1 0 • SP: Sense Pair Mode Selection Each SP[n] bit determines the operation mode of sense pair n (CSAn and CSBn pins). The (PINMODE1.SP[n] PINMODE0.SP[n]) bits have the following definitions: 00: Sense pair n disabled. 01: Sense pair n is assigned to QTouch Group A. 10: Sense pair n is assigned to QTouch Group B. 11: Sense pair n is assigned to the QMatrix Group. 677 32099A–AVR32–06/09 AT32UC3L 28.7.4 Name: Autonomous Touch Configuration Register 0 ATCFG0 Read/Write 0x10 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DIV[15:8] 27 26 25 24 23 22 21 20 DIV[7:0] 19 18 17 16 15 14 13 12 CHLEN 11 10 9 8 7 6 5 4 SELEN 3 2 1 0 • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.The prescaler uses the following formula to generate the sampling clock: Sampling clock = CLK_CAT / (2(DIV+1)) • CHLEN: Charge Length For the autonomous QTouch sensor, specifies how many sample clock cycles should be used for transferring charge to the sense capacitor. • SELEN: Settle Length For the autonomous QTouch sensor, specifies how many sample clock cycles should be used for settling after charge transfer. 678 32099A–AVR32–06/09 AT32UC3L 28.7.5 Name: Autonomous Touch Configuration Register 1 ATCFG1 Read/Write 0x14 0x00000000 Access Type: Offset: Reset Value: 31 23 30 29 DISHIFT 28 27 - 26 25 SYNC 24 SPREAD 16 22 21 20 DILEN 19 18 17 15 14 13 12 MAX[15:8] 11 10 9 8 7 6 5 4 MAX[7:0] 3 2 1 0 • DISHIFT: Discharge Shift For the autonomous QTouch sensor, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time. • SYNC: Sync Pin For the autonomous QTouch sensor, specifies that acquisition shall begin when a falling edge is received on the SYNC line. • SPREAD: Spread Spectrum Sensor Drive For the autonomous QTouch sensor, specifies that spread spectrum sensor drive shall be used. • DILEN: Discharge Length For the autonomous QTouch sensor, specifies how many sample clock cycles the CAT should use to discharge the capacitors before charging them. • MAX: Maximum Count For the autonomous QTouch sensor, specifies how many counts the maximum acquisition should be. 679 32099A–AVR32–06/09 AT32UC3L 28.7.6 Name: Autonomous Touch Configuration Register 2 ATCFG2 Read/Write 0x18 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 - 21 20 19 18 FILTER 17 16 15 14 13 12 OUTSENS 11 10 9 8 7 6 5 4 SENSE 3 2 1 0 • FILTER: Autonomous Touch Filter Setting For the autonomous QTouch sensor, specifies how many positive detects in a row the CAT needs to have on the autonomous QTouch sensor before reporting it as a touch. A FILTER value of 0 is not allowed and will result in undefined behavior. • OUTSENS: Out-of-Touch Sensitivity For the autonomous QTouch sensor, specifies how sensitive the out-of-touch detector should be. • SENSE: Sensitivity For the autonomous QTouch sensor, specifies how sensitive the touch detector should be. 680 32099A–AVR32–06/09 AT32UC3L 28.7.7 Name: Autonomous Touch Configuration Register 3 ATCFG3 Read/Write 0x1C 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 PTHR 19 18 17 16 15 14 13 12 PDRIFT 11 10 9 8 7 6 5 4 NDRIFT 3 2 1 0 • PTHR: Positive Recalibration Threshold For the autonomous QTouch sensor, specifies how far a sensor’s signal must move in a positive direction from the reference in order to cause a recalibration. • PDRIFT: Positive Drift Compensation For the autonomous QTouch sensor, specifies how often a positive drift compensation should be performed. When this field is zero, positive drift compensation will never be performed. When this field is non-zero, the positive drift compensation time interval is given by the following formula: Tpdrift = PDRIFT * 65536 * (sample clock period) • NDRIFT: Negative Drift Compensation For the autonomous QTouch sensor, specifies how often a negative drift compensation should be performed. When this field is zero, negative drift compensation will never be performed. When this field is non-zero, the negative drift compensation time interval is given by the following formula: Tndrift = NDRIFT * 65536 * (sample clock period) With the typical sample clock frequency of 1 MHz, PDRIFT and NDRIFT can be set from 0.066 seconds to 16.7 seconds with 0.066 second resolution. 681 32099A–AVR32–06/09 AT32UC3L 28.7.8 Name: Touch Group x Configuration Register 0 TGxCFG0 Read/Write 0x20, 0x28 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DIV[15:8] 27 26 25 24 23 22 21 20 DIV[7:0] 19 18 17 16 15 14 13 12 CHLEN 11 10 9 8 7 6 5 4 SELEN 3 2 1 0 • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.The prescaler uses the following formula to generate the sampling clock: Sampling clock = CLK_CAT / (2(DIV+1)) • CHLEN: Charge Length For the QTouch method, specifies how many sample clock cycles should be used for transferring charge to the sense capacitor. • SELEN: Settle Length For the QTouch method, specifies how many sample clock cycles should be used for settling after charge transfer. 682 32099A–AVR32–06/09 AT32UC3L 28.7.9 Name: Touch Group x Configuration Register 1 TGxCFG1 Read/Write 0x24, 0x2C 0x00000000 Access Type: Offset: Reset Value: 31 23 30 22 29 DISHIFT 21 28 27 - 26 18 25 SYNC 17 24 SPREAD 16 20 DILEN 19 15 14 13 12 MAX[15:8] 11 10 9 8 7 6 5 4 MAX[7:0] 3 2 1 0 • DISHIFT: Discharge Shift For the sensors in QTouch group x, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time. • SYNC: Sync Pin For sensors in QTouch group x, specifies that acquisition shall begin when a falling edge is received on the SYNC line. • SPREAD: Spread Spectrum Sensor Drive For sensors in QTouch group x, specifies that spread spectrum sensor drive shall be used. • DILEN: Discharge Length For sensors in QTouch group x, specifies how many clock cycles the CAT should use to discharge the capacitors before charging them. • MAX: Touch Maximum Count For sensors in QTouch group x, specifies how many counts the maximum acquisition should be. 683 32099A–AVR32–06/09 AT32UC3L 28.7.10 Name: Matrix Group Configuration Register 0 MGCFG0 Read/Write 0x30 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 DIV[15:8] 27 26 25 24 23 22 21 20 DIV[7:0] 19 18 17 16 15 14 13 12 CHLEN 11 10 9 8 7 6 5 4 SELEN 3 2 1 0 • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 4 MHz to produce the burst timing clock.The prescaler uses the following formula to generate the burst timing clock: Burst timing clock = CLK_CAT / (2(DIV+1)) • CHLEN: Charge Length For QMatrix sensors, specifies how many burst prescaler clock cycles should be used for transferring charge to the sense capacitor. • SELEN: Settle Length For QMatrix sensors, specifies how many burst prescaler clock cycles should be used for settling after charge transfer. 684 32099A–AVR32–06/09 AT32UC3L 28.7.11 Name: Matrix Group Configuration Register 1 MGCFG1 Read/Write 0x34 0x00000000 Access Type: Offset: Reset Value: 31 23 30 29 DISHIFT 28 27 - 26 25 SYNC 24 SPREAD 16 22 21 20 DILEN 19 18 17 15 14 13 12 MAX[15:8] 11 10 9 8 7 6 5 4 MAX[7:0] 3 2 1 0 • DISHIFT: Discharge Shift For QMatrix sensors, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time. • SYNC: Sync Pin For QMatrix sensors, specifies that acquisition shall begin when a falling edge is received on the SYNC line. • SPREAD: Spread Spectrum Sensor Drive For QMatrix sensors, specifies that spread spectrum sensor drive shall be used. • DILEN: Discharge Length For QMatrix sensors, specifies how many burst prescaler clock cycles the CAT should use to discharge the capacitors at the beginning of a burst sequence. • MAX: Maximum Count For QMatrix sensors, specifies how many counts the maximum acquisition should be. 685 32099A–AVR32–06/09 AT32UC3L 28.7.12 Name: Matrix Group Configuration Register 2 MGCFG2 Read/Write 0x38 0x00000000 Access Type: Offset: Reset Value: 31 ACCTRL 23 30 29 CONSEN 28 27 26 - 25 24 22 21 20 CXDILEN 19 18 17 16 15 14 - 13 12 11 10 9 8 SYNCTIM[11:8] 5 4 SYNCTIM[7:0] 3 2 1 0 7 6 • ACCTRL: Analog Comparator Control When written to one, allows the CAT to disable the analog comparators when they are not needed. When written to zero, the analog comparators are always enabled. • CONSEN: Consensus Filter Length For QMatrix sensors, specifies that discharge will be terminated when CONSEN out of the most recent 5 comparator samples are positive. For example, a value of 3 in the CONSEN field will terminate discharge when 3 out of the most recent 5 comparator samples are positive. When CONSEN has the default value of 0, discharge will be terminated immediately when the comparator output goes positive. • CXDILEN: Cx Capacitor Discharge Length For QMatrix sensors, specifies how many burst prescaler clock cycles the CAT should use to discharge the Cx capacitor at the end of each burst cycle. • SYNCTIM: Sync Time Interval When non-zero, determines the number of prescaled clock cycles between the start of the acquisition on each X line for QMatrix acquisition. 686 32099A–AVR32–06/09 AT32UC3L 28.7.13 Name: Status Register SR Read-only 0x3C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 MBLREQ 27 19 11 3 ATSTATE 26 18 10 2 ATSC 25 17 9 ACQDONE 1 ATCAL 24 16 8 ACREADY 0 ENABLED • ACQDONE: Acquisition Done 0: Acquisition is not done (still in progress). 1: Acquisition is complete. • ACREADY: Acquired Count Data is Ready 0: Acquired count data is not available in the ACOUNT register. 1: Acquired count data is available in the ACOUNT register. • MBLREQ: Matrix Burst Length Required 0: The QMatrix acquisition does not require any burst lengths. 1: The QMatrix acquisition requires burst lengths for the current X line. • ATSTATE: Autonomous Touch Sensor State 0: The autonomous QTouch sensor is not active. 1: The autonomous QTouch sensor is active. • ATSC: Autonomous Touch Sensor Status Interrupt 0: No status change in the autonomous QTouch sensor. 1: Status change in the autonomous QTouch sensor. • ATCAL: Autonomous Touch Calibration Ongoing 0: The autonomous QTouch sensor is not calibrating. 1: The autonomous QTouch sensor is calibrating. • ENABLED: Module Enabled 0: The module is disabled. 1: The module is enabled. 687 32099A–AVR32–06/09 AT32UC3L 28.7.14 Name: Status Clear Register SCR Write-only 0x40 - Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 ATSC 25 17 9 ACQDONE 1 ATCAL 24 16 8 ACREADY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 688 32099A–AVR32–06/09 AT32UC3L 28.7.15 Name: Interrupt Enable Register IER Write-only 0x44 - Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 ATSC 25 17 9 ACQDONE 1 ATCAL 24 16 8 ACREADY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 689 32099A–AVR32–06/09 AT32UC3L 28.7.16 Name: Interrupt Disable Register IDR Write-only 0x48 - Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 ATSC 25 17 9 ACQDONE 1 ATCAL 24 16 8 ACREADY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 690 32099A–AVR32–06/09 AT32UC3L 28.7.17 Name: Interrupt Mask Register IMR Read-only 0x4C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 ATSC 25 17 9 ACQDONE 1 ATCAL 24 16 8 ACREADY 0 - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 691 32099A–AVR32–06/09 AT32UC3L 28.7.18 Name: Acquisition Initiation and Selection Register AISR Read/Write 0x50 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 - 19 18 17 16 15 14 13 12 - 11 10 9 8 7 6 5 - 4 3 2 1 ACQSEL 0 • ACQSEL: Acquisition Type Selection A write to this register initiates an acquisition of the following type: 00: QTouch Group A. 01: QTouch Group B. 10: QMatrix Group. 11: Undefined behavior. A read of this register will return the value that was previously written. 692 32099A–AVR32–06/09 AT32UC3L 28.7.19 Name: Acquired Count Register ACOUNT Read-only 0x54 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 Y 27 26 25 24 23 22 21 20 SPORX 19 18 17 16 15 14 13 12 COUNT[15:8] 11 10 9 8 7 6 5 4 COUNT[7:0] 3 2 1 0 • Y: Y index The Y index (for QMatrix method) associated with this count value. • SPORX: Sensor pair or X index The sensor pair index (for QTouch method) or X index (for QMatrix method) associated with this count value. • COUNT: Count value The signal (number of counts) acquired on the channel specified in the SPORX and Y fields. When multiple acquired count values are read from a QTouch acquisition, the Y field will always be 0 and the SPORX value will increase monotonically. For example, suppose a QTouch acquisition is performed using sensor pairs SP1, SP4, and SP9. The first count read will have SPORX=1, the second read will have SPORX=4, and the third read will have SPORX=9. When multiple acquired count values are read from a QMatrix acquisition, the SPORX value will stay the same while Y increases monotonically through all Y values in the group. Then SPORX will increase to the next X value in the group. For example, a QMatrix acquisition with X=2,3 and Y=4,7 would provide count values in the following order: X=2 and Y=4, then X=2 and Y=7, then X=3 and Y=4, and finally X=3 and Y=7. 693 32099A–AVR32–06/09 AT32UC3L 28.7.20 Name: Matrix Burst Length Register MBLEN Write-only 0x58 - Access Type: Offset: Reset Value: 31 30 29 28 BURST0 27 26 25 24 23 22 21 20 BURST1 19 18 17 16 15 14 13 12 BURST2 11 10 9 8 7 6 5 4 BURST3 3 2 1 0 • BURSTx: Burst Length x For QMatrix sensors, specifies how many times the switching sequence should be repeated before acquisition begins for each channel. Each count in the BURSTx field specifies 1 repeat of the switching sequence, so the actual burst length will be BURST. Before doing a QMatrix acquisition on one X line this register has to be written with the burst values for the current XY pairs. For each X line this register needs to be programmed with all the Y values. If Y values larger than 3 are used the register has to be written several times in order to specify all burst lengths. The Status Register bit MBLREQ is set to 1 when the CAT is waiting for values to be written into this register. 694 32099A–AVR32–06/09 AT32UC3L 28.7.21 Name: Discharge Current Source Register DICS Read/Write 0x5C 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 27 26 25 24 FSOURCES[7:0] 23 GLEN 15 7 22 14 6 21 13 5 4 3 20 12 19 11 18 10 TRIM 2 1 0 17 INTVREFSEL 16 INTREFSEL 8 9 SOURCES[7:0] • FSOURCES: Force Discharge Current Sources When FSOURCES[n] is 0, the corresponding discharge current source behavior depends on SOURCES[n]. When FSOURCES[n] is 1, the corresponding discharge current source is forced to be enabled continuously. This is useful for testing or debugging but should not be done during normal acquisition. • GLEN: Global Enable 0: The current source module is globally disabled. 1: The current source module is globally enabled. • INTVREFSEL: Internal Voltage Reference Select 0: The voltage for the reference resistor is generated from the internal band gap circuit. 1: The voltage for the reference resistor is VDDIO/2. • INTREFSEL: Internal Reference Select 0: The reference current flows through an external resistor on the DIS pin. 1: The reference current flows through the internal reference resistor. • TRIM: Reference Current Trimming This field is used to trim the discharge current. 0x00 corresponds to the minimum current value, and 0x1F corresponds to the maximum current value. • SOURCES: Enable Discharge Current Sources When SOURCES[n] is 0, the corresponding discharge current source is disabled. When SOURCES[n] is 1, the corresponding discharge current source is enabled at appropriate times during acquisition. 695 32099A–AVR32–06/09 AT32UC3L 28.7.22 Name: Spread Spectrum Configuration Register SSCFG Read/Write 0x60 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 MAXDEV 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 • MAXDEV: Maximum Deviation When spread spectrum burst is enabled, MAXDEV indicates the maximum number of prescaled clock cycles the burst pulse will be extended or shortened. 696 32099A–AVR32–06/09 AT32UC3L 28.7.23 Name: CSA Resistor Control Register CSARES Read/Write 0x64 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 - 19 18 17 16 RES[16] 15 14 13 12 RES[15:8] 11 10 9 8 7 6 5 4 RES[7:0] 3 2 1 0 • RES: Resistive Drive Enable When RES[n] is 0, CSA[n] has the same drive properties as normal I/O pads. When RES[n] is 1, CSA[n] has a nominal output resistance of 1kOhm during the burst phase. 697 32099A–AVR32–06/09 AT32UC3L 28.7.24 Name: CSB Resistor Control Register CSBRES Read/Write 0x68 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 - 19 18 17 16 RES[16] 15 14 13 12 RES[15:8] 11 10 9 8 7 6 5 4 RES[7:0] 3 2 1 0 • RES: Resistive Drive Enable When RES[n] is 0, CSB[n] has the same drive properties as normal I/O pads. When RES[n] is 1, CSB[n] has a nominal output resistance of 1kOhm during the burst phase. 698 32099A–AVR32–06/09 AT32UC3L 28.7.25 Name: Autonomous Touch Base Count Register ATBASE Read-only 0x6C 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 - 19 18 17 16 15 14 13 12 COUNT[15:8] 11 10 9 8 7 6 5 4 COUNT[7:0] 3 2 1 0 • COUNT: Count value The base count currently stored by the autonomous touch sensor. This is useful for autonomous touch debugging purposes. 699 32099A–AVR32–06/09 AT32UC3L 28.7.26 Name: Autonomous Touch Current Count Register ATCURR Read-only 0x70 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 - 19 18 17 16 15 14 13 12 COUNT[15:8] 11 10 9 8 7 6 5 4 COUNT[7:0] 3 2 1 0 • COUNT: Count value The current count acquired by the autonomous touch sensor. This is useful for autonomous touch debugging purposes. 700 32099A–AVR32–06/09 AT32UC3L 28.7.27 Name: Analog Comparator Shift Offset Register x ACSHIx Read/Write 0x80, 0x84, 0x88, 0x8C, 0x90, 0x94, 0x98, and 0x9C 0x00000000 Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 - 19 18 17 16 15 14 - 13 12 11 10 SHIVAL[11:8] 9 8 7 6 5 4 SHIVAL[7:0] 3 2 1 0 • SHIVAL: Shift Offset Value Specifies the amount to shift the count value from each comparator. This allows the offset of each comparator to be compensated. 701 32099A–AVR32–06/09 AT32UC3L 28.7.28 Name: Parameter Register PARAMETER Read-only 0xF8 - Access Type: Offset: Reset Value: 31 30 29 28 - 27 26 25 24 23 22 21 20 SP[23:16] 19 18 17 16 15 14 13 12 SP[15:8] 11 10 9 8 7 6 5 4 SP[7:0] 3 2 1 0 • SP[n]: Sensor pair implemented 0: The corresponding sensor pair is not implemented 1: The corresponding sensor pair is implemented. 702 32099A–AVR32–06/09 AT32UC3L 28.7.29 Name: Version Register VERSION Read-only 0xFC - Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 26 18 VARIANT 25 17 24 16 11 10 9 8 VERSION[11:8] 3 VERSION[7:0] 2 1 0 • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated. 703 32099A–AVR32–06/09 AT32UC3L 28.8 Module Configuration The specific configuration the CAT module is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 28-4. Module Name CAT Module Clock Name Clock Name CLK_CAT Table 28-5. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000200 0x0001FFFF 28.8.1 Resistive Drive By default, the CAT pins are driven with normal I/O drive properties. Some of the CSA and CSB pins can optionally drive with a 1k output resistance for improved EMC. To enable resistive drive on a pin, the user must write a one to the corresponding bit in the CSA Resistor Control Register (CSARES) or CSB Resistor Control Register (CSBRES) register. 704 32099A–AVR32–06/09 AT32UC3L 29. Glue Logic Controller (GLOC) Rev.: 1.0.0.0 29.1 Features • • • • Glue logic for general purpose PCB design Programmable lookup table Up to four inputs supported per lookup table Optional filtering of output 29.2 Overview The Glue Logic Controller (GLOC) contains programmable logic which can be connected to the device pins. This allows the user to eliminate logic gates for simple glue logic functions on the PCB. The GLOC consists of a number of lookup table (LUT) units. Each LUT can generate an output as a user programmable logic expression with four inputs. Inputs can be individually masked. The output can be combinatorially generated from the inputs, or filtered to remove spikes. 29.3 Block Diagram Figure 29-1. GLOC Block Diagram PERIPHERAL BUS TRUTH FILTER OUT[0] ... OUT[n] FILTEN AEN LUT IN[3:0] … IN[(4n+3):4n] 705 32099A–AVR32–06/09 AT32UC3L 29.4 I/O Lines Description Table 29-1. Pin Name IN0-INm OUT0-OUTn I/O Lines Description Pin Description Inputs to lookup tables Output from lookup tables Type Input Output Each LUT have 4 inputs and one output. The inputs and outputs for the LUTs are mapped sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to IN[4n+3] and OUTn. 29.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 29.5.1 I/O Lines The pins used for interfacing the GLOC may be multiplexed with I/O Controller lines. The programmer must first program the I/O Controller to assign the desired GLOC pins to their peripheral function. If I/O lines of the GLOC are not used by the application, they can be used for other purposes by the I/O Controller. It is only required to enable the GLOC input and outputs actually in use. 29.5.2 Clocks The clock for the GLOC bus interface (CLK_GLOC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the GLOC before disabling the clock, to avoid freezing the module in an undefined state. Additionally, the GLOC depends on a dedicated Generic Clock (GCLK). The GCLK can be set to a wide range of frequencies and clock sources, and must be enabled by the System Control Interface (SCIF) before the GLOC filter can be used. 29.5.3 Debug Operation When an external debugger forces the CPU into debug mode, the GLOC continues normal operation. 29.6 29.6.1 Functional Description Enabling the Lookup Table Inputs Since the inputs to each lookup table (LUT) unit can be multiplexed with other peripherals, each input must be explicitly enabled by writing a one to the corresponding enable bit (AEN) in the corresponding Lookup Table Control Register ( LUTCR). If no inputs are enabled, the output OUTn will be the least significant bit in the TRUTHn register. 706 32099A–AVR32–06/09 AT32UC3L 29.6.2 Configuring the Lookup Table The lookup table in each LUT unit can generate any logic expression OUT as a function of up to four inputs, IN[3:0]. The truth table for the expression is written to the TRUTH register for the LUT. Table 29-2 shows the truth table for LUT0. The truth table for LUTn is written to TRUTHn, and the corresponing input and outputs will be IN[4n] to IN[4n+3] and OUTn. Table 29-2. IN[3] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Truth Table for the Lookup Table in LUT0 IN[2] 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IN[1] 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IN[0] 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OUT[0] TRUTH0[0] TRUTH0[1] TRUTH0[2] TRUTH0[3] TRUTH0[4] TRUTH0[5] TRUTH0[6] TRUTH0[7] TRUTH0[8] TRUTH0[9] TRUTH0[10] TRUTH0[11] TRUTH0[12] TRUTH0[13] TRUTH0[14] TRUTH0[15] 29.6.3 Output Filter By default, the output OUTn is a combinatorial function of the inputs IN[4n] to IN[4n+3]. This may cause some short glitches to occur when the inputs change value. It is also possible to clock the output through a filter to remove glitches. This requires that the corresponding generic clock (GCLK) has been enabled before use. The filter can then be enabled by writing a one to the Filter Enable (FILTEN) bit in LUTCRn. The OUTn output will be delayed by three to four GCLK cycles when the filter is enabled. 707 32099A–AVR32–06/09 AT32UC3L 29.7 User Interface GLOC Register Memory Map Register Lookup Table Control Register n Truth Table Register n Parameter Register Version Register Register Name LUTCRn TRUTHn PARAMETER VERSION Access Read/Write Read/Write Read-only Read-only Reset 0x00000000 0x00000000 - (1) - (1) Table 29-3. Offset 0x00+n*0x08 0x04+n*0x08 0x38 0x3C Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 708 32099A–AVR32–06/09 AT32UC3L 29.7.1 Name: Lookup Table Control Register n LUTCRn Read/Write 0x00+n*0x08 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 FILTEN 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 2 AEN 1 0 • FILTEN: Filter Enable 1: The output is glitch filtered 0: The output is not glitch filtered • AEN: Enable IN Inputs Input IN[n] is enabled when AEN[n] is one. Input IN[n] is disabled when AEN[n] is zero, and will not affect the OUT value. 709 32099A–AVR32–06/09 AT32UC3L 29.7.2 Name: Truth Table Register n TRUTHn Read/Write 0x04+n*0x08 0x00000000 30 29 28 27 26 25 24 - Access Type: Offset: Reset Value: 31 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 14 13 12 TRUTH[15:8] 11 10 9 8 7 6 5 4 TRUTH[7:0] 3 2 1 0 • TRUTH: Truth Table Value This value defines the output OUT as a function of inputs IN: OUT = TRUTH[IN] 710 32099A–AVR32–06/09 AT32UC3L 29.7.3 Name: Parameter Register PARAMETER Read-only 0x38 - Access Type: Offset: Reset Value: 31 23 15 - 30 22 14 - 29 21 13 - 28 20 12 - 27 19 11 - 26 18 10 - 25 17 9 - 24 16 8 - 7 6 5 4 LUTS 3 2 1 0 • LUTS: Lookup Table Units Implemented This field contains the number of lookup table units implemented in this device. 711 32099A–AVR32–06/09 AT32UC3L 29.7.4 Name: VERSION Register VERSION Read-only 0x3C - Access Type: Offset: Reset Value: 31 23 15 - 30 22 14 - 29 21 13 - 28 20 12 - 27 19 26 18 VARIANT 25 17 24 16 11 10 9 8 VERSION[11:8] 7 6 5 4 VERSION[7:0] 3 2 1 0 • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated. 712 32099A–AVR32–06/09 AT32UC3L 29.8 Module Configuration The specific configuration for each GLOC instance is listed in the following tables.The GLOC bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 29-4. Feature Number of LUT units GLOC Configuration GLOC 2 Table 29-5. GLOC Name GLOC GLOC Clock Name Clock Name CLK_GLOC Table 29-6. Register VERSION PARAMETER Register Reset Values Reset Value 0x00000100 0x00000002 713 32099A–AVR32–06/09 AT32UC3L 30. aWire UART (AW) Rev.: 2.1.0.0 30.1 Features • Asynchronous receiver or transmitter when the aWire system is not used for debugging. • One- or two-pin operation supported. 30.2 Overview If the AW is not used for debugging, the aWire UART can be used by the user to send or receive data with one stop bit, eight data bits, no parity bits, and one stop bit. This can be controlled through the aWire UART user interface. This chapter only describes the aWire UART user interface. For a description of the aWire Debug Interface, please see the Programming and Debugging chapter. 714 32099A–AVR32–06/09 AT32UC3L 30.3 Block Diagram Figure 30-1. aWire Debug Interface Block Diagram PB aWire Debug Interface CHIP_ERASE command Flash Controller CPU AW User Interface HALT command RESET command Power Manager External reset AW_ENABLE AW CONTROL Reset filter RESET_N SAB interface RW SZ ADDR DATA Baudrate Detector UART CRC SAB 30.4 I/O Lines Description I/O Lines Description Description aWire data multiplexed with the RESET_N pin. Type Input/Output Table 30-1. Name DATA 30.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 715 32099A–AVR32–06/09 AT32UC3L 30.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin. To enable the aWire functionality on the RESET_N pin the user must enable the aWire UART user interface. 30.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the aWire UART user interface, the aWire UART user interface will stop functioning and resume operation after the system wakes up from sleep mode. Clocks The aWire UART uses the internal 120 MHz RC oscillator (RC120M) as clock source for its operation. When using the aWire UART user interface RC120M must enabled using the Clock Request Register (see Section 30.6.1). The clock for the aWire UART user interface (CLK_AW) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the aWire UART user interface before disabling the clock, to avoid freezing the aWire UART user interface in an undefined state. 30.5.4 Interrupts The aWire UART user interface interrupt request line is connected to the interrupt controller. Using the aWire UART user interface interrupt requires the interrupt controller to be programmed first. 30.5.5 Debug Operation If the AW is used for debugging the aWire UART user interface will not be usable. When an external debugger forces the CPU into debug mode, the aWire UART user interface continues normal operation. If the aWire UART user interface is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging. 30.5.6 External Components The AW needs an external pullup on the RESET_N pin to ensure that the pin is pulled up when the bus is not driven. 30.5.3 30.6 Functional Description The aWire UART user interface can be used as a spare Asynchronous Receiver or Transmitter when AW is not used for debugging. 30.6.1 How to Initialize The Module To initialize the aWire UART user interface the user must first enable the clock by writing a one to the Clock Enable bit in the Clock Request Register (CLKR.CLKEN) and wait for the Clock Enable bit in the Status Register (SR.CENABLED) to be set. After doing this either receive, transmit or receive with resync must be selected by writing the corresponding value into the Mode field of the Control (CTRL.MODE) Register. Due to the RC120M being asynchronous the with the system clock values must be allowed to propagate in the system. During this time the aWire master will set the Busy bit in the Status Register (SR.BUSY). 716 32099A–AVR32–06/09 AT32UC3L After the SR.BUSY bit is cleared the Baud Rate field in the Baud Rate Register (BRR.BR) can be written with the wanted baudrate ( f br ) according to the following formula ( f aw is the RC120M clock frequency): 8 f aw f br = ---------BR After this operation the user must wait until the SR.BUSY is cleared. The interface is now ready to be used. 30.6.2 Basic Asynchronous Receiver Operation The aWire UART user interface must be initialized according to the sequence above, but the CTRL.MODE field must be written to one (Receive mode). When a data byte arrives the aWire UART user interface will indicate this by setting the Data Ready Interrupt bit in the Status Register (SR.DREADYINT). The user must read the Data in the Receive Holding Register (RHR.RXDATA) and clear the Interrupt bit by writing a one to the Data Ready Interrupt Clear bit in the Status Clear Register (SCR.DREADYINT). The interface is now ready to receive another byte. 30.6.3 Basic Asynchronous Transmitter Operation The aWire UART user interface must be initialized according to the sequence above, but the CTRL.MODE field must be written to two (Transmit mode). To transmit a data byte the user must write the data to the Transmit Holding Register (THE.TXDATA). Before the next byte can be written the SR.BUSY must be cleared. 30.6.4 Basic Asynchronous Receiver with Resynchronization By writing three into CTRL.MODE the aWire UART user interface will assume that the first byte it receives is a sync byte (0x55) and set BRR.BR according to this. All subsequent transfers will assume this baudrate, unless BRR.BR is rewritten by the user. To make the aWire UART user interface accept a new sync resynchronization the aWire UART user interface must be disabled by writing zero to CTRL.MODE and then reenable the interface. 30.6.5 Overrun In Receive mode an overrun can occur if the user has not read the previous received data from the RHR.RXDATA when the newest data should be placed there. Such a condition is flagged by setting the Overrun bit in the Status Register (SR.OVERRUN). If SR.OVERRUN is set the newest data received is placed in RHR.RXDATA and the data that was there before is overwritten. 30.6.6 Interrupts To make the CPU able to do other things while waiting for the aWire UART user interface to finish its operations the aWire UART user interface supports generating interrupts. All status bits in the Status Register can be used as interrupt sources, except the SR.BUSY and SR.CENABLED bits. To enable an interrupt the user must write a one to the corresponding bit in the Interrupt Enable Register (IER). Upon the next zero to one transition of this SR bit the aWire UART user interface will flag this interrupt to the CPU. To clear the interrupt the user must write a one to the corresponding bit in the Status Clear Register (SCR). 717 32099A–AVR32–06/09 AT32UC3L Interrupts can be disabled by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The interrupt Mask Register (IMR) can be read to check if an interrupt is enabled or disabled. 30.6.7 Using the Peripheral DMA Controller To relieve the CPU of data transfers the aWire UART user interface support using the Peripheral DMA controller. To transmit using the Peripheral DMA Controller do the following: 1. Setup the aWire UART user interface in transmit mode. 2. Setup the Peripheral DMA Controller with buffer address and length, use byte as transfer size. 3. Enable the Peripheral DMA Controller. 4. Wait until the Peripheral DMA Controller is done. To receive using the Peripheral DMA Controller do the following: 1. Setup the aWire UART user interface in receive mode 2. Setup the Peripheral DMA Controller with buffer address and length, use byte as transfer size. 3. Enable the Peripheral DMA Controller. 4. Wait until the Peripheral DMA Controller is ready. 718 32099A–AVR32–06/09 AT32UC3L 30.7 User Interface aWire UART user interface Register Memory Map Register Control Register Status Register Status Clear Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Baud Rate Register Version Register Clock Request Register Register Name CTRL SR SCR IER IDR IMR RHR THR BRR VERSION CLKR Access Read/Write Read-only Write-only Write-only Write-only Read-only Read-only Read/Write Read/Write Read-only Read/Write Reset 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 -(1) 0x00000000 Table 30-2. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter. 719 32099A–AVR32–06/09 AT32UC3L 30.7.1 Name: Control Register CTRL Read/Write 0x00 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 MODE 24 16 8 0 • MODE: aWire UART user interface mode Table 30-3. MODE 0 1 2 3 aWire UART user interface Modes Mode Description Disabled Receive Transmit Receive with resync. 720 32099A–AVR32–06/09 AT32UC3L 30.7.2 Name: Status Register SR Read-only 0x04 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 TRMIS 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 OVERRUN 2 CENABLED 25 17 9 DREADYINT 1 - 24 16 8 READYINT 0 BUSY • TRMIS: Transmit Mismatch 0: No transfers mismatches. 1: The transceiver was active when receiving. This bit is set when the transceiver is active when receiving. This bit is cleared when corresponding bit in SCR is written to one. • OVERRUN: Data Overrun 0: No data overwritten in RHR. 1: Data in RHR has been overwritten before it has been read. This bit is set when data in RHR is overwritten before it has been read. This bit is cleared when corresponding bit in SCR is written to one. • DREADYINT: Data Ready Interrupt 0: No new data in the RHR. 1: New data received and placed in the RHR. This bit is set when new data is received and placed in the RHR. This bit is cleared when corresponding bit in SCR is written to one. • READYINT: Ready Interrupt 0: The interface has not generated an ready interrupt. 1: The interface has had a transition from busy to not busy. This bit is set when the interface has transition from busy to not busy. This bit is cleared when corresponding bit in SCR is written to one. • CENABLED: Clock Enabled 0: The aWire clock is not enabled. 1: The aWire clock is enabled. 721 32099A–AVR32–06/09 AT32UC3L This bit is set when the clock is disabled. This bit is cleared when the clock is enabled. • BUSY: Synchronizer Busy 0: The asynchronous interface is ready to accept more data. 1: The asynchronous interface is busy and will block writes to CTRL, BRR, and THR. This bit is set when the asynchronous interface becomes busy. This bit is cleared when the asynchronous interface becomes ready. 722 32099A–AVR32–06/09 AT32UC3L 30.7.3 Name: Status Clear Register SCR Write-only 0x08 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 TRMIS 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 OVERRUN 2 - 25 17 9 DREADYINT 1 - 24 16 8 READYINT 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request. 723 32099A–AVR32–06/09 AT32UC3L 30.7.4 Name: Interrupt Enable Register IER Write-only 0x0C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 TRMIS 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 OVERRUN 2 - 25 17 9 DREADYINT 1 - 24 16 8 READYINT 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR. 724 32099A–AVR32–06/09 AT32UC3L 30.7.5 Name: Interrupt Disable Register IDR Write-only 0x10 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 TRMIS 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 OVERRUN 2 - 25 17 9 DREADYINT 1 - 24 16 8 READYINT 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR. 725 32099A–AVR32–06/09 AT32UC3L 30.7.6 Name: Interrupt Mask Register IMR Read-only 0x14 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 TRMIS 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 OVERRUN 2 - 25 17 9 DREADYINT 1 - 24 16 8 READYINT 0 - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one. A bit in this register is set when the corresponding bit in IER is written to one. 726 32099A–AVR32–06/09 AT32UC3L 30.7.7 Name: Receive Holding Register RHR Read-only 0x18 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 RXDATA 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 • RXDATA: Received Data The last byte received. 727 32099A–AVR32–06/09 AT32UC3L 30.7.8 Name: Transmit Holding Register THR Read/Write 0x1C 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 TXDATA 27 19 11 3 26 18 10 2 25 17 9 1 24 16 8 0 • TXDATA: Transmit Data The data to send. 728 32099A–AVR32–06/09 AT32UC3L 30.7.9 Name: Baud Rate Register BRR Read/Write 0x20 0x00000000 Access Type: Offset: Reset Value: 31 23 15 30 22 14 29 21 13 28 20 12 BR[15:8] 27 19 11 26 18 10 25 17 9 24 16 8 7 6 5 4 BR[7:0] 3 2 1 0 • BR: Baud Rate The baud rate ( f br ) of the transmission, calculated using the following formula ( f aw is the RC120M frequency): 8 f aw f br = ---------BR BR should not be set to a value smaller than 32. Writing a value to this field will update the baud rate of the transmission. Reading this field will give the current baud rate of the transmission. 729 32099A–AVR32–06/09 AT32UC3L 30.7.10 Name: Version Register VERSION Read-only 0x24 0x00000200 Access Type: Offset: Reset Value: 31 23 15 7 30 22 14 6 29 21 13 5 28 20 12 4 27 19 11 26 18 10 25 17 9 24 16 8 VERSION[11:8] 3 VERSION[7:0] 2 1 0 • VERSION: Version Number Version number of the module. No functionality associated. 730 32099A–AVR32–06/09 AT32UC3L 30.7.11 Name: Clock Request Register CLKR Read/Write 0x28 0x00000000 Access Type: Offset: Reset Value: 31 23 15 7 - 30 22 14 6 - 29 21 13 5 - 28 20 12 4 - 27 19 11 3 - 26 18 10 2 - 25 17 9 1 - 24 16 8 0 CLKEN • CLKEN: Clock Enable 0: The aWire clock is disabled. 1: The aWire clock is enabled. Writing a zero to this bit will disable the aWire clock. Writing a one to this bit will enable the aWire clock. 731 32099A–AVR32–06/09 AT32UC3L 30.8 Module Configuration The specific configuration for each aWire instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 30-4. Module name aWire Module clock name Clock name CLK_AW Table 30-5. Register VERSION Register Reset Values Reset Value 0x00000210 732 32099A–AVR32–06/09 AT32UC3L 31. Programming and Debugging 31.1 Overview The AT32UC3L supports programming and debugging through two interfaces, JTAG or aWire™. JTAG is an industry standard interface and allows boundary scan for PCB testing, as well as daisy-chaining of multiple devices on the PCB. aWire is an Atmel proprietary protocol which offers higher throughput and robust communication, and does not require application pins to be reserved. Either interface provides access to the internal Service Access Bus (SAB), which offers a bridge to the High Speed Bus, giving access to memories and peripherals in the device. By using this bridge to the bus system, the flash and fuses can thus be programmed by accessing the Flash Controller in the same manner as the CPU. The SAB also provides access to the Nexus-compliant On-Chip Debug (OCD) system in the device, which gives the user non-intrusive run-time control of the program execution. Additionally, trace information can be output on the Auxiliary (AUX) debug port or buffered in internal RAM for later retrieval by JTAG or aWire. 31.2 Service Access Bus The AVR32 architecture offers a common interface for access to On-Chip Debug, programming, and test functions. These are mapped on a common bus called the Service Access Bus (SAB), which is linked to the JTAG and aWire port through a bus master module, which also handles synchronization between the debugger and SAB clocks. When accessing the SAB through the debugger there are no limitations on debugger frequency compared to chip frequency, although there must be an active system clock in order for the SAB accesses to complete. If the system clock is switched off in sleep mode, activity on the debugger will restart the system clock automatically, without waking the device from sleep. Debuggers may optimize the transfer rate by adjusting the frequency in relation to the system clock. This ratio can be measured with debug protocol specific instructions. The Service Access Bus uses 36 address bits to address memory or registers in any of the slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared. 31.2.1 SAB Address Map The Service Access Bus (SAB) gives the user access to the internal address space and other features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32 LSBs are decoded within the slave’s address space. The SAB slaves are shown in Table 31-1. Table 31-1. Slave Unallocated OCD HSB SAB Slaves, Addresses and Descriptions Address [35:32] 0x0 0x1 0x4 Description Intentionally unallocated OCD registers HSB memory space, as seen by the CPU 733 32099A–AVR32–06/09 AT32UC3L Table 31-1. Slave HSB Memory Service Unit Reserved SAB Slaves, Addresses and Descriptions Address [35:32] 0x5 0x6 Other Description Alternative mapping for HSB space, for compatibility with other AVR32 devices. Memory Service Unit registers Unused 31.2.2 SAB Security Restrictions The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below. Security measure and control location A security measure is a mechanism to either block or allow SAB access to a certain address or address range. A security measure is enabled or disabled by one or several control signals. This is called the control location for the security measure. These security measures can be used to prevent an end user from reading out the code programmed in the flash, for instance. Table 31-2. SAB Security Measures Control Location FLASHCDW SECURE bits set FLASHCDW security bit set FLASHCDW UPROT + security bit set Description Allocates a portion of the flash for secure code. This code cannot be read or debugged. Programming and debugging not possible, very restricted access. Restricts all access except parts of the flash and the flash controller for programming user code. Debugging is not possible unless an OS running from the secure part of the flash supports it. 31.2.2.1 Security Measure Secure mode Security bit User code programming Below follows a more in depth description of what locations are accessible when the security measures are active. Table 31-3. Name Secure flash area Secure RAM area Other accesses Secure Mode SAB Restrictions Address Start 0x580000000 0x500000000 Address End 0x580000000 + (USERROW[15:0]