AT32UC3L064-D3HR

Features • High Performance, Low Power 32-bit AVR® Microcontroller – Compact Single-Cycle RISC Instruction Set Including DSP Instructions – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performance • Up to 64 DMIPS Running at 50MHz from Flash (1 Flash Wait State) • Up to 36 DMIPS Running at 25MHz from Flash (0 Flash Wait State) – Memory Protection Unit (MPU) • Secure Access Unit (SAU) providing user defined peripheral protection picoPower® Technology for Ultra-Low Power Consumption Multi-Hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 12 Peripheral DMA Channels Improve Speed for Peripheral Communication Internal High-Speed Flash – 64Kbytes, 32Kbytes, and 16Kbytes Versions – Single-Cycle Access up to 25MHz – FlashVault™ Technology Allows Pre-programmed Secure Library Support for End User Applications – Prefetch Buffer Optimizing Instruction Execution at Maximum Speed – 100,000 Write Cycles, 15-year Data Retention Capability – Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM, Single-Cycle Access at Full Speed – 16Kbytes (64Kbytes and 32Kbytes Flash), or 8Kbytes (16Kbytes Flash) Interrupt Controller (INTC) – Autovectored Low Latency Interrupt Service with Programmable Priority External Interrupt Controller (EIC) Peripheral Event System for Direct Peripheral to Peripheral Communication System Functions – Power and Clock Manager – SleepWalking™ Power Saving Control – Internal System RC Oscillator (RCSYS) – 32 KHz Oscillator – Multipurpose Oscillator and Digital Frequency Locked Loop (DFLL) Windowed Watchdog Timer (WDT) Asynchronous Timer (AST) with Real-Time Clock Capability – Counter or Calendar Mode Supported Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency Six 16-bit Timer/Counter (TC) Channels – External Clock Inputs, PWM, Capture and Various Counting Capabilities PWM Channels on All I/O Pins (PWMA) – 8-bit PWM up to 150MHz Source Clock Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Independent Baudrate Generator, Support for SPI – Support for Hardware Handshaking One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals – Up to 15 SPI Slaves can be Addressed Two Master and Two Slave Two-Wire Interfaces (TWI), 400kbit/s I2C-compatible One 8-channel Analog-To-Digital Converter (ADC) with up to 12 Bits Resolution – Internal Temperature Sensor • • 32-bit AVR® Microcontroller AT32UC3L064 AT32UC3L032 AT32UC3L016 Preliminary Summary • • • • • • • • • • • • • • • 32099DS–06/2010 AT32UC3L016/32/64 • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module – Hardware Assisted QTouch® and QMatrix® Touch Acquisition – Supports QTouch® and QMatrix® Capture from Capacitive Touch Sensors QTouch® Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch® and QMatrix® Acquisition On-Chip Non-Intrusive Debug System – Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace – aWire™ Single-Pin Programming Trace and Debug Interface Muxed with Reset Pin – NanoTrace™ Provides Trace Capabilities through JTAG or aWire Interface 48-pin TQFP/QFN/TLLGA (36 GPIO Pins) Five High-Drive I/O Pins Single 1.62-3.6V Power Supply • • • • • 2 32099DS–06/2010 AT32UC3L016/32/64 1. Description The AT32UC3L is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. The Secure Access Unit (SAU) is used together with the MPU to provide the required security and integrity. Higher computation capability is achieved using a rich set of DSP instructions. The AT32UC3L embeds state-of-the-art picoPower technology for ultra-low power consumption. Combined power control techniques are used to bring active current consumption down to 165 µA/MHz, and leakage down to 9 nA while still retaining a bank of backup registers. The device allows a wide range of trade-offs between functionality and power consumption, giving the user the ability to reach the lowest possible power consumption with the feature set required for the application. The Peripheral Direct Memory Access (DMA) controller enables data transfers between peripherals and memories without processor involvement. The Peripheral DMA controller drastically reduces processing overhead when transferring continuous and large data streams. The AT32UC3L incorporates on-chip Flash and SRAM memories for secure and fast access. The FlashVault technology allows secure libraries to be programmed into the device. The secure libraries can be executed while the CPU is in Secure State, but not read by non-secure software in the device. The device can thus be shipped to end costumers, who will be able to program their own code into the device, accessing the secure libraries, but without risk of compromising the proprietary secure code. The Peripheral Event System allows peripherals to receive, react to, and send peripheral events without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low power sleep modes. The Power Manager improves design flexibility and security. The Power Manager supports SleepWalking functionality, by which a module can be selectively activated based on peripheral events, even in sleep modes where the module clock is stopped. Power monitoring is supported by on-chip Power-On Reset (POR), Brown-Out Detector (BOD), and Supply Monitor (SM). The device features several oscillators, such as Digital Frequency Locked Loop (DFLL), Oscillator 0 (OSC0), and system RC oscillator (RCSYS). Either of these oscillators can be used as source for the system clock. The DFLL is a programmable internal oscillator from 40 to 150MHz. It can be tuned to a high accuracy if an accurate oscillator is running, e.g. the 32KHz crystal oscillator. The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable. The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in counter mode or calendar mode. The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it to a known reference clock. 3 32099DS–06/2010 AT32UC3L016/32/64 The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing, and pulse width modulation. The Pulse Width Modulation controller (PWMA) provides 8-bit PWM channels which can be synchronized and controlled from a common timer. One PWM channel is available for each I/O pin on the device, enabling applications that require multiple PWM outputs, such as LCD backlight control. The PWM channels can operate independently, with duty cycles set independently from each other, or in interlinked mode, with multiple channels changed at the same time. The AT32UC3L also features many communication interfaces for communication intensive applications like USART, SPI, or TWI. A general purpose 8-channel ADC is provided, as well as eight analog comparators (AC). The ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel. The analog comparators can be paired to detect when the sensing voltage is within or outside the defined reference window. The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using the QTouch technology. Capacitive touch sensors use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. One touch sensor can be configured to operate autonomously without software interaction, allowing wakeup from sleep modes when activated. Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and included fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications. The AT32UC3L integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access, in addition to basic runtime control. The NanoTrace interface enables trace feature for aWire- or JTAG-based debuggers. The single-pin aWire interface allows all features available through the JTAG interface to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or peripherals. 4 32099DS–06/2010 AT32UC3L016/32/64 2. Overview 2.1 Block Diagram Figure 2-1. Block Diagram MEMORY INTERFACE MCKO MDO[5..0] MSEO[1..0] EVTI_N EVTO_N TCK TDO TDI TMS RESET_N DATAOUT LOCAL BUS INTERFACE LOCAL BUS AVR32UC CPU NEXUS CLASS 2+ OCD JTAG INTERFACE aWire MEMORY PROTECTION UNIT INSTR INTERFACE DATA INTERFACE 16/8 KB SRAM M M HIGH SPEED BUS MATRIX M S FLASH CONTROLLER 64/32/16 KB FLASH SAU S/M S M S CONFIGURATION S REGISTERS BUS HSB-PB BRIDGE B HSB-PB BRIDGE A PERIPHERAL DMA CONTROLLER GENERALPURPOSE I/Os POWER MANAGER CLOCK CONTROLLER SLEEP CONTROLLER RESET CONTROLLER DMA CSA[16:0] PA PB CAPACITIVE TOUCH MODULE USART0 USART1 USART2 USART3 CSB[16:0] SMP SYNC RXD TXD CLK RTS, CTS SCK DMA R CSYS RC32K NPCS[3..0] DMA RC120M XIN32 XOUT32 XIN0 XOUT0 OSC32K OSC0 DFLL BOD SYSTEM CONTROL INTERFACE TWI MASTER 0 TWI MASTER 1 TWCK TWD TWALM TWCK GENERAL PURPOSE I/Os GCLK[4..0] DMA SPI MISO, MOSI PA PB TWI SLAVE 0 TWI SLAVE 1 DMA TWD TWALM DMA INTERRUPT CONTROLLER EXTINT[5..1] NMI 8-CHANNEL ADC INTERFACE AD[8..0] ADVREFP EXTERNAL INTERRUPT CONTROLLER PWM CONTROLLER ASYNCHRONOUS TIMER WATCHDOG TIMER FREQUENCY METER AC INTERFACE TIMER/COUNTER 0 TIMER/COUNTER 1 A[2..0] B[2..0] PWM[35..0] CLK[2..0] ACBP[3..0] ACBN[3..0] ACAP[3..0] ACAN[3..0] ACREFN GLUE LOGIC CONTROLLER OUT[1:0] IN[7..0] 5 32099DS–06/2010 AT32UC3L016/32/64 2.2 Configuration Summary Table 2-1. Feature Flash SRAM GPIO High-drive pins External Interrupts TWI USART Peripheral DMA Channels Peripheral Event System SPI Asynchronous Timers Timer/Counter Channels PWM channels Frequency Meter Watchdog Timer Power Manager Secure Access Unit Glue Logic Controller Configuration Summary AT32UC3L064 64KB 16KB AT32UC3L032 32KB 16KB 36 5 6 2 4 12 1 1 1 6 36 1 1 1 1 1 Digital Frequency Locked Loop 40-150 MHz (DFLL) Crystal Oscillator 3-16 MHz (OSC0) Crystal Oscillator 32 KHz (OSC32K) RC Oscillator 120MHz (RC120M) RC Oscillator 115 kHz (RCSYS) RC Oscillator 32 kHz (RC32K) 8-channel 12-bit 1 8 1 1 1 50 MHz TQFP48/QFN48/TLLGA48 AT32UC3L016 16KB 8KB Oscillators ADC Temperature Sensor Analog Comparators Capacitive Touch Module JTAG aWire Max Frequency Package 6 32099DS–06/2010 AT32UC3L016/32/64 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2. Figure 3-1. TQFP48/QFN48 Pinout PA15 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 37 38 39 40 41 42 43 44 45 46 47 48 12 11 10 9 8 7 6 5 4 3 2 1 PA05 PA00 PA06 PA22 PB03 PB02 PB00 PB12 PA03 PA08 PA09 GND 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 PA21 PB10 RESET_N PB04 PB05 GND VDDCORE VDDIN PB01 PA07 PA01 PA02 7 32099DS–06/2010 AT32UC3L016/32/64 Figure 3-2. TLLGA48 Pinout 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 PA16 PA17 PA19 PA18 VDDIO GND PB11 GND PA10 PA12 VDDIO 38 39 40 41 42 43 44 45 46 47 48 PA21 PB10 RESET_N PB04 PB05 GND VDDCORE VDDIN PB01 PA07 PA01 13 12 11 10 9 8 7 6 5 4 3 2 1 PA02 PA05 PA00 PA06 PA22 PB03 PB02 PB00 PB12 PA03 PA08 PA09 GND 8 32099DS–06/2010 AT32UC3L016/32/64 3.2 3.2.1 Peripheral Multiplexing on I/O lines Multiplexed signals Each GPIO line can be assigned to one of the peripheral functions.The following table describes the peripheral signals multiplexed to the GPIO lines. GPIO Controller Function Multiplexing GPIO Function G PI O 0 1 2 3 4 Table 3-1. Q F P 48 11 14 13 4 28 PIN PA00 PA01 PA02 PA03 PA04 Supply VDDIO VDDIO VDDIO VDDIO VDDIO Pad Type Normal I/O Normal I/O Highdrive I/O Normal I/O Normal I/O TWI, Normal I/O Highdrive I/O, 5V tolerant TWI, Normal I/O Highdrive I/O Highdrive I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O TWI, Normal I/O A USART0TXD USART0RXD USART0RTS USART0CTS SPI-MISO B USART1RTS USART1CTS ADCIFBTRIGGER SPINPCS[1] TWIMS0TWCK TWIMS1TWCK C SPINPCS[2] SPINPCS[3] USART2TXD USART2TXD USART1RXD USART1TXD D E PWMAPWMA[0] F G SCIFGCLK[0] H CAT-CSA[2] CAT-CSA[1] CAT-CSA[3] CAT-CSB[3] CAT-CSA[7] USART1CLK TC0-A0 TC0-B0 TC0-B1 PWMAPWMA[1] PWMAPWMA[2] PWMAPWMA[3] PWMAPWMA[4] PWMAPWMA[5] ACIFBACAP[0] ACIFBACBP[0] ACIFBACBN[3] ACIFBACBP[1] ACIFBACBN[0] TWIMS0TWALM USART0CLK USART0CLK 12 PA05 5 VDDIO SPI-MOSI TC0-A1 TWIMS0TWD CAT-CSB[7] 10 PA06 6 VDDIO SPI-SCK USART2TXD USART1CLK TC0-B0 PWMAPWMA[6] SCIFGCLK[1] CAT-CSB[1] 15 PA07 7 VDDIO SPINPCS[0] USART1TXD USART1RXD TWIMS0TWD USART2RXD SPINPCS[2] SPINPCS[3] TWIMS1TWALM TC0-A2 TC0-B2 TC0-A0 TWIMS0TWCK ADCIFBADP[0] ADCIFBADP[1] PWMAPWMA[7] PWMAPWMA[8] PWMAPWMA[9] PWMAPWMA[10] PWMAPWMA[11] ACIFBACAN[0] NMI CAT-CSB[2] 3 2 46 27 47 26 36 37 38 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 PA16 8 9 10 11 12 13 14 15 16 VDDIO VDDIO VDDIO VDDIN VDDIO VDDIN VDDIO VDDIO VDDIO CAT-CSA[4] SCIF-GCLK[2] ACIFBACAP[1] EICEXTINT[1] SCIFGCLK[2] CAT-CSB[4] CAT-CSA[5] ADCIFBPRND GLOCOUT[0] ADCIFBAD[0] ADCIFBAD[1] ADCIFBAD[2] USART2CLK GLOC-IN[7] TC0-CLK2 TC0-CLK1 TC0-CLK0 TC0-CLK1 TC0-A0 USART2RTS CAT-SMP SCIFGCLK[2] CAT-SMP GLOC-IN[6] GLOC-IN[5] PWMAPWMA[12] PWMAPWMA[13] PWMAPWMA[14] PWMAPWMA[15] PWMAPWMA[16] PWMAPWMA[17] ACIFBACAN[1] CAT-SMP SCIFGCLK[3] EICEXTINT[2] SCIFGCLK[4] CAT-CSB[5] CAT-CSA[0] CAT-CSA[6] CAT-CSB[6] CAT-CSA[8] CAT-SYNC ACIFBACREFN CAT-SMP EICEXTINT[3] EICEXTINT[4] CAT-DIS 39 PA17 17 VDDIO TC0-A1 USART2CTS TWIMS1TWD CAT-CSB[8] 9 32099DS–06/2010 AT32UC3L016/32/64 Table 3-1. 41 40 25 PA18 PA19 PA20 GPIO Controller Function Multiplexing 18 19 20 VDDIO VDDIO VDDIN Normal I/O Normal I/O Normal I/O TWI, 5V tolerant, SMBus, Normal I/O Normal I/O Normal I/O Highdrive I/O Normal I/O Normal I/O TWI, 5V tolerant, SMBus, Normal I/O TWI, 5V tolerant, SMBus, Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O Normal I/O ADCIFBAD[4] ADCIFBAD[5] USART2TXD TC0-B1 TC0-A2 TC0-A1 GLOC-IN[4] TWIMS1TWALM GLOC-IN[3] PWMAPWMA[18] PWMAPWMA[19] PWMAPWMA[20] SCIFRC32OUT CAT-SYNC EICEXTINT[5] CAT-SYNC CAT-CSB[0] CATCSA[10] CATCSA[12] 24 PA21 21 VDDIN USART2RXD TWIMS0TWD TC0-B1 ADCIFBTRIGGER PWMAPWMA[21] PWMAPWMAOD[21] SCIFGCLK[0] CAT-SMP 9 6 16 7 8 PA22 PB00 PB01 PB02 PB03 22 32 33 34 35 VDDIO VDDIO VDDIO VDDIO VDDIO USART0CTS USART3TXD USART3RXD USART3RTS USART3CTS USART2CLK ADCIFBADP[0] ADCIFBADP[1] USART3CLK USART3CLK TC0-B2 SPINPCS[0] SPI-SCK SPI-MISO SPI-MOSI CAT-SMP TC0-A1 TC0-B1 TC0-A2 TC0-B2 PWMAPWMA[22] PWMAPWMA[23] PWMAPWMA[24] PWMAPWMA[25] PWMAPWMA[26] ACIFBACBN[2] ACIFBACAP[2] TC1-A0 TC1-A1 ACIFBACAN[2] ACIFBACBP[2] SCIFGCLK[1] TC1-A2 CATCSB[10] CAT-CSA[9] CAT-CSB[9] CATCSB[11] CATCSA[11] 21 PB04 36 VDDIN TC1-A0 USART1RTS USART1CLK TWIMS0TWALM PWMAPWMA[27] PWMAPWMAOD[27] TWIMS1TWCK CATCSA[14] 20 PB05 37 VDDIN TC1-B0 USART1CTS USART1CLK TWIMS0TWCK PWMAPWMA[28] PWMAPWMAOD[28] SCIFGCLK[3] CATCSB[14] 30 31 32 29 23 44 5 PB06 PB07 PB08 PB09 PB10 PB11 PB12 38 39 40 41 42 43 44 VDDIO VDDIO VDDIO VDDIO VDDIN VDDIO VDDIO TC1-A1 TC1-B1 TC1-A2 TC1-B2 TC1-CLK0 TC1-CLK1 TC1-CLK2 USART3TXD USART3RXD USART3RTS USART3CTS USART1TXD USART1RXD ADCIFBAD[6] ADCIFBAD[7] ADCIFBAD[8] USART3CLK USART3CLK GLOC-IN[2] GLOC-IN[1] GLOC-IN[0] PWMAPWMA[29] PWMAPWMA[30] PWMAPWMA[31] PWMAPWMA[32] ACIFBACAN[3] ACIFBACAP[3] CAT-SYNC ACIFBACBN[1] NMI EICEXTINT[1] EICEXTINT[2] EICEXTINT[3] EICEXTINT[4] CATCSB[13] CATCSA[13] CATCSB[12] CATCSB[15] CATCSB[16] CATCSA[16] CATCSA[15] GLOCOUT[1] ADCIFBTRIGGER PWMAPWMA[33] PWMAPWMA[34] PWMAPWMA[35] CAT-VDIVEN ACIFBACBP[3] EICEXTINT[5] SCIFGCLK[4] TWIMS1TWALM CAT-SYNC See Section 3.3 for a description of the various peripheral signals. Signals are prioritized according to the function priority listed in Table 3-2 on page 11 if multiple functions are enabled simultaneously. Refer to ”Electrical Characteristics” on page 41 for a description of the electrical properties of the pad types used. 10 32099DS–06/2010 AT32UC3L016/32/64 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled. Table 3-2. Function A B C D E F G H Peripheral Functions Description GPIO peripheral selection A GPIO peripheral selection B GPIO peripheral selection C GPIO peripheral selection D GPIO peripheral selection E GPIO peripheral selection F GPIO peripheral selection G GPIO peripheral selection H 3.2.3 JTAG Port Connections If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O Controller configuration. Table 3-3. JTAG Pinout Pin PA00 PA01 PA02 PA03 JTAG Function TCK TMS TDO TDI 48TQFP/QFN/TLLGA 11 14 13 4 3.2.4 Nexus OCD AUX Port Connections If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the I/O Controller configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 3-4. Pin EVTI_N MDO[5] MDO[4] MDO[3] Nexus OCD AUX Port Connections AXS=1 PA05 PA10 PA18 PA17 AXS=0 PB08 PB00 PB04 PB05 11 32099DS–06/2010 AT32UC3L016/32/64 Table 3-4. Pin MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0] Nexus OCD AUX Port Connections AXS=1 PA16 PA15 PA14 PA04 PA06 PA07 PA11 AXS=0 PB03 PB02 PB09 PA04 PB01 PB11 PB12 3.2.5 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. Oscillator Pinout Pin PA08 PA10 PA13 PA09 PA12 PA20 Oscillator Function XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 48TQFP/QFN/TLLGA 3 46 26 2 47 25 3.2.6 Other Functions The functions listed in Table 3-6 are not mapped to the normal GPIO functions.The aWire DATA pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be actice after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is always enabled. Please refer to Section 6.1.4 on page 40 for constraints on the WAKE_N pin. Table 3-6. Other Functions Pin PA11 RESET_N PA00 Function WAKE_N aWire DATA aWire DATAOUT 48TQFP/TQFN/TLLGA 27 22 11 12 32099DS–06/2010 AT32UC3L016/32/64 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7. Signal Name Signal Descriptions List Function Type Analog Comparator Interface - ACIFB Active Level Comments ACAN3 - ACAN0 ACAP3 - ACAP0 ACBN3 - ACBN0 ACBP3 - ACBP0 ACREFN Negative inputs for comparators "A" Positive inputs for comparators "A" Negative inputs for comparators "B" Positive inputs for comparators "B" Common negative reference Analog Analog Analog Analog Analog ADC Interface - ADCIFB AD8 - AD0 ADP1 - ADP0 PRND TRIGGER Analog Signal Drive Pin for resistive touch screen Pseudorandom output signal External trigger aWire - AW DATA DATAOUT aWire data aWire data output for 2-pin mode I/O I/O Analog Output Output Input Capacitive Touch Module - CAT CSA16 - CSA0 CSB16 - CSB0 SMP SYNC VDIVEN Capacitive Sense A Capacitive Sense B SMP signal Synchronize signal Voltage divider enable I/O I/O Output Input Output External Interrupt Controller - EIC NMI EXTINT5 - EXTINT1 Non-Maskable Interrupt External interrupt Input Input Glue Logic Controller - GLOC IN7 - IN0 OUT1 - OUT0 Inputs to lookup tables Outputs from lookup tables Input Output JTAG module - JTAG TCK TDI TDO TMS Test Clock Test Data In Test Data Out Test Mode Select Input Input Output Input 13 32099DS–06/2010 AT32UC3L016/32/64 Table 3-7. Signal Descriptions List Power Manager - PM RESET_N Reset Input Low Pulse Width Modulation Controller - PWMA PWMA35 - PWMA0 PWMAOD35 PWMAOD0 PWMA channel waveforms PWMA channel waveforms, open drain mode Output Output Not all channels support open drain mode System Control Interface - SCIF GCLK4 - GCLK0 RC32OUT XIN0 XIN32 XIN32_2 XOUT0 XOUT32 XOUT32_2 Generic Clock Output RC32K output at startup Crystal 0 Input Crystal 32 Input (primary location) Crystal 32 Input (secondary location) Crystal 0 Output Crystal 32 Output (primary location) Crystal 32 Output (secondary location) Output Output Analog/ Digital Analog/ Digital Analog/ Digital Analog Analog Analog Serial Peripheral Interface - SPI MISO MOSI NPCS3 - NPCS0 SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O I/O Timer/Counter - TC0, TC1 A0 A1 A2 B0 B1 B2 CLK0 CLK1 CLK2 Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input I/O I/O I/O I/O I/O I/O Input Input Input Low Two-wire Interface - TWIMS0, TWIMS1 TWALM TWCK TWD SMBus SMBALERT Two-wire Serial Clock Two-wire Serial Data I/O I/O I/O Low Universal Synchronous/Asynchronous Receiver/Transmitter - USART0, USART1, USART2, USART3 14 32099DS–06/2010 AT32UC3L016/32/64 Table 3-7. CLK CTS RTS RXD TXD Note: Signal Descriptions List Clock Clear To Send Request To Send Receive Data Transmit Data I/O Input Output Input Output Low Low 1. ADCIFB: AD3 does not exist. Table 3-8. Signal Name Signal Description List, continued Function Power Type Active Level Comments VDDCORE Core Power Supply / Voltage Regulator Output Power Input/Output 1.62V to 1.98V 1.62V to 3.6V. VDDIO should always be equal to or lower than VDDIN. 1.62V to 1.98V TBD to 1.98V 1.62V to 3.6V (1) VDDIO I/O Power Supply Power Input VDDANA ADVREFP VDDIN GNDANA GND Analog Power Supply Analog Reference Voltage Voltage Regulator Input Analog Ground Ground Power Input Power Input Power Input Ground Ground Auxiliary Port - AUX MCKO MDO5 - MDO0 MSEO1 - MSEO0 EVTI_N EVTO_N Trace Data Output Clock Trace Data Output Trace Frame Control Event In Event Out Output Output Output Input Output General Purpose I/O pin Low Low PA22 - PA00 PB12 - PB00 1. Parallel I/O Controller I/O Port 0 Parallel I/O Controller I/O Port 1 I/O I/O See Section 6.1 on page 36 15 32099DS–06/2010 AT32UC3L016/32/64 3.4 3.4.1 I/O Line Considerations JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI pins have pull-up resistors when JTAG is enabled. The TCK pin always have pull-up enabled during reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled. Please refer to Section 3.2.3 on page 11 for the JTAG port connections. 3.4.2 PA00 Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the application. 3.4.3 RESET_N Pin The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product. The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debugging, it must not be driven by external circuitry. 3.4.4 TWI0 Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the characteristics indicated in the Electrical Characteristics section. Selected pins are also SMBus compliant (refer to Section 3.2 on page 9). As required by the SMBus specification, these pins provide no leakage path to ground when the AT32UC3L is powered down. This allows other devices on the SMBus to continue communicating even though the AT32UC3L is not powered. This feature is only available when pins PA21/PB04/PB05 are used for TWI0. 3.4.5 TWI1 Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. 3.4.6 GPIO Pins All the I/O lines integrate a pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except PA00. PA20 selects SCIF-RC32OUT (GPIO Function F) as default enabled after reset. 3.4.7 High-Drive Pins The five pins PA02, PA06, PA08, PA09, and PB01 have high-drive output capabilities. Refer to Section 7. on page 41 for electrical characteristics. RC32OUT Pin Clock output at startup After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20, even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by 3.4.8 3.4.8.1 16 32099DS–06/2010 AT32UC3L016/32/64 the system to start other devices or to clock a switching regulator to rise the power supply voltage up to an acceptable value. The clock will be available on PA20 until one of the following conditions are true: •PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT) •PA20 is configured as a General Purpose Input/Output (GPIO) •The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power Manager chapter) The maximum amplitude of the clock signal will be defined by VDDIN. 3.4.8.2 XOUT32_2 function PA20 selects RC32OUT as default enabled after reset. This function is not automatically disabled when the user enables the XOUT32_2 function on PA20. This disturbes the oscillator and may result in the wrong frequency. To avoid this, RC32OUT must be disabled when XOUT32_2 is enabled. ADC Input Pins These pins are regular I/O pins powered from the VDDIO. However, when these pins are used for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range. 3.4.9 17 32099DS–06/2010 AT32UC3L016/32/64 4. Processor and Architecture Rev: 2.1.0.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.1 Features • 32-bit load/store AVR32A RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Privileged and unprivileged modes enabling efficient and secure operating systems Innovative instruction set together with variable instruction length ensuring industry leading code density – DSP extension with saturating arithmetic, and a wide variety of multiply instructions • 3-stage pipeline allowing one instruction per clock cycle for most instructions – Byte, halfword, word, and double word memory access – Multiple interrupt priority levels • MPU allows for operating systems with memory protection • Secure State for supporting FlashVaultTM technology – – – – – 4.2 AVR32 Architecture AVR32 is a new, high-performance 32-bit RISC microprocessor architecture, designed for costsensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance processors. AVR32 extends the AVR family into the world of 32- and 64-bit applications. Through a quantitative approach, a large set of industry recognized benchmarks has been compiled and analyzed to achieve the best code density in its class. In addition to lowering the memory requirements, a compact code size also contributes to the core’s low power characteristics. The processor supports byte and halfword data types without penalty in code size and performance. Memory load and store operations are provided for byte, halfword, word, and double word data with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely linked to the architecture and is able to exploit code optimization features, both for size and speed. In order to reduce code size to a minimum, some instructions have multiple addressing modes. As an example, instructions with immediates often have a compact format with a smaller immediate, and an extended format with a larger immediate. In this way, the compiler is able to use the format giving the smallest code size. Another feature of the instruction set is that frequently used instructions, like add, have a compact format with two operands as well as an extended format with three operands. The larger format increases performance, allowing an addition and a data move in the same instruction in a single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. 18 32099DS–06/2010 AT32UC3L016/32/64 The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced On-Chip Debug (OCD) system, no caches, and a Memory Protection Unit (MPU). Java acceleration hardware is not implemented. AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch, one High Speed Bus master for data access, and one High Speed Bus slave interface allowing other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing. Also, power consumption is reduced by not needing a full High Speed Bus access for memory accesses. A dedicated data RAM interface is provided for communicating with the internal data RAMs. A local bus interface is provided for connecting the CPU to device-specific high-speed systems, such as floating-point units and I/O controller ports. This local bus has to be enabled by writing a one to the LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory range allocated to it, and data transfers are performed using regular load and store instructions. Details on which devices that are mapped into the local bus space is given in the CPU Local Bus section in the Memories chapter. Figure 4-1 on page 20 displays the contents of AVR32UC. 19 32099DS–06/2010 AT32UC3L016/32/64 Figure 4-1. Overview of the AVR32UC CPU Reset interface OCD interface Interrupt controller interface OCD system Power/ Reset control AVR32UC CPU pipeline MPU Instruction memory controller High Speed Bus master High Speed Bus Data memory controller High Speed Bus slave High Speed Bus High Speed Bus master CPU Local Bus master CPU Local Bus CPU RAM 4.3.1 Pipeline Overview AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruction Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) section, and one load/store (LS) section. Instructions are issued and complete in order. Certain operations require several clock cycles to complete, and in this case, the instruction resides in the ID and EX stages for the required number of clock cycles. Since there is only three pipeline stages, no internal data forwarding is required, and no data dependencies can arise in the pipeline. Figure 4-2 on page 21 shows an overview of the AVR32UC pipeline stages. High Speed Bus 20 32099DS–06/2010 AT32UC3L016/32/64 Figure 4-2. The AVR32UC Pipeline MUL Multiply unit IF Prefetch unit ID Decode unit Regfile Read ALU Regfile write ALU unit LS Load-store unit 4.3.2 AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts. Additionally, it does not provide hardware registers for the return address registers and return status registers. Instead, all this information is stored on the system stack. This saves chip area at the expense of slower interrupt handling. Interrupt Handling Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These registers are pushed regardless of the priority level of the pending interrupt. The return address and status register are also automatically pushed to stack. The interrupt handler can therefore use R8-R12 freely. Upon interrupt completion, the old R8-R12 registers and status register are restored, and execution continues at the return address stored popped from stack. The stack is also used to store the status register and return address for exceptions and scall. Executing the rete or rets instruction at the completion of an exception or system call will pop this status register and continue execution at the popped return address. 4.3.2.1 4.3.2.2 Java Support AVR32UC does not provide Java hardware acceleration. 4.3.2.3 Memory Protection The MPU allows the user to check all memory accesses for privilege violations. If an access is attempted to an illegal memory address, the access is aborted and an exception is taken. The MPU in AVR32UC is specified in the AVR32UC Technical Reference manual. Unaligned Reference Handling AVR32UC does not support unaligned accesses, except for doubleword accesses. AVR32UC is able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an 4.3.2.4 21 32099DS–06/2010 AT32UC3L016/32/64 address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. Instruction ld.d st.d Instructions with Unaligned Reference Support Supported Alignment Word Word 4.3.2.5 Unimplemented Instructions The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented Instruction Exception if executed: • All SIMD instructions • All coprocessor instructions if no coprocessors are present • retj, incjosp, popjc, pushjc • tlbr, tlbs, tlbw • cache 4.3.2.6 CPU and Architecture Revision Three major revisions of the AVR32UC CPU currently exist. The device described in this datasheet uses CPU revision 3. The Architecture Revision field in the CONFIG0 system register identifies which architecture revision is implemented in a specific device. AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. code compiled for revision 1 or 2 is binary-compatible with revision 3 CPUs. 22 32099DS–06/2010 AT32UC3L016/32/64 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3. Application Bit 31 Bit 0 Bit 31 The AVR32UC Register File INT0 Bit 31 Bit 0 Supervisor Bit 0 INT1 Bit 31 Bit 0 INT2 Bit 31 Bit 0 INT3 Bit 31 Bit 0 Exception Bit 31 Bit 0 NMI Bit 31 Bit 0 Secure Bit 31 Bit 0 PC LR SP_APP R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SYS R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR PC LR SP_SEC R12 R11 R10 R9 R8 INT0PC R7 INT1PC R6 FINTPC R5 SMPC R4 R3 R2 R1 R0 SR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR 4.4.2 Status Register Configuration The Status Register (SR) is split into two halfwords, one upper and one lower, see Figure 4-4 and Figure 4-5. The lower word contains the C, Z, N, V, and Q condition code flags and the R, T, and L bits, while the upper halfword contains information about the mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details. Figure 4-4. Bit 31 The Status Register High Halfword Bit 16 SS LC 1 0 - - DM D - M2 M1 M0 EM I3M I2M FE I1M I0M GM Bit nam e Initial value G lobal Interrupt M ask Interrupt Level 0 M ask Interrupt Level 1 M ask Interrupt Level 2 M ask Interrupt Level 3 M ask Exception M ask M ode Bit 0 M ode Bit 1 M ode Bit 2 Reserved Debug State Debug State M ask Reserved Secure State 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 23 32099DS–06/2010 AT32UC3L016/32/64 Figure 4-5. Bit 15 The Status Register Low Halfword Bit 0 0 T 0 0 0 0 0 0 0 0 0 L 0 Q 0 V 0 N 0 Z 0 C 0 Bit name Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 4.4.3.1 Processor States Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Table 4-2. Priority 1 2 3 4 5 6 N/A N/A Overview of Execution Modes, their Priorities and Privilege Levels. Mode Non Maskable Interrupt Exception Interrupt 3 Interrupt 2 Interrupt 1 Interrupt 0 Supervisor Application Security Privileged Privileged Privileged Privileged Privileged Privileged Privileged Unprivileged Description Non Maskable high priority interrupt mode Execute exceptions General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode General purpose interrupt mode Runs supervisor calls Normal program execution mode Mode changes can be made under software control, or can be caused by external interrupts or exception processing. A mode can be interrupted by a higher priority mode, but never by one with lower priority. Nested exceptions can be supported with a minimal software overhead. When running an operating system on the AVR32, user processes will typically execute in the application mode. The programs executed in this mode are restricted from executing certain instructions. Furthermore, most system registers together with the upper halfword of the status register cannot be accessed. Protected memory areas are also not available. All other operating modes are privileged and are collectively called System Modes. They have full access to all privileged and unprivileged resources. After a reset, the processor will be in supervisor mode. 4.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor routines that can read out and alter system information for use during application development. This implies that all system and application registers, including the status registers and program counters, are accessible in debug state. The privileged instructions are also available. All interrupt levels are by default disabled when debug state is entered, but they can individually be switched on by the monitor routine by clearing the respective mask bit in the status register. 24 32099DS–06/2010 AT32UC3L016/32/64 Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. The rest of the code can not access resources reserved for this secure code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Technical Reference Manual for details. System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is responsible for maintaining correct sequencing of any instructions following a mtsr instruction. For detail on the system registers, refer to the AVR32UC Technical Reference Manual. Table 4-3. Reg # 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 4.4.4 System Registers Address 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 Name SR EVBA ACBA CPUCR ECR RSR_SUP RSR_INT0 RSR_INT1 RSR_INT2 RSR_INT3 RSR_EX RSR_NMI RSR_DBG RAR_SUP RAR_INT0 RAR_INT1 RAR_INT2 RAR_INT3 RAR_EX RAR_NMI RAR_DBG JECR JOSP JAVA_LV0 Function Status Register Exception Vector Base Address Application Call Base Address CPU Control Register Exception Cause Register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Status Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Return Address Register for Debug mode Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC 25 32099DS–06/2010 AT32UC3L016/32/64 Table 4-3. Reg # 24 25 26 27 28 29 30 31 32 33-63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 System Registers (Continued) Address 96 100 104 108 112 116 120 124 128 132-252 256 260 264 268 272 276 280 284 288 292 296 300 304 308 312 316 320 324 328 332 336 340 344 348 352 356 Name JAVA_LV1 JAVA_LV2 JAVA_LV3 JAVA_LV4 JAVA_LV5 JAVA_LV6 JAVA_LV7 JTBA JBCR Reserved CONFIG0 CONFIG1 COUNT COMPARE TLBEHI TLBELO PTBR TLBEAR MMUCR TLBARLO TLBARHI PCCNT PCNT0 PCNT1 PCCR BEAR MPUAR0 MPUAR1 MPUAR2 MPUAR3 MPUAR4 MPUAR5 MPUAR6 MPUAR7 MPUPSR0 MPUPSR1 Function Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Reserved for future use Configuration register 0 Configuration register 1 Cycle Counter register Compare register Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Unused in AVR32UC Bus Error Address Register MPU Address Register region 0 MPU Address Register region 1 MPU Address Register region 2 MPU Address Register region 3 MPU Address Register region 4 MPU Address Register region 5 MPU Address Register region 6 MPU Address Register region 7 MPU Privilege Select Register region 0 MPU Privilege Select Register region 1 26 32099DS–06/2010 AT32UC3L016/32/64 Table 4-3. Reg # 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112-191 192-255 System Registers (Continued) Address 360 364 368 372 376 380 384 388 392 396 400 404 408 412 416 420 424 428 432 436 440 444 448-764 768-1020 Name MPUPSR2 MPUPSR3 MPUPSR4 MPUPSR5 MPUPSR6 MPUPSR7 MPUCRA MPUCRB MPUBRA MPUBRB MPUAPRA MPUAPRB MPUCR SS_STATUS SS_ADRF SS_ADRR SS_ADR0 SS_ADR1 SS_SP_SYS SS_SP_APP SS_RAR SS_RSR Reserved IMPL Function MPU Privilege Select Register region 2 MPU Privilege Select Register region 3 MPU Privilege Select Register region 4 MPU Privilege Select Register region 5 MPU Privilege Select Register region 6 MPU Privilege Select Register region 7 Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC Unused in this version of AVR32UC MPU Access Permission Register A MPU Access Permission Register B MPU Control Register Secure State Status Register Secure State Address Flash Register Secure State Address RAM Register Secure State Address 0 Register Secure State Address 1 Register Secure State Stack Pointer System Register Secure State Stack Pointer Application Register Secure State Return Address Register Secure State Return Status Register Reserved for future use IMPLEMENTATION DEFINED 4.5 Exceptions and Interrupts In the AVR32 architecture, events are used as a common term for exceptions and interrupts. AVR32UC incorporates a powerful event handling scheme. The different event sources, like Illegal Op-code and interrupt requests, have different priority levels, ensuring a well-defined behavior when multiple events are received simultaneously. Additionally, pending events of a higher priority class may preempt handling of ongoing events of a lower priority class. When an event occurs, the execution of the instruction stream is halted, and execution is passed to an event handler at an address specified in Table 4-4 on page 31. Most of the handlers are placed sequentially in the code space starting at the address specified by EVBA, with four bytes between each handler. This gives ample space for a jump instruction to be placed there, jumping to the event routine itself. A few critical handlers have larger spacing between them, allowing the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address 27 32099DS–06/2010 AT32UC3L016/32/64 relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme. An interrupt controller does the priority handling of the interrupts and provides the autovector offset to the CPU. 4.5.1 System Stack Issues Event handling in AVR32UC uses the system stack pointed to by the system stack pointer, SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section, since the timing of accesses to this memory section is both fast and deterministic. The user must also make sure that the system stack is large enough so that any event is able to push the required registers to stack. If the system stack is full, and an event occurs, the system will enter an UNDEFINED state. 4.5.2 Exceptions and Interrupt Requests When an event other than scall or debug request is received by the core, the following actions are performed atomically: 1. The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and GM bits in the Status Register are used to mask different events. Not all events can be masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and Bus Error) can not be masked. When an event is accepted, hardware automatically sets the mask bits corresponding to all sources with equal or lower priority. This inhibits acceptance of other events of the same or lower priority, except for the critical events listed above. Software may choose to clear some or all of these bits after saving the necessary state if other priority schemes are desired. It is the event source’s responsability to ensure that their events are left pending until accepted by the CPU. 2. When a request is accepted, the Status Register and Program Counter of the current context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also automatically stored to stack. Storing the Status Register ensures that the core is returned to the previous execution mode when the current event handling is completed. When exceptions occur, both the EM and GM bits are set, and the application may manually enable nested exceptions if desired by clearing the appropriate bit. Each exception handler has a dedicated handler address, and this address uniquely identifies the exception source. 3. The Mode bits are set to reflect the priority of the accepted event, and the correct register file bank is selected. The address of the event handler, as shown in Table 4-4 on page 31, is loaded into the Program Counter. The execution of the event handler routine then continues from the effective address calculated. The rete instruction signals the end of the event. When encountered, the Return Status Register and Return Address Register are popped from the system stack and restored to the Status Register and Program Counter. If the rete i nstruction returns from INT0, INT1, INT2, or INT3, registers R8-R12 and LR are also popped from the system stack. The restored Status Register contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 28 32099DS–06/2010 AT32UC3L016/32/64 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers. The scall instruction behaves differently depending on which mode it is called from. The behaviour is detailed in the instruction set reference. In order to allow the scall routine to return to the correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC CPU, scall and rets uses the system stack to store the return address and the status register. 4.5.4 Debug Requests The AVR32 architecture defines a dedicated Debug mode. When a debug request is received by the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the status register. Upon entry into Debug mode, hardware sets the SR.D bit and jumps to the Debug Exception handler. By default, Debug mode executes in the exception context, but with dedicated Return Address Register and Return Status Register. These dedicated registers remove the need for storing this data to the system stack, thereby improving debuggability. The Mode bits in the Status Register can freely be manipulated in Debug mode, to observe registers in all contexts, while retaining full privileges. Debug mode is exited by executing the retd instruction. This returns to the previous context. 4.5.5 Entry Points for Events Several different event handler entry points exist. In AVR32UC, the reset address is 0x80000000. This places the reset address in the boot flash memory area. TLB miss exceptions and scall have a dedicated space relative to EVBA where their event handler can be placed. This speeds up execution by removing the need for a jump instruction placed at the program address jumped to by the event hardware. All other exceptions have a dedicated event routine entry point located relative to EVBA. The handler routine address identifies the exception source directly. AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation. ITLB and DTLB miss exceptions are used to signal that an access address did not map to any of the entries in the MPU. TLB multiple hit exception indicates that an access address did map to multiple TLB entries, signalling an error. All interrupt requests have entry points located at an offset relative to EVBA. This autovector offset is specified by an interrupt controller. The programmer must make sure that none of the autovector offsets interfere with the placement of other code. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. Special considerations should be made when loading EVBA with a pointer. Due to security considerations, the event handlers should be located in non-writeable flash memory, or optionally in a privileged memory protection region if an MPU is present. If several events occur on the same instruction, they are handled in a prioritized way. The priority ordering is presented in Table 4-4 on page 31. If events occur on several instructions at different locations in the pipeline, the events on the oldest instruction are always handled before any events on any younger instruction, even if the younger instruction has events of higher priority 29 32099DS–06/2010 AT32UC3L016/32/64 than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 31. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit. 30 32099DS–06/2010 AT32UC3L016/32/64 Table 4-4. Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Priority and Handler Addresses for Events Handler Address 0x80000000 Provided by OCD system EVBA+0x00 EVBA+0x04 EVBA+0x08 EVBA+0x0C EVBA+0x10 Autovectored Autovectored Autovectored Autovectored EVBA+0x14 EVBA+0x50 EVBA+0x18 EVBA+0x1C EVBA+0x20 EVBA+0x24 EVBA+0x28 EVBA+0x2C EVBA+0x30 EVBA+0x100 EVBA+0x34 EVBA+0x38 EVBA+0x60 EVBA+0x70 EVBA+0x3C EVBA+0x40 EVBA+0x44 Name Reset OCD Stop CPU Unrecoverable exception TLB multiple hit Bus error data fetch Bus error instruction fetch NMI Interrupt 3 request Interrupt 2 request Interrupt 1 request Interrupt 0 request Instruction Address ITLB Miss ITLB Protection Breakpoint Illegal Opcode Unimplemented instruction Privilege violation Floating-point Coprocessor absent Supervisor call Data Address (Read) Data Address (Write) DTLB Miss (Read) DTLB Miss (Write) DTLB Protection (Read) DTLB Protection (Write) DTLB Modified Event source External input OCD system Internal MPU Data bus Data bus External input External input External input External input External input CPU MPU MPU OCD system Instruction Instruction Instruction UNUSED Instruction Instruction CPU CPU MPU MPU MPU MPU UNUSED PC of offending instruction PC(Supervisor Call) +2 PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction PC of offending instruction Stored Return Address Undefined First non-completed instruction PC of offending instruction PC of offending instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction First non-completed instruction PC of offending instruction PC of offending instruction PC of offending instruction 31 32099DS–06/2010 AT32UC3L016/32/64 5. Memories 5.1 Embedded Memories • Internal High-Speed Flash – 64Kbytes (AT32UC3L064) – 32Kbytes (AT32UC3L032) – 16Kbytes (AT32UC3L016) • 0 Wait State Access at up to 25MHz in Worst Case Conditions • 1 Wait State Access at up to 50MHz in Worst Case Conditions • Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access • Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation to only 8% compared to 0 wait state operation • 100 000 Write Cycles, 15-year Data Retention Capability • Sector Lock Capabilities, Bootloader Protection, Security Bit • 32 Fuses, Erased During Chip Erase • User Page For Data To Be Preserved During Chip Erase • Internal High-Speed SRAM, Single-cycle access at full speed – 16Kbytes (AT32UC3L064, AT32UC3L032) – 8Kbytes (AT32UC3L016) 5.2 Physical Memory Map The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows: Table 5-1. Device AT32UC3L Physical Memory Map Start Address 0x00000000 0x80000000 0xFFFE0000 0xFFFF0000 Size AT32UC3L064 AT32UC3L032 AT32UC3L016 Embedded SRAM Embedded Flash HSB-PB Bridge B HSB-PB Bridge A 16Kbytes 64Kbytes 64Kbytes 64Kbytes 16Kbytes 32Kbytes 64Kbytes 64Kbytes 8Kbytes 16Kbytes 64Kbytes 64Kbytes Table 5-2. Flash Memory Parameters Part Number AT32UC3L064 AT32UC3L032 AT32UC3L016 Flash Size (FLASH_PW) 64Kbytes 32Kbytes 16Kbytes Number of pages (FLASH_P) 256 128 64 Page size (FLASH_W) 256 bytes 256 bytes 256 bytes 32 32099DS–06/2010 AT32UC3L016/32/64 5.3 Peripheral Address Map Peripheral Address Mapping Address 0xFFFE0000 Table 5-3. Peripheral Name FLASHCDW Flash Controller - FLASHCDW Bus 0xFFFE0400 HMATRIX 0xFFFE0800 HSB Matrix - HMATRIX SAU 0xFFFF0000 Secure Access Unit - SAU PDCA 0xFFFF1000 Peripheral DMA Controller - PDCA INTC 0xFFFF1400 Interrupt controller - INTC PM 0xFFFF1800 Power Manager - PM SCIF 0xFFFF1C00 System Control Interface - SCIF AST 0xFFFF2000 Asynchronous Timer - AST WDT 0xFFFF2400 Watchdog Timer - WDT EIC 0xFFFF2800 External Interrupt Controller - EIC FREQM 0xFFFF2C00 Frequency Meter - FREQM GPIO 0xFFFF3000 General Purpose Input/Output Controller - GPIO Universal Synchronous/Asynchronous Receiver/Transmitter - USART0 Universal Synchronous/Asynchronous Receiver/Transmitter - USART1 Universal Synchronous/Asynchronous Receiver/Transmitter - USART2 Universal Synchronous/Asynchronous Receiver/Transmitter - USART3 Serial Peripheral Interface - SPI USART0 0xFFFF3400 USART1 0xFFFF3800 USART2 0xFFFF3C00 USART3 0xFFFF4000 SPI 0xFFFF4400 TWIM0 Two-wire Master Interface - TWIM0 33 32099DS–06/2010 AT32UC3L016/32/64 Table 5-3. Peripheral Address Mapping 0xFFFF4800 TWIM1 0xFFFF4C00 Two-wire Master Interface - TWIM1 TWIS0 0xFFFF5000 Two-wire Slave Interface - TWIS0 TWIS1 0xFFFF5400 Two-wire Slave Interface - TWIS1 PWMA 0xFFFF5800 Pulse Width Modulation Controller - PWMA TC0 0xFFFF5C00 Timer/Counter - TC0 TC1 0xFFFF6000 Timer/Counter - TC1 ADCIFB 0xFFFF6400 ADC Interface - ADCIFB ACIFB 0xFFFF6800 Analog Comparator Interface - ACIFB CAT 0xFFFF6C00 Capacitive Touch Module - CAT GLOC 0xFFFF7000 Glue Logic Controller - GLOC AW aWire - AW 5.4 CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers. 34 32099DS–06/2010 AT32UC3L016/32/64 The following GPIO registers are mapped on the local bus: Table 5-4. Port 0 Local Bus Mapped GPIO Registers Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x40000040 0x40000044 0x40000048 0x4000004C 0x40000050 0x40000054 0x40000058 0x4000005C 0x40000060 0x40000240 0x40000244 0x40000248 0x4000024C 0x40000250 0x40000254 0x40000258 0x4000025C 0x40000260 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Register Output Driver Enable Register (ODER) Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) 1 Output Driver Enable Register (ODER) WRITE SET CLEAR TOGGLE Output Value Register (OVR) WRITE SET CLEAR TOGGLE Pin Value Register (PVR) - 35 32099DS–06/2010 AT32UC3L016/32/64 6. Supply and Startup Considerations 6.1 6.1.1 Supply Considerations Power Supplies The AT32UC3L has several types of power supply pins: •VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. •VDDIN: Powers I/O lines and the internal regulator. Voltage is 1.8 to 3.3V nominal. •VDDANA: Powers the ADC. Voltage is 1.8V nominal. •VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. The ground pins GND are common to VDDCORE and VDDIO. The ground pin for VDDANA is GNDANA. Refer to Section 7. on page 41 for power consumption on the various supply pins. 6.1.2 Voltage Regulator The AT32UC3L embeds a voltage regulator that converts from 3.3V nominal to 1.8V with a load of up to 60 mA. The regulator supplies the output voltage on VDDCORE. The regulator may only be used to drive internal circuitry in the device. VDDCORE should be externally connected to the 1.8V domains. See Section 6.1.3 for regulator connection figures. Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallell between VDDCORE and GND as close to the chip as possible. Please refer to Section 7.9.1 on page 50 for decoupling capacitors values and regulator characteristics. Figure 6-1. Supply Decoupling 3.3V C IN3 CIN2 CIN1 VDDIN 1.8V Regulator VDDCORE 1.8V COUT2 COUT1 6.1.3 Regulator Connection The AT32UC3L supports three power supply configurations: • 3.3V single supply mode • 1.8V single supply mode • 3.3V supply mode, with 1.8V regulated I/O lines 36 32099DS–06/2010 AT32UC3L016/32/64 6.1.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). Figure 6-2. 3.3V Single Power Supply mode + 1.98-3.6V - VDDIN VDDIO GND I/O Pins Linear VDDCORE I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL VDDANA ADC GNDANA 37 32099DS–06/2010 AT32UC3L016/32/64 6.1.3.2 1.8V Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8V supply as shown in Figure 6-3. All I/O lines will be powered by the same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.8V Single Power Supply Mode. + 1.62-1.98V - VDDIN VDDIO GND I/O Pins Linear VDDCORE I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL VDDANA ADC GNDANA 38 32099DS–06/2010 AT32UC3L016/32/64 6.1.3.3 3.3V Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to use Shutdown mode. Figure 6-4. 3.3V Power with 1.8V Regulated I/O Lines 1.98-3.6V + - VDDIN VDDIO GND I/O Pins Linear VDDCORE I/O Pins OSC32K RC32K AST Wake POR33 SM33 CPU, Peripherals, Memories, SCIF, BOD, RCSYS, DFLL VDDANA ADC GNDANA In this mode, some I/O lines are powered by VDDIN while others I/O lines are powered by VDDIO. Refer to Section 3.2 on page 9 for description of power supply for each I/O line. Refer to the Power Manager chapter for a description of what parts of the system are powered in Shutdown mode. Important note: As the regulator has a maximum output current of 60mA, this mode can only be used in applications where the maximum I/O current is known and compatible with the core and peripheral power consumption. Typically, great care must be used to ensure that only a few I/O lines are toggling at the same time and drive very small loads. 39 32099DS–06/2010 AT32UC3L016/32/64 6.1.4 6.1.4.1 Power-up Sequence Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 7-3 on page 42. Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise Rate The integrated Power-Reset circuitry monitoring the VDDIN powering supply requires a minimum rise rate for the VDDIN power supply. See Table 7-3 on page 42 for the minimum rise rate value. If the application can not ensure that the minimum rise rate condition for the VDDIN power supply is met, one of the following configuration can be used: • A logic “0” value is applied during power-up on pin PA11 until VDDIN rises above 1.2V. • A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V. 6.2 Startup Considerations This chapter summarizes the boot sequence of the AT32UC3L. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 6.2.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry for a short time to allow the power to stabilize throughout the device. After reset, the device will use the System RC Oscillator (RCSYS) as clock source. Please refer to Table 7-17 on page 49 for the frequency for this oscillator. On system start-up, the DFLL is disabled. All clocks to all modules are running. No clocks have a divided frequency; all parts of the system receive a clock with the same frequency as the System RC Oscillator. When powering up the device, there may be a delay before the voltage has stabilized, depending on the rise time of the supply used. The CPU can start executing code as soon as the supply is above the POR threshold, and before the supply is stable. Before switching to a high-speed clock source, the user should use the BOD to make sure the VDDCORE is above the minimum level (1.62V). 6.2.2 Fetching of Initial Instructions After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x80000000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the DFLL, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals. 40 32099DS–06/2010 AT32UC3L016/32/64 7. Electrical Characteristics 7.1 Disclaimer All values in this chapter are preliminary and subject to change without further notice. 7.2 Absolute Maximum Ratings* Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 7-1. Operating temperature..................................... -40°C to +85°C Storage temperature...................................... -60°C to +150°C Voltage on input pins (except for 5V pins) with respect to ground .................................................................-0.3V to VVDD(2)+0.3V Voltage on 5V tolerant(1) pins with respect to ground ............... .............................................................................-0.3V to 5.5V Total DC output current on all I/O pins - VDDIO ........... 120mA Total DC output current on all I/O pins - VDDIN ............. 36mA Maximum operating voltage VDDCORE......................... 1.98V Maximum operating voltage VDDIO, VDDIN .................... 3.6V Notes: 1. 5V tolerant pins, see Section 3.2 ”Peripheral Multiplexing on I/O lines” on page 9 2. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details. 7.3 Supply Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C. Table 7-2. Supply Characteristics(1) Voltage Symbol VVDDIO Parameter DC supply peripheral I/Os DC supply peripheral I/Os, 1.8V single supply mode VVDDIN DC supply peripheral I/Os and internal regulator, 3.3V single supply mode DC supply core Analog supply voltage Analog reference voltage Min 1.62 1.62 Max 3.6 1.98 Unit V V 1.98 1.62 1.62 1.62 3.6 1.98 1.98 VVDDANA V V V V VVDDCORE VVDDANA VADVREFP Note: 1. VDDANA = VDDCORE 41 32099DS–06/2010 AT32UC3L016/32/64 Table 7-3. Supply Rise Rates and Order Rise Rate Symbol VVDDIO VVDDIN VVDDCORE VVDDANA Note: Parameter DC supply peripheral I/Os DC supply peripheral I/Os and internal regulator DC supply core Analog supply voltage Min 0 0.002(1) 0 0 Max 2.5 2.5 2.5 2.5 Unit V/µs V/µs V/µs V/µs Rise before or at the same time as VDDIO Rise together with VDDCORE Comment 1. Slower rise time requires external power-on reset circuit. 7.4 Maximum Clock Frequencies These parameters are given in the following conditions: • VVDDCORE = 1.62 to 1.98V • Temperature = -40°C to 85°C Table 7-4. Symbol fCPU fPBA fPBB fGCLK0 fGCLK1 fGCLK2 fGCLK3 fGCLK4 fGCLK5 Clock Frequencies Parameter CPU clock frequency PBA clock frequency PBB clock frequency GCLK0 clock frequency GCLK1 clock frequency GCLK2 clock frequency GCLK3 clock frequency GCLK4 clock frequency GCLK5 clock frequency Conditions Min Max 50 50 50 150 150 80 110 110 80 Units MHz MHz MHz MHz MHz MHz MHz MHz MHz 7.5 Power Consumption The values in Table 7-5 are measured values of power consumption under the following conditions, except where noted: • Operating conditions internal core supply (Figure 7-1) - this is the default configuration – VVDDIN = 3.0V – VVDDCORE = 1.62V – TA = 25°C • Operating conditions external core supply (Figure 7-2) - used only when noted – VVDDIN = VVDDCORE = 1.8V – TA = 25°C • Oscillators 42 32099DS–06/2010 AT32UC3L016/32/64 – OSC0 (crystal oscillator) stopped – OSC32K (32KHz crystal oscillator) running with external 32KHz crystal – DFLL running at 50MHz with OSC32K as reference • Clocks – DFLL used as main clock source – CPU, HSB, and PBB clocks undivided – PBA clock divided by 4 – The following peripheral clocks running • PM, SCIF, AST, FLASHCDW, PBA bridge – All other peripheral clocks stopped • I/Os are inactive with internal pull-up • Flash enabled in high speed mode • POR33 disabled Table 7-5. Mode Active -CPU running a division algorithm Idle Frozen Standby Stop DeepStop -OSC32K and AST stopped -Internal core supply Static -OSC32K running -AST running at 1KHz -External core supply (Figure 7-2) -OSC32K and AST stopped -External core supply (Figure 7-2) -OSC32K running -AST running at 1KHz -AST and OSC32K stopped Amp0 165 92 58 47 37 23 10 µA 5.3 µA/MHz Power Consumption for Different Modes Conditions -CPU running a recursive Fibonacci algorithm Measured on Consumption Typ 260 Unit 4.7 600 nA 9 Shutdown 43 32099DS–06/2010 AT32UC3L016/32/64 Figure 7-1. Measurement Schematic, Internal Core Supply Amp0 VDDIN VDDIO VDDCORE VDDANA Figure 7-2. Measurement Schematic, External Core Supply Amp0 VDDIN VDDIO VDDCORE VDDANA 7.6 I/O Pad Characteristics Normal I/O Pad Characteristics(1) Parameter Pull-up resistance Input low-level voltage VVDD = 3.0V VVDD = 1.62V Input high-level voltage VVDD = 3.6V VVDD = 1.98V Condition Min 75 -0.3 -0.3 0.7*VVDD 0.7*VVDD Typ 100 Max 145 0.3*VVDD 0.3*VVDD VVDD + 0.3 VVDD + 0.3 V Units kOhm V Table 7-6. Symbol RPULLUP VIL VIH 44 32099DS–06/2010 AT32UC3L016/32/64 Table 7-6. Symbol VOL Normal I/O Pad Characteristics(1) Parameter Output low-level voltage Condition VVDD = 3.0V, IOL = 3 mA VVDD = 1.62 V, IOL = 2 mA Output high-level voltage Input leakage current VVDD = 3.0V, IOH = 3 mA VVDD = 1.62 V, IOH = 2 mA Pull-up resistors disabled VVDD - 0.4 VVDD - 0.4 1 µA Min Typ Max 0.4 V 0.4 V Units VOH ILEAK Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details. Table 7-7. Symbol High-drive I/O Pad Characteristics(1) Parameter Condition PA06 Min 30 75 10 -0.3 -0.3 0.7*VVDD 0.7*VVDD Typ 50 100 20 Max 110 145 45 0.3*VVDD 0.3*VVDD VVDD + 0.3 VVDD + 0.3 0.4 V 0.4 VVDD-0.4 VVDD-0.4 1 µA V V V kOhm Units RPULLUP Pull-up resistance PA02, PB01, RESET PA08, PA09 VIL Input low-level voltage VVDD = 3.0V VVDD = 1.62V VIH Input high-level voltage VVDD = 3.6V VVDD = 1.98V VOL Output low-level voltage VVDD = 3.0V, IOL = 6 mA VVDD = 1.62 V, IOL = 4 mA VOH ILEAK Notes: Output high-level voltage Input leakage current VVDD = 3.0V, IOH = 6 mA VVDD = 1.62 V, IOH = 4 mA Pull-up resistors disabled 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details. Table 7-8. Symbol RPULLUP VIL 5V Tolerant Normal I/O Pad Characteristics(1) Parameter Pull-up resistance Input low-level voltage VVDD = 3.0V VVDD = 1.62V Input high-level voltage VVDD = 3.6V VVDD = 1.98V Output low-level voltage VVDD = 3.0V, IOL = 3 mA VVDD = 1.62 V, IOL = 2mA Output high-level voltage Input leakage current VVDD = 3.0V, IOH = 3 mA VVDD = 1.62 V, IOH = 2 mA 5.5V, pull-up resistors disabled VVDD-0.4 VVDD-0.4 1 µA Condition Min 75 -0.3 -0.3 0.7*VVDD 0.7*VVDD Typ 100 Max 145 0.3*VVDD 0.3*VVDD 5.5 V 5.5 0.4 V 0.4 V Units kOhm V VIH VOL VOH ILEAK Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details. 45 32099DS–06/2010 AT32UC3L016/32/64 5V Tolerant High-drive I/O Pad Characteristics(1) Parameter Pull-up resistance Input low-level voltage VVDD = 3.0V VVDD = 1.62V Input high-level voltage VVDD = 3.6V VVDD = 1.98V Output low-level voltage VVDD = 3.0V, IOL = 6 mA VVDD = 1.62 V, IOL = 4 mA Output high-level voltage Input leakage current VVDD = 3.0V, IOH = 6 mA VVDD = 1.62 V, IOH = 4 mA 5.5V, pull-up resistors disabled VVDD-0.4 VVDD-0.4 1 µA Condition Min 30 -0.3 -0.3 0.7*VVDD 0.7*VVDD Typ 50 Max 110 0.3*VVDD 0.3*VVDD 5.5 V 5.5 0.4 V 0.4 V Units kOhm V Table 7-9. Symbol RPULLUP VIL VIH VOL VOH ILEAK Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details. Table 7-10. Symbol RPULLUP VIL TWI Pad Characteristics(1) Parameter Pull-up resistance Input low-level voltage VVDD = 3.0V VVDD = 1.62V Input high-level voltage Output low-level voltage Input leakage current Input low leakage Input high leakage Max frequency Cbus = 400pF, VVDD > 2.0V 400 VVDD = 3.6V VVDD = 1.98V IOL = 3 mA Pull-up resistors disabled Condition Min 25 -0.3 -0.3 0.7*VVDD 0.7*VVDD Typ 35 Max 50 0.3*VVDD 0.3*VVDD VVDD + 0.3 VVDD + 0.3 0.4 1 1 1 V µA µA µA kHz V Units kOhm V VIH VOL ILEAK IIL IIH fMAX Notes: 1. VVDD corresponds to either VVDDIN or VVDDIO, depending on the supply for the pad. Refer to Section 3.2 on page 9 for details. 7.7 7.7.1 7.7.1.1 Oscillator Characteristics Oscillator 0 (OSC0) Characteristics Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Digital Clock Characteristics Parameter XIN clock frequency XIN clock duty cycle 40 Conditions Min Typ Max 50 60 Units MHz % Table 7-11. Symbol fCPXIN tCPXIN 46 32099DS–06/2010 AT32UC3L016/32/64 7.7.1.2 Crystal Oscillator Characteristics The following table describes the characteristics for the oscillator when a crystal is connected between XIN and XOUT as shown in Figure 7-3. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed as follows: C LEXT = 2 ( C L – C i ) – C PCB where CPCB is the capacitance of the PCB. Table 7-12. Symbol 1/(tCPMAIN) CL Ci tSTARTUP Notes: Crystal Oscillator Characteristics Parameter Crystal oscillator frequency Crystal load capacitance Internal equivalent load capacitance Startup time SCIF.OSCCTRL.GAIN = 2(1) Conditions Min 3 6 2 30 000(2) Typ Max 16 18 Unit MHz pF pF cycles 1. Please refer to the SCIF chapter for details. 2. Nominal crystal cycles. Figure 7-3. Oscillator Connection CLEXT XOUT UC3L Ci CL XIN CLEXT 7.7.2 32KHz Crystal Oscillator (OSC32K) Characteristics Figure 7-3 and the equation above also applies to the 32 KHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can then be found in the crystal datasheet. 32 KHz Crystal Oscillator Characteristics Parameter Crystal oscillator frequency Startup time Crystal load capacitance RS = 60kOhm, CL = 9 pF 6 Conditions Min Typ 32 768 30 000 (1) Table 7-13. Symbol 1/(tCP32KHz) tST CL Max Unit Hz cycles 12.5 pF 47 32099DS–06/2010 AT32UC3L016/32/64 Table 7-13. Symbol Ci IOSC RS Note: 32 KHz Crystal Oscillator Characteristics Parameter Internal equicalent load capacitance Current consumption Equivalent series resistance 32 768Hz 35 Conditions Min Typ 2 0.9 85 Max Unit pF µA kOhm 1. Nominal crystal cycles. 7.7.3 Digital Frequency Locked Loop (DFLL) Characteristics Digital Frequency Locked Loop Characteristics Parameter Output frequency Reference frequency FINE resolution FINE>100, all COARSE values Fine lock, fREF=32kHz, SSG disabled Accurate lock, fREF=32kHz, dither clk RCSYS/2, SG disabled Accuracy Fine lock, fREF=8-150kHz, SSG disabled Accurate lock, fREF=8-150kHz, dither clk RCSYS/2, SSG disabled Power consumption 0.2 0.1 22 Within 90% of final values fREF = 32kHz, fine lock, SSG disabled 600 µs 1100 100 1 1 µA/MHz µs Conditions Min 40 8 0.25 0.1 0.06 0.5 0.5 % Typ Max 150 150 Unit MHz kHz % Table 7-14. Symbol fOUT fREF tSTARTUP tLOCK Startup time Lock time fREF = 32kHz, accurate lock, dithering clock = RCSYS/2, SSG disabled Note: 1. Spread Spectrum Generator (SSG) is disabled by writing a zero to the EN bit in the SCIF.DFLL0SSG register. 48 32099DS–06/2010 AT32UC3L016/32/64 7.7.4 120MHz RC Oscillator (RC120M) Characteristics Internal 120MHz RC Oscillator Characteristics Parameter Output frequency Temperature drift Duty Duty cycle 40 Conditions T = 25°C, VVDDCORE = 1.8V Min 88 Typ 120 +/-5 50 60 Max 152 Unit MHz % % Table 7-15. Symbol fOUT 7.7.5 32kHz RC Oscillator (RC32K) Characteristics 32kHz RC Oscillator Characteristics Parameter Output frequency Conditions T = 25°C, VVDDIO = 3.3V Min 20 Typ 32 Max 44 Unit kHz Table 7-16. Symbol fOUT 7.7.6 System RC Oscillator (RCSYS) Characteristics System RC Oscillator Characteristics Parameter Output frequency Conditions Calibrated at 85°C Min Typ 115 Max Unit kHz Table 7-17. Symbol fOUT 7.8 Flash Characteristics Table 7-18 gives the device maximum operating frequency depending on the number of flash wait states and the flash read mode. The FSW bit in the FLASHCDW FSR register controls the number of wait states used when accessing the flash memory. Table 7-18. Maximum Operating Frequency Read Mode High speed read mode 0 1 Normal read mode 0 15MHz 25MHz 30MHz Maximum Operating Frequency 50MHz Flash Wait States 1 Table 7-19. Symbol TFPP TFPE TFFP TFEA TFCE Flash Characteristics Parameter Page programming time Page erase time Fuse programming time Full chip erase time (EA) JTAG chip erase time (CHIP_ERASE) fCLK_HSB= 115kHz fCLK_HSB= 50MHz Conditions Min Typ 5 5 1 5 300 ms Max Unit 49 32099DS–06/2010 AT32UC3L016/32/64 Table 7-20. Symbol NFARRAY NFFUSE tRET Flash Endurance and Data Retention Parameter Array endurance (write/page) General Purpose fuses endurance (write/bit) Data retention Conditions Min 100k 10k 15 Typ Max Unit cycles cycles years 7.9 7.9.1 7.9.1.1 Analog Characteristics Voltage Regulator Characteristics Electrical Characteristics Table 7-21. Symbol VVDDIN VVDDCORE Electrical Characteristics Parameter Input voltage range Output voltage VVDDIN > 1.98V IOUT = 0.1mA to 60mA, VVDDIN>2.2V IOUT = 0.1mA to 60mA, VVDDIN=1.98V to 2.2V Normal mode Condition Min 1.98 Typ 3.3 1.8 2 % 4 60 1 20 6 mA mA µA µA Max 3.6 Units V V Output voltage accuracy IOUT DC output current Low power mode Normal mode Static current of internal regulator Low power mode ISCR 7.9.1.2 Table 7-22. Symbol CIN1 CIN2 CIN3 COUT1 COUT2 Note: Decoupling Requirements Decoupling Requirements Parameter Input regulator capacitor 1 Input regulator capacitor 2 Input regulator capacitor 3 Output regulator capacitor 1 Output regulator capacitor 2 1. Refer to Section 6.1.2 on page 36. Condition Typ 33 100 10 100 2.2 Tantalum 0.5