AT34C02CU3-UU-T

Features • Permanent and Reversible Software Write Protection for the First-half of the Array – Software Procedure to Verify Write Protect Status • Hardware Write Protection for the Entire Array • Low-voltage and Standard-voltage Operation • • • • • • • • • – 1.7 (VCC = 1.7V to 5.5V) Internally Organized 256 x 8 Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.7V) and 400 kHz (2.7V and 5.0V) Compatibility 16-byte Page Write Modes Partial Page Writes Are Allowed Self-timed Write Cycle (5 ms max) High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball dBGA2 Packages Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers • • Two-wire Serial EEPROM with Permanent and Reversible Software Write Protect 2K (256 x 8) Description The AT34C02C provides 2048 bits of serial electrically-erasable and programmable read only memory (EEPROM) organized as 256 words of 8 bits each. The first-half of the device incorporates a permanent and a reversible software write protection feature while hardware write protection for the entire array is available via an external pin. Once the permanent software write protection is enabled, by sending a special command to the device, it cannot be reversed. However, the reversible software write protection is enabled and can be reversed by sending a special command. The hardware write protection is controlled with the WP pin and can be used to protect the entire array, whether or not the software write protection has been enabled. This allows the user to protect none, first-half, or all of the array depending on the application. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT34C02C is available in space saving 8-lead JEDEC SOIC, 8-lead Ultra Thin Mini-MAP (MLP 2x3), 8-lead TSSOP, and 8-ball dBGA2 packages and is accessed via a Two-wire serial interface. It is available in 1.7V (1.7V to 5.5V). 8-lead Ultra Thin Mini-MAP VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND AT34C02C 8-ball dBGA2 8-lead TSSOP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA VCC WP SCL SDA 8 7 6 5 1 2 3 4 A0 A1 A2 GND (MLP 2x3) Bottom View 8-lead SOIC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Bottom View Rev. 5185D–SEEPR–1/08 Table 0-1. Pin Name A0 - A2 SDA SCL WP Pin Configurations Function Address Inputs Serial Data Serial Clock Input Write Protect 1. Absolute Maximum Ratings* Operating Temperature..................................–55°C to +125 °C Storage Temperature .....................................–65°C to +150°C Voltage on Any Pin with Respect to Ground .................................... –1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Figure 1-1. Block Diagram VCC GND WP SCL SDA START STOP LOGIC SERIAL CONTROL LOGIC WRITE PROTECT CIRCUITRY LOAD DEVICE ADDRESS COMPARATOR A2 A1 A0 COMP LOAD INC X DEC DATA RECOVERY SOFTWARE WRITE PROTECTED AREA (00H - 7FH) EN H.V. PUMP/TIMING R/W DATA WORD ADDR/COUNTER EEPROM Y DEC SERIAL MUX DIN DOUT/ACK LOGIC DOUT 2 AT34C02C 5185D–SEEPR–1/08 AT34C02C 2. Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hardwired (directly to GND or to Vcc) for compatibility with other AT24Cxx devices. When the pins are hardwired, as many as eight 2K devices may be addressed on a single bus system. (Device addressing is discussed in detail under “Device Addressing,” page 9.) A device is selected when a corresponding hardware and software match is true. If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write operations. When WP is connected directly to Vcc, all write operations to the memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down to GND. However, due to capacitive coupling that may appear during customer applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor, Atmel recommends using 10kΩ or less. Table 2-1. AT34C02C Write Protection Modes Permanent Write Protect Register – Not Programmed Programmed – Reversible Write Protect Register – Not Programmed – Programmed Part of the Array Write Protected Full Array (2K) Normal Read/Write First-Half of Array (1K: 00H - 7FH) First-Half of Array (1K: 00H - 7FH) WP Pin Status VCC GND or Floating GND or Floating GND or Floating Table 2-2. Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 100 kHz, VCC = +1.7V Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V 3 5185D–SEEPR–1/08 Table 2-3. DC Characteristics Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.7V to +5.5V, (unless otherwise noted) Symbol VCC ICC ICC ISB1 ISB2 ISB3 ILI ILO VIL VIH VOL2 VOL1 Note: Parameter Supply Voltage Supply Current VCC = 5.0V Supply Current VCC = 5.0V Standby Current VCC = 1.7V Standby Current VCC = 3.6V Standby Current VCC = 5.5V Input Leakage Current Output Leakage Current Input Low Level (1) (1) Test Condition Min 1.7 Typ Max 5.5 Units V mA mA µA µA µA µA µA V V V V READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VIN = VCC or VSS VOUT = VCC or VSS 0.4 2.0 0.6 1.6 8.0 0.10 0.05 1.0 3.0 3.0 4.0 18.0 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 –0.6 VCC x 0.7 IOL = 2.1 mA IOL = 0.15 mA Input High Level Output Low Level VCC = 3.0V Output Low Level VCC = 1.7V 1. VIL min and VIH max are reference only and are not tested. Table 2-4. AC Characteristics Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.7V Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time (1) 2.7V, 5.0V Max 100 Min Max 400 1.2 0.6 100 50 0.1 1.2 0.6 0.6 0 100 1.0 300 0.3 300 0.6 0.9 Units kHz µs µs ns µs µs µs µs µs ns µs ns µs Min 4.7 4.0 Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time (1) 0.1 4.7 4.0 4.7 0 200 4.5 Inputs Fall Time(1) Stop Set-up Time 4.7 4 AT34C02C 5185D–SEEPR–1/08 AT34C02C Table 2-4. AC Characteristics Applicable over recommended operating range from TAI = –40°C to +85°C, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) 1.7V Symbol tDH tWR Endurance(1) Note: Parameter Data Out Hold Time Write Cycle Time 25°C, Page Mode 1M Min 100 5 1M Max 2.7V, 5.0V Min 50 5 Max Units ns ms Write Cycles 1. This parameter is characterized and is not 100% tested. 3. Memory Organization AT34C02C, 2K Serial EEPROM: The 2K is internally organized with 16 pages of 16 bytes each. Random word addressing requires a 8-bit data word address. 5 5185D–SEEPR–1/08 4. Device Operation CLOCK and DATA TRANSITIONS: T he SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 4-3 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 4-4 on page 7). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 4-4 on page 7). ACKNOWLEDGE: A ll addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. STANDBY MODE: The AT34C02C features a low-power standby mode which is enabled: (a) upon power-up or (b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any Two-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition. Figure 4-1. Bus Timing SCL: Serial Clock SDA: Serial Data I/O 6 AT34C02C 5185D–SEEPR–1/08 AT34C02C Figure 4-2. Write Cycle Timing SCL: Serial Clock SDA: Serial Data I/O SCL SDA 8th BIT WORDn ACK twr (1) STOP CONDITION START CONDITION Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. Figure 4-3. Data Validity Figure 4-4. Start and Stop Condition 7 5185D–SEEPR–1/08 Figure 4-5. Output Acknowledge 5. Device Addressing The 2K EEPROM device requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 8-1 on page 13). The device address word consists of a mandatory one-zero sequence for the first four most-significant bits (1010) for normal read and write operations and 0110 for writing to the write protect register. The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02C EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the chip will return to a standby state. The device will not acknowledge if the write protect register has been programmed and the control code is 0110. 6. Write Operations BYTE WRITE: A w rite operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8-2 on page 13). The device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. The write cycle time must be observed even when the write protection is enabled. PAGE WRITE: The 2K device is capable of 16-byte page write. 8 AT34C02C 5185D–SEEPR–1/08 AT34C02C A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 1 on page 13). The data word address lower four bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than sixteen data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. The device will acknowledge a write command, but not write the data, if the software or hardware write protection has been enabled. The write cycle time must be observed even when the write protection is enabled. ACKNOWLEDGE POLLING: O nce the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. 7. Write Protection The software write protection, once enabled, write protects only the first-half of the array (00H 7FH) while the hardware write protection, via the WP pin, is used to protect the entire array. PERMANENT SOFTWARE WRITE PROTECTION: The software write protection is enabled by sending a command, similar to a normal write command, to the device which programs the permanent write protect register. This must be done with the WP pin low. The write protect register is programmed by sending a write command with the device address of 0110 instead of 1010 with the address and data bit being don’t cares (see Figure 7-1 on page 10). Once the software write protection has been enabled, the device will no longer acknowledge the 0110 control byte. The software write protection cannot be reversed even if the device is powered down. The write cycle time must be observed. REVERSIBLE SOFTWARE WRITE PROTECTION: The reversible software write protection is enabled by sending a command, similar to a normal write command, to the device which programs the reversible write protect register. This must be done with the WP pin low. The write protect register is programmed by sending a write command 01100010 with pins A2 and A1 tied to ground or don't connect and pin A0 connected to VHV (see Figure 7-2). The reversible write protection can be reversed by sending a command 01100110 with pin A2 tied to ground or no connect, pin A1 tied to VCC and pin A0 tied to VHV (see Figure 7-3). HARDWARE WRITE PROTECTION: The WP pin can be connected to VCC, GND, or left floating. Connecting the WP pin to VCC will write protect the entire array, regardless of whether or not the software write protection has been enabled. The software write protection register cannot be programmed when the WP pin is connected to VCC. If the WP pin is connected to GND or left floating, the write protection mode is determined by the status of the software write protect register. 9 5185D–SEEPR–1/08 Figure 7-1. Setting Permanent Write Protect Register (PSWP) S T A R T SDA LINE CONTROL BYTE WORD ADDRESS DATA S T O P 0 1 1 0 A2 A1 A0 0 A C K A C K A C K = Don't Care Figure 7-2. Setting Reversible Write Protect Register (RSWP) S T A R T SDA LINE CONTROL BYTE WORD ADDRESS DATA S T O P 01100010 A C K A C K A C K = Don't Care Figure 7-3. Clearing Reversible Write Protect Register (RSWP) S T A R T SDA LINE CONTROL BYTE WORD ADDRESS DATA S T O P 01100110 A C K A C K A C K = Don't Care Table 7-1. Write Protection Pin Preamble A0 A0 VHV VHV B7 0 0 0 B6 1 1 1 B5 1 1 1 B4 0 0 0 B3 A2 0 0 B2 A1 0 1 B1 A0 1 1 RW B0 0 0 0 Command Set PSWP Set RSWP Clear RSWP A2 A2 0 0 A1 A1 0 1 Table 7-2. VHV Min Max 10 Units V VHV Note: VHV - VCC > 4.8V 7 10 AT34C02C 5185D–SEEPR–1/08 AT34C02C Table 7-3. WP Connected to GND or Floating Permanent Write Protect Register PSWP X Programmed X Not Programmed WP Connected to GND or Floating Command 1010 1010 1010 1010 R/W Bit R W W W Reversible Write Protect Register RSWP X X Programmed Not Programmed Acknowledgme nt from Device ACK ACK ACK ACK Action from Device Can write to second Half (80H - FFH) only Can write to second Half (80H - FFH) only Can write to full array Read PSWP Read PSWP Set PSWP Set PSWP R R W W Programmed Not Programmed Programmed Not Programmed X X X X No ACK ACK No ACK ACK STOP - Indicates permanent write protect register is programmed Read out data don't care. Indicates PSWP register is not programmed STOP - Indicates permanent write protect register is programmed Program permanent write protect register (irreversible) Read RSWP Read RSWP Set RSWP Set RSWP Clear RSWP Clear RSWP R R W W W W X X X X Programmed Not Programmed Programmed Not Programmed Programmed Not Programmed X X No ACK ACK No ACK ACK No ACK ACK STOP - Indicates reversible write protect register is programmed Read out data don't care. Indicates RSWP register is not programmed STOP - Indicates reversible write protect register is programmed Program reversible write protect register (reversible) STOP - Indicates permanent write protect register is programmed Clear (unprogram) reversible write protect register (reversible) Table 7-4. WP Connected to Vcc Comman d 1010 1010 WP Connected to Vcc R/W Bit R W Permanent Write Protect Register PSWP X X Reversible Write Protect Register RSWP X X Acknowledgme nt from Device ACK ACK Action from Device Read array Device Write Protect Read PSWP Read PSWP R R Programmed Not Programmed X X No ACK ACK STOP - Indicates permanent write protect register is programmed Read out data don't care. Indicates PSWP register is not programmed 11 5185D–SEEPR–1/08 WP Connected to Vcc Set PSWP Set PSWP W W Programmed Not Programmed X X No ACK ACK STOP - Indicates permanent write protect register is programmed Cannot program write protect registers Read RSWP Read RSWP Set RSWP Set RSWP Clear RSWP Clear RSWP R R W W W W X X X X Programmed Not Programmed Programmed Not Programmed Programmed Not Programmed X X No ACK ACK No ACK ACK No ACK ACK STOP - Indicates reversible write protect register is programmed Read out data don't care. Indicates RSWP register is not programmed STOP - Indicates reversible write protect register is programmed Cannot program write protect registers STOP - Indicates permanent write protect register is programmed Cannot write to write protect registers 8. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: T he internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. To end the command, the microcontroller does not respond with an input zero but does generate a following stop condition (see Figure 8-3 on page 14). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. To end the command, the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-4 on page 14). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (see Figure 8-5 on page 14). 12 AT34C02C 5185D–SEEPR–1/08 AT34C02C PERMANENT WRITE PROTECT REGISTER (PSWP) STATUS: To find out if the register has been programmed, the same procedure is used as to program the register except that the R/W bit is set to 1. If the device sends an acknowledge, then the permanent write protect register has not been programmed. Otherwise, it has been programmed and the device is permanently write protected at the first half of the array. Table 8-1. PSWP Status Pin Preamble A0 A0 B7 0 B6 1 B5 1 B4 0 B3 A2 B2 A1 B1 A0 RW B0 1 Command Read PSWP A2 A2 A1 A1 REVERSIBLE WRITE PROTECT REGISTER(RSWP) STATUS: To find out if the register has been programmed, the same procedure is used as to program the register except that the R/W bit is set to 1. If the sends an device acknowledge, then the reversible write protect register has not been programmed. Otherwise, it has been programmed and the device is write protected (reversible) at the first half of the array. Figure 8-1. Device Address Figure 8-2. Byte Write Figure 1. Page Write 13 5185D–SEEPR–1/08 Figure 8-3. Current Address Read Figure 8-4. Random Read Figure 8-5. Sequential Read 14 AT34C02C 5185D–SEEPR–1/08 AT34C02C AT34C02C Ordering Information Ordering Code AT34C02CN-SH-B AT34C02C-TH-B (1) Package (NiPdAu Lead Finish) 8S1 8S1 8A2 8A2 8Y6 8U3-1 (2) Operation Range AT34C02CN-SH-T (NiPdAu Lead Finish) (1) (NiPdAu Lead Finish) (2) AT34C02C-TH-T(2) (NiPdAu Lead Finish) AT34C02CY6-YH-T (NiPdAu Lead Finish) AT34C02CU3-UU-T Notes: (2) Lead-free/Halogen-free/ Industrial Temperature (–40°C to 85°C) 1. “-B” denotes bulk. 2. “-T” denotes tape and reel. SOIC = 4K per reel; TSSOP, Ultra Thin Mini MAP and dBGA2 = 5K per reel. Package Type 8S1 8A2 8Y6 8U3-1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead Package (DFN), (MLP 2x3 mm) 8-ball, die Ball Grid Array Package (dBGA2) Options –1.7 Low Voltage (1.7V to 5.5V) 15 5185D–SEEPR–1/08 9. New part marking 9.3 8-TSSOP TOP MARK Pin 1 Indicator (Dot) | |---|---|---|---| * H Y W W |---|---|---|---|---| 3 4 C 1* |---|---|---|---|---| BOTTOM MARK |---|---|---|---|---|---|---| C 0 0 |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| LINE 2-------> 34CU YMTC |