AT42QT1060-MMU

Features • Configurations: – Can be configured as a combination of keys and input/output lines • Number of Keys: – 2 to 6 • Number of I/O Lines: – 7, configurable for input or output, with PWM control for LED driving • Technology: – Patented spread-spectrum charge-transfer (direct mode) • Key Outline Sizes: – 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible Layers Required: – One Electrode Materials: – Etched copper – Silver – Carbon – Indium Tin Oxide (ITO) Panel Materials: – Plastic – Glass – Composites – Painted surfaces (low particle density metallic paints possible) Panel Thickness: – Up to 10 mm glass (electrode size dependent) – Up to 5 mm plastic (electrode size dependent) Key Sensitivity: – Individually settable via simple commands over serial interface Interface: – I2C-compatible slave mode (100 kHz). Discrete detection outputs Power: – 1.8V to 5.5V Package: – 28-pin 4 x 4 mm MLF RoHS compliant IC Signal Processing: – Self-calibration – auto drift compensation – noise filtering – Adjacent Key Suppression™ Applications: – Mobile appliances • • QTouch™ 6-channel Sensor IC AT42QT1060 • • • • • • • • 9505E–AT42–02/09 1. Pinout and Schematic 1.1 Pinout Configuration SNS0K 1 2 3 4 5 6 7 8 CHG SDA RST SCL SNS1K SNS2K VDD VSS IO5 IO6 SNS3K 28 27 26 25 24 23 22 21 20 19 IO4 SNS5K QT1060 15 9 10 11 12 13 14 IO3 SNS0 IO2 IO1 IO0 VSS VDD VDD SNS5 18 17 16 SNS4K SNS1 SNS3 SNS4 SNS2 1.2 Pin Descriptions Table 1-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Listing Name SNS1K SNS2K VDD VSS IO5 IO6 SNS3K SNS4K SNS5K SNS0 SNS1 SNS2 SNS3 SNS4 SNS5 VDD VDD Type IO IO P P IO IO IO IO IO IO IO IO IO IO IO P P Description To Cs capacitor and to key To Cs capacitor and to key Positive power pin Ground power pin IO Port Pin 5 IO Port Pin 6 To Cs capacitor and to key To Cs capacitor and to key To Cs capacitor and to key To Cs Capacitor To Cs Capacitor To Cs Capacitor To Cs Capacitor To Cs Capacitor To Cs Capacitor Positive power pin Positive power pin Leave open and set as output Leave open and set as output Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open If Unused, Connect To... Leave open Leave open 2 AT42QT1060 9505E–AT42–02/09 AT42QT1060 Table 1-1. Pin 18 19 20 21 22 23 24 25 26 27 28 Pin Listing (Continued) Name VSS IO0 IO1 IO2 CHG SDA SCL RST IO3 IO4 SNS0K I O OD Type P IO IO IO OD OD OD I IO IO IO Input only Output only, push-pull Open drain output Description Ground power pin IO Port Pin 0 IO Port Pin 1 IO Port Pin 2 Change line I2C-compatible Data line I2C-compatible Clock Line Reset, active low IO Port Pin 3 IO Port Pin 4 To Cs capacitor and to key IO P Leave open and set as output Leave open and set as output Leave open and set as output Leave open Resistor to Vdd or Vss only in standalone mode Resistor to Vdd or Vdd only in standalone mode Vdd Leave open and set as output Leave open and set as output Leave open Input and output Ground or power If Unused, Connect To... 3 9505E–AT42–02/09 1.3 Schematic Typical Circuit Vunreg Voltage Reg Figure 1-1. 100nF CB1 VDD Note: Bypass capacitor to be tightly wired between Vdd and Vss. Follow recommendations from regulator manufacturer for input and output capacitors. 16 3 17 VDD VDD VDD Rs5 25 SNS5K RST SNS5 SNS4K 9 15 8 14 7 13 2 12 1 11 28 10 KEY 5 Cs5 Rs4 KEY 4 Cs4 Rs3 6 5 27 IO6 IO5 IO4 IO3 IO2 IO1 IO0 SNS4 SNS3K SNS3 SNS2K SNS2 SNS1K SNS1 SNS0K SNS0 KEY 3 Cs3 Rs2 IO Port pins 26 21 20 19 KEY 2 Cs2 Rs1 KEY 1 Cs1 Rs0 KEY 0 Cs0 QT1060 VDD Rchg 100k Keep these parts close to the IC SDA 22 23 24 I C-compatible Data I C-compatible Clock in Standalone Mode 2 2 Change CHG SCL Note: The central pad on the underside of the chip is a Vss pin and should be connected to ground. VSS VSS SDA 23 18 4 VDD SCL 24 Note: In some systems it may be desirable to connect RST to the master reset signal. Suggested regulator manufacturers: • • • Torex (XC6215 series) Seiko (S817 series) BCDSemi (AP2121 series) Re Figure 1-1 check the following sections for component values: • • • • • Section 3.1 on page 9: Cs capacitors (Cs0 – Cs5) Section 3.2 on page 9: Series resistors (Rs0 – Rs5) Section 3.5 on page 10: Voltage levels Section 5.4 on page 16: SDA, SCL pull-up resistors (not shown) Section 3.3 on page 10: LED traces 4 AT42QT1060 9505E–AT42–02/09 AT42QT1060 2. Overview 2.1 Introduction The AT42QT1060 (QT1060) is a digital burst mode charge-transfer (QT™) capacitive sensor driver designed specifically for mobile phone applications. The device can sense from two to six keys; up to four keys can be disabled by not installing their respective sense capacitors (Cs). It also has up to seven configurable input/output lines, with Pulse Width Modulation (PWM) for LED driving. This device includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. Only a few external parts are required for operation. The QT1060 modulates its bursts in a spread-spectrum fashion in order to heavily suppress the effects of external noise, and to suppress RF emissions. 2.2 Keys The QT1060 can have a minimum of two keys and a maximum of six keys. These can be constructed in different shapes and sizes. See “Features” on page 1 for the recommended dimensions. Unused keys should be disabled by removing the corresponding Cs and Rs components and connecting the SNS pins as shown in the “If Unused” column of Table 1-1 on page 2. The unused keys are always pared from the burst sequence in order to optimize speed. See Section 7. on page 25 about setting up the keys. 2.3 Standalone Mode The QT1060 can operate in a standalone mode where an I 2 C-compatible interface is not required. To enter standalone mode, connect SDA to Vss and SCL to Vdd before powering up the QT1060. In standalone mode the default start-up values are used except for the I/O mask (Address 23). The I/O mask is configured so that all the IOs are outputs (IO mask = 0x7F). This means that key detection is reported via their respective IOs. 2.4 2.4.1 I/O Lines Overview There is an input/output (I/O) port consisting of seven lines that can be individually programmed as inputs or outputs. They can be either a digital type or PWM. The PWM level can be set to 256 possible values and is common to all lines. The I/O lines are normally initialized as inputs. However, if an I2C-compatible interface is not used and the SDA and SCL pins are connected to Vss and Vdd respectively, then the I/O lines are initialized as outputs (see Section 2.3). The outputs can also be linked to either the detection channels or the output register to allow the outputs to be either user controlled or to indicate detection. These options can be set in the pin control masks (see Table 6-1 on page 17). Unused I/O lines should be disabled by connecting as shown in the “If Unused” column of Table 1-1 on page 2. See Section 7. on page 25 about setting up the I/O lines. 5 9505E–AT42–02/09 2.4.2 I/O Mask A 1 in any bit position of this mask sets the corresponding pin to an output. If a bit is 0, the pin is an input and the function of the PWM, detect and active state masks will not matter for this pin. The level of the input pins is reflected in the input Status register. Changes to the logic levels on the inputs cause the CHG line to be asserted. 2.4.3 PWM Mask A 1 in any bit position in this mask sets the corresponding pin to operate in PWM mode when its user output buffer is active and configured as an output. A zero sets the pin in digital mode. The PWM value is set in the PWM register that is writable via I2C-compatible communication. 2.4.4 Detection Mask A 1 in any bit position in this mask sets the corresponding pin to be controlled by the status register. If the pin is configured as an output, it is asserted automatically if there is a detection on the corresponding sensor channel. A zero in any bit sets the pin to be controlled by the user output buffer, allowing the user to control the pins directly. Active Level Mask A 1 in any bit position in this mask sets the corresponding pin to be active high if configured as an output. A zero sets the pin to be active low. 2.4.5 2.5 Acquisition/Low Power Modes (LP) There are several different acquisition modes. These are controlled via the Low Power (LP) mode byte (see Section 6.12 on page 20) which can be written to via I 2 C-compatible communication. LP mode controls the intervals between acquisition measurements. Longer intervals consume lower power but have increased response time. During calibration and during the detect integrator (DI) period, the LP mode is temporarily set to LP mode 1 for a faster response. The QT1060 operation is based on a fixed cycle time of approximately 16 ms. The LP mode setting indicates how many of these periods exist per measurement cycle. For example, If LP mode = 1, there is an acquisition every cycle (16 ms). If LP mode = 3, there is an acquisition every 3 cycles (48 ms) etc. SLEEP mode (LP mode = 0) is available for minimum current drain. In this mode, the device is inactive, with the device status being held as it was before going to sleep, and no measurements are carried out. LP settings above mode 32 (512 ms) result in slower thermal drift compensation and should be avoided in applications where fast thermal transients occur. If LP mode = 255 the device operates in Free-run mode. In this mode the device will not enter LP mode between measurements. The device continuously performs measurements one after another, resulting in the fastest response time but the highest power consumption. 2.6 Adjacent Key Suppression (AKS) Technology The device includes Atmel’s patented Adjacent Key Suppression (AKS) technology, to allow the use of tightly spaced keys on a keypad with no loss of selectability by the user. 6 AT42QT1060 9505E–AT42–02/09 AT42QT1060 There can be one AKS group, implemented so that only one key in the group may be reported as being touched at any one time. A key with a higher delta signal dominates and pushes a key with a smaller delta out of detect. This allows a user to slide a finger across multiple keys with only the dominant key reporting touch. The keys which are members of the AKS group can be set via the AKS mask (see Section 6.15 on page 22). Keys outside the group may be in detect simultaneously. For maximum flexibility there is no automatic key recalibration timeout on key detection. The user should issue a recalibration command if the key has been in detect for too long, for example for more than 30 seconds (see Figure 2.9). 2.7 Change Line The Change line (see CHG in Figure 1-1 on page 4) signals when there is a change in state in the Detection or Input status bytes and is active low. It is cleared (allowed to float high) when the host reads the status bytes. If the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the CHG line will be held low. In this case, a read to any memory location will clear the CHG line. The CHG l ine is open-drain and should be connected via a 100k  r esistor to Vdd. It is necessary for minimum power operation as it ensures that the QT1060 can sleep for as long as possible. Communications wake up the QT1060 from sleep causing a higher power consumption if the part is randomly polled. The keys enabled by the key bit mask or a change in the Input port status cause a key change interrupt (see Table 6-1 on page 17). Create a guard channel by removing that key from the key mask and including it in the AKS mask. Touching the guard channel does not cause an interrupt. The key and AKS masks are set by using the mask commands (see Table 6-1 on page 17). 2.8 2.8.1 Types of Reset External Reset An external reset logic line can be used if desired, fed into the RST pin. However, under most conditions it is acceptable to tie RST to Vdd. 2.8.2 Soft Reset The host can cause a device reset by writing a nonzero value to the reset byte. This soft reset triggers the internal watchdog timer on a ~16 ms interval. • After ~16 ms the device resets and wakes again. • After a further 30 ms initialization period the device begins responding to its I2C-compatible slave address. • After another ~80 ms the device asserts the CHG line to indicate it is ready for touch sensing. The device NACKs any attempts to communicate with it during the first 30 ms of its initialization period. After CHG goes low, the device calibrates the sensing channels. When complete, the CHG pin is set low once again. 7 9505E–AT42–02/09 2.9 Calibration The command byte can force a recalibration at any time by writing a nonzero value to the calibration byte. This can be useful to clear out a stuck key condition after a prolonged period of uninterrupted detection. When the device recalibrates, it also autosenses which keys are enabled by examining the burst length of each electrode. If the burst length is either too short (if there is a missing or open Cs capacitor) or too long (a Cs capacitor is shorted), the key is ignored until the next calibration. The count of the number of currently enabled keys is found in the status response byte. This number can change after a CAL command; for example, if a Cs capacitor is intermittent. 2.10 Guard Channel The device has a guard channel option, which allows any key, or combination of keys, to be configured as a guard channel to help prevent false detection. Guard channel keys should be more sensitive than the other keys (physically bigger or larger Cs), subject to burst length limitations (see Section 2.11.3). With guard channel enabled, the designated key(s) is connected to a sensor pad which detects the presence of touch and overrides any output from the other keys using the chip’s AKS feature. The guard channel option is enabled by an I2C-compatible command. To enable a guard channel the relevant key should be removed from the key mask (see Table 61 on page 17). In addition, the guard channel needs to be included within the AKS mask with the other keys for the guard function to operate. Note that a detection on the guard channel does not cause a change request. With the guard channel not enabled, all the keys work normally. Figure 2-1. Guard Channel Example Guard channel 2.11 2.11.1 Signal Processing Detect Threshold The device detects a touch when the signal has crossed a threshold level and remained there for a specified number of counts (see Section 6.11 on page 20). This can be altered on a key-by-key basis using the key threshold I2C-compatible commands. 8 AT42QT1060 9505E–AT42–02/09 AT42QT1060 2.11.2 Detect Integrator The device features a fast detection integrator counter (DI filter), which acts to filter out noise at the small expense of slower response time. The DI filter requires a programmable number of consecutive samples confirmed in detection before the key is declared to be touched. There is also a fast DI on the end of the detection (see Section 6.20 on page 23). The fast DI will not be applied at the start of a detection if a detection on any other channel has already been declared. Burst Length Limitations In a balanced system common signals are regarded as thermal shifts and are removed by the relative referencing drifting, if enabled. This means that the burst lengths must be similar. This can be checked by reading the reference values (Address 52 – 63) and making sure that they are similar. The absolute maximum difference is that the maximum value of reference is less than three times the minimum value amongst all the channels. It is recommended having the burst lengths (references) as close together as possible, through better routing and layout. For example, if the keys have references of 250, 230, 220, 240, 200 and 210, this is acceptable. If the keys have references of 250, 230, 220, 240, 200 and 710, the efficiency of the relative referencing drifting will be affected. The last key’s (710) layout should be changed or relative referencing be disabled. The closer the references are in value, the better the relative referencing drifting performs. If only normal drifting is enabled, the burst lengths can have bigger variations. The normal operating limit of burst lengths is between 16 and 1536 counts. A value out of these limits causes the respective key to be disabled and not measured until a calibration. Signal value for an out-of-limit key is zero. 2.11.3 3. Wiring and Parts 3.1 Cs Sample Capacitors Cs0 – Cs5 are the charge sensing sample capacitors; normally they are identical in nominal value. The optimal Cs values depend on the thickness of the panel and its dielectric constant. Thicker panels require larger values of Cs. Typical values are 2.2 nF to 10 nF. The value of Cs should be chosen so that a light touch on a key produces a reduction of ~10 – 20 in the key signal value (see Section 6.22 on page 23). The chosen Cs value should never be so large that the key signals exceed ~1000, as reported by the chip in the debug data. The Cs capacitors must be X7R or PPS film type, for stability. For consistent sensitivity, they should have a 10 percent tolerance. Twenty percent tolerance may cause small differences in sensitivity from key to key and unit to unit. If a channel is not used, the Cs capacitor may be omitted. 3.2 Rs Resistors Series resistors Rs (Rs0 – Rs5) are inline with the electrode connections and should be used to limit electrostatic discharge (ESD) currents and to suppress radio frequency (RF) interference. They should be approximately 4.7 kto 20 k each. Although these resistors may be omitted, the device may become susceptible to external noise or radio frequency interference (RFI). For details of how to select these resistors see the Application Note QTAN0002, Secrets of a Successful QTouch™ Design, downloadable from the Touch Technology area of Atmel’s website, www.atmel.com. 9 9505E–AT42–02/09 3.3 LED Traces and Other Switching Signals Digital switching signals near the sense lines induce transients into the acquired signals, deteriorating the SNR performance of the device. Such signals should be routed away from the sensing traces and electrodes, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). LED terminals which are multiplexed or switched into a floating state, and which are within, or physically very near, a key (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 10 nF capacitor. This is to suppress capacitive coupling effects which can induce false signal shifts. The bypass capacitor does not need to be next to the LED, in fact it can be quite distant. The bypass capacitor is noncritical and can be of any type. LED terminals which are constantly connected to Vss or Vdd do not need further bypassing. 3.4 PCB Cleanliness All capacitive sensors should be treated as highly sensitive circuits which can be influenced by stray conductive leakage paths. QT devices have a basic resolution in the femtofarad range; in this region, there is no such thing as “no clean flux”. Flux absorbs moisture and becomes conductive between solder joints, causing signal drift and resultant false detections or transient losses of sensitivity or instability. Conformal coatings trap in existing amounts of moisture which then become highly temperature sensitive. The designer should specify ultrasonic cleaning as part of the manufacturing process, and in cases where a high level of humidity is anticipated, the use of conformal coatings after cleaning to keep out moisture. 3.5 Power Supply See Section 8.2 on page 26 for the power supply range. If the power supply fluctuates slowly with temperature, the device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. The usual power supply considerations with QT parts apply to the device. The power should be clean and come from a separate regulator if possible. However, this device is designed to minimize the effects of unstable power, and except in extreme conditions should not require a separate Low Dropout (LDO) regulator. See underneath Figure 1-1 on page 4 for suggested regulator manufacturers. Caution: A regulator IC shared with other logic can result in erratic operation and is not advised. A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed very close to the power pins of the IC. Failure to do so can result in device oscillation, high current consumption, erratic operation etc. It is assumed that a larger bypass capacitor (like1 µF) is somewhere else in the power circuit; for example, near the regulator. To assist with transient regulator stability problems, the QT1060 waits 500 µs any time it wakes up from a sleep state (i.e. in SLEEP and LP modes) before acquiring, to allow Vdd to fully stabilize. 10 AT42QT1060 9505E–AT42–02/09 AT42QT1060 4. I2C-compatible Bus Operation 4.1 Interface Bus More detailed information about the I 2 C -compatible bus protocol is available from www.i2C-bus.org. Devices are connected onto the I2C-compatible bus as shown in Figure 4-1. Both bus lines are connected to Vdd via pull-up resistors. The bus drivers of all I2C-compatible devices must be open-drain type. This implements a wired-AND function which allows any and all devices to drive the bus, one at a time. A low level on the bus is generated when a device outputs a zero. Figure 4-1. I2C-compatible Interface Bus Vdd Device 1 Device 2 Device 3 Device n R1 R2 SDA SCL Table 4-2. Parameter I2C-compatible Bus Specifications Unit 7-bit 100 kHz 4 µs minimum 4 µs minimum 4.7 µs minimum 1 µs maximum Address space Maximum bus speed (SCL) Hold time START condition Setup time for STOP condition Bus free time between a STOP and START condition Rise times on SDA and SCL 4.2 Transferring Data Bits Each data bit transferred on the bus is accompanied by a pulse on the clock line. The level of the data line must be stable when the clock line is high; The only exception to this rule is for generating START and STOP conditions. 11 9505E–AT42–02/09 Figure 4-3. Data Transfer SDA SCL Data Stable Data Stable Data Change 4.3 START and STOP Conditions The host initiates and terminates a data transmission. The transmission is initiated when the host issues a START condition on the bus, and is terminated when the host issues a STOP condition. Between START and STOP conditions, the bus is considered busy. As shown below, START and STOP conditions are signaled by changing the level of the SDA line when the SCL line is high. Figure 4-4. START and STOP Conditions SDA SCL START STOP 4.4 Address Packet Format All address packets are 9 bits long, consisting of 7 address bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is performed, otherwise a write operation is performed. When the device recognizes that it is being addressed, it will acknowledge by pulling SDA low in the ninth SCL (ACK) cycle. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively. The most significant bit of the address byte is transmitted first. The address sent by the host must be consistent with that selected with the option jumpers. Figure 4-5. Address Packet Format Addr MSB SDA Addr LSB R/W ACK SCL 1 START 2 7 8 9 12 AT42QT1060 9505E–AT42–02/09 AT42QT1060 4.5 Data Packet Format All data packets are 9 bits long, consisting of one data byte and an acknowledge bit. During a data transfer, the host generates the clock and the START and STOP conditions, while the Receiver is responsible for acknowledging the reception. An acknowledge (ACK) is signaled by the Receiver pulling the SDA line low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is signaled. 4.6 Combining Address and Data Packets Into a Transmission A transmission consists of a START condition, an SLA+R/W, one or more data packets and a STOP condition. The wired-ANDing of the SCL line is used to implement handshaking between the host and the device. The device extends the SCL low period by pulling the SCL line low whenever it needs extra time for processing between the data transmissions. Holding down either SCL or SDA for clock stretching or any other purpose will slow down the operation of the QT2160. If SCL or SDA is continuously held low for more than ~12ms, this will be deemed as a error condition and the I2C-compatible unit reset. Note: Each write or read cycle must end with a STOP condition. The QT2160 may not respond correctly if a cycle is terminated by a new START condition. Figure 4-7 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP. Figure 4-6. Data Packet Format Data MSB Aggregate SDA SDA from Transmitter SDA from Receiver SCL from Master SLA+R/W Data LSB ACK 1 2 7 Data Byte 8 9 STOP or Next Data Byte Figure 4-7. SDA Packet Transmission Addr MSB Addr LSB R/W ACK Data MSB Data LSB ACK SCL 1 START 2 SLA+R/W 7 8 9 1 2 Data Byte 7 8 9 STOP 13 9505E–AT42–02/09 5. I2C-compatible Communications 5.1 5.1.1 I2C-compatible Protocol Protocol The I2C-compatible protocol is based around access to an address table (see Figure 6-1 on page 17) and supports multibyte reads and writes. The maximum clock rate is 100 kHz. 5.1.2 Signals The I2C-compatible interface requires two signals to operate: • SDA - Serial Data • SCL - Serial Clock A third line, CHG, is used to signal when the device has seen a change in the status byte: • CHG: Open-drain, active low when any capacitive key in the key mask has changed state or any input line has changed state since the last I2C-compatible read. After reading the two status bytes, this pin floats (high) again if it is pulled up with an external resistor. If the status bytes change back to their original state before the host has read the status bytes (for example, a touch followed by a release), the CHG line will be held low. In this case, a read to any memory location will clear the CHG line. 5.1.3 Clock Stretching The device has an internal monitor that resets its I 2 C-compatible hardware if either I2C-compatible line is held low, without the other line changing, for more than about 14 ms. It is important that no other device on the bus clock stretches for 14 ms, otherwise the monitor will reset the I2C-compatible hardware and transfers with the chip may be corrupted. If the device is configured to run in stand-alone mode, the monitor will be turned off. 5.2 I2C-compatible Address There is one preset I2C-compatible address of 0x12. This is not changeable. 5.3 5.3.1 Data Read/Write Writing Data to the Device The sequence of events required to write data to the device is shown next. Host to Device S SLA+W A MemAddress A Device to Host Data A P Table 5-1. Key S SLA+W A Description of Write Data Bits Description Start condition Slave address plus write bit Acknowledge bit 14 AT42QT1060 9505E–AT42–02/09 AT42QT1060 Table 5-1. Key MemAddress Data P Description of Write Data Bits Description Target memory address within device Data to be written Stop condition 1. The host initiates the transfer by sending the START condition 2. The host follows this by sending the slave address of the device together with the WRITE bit. 3. The device sends an ACK. 4. The host then sends the memory address within the device it wishes to write to. 5. The device sends an ACK. 6. The host transmits one or more data bytes; each is acknowledged by the device. 7. If the host sends more than one data byte, they are written to consecutive memory addresses. 8. The device automatically increments the target memory address after writing each data byte. 9. After writing the last data byte, the host should send the STOP condition. Note: the host should not try to write beyond address 255 because this is the limit of the device’s internal memory address. 5.3.2 Reading Data From the Device The sequence of events required to read data from the device is shown next. Host to Device S SLA+W Data 1 A A MemAddress A P Data 2 A S Device to Host SLA+R Data n A /A P 1. The host initiates the transfer by sending the START condition 2. The host follows this by sending the slave address of the device together with the WRITE bit. 3. The device sends an ACK. 4. The host then sends the memory address within the device it wishes to read from. 5. The device sends an ACK. 6. The host must then send a STOP and a START condition followed by the slave address again but this time accompanied by the READ bit. 7. The device returns an ACK, followed by a data byte. 8. The host must return either an ACK or NACK. a. If the host returns an ACK, the device subsequently transmits the data byte from the next address. Each time a data byte is transmitted, the device automatically increments the internal address. The device continues to return data bytes until the host responds with a NACK. b. If the host returns a NACK, it should then terminate the transfer by issuing the STOP condition. 15 9505E–AT42–02/09 9. The device resets the internal address to the location indicated by the memory address sent to it previously. Therefore, there is no need to send the memory address again when reading from the same location. 5.4 SDA, SCL The I2C-compatible bus transmits data and clock with SDA and SCL respectively. They are open-drain; that is I2C-compatible master and slave devices can only drive these lines low or leave them open. The termination resistors (not shown) pull the line up to Vdd if no I2C-compatible device is pulling it down. The termination resistors commonly range from 1 k to 10 kand should be chosen so that the rise times on SDA and SCL meet the I2C-compatible specifications (1 µs maximum). Standalone mode: if I2C-compatible communications are not required, then standalone mode can be enabled by connecting SDA to Vss and SCL to Vdd. See Section 2.3 on page 5 for more information. 16 AT42QT1060 9505E–AT42–02/09 AT42QT1060 6. Setups 6.1 Introduction The device calibrates and processes signals using a number of algorithms specifically designed to provide for high survivability in the face of adverse environmental challenges. User-defined Setups are employed to alter these algorithms to suit each application. These Setups are loaded into the device over the I2C-compatible serial interfaces. Table 6-1. Address 0 1 2 3 4 5 6 – 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 – 39 Chip ID Version Minor version Reserved Detection status Input port status Reserved Calibrate Reset Drift Option Positive Recalibration Delay NTHR key 0 NTHR key 1 NTHR key 2 NTHR key 3 NTHR key 4 NTHR key 5 LP mode I/O mask Key mask AKS mask PWM mask Detection mask Active level mask User output buffer DI PWM level Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Res'd MSB MSB MSB MSB MSB MSB MSB MSB MSB CAL Res'd Res'd Res'd Res'd Res'd MSB MSB Reserved IO6 Res'd Res'd IO6 IO6 IO6 IO6 IO5 Key 5 Key 5 IO5 IO5 IO5 IO5 IO4 Key 4 Key 4 IO4 IO4 IO4 IO4 IO3 Key 3 Key 3 IO3 IO3 IO3 IO3 IO2 Key 2 Key 2 IO2 IO2 IO2 IO2 IO1 Key 1 Key 1 IO1 IO1 IO1 IO1 Res'd R R Calibrating Res'd Res'd Input 6 Key5 Input 5 Internal Register Address Allocation Use R/W R R R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Major ID (= 3) Version number Minor version number Reserved Key4 Input 4 Reserved Key3 Input 3 Minor ID (= 1) Key2 Input 2 Key1 Input 1 Key0 Input 0 Writing a nonzero value forces a calibration Writing a nonzero value forces a reset Res'd Res'd Res'd Res'd Res'd DRIFT LSB LSB LSB LSB LSB LSB LSB LSB IO0 Key 0 Key 0 IO0 IO0 IO0 IO0 LSB LSB 17 9505E–AT42–02/09 Table 6-1. Address 40 – 51 52 – 63 Note: Internal Register Address Allocation (Continued) Use Key 0 – 5 Signal Key 0 – 5 Reference R/W R R Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Res'd = Reserved; only write zero to these bits. 6.2 Address 0: Chip ID Table 6-2. Address 0 Chip ID b7 b6 b5 b4 b3 b2 b1 b0 MAJOR ID MINOR ID MAJOR ID: Reads back as 3 MINOR ID: Reads back as 1 6.3 Address 1: Device Version Number Table 6-3. Address 1 Device Version Number b7 b6 b5 b4 b3 b2 b1 b0 DEVICE VERSION NUMBER DEVICE VERSION NUMBER: this is the 8-bit firmware version number (0x03). 6.4 Address 2: Minor Version Number Table 6-4. Address 2 Minor Version Number b7 b6 b5 b4 b3 b2 b1 b0 MINOR VERSION NUMBER MINOR VERSION NUMBER: this is the 8-bit minor firmware revision number (0x00). 6.5 Address 4: Detection Status Table 6-5. Address 4 Detection Status b7 CAL b6 Reserved b5 KEY5 b4 KEY4 b3 KEY3 b2 KEY2 b1 KEY1 b0 KEY0 CAL: a 1 indicates that the QT1060 is currently calibrating. KEY0 – 5: bits 0 to 5 indicate which keys are in detection, if any; touched keys report as 1, untouched or disabled keys report as 0. 18 AT42QT1060 9505E–AT42–02/09 AT42QT1060 6.6 Address 5: Input Port Status Table 6-6. Address 5 Input Port Status b7 Reserved b6 INPUT 6 b5 INPUT 5 b4 INPUT 4 b3 INPUT 3 b2 INPUT 2 b1 INPUT 1 b0 INPUT 0 INPUT 0 – 6: t hese bits indicate the state of the IO lines that are configured as inputs; 1 indicating logic 1 on the input, 0 indicating logic 0. The bits corresponding to any keys configured as outputs read as 0. 6.7 Address 12: Calibrate Table 6-7. Address 12 Calibrate b7 b6 b5 b4 b3 b2 b1 b0 Writing a nonzero value forces a calibration Writing any nonzero value into this address triggers the device to start a calibration cycle. The CAL flag in the status register is set when begun and cleared when the calibration has finished. 6.8 Address 13: Reset Table 6-8. Address 13 Reset b7 b6 b5 b4 b3 b2 b1 b0 Writing a nonzero value forces a reset Writing any nonzero value to this address triggers the device to reset. 6.9 Address 14: Drift Option Table 6-9. Address 14 Drift Option b7 b6 b5 b4 b3 b2 b1 b0 DRIFT DRIFT: there are two types of drift option: normal and relative referencing. If DRIFT = 0, relative referencing and normal drift are enabled. If DRIFT = 1, only normal drift is enabled. Relative referencing compensates for fast signal drifts that are common to all keys. This mode is suitable if the keys are placed close to each other and have closely matched burst lengths (see Section 2.11.3 on page 9). Normal drifting is also carried out but at a slower rate compared to the relative referencing drift rate. Default: 1 (relative referencing Off) 19 9505E–AT42–02/09 6.10 Address 15: Positive Recalibration Delay Table 6-10. Address 15 Positive Recalibration Delay b7 b6 b5 b4 b3 b2 b1 b0 POSITIVE RECALIBRATION DELAY POSITIVE RECALIBRATION DELAY: I f any key is found to have a significant drop in capacitance, i.e. an “away from touch” signal, then this is deemed to be an error condition. If this condition persists for more than the Positive Recalibration Delay (PRD) period, then an automatic recalibration is carried out on all keys. The condition that the error is triggered on depends on the drift compensation mode. If relative referencing drifting is enabled (DRIFT = 0), then an “away from touch” delta of more than four counts triggers the error. If only normal mode drifting is enabled (DRIFT = 1), then an “away from touch” delta of more than 75 percent of the NTHR triggers the error. The PRD is incremented according to the current LP mode setting (the duration is equal to the cycle time multiplied by the PRD value). Default: ~7 ms x 40 = 280 ms (in free-run mode) 6.11 Address 16 – 21: NTHR Keys 0 – 5 Table 6-11. Address 16 – 21 NTHR Keys 0 – 5 b7 MSB b6 b5 b4 b3 b2 b1 b0 LSB NTHR Keys 0 – 5: these 8-bit values set the threshold value for each key to register a detection. Default: 10 counts 6.12 Address 22: LP Mode Table 6-12. Address 22 LP Mode b7 MSB b6 b5 b4 b3 b2 b1 b0 LSB LP Mode: t his 8-bit value determines the number of 16 ms intervals between key measurements. Longer intervals between measurements yield lower power consumption at the expense of slower response to touch. 20 AT42QT1060 9505E–AT42–02/09 AT42QT1060 LP7 – 0 0 1 2 3 4 ...254 255 Mode SLEEP 16 ms 32 ms 48 ms 64 ms 4.064s Free-run A value of zero causes the device to enter SLEEP mode where no measurements are performed. A value of 255 causes the device to enter Free-run mode where measurements are continuously performed without entering a low power mode between measurements. This provides the fastest response time but also the highest power consumption. Default: 2 (32 ms between key acquisitions) 6.13 Address 23: I/O Mask Table 6-13. Address 23 I/O Mask b7 Reserved b6 IO6 b5 IO5 b4 IO4 b3 IO3 b2 IO2 b1 IO1 b0 IO0 IO0 – 6: these bits control the direction of the IO pins. A 1 sets the pin as an output, a 0 as an input. See Section 6.24 on page 24 for I/O register precedence and example usage. Default: 0 (all IO's are set as inputs, when using the I2C-compatible mode) (all IO's are set as outputs (0x7F), when using the standalone mode) 6.14 Address 24: Key Mask Table 6-14. Address 24 Key Mask b7 CAL b6 Reserved b5 KEY5 b4 KEY4 b3 KEY3 b2 KEY2 b1 KEY1 b0 KEY0 CAL: this bit controls whether the CAL bit causes a CHG transition. KEY0 – 5 (Key Mask): these bits control whether a change in the corresponding bit in the detection status register generates a transition on the CHG line. A 1 allows the status bit to cause a CHG request, a 0 stops the corresponding bit from causing a CHG request. Default: 0xBF (all bits create a CHG request) 21 9505E–AT42–02/09 6.15 Address 25: AKS Mask Table 6-15. Address 25 AKS Mask b7 b6 b5 KEY5 b4 KEY4 b3 KEY3 b2 KEY2 b1 KEY1 b0 KEY0 Reserved Reserved KEY0 – 5 (AKS Mask): these bits control which keys are included in the AKS group. A 1 means the corresponding key is included in the AKS group and may only go into detect when it has the largest signal change of any key in the group. A 0 means that it is excluded and can go into detect whenever its threshold is passed. Default: 0x00 (no keys are within the AKS group) 6.16 Address 26: PWM Mask Table 6-16. Address 26 PWM Mask b7 Reserved b6 IO6 b5 IO5 b4 IO4 b3 IO3 b2 IO2 b1 IO1 b0 IO0 IO0 – 6 (PWM Mask): these bits control which IOs that are configured as outputs, and its user output buffer activated, will output a PWM signal. A 1 means the output generates a PWM signal, a 0 means the output generates a logic level. The active level of the output (both logical and PWM) is determined by the Active level mask. See Section 6.24 on page 24 for I/O register precedence and example usage. Default: 0x00 (PWM is off on all IOs) 6.17 Address 27: Detection Mask Table 6-17. Address 27 Detection Mask b7 Reserved b6 IO6 b5 IO5 b4 IO4 b3 IO3 b2 IO2 b1 IO1 b0 IO0 IO0 – 6 (Detection Mask): these bits control which IOs that are configured as outputs will be controlled by their corresponding capacitive key. A 1 means the output “n” generates an active output when key “n” is detecting a touch. A 0 means that the output is controlled by the output buffer. See Section 6.24 on page 24 for I/O register precedence and example usage. Default: 0x3F (all IOs are controlled by key status) 6.18 Address 28: Active Level Mask Table 6-18. Address 28 Active Level Mask b7 Reserved b6 IO6 b5 IO5 b4 IO4 b3 IO3 b2 IO2 b1 IO1 b0 IO0 IO0 – 6 (Active Level Mask): t hese bits control the active logic level for the IOs that are configured as outputs. A 1 means the output generates an active high output, a 0 means that the output is active low. See Section 6.24 for IO register precedence and example usage. Default: 0 (all IOs are active low output) 22 AT42QT1060 9505E–AT42–02/09 AT42QT1060 6.19 Address 29: User Output Buffer Table 6-19. Address 29 User Output Buffer b7 Reserved b6 IO6 b5 IO5 b4 IO4 b3 IO3 b2 IO2 b1 IO1 b0 IO0 IO0 – 6 (User Output Buffer): these bits control the output level for the IO's that are configured as outputs. A 1 means the output generates an active output, a 0 means that the output is inactive. See Section 6.24 on page 24 for I/O register precedence and example usage. Default: 0 (all IO's inactive) 6.20 Address 30: Detection Integrator Table 6-20. Address 30 Detection Integrator b7 MSB b6 b5 b4 b3 b2 b1 b0 LSB DETECTION INTEGRATOR DETECTION INTEGRATOR: this 8-bit value controls the number of consecutive measurements that must be confirmed as having passed the key threshold before that key is registered as being in detect. A value of zero should not be used. Default: 3 6.21 Address 31: PWM Level Table 6-21. Address 31 PWM Level b7 MSB b6 b5 b4 b3 b2 b1 b0 LSB PWM LEVEL PWM LEVEL: this 8-bit value controls the duty cycle of the PWM output signal. A value of 255 means the output is permanently active. Default: 128 (50:50 duty cycle) 6.22 Address 40 – 51: Key Signal Table 6-22. Address 40 41 42 – 51 Key Signal b7 b6 b5 b4 b3 b2 b1 b0 LSB OF KEY SIGNAL FOR KEY 0 MSB OF KEY SIGNAL FOR KEY 0 LSB/MSB OF KEY SIGNAL FOR KEYS 1 – 5 KEY SIGNAL: addresses 40 – 51 allow key signals to be read for each key, starting with key 0. There are two bytes of data for each key. These are the key’s 16-bit key signals which are accessed as two 8-bit bytes, stored LSB first. These addresses are read-only. 23 9505E–AT42–02/09 6.23 Address 52 – 63: Reference Data Table 6-23. Address 52 53 54 – 63 Reference Data b7 b6 b5 b4 b3 b2 b1 b0 LSB OF REFERENCE DATA FOR KEY 0 MSB OF REFERENCE DATA FOR KEY 0 LSB/MSB OF REFERENCE DATA FOR KEYS 1 – 5 REFERENCE DATA: addresses 52 – 63 allow reference data to be read for each key, starting with key 0. There are two bytes of data for each key. These are the key’s 16-bit reference data which is accessed as two 8-bit bytes, stored LSB first. These addresses are read-only. 6.24 Mask Precedence Table 6-24 gives the order of priority for the settings in the mask inputs/outputs. The settings in the left-most column have the highest priority, those in the second-left have the next priority etc. If two or more settings are incompatible then the setting in the left-hand column overrides the other. The right-most column, I/O Function, specifies the expected result. Table 6-24. I/O Mask (bit n) 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: Input/Output Mask Precedence Detection Mask (bit n) X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PWM Mask (bit n) X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Active Level Mask (bit n) X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 User Reg (bit n) X 0 1 0 1 0 1 0 1 X X X X X X X X QTouch Key (channel n) X X X X X X X X X Untouched Touched Untouched Touched Untouched Touched Untouched Touched I/O Function (I/O n) Digital Input Output - Vdd Output - 0V Output - 0V Output - Vdd Output - Vdd PWM Output Output - 0V PWM Output Output - Vdd Output - 0V Output - 0V Output - Vdd Output - Vdd PWM Output Output - 0V PWM Output X = don’t care (can be a 1 or a 0) 24 AT42QT1060 9505E–AT42–02/09 AT42QT1060 7. Setting Up Procedures To Set Up Keys Set the number of keys required by leaving the SNS pins unconnected in unused keys. To Set Up I/O Lines Determine the direction of the I /O lines. If any lines are unused , set them to be outputs and leave them unconnected . [Address 23: I/O Mask] Determine whether a change in the corresponding bit in the detection status register generates a transition on the CHG line. [Address 24: Key Mask] Determine which I /Os that are configured as outputs will be controlled by their corresponding capacitive key. [Address 27: Detection Mask] D etermine which keys are in the AKS group . [Address 25 : AKS Mask] Determine the duty cycle of the PW M output signal . [Address 31 : PW M Level ] Determine the number of measurements that must be confirmed as having passed the key threshold before that key is registered as being in detect . [Address 30: Detection Integrator ] Determine which I /Os that are configured as outputs will output a PW M signal. [Address 26 : PW M Mask] Tune the sensitivity of the keys by adjusting the value of the sampling capacitor, Cs and the negative threshold (NTHR) [Address 16 – 21: NTHR] Determine the active logic level for the I/Os that are configured as outputs . [Address 28: Active Level Mask] Determine the output level for the I /Os that are configured as outputs . [Address 29 : U ser Output Buffer] 25 9505E–AT42–02/09 8. Specifications 8.1 Vdd Max continuous pin current, any control or drive pin Short circuit duration to ground, any pin Short circuit duration to Vdd, any pin Voltage forced onto any pin Absolute Maximum Specifications -0.5 to +6V ±10 mA infinite infinite -0.6V to (Vdd + 0.6) Volts CAUTION: Stresses beyond those listed under Absolute Maximum Specifications may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum specification conditions for extended periods may affect device reliability. 8.2 Recommended Operating Conditions -40oC to +85oC -55oC to +125oC +1.8V to 5.5V ±25 mV 2 to 20 pF Operating temp Storage temp Vdd Supply ripple+noise Cx load capacitance per key 8.3 DC Specifications Vdd = 3.3V, Cs = 10nF, load = 5 pF, 32 ms default sleep, Ta = recommended range, unless otherwise noted Parameter Vil Vih Vol Voh Iil Ar Description Low input logic level High input logic level Low output voltage High output voltage Input leakage current Acquisition resolution Minimum – 0.6Vdd – Vdd - 0.7V – – Typical – – – – – 8 Maximum 0.2Vdd – 0.5 – ±1 – Units V V V V µA bits 4 mA sink 1 mA source Notes 26 AT42QT1060 9505E–AT42–02/09 AT42QT1060 Cs = 10nF, Cx = 5 pF, Rs = 10k Idd (µA) at Vdd = LP Mode 5V 0 (SLEEP) 1 (16 ms) 2 (32 ms) 4 (64 ms) 8 (128 ms) 16 (256 ms) 32 (512 ms) 64 (1024 ms) 2.48 1745 1615 1545 1510 1500 1485 1475 3.3V 1.8 1135 1065 1030 1010 1000 995 992 1.8V 1.1 403 373 360 351 348 346 345 8.4 AC Specifications Description Response time Sample frequency Power-up delay to operate/calibration time I2C-compatible clock rate Reset pulse width Minimum DI setting x 16 ms 162 – – 5 Typical – 180