AT42QT1111-MU

Features • Sensor Keys: • – Up to 11 QTouch™ channels Data Acquistion: – Measurement of keys triggered either by a signal applied to the SYNC pin or at regular intervals timed by the AT42QT1110's internal clock – Keys measured sequentially for better performance, or in parallel groups for faster operation – Raw data for key touches can be read as a report over the SPI interface Discrete Outputs: – Configurable “Detect” outputs indicating individual key touch (7-key mode) Device Setup: – Device configuration can be stored in EEPROM Technology: – Patented spread-spectrum charge-transfer (direct mode) Key Outline Sizes: – 6 mm x 6 mm or larger (panel thickness dependent); widely different sizes and shapes possible, including solid or ring shapes Key Spacings: – 7 mm center to center or more (panel thickness dependent) Layers Required: – One Electrode Materials: – Etched copper, silver, carbon, Indium Tin Oxide (ITO) Electrode Substrates: – PCB, FPCB, plastic films, glass Panel Materials: – Plastic, glass, composites, painted surfaces (low particle density metallic paints possible) Panel Thickness: – Up to 10 mm glass, 5 mm plastic (electrode size dependent) Key Sensitivity: – Individually settable via simple commands over serial interface Adjacent Key Suppression® (AKS™) – Patented AKS technology to enable accurate key detection Interface: – Full-duplex SPI slave mode (750 KHz), “change” pin, discrete detection outputs Moisture Tolerance Good Power: – 1.8V ~ 5.5V Package: – 32-pin 5 x 5 mm MLF RoHS compliant – 32-pin 7 x 7 mm TQFP RoHS compliant Signal Processing: – Self-calibration, auto drift compensation, noise filtering, AKS technology Applications: – Consumer and industrial applications, such as TV, media player, etc • • • • QTouch™ 11-key Sensor IC AT42QT1111-MU AT42QT1111-AU • • • • • • • • • • • • • • 9571A–AT42–02/10 1. Pinout and Schematic 1.1 Pinout Configuration SNS9K/DETECT5 SNS8K/DETECT3 SNS9/DETECT4 CHANGE RESET SNS10/DETECT6 SNS10K/SYNC SNS0 SNS0K SNS1 SNS1K VDD VSS SNS2K SNS2 SNS3 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 QT1111 20 19 18 17 9 10 11 12 13 14 15 16 QT1110 SNS8/DETECT2 SNS7/DETECT1 SNS7K/DETECT0 VSS SNS6 SNS6K VDD SCK 2 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 SNS5 SNS4K SNS4 SNS3K MISO MOSI SNS5K SS AT42QT1111-MU/AT42QT1111-AU 1.2 Pin Descriptions Pin Listing Name SNS0K SNS1 SNS1K Vdd Vss SNS2K SNS2 SNS3 SNS3K SNS4 SNS4K SNS5 SNS5K SS MOSI MISO SCK Vdd SNS6K SNS6 Vss SNS7K/DETECT0 SNS7/DETECT1 SNS8/DETECT2 SNS8K/DETECT3 SNS9/DETECT4 SNS9K/DETECT5 CHANGE RESET SNS10/DETECT6 SNS10K/SYNC SNS0 Type I/O I/O I/O P P I/O I/O I/O I/O I/O I/O I/O I/O I I O I P I/O I/O P I/O I/O I/O I/O I/O I/O OD I I/O I/O I/O Comments Sense Pin Sense Pin Sense Pin Power Supply Ground Sense Pin Sense Pin Sense Pin Sense Pin Sense Pin Sense Pin Sense Pin Sense Pin Enable SPI SPI Data In SPI Data Out SPI Clock Power Sense Pin Sense Pin Supply Ground Sense Pin/Key Status Indicator Sense Pin/Key Status Indicator Sense Pin / Key Status Indicator Sense Pin / Key Status Indicator Sense Pin / Key Status Indicator Sense Pin / Key Status Indicator Touch Event Indicator Reset Sense Pin / Key Status Indicator Sense Pin / Synchronization Input Sense Pin If Unused, Connect To... Leave open Leave open Leave open – – Leave open Leave open Leave open Leave open Leave open Leave open Leave open Leave open Vss via 100 k resistor to enable SPI Vdd via 100 k resistor to disable SPI Leave open Leave open Leave open – Leave open Leave open – Leave open Leave open Leave open Leave open Leave open Leave open Leave open Vdd Leave open Vdd or Vss via 100 k resistor Leave open Table 1-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 I O Input only Output only, push-pull I/O OD Input and output Open drain output P Ground or power 3 9571A–AT42–02/10 1.3 Schematics Typical Circuit: 7 keys With Detect Outputs and No External Trigger Figure 1-1. 4 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 Vunreg VREG QT1111 AT42QT1111-MU/AT42QT1111-AU Figure 1-2. Typical Circuit: 11 Keys With No External Trigger Vunreg VREG QT1111 5 9571A–AT42–02/10 Figure 1-3. Typical Circuit: 10 Keys With External Trigger (SYNC Mode) Vunreg VREG QT1111 Suggested voltage regulator manufacturers: • Torex (XC6215 series) • Seiko (S817 series) • BCDSemi (AP2121 series) Re Figure 1-1, Figure 1-2 and Figure 1-3 check the following sections for component values: • Section 3.1 on page 8: Cs capacitors (Cs0 – Cs10) • Section 3.2 on page 8: Sample resistors (Rs0 – Rs10) • Section 3.5 on page 9: Voltage levels • Section 3.3 on page 8: LED traces 6 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 2. Overview of the AT42QT1111 2.1 Introduction The AT42QT1111 (QT1111) is a digital burst mode charge-transfer (QT™) capacitive sensor driver designed for any touch-key applications. The keys can be constructed in different shapes and sizes. Refer to the Touch Sensors Design Guide and Application Note QTAN0002, Secrets of a Successful QTouch™ Design, for more information on construction and design methods (both downloadable from the Atmel® website). The device includes all signal processing functions necessary to provide stable sensing under a wide variety of changing conditions, and the outputs are fully debounced. Only a few external parts are required for operation. The QT1111 modulates its bursts in a spread-spectrum fashion in order to suppress heavily the effects of external noise, and to suppress RF emissions. 2.2 Configurations The QT1111 is designed as a versatile device, capable of various configurations. There are two basic configurations for the QT1111: • 11-key QTouch. The device can sense up to 11 keys. • 7-key QTouch with individual outputs for each key. The device can sense up to 7 keys and drive the matching Detect outputs to a user-configurable PWM. Both configurations allow for a choice of acquisition modes, thus providing a variety of possibilities that will satisfy most applications (see the following sections for more information). Additionally, the SYNC line can be used as an external trigger input. Note that in 11-key mode the SYNC line replaces one key, thus allowing only 10 keys. See Section 4.7 on page 18 for more information. 2.3 Guard Channel The device has a guard channel option (available in all key modes), which allows one key to be configured as a guard channel to help prevent false detection. See Section 4.9 on page 19 for more information. 2.4 Self-test Functions The QT1111 has two types of self-test functions: • Internal Hardware tests – check for hardware failures in the device’s internal memory. • Functional checks – confirm that the device is operating within expected parameters. See Section 4.10 on page 20 for more information. 7 9571A–AT42–02/10 3. Wiring and Parts 3.1 Cs Sample Capacitors Cs0 – Cs10 are the charge sensing sample capacitors. Normally they are identical in nominal value. The optimal Cs values depend on the thickness of the panel and its dielectric constant. Thicker panels require larger values of Cs. Values can be in the range 2.2 nF (for faster operation) to 33 nF (for best sensitivity); typical values are 4.7 nF to 10 nF. The value of Cs should be chosen so that a light touch on a key produces a reduction of ~20 to 30 in the key signal value (see Section 6.8 on page 26). The chosen Cs value should never be so large that the key signals exceed ~1000, as reported by the chip in the debug data. The Cs capacitors must be X7R or PPS film type, for stability. For consistent sensitivity, they should have a 10 percent tolerance. Twenty percent tolerance may cause small differences in sensitivity from key to key and unit to unit. If a key is not used, the Cs capacitor may be omitted. 3.2 Rs Resistors The series resistors Rs0 – Rs10 are inline with the electrode connections and should be used to limit electrostatic discharge (ESD) currents and to suppress radio frequency (RF) interference. Values should be approximately 2 kto 20 k each; a typical value is 4.7 k. Although these resistors may be omitted, the device may become susceptible to external noise or radio frequency interference (RFI). For details of how to select these resistors see the Application Note QTAN0002, Secrets of a Successful QTouch™ Design, downloadable from the Touch Technology area of Atmel’s website, www.atmel.com. 3.3 LED Traces and Other Switching Signals Digital switching signals near the sense lines can induce transients into the acquired signals, deteriorating the SNR performance of the device. Such signals should be routed away from the sensing traces and electrodes, or the design should be such that these lines are not switched during the course of signal acquisition (bursts). LED terminals which are multiplexed or switched into a floating state, and which are within, or physically very near, a key (even if on another nearby PCB) should be bypassed to either Vss or Vdd with at least a 1 nF capacitor. This is to suppress capacitive coupling effects which can induce false signal shifts. The bypass capacitor does not need to be next to the LED, in fact it can be quite distant. The bypass capacitor is noncritical and can be of any type. LED terminals which are constantly connected to Vss or Vdd do not need further bypassing. 3.4 PCB Cleanliness Modern no-clean flux is generally compatible with capacitive sensing circuits. CAUTION: If a PCB is reworked to correct soldering faults relating to the QT1111, or to any associated traces or components, be sure that you fully understand the nature of the flux used during the rework process. Leakage currents from hygroscopic ionic residues can stop capacitive sensors from functioning. If you have any doubts, a thorough cleaning after rework may be the only safe option. 8 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 3.5 Power Supply See Section 8.2 on page 38 for the power supply range. If the power supply fluctuates slowly with temperature, the device tracks and compensates for these changes automatically with only minor changes in sensitivity. If the supply voltage drifts or shifts quickly, the drift compensation mechanism is not able to keep up, causing sensitivity anomalies or false detections. The usual power supply considerations with QT parts apply to the device. The power should be clean and come from a separate regulator if possible. However, this device is designed to minimize the effects of unstable power, and, except in extreme conditions, should not require a separate Low Dropout (LDO) regulator. See underneath Figure 1.3 on page 4 for suggested regulator manufacturers. Caution: A regulator IC shared with other logic can result in erratic operation and is not advised. A single ceramic 0.1 µF bypass capacitor, with short traces, should be placed very close to the power pins of the IC. Failure to do so can result in device oscillation, high current consumption, erratic operation etc. It is assumed that a larger bypass capacitor (like1 µF) is somewhere else in the power circuit; for example, near the regulator. 3.6 MLF Package Restrictions The central pad on the underside of the MLF chip should be connected to ground. Do not run any tracks underneath the body of the chip, only ground. Figure 3-1 shows an example of good/bad tracking. Figure 3-1. Examples of Good and Bad Tracking Example of GOOD Tracking Example of BAD Tracking 9 9571A–AT42–02/10 4. Detailed Operations 4.1 4.1.1 Communications Introduction All communication with the device is carried out over the Serial Peripheral Interface (SPI). This is a synchronous serial data link that operates in full-duplex mode. The host communicates with the QT controller over the SPI using a master-slave relationship, with the QT1111 acting in slave mode. 4.1.2 SPI Operation The SPI uses four logic signals: • Serial Clock (SCK) – output from the host. • Master Output, Slave Input (MOSI) – output from the host, input to the QT controller. Used by the host to send data to the QT controller. • Master Input, Slave Output (MISO) – input to the host, output from the QT controller. Used by the QT device to send data to the host. • Slave Select (SS) – active low output from the host. At each byte, the master pulls SS low and generates 8 clock pulses on SCK. With these 8 clock pulses, a byte of data is transmitted from the master to the slave over MOSI, most significant bit (msb) first. Simultaneously a byte of data is transmitted from the slave to the master over MISO, also most significant bit first. The slave reads the status of MOSI at the leading edge of each clock pulse, and the master reads the slave’s data from MISO at the trailing edge. The QT1111 requires that the clock idles “high”, meaning that the data on MOSI and MISO pins are set at the falling edges and sampled at the rising edges. That is: Clock polarity CPOL = 1 Clock phase CPHA = 1 The QT1111 SPI interface can operate at any SCK frequency up to 750 KHz. In multibyte communications, the master must pause for a minimum delay of 300 µs between the completion of one byte exchange and the beginning of the next. Note that the number of bytes to be transmitted depends on the initial command sent by the host. This sets the mode on the QT1111 so that the QT1111 knows how to respond to, or how to interpret, the following bytes. If there is a delay of >100 ms between bytes while the QT1111 is waiting for data, or waiting to send data, then the incomplete transmission is discarded and the device resets its SPI state machine. It will then interpret the next byte it receives as a fresh command. When the QT1111 SPI interface is receiving a new command, it returns the “Idle” status code (0x55) on MISO during the first byte exchange to indicate to the master that it is in the correct state for receiving instructions. 10 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 4.1.3 CRC Bytes If enabled, a CRC checking procedure is implemented on all communications between the SPI master and the QT1111. In this case, each command or report request sent by the master must have a byte appended containing the CRC checksum of the data sent. The QT1111 will not respond to commands until the CRC byte has been received and verified. Sample C code showing the algorithm for calculating the CRC of the data can be found in Appendix A. When the QT1111 is expecting a CRC byte, it returns (on MISO) the calculated CRC byte which it expects to receive. This is sent simultaneously with the QT1111 receiving the CRC byte from the master (that is, during the same byte exchange). This allows both devices to confirm that the data was sent correctly. All data returned by the QT1111 is also be followed by a CRC byte, allowing the master to confirm the integrity of the data transmission. 4.1.4 SPI Commands There are three types of communication between the SPI master and the QT1111: • Control commands (see Section 5 on page 22) – To send control instructions to the QT1111 • Report requests (see Section 6 on page 24) – To reading status information from the QT1111 • Setup commands (see Section 7 on page 28) – To set configuration options (“Set” instructions) – To read configuration options (“Get” instructions) Additionally the “Null” command (0x00) is transmitted by the host device as it is receiving data from the QT1111. 4.1.4.1 Control Commands A control command is an instruction sent to the QT1111 that controls operations of the device, and for which no response is required. Examples of control commands are: “Reset”, “Calibrate”, “Send Setups”. With the exception of “Send Setups”, control commands normally require a single byte exchange, unless CRC checking is enabled, in which case a second byte must be transmitted by the host with the calculated CRC of the command byte. Figure 4-1. Sleep Command – CRC Disabled Host (Sends on MOSI) Command: 0x05 Device (Responds on MISO) Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission 11 9571A–AT42–02/10 Figure 4-2. Sleep Command – CRC Enabled Host (Sends on MOSI) Command: 0x05 Device (Responds on MISO) Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission Command CRC: 0x3F Response: 0x3F (Expected Command CRC) When the “Send Setups” command is received, the QT1111 stops measurement of QTouch sensors and waits for 42 bytes of data to be sent. Only when all 42 bytes have been received (and the CRC byte, if CRC is enabled), the QT1111 applies all the settings to RAM and resumes measurement. In this case, if CRC is enabled, the CRC byte is calculated for all the data sent by the host, including the command byte 0x01. Control Commands are specified in detail in Section 5 on page 22. 4.1.5 Report Requests Report Requests are sent by the Host to instruct the QT1111 to return status information. The host sends the appropiate “Report Request” command, then transmits Null bytes on MOSI while the QT1111 returns the report data on MISO. Figure 4-3. All Keys Report – CRC Disabled Host (Sends on MOSI) Command: 0xC1 Device (Responds on MISO) Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission Null: 0x00 Key Status Report Byte 0 Null: 0x00 Key Status Report Byte 1 12 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU For example, Figure 4-3 on page 12 shows the exchange that takes place to read the 2-byte “All Keys” report. In this exchange, the host sends: 0xC1 — 0x00 — 0x00 and the QT1110 returns (simultaneously): 0x55 — Report Byte 0 — Report Byte 1 If CRC is enabled, this exchange is extended to 5 bytes, as shown in Figure 4-4. Figure 4-4. All Keys Report – CRC Enabled Host (Sends on MOSI) Command: 0xC1 Device (Responds on MISO) Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission Command CRC: 0x94 Response: 0x94 (Expected Command CRC) Null: 0x00 Key Status Report Byte 0 Null: 0x00 Key Status Report Byte 1 Null: 0x00 Report CRC: 0x?? 4.1.5.1 Set Instructions Set Instructions are 2-byte transmissions by the host that are used to send settings to individual locations in the device memory map. At the first byte, the QT1111 returns 0x55 (“Idle”) to confirm that it will interpret the byte as a new command. At the second byte, the QT1111 returns the “Set” command it has just received. For example, to set the “Positive Recalibration Delay” to 1920 ms, address 5 in the memory map is set to 12 (0x0C). This is done with the “Set” command for address 5 (command code 0x95), as shown in Figure 4-5 on page 14. 13 9571A–AT42–02/10 Figure 4-5. Positive Recalibration Delay Set Instruction – CRC Disabled Host (Sends on MOSI) Command: 0x95 Device (Responds on MISO) Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission “Set” Data: 0x0C Response: 0x95 (Command Just Received) With CRC Enabled, a CRC byte is also required (Figure 4-6). This is calculated for the two transmitted bytes (that is, the “Set” command and the data byte). For example, for the sequence shown in Figure 4-5 (0x95 — 0x0C), the CRC Byte is 0x9F. As is the case with the other command types, when the QT1111 is expecting a CRC byte from the host, it calculates that byte in advance and returns the expected value to the host in the same transmission as the host sends the CRC byte. The sent data is not applied to the memory location until the CRC byte has been received and verified. Figure 4-6. Positive Recalibration Delay Set Instruction – CRC Enabled Host (Sends on MOSI) Command: 0x95 Device (Responds on MISO) Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission “Set” Data: 0x0C Response: 0x95 (Command Just Received) Command CRC: 0x9F Response: 0x9F (Expected CRC) 14 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 4.1.5.2 Get Instructions Get instructions are instructions that read the data from a location in the QT1111 memory map. Figure 4-7. Positive Recalibration Delay Get Instruction – CRC Disabled Host (Sends on MOSI) Command: 0xD5 Device (Responds on MISO) Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission Null: 0x00 “Get” Data: 0x0C (Positive Recalibration Delay) The host sends the appropriate “Get” command, followed by a “Null” byte. The QT1111 returns the contents of the addressed memory location. Figure 4-7 on page 15 shows the exchange for a report on the positive recalibration delay (assuming that the data byte is 0x0C). With CRC Enabled, this exchange takes 4 bytes, with a command CRC transmitted by the host and a report CRC returned by the QT1111 (see Figure 4-8). Figure 4-8. Positive Recalibration Delay Get Instruction – CRC Enabled Host (Sends on MOSI) Command: 0xD5 Device (Responds on MISO) Response: 0x55 (“Idle” – Fresh Command) Simultaneous Transmission Command CRC: 0x68 Response: 0x68 (Expected Command CRC) Null: 0x00 “Get” Data: 0x0C (Positive Recalibration Delay) Null: 0x00 “Get” CRC: 0xA3 15 9571A–AT42–02/10 4.1.6 4.1.6.1 Quick SPI Mode Introduction In Quick SPI Mode, the QT1111 sends a 7-byte key report at each exchange. No host commands are required over SPI in this mode; the host clocks the data bytes out in sequence. 4.1.6.2 Quick SPI Report The 7 report bytes are in the format given in Table 4-1. Table 4-1. Byte 0 1 2 3 4 5 6 Device Status Report Format Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Counter – increments from 0 to 255 Channel 3 Channel 7 Reserved Channel 3 Channel 7 Reserved Channel 2 Channel 6 Channel 10 Channel 2 Channel 6 Channel 10 Channel 1 Channel 5 Channel 9 Channel 1 Channel 5 Channel 9 Channel 0 Channel 4 Channel 8 Channel 0 Channel 4 Channel 8 Description Counter Detect status, channels 0 – 3 Detect status, channels 4 – 7 Detect status, channels 8 – 10 Error status, channels 0 – 3 Error status, channels 4 – 7 Error status, channels 8 – 10 where: • Byte 0 is a counter that increments from 0 to 254 on successive exchanges to confirm that firmware is operating correctly. • Bytes 1 – 3 indicate the detect status of channels 0 – 3, 4 – 7 and 8 – 10 respectively (two bits per channel), as follows: – 00 = Channel not in detect – 01 = Channel in detect – 10 = Not Allowed – 11 = Invalid Signal (Channel disabled) • Bytes 4 – 6 indicate the error status of channels 0 – 3, 4 – 7 and 8 – 10 respectively (two bits per channel), as follows: – 00 = No error – 01 = Not allowed – 10 = Error on channel – 11 = Invalid signal (channel disabled) 4.1.6.3 Commands in Quick SPI Mode Only two host commands are recognized under Quick SPI mode. These are shown in Table 4-2. Table 4-2. Command Store to EEPROM Enable Full SPI Host Commands in Quick SPI Mode Code 0x0A 0x36 Purpose Allows for “Quick SPI mode” to be stored as the default start-up mode Enables full SPI mode CRC checking is not implemented in Quick SPI mode for host commands or return data. 16 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 4.1.6.4 Quick SPI Mode timing In Quick SPI mode, the minimum time between byte exchanges is reduced to 100 µS. If a pause in communications of 100 ms is detected during reading of the 7-byte report, the QT1111 resets the exchange, and on the next byte read it returns byte 0 of the report. 4.2 Reset The QT1111 can be reset using one of two methods: • Hardware reset: An external reset logic line can be used if desired, fed into the RESET pin. However, under most conditions it is acceptable to tie RESET to Vdd. • Software reset: A software reset can be forced using the “Reset” control command. For both methods, the device will follow the same initialization sequence. If there any saved settings in the EEPROM, these are loaded into RAM. Otherwise the default settings are applied. Note: The SPI interface becomes active after the QT1111 has completed its startup sequence, taking approximately 320 ms after power on/reset. 4.3 Sleep Mode The QT1111 can be put into a very low power sleep mode (typically < 2 µA). During sleep mode, no keys are measured and the DETECT outputs are all put into high impedience mode to minimize current consumption. The device remains in sleep mode until a falling edge is detected on either the SS p in or the CHANGE p in. When the QT1111 wakes from sleep mode, it continues to operate as it was before it was put into sleep mode. The QT1111 requires approximately 100 µs to wake from sleep mode and will not respond correctly to SPI communications until the wake-up procedure is complete. The low level on the SS or CHANGE pin that is used to wake the device must be maintained for 100 µs to ensure correct operation. Note: If the device is set to sleep mode for an extended period, the host should initiate a recalibration immediately after waking the QT1111. 4.4 Calibration The device can be forced to recalibrate the sensor keys at any time. This can be useful where, for example, a portable device is plugged into mains power, or during product development when settings are being tuned. The QT1111 can also be configured to automatically recalibrate if it remains in detection for too long. This avoids keys becoming “stuck” after a prolonged period of uninterrupted detection. See Section 7.17 on page 37 for details. 4.5 CHANGE Pin The CHANGE pin can be configured using the Comms Options setup byte (see Section 7.5 on page 30) to act in one of two modes: • Data mode – The CHANGE pin is asserted (pulled low) when the detection status of a key changes from that last sent to the host; that is when a key-touch or key-release event occurs. – The CHANGE pin is pulled low when a key’s status changes and is only released when the “Send All keys” report is requested (0xC1), or the key status information bytes are read in Quick SPI mode (see Section 7.5 on page 30). 17 9571A–AT42–02/10 • Touch mode – The CHANGE pin is pulled low when one or more keys are in detect. The CHANGE pin remains low as long as there is a key in detect, regardless of communications. – The CHANGE pin is released when there are no keys in detect. No host communications are required to release the CHANGE pin. 4.6 Stand-alone Mode The QT1111 can operate in a stand-alone mode without the use of the SPI interface. The settings are loaded from EEPROM and the device operates in 7-key mode using the Detect outputs. 4.7 4.7.1 Key Modes 11-key Mode In 11-key mode, the device can sense up to 11 keys. Alternatively, one key can be replaced by the SYNC line as an external trigger input (see Section 4.8.2 on page 19). 11-key mode is configured by setting the “MODE” bit in the Device Mode setup byte (see Section 7.4 on page 29). Key acquisition can be triggered in one of two ways: using the internal clock to trigger acquisition either at a fixed repetition period or in a continuous “free run” mode (see Section 4.8.1), or using the SYNC pin to provide an external trigger (see Section 4.8.2 on page 19), 4.7.2 7-key Mode In 7-key mode, the detect outputs DETECT0 to DETECT6 become active on pins 22–27 and 30. These outputs provide configurable PWM signals that indicate when each of the keys is touched. 7-key mode is configured by clearing the “MODE” bit in the Device Mode setup byte (see Section 7.4 on page 29). Each DETECT output can be individually configured to output a PWM signal while the matching key is in detect or out of detect. This signal can be one of nine levels, ranging from low (PWM = 0 percent) to high (PWM = 100 percent). This allows for the use of an indicating LED. This is achieved by enabling the appropriate bit in the Key to LED setup byte (see Section 7.14 on page 35), and setting the desired outputs levels or PWMs in setup addresses 9 to 15 (see Section 7.12 on page 33). 4.8 4.8.1 Trigger Modes Timed Trigger In 11-key mode, The QT1111 can be configured to use the internal clock as a timed trigger. In this case, the QT1111 is configured with a cycle period, such that each acquisition cycle starts a specified length of time after the start of the previous cycle. If the cycle period is set to “0”, each acquisition cycle starts as soon as the previous one has finished, resulting in the acquisition cycles running back-to-back in a “free run” mode. The use of a timed trigger, and the cycle period to be used, is set in the Device Mode setup byte (see Section 7.4 on page 29). 18 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 4.8.2 Synchronized Trigger In 11-key mode, if a time trigger is not enabled, the QT1111 operates in “synchronized” mode. In this mode, SNS10K is used as a SYNC pin to trigger key acquisition, rather than using the device’s internal clock. In this case the maximum number of keys is reduced to 10. The SYNC pin can use one of two methods to trigger key measurements, selectable via bit 4 of the Device Mode setup byte (see Section 7.4 on page 29): Low Level and Rising Edge. With the Low Level method the QT1111 operates in “free run” mode for as long as the SYNC pin is read as a logical “0”. When the SYNC pin goes high, the current measurement cycle will be finished and no more key measurements will be taken until the SYNC pin goes low again. The low level trigger should be a minimum of 1 ms so that there is sufficient time for the device to detect the low level. With the Rising Edge method all enabled keys are measured once when a rising edge is detected on the SYNC pin. This allows key measurements to be synchronized to an external event or condition. For example, the SYNC pin can be used by the host to synchronize several devices to each other. This would ensure that only one of the devices outputs pulses at any given time and signals from one QT1111 do not interfere with the measurements from another. Another use for synchronizing to the rising edge is to steady the signals when the device is running off a mains transformer with insufficient mains frequency filtering that is causing a 50Hz or 60Hz ripple on Vdd. If the mains voltage is scaled down with a simple voltage divider and connected to the SYNC pin, then the key measurement can be triggered by the rising edge detected at a positive going zero-crossing. Note that in this case, each key signal will be taken at the same point in the cycle, so Vdd will be the same at each measurement for a given key and the signals will be steadier. 4.9 Guard Channel Option The device has a guard channel option (available in all key modes), which allows one key to be configured as a guard channel to help prevent false detection (see Figure 4-9 on page 20). Guard channel keys should be more sensitive than the other keys (physically bigger or larger Cs), subject to burst length limitations (see Section 4.11.2 on page 21). With guard channel enabled, the designated key is connected to a sensor pad which detects the presence of touch and overrides any output from the other keys using the chip’s AKS feature. The guard channel option is enabled by the Guard Key setup byte (see Section 7.5 on page 30). With the guard channel not enabled, all the keys work normally. Note: If a key is already “in detect” when the guard channel becomes active, that key will remain in detect and the guard key will not activate until the active key goes out of detect. 19 9571A–AT42–02/10 Figure 4-9. Guard Channel Example Key Pad Formed of Six Keys Guard Channel Formed of One Key 4.10 4.10.1 Self-test Functions Internal Hardware Tests Internal hardware tests check for hardware failure in the device’s internal memory areas and data paths. Any failure detected in the function or contents of application ROM, RAM or registers causes the device to reset itself. The application code is scanned with a CRC check routine to confirm that the application data is all correct. The RAM and registers are checked periodically (every 10 seconds) for dynamic and static failures. 4.10.2 Functional Checks Functional checks confirm that the device is operating within expected parameters; any failure detected in these tests is notified to the system host. The device will continue to operate in the event that such functional failures are detected. The functional tests are: • Check that the channel-measurement signals are within the defined range. • Confirm that data stored in the EEPROM is valid. These tests are carried out as the particular functions are used. For example, the EEPROM is checked when the device attempts to load data from EEPROM, and the channel signals are checked when a measurement is carried out. Note: If a particular channel is unused, the threshold of that channel should be set to 0 to prevent the incorrect reporting of the unused channel as being in an error state. 4.11 4.11.1 Signal Processing Detection Integrator The device features a detection integration mechanism, which acts to confirm a detection in a robust fashion. A per-key counter is incremented each time the key has exceeded its threshold. When this counter reaches a preset limit the key is finally declared to be touched. For example, if the DI limit is set to 10, then a key’s signal must fall by more than the key threshold, and remain below that level for 10 acquisitions, before the key is declared to be touched. Similarly, the DI is applied to a key that is going out of detect: it must take 10 acquisitions where the signal has not exceeded its detect threshold before it is declared to leave touch. 20 AT42QT1111-MU/AT42QT1111-AU 9571A–AT42–02/10 AT42QT1111-MU/AT42QT1111-AU 4.11.2 Burst Length Limitations The maximum burst length is 2048 pulses. The recommended design is to use a capacitor that gives a signal of