AT45DB321C

Features • Single 2.7 - 3.6V Supply • RapidS™ Serial Interface: 40 MHz Maximum Clock Frequency (SPI Modes 0 and 3 Compatible for Frequencies Up to 33 MHz) • Page Program • – 8192 Pages (528 Bytes/Page) Automated Erase Operations – Page Erase 528 Bytes – Block Erase 4,224 Bytes Two 528-byte SRAM Data Buffers – Allows Receiving of Data while Reprogramming the Flash Array Continuous Read Capability through Entire Array – Ideal for Code Shadowing Applications Low-power Dissipation – 10 mA Active Read Current Typical – 6 µA Standby Current Typical Hardware and Software Data Protection Features – Individual Sector Locking Security: 128-byte Security Register – 64-byte User Programmable Space – Unique 64-byte Device Identifier JEDEC Standard Manufacturer and Device ID Read 100,000 Program/Erase Cycles per Page Minimum Data Retention – 20 years Commercial and Industrial Temperature Ranges Green (Pb/Halide-free/RoHS Compliant) Packaging Options • • • 32-megabit 2.7 volt DataFlash® AT45DB321C • • • • • • • 1. Description The AT45DB321C is an SPI compatible, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and datastorage applications. The AT45DB321C supports a 4-wire serial interface known as RapidS for applications requiring very high speed operations. Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addition to the 33-megabit main memory, the AT45DB321C also contains two SRAM buffers of 528 bytes each. The buffers allow the receiving of data while a page in the main page Memory is being reprogrammed, as well as writing a continuous data stream. EEPROM emulation (bit or byte alterability) is easily handled with a self-contained three step read-modify-write operation. Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface, the DataFlash uses a RapidS serial interface to sequentially access its data. The simple sequential access dramatically reduces active pin count, facilitates hardware layout, increases system reliability, minimizes switching noise, and reduces package size. The device is optimized for use in many commercial and industrial applications where high-density, low-pin count, lowvoltage and low-power are essential. The device operates at clock frequencies up to 40 MHz with a typical active read current consumption of 10 mA. 3387L–DFLASH–6/06 To allow for simple in-system reprogrammability, the AT45DB321C does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321C is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK). All programming and erase cycles are self-timed. 2. Pin Configurations and Packages Table 2-1. Pin Name CS SCK SI SO WP RESET RDY/BUSY Pin Configurations Function Chip Select Serial Clock Serial Input Serial Output Hardware Page Write Protect Pin Chip Reset Ready/Busy Figure 2-1. RDY/BUSY RESET WP NC NC VCC GND NC NC NC CS SCK SI SO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 TSOP Top View – Type 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC NC NC NC NC NC NC NC NC NC NC NC NC Figure 2-2. 1 CBGA Top View through Package 2 3 4 5 Figure 2-3. GND NC NC CS SCK SI SO NC NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SOIC Top View 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC NC NC WP RESET RDY/BUSY NC NC NC NC NC NC NC NC A NC NC NC NC NC NC B NC SCK GND VCC CS RDY/BSY WP SO NC C NC D NC SI RESET NC NC NC NC E NC Figure 2-4. DataFlash Card(1) Top View through Package 7654321 Figure 2-5. SI SCK RESET CS 1 2 3 4 CASON – Top View through Package 8 7 6 5 SO GND VCC WP Note: 1. See AT45DCB004C Datasheet 2 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 3. Block Diagram WP FLASH MEMORY ARRAY PAGE (528 BYTES) BUFFER 1 (528 BYTES) BUFFER 2 (528 BYTES) SCK CS RESET VCC GND RDY/BUSY I/O INTERFACE SI SO 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB321C is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the block or page level. Figure 4-1. Memory Architecture Diagram BLOCK ARCHITECTURE SECTOR 0a BLOCK 0 BLOCK 1 SECTOR ARCHITECTURE SECTOR 0a = 8 Pages 4224 bytes (4K + 128) PAGE ARCHITECTURE 8 Pages PAGE 0 PAGE 1 SECTOR 0b = 504 Pages 266,112 bytes (252K + 8064) SECTOR 0b BLOCK 2 BLOCK 0 PAGE 6 PAGE 7 PAGE 8 BLOCK 62 BLOCK 63 SECTOR 1 = 512 Pages 270,336 bytes (256K + 8K) SECTOR 2 = 512 Pages 270,336 bytes (256K + 8K) SECTOR 1 BLOCK 65 BLOCK 1 BLOCK 64 PAGE 9 PAGE 14 PAGE 15 BLOCK 126 BLOCK 127 BLOCK 128 SECTOR 14 = 512 Pages 270,336 bytes (256K + 8K) BLOCK 129 PAGE 16 PAGE 17 PAGE 18 SECTOR 15 = 512 Pages 270,336 bytes (256K + 8K) PAGE 8189 BLOCK 1022 BLOCK 1023 PAGE 8190 PAGE 8191 Block = 4224 bytes (4K + 128) Page = 528 bytes (512 + 16) 3 3387L–DFLASH–6/06 5. Device Operation The device operation is controlled by instructions from the host processor. The list of instructions and their associated opcodes are contained in Tables 1 through 4. A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location. While the CS pin is low, toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input) pin. All instructions, addresses, and data are transferred with the most significant bit (MSB) first. Buffer addressing is referenced in the datasheet using the terminology BFA9-BFA0 to denote the 10 address bits required to designate a byte address within a buffer. Main memory addressing is referenced using the terminology PA12-PA0 and BA9-BA0, where PA12-PA0 denotes the 13 address bits required to designate a page address and BA9-BA0 denotes the 10 address bits required to designate a byte address within the page. 5.1 Read Commands By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocol for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode. 5.1.1 Continuous Array Read By supplying an initial starting address for the main memory array, the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal; no additional addressing information or control signals need to be provided. The DataFlash incorporates an internal address counter that will automatically increment on every clock cycle, allowing one continuous read operation without the need of additional address sequences. To perform a continuous read, an opcode of E8H must be clocked into the device. The opcode is followed by three address bytes (which comprises 24-bit page and byte address sequence) and 32 don’t care clock cycles. The first bit of the 24-bit address sequence is reserved for upward and downward compatibility to larger and smaller density devices (see the notes under Section 13.6 on page 25. The next 13 bits (PA12-PA0) of the 24-bit address sequence specify which page of the main memory array to read, and the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the starting byte address within the page. The 32 don’t care clock cycles that follow the four address bytes are needed to initialize the read operation. Following the don’t care clock cycles, additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page). When the last bit in the main memory array has been read, the device will continue reading back at the beginning of the first page of memory. As with crossing over page boundaries, no delays will be incurred when wrapping around from the end of the array to the beginning of the array. A low-to-high transition on the CS pin will terminate the read operation and tristate the output pin (SO). The maximum SCK frequency allowable for the Continuous Array Read is defined by the fCAR specification. The Continuous Array Read bypasses both data buffers and leaves the contents of the buffers unchanged. 4 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 5.1.2 Main Memory Page Read A main memory page read allows the user to read data directly from any one of the 8192 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read, an opcode of D2H must be clocked into the device. The opcode is followed by three address bytes (which comprise 24-bit page and byte address sequence) and 32 don’t care clock cycles. The first bit of the 24-bit address sequence is a reserved bit, the next 13 bits (PA12-PA0) of the 24-bit address sequence specify the page in main memory to be read, and the last 10 bits (BA9-BA0) of the 24-bit address sequence specify the starting byte address within that page. The 32 don’t care clock cycles that follow the three address bytes are sent to initialize the read operation. Following the don’t care bytes, additional pulses on SCK result in data being output on the SO (serial output) pin. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a page in main memory is reached, the device will continue reading back at the beginning of the same page. A low-to-high transition on the CS pin will terminate the read operation and tristate the output pin (SO). The maximum SCK frequency allowable for the Main Memory Page Read is defined by the fSCK specification. The Main Memory Page Read bypasses both data buffers and leaves the contents of the buffers unchanged. Buffer Read Data can be read from either one of the two buffers, using different opcodes to specify which buffer to read from. An opcode of D4H is used to read data from buffer 1, and an opcode of D6H is used to read data from buffer 2. To perform a buffer read, the opcode must be clocked into the device followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9-BFA0). Following the three address bytes, an additional don’t care byte must be clocked in to initialize the read operation. Since the buffer size is 528 bytes, 10 buffer address bits are required to specify the first byte of data to be read from the buffer. The CS pin must remain low during the loading of the opcode, the address bytes, the don’t care bytes, and the reading of data. When the end of a buffer is reached, the device will continue reading back at the beginning of the buffer. A low-to-high transition on the CS pin will terminate the read operation and tristate the output pin (SO). 5.1.3 5.2 5.2.1 Program and Erase Commands Buffer Write Data can be clocked in from the SI pin into either buffer 1 or buffer 2. To load data into either buffer, a 1-byte opcode, 84H for buffer 1 or 87H for buffer 2, must be clocked into the device, followed by three address bytes comprised of 14 don’t care bits and 10 buffer address bits (BFA9BFA0). The 10 buffer address bits specify the first byte in the buffer to be written. After the last address byte has been clocked into the device, data can then be clocked in on subsequent clock cycles. If the end of the data buffer is reached, the device will wrap around back to the beginning of the buffer. Data will continue to be loaded into the buffer until a low-to-high transition is detected on the CS pin. 5 3387L–DFLASH–6/06 5.2.2 Buffer to Main Memory Page Program with Built-in Erase: Data written into either buffer 1 or buffer 2 can be programmed into the main memory. To start the operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be clocked into the device followed by three address bytes consisting of one reserved bit, 13 page address bits (PA12-PA0) that specify the page in the main memory to be written and 10 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first erase the selected page in main memory (the erased state is a logic 1) and then program the data stored in the buffer into the specified page in main memory. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. Buffer to Main Memory Page Program without Built-in Erase A previously-erased page within main memory can be programmed with the contents of either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or 89H for buffer 2, must be clocked into the device followed by three address bytes consisting of one reserved bit, 13 page address bits (PA12-PA0) that specify the page in the main memory to be written and 10 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will program the data stored in the buffer into the specified page in the main memory. It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally selftimed and should take place in a maximum time of tP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. Page Erase The Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program without Built-in Erase command to be utilized at a later time. To perform a page erase, an opcode of 81H must be loaded into the device, followed by three address bytes comprised of one reserved bit, 13 page address bits (PA12-PA0) that specify the page in the main memory to be erased and 10 don’t care bits. When a low-tohigh transition occurs on the CS pin, the part will erase the selected page (the erased state is a logic 1). The erase operation is internally self-timed and should take place in a maximum time of tPE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. 5.2.3 5.2.4 5.2.5 Block Erase A block of eight pages can be erased at one time. This command is useful when large amounts of data has to be written into the device. This will avoid using multiple Page Erase Commands. To perform a block erase, an opcode of 50H must be loaded into the device, followed by three address bytes comprised of one reserved bit, 10 page address bits (PA12-PA3) and 13 don’t care bits. The 10 page address bits are used to specify which block of eight pages is to be erased. When a low-to-high transition occurs on the CS pin, the part will erase the selected block of eight pages. The erase operation is internally self-timed and should take place in a maximum time of tBE. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. 6 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C Table 5-1. PA12 0 0 0 0 • • • 1 1 1 1 Block Erase Addressing PA11 0 0 0 0 • • • 1 1 1 1 PA10 0 0 0 0 • • • 1 1 1 1 PA9 0 0 0 0 • • • 1 1 1 1 PA8 0 0 0 0 • • • 1 1 1 1 PA7 0 0 0 0 • • • 1 1 1 1 PA6 0 0 0 0 • • • 1 1 1 1 PA5 0 0 0 0 • • • 1 1 1 1 PA4 0 0 1 1 • • • 0 0 1 1 PA3 0 1 0 1 • • • 0 1 0 1 PA2 X X X X • • • X X X X PA1 X X X X • • • X X X X PA0 X X X X • • • X X X X Block 0 1 2 3 • • • 1020 1021 1022 1023 5.2.6 Main Memory Page Program Through Buffer This operation is a combination of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations. Data is first clocked into buffer 1 or buffer 2 from the input pin (SI) and then programmed into a specified page in the main memory. To initiate the operation, an 8-bit opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three address bytes. The address bytes are comprised of one reserved bit, 13 page address bits (PA12-PA0) that select the page in the main memory where data is to be written, and 10 buffer address bits (BFA9-BFA0) that select the first byte in the buffer to be written. After all address bytes are clocked in, the part will take data from the input pins and store it in the specified data buffer. If the end of the buffer is reached, the device will wrap around back to the beginning of the buffer. When there is a low-to-high transition on the CS pin, the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into that memory page. Both the erase and the programming of the page are internally self-timed and should take place in a maximum time of tEP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. 5.3 5.3.1 Additional Commands Main Memory Page to Buffer Transfer A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start the operation, a 1-byte opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes comprised of one reserved bit, 13 page address bits (PA12- PA0), which specify the page in main memory that is to be transferred, and 10 don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode and the address bytes from the input pin (SI). The transfer of the page of data from the main memory to the buffer will begin when the CS pin transitions from a low to a high state. During the transfer of a page of data (tXFR), the status register can be read to determine whether the transfer has been completed or not. 7 3387L–DFLASH–6/06 5.3.2 Main Memory Page to Buffer Compare A page of data in main memory can be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode, 60H for buffer 1 and 61H for buffer 2, must be followed by 24 address bits consisting of one reserved bit, 13 address bits (PA12 - PA0) which specify the page in the main memory that is to be compared to the buffer, and ten don’t care bits. The CS pin must be low while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits from the SI pin. On the low-to-high transition of the CS p in, the 528 bytes in the selected main memory page will be compared with the 528 bytes in buffer 1 or buffer 2. During this time (tXFR), the status register will indicate that the part is busy. On completion of the compare operation, bit 6 of the status register is updated with the result of the compare. Auto Page Rewrite This mode is only needed if multiple bytes within a page or multiple pages of data are modified in a random fashion. This mode is a combination of two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase. A page of data is first transferred from the main memory to buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed back into its original page of main memory. To start the rewrite operation, a 1-byte opcode, 58H for buffer 1 or 59H for buffer 2, must be clocked into the device, followed by three address bytes comprised of one reserved bit, 13 page address bits (PA12-PA0) that specify the page in main memory to be rewritten and 10 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory. The operation is internally self-timed and should take place in a maximum time of tEP. During this time, the status register and the RDY/BUSY pin will indicate that the part is busy. If a sector is programmed or reprogrammed sequentially page by page, then the programming algorithm shown in Figure 15-1 on page 31 is recommended. Otherwise, if multiple bytes in a page or several pages are programmed randomly in a sector, then the programming algorithm shown in Figure 15-2 on page 32 is recommended. Each page within a sector must be updated/rewritten at least once within every 10,000 cumulative page erase/program operations in that sector. 5.3.3 5.3.4 Status Register Read The status register can be used to determine the device’s ready/busy status, the result of a Main Memory Page to Buffer Compare operation, or whether the sector protection has been enabled. To read the status register, an opcode of D7H must be loaded into the device. After the opcode and optional dummy byte is clocked in, the 1-byte status register will be clocked out on the output pin (SO), starting with the next clock cycle. For applications over 25 MHz, the opcode must be always followed with a dummy (don’t care) byte. The data in the status register, starting with the MSB (bit 7), will be clocked out on the SO pin during the next eight clock cycles. The most-significant bits of the status register will contain device information, while the remaining least-significant bit is reversed for future use and will have undefined value. After the one byte of the status register has been clocked out, the sequence will repeat itself (as long as CS remains low and SCK is being toggled). The data in the status register is constantly updated, so each repeating sequence will output new data. Ready/busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the device is not busy and is ready to accept the next command. If bit 7 is a 0, then the device is in a busy state. There are many operations that can cause the device to be in a busy state: Main Memory Page to Buffer Transfer, Buffer to Main Memory Page Program with Built-in Erase, Buffer to 8 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C Main Memory Page Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page Program, and Auto Page Rewrite. Bit 1 in the Status Register is used to provide information to the user whether or not the sector protection has been enabled or disabled, either by software-controlled method or hardware-controlled method. A logic 1 indicates that sector protection has been enabled and logic 0 indicates that sector protection has been disabled. The device density is indicated using bits 5, 4, 3, and 2 of the status register. For the AT45DB321C, the four bits are 1,1, 0, 1. The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices. The device density is not the same as the density code indicated in the JEDEC device ID information. The device density is provided only for backward compatibility. The result of the most recent Main Memory Page to Buffer Compare operation is indicated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the main memory page does not match the data in the buffer. Table 5-2. Bit 7 RDY/BUSY Status Register Format Bit 6 COMP Bit 5 1 Bit 4 1 Bit 3 0 Bit 2 1 Bit 1 Protect Bit 0 X 6. Sector Protection Two protection methods, hardware and software controlled, are provided. The selection of which sectors to be protected/unprotected from program and erase operations is defined in the Sector Protection Register. 6.1 Software Sector Protection Sectors specified for protection in the Sector Protection Register can be protected from program and erase operations by issuing the Enable Sector Protection command. To enable the sector protection using the software controlled method, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte command sequence must be clocked in via the input pin (SI). After the last bit of the command sequence has been clocked in, the CS pin must be deasserted after which the sector protection will be enabled. Command Enable Sector Protection Disable Sector Protection Read Sector Protection Register Byte 1 3DH 3DH 32H Byte 2 2AH 2AH 00H Byte 3 7FH 7FH 00H Byte 4 A9H 9AH 00H To disable the sector protection using the software controlled method, the CS pin must first be asserted as it would be with any other command. Once the CS pin has been asserted, the appropriate 4-byte sequence for the Disable Sector Protection command must be clocked in via the input pin (SI). After the last bit of the command sequence has been clocked in, the CS pin must be deasserted after which the sector protection will be disabled. The Disable Sector Protection command is ignored while the WP pin is asserted. 9 3387L–DFLASH–6/06 Software Sector Protection is useful in applications in which the WP pin is not or cannot be controlled by a host processor. In such instances, the WP pin may be left floating (the WP pin is pulled high internally) and sector protection can be controlled using the software commands. If the device is power cycled, then the Software Sector Protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector protection is desired and if the WP pin is not used. The RESET pin has no effect on the Software Sector Protection. 6.2 Hardware Sector Protection Sectors specified for protection in Sector Protection Register can be protected from program and erase operations by utilizing the Write Protection (WP) pin. The protection can be enabled by asserting the WP pin and keeping the pin in its asserted state. Any sector specified for protection cannot be erased or reprogrammed as long as the WP pin is asserted. The protection can be disabled by deasserting the WP pin high. A filter is provided on the WP pin to help protect against spurious noise on the WP pin. Hardware Sector Protection will provide continuous protection, based on the contents of the Sector Protection Register, in an application where WP is always driven low. Please read “Write Protect (WP)” on page 15 for more information. 6.3 Sector Protection Register Sector Protection Register is a nonvolatile register that contains 16 bytes of data, as shown below: Sector Number Protected See Below Unprotected 00H 0 (0a, 0b) 1 to 15 FFH Table 6-1. Sector 0 (0a, 0b): 0a (Page 0-7) Bit 6, 7 Bit 4, 5 0b (Page 8-511) Bit 2, 3 Bit 0, 1 Data Value 00H C0H 3CH FCH Sectors 0a, 0b Unprotected Protect Sector 0a (Page 0-7) Protect Sector 0b (Page 8-511) Protect Sectors 0a, 0b (Page 0-511) Note: 00 11 00 11 00 00 11 11 00 00 11 11 00 00 00 00 1. Default value for devices shipped from Atmel is 00H. 10 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 6.3.1 Erasing the Sector Protection Register To erase the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, the 4-byte erase command sequence must be clocked in via the SI (serial input) pin. After the last bit of the command sequence has been clocked in, the CS pin must be deasserted to initiate the internally self-timed erase cycle (tPE). The Ready/Busy status will indicate that the device is busy during the erase cycle. The erased state of each bit (of a byte) in the Sector Protection Register indicates that the corresponding sector is flagged for protection. The RESET pin is disabled during this erase cycle to prevent incomplete erasure of the Sector Protection Register. Command Erase Sector Protection Register Byte 1 3DH Byte 2 2AH Byte 3 7FH Byte 4 CFH 6.3.2 Programming the Sector Protection Register To program the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, the 4-byte command sequence must be clocked in via the SI (serial input) pin. After the last bit of the command sequence has been clocked in, the data for the contents of the Sector Protection Register must be clocked in. The first byte corresponds to sector 0 (0a, 0b), the second byte corresponds to Sector 1 and the last byte (byte 16) corresponds to Sector 15. After the last bit of data has been clocked in, the CS pin must be deasserted to initiate the internally self-timed program cycle (tP). The Ready/Busy status will indicate that the device is busy during the program cycle. The RESET pin is disabled during this program cycle to prevent incomplete programming of the sector protection register. Command Program Sector Protection Register Byte 1 3DH Byte 2 2AH Byte 3 7FH Byte 4 FCH 6.3.3 Reading the Sector Protection Register To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, a 4-byte command sequence 32H, 00H, 00H, 00H and 32 don’t care clock cycles must be clocked in via the SI (serial input) pin. The 32 don’t care clock cycles are required to initialize the read operation. After the 32 don’t care clock cycles, any additional clock pulses on the SCK pin will result in data being output on the SO (serial output) pin. The read will begin with Byte_1 of the Sector Protection Register for Sector_0, followed with Byte_2 for Sector_1. The read operation will continue until Byte_16 for Sector_15 is read. Once the last byte is read a lowto-high transition on the CS pin is required to terminate the read operation. Command Read Sector Protection Register Note: Byte 1 32H Byte 2 00H Byte 3 00H Byte 4 00H Next generation devices of the “D” family will not require the 32 don’t care clock cycles. 11 3387L–DFLASH–6/06 6.3.4 Various Aspects About the Sector Protection Register Due to the sharing of the internal circuitry, the contents of the buffer 1 will get modified during the erase and programming of Sector Protection Register. If the device is powered down during erasing or programming the sector protection register, then the contents of the Sector Protection Register cannot be guaranteed. The Sector Protection Register can be erased or reprogrammed with the sector protection enabled or disabled. Being able to reprogram the Sector Protection Register with the sector protection enabled allows the user to temporarily disable the sector protection to an individual sector rather than disabling the sector protection completely. The Sector Protection Register is subject to the same endurance characteristics as the main memory array. Users are encouraged to carefully evaluate the number of times the Sector Protection Register will be modified during the course of the applications’ life cycle. If the application requires that the Sector Protection Register be modified more than the specified endurance of the DataFlash because the application needs to temporarily unprotect individual sectors (sector protection remains enabled while the Sector Protection Register is reprogrammed), then the application will need to limit this practice. Instead, a combination of temporarily unprotecting individual sectors along with disabling sector protection completely will need to be implemented by the application to ensure that the endurance limits of the device are not exceeded. 12 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 7. Manufacturer and Device ID Read This instruction conforms to the JEDEC standard and allows the user to read the Manufacturer ID, Device ID, and Extended Device Information. A 1-byte opcode, 9FH, must be clocked into the device while the CS pin is low. After the opcode is clocked in, the Manufacturer ID, 2 bytes of Device ID and Extended Device Information will be clocked out on the SO pin. The fourth byte of the sequence output is the Extended Device Information String Length byte. This byte is used to signify how many bytes of Extended Device Information will be output. 7.1 7.1.1 Hex Value 1FH Manufacturer and Device ID Information Byte 1 – Manufacturer ID JEDEC Assigned Code Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 1 Bit 3 1 Bit 2 1 Bit 1 1 Bit 0 1 Manufacturer ID 1FH = Atmel 7.1.2 Hex Value 27H Byte 2 – Device ID (Part 1) Family Code Bit 7 0 Bit 6 0 Bit 5 1 Bit 4 0 Density Code Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 1 Family Code Density Code 001 = DataFlash 00111 = 32-Mbit 7.1.3 Hex Value 00H Byte 3 – Device ID (Part 2) MLC Code Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Product Version Code Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 MLC Code Product Version 000 = 1-bit/Cell Technology 00000 = Initial Version 7.1.4 Hex Value 00H Byte 4 – Extended Device Information String Length Byte Count Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0 Byte Count 00H = 0 Bytes of Information CS SI 9FH Opcode SO 1FH Manufacturer ID Byte n 27H Device ID Byte 1 00H Device ID Byte 2 00H Extended Device Information String Length Data Extended Device Information Byte x Data Extended Device Information Byte x + 1 Each transition represents 8 bits and 8 clock cycles This information would only be output if the Extended Device Information String Length value was something other than 00H. Note: Based on JEDEC publication 106 (JEP106), Manufacturer ID data can be comprised of any number of bytes. Some manufacturers may have Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. 13 3387L–DFLASH–6/06 7.2 Security Register The AT45DB321C contains a specialized register that can be used for security purposes in system design. The Security Register is a unique 128-byte register that is divided into two portions. The first 64 bytes (byte 0 to byte 63) of this page are allocated as a one-time user programmable space. Once these 64 bytes have been programmed, they should not be reprogrammed. The remaining 64 bytes of this page (byte 64 to byte 127) are factory programmed by Atmel and will contain a unique number for each device. The factory programmed data is fixed and cannot be changed. The Security Register can be read by clocking in a 4-byte sequence 77H, 00H, 00H, 00H to the device followed by 32 don’t care clock cycles. See the opcode Table 9-4 on page 20. Note: Next generation devices of the “D” family will not require the 32 don’t care clock cycles. To program the first 64 bytes of the Security Register, a two step sequence must be used. The first step requires that the user loads the desired data into Buffer 1 by using the Buffer 1 Write operation (opcode 84H – “Buffer Write” on page 5). The user should specify the starting buffer address as location zero and should write a full 64 bytes of information into the buffer. Otherwise, the first 64 bytes of the buffer may contain data that was previously stored in the buffer. It is not necessary to fill the remaining 464 bytes (byte locations 64 through 527) of the buffer with data. After the Buffer 1 Write operation has been completed, the Security Register can be subsequently programmed by reselecting the device and clocking in opcode 9AH into the device followed by three don’t care bytes (24 clock cycles). After the final don’t care clock cycle has been completed, a low-to-high transition on the CS pin will cause the device to initiate an internally self-timed program operation in which the contents of Buffer 1 will be programmed into the Security Register. Only the first 64 bytes of data in Buffer 1 will be programmed into the Security Register; the remaining 464 bytes of the buffer will be ignored. The Security Register program operation should take place in a maximum time of tP. 7.3 Operation Mode Summary The modes described can be separated into two groups – modes that make use of the Flash memory array (Group A) and modes that do not make use of the Flash memory array (Group B). Group A modes consist of: 1. Main Memory Page Read 2. Continuous Array Read 3. Main Memory Page to Buffer 1 (or 2) Transfer 4. Main Memory Page to Buffer 1 (or 2) Compare 5. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase 6. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase 7. Main Memory Page Program through Buffer 1 (or 2) 8. Page Erase 9. Block Erase 10. Auto Page Rewrite Group B modes consist of: 1. Buffer 1 (or 2) Read 2. Buffer 1 (or 2) Write 3. Status Register Read 4. Manufacturer and Device ID Read 14 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C If a Group A mode is in progress (not fully completed), then another mode in Group A should not be started. However, during this time in which a Group A mode is in progress, modes in Group B can be started, except the first two Group A commands (Memory Array Read Commands). This gives the DataFlash the ability to virtually accommodate a continuous data stream. While data is being programmed into main memory from buffer 1, data can be loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. 7.4 7.4.1 Pin Descriptions Serial Input (SI) The SI pin is an input-only pin and is used to shift data serially into the device. The SI pin is used for all data input, including opcodes and address sequences. Serial Output (SO) The SO pin is an output-only pin and is used to shift data serially out from the device. Serial Clock (SCK) The SCK pin is an input-only pin and is used to control the flow of data to and from the DataFlash. Data is always clocked into the device on the rising edge of SCK and clocked out of the device on the falling edge of SCK. Chip Select (CS) The DataFlash is selected when the CS pin is low. When the device is not selected, data will not be accepted on the input pin (SI), and the output pin (SO) will remain in a high impedance state. A high-to-low transition on the CS pin is required to start an operation, and a low-to-high transition on the CS pin is required to end an operation or to start an internally self-timed operation. Write Protect (WP) The WP pin is used to control the Hardware Sector Protection. Hardware Sector Protection is enabled by asserting the WP pin and keeping the pin in it’s asserted state. Disabling Hardware Sector Protection is accomplished by simply deasserting the WP pin. The WP pin will override the software controlled sector protection method but only for protecting the sectors. For example, if the sectors were not previously protected by the Enable Sector Protection command, then simply asserting the WP pin for the minimum specified time (tWPE) would enable the sector protection. When the WP pin is deasserted; however, the sector protection would no longer be enabled as long as the Enable Sector Protection command was not issued while the WP pin was asserted. If the Enable Sector Protection command was issued before or while the WP pin was asserted, then simply deasserting the WP pin would not disable the sector protection. In this case, the Disable Sector Protection command would need to be issued while the WP pin is deasserted to disable the sector protection. The Disable Sector Protection command is also ignored whenever the WP pin is asserted. To ensure backwards compatibility with previous generations of DataFlash, the function of the WP pin has not changed. Therefore, when the WP pin is asserted, certain sectors in the memory array will be protected, and when the WP pin is deasserted, the memory array will be unprotected provided the Enable Sector Protection command hasn’t been issued. New devices are shipped from Atmel with the contents of the Sector Protection Register pre-programmed with “00H” (unprotect). The user can reprogram the Sector Protection Register to change which sectors will be protected by the WP pin. 7.4.2 7.4.3 7.4.4 7.4.5 15 3387L–DFLASH–6/06 The table below details the sector protection status for various scenarios of the WP pin, the Enable Sector Protection command, and the Disable Sector Protection command. 1 WP 2 3 Time Period WP Pin High Enable Sector Protection Command Command Not Issued Previously Command Issued – x Command Issued during Period 1 or 2 – Issue Command Disable Sector Protection Command x – Command Issued x Not Issued Yet Command Issued – Sector Protection Status Disabled Enabled Disabled Enabled Enabled Disabled Enabled 1 High High 2 Low High 3 High High 7.4.6 RESET A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level. The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. The RESET pin is also internally pulled high; therefore, in low pin count applications, connection of the RESET pin is not necessary if this pin and feature will not be utilized. However, it is recommended that the RESET p in be driven high externally whenever possible. 7.4.7 READY/BUSY This open drain output pin will be driven low when the device is busy in an internally self-timed operation. This pin, which is normally in a high state (through an external pull-up resistor), will be pulled low during programming/erase operations, and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. During Page Erase and Block Erase, read and write operations can be performed to both buffers. 16 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 8. Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the device will default to Mode 3. In addition, the output pin (SO) will be in a high impedance state, and a high-to-low transition on the CS pin will be required to start a valid instruction. The mode (Mode 3 or Mode 0) will be automatically selected on every falling edge of CS by sampling the inactive clock state. After power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms before an operational mode (DataFlash) is started. 9. System Considerations The RapidS serial interface is controlled by the serial clock SCK, serial input SI and chip select CS pins. These signals must rise and fall monotonically and be free from noise. Excessive noise or ringing on these pins can be misinterpreted as multiple edges and cause improper operation of the device. The PC board traces must be kept to a minimum distance or appropriately terminated to ensure proper operation. If necessary, decoupling capacitors can be added on these pins to provide filtering against noise glitches. As system complexity continues to increase, voltage regulation is becoming more important. A key element of any voltage regulation scheme is its current sourcing capability. Like all Flash memories, the peak current for DataFlash occur during the programming and erase operation. The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during programming or erase can lead to improper operation and possible data corruption. For applications that require random modifications of data within a sector, please refer to “Auto Page Rewrite” on page 8. Atmel C generation DataFlash utilizes a sophisticated adaptive algorithm during erase and programming to maximize the endurance over the life of the device. The algorithm uses a verification mechanism to check if the memory cells have been erased or programmed successfully. If the memory cells were not erased or programmed completely, the algorithm erases or programs the memory cells again. The process will continue until the device is erased or programmed successfully. In order to optimize the erase and programming time, fixed timing should not be used. Instead, the RDY/BUSY b it of the status register or the RDY/BUSY p in should be monitored. 17 3387L–DFLASH–6/06 Table 9-1. Command Read Commands SCK Mode RapidS Mode 0 or 3 Opcode E8H 68H D2H 52H D4H 54H D6H 56H D7H 57H 9FH Continuous Array Read Inactive Clock Polarity Low or High RapidS Mode 0 or 3 Main Memory Page Read Inactive Clock Polarity Low or High RapidS Mode 0 or 3 Buffer 1 Read Inactive Clock Polarity Low or High RapidS Mode 0 or 3 Buffer 2 Read Inactive Clock Polarity Low or High RapidS Mode 0 or 3 Status Register Read Inactive Clock Polarity Low or High Manufacturer and Device ID Note: RapidS Mode 0 or 3 1. Legacy Opcodes 52H, 54H, 56H, 57H, and 68H are still supported for reasons of backward compatibility only and are not recommended for new designs. The inactive clock polarity high or low modes will not be supported in the future products. Table 9-2. Command Buffer 1 Write Buffer 2 Write Program and Erase Commands SCK Mode Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Opcode 84H 87H 83H 86H 88H 89H 81H 50H 82H 85H Buffer 1 to Main Memory Page Program with Built-in Erase Buffer 2 to Main Memory Page Program with Built-in Erase Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 18 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C Table 9-3. Command Main Memory Page to Buffer 1 Transfer Main Memory Page to Buffer 2 Transfer Main Memory Page to Buffer 1 Compare Main Memory Page to Buffer 2 Compare Auto Page Rewrite Through Buffer 1 Auto Page Rewrite Through Buffer 2 Security Register Program Security Register Read Notes: (2) (1) (1) Additional Commands SCK Mode Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Mode 0, Mode 3 Opcode 53H 55H 60H 61H 58H 59H 9AH 77H 1. This command should be used for applications requiring a high number of random page writes within a sector. See “Auto Page Rewrite” on page 8. 2. The Security Register Program command utilizes data stored in Buffer 1. Therefore, this command must be used in conjunction with the Buffer 1 write command. See “Security Register” on page 14 for details. 19 3387L–DFLASH–6/06 Table 9-4. Detailed Bit-level Addressing Sequence Address Byte Reserved Address Byte Address Byte Additional Don’t Care Bytes Required N/A 4 Bytes N/A 1 Byte N/A 1 Byte N/A x x x x B 0 x B x B B x B x x x x x x x B 0 x B x B B x B x x x x x x x B 0 x B x B B x B x x x N/A N/A N/A N/A 4 Bytes 4 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A B B B B B B B B B 4 1 1 1/0 B B B 4 PA12 PA11 PA10 BA7 BA6 BA5 BA1 x B x B x B Opcode 50H 52H 53H 54H 55H 56H 57H 58H 59H 60H 61H 68H 77H 81H 82H 83H 84H 85H 86H 87H 88H 89H 9AH 9FH D2H D4H D6H D7H E8H Opcode 01010000 01010010 01010011 01010100 01010101 01010110 01010111 01011000 01011001 01100000 01100001 01101000 01110111 10000001 10000010 10000011 10000100 10000101 10000110 10000111 10001000 10001001 10011010 10011111 11010010 11010100 11010110 11010111 11101000 r r r x r x P P P x P x P P P x P x P P P x P x P P P x P x P P P x P x P P P x P x P P P x P x P P P x P x P P P x P x P P P x P x x P P x P x x P P x P x x P P x P x x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B x B N/A r r r r r 0 r r r x r r x r r x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x N/A P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x P P P P P 0 P P P x P P x P P x x x x x B 0 x B x B B x B x x x x x x x B 0 x B x B B x B x x x x x x x B 0 x B x B B x B x x x x x x x B 0 x B x B B x B x x x x x x x B 0 x B x B B x B x x x N/A x x x x B 0 x B x B B x B x x x x x x x B 0 x B x B B x B x x x N/A r x x P x x P x x P x x P x x P x x P x x P x x P x x P x x P x x N/A P x x P x x P x x B B B B B B B B B B B B B B B N/A B B B B B B N/A r P P P P P P P P P P N/A P P P B B B B B N/A B B Note: r = Reserved Bit, P = Page Address Bit, B = Byte/Buffer Address Bit, x = Don’t Care 20 AT45DB321C 3387L–DFLASH–6/06 BA0 x B x B x B BA9 BA8 BA4 BA3 BA2 PA8 PA7 PA6 PA5 PA2 PA1 PA9 PA4 PA3 PA0 AT45DB321C 10. Electrical Specifications Table 10-1. Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Temperature under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Table 10-2. DC and AC Operating Range AT45DB321C Com. 0°C to 70°C -40°C to 85°C 2.7V to 3.6V Operating Temperature (Case) Ind. VCC Power Supply Note: (1) 1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an operational mode is started. Table 10-3. Symbol ISB(1) ICC1(2)(3) ICC2 ICC3 ICC4 ILI ILO VIL VIH VOL VOH Notes: DC Characteristics Parameter Standby Current Active Current, Read Operation, Serial Interface Active Current, Program Operation, Page Program Active Current, Page Erase Operation Active Current, Block Erase Operation Input Load Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA; VCC = 2.7V IOH = -100 µA VCC - 0.2V VCC x 0.7 0.4 Condition CS, RESET, WP = VIH, all inputs at CMOS levels f = 20 MHz; IOUT = 0 mA; VCC = 3.6V VCC = 3.6V VCC = 3.6V VCC = 3.6V VIN = CMOS levels VI/O = CMOS levels Min Typ 6 10 35 30 30 Max 15 15 50 40 40 1 1 VCC x 0.3 Units µA mA mA mA mA µA µA V V V V 1. ISB maximum specification limit is tested at 3.3V and 70°C. 2. ICC1 during a buffer read is 30 mA maximum. 3. ICC1 changes typically by 300 µA per 1 MHz change in clock frequency. 4. All inputs are 5 volts tolerant. 21 3387L–DFLASH–6/06 Table 10-4. Symbol fSCK(1) fCAR tWH tWL tCS tCSS tCSH tCSB tSU tH tHO tDIS tV tXFR tEP(2)(3) tP(2)(3) tPE(2)(3) tBE(2)(3) tRST tREC tWPE tWPD Note: (1) AC Characteristics – Serial Interface Parameter SCK Frequency SCK Frequency for Continuous Array Read SCK High Time SCK Low Time Minimum CS High Time CS Setup Time CS Hold Time CS High to RDY/BUSY Low Data In Setup Time Data In Hold Time Output Hold Time Output Disable Time Output Valid Page to Buffer Transfer/Compare Time Page Erase and Programming Time Page Programming Time Page Erase Time Block Erase Time RESET Pulse Width RESET Recovery Time WP Low to Protection Enabled WP High to Protection Disabled 1 1 10 1 16 8 8 20 3 6 0 10 12 350 50 15 35 100 10 10 250 100 250 150 Min Typ Max 40 40 Units MHz MHz ns ns ns ns ns ns ns ns ns ns ns µs ms ms ms ms µs µs µs µs 1. Maximum specified frequency for SPI compatibility is 33 MHz. 2. The device uses an adaptive algorithm during program and erase operations. Use the RDY/BUSY bit of the status register or the RDY/BUSY pin to determine whether the program or erase operation has completed. Fixed timing should not be used. 3. Value are based on device characterization, not 100% tested in production. 22 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 11. Input Test Waveforms and Measurement Levels AC DRIVING LEVELS 3.0V 1.5V AC MEASUREMENT LEVEL 0V tR, tF < 2 ns (10% to 90%) 12. Output Test Load DEVICE UNDER TEST 30 pF 13. AC Waveforms Four different timing waveforms are shown below. Waveform 1 shows the SCK signal being low when CS makes a high-to-low transition, and waveform 2 shows the SCK signal being high when CS makes a high-to-low transition. In both cases, output SO becomes valid while the SCK signal is still low (SCK low time is specified as tWL). Timing waveforms 1 and 2 conform to RapidS serial interface but for frequencies up to 33 MHz and are compatible with SPI Mode 0 and SPI Mode 3 respectively. Waveforms 1 and 2 are also compatible with inactive clock polarity low and inactive clock polarity high, since the maximum specified frequency in that case is 33 MHz. Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and waveform 2, except that output SO is not restricted to become valid during the tWL period. These timing waveforms are valid over the full frequency range (maximum frequency = 40 MHz) of the RapidS serial case. 13.1 Waveform 1 – SPI Mode 0 Compatible (for Frequencies up to 33 MHz) tCS CS tCSS SCK tV SO HIGH IMPEDANCE tSU SI VALID IN tH tHO VALID OUT tDIS HIGH IMPEDANCE tWH tWL tCSH 23 3387L–DFLASH–6/06 13.2 Waveform 2 – SPI Mode 3 Compatible (for Frequencies up to 33 MHz) tCS CS tCSS SCK tV SO HIGH Z tSU SI VALID IN tHO VALID OUT tH tDIS HIGH IMPEDANCE tWL tWH tCSH 13.3 Waveform 3 – RapidS Mode 0 (for all Frequencies) tCS CS tCSS SCK tWH tWL tCSH tV SO HIGH IMPEDANCE tHO VALID OUT tDIS HIGH IMPEDANCE tSU SI VALID IN tH 13.4 Waveform 4 – RapidS Mode 3 (for all Frequencies) tCS CS tCSS SCK tWL tWH tCSH tV SO HIGH Z tHO VALID OUT tDIS HIGH IMPEDANCE tSU SI VALID IN tH 24 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 13.5 Reset Timing CS tREC tCSS SCK tRST RESET HIGH IMPEDANCE HIGH IMPEDANCE SO SI Note: The CS signal should be in the high state before the RESET signal is deasserted. 13.6 Command Sequence for Read/Write Operations (except Status Register Read) SI CMD 8 bits 8 bits 8 bits MSB r X X X XXXX Reserved for larger densities XXXX XXXX XXXX XXXX LSB Page Address (PA12-PA0) Byte/Buffer Address (BA9-BA0/BFA9-BFA0) Notes: 1. “r” designates bits reserved for larger densities. 2. It is recommended that “r” be a logical “0” for densities of 32M bits or smaller. 3. For densities larger than 32M bits, the “r” bit becomes the most significant Page Address bit for the appropriate density. 25 3387L–DFLASH–6/06 14. Write Operations The following block diagram and waveforms illustrate the various write sequences available. FLASH MEMORY ARRAY PAGE (528 BYTES) BUFFER 1 TO MAIN MEMORY PAGE PROGRAM MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 2 BUFFER 2 TO MAIN MEMORY PAGE PROGRAM BUFFER 1 (528 BYTES) BUFFER 1 WRITE MAIN MEMORY PAGE PROGRAM THROUGH BUFFER 1 BUFFER 2 (528 BYTES) BUFFER 2 WRITE I/O INTERFACE SI 14.1 Main Memory Page Program through Buffers · Completes writing into selected buffer · Starts self-timed erase/program operation CS SI CMD r, PA12-6 PA5-0, BFA9-8 BFA7-0 n n+1 Last Byte 14.2 Buffer Write · Completes writing into selected buffer CS SI CMD X X···X, BFA9-8 BFA7-0 n n+1 Last Byte 14.3 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page) Starts self-timed erase/program operation CS SI CMD r , PA12-6 PA5-0, XX X Each transition represents 8 bits and 8 clock cycles n = 1st byte write n+1 = 2nd byte write 26 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 15. Read Operations The following block diagram and waveforms illustrate the various read sequences available. FLASH MEMORY ARRAY PAGE (528 BYTES) MAIN MEMORY PAGE TO BUFFER 1 MAIN MEMORY PAGE TO BUFFER 2 BUFFER 1 (528 BYTES) BUFFER 1 READ BUFFER 2 (528 BYTES) MAIN MEMORY PAGE READ BUFFER 2 READ I/O INTERFACE SO 15.1 CS SI SO Main Memory Page Read CMD r , PA12-6 PA5-0, BA9-8 BA7-0 X X X X n n+1 15.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer) Starts reading page data into buffer CS SI SO CMD r , PA12-6 PA5-0, XX X 15.3 Buffer Read CS SI SO CMD X X···X, BFA9-8 BFA7-0 X n n+1 Each transition represents 8 bits and 8 clock cycles n = 1st byte read n+1 = 2nd byte read 27 3387L–DFLASH–6/06 15.4 15.4.1 Detailed Bit-level Read Timing – RapidS Serial Interface Mode 0 Continuous Array Read (Opcode: E8H) CS SCK 1 2 62 63 64 65 66 67 tSU SI 1 1 X X X tV SO HIGH IMPEDANCE DATA OUT D7 D6 D5 D2 D1 LSB D0 MSB D7 D6 D5 BIT 4223 OF PAGE n BIT 0 OF PAGE n+1 15.4.2 CS Main Memory Page Read (Opcode: D2H) SCK tSU SI 1 2 3 4 5 60 61 62 63 64 65 66 67 COMMAND OPCODE 1 1 0 1 0 X X X X X tV SO HIGH IMPEDANCE D7 MSB DATA OUT D6 D5 D4 15.4.3 Buffer Read (Opcode: D4H or D6H) CS SCK tSU SI 1 2 3 4 5 36 37 38 39 40 41 42 43 COMMAND OPCODE 1 1 0 1 0 X X X X X tV SO HIGH IMPEDANCE D7 MSB DATA OUT D6 D5 D4 28 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 15.4.4 CS Status Register Read (Opcode: D7H) SCK tSU SI 1 2 3 4 5 6 7 8 9 10 11 12 15 16 COMMAND OPCODE 1 1 0 1 0 1 1 1 tV SO HIGH IMPEDANCE D7 MSB tV STATUS REGISTER OUTPUT D6 D5 D4 D1 D0 LSB D7 MSB DON’T CARE BYTE FOR FREQ. OVER 25 MHz 15.4.5 CS Manufacturer and Device ID Read (Opcode: 9FH) SCK tSU SI 1 2 3 4 5 6 7 8 9 10 11 12 16 17 18 COMMAND OPCODE 1 00 1 1 1 1 1 tV SO HIGH IMPEDANCE 0 MSB 0 PRODUCT ID OUTPUT 0 1 1 LSB 0 MSB 0 MANUFACTURER ID 15.5 15.5.1 Detailed Bit-level Read Timing – RapidS Serial Interface Mode 3 Continuous Array Read (Opcode: E8H) CS SCK 1 2 63 64 65 66 67 tSU SI 1 1 X X X tV SO HIGH IMPEDANCE DATA OUT D7 D6 D5 D2 D1 LSB D0 MSB D7 D6 D5 BIT 4223 OF PAGE n BIT 0 OF PAGE n+1 29 3387L–DFLASH–6/06 15.5.2 Main Memory Page Read (Opcode: D2H) CS SCK tSU SI 1 2 3 4 5 61 62 63 64 65 66 67 68 COMMAND OPCODE 1 1 0 1 0 X X X X X tV SO HIGH IMPEDANCE D7 MSB DATA OUT D6 D5 D4 15.5.3 Buffer Read (Opcode: D4H or D6H) CS SCK tSU SI 1 2 3 4 5 37 38 39 40 41 42 43 44 COMMAND OPCODE 1 1 0 1 0 X X X X X tV SO HIGH IMPEDANCE D7 MSB DATA OUT D6 D5 D4 15.5.4 CS Status Register Read (Opcode: D7H) SCK tSU SI 1 2 3 4 5 6 7 8 9 10 11 12 17 18 COMMAND OPCODE 1 1 0 1 0 1 1 1 tV SO HIGH IMPEDANCE tV STATUS REGISTER OUTPUT D7 MSB D6 D5 D4 D0 LSB D7 MSB D6 DON’T CARE BYTE FOR FREQ. OVER 25 MHz 30 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 15.5.5 CS Manufacturer and Device ID Read (Opcode: 9FH) SCK tSU SI 1 2 3 4 5 6 7 8 9 10 11 12 17 18 COMMAND OPCODE 1 0 0 1 1 1 1 1 tV SO HIGH IMPEDANCE 0 MSB 0 PRODUCT ID OUTPUT 0 1 1 LSB 0 MSB 0 MANUFACTURER ID 15.6 Auto Page Rewrite Flowchart Figure 15-1. Algorithm for Programming or Reprogramming of the Entire Array Sequentially START provide address and data BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) END Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-bypage. 2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 31 3387L–DFLASH–6/06 Figure 15-2. Algorithm for Randomly Modifying Data START provide address of page to modify MAIN MEMORY PAGE TO BUFFER TRANSFER (53H, 55H) If planning to modify multiple bytes currently stored within a page of the Flash array BUFFER WRITE (84H, 87H) MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) BUFFER TO MAIN MEMORY PAGE PROGRAM (83H, 86H) AUTO PAGE REWRITE (58H, 59H) (2) INCREMENT PAGE (2) ADDRESS POINTER END Notes: 1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000 cumulative page erase and program operations. 2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command must use the address specified by the Page Address Pointer. 3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. 32 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 16. Sector Addressing PA12 0 0 0 0 • • • 1 1 1 1 PA11 0 0 0 0 • • • 1 1 1 1 PA10 0 0 0 1 • • • 0 0 1 1 PA9 0 0 1 0 • • • 0 1 0 1 PA8 0 X X X • • • X X X X PA7 0 X X X • • • X X X X PA6 0 X X X • • • X X X X PA5 0 X X X • • • X X X X PA4 0 X X X • • • X X X X PA3 0 X X X • • • X X X X PA2 - PA0 X X X X • • • X X X X Sector 0a 0b 1 2 • • • 12 13 14 15 33 3387L–DFLASH–6/06 17. Ordering Information fSCK (MHz) 40 ICC (mA) Active 15 Standby 0.015 Ordering Code AT45DB321C-CC AT45DB321C-CNC AT45DB321C-TC AT45DB321C-CI AT45DB321C-TI Package 24C3 8CN3 28T 24C3 28T Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) 40 15 0.015 18. Green Package Options (Pb /Halide-free/RoHS Compliant) fSCK (MHz) 40 ICC (mA) Active 15 Standby 0.015 Ordering Code AT45DB321C-CU AT45DB321C-CNU AT45DB321C-TU Package 24C3 8CN3 28T Operation Range Industrial (-40°C to 85°C) 19. Legacy Package Options(1) fSCK (MHz) 40 40 Note: ICC (mA) Active 15 15 Standby 0.015 0.015 Ordering Code AT45DB321C-RC AT45DB321C-RU Package 28R 28R Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) 1. Not recommended for new designs. Package Type 24C3 8CN3 28T 28R 24-ball (5 x 5 Array), 1.0 mm Pitch, 6 x 8 x 1.2 mm, Plastic Chip-scale Ball Grid Array (CBGA) 8-pad (6 mm x 8 mm) Chip Array Small Outline No Lead Package (CASON) 28-lead, Plastic Thin Small Outline Package (TSOP) 28-lead, 0.330” Wide, Plastic Gull Wing Small Outline Package (SOIC) 34 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 20. Packaging Information 20.1 24C3 – CBGA E A1 Ball ID D Top View A 1.00 REF A1 E1 e A1 Ball Corner 2.00 REF Side View A B C D E e D1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL E E1 D D1 A A1 – 0.25 7.90 MIN 5.90 NOM 6.00 4.0 TYP 8.00 4.0 TYP – – 1.00 BSC 0.40 TYP 1.20 – 8.10 MAX 6.10 NOTE 5 4 3 Øb 2 1 Bottom View e b 9/10/04 2325 Orchard Parkway San Jose, CA 95131 TITLE 24C3, 24-ball (5 x 5 Array), 1.0 mm Pitch, 6 x 8 x 1.20 mm, Chip-scale Ball Grid Array Package (CBGA) DRAWING NO. 24C3 REV. A R 35 3387L–DFLASH–6/06 20.2 8CN3 – CASON Marked Pin1 Indentifier E D Top View A A1 Side View Pin1 Pad Corner 0.10 mm TYP L1 8 1 e 7 2 COMMON DIMENSIONS (Unit of Measure = mm) 6 3 b 5 4 SYMBOL A A1 b D MIN NOM MAX 1.0 NOTE 0.17 0.21 0.41 TYP 0.25 4 8.10 6.10 e1 Bottom View L 7.90 5.90 8.00 6.00 1.27 BSC 1.095 REF 0.67 TYP E e e1 L 4 1.02 4 Notes: 1. 2. 3. 4. All dimensions and tolerance conform to ASME Y 14.5M, 1994. The surface finish of the package shall be EDM Charmille #24-27. Unless otherwise specified tolerance: Decimal ±0.05, Angular ±2o. Metal Pad Dimensions. L1 0.92 0.97 7/10/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 8CN3, 8-pad (6 x 8 x 1.0 mm Body), Lead Pitch 1.27 mm, Chip Array Small Outline No Lead Package (CASON) DRAWING NO. 8CN3 REV. B R 36 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 20.3 28T – TSOP, Type I PIN 1 0º ~ 5º c Pin 1 Identifier Area D1 D L e b L1 E A2 A SEATING PLANE GAGE PLANE A1 SYMBOL A A1 A2 Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. D D1 E L L1 b c e COMMON DIMENSIONS (Unit of Measure = mm) MIN – 0.05 0.90 13.20 11.70 7.90 0.50 NOM – – 1.00 13.40 11.80 8.00 0.60 0.25 BASIC 0.17 0.10 0.22 – 0.55 BASIC 0.27 0.21 MAX 1.20 0.15 1.05 13.60 11.90 8.10 0.70 Note 2 Note 2 NOTE 12/06/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) DRAWING NO. 28T REV. C R 37 3387L–DFLASH–6/06 20.4 28R – SOIC B E1 E PIN 1 e D A A1 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.39 0.050 18.00 11.70 1 8.59 0.356 0.203 0.94 NOM – – – – – – – – 1.27 TYP MAX 2.79 0.356 18.50 12.50 8.79 0.508 0.305 1.27 Note 1 Note 1 NOTE 0º ~ 8º C A A1 L D E E B Note: 1. Dimensions D and E1 do not include mold Flash or protrusion. Mold Flash or protrusion shall not exceed 0.25 mm (0.010"). C L e 5/18/2004 2325 Orchard Parkway San Jose, CA 95131 TITLE 28R, 28-lead, 0.330" Body Width, Plastic Gull Wing Small Outline (SOIC) DRAWING NO. 28R REV. C R 38 AT45DB321C 3387L–DFLASH–6/06 AT45DB321C 21. Revision History Revision Level – Release Date L – June 2006 History Added 28-lead SOIC pinout diagram on page 2. 39 3387L–DFLASH–6/06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Atmel®, logo and combinations thereof, Everywhere You Are® a nd DataFlash ® are registered trademarks, and RapidS™ a nd others are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Printed on recycled paper. 3387L–DFLASH–6/06