AT49BV002-90TI

Features • • • • Single Supply for Read and Write: 2.7V to 3.6 (BV), 3.0 to 3.6V (LV) Fast Read Access Time - 70 ns Internal Program Control and Timer Sector Architecture – One 16K Byte Boot Block with Programming Lockout – Two 8K Byte Parameter Blocks – Two Main Memory Blocks (96K, 128K) Bytes Fast Erase Cycle Time - 10 seconds Byte By Byte Programming - 30 µs/Byte Typical Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation – 25 mA Active Current – 50 µA CMOS Standby Current Typical 10,000 Write Cycles • • • • • • Description The AT49BV/LV002(N)(T) is a 3-volt-only in-system reprogrammable Flash Memory. Its 2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 70 ns with power dissipation of just 90 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 50 µA. For the 2-Megabit (256K x 8) Single 2.7-Volt Battery-Voltage™ Flash Memory AT49BV002 AT49LV002 AT49BV002N AT49LV002N AT49BV002T AT49LV002T AT49BV002NT AT49LV002NT (continued) Pin Configurations Pin Name A0 - A17 CE OE WE RESET I/O0 - I/O7 DC Function Addresses Chip Enable Output Enable Write Enable RESET Data Inputs/Outputs Don’t Connect DIP Top View *RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 PLCC Top View A12 A15 A16 RESET* VCC WE A17 A11 A9 A8 A13 A14 A17 WE VCC *RESET A16 A15 A12 A7 A6 A5 A4 VSOP Top View (8 x 14 mm) or TSOP Top View (8 x 20 mm) Type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 14 15 16 17 18 19 20 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 Rev. 0982C–07/98 *Note: This pin is a DC on the AT49BV002N(T) and AT49LV002N(T). 1 AT49BV/LV002N(T) pin 1 for the DIP and PLCC packages and pin 9 for the TSOP package are don’t connect pins. To allow for simple in-system reprogrammability, the AT49BV/LV002(N)(T) does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49BV/LV002(N)(T) is performed by erasing a block of data and then programming on a byte by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections and two main memory blocks. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed. In the AT49BV/LV002N(T), once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49BV/LV002(T), once the boot block programming lockout feature is enabled, the contents of the boot block cannot be changed with input voltage levels of 5.5 volts or less. Block Diagram AT49BV/LV002(N) DATA INPUTS/OUTPUTS I/O7 - I/O0 VCC GND OE WE CE RESET 8 INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING 3FFFF X DECODER MAIN MEMORY BLOCK 2 (128K BYTES) MAIN MEMORY BLOCK 1 (96K BYTES) PARAMETER BLOCK 2 (8K BYTES) PARAMETER BLOCK 1 (8K BYTES) BOOT BLOCK (16K BYTES) BOOT BLOCK (16K BYTES) 20000 1FFFF PARAMETER BLOCK 1 (8K BYTES) PARAMETER BLOCK 2 (8K BYTES) MAIN MEMORY BLOCK 1 (96K BYTES) MAIN MEMORY BLOCK 2 (128K BYTES) AT49BV/LV002(N)T DATA INPUTS/OUTPUTS I/O7 - I/O0 8 INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING 3FFFF 3C000 3BFFF CONTROL LOGIC Y DECODER ADDRESS INPUTS 08000 07FFF 3A000 39FFF 06000 05FFF 38000 37FFF 04000 03FFF 00000 20000 1FFFF 00000 2 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) Device Operation READ: T he AT49BV/LV002(N)(T) is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE o r OE i s high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table. The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE o r WE , whichever occurs last. The data is latched by the first rising edge of CE o r WE . Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedance state. If the RESET pin makes a high to low transition during a program or erase operation, the operation may not be sucessfully completed and the operation will have to be repeated after a high level is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET p in, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). The RESET feature is not available on the AT49BV/LV002N(T). ERASURE: Before a byte can be reprogrammed, the main memory block or parameter block which contains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Memory Block 2 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-byte parameter block sections can be independently erased and reprogrammed. The two main memory sections are designed to be used as alternative memory sectors. That is, whenever one of the blocks has been erased and reprogrammed, the other block should be erased and reprogrammed before the first block is again erased. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE . The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. BYTE PROGRAMMING: O nce the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE o r CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 00000 to 03FFF for the AT49BV/LV002(N) while the 3 address range of the boot block is 3C000 to 3FFFF for the AT49BV/LV002(N)T. Once the feature is enabled, the data in the boot block can no longer be erased or programmed with input voltage of 5.5V or less. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A s oftware method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out for the AT49BV/LV002(N), and a read from address location 3C002H will show if programming the bootblock is locked out for AT49BV/LV002(N)T. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 volts during the entire chip erase, sector erase or byte programming operation. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. This feature is not available on the AT49BV/LV002N(T). PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: T he AT49BV/LV002(N)(T) features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49BV/LV002(N)(T) provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: H ardware features protect against inadvertent programs to the AT49BV/LV002(N)(T) in the following ways: (a) VCC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE l ow, CE high or WE high inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. 4 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) Command Definition (in Hex)(1) Command Sequence Read Chip Erase Sector Erase Byte Program Boot Block Lockout(2) Product ID Entry Product ID Exit Product ID Exit Notes: (3) (3) Bus Cycles 1 6 6 4 6 3 3 1 1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 5555 XXXX Data DOUT AA AA AA AA AA AA F0 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 55 5555 5555 5555 5555 5555 5555 80 80 A0 80 90 F0 5555 5555 Addr 5555 AA AA DIN AA 2AAA 2AAA 55 55 5555 SA (4) 10 30 2AAA 55 5555 40 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex) 2. The 16K byte boot sector has the address range 00000H to 03FFFH for the AT49BV/LV002(N) and 3C000H to 3FFFFH for the AT49BV/LV002(N)T 3. Either one of the Product ID Exit commands can be used. 4. SA = sector addresses: For the AT49BV/LV002(N): SA = 00000 to 03FFF for BOOT BLOCK Nothing will happen and the device goes back to the read mode in 100 ns SA = 04000 to 05FFF for PARAMETER BLOCK 1 SA = 06000 to 07FFF for PARAMETER BLOCK 2 SA = 08000 to 1FFFF for MAIN MEMORY ARRAY BLOCK 1 This command will erase - PB1, PB2 and MMB1 SA = 20000 to 3FFFF for MAIN MEMORY ARRAY BLOCK 2 For the AT49BV/LV002(N)T: SA = 3C000 to 3FFFF for BOOT BLOCK Nothing will happen and the device goes back to the read mode in 100 ns SA = 3A000 to 3BFFF for PARAMETER BLOCK 1 SA = 38000 to 39FFF for PARAMETER BLOCK 2 SA = 20000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1 This command will erase - PB1, PB2 and MMB1 SA = 00000 to IFFFF for MAIN MEMORY ARRAY BLOCK 2 Absolute Maximum Ratings Temperature Under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5 DC and AC Operating Range AT49LV002(N)(T)-70 Operating Temperature (Case) VCC Power Supply Com. Ind. 0°C - 70°C -40°C - 85°C 3.0V - 3.6V AT49BV/LV002(N)(T)-90 0°C - 70°C -40°C - 85°C 2.7V - 3.6V/3.0V - 3.6V AT49BV/LV002(N)(T)-12 0°C - 70°C -40°C - 85°C 2.7V - 3.6V/3.0V - 3.6V Operating Modes Mode Read Program/Erase (2) CE VIL VIL VIH X X X X OE VIL VIH X (1) WE VIH VIL X VIH X X X RESET(6) VIH VIH VIH VIH VIH VIH VIL Ai Ai Ai X I/O DOUT DIN High Z Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Reset Product Identification X VIL VIH X High Z X High Z Hardware A1 - A17 = VIL, A9 = VH,(3) A0 = VIL VIL VIL VIH A1 - A17 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL, A1 - A17=VIL A0 = VIH, A1 - A17=VIL Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) Software(5) Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V ± 0.5V. 4. Manufacturer Code: 1FH, Device Code: 07H - AT49BV/LV002(N), 08H - AT49BV/LV002(N)T 5. See details under Software Product Identification Entry/Exit. 6. This pin is not available on the AT49BV/LV002N(T). DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC(1) VIL VIH VOL VOH Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage I OL = 2.1 mA IOH = -400 µA 2.4 2.0 .45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Min Max 10 10 50 3 25 0.6 Units µA µA µA mA mA V V V V Note: 1. In the erase mode, ICC is 50 mA. 6 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) AC Read Characteristics AT49LV002(N)(T)-70 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first 0 0 0 Min Max 70 70 35 25 0 0 0 AT49BV/LV002(N)(T)-90 Min Max 90 90 40 25 0 0 0 AT49BV/LV002(N)(T)-12 Min Max 120 120 50 30 Units ns ns ns ns ns AC Read Waveforms (1)(2)(3)(4) ADDRESS CE ADDRESS VALID OE tCE tOE t DF tACC tOH OUTPUT VALID OUTPUT HIGH Z Notes: 1. 2. 3. 4. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested. Input Test Waveform and Measurement Level 2.4V AC DRIVING LEVELS 0.4V 1.5V AC MEASUREMENT LEVEL Output Load Test 3.0V 1.8K OUTPUT PIN 1.3K 30 pF tR, tF < 5 Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ CIN COUT Note: 4 8 1. This parameter is characterized and is not 100% tested. Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 7 AC Byte Load Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 70 0 0 90 70 Max Units ns ns ns ns ns ns 0 90 ns ns AC Byte Load Waveforms WE Controlled OE tOES ADDRESS CE tAS tCS tWPH tWP tDS DATA IN tDH tAH tCH tOEH WE CE Controlled OE tOES ADDRESS tAS WE tCS CE tWPH tWP tDS DATA IN tDH tAH tCH tOEH 8 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) Program Cycle Characteristics Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 70 70 0 90 90 10 Min Typ 30 Max 50 Units µs ns ns ns ns ns ns seconds Program Cycle Waveforms A0 - A17 Sector or Chip Erase Cycle Waveforms OE (1) CE tWP WE tWPH tAS A0 - A17 tAH 5555 tDH 2AAA 5555 5555 2AAA Note 2 tDS DATA AA 55 80 AA 55 Note 3 tEC BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 Notes: 1. 2. 3. OE must be high only when WE and CE are both low. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See note 4 under command definitions.) For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 9 Data Polling Characteristics Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Min 10 10 Typ Max Units ns ns ns Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 0 ns DATA Polling Waveforms WE CE tOEH OE tDH I/O7 A0-A17 An tOE HIGH Z tWR An An An An Toggle Bit Characteristics Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns Toggle Bit Waveforms(1)(2)(3) WE CE tOEH OE tDH I/O6 tOE HIGH Z tWR tOEHP Notes: 1. 2. 3. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary. 10 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) Software Product Identification Entry(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) Boot Block Lockout Feature Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA Software Product Identification Exit(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE(4) OR LOAD DATA F0 TO ANY ADDRESS EXIT PRODUCT IDENTIFICATION MODE(4) LOAD DATA 40 TO ADDRESS 5555 PAUSE 1 second(2) Notes for boot block lockout feature enable: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. Notes for software product identification 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A17 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Device Code: 07H - AT49BV/LV002(N) 08H - AT49BV/LV002(N)T 11 AT49BV002 Ordering Information tACC (ns) 90 ICC (mA) Active 50 Standby 0.1 Ordering Code AT49BV002-90JC AT49BV002-90PC AT49BV002-90TC AT49BV002-90VC AT49BV002-90JI AT49BV002-90PI AT49BV002-90TI AT49LV002-90VI AT49BV002-12JC AT49BV002-12PC AT49BV002-12TC AT49BV002-12VC AT49BV002-12JI AT49BV002-12PI AT49BV002-12TI AT49BV002-12VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 120 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) Package Type 32J 32P6 32T 32V 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm) 12 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) AT49LV002 Ordering Information tACC (ns) 70 ICC (mA) Active 50 Standby 0.1 Ordering Code AT49LV002-70JC AT49LV002-70PC AT49LV002-70TC AT49LV002-70VC AT49LV002-70JI AT49LV002-70PI AT49LV002-70TI AT49LV002-70VI AT49LV002-90JC AT49LV002-90PC AT49LV002-90TC AT49LV002-90VC AT49LV002-90JI AT49LV002-90PI AT49LV002-90TI AT49LV002-90VI AT49LV002-12JC AT49LV002-12PC AT49LV002-12TC AT49LV002-12VC AT49LV002-12JI AT49LV002-12PI AT49LV002-12TI AT49LV002-12VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 90 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 120 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) Package Type 32J 32P6 32T 32V 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm) 13 AT49BV002N Ordering Information tACC (ns) 90 ICC (mA) Active 50 Standby 0.1 Ordering Code AT49BV002N-90JC AT49BV002N-90PC AT49BV002N-90TC AT49BV002N-90VC AT49BV002N-90JI AT49BV002N-90PI AT49BV002N-90TI AT49BV002N-90VI AT49BV002N-12JC AT49BV002N-12PC AT49BV002N-12TC AT49BV002N-12VC AT49BV002N-12JI AT49BV002N-12PI AT49BV002N-12TI AT49BV002N-12VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 120 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) Package Type 32J 32P6 32T 32V 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm) 14 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) AT49LV002N Ordering Information tACC (ns) 70 ICC (mA) Active 50 Standby 0.1 Ordering Code AT49LV002N-70JC AT49LV002N-70PC AT49LV002N-70TC AT49LV002N-70VC AT49LV002N-70JI AT49LV002N-70PI AT49LV002N-70TI AT49LV002N-70VI AT49LV002N-90JC AT49LV002N-90PC AT49LV002N-90TC AT49LV002N-90VC AT49LV002N-90JI AT49LV002N-90PI AT49LV002N-90TI AT49LV002N-90VI AT49LV002N-12JC AT49LV002N-12PC AT49LV002N-12TC AT49LV002N-12VC AT49LV002N-12JI AT49LV002N-12PI AT49LV002N-12TI AT49LV002N-12VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 90 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 120 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) Package Type 32J 32P6 32T 32V 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm) 15 AT49BV002T Ordering Information tACC (ns) 90 ICC (mA) Active 50 Standby 0.1 Ordering Code AT49BV002T-90JC AT49BV002T-90PC AT49BV002T-90TC AT49BV002T-90VC AT49BV002T-90JI AT49BV002T-90PI AT49BV002T-90TI AT49BV002T-90VI AT49BV002T-12JC AT49BV002T-12PC AT49BV002T-12TC AT49BV002T-12VC AT49BV002T-12JI AT49BV002T-12PI AT49BV002T-12TI AT49BV002T-12VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 120 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) Package Type 32J 32P6 32T 32V 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm) 16 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) AT49BV002T Ordering Information tACC (ns) 70 ICC (mA) Active 50 Standby 0.1 Ordering Code AT49LV002T-70JC AT49LV002T-70PC AT49LV002T-70TC AT49LV002T-70VC AT49LV002T-70JI AT49LV002T-70PI AT49LV002T-70TI AT49LV002T-70VI AT49LV002T-90JC AT49LV002T-90PC AT49LV002T-90TC AT49LV002T-90VC AT49LV002T-90JI AT49LV002T-90PI AT49LV002T-90TI AT49LV002T-90VI AT49LV002T-12JC AT49LV002T-12PC AT49LV002T-12TC AT49LV002T-12VC AT49LV002T-12JI AT49LV002T-12PI AT49LV002T-12TI AT49LV002T-12VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 90 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 120 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) Package Type 32J 32P6 32T 32V 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm) 17 AT49BV002NT Ordering Information tACC (ns) 90 50 ICC (mA) 0.1 Ordering Code AT49BV002NT-90JC AT49BV002NT-90PC AT49BV002NT-90TC AT49BV002NT-90VC AT49BV002NT-90JI AT49BV002NT-90PI AT49BV002NT-90TI AT49BV002NT-90VI AT49BV002NT-12JC AT49BV002NT-12PC AT49BV002NT-12TC AT49BV002NT-12VC AT49BV002NT-12JI AT49BV002NT-12PI AT49BV002NT-12TI AT49BV002NT-12VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 120 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) Package Type 32J 32P6 32T 32V 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm) 18 AT49BV/LV002(N)(T) AT49BV/LV002(N)(T) AT49LV002NT Ordering Information tACC (ns) 70 50 ICC (mA) 0.1 Ordering Code AT49LV002NT-70JC AT49LV002NT-70PC AT49LV002NT-70TC AT49LV002NT-70VC AT49LV002NT-70JI AT49LV002NT-70PI AT49LV002NT-70TI AT49LV002NT-70VI AT49LV002NT-90JC AT49LV002NT-90PC AT49LV002NT-90TC AT49LV002NT-90VC AT49LV002NT-90JI AT49LV002NT-90PI AT49LV002NT-90TI AT49LV002NT-90VI AT49LV002NT-12JC AT49LV002NT-12PC AT49LV002NT-12TC AT49LV002NT-12VC AT49LV002NT-12JI AT49LV002NT-12PI AT49LV002NT-12TI AT49LV002NT-12VI Package 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V 32J 32P6 32T 32V Operation Range Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 90 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) 120 50 0.1 Commercial (0° to 70°C) 50 0.3 Industrial (-40° to 85°C) Package Type 32J 32P6 32T 32V 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 32-Lead, Thin Small Outline Package (VSOP) (8 x 14 mm) 19 Packaging Information 32J, 32-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-016 AE 32P6, 32-Lead, 0.600" Wide, Plastic Dual In-line Package (PDIP) Dimensions in Inches and (Millimeters) .045(1.14) X 45° PIN NO. 1 IDENTIFY .025(.635) X 30° - 45° .012(.305) .008(.203) .530(13.5) .490(12.4) .021(.533) .013(.330) .030(.762) .015(3.81) .095(2.41) .060(1.52) .140(3.56) .120(3.05) 1.67(42.4) 1.64(41.7) PIN 1 .032(.813) .026(.660) .553(14.0) .547(13.9) .595(15.1) .585(14.9) .566(14.4) .530(13.5) .050(1.27) TYP .300(7.62) REF .430(10.9) .390(9.90) AT CONTACT POINTS 1.500(38.10) REF .220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18) .090(2.29) MAX .005(.127) MIN .022(.559) X 45° MAX (3X) .453(11.5) .447(11.4) .495(12.6) .485(12.3) .110(2.79) .090(2.29) .065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 REF 15 .690(17.5) .610(15.5) .065(1.65) .015(.381) .022(.559) .014(.356) .012(.305) .008(.203) 32T, 32-Lead, Plastic Thin Small Outline Package (TSOP) Dimensions in Millimeters and (Inches)* 32V, 32-Lead, Plastic Thin Small Outline Package (VSOP) Dimensions in Millimeters and (Inches) INDEX MARK INDEX MARK 18.5(.728) 18.3(.720) 20.2(.795) 19.8(.780) 12.5(.492) 12.3(.484) 14.2(.559) 13.8(.543) 0.50(.020) BSC 7.50(.295) REF 8.20(.323) 7.80(.307) 0.25(.010) 0.15(.006) 0.50(.020) BSC 7.50(.295) REF 8.10(.319) 7.90(.311) 0.25(.010) 0.15(.006) 1.20(.047) MAX 1.20(.047) MAX 0.15(.006) 0.05(.002) 0 5 REF 0.20(.008) 0.10(.004) 0.70(.028) 0.50(.020) 0.15(.006) 0.05(.002) 0 5 REF 0.20(.008) 0.10(.004) 0.70(.028) 0.50(.020) *Controlling dimension: millimeters 20 AT49BV/LV002(N)(T)