AT49BV010-15JI

AT49(H)BV/(H)LV01 Features • • • • • • • • • • Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Fast Read Access Time - 55 ns Internal Program Control and Timer 8K bytes Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Byte By Byte Programming - 30 µs/Byte typical Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation – 25 mA Active Current – 50 µA CMOS Standby Current • Typical 10,000 Write Cycles Description The AT49(H)BV010 and the AT49(H)LV010 are 3-volt-only, 1-megabit Flash memories organized as 131,072 words of 8 bits each. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 55 ns with power dissipation of just 90 mW over the commercial temperature range. When the devices are deselected, the CMOS standby current is less than 50 µA. To allow for simple in-system reprogrammability, the AT49(H)BV/(H)LV010 does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49(H)BV/(H)LV010 is performed by erasing the entire 1 megabit of memory and then programming on a byte by byte basis. The typical byte programming time is a fast 30 µs. The end of a program cycle can be optionally detected by the DATA polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. (continued) 1-Megabit (128K x 8) Single 2.7-volt Battery-Voltage™ Flash Memory AT49BV010 AT49HBV010 AT49LV010 AT49HLV010 Pin Configurations Pin Name A0 - A16 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect TSOP Top View Type 1 A11 A9 A8 A13 A14 NC WE VCC NC A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 PLCC Top View A12 A15 A16 NC VCC WE A17 14 15 16 17 18 19 20 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 0677B-A–9/97 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 1 The optional 8K bytes boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being reprogrammed. Block Diagram VCC GND OE WE CE DATA INPUTS/OUTPUTS I/O0 - I/O7 OE, CE AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING MAIN MEMORY (120K BYTES) OPTIONAL BOOT BLOCK (8K BYTES) Y DECODER ADDRESS INPUTS X DECODER 01FFF 00000 Device Operation R EAD: T he AT49(H)BV/(H)LV010 is accessed like an EPROM. When CE a nd OE are low and WE i s high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE o r OE i s high. This dual-line control gives designers flexibility in preventing bus contention. ERASURE: Before a byte can be reprogrammed, the 128K bytes memory array (or 120K bytes if the boot block featured is used) must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. BYTE PROGRAMMING: O nce the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE or CE , whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified t BP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. 2 BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 8K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 00000H to 01FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A s oftware method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. AT49(H)BV/(H)LV010 AT49(H)BV/(H)LV010 For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. D ATA POLLING: T he AT49(H)BV/(H)LV010 features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA p olling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49(H)BV/(H)LV010 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: H ardware features protect against inadvertent programs to the AT49(H)BV/(H)LV010 in the following ways: (a) V CC sense: if VCC is below 1.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. I NPUT LEVELS: W hile operating with a 2.7V to 3.6V power supply, the address inputs and control inputs (OE, CE a nd WE ) may be driven from 0 to 5.5V without adversely affecting the operation of the device. The I/O lines can only be driven from 0 to VCC + 0.6V. Command Definition (in Hex) Command Sequence Bus Cycles 1st Bus Cycle Addr Read Chip Erase Byte Program Boot Block Lockout(1) Product ID Entry Product ID Exit(2) Product ID Exit(2) Notes: 1 6 4 6 3 3 1 Addr 5555 5555 5555 5555 5555 XXXX Data DOUT AA AA AA AA AA F0 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 5555 5555 5555 5555 5555 80 A0 80 90 F0 5555 Addr 5555 AA DIN AA 2AAA 55 5555 40 2AAA 55 5555 10 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data 1. The 8K byte boot sector has the address range 00000H to 01FFFH. 2. Either one of the Product ID exit commands can be used. Absolute Maximum Ratings* Temperature Under Bias ......................-55°C to +125°C Storage Temperature............................-65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground......................... -0.6V to +6.25V All Output Voltages with Respect to Ground................... -0.6V to VCC + 0.6V Voltage on OE with Respect to Ground......................... -0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 DC and AC Operating Range AT49HLV 010-55 Operating Temperature (Case) VCC Power Supply Com. Ind. AT49LV010 AT49BV010 AT49HBV/ HLV010-70 0°C - 70°C -40°C - 85°C 3.0V to 3.6V 2.7V to 3.6V AT49HBV/ HLV010-90 0°C - 70°C -40°C - 85°C 3.0V to 3.6V 2.7V to 3.6V AT49BV/ LV010-12 0°C - 70°C -40°C - 85°C 3.0V to 3.6V 2.7V to 3.6V AT49BV010-15 0°C - 70°C -40°C - 85°C N/A 2.7V to 3.6V 0°C - 70°C -40°C - 85°C 3.0V to 3.6V N/A Operating Modes Mode Read Program(2) Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification Hardware VIL VIL VIH A1 - A16 = VIL, A9 = VH,(3) A0 = VIL A1 - A16 = VIL, A9 = VH,(3) A0 = VIH Software(5) A0 = VIL, A1 - A16 = VIL A0 = VIH, A1 - A16 = VIL Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V ± 0.5V. 4. Manufacturer Code: 1FH, Device Code: 17H. 5. See details under Software Product Identification Entry/Exit. Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) CE VIL VIL VIH X X X OE VIL VIH X(1) X VIL VIH WE VIH VIL X VIH X X High Z Ai Ai Ai X I/O DOUT DIN High Z DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC(1) VIL VIH VOL VOH Note: Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 1. In the erase mode, ICC is 50 mA. IOL = 2.1 mA IOH = -100 µA; VCC = 3.0V 2.4 2.0 0.45 Condition VIN = 0V to VCC VI/O = 0V to VCC CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Min Max 10 10 50 1 25 0.6 Units µA µA µA mA mA V V V V 4 AT49(H)BV/(H)LV010 AT49(H)BV/(H)LV010 AC Read Characteristics AT49HLV 010-55 Symbol tACC tCE (1) tOE (2) tDF tOH (3, 4) AT49HBV/ HLV010-70 Min Max AT49HBV/ HLV010-90 Min Max AT49BV/ LV010-12 Min Max AT49BV01015 Min Max Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first Min Max Units ns ns ns ns ns 55 55 30 0 0 25 0 0 70 70 35 25 0 0 90 90 40 25 0 0 120 120 50 30 0 0 0 150 150 70 40 AC Read Waveforms(1)(2)(3)(4) ADDRESS ADDRESS VALID CE tCE OE tACC OUTPUT Notes: tDF tOH OUTPUT VALID HIGH Z 1. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impace on tACC. 3. tDF is specified from OE or CE whichever occurs frist (CL - 5 pF). 4. This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level AC DRIVING LEVELS tR, tF < 5 ns Output Test Load 55/70 ns 3.0V 1.8K OUTPUT PIN 1.3K 30 pF 1.3K 1.8K OUTPUT PIN 100 pF 90/120/150 ns 3.0V 2.4V 1.5V 0.4V AC MEASUREMENT LEVEL Pin Capacitance (f = 1 MHz, T = 25°C)(1) Typ CIN COUT Note: 4 8 Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 1. This parameter is characterized and is not 100% tested. 5 AC Byte Load Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 100 0 0 200 100 0 200 Max Units ns ns ns ns ns ns ns ns AC Byte Load Waveforms WE Controlled OE tOES ADDRESS tAS CE tCS WE tWP tDS DATA IN tWPH tDH tAH tCH tOEH CE Controlled OE tOES ADDRESS tAS WE tCS CE tWP tDS DATA IN tWPH tDH tAH tCH tOEH 6 AT49(H)BV/(H)LV010 AT49(H)BV/(H)LV010 Program Cycle Characteristics Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 100 100 0 200 200 10 Min Typ 30 Max Units µs ns ns ns ns ns ns seconds Program Cycle Waveforms PROGRAM CYCLE OE CE tWP WE tAS A0-A16 5555 tDS DATA AA 55 A0 INPUT DATA tWPH tBP tAH 2AAA tDH 5555 ADDRESS Chip Erase Cycle Waveforms OE CE tWP WE tAS A0-A16 5555 tDS DATA AA BYTE 0 Note: tWPH tAH 2AAA tDH 5555 5555 2AAA 5555 tEC 55 BYTE 1 80 BYTE 2 AA BYTE 3 55 BYTE 4 10 BYTE 5 OE must be high only when WE and CE are both low. 7 Data Polling Characteristics(1) Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 0 Min 0 10 Typ Max Units ns ns ns ns Data Polling Waveforms WE CE tOEH OE tDH I/O7 tOE tWR A0-A17 An An An An An Toggle Bit Characteristics(1) Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 150 0 Min 0 10 Typ Max Units ns ns ns ns ns Toggle Bit Waveforms(1)(2)(3) WE CE tOEH OE tDH I/O6 tOE HIGH Z tWR tOEHP Notes: 1. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). 2. Beginning and ending state of I/O6 will vary. 3. Any address location may be used but the address should not vary. 8 AT49(H)BV/(H)LV010 AT49(H)BV/(H)LV010 Software Product Identification Entry(1) LOAD DATA AA TO ADDRESS 5555 Boot Block Lockout Feature Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 LOAD DATA 80 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) LOAD DATA AA TO ADDRESS 5555 Software Product Identification Exit(1) LOAD DATA AA TO ADDRESS 5555 OR LOAD DATA F0 TO ANY ADDRESS LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 40 TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA EXIT PRODUCT IDENTIFICATION MODE(4) PAUSE 1 second(2) LOAD DATA F0 TO ADDRESS 5555 Notes: 1. 2. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). Boot block lockout feature enabled. EXIT PRODUCT IDENTIFICATION MODE(4) Notes: 1. 2. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). A1 - A16 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. The device does note remain in identification mode if powered down. The device returns to standard operation mode. Manufacturers Code: 1FH Device Code: 17H. 3. 4. 5. 9 Ordering Information(1) tACC (ns) 70 ICC (mA) Active 25 25 90 25 25 120 25 25 150 25 25 Note: Standby 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 Ordering Code AT49HBV010-70JC AT49HBV010-70TC AT49HBV010-70JI AT49HBV010-70TI AT49HBV010-90JC AT49HBV010-90TC AT49HBV010-90JI AT49HBV010-90TI AT49BV010-12JC AT49BV010-12TC AT49BV010-12JI AT49BV010-12TI AT49BV010-15JC AT49BV010-15TC AT49BV010-15JI AT49BV010-15TI Package 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T Operation Range Commercial (0°C - 70°C) Industrial (-40°C - 85°C) Commercial (0°C - 70°C) Industrial (-40°C - 85°C) Commercial (0°C - 70°C) Industrial (-40°C - 85°C) Commercial (0°C - 70°C) Industrial (-40°C - 85°C) 1. The 49(H)BV/(H)LV010 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 00000H to 01FFFH). Users requiring the boot block to be in the higher address range should contact Atmel. Package Type 32J 32T 32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC) 32-Lead, Thin Small Outline Package (TSOP) 10 AT49(H)BV/(H)LV010 AT49(H)BV/(H)LV010 Ordering Information (Continued) tACC (ns) 55 ICC (mA) Active 25 25 70 25 25 90 25 25 120 25 25 Standby 0.05 0.05 0.05 0.05 0.05 0.05 0.05 0.05 Ordering Code AT49HLV010-55JC AT49HLV010-55TC AT49HLV010-55JI AT49HLV010-55TI AT49HLV010-70JC AT49HLV010-70TC AT49HLV010-70JI AT49HLV010-70TI AT49HLV010-90JC AT49HLV010-90TC AT49HLV010-90JI AT49HLV010-90TI AT49LV010-12JC AT49LV010-12TC AT49LV010-12JI AT49LV010-12TI Package 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T 32J 32T Operation Range Commercial (0°C - 70°C) Industrial (-40°C - 85°C) Commercial (0°C - 70°C) Industrial (-40°C - 85°C) Commercial (0°C - 70°C) Industrial (-40°C - 85°C) Commercial (0°C - 70°C) Industrial (-40°C - 85°C) Package Type 32J 32T 32-Lead, Plastic J-Leaded Chip Carrier Package (PLCC) 32-Lead, Thin Small Outline Package (TSOP) 11