AT49F002T-70TC

Features • Single Voltage Operation • • • – 5V Read – 5V Reprogramming Fast Read Access Time - 55 ns Internal Program Control and Timer Sector Architecture – One 16K Byte Boot Block with Programming Lockout – Two 8K Byte Parameter Blocks – Two Main Memory Blocks (96K, 128K) Bytes Fast Erase Cycle Time - 10 seconds Byte By Byte Programming - 10 µs/Byte Typical Hardware Data Protection DATA Polling For End Of Program Detection Low Power Dissipation – 50 mA Active Current – 100 µA CMOS Standby Current Typical 10,000 Write Cycles • • • • • • Description The AT49F002(N)T is a 5-volt-only in-system reprogrammable Flash Memory. Its 2 megabits of memory is organized as 262,144 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 275 mW over the commercial temperature range. 2-Megabit (256K x 8) 5-volt Only CMOS Flash Memory AT49F002T AT49F002NT Pin Configurations Pin Name A0 - A17 CE OE WE RESET I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable RESET Data Inputs/Outputs No Connect PLCC Top View A12 A15 A16 RESET * VCC WE A17 (continued) DIP Top View * RESET A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC WE A17 A14 A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 TSOP Top View Type 1 A11 A9 A8 A13 A14 A17 WE VCC * RESET A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 14 15 16 17 18 19 20 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 5 6 7 8 9 10 11 12 13 4 3 2 1 32 31 30 29 28 27 26 25 24 23 22 21 A14 A13 A8 A9 A11 OE A10 CE I/O7 0920B-B–12/97 *Note: This pin is a NC on the AT49F002NT. 1 When the device is deselected, the CMOS standby current is less than 100 µA. For the AT49F002NT pin 1 for the DIP and PLCC packages and pin 9 for the TSOP package are no connect pins. To allow for simple in-system reprogrammability, the AT49F002(N)T does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM; it has standard CE, OE, and WE inputs to avoid bus contention. Reprogramming the AT49F002(N)T is performed by erasing a block of data and then programming on a byte by byte basis. The byte programming time is a fast 50 µs. The end of a program cycle can be optionally detected by the DATA p olling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The device is erased by executing the erase command sequence; the device internally controls the erase operations. There are two 8K byte parameter block sections and two main memory blocks. The device has the capability to protect the data in the boot block; this feature is enabled by a command sequence. The 16K-byte boot block section includes a reprogramming lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is protected from being reprogrammed. In the AT49F002NT, once the boot block programming lockout feature is enabled, the contents of the boot block are permanent and cannot be changed. In the AT49F002T, once the boot block programming lockout feature is enabled, the contents of the boot block cannot be changed with input voltage levels of 5.5 volts or less. Block Diagram DATA INPUTS/OUTPUTS I/O7 - I/O0 VCC GND OE WE CE RESET 8 INPUT/OUTPUT BUFFERS PROGRAM DATA LATCHES Y-GATING 3FFFF X DECODER BOOT BLOCK (16K BYTES) PARAMETER BLOCK 1 (8K BYTES) PARAMETER BLOCK 2 (8K BYTES) MAIN MEMORY BLOCK 1 (96K BYTES) MAIN MEMORY BLOCK 2 (128K BYTES) 3C000 3BFFF CONTROL LOGIC Y DECODER ADDRESS INPUTS 3A000 39FFF 38000 37FFF 20000 1FFFF 00000 2 AT49F002(N)T AT49F002(N)T Device Operation READ: The AT49F002(N)T is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or standby mode depending upon the state of the control line inputs. In order to perform other device functions, a series of command sequences are entered into the device. The command sequences are shown in the Command Definitions table. The command sequences are written by applying a low pulse on the WE or CE input with CE or WE low (respectively) and OE high. The address is latched on the falling edge of CE o r WE , whichever occurs last. The data is latched by the first rising edge of CE o r WE . Standard microprocessor write timings are used. The address locations used in the command sequences are not affected by entering the command sequences. RESET: A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET input halts the present device operation and puts the outputs of the device in a high impedence state. If the RESET pin makes a high to low transition during a program or erase operation, the operation may not be sucessfully completed and the operation will have to be repeated after a high level is applied to the RESET pin. When a high level is reasserted on the RESET pin, the device returns to the read or standby mode, depending upon the state of the control inputs. By applying a 12V ± 0.5V input signal to the RESET p in, the boot block array can be reprogrammed even if the boot block lockout feature has been enabled (see Boot Block Programming Lockout Override section). The RESET feature is not available for the AT49F002NT. 0ERASURE: B efore a byte can be reprogrammed, the main memory block or parameter block which contains the byte must be erased. The erased state of the memory bits is a logical “1”. The entire device can be erased at one time by using a 6-byte software code. The software chip erase code consists of 6-byte load commands to specific address locations with a specific data pattern (please refer to the Chip Erase Cycle Waveforms). After the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. The maximum time needed to erase the whole chip is tEC. If the boot block lockout feature has been enabled, the data in the boot sector will not be erased. CHIP ERASE: If the boot block lockout has been enabled, the Chip Erase function will erase Parameter Block 1, Parameter Block 2, Main Memory Block 1, and Main Memory Block 2 but not the boot block. If the Boot Block Lockout has not been enabled, the Chip Erase function will erase the entire chip. After the full chip erase the device will return back to read mode. Any command during chip erase will be ignored. SECTOR ERASE: As an alternative to a full chip erase, the device is organized into sectors that can be individually erased. There are two 8K-byte parameter block sections and two main memory blocks. The 8K-byte parameter block sections can be independently erased and reprogrammed. The two main memory sections are designed to be used as alternative memory sectors. That is, whenever one of the blocks has been erased and reprogrammed, the other block should be erased and reprogrammed before the first block is again erased. The Sector Erase command is a six bus cycle operation. The sector address is latched on the falling WE edge of the sixth cycle while the 30H data input command is latched at the rising edge of WE . The sector erase starts after the rising edge of WE of the sixth cycle. The erase operation is internally controlled; it will automatically time to completion. BYTE PROGRAMMING: O nce the memory array is erased, the device is programmed (to a logical “0”) on a byte-by-byte basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE o r CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified t BP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The size of the block is 16K bytes. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 3C000 to 3FFFF. 3 Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A s oftware method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 00002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification code should be used to return to standard operation. BOOT BLOCK PROGRAMMING LOCKOUT OVERRIDE: The user can override the boot block programming lockout by taking the RESET pin to 12 volts. By doing this, protected boot block data can be altered through a chip erase, sector erase or word programming. When the RESET pin is brought back to TTL levels the boot block programming lockout feature is again active. This feature is not available on the AT49F002NT. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external pro- grammer to identify the correct programming algoithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F002(N)T features DATA polling to indicate the end of a program cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA polling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49F002(N)T provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F002(N)T in the following ways: (a) VCC sense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE l ow, CE h igh or WE h igh inhibits program cycles. (c) Noise filter: pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. 4 AT49F002(N)T AT49F002(N)T Command Definition (in Hex)(1) Command Sequence Read Chip Erase Sector Erase Byte Program Boot Block Lockout Product ID Entry Product ID Exit(3) Product ID Notes: Exit(3) (2) Bus Cycles 1 6 6 4 6 3 3 1 1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 5555 XXXX Data DOUT AA AA AA AA AA AA F0 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 55 5555 5555 5555 5555 5555 5555 80 80 A0 80 90 F0 5555 5555 Addr 5555 AA AA DIN AA 2AAA 2AAA 55 55 5555 SA(4) 10 30 2AAA 55 5555 40 1. The DATA FORMAT in each bus cycle is as follows: I/O7 - I/O0 (Hex) 2. The 16K byte boot sector has the address range 3C000H to 3FFFFH. 3. Either one of the Product ID Exit commands can be used. 4. SA = sector addresses: SA = 3C000 to 3FFFF for BOOT BLOCK If the boot block is not locked out, this command will erase - BOOT BLOCK, PB1, PB2 and MMB1 If the boot block is locked out, nothing will happen and the device goes back to the read mode in 100 ns SA = 3A000 to 3BFFF for PARAMETER BLOCK 1 SA = 38000 to 39FFF for PARAMETER BLOCK 2 SA = 20000 to 37FFF for MAIN MEMORY ARRAY BLOCK 1 If the boot block is not locked out, this command will erase - BOOT BLOCK, PB1, PB2 and MMB1 If the boot block is locked out, this command will erase - PB1, PB2 and MMB1 SA = 00000 to IFFFF for MAIN MEMORY ARRAY BLOCK 2 Absolute Maximum Ratings* Temperature Under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground ............................ -0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 5 DC and AC Operating Range AT49F002(N)T-55 Operating Temperature (Case) VCC Power Supply Com. Ind. 0°C - 70°C -40°C - 85°C 5V ± 10% AT49F002(N)T-70 0°C - 70°C -40°C - 85°C 5V ± 10% Operating Modes Mode Read Program/Erase (2) CE VIL VIL VIH X X X X OE VIL VIH X(1) X VIL VIH X WE VIH VIL X VIH X X X RESET(6) VIH VIH VIH VIH VIH VIH VIL Ai Ai Ai X I/O DOUT DIN High Z Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Reset Product Identification High Z X High Z Hardware A1 - A17 = VIL, A9 = VH,(3) A0 = VIL VIL VIL VIH A1 - A17 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL, A1 - A17=VIL A0 = VIH, A1 - A17=VIL Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) Software(5) Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V ± 0.5V. 4. Manufacturer Code: 1FH, Device Code: 08H 5. See details under Software Product Identification Entry/Exit. 6. This pin is not available on the AT49F002NT. DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC(1) VIL VIH VOL VOH1 VOH2 Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS IOL = 2.1 mA IOH = -400 µA IOH = -100 µA; VCC = 4.5V 2.4 4.2 2.0 .45 Condition VIN = 0V to VCC VI/O = 0V to VCC Com. CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Ind. Min Max 10 10 100 300 3 50 0.8 Units µA µA µA µA mA mA V V V V V Note: 1. In the erase mode, ICC is 90 mA. 6 AT49F002(N)T AT49F002(N)T AC Read Characteristics AT49F002(N)T-55 Symbol tACC tCE(1) tOE(2) tDF (3)(4) AT49F002(N)T-70 Min Max Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first Min Max Units ns ns ns ns ns 55 55 0 0 0 30 25 0 0 0 70 70 35 25 tOH AC Read Waveforms (1)(2)(3)(4) ADDRESS CE ADDRESS VALID OE tCE tOE t DF tACC tOH OUTPUT VALID OUTPUT HIGH Z Notes: 1. 2. 3. 4. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on t ACC. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested. Input Test Waveform and Measurement Level Output Load Test tR, tF < 5 ns Pin Capacitance (f = 1 MHz, T = 25°C) (1) Typ CIN COUT Note: 4 8 1. This parameter is characterized and is not 100% tested. Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 7 AC Byte Load Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 90 50 Max Units ns ns ns ns ns ns 0 90 ns ns AC Byte Load Waveforms WE Controlled OE tOES ADDRESS CE tAS tCS tWPH tWP tDS DATA IN tDH tAH tCH tOEH WE CE Controlled OE tOES ADDRESS tAS WE tCS CE tWPH tWP tDS DATA IN tDH tAH tCH tOEH 8 AT49F002(N)T AT49F002(N)T Program Cycle Characteristics Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Byte Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 50 50 0 90 90 10 Min Typ 10 Max 50 Units µs ns ns ns ns ns ns seconds Program Cycle Waveforms Sector or Chip Erase Cycle Waveforms OE (1) CE tWP WE tWPH tAS AO - A17 tAH 5555 tDH 2AAA 5555 5555 2AAA Note 2 tDS DATA AA 55 80 AA 55 Note 3 tEC BYTE 0 BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 Notes: 1. 2. 3. OE must be high only when WE and CE are both low. For chip erase, the address should be 5555. For sector erase, the address depends on what sector is to be erased. (See note 4 under command definitions.) For chip erase, the data should be 10H, and for sector erase, the data should be 30H. 9 Data Polling Characteristics(1) Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 0 Min 10 10 Typ Max Units ns ns ns ns DATA Polling Waveforms WE CE tOEH OE tDH I/O7 A0-A17 An tOE HIGH Z tWR An An An An Toggle Bit Characteristics(1) Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. (2) Min 10 10 Typ Max Units ns ns ns 150 0 ns ns Toggle Bit Waveforms(1)(2)(3) WE CE tOEH OE tDH I/O6 tOE HIGH Z tWR tOEHP Notes: 1. 2. 3. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary. 10 AT49F002(N)T AT49F002(N)T Software Product Identification Entry(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE(2)(3)(5) Boot Block Lockout Feature Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 80 TO ADDRESS 5555 LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 40 TO ADDRESS 5555 Software Product Identification Exit(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA F0 TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE(4) PAUSE 1 second(2) OR LOAD DATA AA TO ADDRESS 5555 EXIT PRODUCT IDENTIFICATION MODE(4) Notes for boot block lockout feature enable: 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. Notes for software product identification 1. Data Format: I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A17 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 08H 11 Ordering Information tACC (ns) 55 ICC (mA) Active 50 Standby 0.1 Ordering Code AT49F002T-55JC AT49F002T-55PC AT49F002T-55TC AT49F002T-55JI AT49F002T-55PI AT49F002T-55TI AT49F002T-70JC AT49F002T-70PC AT49F002T-70TC AT49F002T-70JI AT49F002T-70PI AT49F002T-70TI AT49F002NT-55JC AT49F002NT-55PC AT49F002NT-55TC AT49F002NT-55JI AT49F002NT-55PI AT49F002NT-55TI AT49F002NT-70JC AT49F002NT-70PC AT49F002NT-70TC AT49F002NT-70JI AT49F002NT-70PI AT49F002NT-70TI Package 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T 32J 32P6 32T Operation Range Commercial (0° to 70°C) Industrial (-40° to 85°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) 50 0.3 70 50 0.1 50 0.3 55 50 0.1 50 0.3 70 50 0.1 50 0.3 Package Type 32J 32P6 32T 32-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 32-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32-Lead, Thin Small Outline Package (TSOP) 12 AT49F002(N)T