AT49F1025-90JI

Features • Single Voltage Operation • • • • • • • • • – 5V Read – 5V Reprogramming Fast Read Access Time - 45 ns Internal Program Control and Timer 8K word Boot Block With Lockout Fast Erase Cycle Time - 10 seconds Word By Word Programming - 10 µs/Word Typical Hardware Data Protection DATA Polling For End Of Program Detection Small 10 x 14 mm VSOP Package Typical 10,000 Write Cycles Description The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash Memories. Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA. The only difference between the AT49F1024 and the AT49F1025 is the pinout. The AT49F1024 is pin compatable with the AT27C1024, and the AT49F1025 is pin compatable with the AT29C1024. (continued) 1-Megabit (64K x 16) 5-volt Only Flash Memory AT49F1024 AT49F1025 Pin Configurations Pin Name A0 - A15 CE OE WE I/O0 - I/O15 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect AT49F1025 VSOP Top View Type 1 10 x 14 mm A0 A1 A2 A3 A4 A5 A6 A7 A8 GND A9 A10 A11 A12 A13 A14 A15 NC WE VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/07 GND I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 NC CE A9 A10 A11 A12 A13 A14 A15 NC WE VCC NC CE I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 AT49F1024 VSOP Top View Type 1 10 x 14 mm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 GND A8 A7 A6 A5 A4 A3 A2 A1 A0 OE I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 GND PLCC Top View I/O13 I/O14 I/O15 CE NC NC VCC WE NC A15 A14 I/O12 I/O11 I/O10 I/O9 I/O8 GND NC I/O7 I/O6 I/O5 I/O4 7 8 9 10 11 12 13 14 15 16 17 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 A13 A12 A11 A10 A9 GND NC A8 A7 A6 A5 10 x 14 mm I/O3 I/O2 I/O1 I/O0 OE DC A0 A1 A2 A3 A4 18 19 20 21 22 23 24 25 26 27 28 Rev. 0765D–09/98 1 To allow for simple in-system reprogrammability, the AT49F1024/1025 does not require high input voltages for programming. Five-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F1024/1025 is performed by erasing a block of data (entire chip or main memory block) and then programming on a word by word basis. The typical word programming time is a fast 10 µs. The end of a program cycle can be optionally detected by the DATA poll- ing feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles. The optional 8K words boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed. Block Diagram VCC GND OE WE CE DATA INPUTS/OUTPUTS I/O15 - I/O0 16 OE, CE, AND WE LOGIC DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING MAIN MEMORY (56K WORDS) 1FFFH OPTIONAL BOOT BLOCK (8K WORDS) 0000H Y DECODER ADDRESS INPUTS X DECODER Device Operation R EAD: T he AT49F1024/1025 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE o r OE i s high. This dual-line control gives designers flexibility in preventing bus contention. CHIP ERASE: When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same chip erase command (See command definitions table). If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode. MAIN MEMORY ERASE: A s an alternative to the chip erase, a main memory block erase can be performed which will erase all bytes not located in the boot block region to an FFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six bus cycle operation. The address (5555H) is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE. The main memory erase starts after the rising edge of WE o f the sixth cycle. Please see Main Memory Erase cycle waveforms. The Main Memory Erase operation is internally controlled; it will automatically time to completion. WORD PROGRAMMING: O nce the memory array is erased, the device is programmed (to a logical “0”) on a word-by-word basis. Please note that a data “0” cannot be programmed back to a “1”; only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the Command Definitions table). The device will automatically generate the required internal program pulses. The program cycle has addresses latched on the falling edge of WE o r CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The DATA polling feature may also be used to indicate the end of a program cycle. BOOT BLOCK PROGRAMMING LOCKOUT: The device has one designated block that has a programming lockout feature. This feature prevents programming of data in the designated block once the feature has been enabled. The 2 AT49F1024/1025 AT49F1024/1025 size of the block is 8K words. This block, referred to as the boot block, can contain secure code that is used to bring up the system. Enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. This feature does not have to be activated; the boot block’s usage as a write protected region is optional to the user. The address range of the boot block is 0000H to 1FFFH. Once the feature is enabled, the data in the boot block can no longer be erased or programmed. Data in the main memory block can still be changed through the regular programming method and can be erased using either the chip erase or the main memory block erase command. To activate the lockout feature, a series of six program commands to specific addresses with specific data must be performed. Please refer to the Command Definitions table. BOOT BLOCK LOCKOUT DETECTION: A s oftware method is available to determine if programming of the boot block section is locked out. When the device is in the software product identification mode (see Software Product Identification Entry and Exit sections) a read from address location 0002H will show if programming the boot block is locked out. If the data on I/O0 is low, the boot block can be programmed; if the data on I/O0 is high, the program lockout feature has been activated and the block cannot be programmed. The software product identification exit code should be used to return to standard operation. PRODUCT IDENTIFICATION: The product identification mode identifies the device and manufacturer as Atmel. It may be accessed by hardware or software operation. The hardware operation mode can be used by an external programmer to identify the correct programming algorithm for the Atmel product. For details, see Operating Modes (for hardware operation) or Software Product Identification. The manufacturer and device code is the same for both modes. DATA POLLING: The AT49F1024/1025 features DATA polling to indicate the end of a program or erase cycle. During a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on I/O7. Once the program cycle has been completed, true data is valid on all outputs and the next cycle may begin. DATA p olling may begin at any time during the program cycle. TOGGLE BIT: In addition to DATA polling the AT49F1024/1025 provides another method for determining the end of a program or erase cycle. During a program or erase operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the program cycle has completed, I/O6 will stop toggling and valid data will be read. Examining the toggle bit may begin at any time during a program cycle. HARDWARE DATA PROTECTION: Hardware features protect against inadvertent programs to the AT49F1024/1025 in the following ways: (a) V CC s ense: if VCC is below 3.8V (typical), the program function is inhibited. (b) Program inhibit: holding any one of OE l ow, CE high or WE high inhibits program cycles. (c) Noise filter: Pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. 3 Command Definition (in Hex) Command Sequence Read Chip Erase Main Memory Erase Word Program Boot Block Lockout Product ID Entry Product ID Exit (3) (2) Bus Cycles 1 6 6 4 6 3 3 1st Bus Cycle Addr Addr 5555 5555 5555 5555 5555 5555 Data DOUT AA AA AA AA AA AA 2nd Bus Cycle Addr Data 3rd Bus Cycle Addr Data 4th Bus Cycle Addr Data 5th Bus Cycle Addr Data 6th Bus Cycle Addr Data 2AAA 2AAA 2AAA 2AAA 2AAA 2AAA 55 55 55 55 55 55 5555 5555 5555 5555 5555 5555 80 80 A0 80 90 F0 5555 5555 Addr 5555 AA AA DIN AA 2AAA 2AAA 55 55 5555 5555 10 30 2AAA 55 5555 40 Product ID Exit(3) 1 xxxx F0 Notes: 1. The DATA FORMAT in each bus cycle is as follows: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex). 2. The 8K word boot sector has the address range 00000H to 1FFFH. 3. Either one of the Product ID Exit commands can be used. Absolute Maximum Ratings* Temperature Under Bias ................................ -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C All Input Voltages (including NC Pins) with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE with Respect to Ground ...................................-0.6V to +13.5V *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 4 AT49F1024/1025 AT49F1024/1025 DCand AC Operating Range AT49F1024/1025-45 Operating Temperature (Case) VCC Power Supply Com. Ind. 5V ± 10% 0°C - 70°C AT49F1024/1025-55 0°C - 70°C -40°C - 85°C 5V ± 10% AT49F1024/1025-70 0°C - 70°C -40°C - 85°C 5V ± 10% AT49F1024/1025-90 0°C - 70°C -40°C - 85°C 5V ± 10% Operating Modes Mode Read Program (2) CE VIL VIL VIH X X X OE VIL VIH X (1) WE VIH VIL X VIH X X Ai Ai Ai X I/O DOUT DIN High Z Standby/Write Inhibit Program Inhibit Program Inhibit Output Disable Product Identification X VIL VIH High Z Hardware VIL VIL VIH A1 - A15 = VIL, A9 = VH,(3) A0 = VIL A1 - A15 = VIL, A9 = VH,(3) A0 = VIH A0 = VIL, A1 - A15 = VIL A0 = VIH, A1 - A15 = VIL Manufacturer Code(4) Device Code(4) Manufacturer Code(4) Device Code(4) Software(5) Notes: 1. X can be VIL or VIH. 2. Refer to AC Programming Waveforms. 3. VH = 12.0V ± 0.5V. 4. Manufacturer Code: 1FH, Device Code: 87H. 5. See details under Software Product Identification Entry/Exit. DC Characteristics Symbol ILI ILO ISB1 ISB2 ICC VIL VIH VOL VOH1 VOH2 (1) Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage CMOS Condition VIN = 0V to VCC VI/O = 0V to VCC Com. CE = VCC - 0.3V to VCC CE = 2.0V to VCC f = 5 MHz; IOUT = 0 mA Ind. Min Max 10 10 100 300 3 50 0.8 Units µA µA µA µA mA mA V V 2.0 IOL = 2.1 mA IOH = -400 µA IOH = -100 µA; VCC = 4.5V 2.4 4.2 0.45 V V V Note: 1. In the erase mode, ICC is 90 mA. 5 AC Read Characteristics AT49F1024-45 AT49F1025-45 Symbol tACC tCE(1) tOE(2) tDF(3)(4) tOH Parameter Address to Output Delay CE to Output Delay OE to Output Delay CE or OE to Output Float Output Hold from OE, CE or Address, whichever occurred first 0 0 0 Min Max 45 45 30 25 0 0 AT49F1024-55 AT49F1025-55 Min Max 55 55 30 25 0 0 AT49F1024-70 AT49F1025-70 Min Max 70 70 35 25 0 0 0 AT49F1024-90 AT49F1025-90 Min Max 90 90 40 25 Units ns ns ns ns ns AC Read Waveforms(1)(2)(3)(4) Notes: 1. 2. 3. 4. CE may be delayed up to tACC - tCE after the address transition without impact on tACC. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE or by tACC - tOE after an address change without impact on tACC. tDF is specified from OE or CE whichever occurs first (CL = 5 pF). This parameter is characterized and is not 100% tested. Input Test Waveforms and Measurement Level Output Test Load 45/55/70 ns 5.0V 1.8K OUTPUT PIN 1.8K OUTPUT PIN 1.3K 100 pF 90/120 ns 5.0V tR, tF < 5 ns 1.3K 30 pF Pin Capacitance f = 1 MHz, T = 25°C(1) Typ CIN COUT Note: 4 8 1. This parameter is characterized and is not 100% tested. Max 6 12 Units pF pF Conditions VIN = 0V VOUT = 0V 6 AT49F1024/1025 AT49F1024/1025 AC Word Load Characteristics Symbol tAS, tOES tAH tCS tCH tWP tDS tDH, tOEH tWPH Parameter Address, OE Set-up Time Address Hold Time Chip Select Set-up Time Chip Select Hold Time Write Pulse Width (WE or CE) Data Set-up Time Data, OE Hold Time Write Pulse Width High Min 0 50 0 0 90 50 0 90 Max Units ns ns ns ns ns ns ns ns AC Word Load Waveforms WE Controlled OE tOES ADDRESS CE tAS tCS tWPH tWP tDS DATA IN tDH tAH tCH tOEH WE CE Controlled OE tOES ADDRESS tAS WE tCS CE tWPH tWP tDS DATA IN tDH tAH tCH tOEH 7 Program Cycle Characteristics Symbol tBP tAS tAH tDS tDH tWP tWPH tEC Parameter Word Programming Time Address Set-up Time Address Hold Time Data Set-up Time Data Hold Time Write Pulse Width Write Pulse Width High Erase Cycle Time 0 50 50 0 90 90 10 Min Typ 10 Max 50 Units µs ns ns ns ns ns ns seconds Program Cycle Waveforms A0-A15 Main Memory or Chip Erase Cycle Waveforms OE CE t WP t WPH WE t AS t AH 5555 t DH 2AAA 5555 5555 2AAA 5555 A0-A15 t DS t EC 55 WORD 1 80 WORD 2 AA WORD 3 55 WORD 4 NOTE 3 WORD 5 DATA AA WORD 0 Notes: 1. 2. OE must be high only when WE and CE are both low. For chip erase, the address should be 10H. For a main memory erase the data should be 30H. 8 AT49F1024/1025 AT49F1024/1025 Data Polling Characteristics(1) Symbol tDH tOEH tOE tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay (2) Min 10 10 Typ Max Units ns ns ns Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 0 ns Data Polling Waveforms Toggle Bit Characteristics(1) Symbol tDH tOEH tOE tOEHP tWR Notes: Parameter Data Hold Time OE Hold Time OE to Output Delay(2) OE High Pulse Write Recovery Time 1. These parameters are characterized and not 100% tested. 2. See tOE spec in AC Read Characteristics. 150 0 Min 10 10 Typ Max Units ns ns ns ns ns Toggle Bit Waveforms(1)(2)(3) Notes: 1. 2. 3. Toggling either OE or CE or both OE and CE will operate toggle bit. The tOEHP specification must be met by the toggling input(s). Beginning and ending state of I/O6 will vary. Any address location may be used but the address should not vary. 9 Software Product Identification Entry(1) LOAD DATA AA TO ADDRESS 5555 Boot Block Lockout Enable Algorithm(1) LOAD DATA AA TO ADDRESS 5555 LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 90 TO ADDRESS 5555 LOAD DATA 80 TO ADDRESS 5555 ENTER PRODUCT IDENTIFICATION MODE (2)(3)(5) LOAD DATA AA TO ADDRESS 5555 Software Product Identifcation Exit(1) LOAD DATA AA TO ADDRESS 5555 O R LOAD DATA F0 TO ANY ADDRESS LOAD DATA 55 TO ADDRESS 2AAA LOAD DATA 55 TO ADDRESS 2AAA EXIT PRODUCT IDENTIFICATION MODE(4) LOAD DATA 40 TO ADDRESS 5555 PAUSE 1 second(2) LOAD DATA F0 TO ADDRESS 5555 Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. Boot block lockout feature enabled. EXIT PRODUCT IDENTIFICATION MODE(4) Notes: 1. Data Format: I/O15 - I/O8 (Don’t Care); I/O7 - I/O0 (Hex); Address Format: A14 - A0 (Hex). 2. A1 - A15 = VIL. Manufacture Code is read for A0 = VIL; Device Code is read for A0 = VIH. 3. The device does not remain in identification mode if powered down. 4. The device returns to standard operation mode. 5. Manufacturer Code: 1FH Device Code: 87H 10 AT49F1024/1025 AT49F1024/1025 AT49F1024 Ordering Information(1) tACC (ns) 45 55 ICC (mA) Active 50 50 50 70 50 50 90 50 50 Note: Standby 0.1 0.1 0.3 0.1 0.3 0.1 0.3 Ordering Code AT49F1024-45VC AT49F1024-55VC AT49F1024-55VI AT49F1024-70VC AT49F1024-70VI AT49F1024-90VC AT49F1024-90VI Package 40V 40V 40V 40V 40V 40V 40V Operation Range Commercial (0° to 70°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) 1. The AT49F1024 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher address range should contact Atmel. Package Type 40V 40-Lead, Thin Small Outline Package (VSOP) (10 mm x 14 mm) 11 AT49F1025 Ordering Information(1) tACC (ns) 45 55 ICC (mA) Active 50 50 50 70 50 50 90 50 50 Note: Standby 0.1 0.1 0.3 0.1 0.3 0.1 0.3 Ordering Code AT49F1025-45JC AT49F1025-45VC AT49F1025-55JC AT49F1025-55VC AT49F1025-55JI AT49F1025-55VI AT49F1025-70JC AT49F1025-70VC AT49F1025-70JI AT49F1025-70VI AT49F1025-90JC AT49F1025-90VC AT49F1025-90JI AT49F1025-90VI Package 44J 40V 44J 40V 44J 40V 44J 40V 44J 40V 44J 40V 44J 40V Operation Range Commercial (0° to 70°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) Commercial (0° to 70°C) Industrial (-40° to 85°C) 1. The AT49F1025 has as optional boot block feature. The part number shown in the Ordering Information table is for devices with the boot block in the lower address range (i.e., 0000H to 1FFFH). Users requiring the boot block to be in the higher address range should contact Atmel. Package Type 44J 40V 44-Lead, Plastic, J-Leaded Chip Carrier Package (PLCC) 40-Lead, Thin Small Outline Package (VSOP) (10 mm x 14 mm) 12 AT49F1024/1025 AT49F1024/1025 Packaging Information 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-018 AC 40V, 40-Lead, Plastic Thin Small Outline Package (VSOP) Dimensions in Millimeters and (Inches)* .045(1.14) X 45° PIN NO. 1 IDENTIFY .045(1.14) X 30° - 45° .012(.305) .008(.203) .656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4) .630(16.0) .590(15.0) .021(.533) .013(.330) .050(1.27) TYP .500(12.7) REF SQ .043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19) .022(.559) X 45° MAX (3X) *Controlling dimension: millimeters 13