AT52SC1284J-70CI

Module Features • • • • 128-Mbit Burst/Page Flash + 32-Mbit/64-Mbit PSRAM Single 88-ball (8 mm x 10 mm x 1.2 mm) CBGA Package 1.7V to 1.95V VCC 1.8V to 1.95V for VCCQ and PVCC 128-Mbit Flash Features • 8M x 16 Organization • High Performance – Random Access Time – 70 ns, 85 ns – Page Mode Read Time – 20 ns – Synchronous Burst Frequency – 66 MHz – Configurable Burst Operation Sector Erase Architecture – Sixteen 4K Word Sectors with Individual Write Lockout – Two Hundred Fifty-four 32K Word Main Sectors with Individual Write Lockout Typical Sector Erase Time: 32K Word Sectors – 800 ms; 4K Word Sectors – 200 ms Thirty-two Plane Organization, Permitting Concurrent Read in Any of the Thirty-one Planes not Being Programmed/Erased Suspend/Resume Feature for Erase and Program – Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector – Supports Reading Any Word by Suspending Programming of Any Other Word Low-power Operation – 30 mA Active – 20 µA Standby VPP Pin for Write Protection and Accelerated Program Operations RESET Input for Device Initialization Two Protection Registers (128 Bits + 2,048 Bits) Common Flash Interface (CFI) Top and Bottom Boot Sectors 1.7V to 1.95V Operating Voltage • 128-Mbit Flash + 32-Mbit/64-Mbit PSRAM Stack Memory AT52SC1283J AT52SC1284J Preliminary • • • • • • • • • • Asynchronous/Page PSRAM Features • • • • • 32-Mbit (2M Word x 16)/64-Mbit (4M Word x 16) 70 ns Random Access Time 30 ns Page Read Cycle Time 1.8V to 1.95V Operating Voltage PVCC - 0.2V Cycle time = Min, II/O = 0 mA, 100% duty, PCS1 = VIL, ZZ = VIH, VIN = VIL or VIH IOL = 0.5 mA IOH = -0.5 mA PCS1 = VIH, ZZ = VIH, other inputs = VIH or VIL PCS1 > PVCC -0.2V, ZZ > PVCC - 0.2V, other inputs = 0 ~ PVCC ZZ < 0.2V, other inputs = 0 ~ PVCC, no refresh (DPD) 0.8 VCCQ 0.3 120 10 0.3 150 10 Min -1 -1 Typ 32M Max 1 1 64M Max 1 1 Unit µA µA Average Operating Current ICC1 3 3 mA ICC2 Output Low Voltage Output High Voltage Standby Current (TTL) Standby Current (CMOS) Low Power Modes VOL VOH ISB ISB1 ISB0 25 0.2 VCCQ 25 0.2 VCCQ mA V V mA µA µA 42 AT52SC1283J/1284J [Preliminary] 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 45. AC Characteristics (PVCC = 1.8V – 1.95V, TA = -25°C to 85°C) Speed Bins 70 ns Parameter List Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output PUB, PLB Access Time Chip Select to Low-Z Output Read PUB, PLB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output PUB, PLB Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write PUB, PLB Valid to End of Write Write Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Page Mode Cycle Time Page Page Mode Address Access Time Maximum Cycle Time PCS1 High Pulse Width Symbol tRC tAA tCO tOE tBA tLZ tBLZ tOLZ tHZ tBHZ tOHZ tOH tWC tCW tAS tAW tBW tWP tWR tWHZ tDW tDH tOW tPC tPAA tMRC tCP 10 10 10 5 0 0 0 5 70 70 0 70 70 50 0 0 20 0 5 30 30 10K 15 8 10K 8 8 8 Min 70 Max 10K 70 70 25 70 10 10 5 0 0 0 5 85 85 0 85 85 60 0 0 20 0 5 30 30 10K 10 10K 8 8 8 Min 85 Speed Bins 85 ns Max 10K 85 85 30 85 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 43 3530B–STKD–2/4/05 46. Power Up Sequence 1. Apply Power. 2. Maintain stable power for a minimum of 200 µs with PCS1 = VIH 47. Standby Mode State Machines Power On PCS1 = VIH Wa it 200 µs Initial State PCS1 = VIH, Z Z = VIH PCS1 = VIL, Z Z = VIH PUB or/and PLB = VIL Active Mode PCS1 = VlL ZZ = V IH PCS1 = VIH (or/and PUB = PLB = VIH) ZZ = VIH PCS1 = VIH, ZZ = VIL Standby Mode Low Power Modes 2 (Data Inv alid) PCS1 = VIH, ZZ = VIL 48. Standby Mode Characteristics Mode Standby Low Power Modes Memory Cell Data Valid Invalid 32M Standby Current (µA) 120 (ISB1) 10 (ISB0) Wait Time (µs) 0 200 44 AT52SC1283J/1284J [Preliminary] 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 49. Read Cycle Waveforms 49.1 Read Cycle (1) (Address Controlled, PCS1 = POE = VIL, ZZ = PWE = VIH, PUB or/and PLB = VIL) Address A H Dat a Out Previous Data Valid Data Valid 49.2 Read Cycle (2) (ZZ = PWE = VIH) Address A H PCS1 A PUB, PLB POE Z E LZ HZ Dat a Out High-Z Data Valid Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ (max) is less than tLZ (min) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 10 µs. 49.3 Page Read Cycle t MRC t RC t PC t PC t PC t PC t PC t PC t PC (ZZ = PWE = VIH, 16 Words Access) A0~ A3 t AA A4~ A20 t OH t CO t HZ PCS1 t BA PUB, PLB t BHZ t OE OE t BLZ t OLZ t PAA Data Valid t PAA Data Valid t PAA Data Valid t PAA Data Valid t PAA Data Valid t PAA Data Valid t PAA Data Valid Data Valid t OHZ Dat a O u t High-Z t LZ Notes: 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ (max) is less than tLZ (min) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 10 µs. 45 3530B–STKD–2/4/05 50. Write Cycle Waveforms 50.1 Write Cycle (1) C (PWE Controlled, ZZ = VIH) Address W (2) R (4) PCS1 W W P (1) PUB, PLB PWE Dat a In Dat a Out S W High-Z HZ Data Valid W High-Z Data Undefined 50.2 Write Cycle (2) C (PCS1 Controlled, ZZ = VIH) Address S W (2) W R (4) PCS1 PUB, PLB PWE W P(1) W Dat a In Dat a O u t Data Valid High-Z High-Z 50.3 Write Cycle (3) (PUB, PLB Controlled, ZZ = VIH) C Address W (2) R (4) PCS1 W PUB, PLB PWE W S P (1) W Dat a In Dat a Out Data Valid High-Z High-Z Notes: 1. A write occurs during the overlap (tWP) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write ends at the earliest transition when PCS1 goes high and PWE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the PCS1 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as PCS1 or PWE going high. 5. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 10 µs. 46 AT52SC1283J/1284J [Preliminary] 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 50.4 Page Write Cycle t MRC t WC t PC t PC t PC t PC t PC t PC t PC (Address Controlled, ZZ = VIH) A0~ A3 A4~ A20 PCS1 PUB, PLB t AS (3) WE t DW t DH t DW t DH t DW t DH t DW t DH Data Valid Data Valid Data Valid t DW t DH t DW t DH t DW t DH Data Valid Data Valid Data Valid t DW t DH Data Valid Dat a In High-Z t WHZ Data Valid High-Z t OW Dat a Out Data Undefined Notes: 1. A write occurs during the overlap (tWP) of low PCS1 and PWE. A write begins when PCS1 goes low and PWE goes low with asserting PUB or PLB for single byte operation or simultaneously asserting PUB and PLB for double byte operation. A write ends at the earliest transition when PCS1 goes high and PWE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the PCS1 going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as PCS1 or PWE going high. 5. Do not access device with cycle timing shorter than tRC (tWC) for continuous periods > 10 µs. 47 3530B–STKD–2/4/05 51. Deep Power-down Mode Entry/Exit C A4 (2) R(4) PCS1 PUB, PLB W P (1) PWE ZWE tZZmin Next Cycle ZZ Register Write (DPD) Deep Power Down Start Deep Power Down Exit Parameter tZZWE tR (Deep Power-down Mode Only) tZZmin Description ZZ low to Write Enable Low Operation Recovery Time Low Power Mode Time Min 0 200 10 Max 1 Units µs µs µs 48 AT52SC1283J/1284J [Preliminary] 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 52. Low-power Modes 52.1 Mode Register Set A20 - A8 (32M) A21 - A8 (64M) 0 A7 Page Mode Enable/Disable A6 1 A5 1 A4 ZZ Enable/Disable A3 - A0 0 52.2 ZZ Enable/Disable A4 0 1 Type Deep Power-down Enable DPD Disable (Default) Note: If the register is written to enable the Deep Power-down, the part will go into Deep Power-down during the following time that ZZ is driven low and there is no MRS update. When ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power-down Disabled). 52.3 Page Mode Enable/Disable In asynchronous operation mode, the user has the option to toggle A0 - A3 in a random way at higher rate (20 ns vs. 70 ns) to lower access times of subsequent reads with 16-word boundary. In synchronous mode, this option has no effect. The maximum page length is 16 words. Please note that as soon as Page Mode is enabled the CS1 low time restriction applies. This means that the CS1 signal must not be kept low longer than tRC(tWC) = 10 µs. A7 0 1 Type Page Mode Disabled (Default) Page Mode Enabled 52.4 MRS Update C Address S W (2) (4) R PCS1 W W PUB, PLB PWE ZWE P(1) ZZ Register Write Start Register Write Complete Register Update Complete Note: The register update takes place on the rising edge of ZZ. Once the register is updated, the next time ZZ goes low, without any updates to the register starting within the tZZWE max time of 1 µs, the part will refresh the array selected. The data bus is a don’t care when ZZ is low during the register updates. 49 3530B–STKD–2/4/05 53. Ordering Information 53.1 AT52SC1283J Standard Package Ordering Code AT52SC1283J-85CI AT52SC1283J-70CI Package 88C1 88C1 Operation Range -25° to 85°C -25° to 85°C tACC (ns) 85 70 53.2 AT52SC1284J Standard Package Ordering Code AT52SC1284J-85CI AT52SC1284J-70CI Package 88C1 88C1 Operation Range -25° to 85°C -25° to 85°C tACC (ns) 85 70 Package Type 88C1 88-ball, Plastic Chip-size Ball Grid Array Package (CBGA) 50 AT52SC1283J/1284J [Preliminary] 3530B–STKD–2/4/05 AT52SC1283J/1284J [Preliminary] 54. Packaging Information 54.1 88C1 – CBGA D 0.10 C C Seating Plane Marked A1 Identifier Side View E Top View A A1 1.20 mm Ref 8 7 6 5 D1 4 3 2 1 A1 Ball Corner A B C D E F G H COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A E1 A1 D D1 E E1 9.90 MIN – 0.25 7.90 NOM – – 8.00 5.60 TYP 10.00 8.80 TYP 0.80 TYP 0.40 TYP 10.10 MAX 1.20 – 8.10 NOTE e J K L M 0.60 mm Ref e Øb e Øb Bottom View 12/18/03 2325 Orchard Parkway San Jose, CA 95131 TITLE 88C1, 88-ball (8 x 12 Array), 8 x 10 x 1.2 mm Body, 0.80 mm Ball Pitch Ball Grid Array Package (CBGA) DRAWING NO. 88C1 REV. A R 51 3530B–STKD–2/4/05 A tmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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