AT68166HT-YS20-E

Features • • • • 16 Mbit SRAM Multi Chip Module Allows 32-, 16- or 8-bit access configuration Operating Voltage: 3.3V + 0.3V, 5V Tolerant Access Time: – 25 ns – 20 ns – 18 ns (preliminary information) Very Low Power Consumption – Active: 595 mW per byte (Max) @ 20 ns(1), 415mW per byte (Max) @ 50ns(2) – Standby: 15 mW (Typ) Military Temperature Range: -55 to +125°C TTL-Compatible Inputs and Outputs Asynchronous Die manufactured on Atmel 0.25 µm Radiation Hardened Process No Single Event Latch Up below LET Threshold of 80 MeV/mg/cm2@125°C Tested up to a Total Dose of 300 krads (Si) according to MIL-STD-883 Method 1019 ESD better than 2000V Quality Grades: – QML-Q or V – ESCC 950 Mils Wide MQFPT68 Package Mass : 8.5 grams 1. For AT68166HT-20 only. 540mW for AT68166HT-25. 2. For AT68166HT-20 only. 450mW for AT68166HT-25. • • • • • • • • • • • Rad Hard 16 MegaBit 3.3V 5V Tolerant SRAM MultiChip Module AT68166HT Notes: Description The AT68166HT is a 16Mbit SRAM packaged in a hermetic Multi Chip Module (MCM) for space applications. The AT68166HT MCM incorporates four 4Mbit AT60142HT SRAM dice. It can be organized as either one bank of 512Kx8, two banks of 512Kx16 or four banks of 512Kx8. It combines rad-hard capabilities, a latch-up threshold of 80MeV.cm²/mg, a Multiple Bit Upset immunity and a total dose tolerance of 300Krads, with a fast access time. The MCM packaging technology allows a reduction of the PCB area by 50% with a weight savings of 75% compared to four 4Mbit packages. Thanks to the small size of the 4Mbit SRAM die, Atmel has been able to accommodate the assembly of the four dice on one side of the package which facilitates the power dissipation. The compatibility with other products allows designers to easily migrate to the Atmel AT68166HT memory. The AT68166HT is powered at 3.3V and is 5V tolerant. The AT68166HT is processed according to the test methods of the latest revision of the MIL-PRF-38535 or the ESCC 9000. 7843A–AERO–10/09 Block Diagram AT68166HT Block Diagram CS3 WE3 CS2 WE2 CS1 WE1 CS0 WE0 A[18:0] OE BANK3 512k x 8 BANK2 512k x 8 BANK1 512k x 8 BANK0 512k x 8 I/O[31:24] or I/O2[31:16] or I/O3[7:0] I/O[23:16] or I/O2[15:0] or I/O2[7:0] I/O[15:8] or I/O1[31:16] or I/O1[7:0] I/O[7:0] or I/O1[15:0] or I/O[7:0] 512K x 8 Banks Block Diagram (AT60142HT) I/Ox0 I/Ox7 CSx OE WEx 2 AT68166HT 7843A–AERO–10/09 AT68166HT Pin Configuration AT68166HT is packaged in a MQFPT68. The pin assignment depends on the access time. There are 2 versions as described in the table below : Access Time Package Version 25 ns YM 20 ns YS 18 ns YS Table 1. Pin assignment for YS & YM versions Lead 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Signal I/O0[0] I/O0[1] I/O0[2] I/O0[3] I/O0[4] I/O0[5] I/O0[6] I/O0[7] GND I/O1[0] I/O1[1] I/O1[2] I/O1[3] I/O1[4] I/O1[5] I/O1[6] I/O1[7] 33 34 Lead 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 YS YM YS YM Signal VCC A11 A12 A13 A14 A15 A16 CS0 OE CS1 A17 WE1 WE2 WE3 A18 GND NC VCC NC Lead 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Signal I/O3[7] I/O3[6] I/O3[5] I/O3[4] I/O3[3] I/O3[2] I/O3[1] I/O3[0] GND I/O2[7] I/O2[6] I/O2[5] I/O2[4] I/O2[3] I/O2[2] I/O2[1] I/O2[0] 68 Lead 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 YS YM Signal VCC A10 A9 A8 A7 A6 WE0 CS3 GND CS2 A5 A4 A3 A2 A1 A0 VCC NC 3 7843A–AERO–10/09 Figure 1. YM package pin assignment NC A0 A1 A2 A3 A4 A5 CS2 GND CS3 WE0 A6 A7 A8 A9 A10 VCC I/O0[0] I/O0[1] I/O0[2] I/O0[3] I/O0[4] I/O0[5] I/O0[6] I/O0[7] GND I/O1[0] I/O1[1] I/O1[2] I/O1[3] I/O1[4] I/O1[5] I/O1[6] I/O1[7] 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 Note: NC pins are not bonded internally. So, they can be connected to GND or Vcc. Figure 2. AT68166HT pin assignment in YS package VCC A0 A1 A2 A3 A4 A5 CS2 GND CS3 WE0 A6 A7 A8 A9 A10 VCC 4 AT68166HT 7843A–AERO–10/09 VCC A11 A12 A13 A14 A15 A16 CS0 OE CS1 A17 WE1 WE2 WE3 A18 GND VCC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 I/O0[0] I/O0[1] I/O0[2] I/O0[3] I/O0[4] I/O0[5] I/O0[6] I/O0[7] GND I/O1[0] I/O1[1] I/O1[2] I/O1[3] I/O1[4] I/O1[5] I/O1[6] I/O1[7] 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 VCC A11 A12 A13 A14 A15 A16 CS0 OE CS1 A17 WE1 WE2 WE3 A18 NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AT68166H (top view) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 I/O2[0] I/O2[1] I/O2[2] I/O2[3] I/O2[4] I/O2[5] I/O2[6] I/O2[7] GND I/O3[0] I/O3[1] I/O3[2] I/O3[3] I/O3[4] I/O3[5] I/O3[6] I/O3[7] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AT68166H (top view) 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 I/O2[0] I/O2[1] I/O2[2] I/O2[3] I/O2[4] I/O2[5] I/O2[6] I/O2[7] GND I/O3[0] I/O3[1] I/O3[2] I/O3[3] I/O3[4] I/O3[5] I/O3[6] I/O3[7] AT68166HT Pin Description Table 2. Pin Names Name A0 - A18 I/O0 - I/O31 CS0 - CS3 WE0 - WE3 OE VCC GND(1) Note: 1. The package lid is connected to GND Description Address Inputs Data Input/Output Chip Select Write Enable Output Enable Power Supply Ground Table 3. Truth Table(1) CSx H L L L Note: WEx X H L H OE X L X H Inputs/Outputs Z Data Out Data In Z Mode Standby Read Write Output Disable 1. L=low, H=high, X= H or L, Z=high impedance. 5 7843A–AERO–10/09 Electrical Characteristics Absolute Maximum Ratings* Supply Voltage to GND Potential: ...................... -0.5V to 4.6V Voltage range on any input: ......................... GND -0.5V to 7V Voltage range on any ouput: ........................ GND -0.5V to 7V Storage Temperature: .................................... -65⋅C to +150⋅C Output Current from Outputs Pins: .............................. 20 mA Electrostatic Discharge Voltage: ............................... > 2000V (MIL STD 883D Method 3015) *NOTE: Stresses beyond those listed under "Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure between recommended DC operating and absolute maximum rating conditions for extended periods may affect device reliability. Military Operating Range Operating Voltage 3.3 + 0.3V Operating Temperature -55⋅C to + 125⋅C Recommended DC Operating Conditions Parameter Vcc GND VIL VIH Note: Description Supply voltage Ground Input low voltage Input high voltage Min 3.0 0.0 GND - 0.3 2.2 Typ 3.3 0.0 0.0 – Max 3.6 0.0 0.8 5.5V(1) Unit V V V V 1. 5.8V in transient conditions. Capacitance Parameter Cin(1) (OE and Ax) Cin(1) (CSx and WEx) Cio(1) Note: Description Input capacitance Input capacitance I/O capacitance 1. Guaranteed but not tested. Min – – – Typ – – – Max 48 12 12 Unit pF pF pF 6 AT68166HT 7843A–AERO–10/09 AT68166HT DC Parameters DC Test Conditions TA = -55°C to + 125°C; Vss = 0V; VCC = 3.0V to 3.6V Parameter IIX(1) IOZ(1) IIH(2) at 5.5V Description Input leakage current Output leakage current Input Leakage Current (OE & Axx) Input Leakage Current (WE & CS) Minimum -1 -1 – – – – 2.4 Typical – – – – – – – 1 1 10 5 5 0.4 – Maximum AT68166HT-25 AT68166HT-20 AT68166HT-18 1 1 6 2 1.5 0.4 – 1 1 6 2 1.5 0.4 – Unit μA μA μA µA μA V V IOZH(2) at 5.5V Output Leakage Current VOL(3) VOH (4) Output low voltage Output high voltage Notes: 1. 2. 3. 4. GND < VIN < VCC, GND < VOUT < VCC Output Disabled. VIN = 5.5V, VOUT = 5.5V, Output Disabled. VCC min, - IOL = 6 mA VCC min, IOH = -4 mA Consumption Symbol Description TAVAV/TAVAW Test Condition – – 18 ns 20 ns 25 ns 50 ns 1 µs 18 ns 20 ns 25 ns 50 ns 1 µs AT68166HT-25 AT68166HT-20 AT68166HT-18 (preliminary) 7.5 7 170 165 145 80 12 145 140 135 115 105 Unit Value ICCSB(1) ICCSB1(2) Standby Supply Current Standby Supply Current 10 8 – – 150 85 15 – – 150 125 110 7 6 – 165 145 80 12 – 140 135 115 105 mA mA max max ICCOP(3) Read per byte Dynamic Operating Current mA max ICCOP(4) Write per byte Dynamic Operating Current mA max Notes: 1. 2. 3. 4. All CSx >VIH All CSx > VCC - 0.3V F = 1/TAVAV, Iout = 0 mA, WEx = OE = VIH, VIN = GND/VCC, VCC max. F = 1/TAVAW, Iout = 0 mA, WEx = VIL, OE = VIH , VIN = GND/VCC, VCC max. 7 7843A–AERO–10/09 Data Retention Mode Atmel CMOS RAM's are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules insure data retention: 1. During data retention chip select CSx must be held high within VCC to VCC -0.2V. 2. Output Enable (OE) should be held high to keep the RAM outputs high impedance, minimizing power dissipation. 3. During power-up and power-down transitions CSx and OE must be kept between VCC + 0.3V and 70% of VCC. 4. The RAM can begin operation > tR ns after VCC reaches the minimum operation voltages (3V). Figure 3. Data Retention Timing vcc CSx Data Retention Characteristics Parameter VCCDR tCDR tR Description VCC for data retention Chip deselect to data retention time Operation recovery time Min 2.0 0.0 tAVAV (1) Typ TA = 25⋅C – – – Max – – – 6 (AT68166HT-25) Unit V ns ns ICCDR (2) Data retention current – 3 4.5 (AT68166HT-20) 5 (AT68166HT-18) mA 1. 2. TAVAV = Read cycle time. All CSx = VCC, VIN = GND/VCC. 8 AT68166HT 7843A–AERO–10/09 AT68166HT AC Characteristics Temperature Range:................................................................................................. -55 +125°C Supply Voltage: ........................................................................................................... 3.3 +0.3V Input Pulse Levels: ................................................................................................. GND to 3.0V Input Rise and Fall Times:................................................................................... 3ns (10 - 90%) Input and Output Timing Reference Levels: ........................................................................ 1.5V Output Loading IOL/IOH:........................................................................................... See Figure 4 Figure 4. AC Test Loads Waveforms General Specific (TWLQZ, TWHQX, TELQX, TEHQZ TGLQX, TGHQZ) Write Cycle Table 4. Write cycle timings(1) AT68166HT-25 Symbol TAVAW TAVWL TAVWH TDVWH TELWH TWLQZ TWLWH TWHAX TWHDX TWHQX Parameter Write cycle time Address set-up time Address valid to end of write Data set-up time CS low to write end Write low to high Z(2) Write pulse width Address hold from end of write Data hold time Write high to low Z(2) min 20 2 14 9 12 12 0 2 5 max 10 AT68166HT-20 min 20 2 11 8 12 9 0 1 5 max 10 AT68166HT-18 (preliminary) min 18 2 10 7 11 9 0 1 5 max 9 Unit ns ns ns ns ns ns ns ns ns ns Notes: 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode. 2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 9.) 9 7843A–AERO–10/09 Write Cycle 1. WE Controlled, OE High During Write ADDRESS CSx E WEx E OE I/Os Write Cycle 2. WE Controlled, OE Low ADDRESS CSx WEx E E I/Os Write Cycle 3. CS Controlled ADDRESS CSx WEx E I/Os The internal write time of the memory is defined by the overlap of CS Low and WE LOW. Both signals must be activated to initiate a write and either signal can terminate a write by going in active mode. The data input setup and hold timing should be referenced to the active edge of the signal that terminates the write. Data out is high impedance if OE= VIH. 10 AT68166HT 7843A–AERO–10/09 AT68166HT Read Cycle Table 5. Read cycle timings(1) Symbol Parameter AT68166HT-25 AT68166HT-20 AT68166HT-18 (preliminary) min 18 5 5 2 max 18 18 9 9 9 Unit ns ns ns ns ns ns ns ns ns min TAVAV TAVQV TAVQX TELQV TELQX TEHQZ TGLQV TGLQX TGHQZ Notes: Read cycle time Address access time Address valid to low Z Chip-select access time CS low to low Z(2) CS high to high Z(2) Output Enable access time OE low to low Z(2) OE high to high Z (2) 25 5 5 2 - max 25 25 10 12 10 min 20 5 5 2 - max 20 20 9 10 9 1. Timings figures applicable for 8-bit, 16-bit and 32-bit mode. 2. Parameters guaranteed, not tested, with output loading 5 pF. (See “AC Test Loads Waveforms” on page 9.) Read Cycle 1. Address Controlled (CS = OE = VIL, WE = VIH) ADDRESS DOUT Read Cycle 2. Chip Select Controlled (WE = VIH) CSx OE DOUT 11 7843A–AERO–10/09 Typical Applications This section shows standard implementations of the AT68166HT in applications. 32-bit mode application When used on a 32-bit (word) application, the module shall be connected as follow : • • • The 32 lines of data are connected to distinct data lines The four CSx are connected together and linked to a single host CS output Each one of the four WEx is connected to a dedicated WE line on the host to allow byte, half word and word format write. Figure 5. 32-bit typical application ( 1 SRAM bank) AT68166HT RAMS0* RAMOE0* RWE[3:0]* CS[3:0] OE WE[3:0] A[17:0] I/O[31:0] A A[19:2] D[31:0] A[19:2] D[31:0] D TSC695F A[27:0] D[31:0] 16-bit mode application When used on a 16-bit (half word) application, the module can be connected as presented in the following figure. This allows use of a single AT68166HT part for two SRAM memory banks. All input controls of the AT68166HT not used in the application shall be pulled-up. Figure 6. 16-bit typical application (two SRAM banks) RAMOE[1:0]* RAMS1* RWE0* RAMS0* RWE0* OE AT68166HT A[17:0] I/O[31:16] I/O[15:0] A[18:1] D[31:16] D[31:16] A[18:1] D[31:0] A D CS[3:2] WE[3:2] CS[1:0] WE[1:0] TSC695F A[27:0] D[31:0] 8-bit mode application When used on a 8-bit (byte) application, the module can be connected as presented in the following figure. This allows use of a single AT68166HT part for up to four SRAM memory banks. All input controls of the AT68166HT not used in the application shall be pulled-up. Figure 7. 8-bit typical application (two SRAM banks) RAMOE[1:0]* RAMS2* RWE0* RAMS2* RWE0* RAMS1* RWE0* RAMS0* RWE0* A[27:0] D[31:0] OE CS[3] WE[3] CS[2] WE[2] CS[1] WE[1] CS[0] WE[0] AT68166HT A[17:0] A[17:0] I/O[31:24] I/O[23:16] I/O[15:8] I/O[7:0] D[31:24] D[31:24] D[31:24] D[31:24] A[17:0] D[31:0] A D TSC695F 12 AT68166HT 7843A–AERO–10/09 AT68166HT Ordering Information Part Number AT68166HT-YM25-E AT68166HT-YM25MQ AT68166HT-YM25SV (2) (2) Temperature Range 25⋅C -55⋅ to +125⋅C -55⋅ to +125⋅C -55⋅ to +125⋅C -55⋅ to +125⋅C 25°C -55° to +125°C -55° to +125°C -55° to +125°C (3) (2) (2) Speed 25 ns 25 ns 25 ns 25 ns 25 ns 20 ns 20 ns 20 ns 20 ns 20 ns 18 ns 18 ns 18 ns 18 ns 18 ns Package MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 MQFPT68 Flow Engineering Samples Mil Level B Space Level B Space Level B RHA ESCC Engineering Samples Mil Level B Space Level B Space Level B RHA ESCC Engineering Samples Mil Level B Space Level B Space Level B RHA ESCC AT68166HT-YM25SR(2) AT68166HT-YM25-SCC(3) AT68166HT-YS20-E AT68166HT-YS20MQ(2) AT68166HT-YS20SV AT68166HT-YS20SR AT68166HT-YS20-SCC AT68166HT-YS18-E(1) AT68166HT-YS18-MQ AT68166HT-YS18-SV -55° to +125°C 25°C (1)(2) -55° to +125°C -55° to +125°C -55° to +125°C -55° to +125°C (1)(2) AT68166HT-YS18-SR(1)(2) AT68166HT-YS18-SCC(1)(3) Note: 1. Please contact your local sales office. 2. Will be replaced by SMD part number when available. 3. Will be replaced by ESCC part number when available. 13 7843A–AERO–10/09 Package Drawing 68-lead Quad Flat Pack (950 Mils) with non conductive tie bar Note: 1. Lid is connected to Ground. 2. YM and YS package drawings are identical. Document Revision History Creation from AT66168FT without any change. 14 AT68166HT 7843A–AERO–10/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support Enter Product Line E-mail Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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