AT80F51-12AC

Features • • • • • • • • • • Compatible with MCS-51™ Products 4K Bytes of Factory Programmable QuickFlash™ Memory Fully Static Operation: 0 Hz to 20 MHz Three-Level Program Memory Lock 128 x 8-Bit Internal RAM 32 Programmable I/O Lines Two 16-Bit Timer/Counters Six Interrupt Sources Programmable Serial Channel Low Power Idle and Power Down Modes Description The AT80F51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K bytes of QuickFlash Memory. The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS51™ instruction set and pinout. The on-chip QuickFlash allows custom codes to be quickly programmed in the factory. By combining a versatile 8-bit CPU with QuickFlash on a monolithic chip, the Atmel AT80F51 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. (continued) 8-Bit Microcontroller with 4K Bytes QuickFlash™ Memory AT80F51 Pin Configurations P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) TQFP (AD0) (AD1) (AD2) (AD3) 44 42 40 38 36 34 43 41 39 37 35 P1.5 P1.6 P1.7 RST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5 P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3 INDEX CORNER (RXD) (TXD) (INT0) (INT1) (T0) (T1) 1 2 3 4 5 6 7 8 9 10 11 13 15 17 19 21 12 14 16 18 20 22 (WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND GND (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 33 32 31 30 29 28 27 26 25 24 23 P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA NC ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) PLCC (AD0) (AD1) (AD2) (AD3) (RXD) (TXD) (INT0) (INT1) (T0) (T1) P1.5 P1.6 P1.7 RST P3.0 NC P3.1 P3.2 P3.3 P3.4 P3.5 6 4 2 44 42 40 1 3 4 3 4 13 9 75 8 38 9 37 10 36 11 35 12 34 13 33 14 32 15 31 16 30 1 7 1 9 2 1 2 3 2 5 2 72 9 18 20 22 24 26 28 (WR) P3.6 (RD) P3.7 X TA L 2 X TA L 1 GND NC (A8) P2.0 (A9) P2.1 (A10) P2.2 (A11) P2.3 (A12) P2.4 P1.4 P1.3 P1.2 P1.1 P1.0 NC VCC P0.0 P0.1 P0.2 P0.3 INDEX CORNER P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA NC ALE PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) 0979A-A–12/97 3-3 Block Diagram P0.0 - P0.7 P2.0 - P2.7 VCC PORT 0 DRIVERS GND PORT 2 DRIVERS RAM ADDR. REGISTER RAM PORT 0 LATCH PORT 2 LATCH QUICK FLASH B REGISTER ACC STACK POINTER PROGRAM ADDRESS REGISTER TMP2 TMP1 BUFFER ALU INTERRUPT, SERIAL PORT, AND TIMER BLOCKS PC INCREMENTER PSW PROGRAM COUNTER PSEN ALE EA RST PORT 1 LATCH PORT 3 LATCH TIMING AND CONTROL INSTRUCTION REGISTER DPTR OSC PORT 1 DRIVERS PORT 3 DRIVERS P1.0 - P1.7 P3.0 - P3.7 3-4 AT80F51 AT80F51 The AT80F51 provides the following standard features: 4K bytes of QuickFlash, 128 bytes of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT80F51 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset. ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register. Port 2 also receives the high-order address bits and some control signals during QuickFlash verification. Port 3 Port 3 is an 8-bit bidirectional I/O port with internal pullups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features of the AT80F51 as listed below: Port Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Functions RXD (serial input port) TXD (serial output port) INT0 (external interrupt 0) INT1 (external interrupt 1) T0 (timer 0 external input) T1 (timer 1 external input) WR (external data memory write strobe) RD (external data memory read strobe) Pin Description VCC Supply voltage. GND Ground. Port 0 Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as highimpedance inputs. Port 0 may also be configured to be the multiplexed loworder address/data bus during accesses to external program and data memory. In this mode P0 has internal pullups. Port 0 also outputs the code bytes during program verification. External pullups are required during program verification. Port 1 Port 1 is an 8-bit bidirectional I/O port with internal pullups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 1 also receives the low-order address bytes during QuickFlash verification. Port 2 Port 2 is an 8-bit bidirectional I/O port with internal pullups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (IIL) because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application it uses strong internal pullups when emitting 1s. During accesses to external data mem- Port 3 also receives some control signals for QuickFlash verification. RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. ALE Address Latch Enable output pulse for latching the low byte of the address during accesses to external memory. In normal operation ALE is emitted at a constant rate of 1/6 the oscillator frequency, and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped during each access to external Data Memory. If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode. PSEN Program Store Enable is the read strobe to external program memory. When the AT80F51 is executing code from external program memory, PSEN is activated twice each machine 3-5 cycle, except that two PSEN activations are skipped during each access to external data memory. EA External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be internally latched on reset. EA should be strapped to VCC for internal program executions. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. Figure 1. Oscillator Connections C2 XTAL2 C1 XTAL1 GND Oscillator Characteristics XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed. Note: C1, C2 = 30 pF ± 10 pF for Crystals = 40 pF ± 10 pF for Ceramic Resonators Figure 2. External Clock Drive Configuration Idle Mode In idle mode, the CPU puts itself to sleep while all the onchip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. It should be noted that when idle is terminated by a hard ware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of Power Down Mode In the power down mode the oscillator is stopped, and the instruction that invokes power down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the power down mode is termi- Status of External Pins During Idle and Power Down Modes Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data 3-6 AT80F51 AT80F51 nated. The only exit from power down is a hardware reset. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V CC i s restored to its normal operating level and must be held active long enough to allow the oscillator to restart and stabilize. When lock bit 1 is programmed, the logic level at the EA pin is sampled and latched during reset. If the device is powered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is necessary that the latched value of EA be in agreement with the current logic level at that pin in order for the device to function properly. Program Memory Lock Bits O n the chip are three lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the table below: Lock Bit Protection Modes Program Lock Bits LB1 1 2 U P LB2 U U LB3 U U No program lock features. MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the QuickFlash is disabled. Same as mode 2, also verify is disabled. Same as mode 3, also external execution is disabled. Protection Type 3 4 P P P P U P Programming/Verifying the QuickFlash T he AT80F51 can only be programmed by Atmel. Customer codes should be submitted in duplicate on a floppy disk or uploaded to Atmel’s bulletin board or Web site. The code should be in the Intel Hex format. The desired states of the Lock Bits should be specified. Once programmed, the code memory and Lock Bits cannot be erased or reprogrammed. Please consult the factory or Atmel’s representatives for details on submitting custom codes. Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The lock bits cannot be verified directly. Verification of the lock bits is achieved by observing that their features are enabled. Reading the Signature Bytes: The signature bytes are read by the same procedure as a normal verification of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows. (030H) = 1EH indicates manufactured by Atmel (031H) = 80H indicates QuickFlash (032H) = 01H indicates AT80F51 QuickFlash Verification Modes Mode Read Code Data Read Signature Byte RST H H PSEN L L ALE H H EA H H P2.6 L L P2.7 L L P3.6 H L P3.7 H L 3-7 Figure 3. Verifying the QuickFlash +5V AT80F51 A0 - A7 ADDR. OOOOH/0FFFH A8 - A11 P2.6 SEE QUICK FLASH VERIFICATION MODES TABLE P2.7 P3.6 P3.7 XTAL 2 EA VIH ALE P1 P2.0 - P2.3 VCC P0 PGM DATA (USE 10K PULLUPS) 3-20 MHz XTAL1 GND RST PSEN VIH QuickFlash Verification Characteristics TA = 0°C to 70°C, VCC = 5.0 ± 10% Symbol 1/tCLCL tAVQV tELQV tEHQZ Parameter Oscillator Frequency Address to Data Valid ENABLE Low to Data Valid Data Float After ENABLE 0 Min 3 Max 20 48tCLCL 48tCLCL 48tCLCL Units MHz QuickFlash Verification Waveforms P1.0 - P1.7 P2.0 - P2.3 PORT 0 ALE VERIFICATION ADDRESS tAVQV DATA OUT LOGIC 1 LOGIC 0 EA LOGIC 1 LOGIC 0 P2.7 (ENABLE) tELQV tEHQZ 3-8 AT80F51 AT80F51 Absolute Maximum Ratings* Operating Temperature .................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage............................................. 6.6V DC Output Current...................................................... 15.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40°C to 85°C, VCC = 5.0V ± 20% (unless otherwise noted) Symbol VIL VIL1 VIH VIH1 VOL VOL1 VOH Parameter Input Low Voltage Input Low Voltage (EA) Input High Voltage Input High Voltage Output Low Voltage (1) Condition (Except EA) Min -0.5 -0.5 Max 0.2 VCC - 0.1 0.2 VCC - 0.3 VCC + 0.5 VCC + 0.5 0.45 0.45 Units V V V V V V V V V V V V (Except XTAL1, RST) (XTAL1, RST) (Ports 1,2,3) IOL = 1.6 mA IOL = 3.2 mA IOH = -60 µA, VCC = 5V ± 10% IOH = -25 µA IOH = -10 µA 0.2 VCC + 0.9 0.7 VCC Output Low (Port 0, ALE, PSEN) Voltage(1) Output High Voltage (Ports 1,2,3, ALE, PSEN) 2.4 0.75 VCC 0.9 VCC 2.4 0.75 VCC 0.9 VCC -50 -650 ±10 50 300 10 20 5 100 40 VOH1 Output High Voltage (Port 0 in External Bus Mode) IOH = -800 µA, VCC = 5V ± 10% IOH = -300 µA IOH = -80 µA IIL ITL ILI RRST CIO ICC Logical 0 Input Current (Ports 1,2,3) Logical 1 to 0 Transition Current (Ports 1,2,3) Input Leakage Current (Port 0, EA) Reset Pulldown Resistor Pin Capacitance Power Supply Current VIN = 0.45V VIN = 2V, VCC = 5V ± 10% 0.45 < VIN < VCC µA µA µA KΩ pF mA mA µA µA Test Freq. = 1 MHz, TA = 25°C Active Mode, 12 MHz Idle Mode, 12 MHz Power Down Mode (2) VCC = 6V VCC = 3V Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V. 3-9 AC Characteristics (Under Operating Conditions; Load Capacitance for Port 0, ALE, and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF) External Program and Data Memory Characteristics Symbol Parameter 12 MHz Oscillator Min 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tPXAV tAVIV tPLAZ tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH Oscillator Frequency ALE Pulse Width Address Valid to ALE Low Address Hold After ALE Low ALE Low to Valid Instruction In ALE Low to PSEN Low PSEN Pulse Width PSEN Low to Valid Instruction In Input Instruction Hold After PSEN Input Instruction Float After PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float RD Pulse Width WR Pulse Width RD Low to Valid Data In Data Hold After RD Data Float After RD ALE Low to Valid Data In Address to Valid Data In ALE Low to RD or WR Low Address to RD or WR Low Data Valid to WR Transition Data Valid to WR High Data Hold After WR RD Low to Address Float RD or WR High to ALE High 43 200 203 23 433 33 0 123 tCLCL-20 0 97 517 585 300 3tCLCL-50 4tCLCL-75 tCLCL-20 7tCLCL-120 tCLCL-20 0 tCLCL+25 400 400 252 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 75 312 10 6tCLCL-100 6tCLCL-100 5tCLCL-90 0 59 tCLCL-8 5tCLCL-55 10 43 205 145 0 tCLCL-10 127 43 48 233 tCLCL-13 3tCLCL-20 3tCLCL-45 Max Variable Oscillator Min 0 2tCLCL-40 tCLCL-13 tCLCL-20 4tCLCL-65 Max 20 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Units 3-10 AT80F51 AT80F51 External Program Memory Read Cycle tLHLL ALE tAVLL PSEN tPLAZ tLLAX PORT 0 A0 - A7 tLLPL tLLIV tPLIV tPLPH tPXAV tPXIZ tPXIX INSTR IN A0 - A7 tAVIV PORT 2 A8 - A15 A8 - A15 External Data Memory Read Cycle tLHLL ALE tWHLH PSEN tLLDV tLLWL RD tAVLL PORT 0 tLLAX tRLAZ DATA IN tRLRH tRLDV tRHDZ tRHDX A0 - A7 FROM PCL INSTR IN A0 - A7 FROM RI OR DPL tAVWL tAVDV PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH 3-11 External Data Memory Write Cycle tLHLL ALE tWHLH PSEN tLLWL WR tAVLL PORT 0 tLLAX tQVWX tWLWH tQVWH DATA OUT tWHQX A0 - A7 FROM PCL INSTR IN A0 - A7 FROM RI OR DPL tAVWL PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH External Clock Drive Waveforms tCHCX VCC - 0.5V 0.7 VCC 0.2 VCC - 0.1V 0.45V tCHCX tCLCH tCHCL tCLCX tCLCL External Clock Drive Symbol 1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time Min 0 41.6 15 15 20 20 Max 20 Units MHz ns ns ns ns ns 3-12 AT80F51 AT80F51 Serial Port Timing: Shift Register Mode Test Conditions (VCC = 5.0 V ± 20%; Load Capacitance = 80 pF) Symbol Parameter 12 MHz Osc Min tXLXL tQVXH tXHQX tXHDX tXHDV Serial Port Clock Cycle Time Output Data Setup to Clock Rising Edge Output Data Hold After Clock Rising Edge Input Data Hold After Clock Rising Edge Clock Rising Edge to Input Data Valid 1.0 700 50 0 700 Max Variable Oscillator Min 12tCLCL 10tCLCL-133 2tCLCL-117 0 10tCLCL-133 Max µs ns ns ns ns Units Shift Register Mode Timing Waveforms INSTRUCTION ALE CLOCK 0 1 2 3 4 5 6 7 8 tXLXL tQVXH WRITE TO SBUF tXHQX 0 1 2 3 4 5 6 7 SET TI VALID VALID VALID VALID VALID OUTPUT DATA CLEAR RI INPUT DATA tXHDV VALID VALID tXHDX VALID SET RI AC Testing Input/Output Waveforms(1) VCC - 0.5V 0.2 VCC + 0.9V TEST POINTS 0.45V 0.2 VCC - 0.1V Float Waveforms(1) V LOAD+ V LOAD V LOAD 0.1V 0.1V V OL Timing Reference Points V OL + 0.1V 0.1V Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at VIH min. for a logic 1 and VIL max. for a logic 0. Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when 100 mV change from the loaded VOH/VOL level occurs. 3-13 Ordering Information Speed (MHz) 12 Power Supply 5V ± 20% Ordering Code AT80F51-12AC AT80F51-12JC AT80F51-12PC AT80F51-12AI AT80F51-12JI AT80F51-12PI 16 5V ± 20% AT80F51-16AC AT80F51-16JC AT80F51-16PC AT80F51-16AI AT80F51-16JI AT80F51-16PI 20 5V ± 20% AT80F51-20AC AT80F51-20JC AT80F51-20PC AT80F51-20AI AT80F51-20JI AT80F51-20PI Package 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Package Type 44A 44J 40P6 44-Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 3-14 AT80F51