AT86RF212-ZU

Features • Fully Integrated 700/800/900 MHz-Band Transceiver - Chinese WPAN Band from 779 to 787 MHz - European SRD Band from 863 to 870 MHz - North American ISM Band from 902 to 928 MHz • Direct Sequence Spread Spectrum with Different Modulation Schemes and Data Rates - BPSK with 20 and 40 kbit/s, compliant to IEEE 802.15.4-2006 - O-QPSK with 100 and 250 kbit/s, compliant to IEEE 802.15.4-2006 - O-QPSK with 250 kbit/s, compliant to IEEE P802.15.4c - O-QPSK with 200, 400, 500, and 1000 kbit/s PSDU Data Rate • Flexible Combination of Frequency Bands and Data Rates • Industry Leading Link Budget - Receiver Sensitivity up to -110 dBm - Programmable TX Output Power up to +10 dBm • Low Power Supply Voltage from 1.8 V to 3.6 V - Internal Voltage Regulators and Battery Monitor • Low Current Consumption - SLEEP = 0.2 µA - TRX_OFF = 0.4 mA - RX_ON = 9.0 mA - BUSY_TX = 18 mA at PTX = 5 dBm • Digital Interface - Registers, Frame Buffer, and AES Accessible through SPI - Clock Output with Configurable Rate • Radio Transceiver Features - Adjustable Receiver Sensitivity - Integrated TX/RX Switch, LNA, and PLL Loop Filter - Fast Settling PLL Supporting Frequency Hopping - Automatic VCO and Filter Calibration - Integrated 16 MHz Crystal Oscillator - 128 byte FIFO for Transmit/Receive • IEEE 802.15.4-2006 Hardware Support - FCS Computation and Check - Clear Channel Assessment - Received Signal Strength Indicator, Energy Detection, and Link Quality Indication • MAC Hardware Accelerator - Automatic Acknowledgement and Retransmission - CSMA-CA and LBT - Automatic Frame Filtering • AES 128 bit Hardware Accelerator (ECB and CBC modes) • Extended Feature Set Hardware Support - True Random Number Generation for Security Applications - TX/RX Indication (External RF Front End Control) • Optimized for Low BoM Cost and Ease of Production - Low External Component Count: Antenna, Reference Crystal, and Bypass Capacitors - Excellent ESD Robustness • Industrial Temperature Range from -40°C to +85°C 3 • 32-pin Low-profile Lead-free Plastic QFN Package, 5.0 x 5.0 x 0.9 mm • Compliant to IEEE 802.15.4-2003, IEEE 802.15.4-2006, IEEE P802.15.4c, ETSI EN 300 220-1, and FCC 47 CFR Section 15.247 AT86RF212 Low Power 700/800/900 MHz Transceiver for IEEE 802.15.4, P802.15.4c Draft Amendment, Zigbee, 6LoWPAN, and ISM Applications PRELIMINARY 8168B-MCU Wireless-02/09 1 Overview The AT86RF212 is a low-power, low-voltage 700/800/900 MHz transceiver specially designed for the IEEE Standard 802.15.4, ZigBee, 6LoWPAN, and high data rate ISM applications. For the sub-1 GHz bands, it supports low data rates (20 and 40 kbit/s) of the IEEE Standard 802.15.4-2003 [2] and provides optional data rates (100 and 250 kbit/s) using O-QPSK, according to the IEEE Standard 802.15.4-2006 [1] and the respective IEEE P802.15.4c Draft Amendment [3]. Furthermore, proprietary High Data Rate Modes up to 1000 kbit/s can be employed. The AT86RF212 is a true SPI-to-antenna solution. RF-critical components except the antenna, crystal, and de-coupling capacitors are integrated on-chip. MAC and AES hardware accelerators improve overall system power efficiency and timing. 1.1 General Circuit Description The AT86RF212 single-chip RF transceiver provides a complete radio interface between the antenna and the microcontroller. It comprises the analog radio part, digital modulation and demodulation including time and frequency synchronization, as well as data buffering. The number of external components is minimized so that only the antenna, a filter (at high output power levels), the crystal, and four bypass capacitors are required. The bidirectional differential antenna pins are used in common for RX and TX, i.e. no external antenna switch is needed. Control of an external power amplifier is supported by two digital control signals (differential operation). The transceiver block diagram is shown in Figure 1-1. The receiver path is based on a low-IF architecture. After channel filtering and downconversion the low-IF signal is sampled and applied to the digital signal processing part. Communication between transmitter and receiver is based on direct sequence spread spectrum with different modulation schemes and spreading codes. The AT86RF212 supports the IEEE 802.15.4-2006 standard mandatory BPSK modulation and optional O-QPSK modulation in the 868.3 MHz and 915 MHz bands. In addition it supports the O-QPSK modulation defined in IEEE P802.15.4c for the Chinese 780 MHz band. For applications not necessarily targeting IEEE compliant networks the radio transceiver supports proprietary High Data Rate Modes based on O-QPSK. A single 128 byte TRX buffer stores receive or transmit data. The AT86RF212 features hardware supported 128 bit security operation. The standalone AES encryption/decryption engine can be accessed in parallel to all PHY operational modes. Configuration of the AT86RF212, reading, and writing of data memory as well as the AES hardware engine are controlled by the SPI interface and additional control signals. On-chip low-dropout voltage regulators provide the analog and digital 1.8 V power supply. Control registers retain their settings in SLEEP mode when the regulators are turned off. The RX and TX signal processing paths are highly integrated and optimized for low power consumption. 2 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Figure 1-1. AT86RF212 Block Diagram XTAL1 XTAL2 TX Power XOSC Voltage Regulator Configuration Registers PA Mixer LPF DAC TX BBP SPI (Slave) /SEL MISO MOSI SCLK RFP RFN Frequency Synthesis FTN, BATMON TRX Buffer AES LNA PPF Mixer BPF ADC RX BBP AGC Analog Domain Control Logic Digital Domain IRQ CLKM DIG1 DIG2 /RST SLP_TR DIG3/4 3 8168B-MCU Wireless-02/09 2 Pin Configuration 2.1 Pin-out Diagram Figure 2-1. AT86RF212 Pin-out Diagram XTAL1 DIG3 DIG4 AVSS RFP RFN AVSS DVSS /RST 32 31 30 29 28 27 26 25 24 1 exposed paddle 2 3 4 5 6 7 8 XTAL2 IRQ /SEL MOSI DVSS MISO SCLK DVSS CLKM 23 22 21 20 19 18 AVDD EVDD DVDD AVSS AVSS AVSS AVSS AT86RF212 17 9 10 11 12 13 14 15 16 DIG1 DIG2 SLP_TR DVDD AVSS DEVDD DVSS Note: The exposed paddle is electrically connected to the die inside the package. It shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability. 2.2 Pin Description Table 2-1. Pin Description Pins 1 2 3 4 5 6 7 8 9 Name DIG3 DIG4 AVSS RFP RFN AVSS DVSS /RST DIG1 Type Digital output Digital output Ground RF I/O RF I/O Ground Ground Digital input Digital output Description RX/TX Indication, see section 9.4; if disabled, internally pulled to AVSS RX/TX Indication (DIG3 inverted), see section 9.4; if disabled, internally pulled to AVSS Ground for RF signals Differential RF signal Differential RF signal Ground for RF signals Digital ground Chip reset; active low Antenna Diversity RF switch control, see section 9.3; if disabled, internally pulled to DVSS 4 AT86RF212 8168B-MCU Wireless-02/09 DVSS AT86RF212 Pins 10 Name DIG2 Type Digital output Description 1. Antenna Diversity RF switch control (DIG1 inverted), see section 9.3 2. Signal IRQ_2 (RX_START) for RX Frame Time Stamping, see section 9.5 If disabled, internally pulled to DVSS Controls sleep, transmit start, receive states; active high, see section 4.6 Digital ground Regulated 1.8 V internal supply voltage; digital domain, see section 7.5 Regulated 1.8 V internal supply voltage; digital domain, see section 7.5 External supply voltage; digital domain Digital ground Master clock signal output; low if disabled, see section 7.7 Digital ground SPI clock SPI data output (master input slave output) Digital ground SPI data input (master output slave input) SPI select, active low 1. Interrupt request signal; active high or active low, see section 4.7 2. Buffer-level mode indicator; active high Crystal pin, see sections 2.2.1.3 and 7.7 Crystal pin or external clock supply, see section 2.2.1.3 and 7.7 Analog ground External supply voltage; analog domain Regulated 1.8 V internal supply voltage; analog domain, see section 7.5 Analog ground Analog ground Analog ground Analog ground; exposed paddle of QFN package 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Paddle SLP_TR DVSS DVDD DVDD DEVDD DVSS CLKM DVSS SCLK MISO DVSS MOSI /SEL IRQ XTAL2 XTAL1 AVSS EVDD AVDD AVSS AVSS AVSS AVSS Digital input Ground Analog Analog Supply Ground Digital output Ground Digital input Digital output Ground Digital input Digital input Digital output Analog Analog Ground Supply Analog Ground Ground Ground Ground 2.2.1 Analog and RF Pins 2.2.1.1 Supply and Ground Pins EVDD, DEVDD EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF212 radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal voltage regulators and require bypass capacitors for stable operation. The voltage regulators are controlled independently by the radio transceivers state machine and are activated depending on the current radio transceiver state. The voltage regulators can be configured for external supply. For details refer to section 7.5. AVSS, DVSS AVSS and DVSS are analog and digital ground pins respectively. 5 8168B-MCU Wireless-02/09 2.2.1.2 RF Pins RFN, RFP A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by reducing spurious emissions originated from other digital ICs such as a microcontroller. The RF port is designed for a 100 Ω differential load. A DC path between the RF pins is allowed. A DC path to ground or supply voltage is not allowed. Therefore when connecting a RF-load providing a DC path to the power supply or ground, AC-coupling is required as indicated in Table 2-2. A simplified schematic of the RF front end is shown in Figure 2-2. Figure 2-2. Simplified RF Front-end Schematic PCB AT86RF212 LNA RX RFP RFN PA TX MC 0.9V M0 RXTX CM Feedback RF port DC values depend on the operating state, refer to section 5. In TRX_OFF state, when the analog front-end is disabled (see section 5.1.2.3), the RF pins are pulled to ground, preventing a floating voltage larger than 1.8 V, which is not allowed for the internal circuitry. In transmit mode, a control loop provides a common-mode voltage of 0.9 V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 100 pF to ensure the stability of this common-mode feedback loop. In receive mode, the RF port provides a low-impedance path to ground when transistor M0, see Figure 2-2, pulls the inductor center tap to ground. A DC voltage drop of 20 mV across the on-chip inductor can be measured at the RF pins. Matching control (MC) is implemented by an adjustable capacitance to ground at each RF pin as shown in Figure 2-2. The input capacitance can be changed within 15 steps by setting a 4-bit control word (register 0x19, RF_CTRL_1). 6 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 2.2.1.3 Crystal Oscillator Pins XTAL1, XTAL2 The pin XTAL1 is the input of the reference oscillator amplifier (XOSC), XTAL2 the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in section 7.7. When using an external clock reference signal, XTAL1 shall be used as input pin. For further details refer to section 7.7.3. 2.2.1.4 Analog Pin Summary Table 2-2. Analog Pin Behavior – DC Values Pin RFP/RFN Values and Conditions VDC = 0.9 V (BUSY_TX) VDC = 20 mV (receive states) VDC = 0 mV (otherwise) VDC = 0.9 V at both pins CPAR = 3 pF VAC ≤ 1.0 Vpp VDC = 1.8 V (all states, except P_ON, SLEEP, and RESET) VDC = 0 mV (otherwise) VDC = 1.8 V (all states, except P_ON, SLEEP, RESET, and TRX_OFF) VDC = 0 mV (otherwise) Comments DC level at pins RFP/RFN for various transceiver states AC-coupling is required if an antenna with a DC path to ground is used. Serial capacitance and capacitance of each pin to ground must be < 100 pF. DC level at pins XTAL1/XTAL2 for various transceiver states Parasitic capacitance (Cpar) of the pins must be considered as additional load capacitance to the crystal. DC level at pin DVDD for various transceiver states Supply pins (voltage regulator output) for the digital 1.8 V voltage domain. The outputs shall be bypassed by 1 µF. DC level at pin AVDD for various transceiver states Supply pin (voltage regulator output) for the analog 1.8 V voltage domain. The outputs shall be bypassed by 1 µF. XTAL1/XTAL2 DVDD AVDD 2.2.2 Digital Pins The AT86RF212 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in chapter 4. Additional digital output signals DIG1 … DIG4 are provided to control external blocks, i.e. for Antenna Diversity RF switch control or as an RX/TX Indicator, see sections 9.3 and 9.4, respectively. After reset, these pins are connected to digital ground (DIG1/DIG2) or analog ground (DIG3/DIG4). 2.2.2.1 Driver Strength Settings The driver strength of all digital output pins (MISO, IRQ, DIG1, …, DIG4) and CLKM pin can be configured using register 0x03 (TRX_CTRL_0), see Table 2-3. Table 2-3. Digital Output Driver Configuration Pin MISO, IRQ, DIG1, …, DIG4 CLKM Default Driver Strength 2 mA 4 mA Comment Adjustable to 2 mA, 4 mA, 6 mA, and 8 mA Adjustable to 2 mA, 4 mA, 6 mA, and 8 mA The capacitive load should be as small as possible and not larger than 50 pF when using the 2 mA minimum driver strength setting. Generally, the output driver strength should be adjusted to the lowest possible value in order to keep the current consumption and the emission of digital signal harmonics low. 7 8168B-MCU Wireless-02/09 2.2.2.2 Pull-up and Pull-down Configuration Pulling resistors are internally connected to all digital input pins in radio transceiver state P_ON, see section 5.1.2.1. Table 2-4 summarizes the pull-up and pull-down configuration. Table 2-4. Pull-up / Pull-Down Configuration of Digital Input Pins in P_ON State Pins /RST /SEL SCLK MOSI SLP_TR H = ˆ pull-up, L H H L L L = ˆ pull-down In all other states including RESET, no pull-up or pull-down resistors are connected to any of the digital input pins. 2.2.2.3 Register Description Register 0x03 (TRX_CTRL_0): The TRX_CTRL_0 register controls the drive current of the digital output pads and the CLKM clock rate. Table 2-5. Register 0x03 (TRX_CTRL_0) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 PAD_IO[1] R/W 0 3 CLKM_SHA_SEL R/W 1 6 PAD_IO[0] R/W 0 2 CLKM_CTRL R/W 0 5 PAD_IO_CLKM[1] R/W 0 1 CLKM_CTRL R/W 0 4 PAD_IO_CLKM[0] R/W 1 0 CLKM_CTRL R/W 1 • Bit 7:6 – PAD_IO These register bits set the output driver current of digital output pads, except CLKM. Table 2-6. Digital Output Driver Strength Register Bits PAD_IO Value 0 (1) Description 2 mA 4 mA 6 mA 8 mA 1 2 3 Note: 1. Underlined values indicate reset settings. 8 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 • Bit 5:4 – PAD_IO_CLKM These register bits set the output driver current of pin CLKM. Refer also to section 7.7. Table 2-7. CLKM Driver Strength Register Bits PAD_IO_CLKM Value 0 1 2 3 Description 2 mA 4 mA 6 mA 8 mA • Bit 3 – CLKM_SHA_SEL Refer to section 7.7. • Bit 2:0 – CLKM_CTRL Refer to section 7.7. 9 8168B-MCU Wireless-02/09 3 Application Circuits 3.1 Basic Application Schematic A basic application schematic of the AT86RF212 with a single-ended RF connector is shown in Figure 3-1. The 50 Ω single-ended RF input is transformed to the 100 Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port. Regulatory rules like FCC 47 section 15.247, ERC/REC 70-03 or ETSI EN 300 220 may require an external filter F1, depending on used transmit power levels. Figure 3-1. Basic Application Schematic VDD CB2 CX1 XTAL CX2 CB1 32 AVSS 31 AVSS 30 29 AVDD AVSS 28 EVDD 27 AVSS 26 XTAL1 25 XTAL2 2 DIG4 RF F1 B1 C2 C1 3 AVSS 4 RFP 5 RFN 6 AVSS 7 DVSS SLP_TR DEVDD DVDD DVDD DVSS 8 /RST DIG1 DIG2 /SEL 23 MOSI 22 AT86RF212 DVSS 21 MISO 20 SCLK 19 DVSS 18 DVSS CLKM 17 R1 C3 9 10 11 12 13 14 15 16 CB3 CB4 The power supply bypass capacitors (CB2, CB4) are connected to the external analog supply pin (EVDD, pin 28) and external digital supply pin (DEVDD, pin 15). Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. All bypass capacitors should be placed as close 10 AT86RF212 8168B-MCU Wireless-02/09 Digital Interface 1 DIG3 IRQ 24 AT86RF212 as possible to the pins and should have a low-resistance and low-inductance connection to ground to achieve the best performance. The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best accuracy and stability of the reference frequency, large parasitic capacitances should be avoided. Crystal lines should be routed as short as possible and not in proximity of digital I/O signals. This is especially required for the High Data Rate Modes, refer to chapter 7.1.4. Crosstalk from digital signals on the crystal pins or the RF pins can degrade the system performance. Therefore, a low-pass filter (C3, R1) is placed close to the CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if the CLKM pin is not used as a microcontroller clock source. In that case, the output should be turned off during device initialization. The ground plane of the application board should be separated into four independent fragments, the analog, the digital, the antenna and the XTAL ground plane. The exposed paddle shall act as the reference point of the individual grounds. Table 3-1. Example Bill of Materials (BoM) for Basic Application Schematic Symbol B1 F1 B1 + F1 CB1, CB3 CB2, CB4 CX1, CX2 C1, C2 Description SMD balun SMD low pass filter Balun/Filter combination LDO VREG bypass capacitor Power supply bypass capacitor Crystal load capacitor RF coupling capacitor Value 900 MHz 900 MHz 900 MHz 1 μF 1 μF 12 pF 68 pF AVX Murata Epcos Epcos AVX AVX Murata 06035A120JA GRP1886C1H120JA01 B37930 B37920 06035A680JAT2A 06035A229DA GRP1886C1H2R0DA01 COG (0603) COG 5% 5% 50 V 50 V Manufacturer Wuerth JTI Wuerth JTI JTI AVX Murata Part Number 748431090 0900BL18B100 748131009 0915LP15A026 0892FB15A0100 0603YD105KAT2A GRM188R61C105KA12D X5R (0603) 10% 16 V Comment (0402 or 0603) COG (0603) ±0.5 pF 50 V C3 CLKM low-pass filter capacitor 2.2 pF Designed for fCLKM = 1 MHz R1 XTAL CLKM low-pass filter resistor 680 Ω Crystal CX-4025 16 MHz SX-4025 16 MHz ACAL Taitien Siward XWBBPL-F-1 A207-011 Designed for fCLKM = 1 MHz 3.2 Extended Feature Set Application Schematic For using the extended features • Antenna Diversity uses pins DIG1/DIG2 (1) section 9.3 • RX/TX Indicator uses pins DIG3/DIG4 section 9.4 • RX Frame Time Stamping uses pin DIG2 section 9.5 an extended application schematic is required. All other extended features (see section 9) do not need an extended schematic. 11 8168B-MCU Wireless-02/09 An extended feature set application schematic illustrating the use of the AT86RF212 Extended Feature Set is shown in Figure 3-2. Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations. Figure 3-2. Extended Feature Application Schematic VDD CB2 CX1 XTAL CX2 CB1 32 ANT0 1 DIG3 N2 RFSwitch SW2 RFSwitch LNA PA F1 N1 C1 B1 C2 2 DIG4 3 AVSS 4 RFP 5 RFN 6 AVSS 7 DVSS DVDD DVDD DVSS DIG1 DIG2 ANT1 DEVDD 8 /RST SLP_TR AVSS 31 AVSS 30 29 AVDD AVSS 28 EVDD 27 AVSS 26 XTAL1 25 XTAL2 /SEL 23 MOSI 22 AT86RF212 DVSS 21 MISO 20 SCLK 19 DVSS 18 DVSS CLKM 17 R1 C3 SW1 9 10 11 12 13 14 15 16 CB3 CB4 In this example, a balun (B1) transforms the differential radio transceiver RF pins (RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic; refer to Figure 3-1. The RF-Switches (SW1, SW2) separate between receive and transmit path in an external RF front-end. These switches are controlled by the RX/TX Indicator, represented by the differential pin pair DIG3/DIG4, refer to 9.4. During receive the corresponding microcontroller may search for the most reliable RF signal path using an Antenna Diversity algorithm or stored statistic data of link signal quality. One antenna is selected (SW2) by the Antenna Diversity RF switch control pin DIG1 (1), the RF signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the second RX/TX switch (SW1). During transmit the AT86RF212 TX signal is amplified using an external PA (N1), low pass filtered to suppress spurious harmonics emission and fed to the antennas via an RF switch (SW2). In this example RF switch SW2 further supports Antenna Diversity controlled by pin DIG1 (1). Note: 1. DIG1/DIG2 can be used as a differential pin pair to control an RF switch if RX Frame Time Stamping is not used, refer to sections 9.3 and 9.5, respectively. 12 AT86RF212 8168B-MCU Wireless-02/09 Digital Interface IRQ 24 AT86RF212 4 Microcontroller Interface 4.1 Overview This section describes the AT86RF212 to microcontroller interface. The interface comprises a slave SPI and additional control signals; see Figure 4-1. The SPI timing and protocol are described below. Figure 4-1. Microcontroller to AT86RF212 Interface Microcontroller SPI - Master /SEL MOSI MISO SCLK SPI /SEL MOSI MISO SCLK CLKM IRQ SLP_TR /RST DIG2 AT86RF212 MOSI MISO SCLK CLKM IRQ SLP_TR /RST DIG2 SPI - Slave /SEL GPIO1/CLK GPIO2/IRQ GPIO3 GPIO4 GPIO5 Microcontrollers with a master SPI such as Atmel’s AVR family interface directly to the AT86RF212. The SPI is used for register, Frame Buffer, SRAM, and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 4-1 introduces the radio transceiver I/O signals and their functionality. Table 4-1. Signal Description of Microcontroller Interface Signal /SEL MOSI MISO SCLK CLKM Description SPI select signal, active low SPI data (Master Output Slave Input) signal SPI data (Master Input Slave Output) signal SPI clock signal Clock output, refer to section 7.7.4, usable as: - microcontroller clock source - high precision timing reference - MAC timer reference Interrupt request signal, further used as: - Frame Buffer Empty indicator, refer to section 9.6. Multi purpose control signal, see section 4.6: - Sleep/Wakeup - TX start - disable/enable CLKM IRQ SLP_TR 13 8168B-MCU Wireless-02/09 Signal /RST DIG2 Description AT86RF212 reset signal, active low Multi purpose control signal, amongst others to signal the reception of a frame, see section 9.5. 4.2 SPI Timing Description Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode. In synchronous mode, the maximum SCLK frequency is 8 MHz. In asynchronous mode, the maximum SCLK frequency is limited to 7.5 MHz. The signal at pin CLKM is not required to derive SCLK and may be disabled to reduce power consumption and spurious emissions. Figure 4-2 and Figure 4-3 illustrate the SPI timing and introduces its parameters. The corresponding timing parameter definitions t1 – t9 are defined in section 10.4. Figure 4-2. SPI Timing, Global Map, and Definition of Timing Parameters t5, t6, t8 and t9 t9 t8 /SEL SCLK MOSI 7 6 5 4 3 2 1 0 t5 7 6 5 4 3 2 1 0 t6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 4-3. SPI Timing, Detailed Drawing of Timing Parameter t1 to t4 /SEL SCLK t3 t4 Bit 6 t2 Bit 7 Bit 6 Bit 5 Bit 5 MOSI t1 Bit 7 MISO The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H. 14 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 /SEL = L enables the MISO output driver of the AT86RF212. The MSB of MISO is valid after t1 (see section 10.4, parameter 10.4.3) and is updated at each falling edge of SCLK. If the driver is disabled, there is no internal pull-up resistor connected to it. Driving the appropriate signal level must be ensured by the master device or an external pull-up resistor. Note, when both /SEL and /RST are active, the MISO output driver is also enabled. Referring to Figure 4-2 and Figure 4-3 MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t3 and t4, refer to section 10.4, parameters 10.4.5 and 10.4.6. This SPI operational mode is commonly known as “SPI mode 0”. 4.3 SPI Protocol Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 4-2) with MSB first. This command byte defines the SPI access mode and additional mode-dependent information. Table 4-2. SPI Command Byte Definition Bit 7 1 1 0 0 0 0 Bit 6 0 1 0 1 0 1 1 1 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Mode Register access Frame Buffer access SRAM access Access Type Read access Write access Read access Write access Read access Write access Register address [5:0] Register address [5:0] Reserved Reserved Reserved Reserved 0 0 Each SPI transfer returns bytes back to the SPI master on MISO. The content of the first byte is the PHY_STATUS field, see section 4.4. In Figure 4-4 to Figure 4-14 and the following chapters logic values stated with XX on MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return values on MISO stated as XX shall be ignored by the microcontroller. The different access modes are described within the following sections. 4.3.1 Register Access Mode A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the command byte including an identifier bit (bit7 = 1), a read/write select bit (bit 6), and a 6-bit register address. On read access, the content of the selected register address is returned in the second byte on MISO (see Figure 4-4). Figure 4-4. Register Access Mode – Read Access byte 1 (command byte) byte 2 (data byte) MOSI MISO 1 0 ADDRESS[5:0] PHY_STATUS (1) XX READ DATA[7:0] 15 8168B-MCU Wireless-02/09 Note: 1. Each SPI access can be configured to return PHY status information (PHY_STATUS) on MISO, refer to section 4.4. On write access, the second byte transferred on MOSI contains the write data to the selected address (see Figure 4-5). Figure 4-5. Register Access Mode – Write Access byte 1 (command byte) byte 2 (data byte) MOSI MISO 1 1 ADDRESS[5:0] PHY_STATUS WRITE DATA[7:0] XX Each register access must be terminated by setting /SEL = H. Figure 4-6 illustrates a typical SPI sequence for a register access sequence for write and read respectively. Figure 4-6. Example SPI Sequence – Register Access Mode Register Write Access /SEL SCLK MOSI MISO WRITE COMMAND PHY_STATUS WRITE DATA XX READ COMMAND PHY_STATUS XX READ DATA Register Read Access 4.3.2 Frame Buffer Access Mode The 128-byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed description of the Frame Buffer can be found in section 7.4. An introduction to the IEEE 802.15.4 frame format can be found in section 6.1. Frame Buffer read and write accesses are used to read or write frame data (PSDU and additional information) from or to the Frame Buffer. Each access starts with /SEL = L followed by a command byte on MOSI. If this byte indicates a frame read or write access, the next byte PHR indicates the frame length followed by the PSDU data, see Figure 4-7 and Figure 4-8. On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO starting with the second byte. After the PSDU data, three more bytes are transferred containing the link quality indication (LQI) value, the energy detection (ED) value, and the status information (RX_STATUS) of the received frame. Figure 4-7 illustrates the packet structure of a Frame Buffer read access. The structure of RX_STATUS is described in Table 4-3. 16 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Figure 4-7. Packet Structure - Frame Read Access byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) byte n-2 (data byte) byte n-1 (data byte) byte n (data byte) MOSI MISO 0 0 1 reserved[5:0] PHY_STATUS XX PHR[7:0] XX PSDU[7:0] XX LQI[7:0] XX ED[7:0] XX RX_STATUS[7:0] Table 4-3. RX_STATUS Bit Content 7 RX_CRC_VALID (register 0x06, PHY_RSSI) Reference Bit Content Reference Section 6.3.5 3 Reserved Reserved Section 5.2.6 2 1 0 6 5 4 TRAC_STATUS (register 0x02, TRX_STATE) Note, the Frame Buffer read access can be terminated at any time without any consequences by setting /SEL = H, e.g. after reading the frame length byte only. A successive Frame Buffer read operation starts again at the PHR field. On Frame Buffer write access the second byte transferred on MOSI contains the frame length (PHR field) followed by the payload data (PSDU) as shown by Figure 4-8. Figure 4-8. Packet Structure - Frame Write Access byte 1 (command byte) byte 2 (data byte) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI MISO 0 1 1 reserved[5:0] PHY_STATUS PHR[7:0] XX PSDU[7:0] XX PSDU[7:0] XX PSDU[7:0] XX The number of bytes n for one frame buffer access is calculated as follows: Read Access: n = 5 + frame_length [PHY_STATUS, PHR, PSDU data, LQI, ED, and RX_STATUS] Write Access: n = 2 + frame_length [command byte, PHR, and PSDU data] The maximum value of frame_length is 127 bytes. That means that n ≤ 132 for Frame Buffer read and n ≤ 129 for Frame Buffer write accesses. Each read or write of a data byte automatically increments the address counter of the Frame Buffer until the access is terminated by setting /SEL = H. Figure 4-9 and Figure 4-10 illustrate an example SPI sequence of a Frame Buffer access to read a frame with 2-byte PSDU and write a frame with 4-byte PSDU. 17 8168B-MCU Wireless-02/09 Figure 4-9. Example SPI Sequence - Frame Buffer Read of a Frame with 2-byte PSDU /SEL SCLK MOSI MISO COMMAND XX XX XX XX XX XX PHY_STATUS PHR PSDU 1 PSDU 2 LQI ED RX_STATUS Figure 4-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4-byte PSDU /SEL SCLK MOSI MISO COMMAND PHR PSDU 1 PSDU 2 PSDU 3 PSDU 4 PHY_STATUS XX XX XX XX XX Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further details, refer to section 7.4. Notes • The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no frame was received in the meanwhile. • To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to section 9.7. • For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to section 5.2.4. 4.3.3 SRAM Access Mode The SRAM access mode allows accessing dedicated bytes within the Frame Buffer. This may reduce the SPI traffic. During frame receive after occurrence of IRQ_2 (RX_START) an SRAM access can be used to upload the PHR field while preserving Dynamic Frame Buffer Protection, see 9.7. Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must indicate an SRAM access mode according to the definition in Table 4-2. The following byte indicates the start address of the write or read access. The address space is 0x00 to 0x7F for radio transceiver receive or transmit operations. The security module (AES) uses an address space from 0x82 to 0x94, refer to section 9.1. On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access sequence (see Figure 4-11). 18 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Figure 4-11. Packet Structure – SRAM Read Access byte 1 (command byte) byte 2 (address) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI MISO 0 0 0 reserved[5:0] PHY_STATUS ADDRESS[7:0] XX XX DATA[7:0] XX DATA[7:0] XX DATA[7:0] On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence (see Figure 4-12). Do not attempt to read or write bytes beyond the SRAM buffer size. Figure 4-12. Packet Structure – SRAM Write Access byte 1 (command byte) byte 2 (address) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI MISO 0 1 0 reserved[5:0] PHY_STATUS ADDRESS[7:0] XX DATA[7:0] XX DATA[7:0] XX DATA[7:0] XX As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H. Figure 4-13 and Figure 4-14 illustrate an example SPI sequence of a SRAM access to read and write a data package of 5-byte length respectively. Figure 4-13. Example SPI Sequence – SRAM Read Access of a 5-byte Data Package /SEL SCLK MOSI MISO COMMAND ADDRESS XX XX XX XX XX PHY_STATUS XX DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 Figure 4-14. Example SPI Sequence – SRAM Write Access of a 5-byte Data Package /SEL SCLK MOSI MISO COMMAND ADDRESS DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 PHY_STATUS XX XX XX XX XX XX Notes • The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes (see section 4.3.2). • Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode, for further details refer to section 7.4.3. 19 8168B-MCU Wireless-02/09 4.4 PHY Status Information Each SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO. The content of the radio transceiver status information can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the first byte send on MISO to the microcontroller is set to 0x00. 4.4.1 Register Description – SPI Control Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Table 4-4. Register 0x04 (TRX_CTRL_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 PA_EXT_EN R/W 0 3 SPI_CMD_MODE R/W 0 6 IRQ_2_EXT_EN R/W 0 2 SPI_CMD_MODE R/W 0 5 TX_AUTO_CRC_ON R/W 1 1 IRQ_MASK_MODE R/W 0 4 RX_BL_CTRL R/W 0 0 IRQ_POLARITY R/W 0 • Bit 7 – PA_EXT_EN Refer to section 9.4.3. • Bit 6 – IRQ_2_EXT_EN Refer to section 9.5.2. • Bit 5 – TX_AUTO_CRC_ON Refer to section 6.3.5. • Bit 4 – RX_BL_CTRL Refer to section 9.6.2. • Bit 3:2 – SPI_CMD_MODE Each SPI transfer returns bytes back to the SPI master. The content of the first byte can be configured using register bits SPI_CMD_MODE. The transfer of the following status information can be configured as follows: Table 4-5. PHY Status Information Register Bits SPI_CMD_MODE Value 0 1 2 3 Description default (empty, all bits 0x00) monitor TRX_STATUS register monitor PHY_RSSI register monitor IRQ_STATUS register Interrupts are not cleared. see 5.1.5 see 6.4 see 4.7 20 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 • Bit 1 – IRQ_MASK_MODE Refer to section 4.7.2. • Bit 0 – IRQ_POLARITY Refer to section 4.7.2. 4.5 Radio Transceiver Identification The AT86RF212 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Additional two registers contain the JEDEC manufacture ID. 4.5.1 Register Description Register 0x1C (PART_NUM): Table 4-6. Register 0x1C (PART_NUM) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 PART_NUM[7:0] R 0 1 1 1 2 1 0 • Bit 7:0 – PART_NUM This register contains the radio transceiver part number. Table 4-7. Radio Transceiver Part Number Register Bits PART_NUM Value 7 State Description AT86RF212 part number Register 0x1D (VERSION_NUM): Table 4-8. Register 0x1D (VERSION_NUM) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 VERSION_NUM[7:0] R 0 0 0 1 • Bit 7:0 – VERSION_NUM This register contains the radio transceiver version number. Table 4-9. Radio Transceiver Version Number Register Bits VERSION_NUM Value 1 State Description Revision A Register 0x1E (MAN_ID_0): Table 4-10. Register 0x1E (MAN_ID_0) 21 8168B-MCU Wireless-02/09 Bit Name Read/Write Reset Value 7 6 5 4 3 MAN_ID_0[7:0] R 2 1 0 0 0 0 1 1 1 1 1 • Bit 7:0 – MAN_ID_0 Bits [7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The highest 16 bits of the ID are not stored in registers. Table 4-11. JEDEC Manufacturer ID – Bits [7:0] Register Bits MAN_ID_0 Value 0x1F State Description Atmel JEDEC manufacturer ID, Bits [7:0] of 32 bit manufacturer ID: 00 00 00 1F Register 0x1F (MAN_ID_1): Table 4-12. Register 0x1F (MAN_ID_1) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 MAN_ID_1[7:0] R 0 0 0 0 2 1 0 • Bit 7:0 – MAN_ID_1 Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers. Table 4-13. JEDEC Manufacturer ID – Bits [15:8] Register Bits MAN_ID_1 Value 0x00 State Description Atmel JEDEC manufacturer ID Bits [15:8] of 32 bit manufacturer ID: 00 00 00 1F 4.6 Sleep/Wake-up and Transmit Signal (SLP_TR) Pin 11 (SLP_TR) is a multi-functional pin. Its function relates to the current state of the AT86RF212 and is summarized in Table 4-14. The radio transceiver states are explained in detail in section 5. In states PLL_ON and TX_ARET_ON, pin SLP_TR is used as trigger input to initiate a TX transaction. Here pin SLP_TR is sensitive on rising edge only. After initiating a state change by a rising edge at pin SLP_TR in radio transceiver states TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the new state as long as the pin is logical high and returns to the preceding state with the falling edge. 22 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 4-14. SLP_TR Multi-functional Pin Transceiver Status PLL_ON TX_ARET_ON BUSY_RX_AACK TRX_OFF SLEEP RX_ON RX_ON_NOCLK RX_AACK_ON RX_AACK_ON_NOCLK Function TX start TX start TX start Sleep Wakeup Disable CLKM Enable CLKM Disable CLKM Enable CLKM Transition Description L L L L H L H L H H H H H L H L H L Starts frame transmission Starts TX_ARET transaction Starts ACK transmission during RX_AACK slotted operation, see section 5.2.3.5. Takes the radio transceiver into SLEEP state, CLKM disabled Takes the radio transceiver back into TRX_OFF state, level sensitive Takes the radio transceiver into RX_ON_NOCLK state and disables CLKM Takes the radio transceiver into RX_ON state and enables CLKM Takes the radio transceiver into RX_AACK_ON_NOCLK state and disables CLKM Takes the radio transceiver into RX_AACK_ON state and enables CLKM SLEEP state The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF212 can be powered down to reduce the overall power consumption. A power-down scenario is shown in Figure 4-15. When the radio transceiver is in TRX_OFF state the microcontroller forces the AT86RF212 to SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 clock cycles. This enables a microcontroller in a synchronous system to complete its power-down routine and prevent deadlock situations. The AT86RF212 awakes when the microcontroller releases pin SLP_TR. This concept provides the lowest possible power consumption. The CLKM clock frequency settings for CLKM_CTRL values 6 and 7 are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering SLEEP state. Figure 4-15. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer SLP_TR CLKM 35 CLKM clock cycles CLKM off tTR2 async timer elapses (microcontroller) Note: Timing figure tTR2 refers to Table 5-1. RX_ON and RX_AACK_ON states For synchronous systems, where CLKM is used as a microcontroller clock source and the SPI master clock (SCLK) is directly derived from CLKM, the AT86RF212 supports an additional power-down mode for receive operating states (RX_ON and RX_AACK_ON). 23 8168B-MCU Wireless-02/09 If an incoming frame is expected and no other applications are running on the microcontroller, it can be powered down without missing incoming frames. This can be achieved by a rising edge on pin SLP_TR that turns off the CLKM. Then the radio transceiver state changes from RX_ON or RX_AACK_ON (Extended Operating Mode) to RX_ON_NOCLK or RX_AACK_ON_NOCLK respectively. In case that a frame is received (e.g. indicated by an IRQ_2 (RX_START) interrupt) the clock output CLKM is automatically switched on again. This scenario is shown in Figure 4-16. In RX_ON state, the clock at pin 17 (CLKM) is switched off after 35 clock cycles when setting the pin SLP_TR = H. The CLKM clock frequency settings for CLKM_CTRL values 6 and 7 are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering RX_ON_NOCLK and RX_AACK_ON_NOCLK respectively. In states RX_(AACK)_ON_NOCLK and RX_(AACK)_ON, the radio transceiver current consumptions are equivalent. However, the RX_(AACK)_ON_NOCLK current consumption is reduced by the current required for driving pin 17 (CLKM). Figure 4-16. Wake-Up Initiated by Radio Transceiver Interrupt IRQ SLP_TR CLKM 35 CLKM clock cycles radio transceiver IRQ issued typ. 5 µs CLKM off 4.7 Interrupt Logic 4.7.1 Overview The AT86RF212 supports 8 interrupt requests as listed in Table 4-15. Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ, pin 24). If an interrupt is issued (pin IRQ = H), the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt status register and thus the IRQ pin, too. Interrupts are not cleared automatically when the event that caused them vanishes. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) because the occurrence of one clears the other. The supported interrupts for the Basic Operating Mode are summarized in Table 4-15. 24 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 4-15. Interrupt Description in Basic Operating Mode IRQ Name IRQ_7 (BAT_LOW) IRQ_6 (TRX_UR) IRQ_5 (AMI) IRQ_4 (CCA_ED_DONE) Description Indicates a supply voltage below the programmed threshold. Indicates a Frame Buffer access violation. Indicates address matching. Multi-functional interrupt: 1. AWAKE_END: • Indicates radio transceiver reached TRX_OFF state at the end of P_ON TRX_OFF and SLEEP TRX_OFF state transition 2. CCA_ED_DONE: • Indicates the end of a CCA or ED measurement RX: Indicates the completion of a frame reception. TX: Indicates the completion of a frame transmission. Indicates the start of a PSDU reception. The TRX_STATE changes to BUSY_RX, the PHR is valid to be read from Frame Buffer. Indicates PLL unlock. If the radio transceiver is in BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately. Indicates PLL lock. Section 7.6.4 7.4.3 6.2 o 5.1.2.3 6.6.4 5.1.3 5.1.3 7.8.5 7.8.5 IRQ_3 (TRX_END) IRQ_2 (RX_START) IRQ_1 (PLL_UNLOCK) IRQ_0 (PLL_LOCK) The interrupt IRQ_4 has two meanings, depending on the current radio transceiver state, refer to register 0x01 (TRX_STATUS). After P_ON, SLEEP, or RESET, the radio transceiver issues an interrupt IRQ_4 (AWAKE_END) when it enters state TRX_OFF. The second meaning is only valid for receive states. If the microcontroller initiates an ED or CCA measurement, the completion of the measurement is indicated by interrupt IRQ_4 (CCA_ED_DONE), refer to sections 6.5.4 and 6.6.4 for details. After P_ON or RESET all interrupts are disabled. During radio transceiver initialization it is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered. Note that AWAKE_END interrupt can usually not be seen when the transceiver enters TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. In this case, state TRX_OFF is normally entered before the microcontroller could modify the register. The interrupt handling in Extended Operating Mode is described in section 5.2.5. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked, refer to Figure 4-18. However, in that case no timing information for this interrupt is provided. The IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin IRQ = H issues an interrupt request. If “Frame Buffer Empty Indicator” is enabled during Frame Buffer read access the IRQ pin has an alternative functionality, refer to section 9.6 for details. A solution to monitor the IRQ_STATUS register (without clearing it) is described in section 4.4. 25 8168B-MCU Wireless-02/09 4.7.2 Register Description Register 0x0E (IRQ_MASK): The IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled after power up sequence (P_ON state) or reset (RESET state). Table 4-16. Register 0x0E (IRQ_MASK) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 MASK_BAT_LOW R/W 0 3 MASK_TRX_END R/W 0 6 MASK_TRX_UR R/W 0 2 MASK_RX_START R/W 0 5 MASK_AMI R/W 0 1 MASK_ PLL_UNLOCK R/W 0 R/W 0 4 MASK_ CCA_ED_DONE R/W 0 0 MASK_PLL_LOCK If an interrupt is enabled, it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history. Register 0x0F (IRQ_STATUS): The IRQ_STATUS register contains the status of the pending interrupt requests. Table 4-17. Register 0x0F (IRQ_STATUS) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 BAT_LOW R 0 3 TRX_END R 0 6 TRX_UR R 0 2 RX_START R 0 5 AMI R 0 1 PLL_UNLOCK R 0 4 CCA_ED_DONE R 0 0 PLL_LOCK R 0 By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked, refer to Figure 4-18. However in that case no timing information for this interrupt is provided. If register bit IRQ_MASK_MODE is set, it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history. 26 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Table 4-18. Register 0x04 (TRX_CTRL_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 PA_EXT_EN R/W 0 3 SPI_CMD_MODE R/W 0 6 IRQ_2_EXT_EN R/W 0 2 SPI_CMD_MODE R/W 0 5 TX_AUTO_CRC_ON R/W 1 1 IRQ_MASK_MODE R/W 0 4 RX_BL_CTRL R/W 0 0 IRQ_POLARITY R/W 0 • Bit 7 – PA_EXT_EN RX/TX Indicator, refer to section 9.4.3. • Bit 6 – IRQ_2_EXT_EN The timing of a received frame can be determined by a separate pin. If register bit IRQ_2_EXT_EN is set to 1, the reception of a PHR field is directly issued on pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START). Note that this pin is also active even if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to 0. The pin remains at high level until the end of the frame receive procedure. For further details refer to section 9.5. • Bit 5 – TX_AUTO_CRC_ON Refer to section 6.3.5. • Bit 4 – RX_BL_CTRL Refer to section 9.6.2. • Bit 3:2 – SPI_CMD_MODE Refer to section 4.4.1. • Bit 1 – IRQ_MASK_MODE The AT86RF212 supports polling of interrupt events. Interrupt polling can be enabled by register bit IRQ_MASK_MODE. Even if an interrupt request is masked by the corresponding bit in register 0x0E (IRQ_MASK), the event is indicated in register 0x0F (IRQ_STATUS). 27 8168B-MCU Wireless-02/09 Table 4-19. IRQ Mask Configuration IRQ_MASK Value 0 0 ≠0 ≠0 IRQ_MASK_MODE 0 1 0 1 Description IRQ is suppressed entirely and none of interrupt causes are shown in register IRQ_STATUS. IRQ is suppressed entirely but all interrupt causes are shown in register IRQ_STATUS. All enabled interrupts are signaled on pin IRQ and are also shown in register IRQ_STATUS. All enabled interrupts are signaled on pin IRQ and all interrupt causes are shown in register IRQ_STATUS. Figure 4-17. IRQ_MASK_MODE = 0 Interrupt Sources . . . IRQ_MASK (register 0x0E) IRQ_STATUS (register 0x0F) OR IRQ Figure 4-18. IRQ_MASK_MODE = 1 Interrupt Sources . . . IRQ_STATUS (register 0x0F) IRQ_MASK (register 0x0E) OR IRQ • Bit 0 – IRQ_POLARITY The default polarity of the IRQ pin is active high. The polarity can be configured to active low via register bit IRQ_POLARITY, see Table 4-20. Table 4-20. Configuration of Pin 24 (IRQ) Register Bit IRQ_POLARITY Value 0 1 Description pin IRQ high active pin IRQ low active This setting does not affect the polarity of the Frame Buffer Empty Indicator, refer to section 9.6. The Frame Buffer Empty Indicator is always active high. 28 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 5 Operating Modes 5.1 Basic Operating Mode This section summarizes all states to provide the basic functionality of the AT86RF212, such as receiving and transmitting frames, the power up sequence and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and ISM applications; the corresponding radio transceiver states are shown in Figure 5-1. Figure 5-1. Basic Operating Mode State Diagram (for timing refer to Table 5-1) P_ON (Power-on after EVDD) XOSC=ON Pull=ON SLEEP (Sleep State) XOSC=OFF Pull=OFF = L TR 3 = H R SL P_ (from all states) /RST = L FORCE_TRX_OFF 12 TRX_OFF (Clock State) XOSC=ON Pull=OFF SL P_ T (all states except SLEEP) N O RX _ O FF FF O X_ TR 1 2 13 /RST = H (all states except P_ON) RESET PL 7 TR X_ 5 X TR FF _O ON L_ 6 SHR Detected Frame End 4 Frame End 10 SLP_TR = H or TX_START 8 BUSY_RX (Receive State) RX_ON (Rx Listen State) RX_ON PLL_ON 9 11 PLL_ON (PLL State) BUSY_TX (Transmit State) SHR Detected = H SL P_ TR FORCE_PLL_ON 14 Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event Basic Operating Mode States X State transition number, see Table 7-1 = L RX_ON_NOCLK (Rx Listen State) CLKM=OFF 5.1.1 State Control The radio transceiver states are controlled either by writing commands to register bits TRX_CMD (register 0x02, TRX_STATE), or directly by two signal pins: pin 11 (SLP_TR) and pin 8 (/RST). A successful state change can be verified by reading the radio transceiver status from register 0x01 (TRX_STATUS). SL P_ TR (all states except SLEEP, P_ON, TRX_OFF, RX_ON_NOCLK) 29 8168B-MCU Wireless-02/09 If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF212 is in a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. Pin SLP_TR is a multifunctional pin, refer to section 4.6. Depending on the radio transceiver state, a rising edge of pin SLP_TR causes the following state transitions: • TRX_OFF → SLEEP • RX_ON → RX_ON_NOCLK • PLL_ON → BUSY_TX whereas the falling edge of pin SLP_TR causes the following state transitions: • SLEEP • RX_ON_NOCLK → → TRX_OFF RX_ON Pin 8 (/RST) causes a reset of all registers (register bits CLKM_CTRL are shadowed, for details refer to section 7.7.4), and the content of the SRAM it deleted. It forces the radio transceiver into TRX_OFF state. However, if the device was in P_ON state it remains in P_ON state. For all states except SLEEP, the state change commands FORCE_TRX_OFF or TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active receive or transmit states (BUSY_*), the command FORCE_TRX_OFF interrupts these active processes, and forces an immediate transition to TRX_OFF. By contrast a TRX_OFF command is stored until an active state (receiving or transmitting) has been finished. After that the transition to TRX_OFF is performed. For a fast transition from receive or active transmit states to PLL_ON state the command FORCE_PLL_ON is provided. Active processes are interrupted. In contrast to FORCE_TRX_OFF this command does not disable the PLL and the analog voltage regulator AVREG. It is not available in states SLEEP, RESET, and all *_NOCLK states. The completion of each requested state change shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS). 5.1.2 Description 5.1.2.1 P_ON – Power-on after EVDD When the external supply voltage (EVDD) is applied first to the AT86RF212 the radio transceiver goes into P_ON state performing an on-chip reset. The crystal oscillator is activated and the default 1 MHz master clock is provided at pin 17 (CLKM) after the crystal oscillator has stabilized. CLKM can be used as a clock source to the microcontroller. The SPI interface and digital voltage regulator are enabled. The on-chip power-on-reset sets all registers to their default values. A dedicated reset signal from the microcontroller at pin 8 (/RST) is not necessary, but recommended for hardware/software synchronization reasons. All digital inputs have pull-up or pull-down resistors during P_ON state, refer to section 2.2.2.2. This is necessary to support microcontrollers where GPIO signals are floating after power on or reset. The input pull-up and pull-down resistors are disabled when the radio transceiver leaves P_ON state. Leaving P_ON state, outputs pins DIG1/DIG2 are internally connected to digital ground, whereas pins DIG3/DIG4 are internally connected to analog ground, unless their configuration is changed. A reset at pin 8 (/RST) does not enable the pull-up or pull-down resistors. 30 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Prior to leaving P_ON, the microcontroller must set the input pins to the default operating values: SLP_TR = L, /RST = H and /SEL = H. All interrupts are disabled by default. Thus, interrupts for state transition control are to be enabled first, e.g. enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state. In P_ON state a first access to the radio transceiver registers is possible after a default 1 MHz master clock is provided at pin 17 (CLKM), refer to tTR1 in Table 5-1. Once the supply voltage has stabilized and the crystal oscillator has settled (see section 10.5, parameter tXTAL), the interrupt mask for the AWAKE_END should be set. A valid SPI write access to register bits TRX_CMD (register 0x02, TRX_STATE) with the command TRX_OFF or FORCE_TRX_OFF initiates a state change from P_ON towards TRX_OFF state, which is then indicated by an AWAKE_END interrupt if enabled. 5.1.2.2 SLEEP – Sleep State In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating. The radio transceiver current consumption is reduced to leakage current and the current of a low power voltage regulator (typ. 100 nA), which provides the supply voltage for the registers such that the contents of them remains valid. This state can only be entered from state TRX_OFF, by setting SLP_TR = H. If CLKM is enabled, the SLEEP state is entered 35 CLKM cycles after the rising edge at pin 11 (SLP_TR). At that time CLKM is turned off. If the CLKM output is already turned off (bits CLKM_CTRL = 0 in register 0x03), the SLEEP state is entered immediately. At clock rates of 250 kHz and symbol clock rate (CLKM_CTRL values 6 and 7, register 0x03, TRX_CTRL_0), the main clock at pin 17 (CLKM) is turned off immediately. Setting SLP_TR = L returns the radio transceiver back to the TRX_OFF state. During SLEEP the register contents remains valid while the content of the Frame Buffer and the security engine (AES) are cleared. /RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see section 7.7.4. 5.1.2.3 TRX_OFF – Clock State In TRX_OFF, the crystal oscillator is running and the master clock is available at pin 17 (CLKM). The SPI interface and digital voltage regulator are enabled, thus the radio transceiver registers, the Frame Buffer and security engine (AES) are accessible (see sections 7.4 and 9.1). In contrast to P_ON state, pull-up and pull-down resistors are disabled. Note that the analog front-end is disabled during TRX_OFF. If TRX_OFF_AVDD_EN (register 0x0C, TRX_CTRL_2) is set, the analog voltage regulator is turned on, enabling faster switch to any transmit/receive state. Entering the TRX_OFF state from P_ON, SLEEP, or RESET state, the state change is indicated by interrupt IRQ_4 (AWAKE_END) if enabled. 31 8168B-MCU Wireless-02/09 5.1.2.4 PLL_ON – PLL State Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first, unless the AVREG is already switched on (register 0x0C, TRX_OFF_AVDD_EN). After the voltage regulator has been settled (see Table 5-2), the PLL frequency synthesizer is enabled. When the PLL has been settled at the receive frequency to a channel defined by register bits CHANNEL (register 0x08, PHY_CC_CCA), CC_NUMBER (register 0x013, CC_CTRL_0), and CC_BAND (register 0x014, CC_CTRL_1), a successful PLL lock is indicated by issuing an interrupt IRQ_0 (PLL_LOCK). After the RX_ON command is issued in PLL_ON state, register bits TRX_STATUS (register 0x01, TRX_STATUS) immediately indicate the radio being in RX_ON state. However, frame reception can only start, once the PLL has locked. The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4. 5.1.2.5 RX_ON and BUSY_RX – RX Listen and Receive State The AT86RF212 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which is always turned on. In both states the receiver and the PLL frequency synthesizer are enabled. During RX_ON state the receiver listens for incoming frames. After detecting a valid synchronization header (SHR), the AT86RF212 automatically enters the BUSY_RX state. The reception of a non-zero PHR field generates an IRQ_2 (RX_START), if enabled. During PSDU reception the frame data are stored continuously in the Frame Buffer until the last byte was received. The completion of the frame reception is indicated by an interrupt IRQ_3 (TRX_END) and the radio transceiver returns the state RX_ON. At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see section 6.3). Received frames are passed to the address match filter, refer to section 6.2. If the content of the MAC addressing fields (refer to IEEE 802.15.4 section 7.2.1) of a frame matches to the expected addresses, which is further dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to 4.7. The expected address values are to be stored in registers 0x20 – 0x2B (Short address, PAN ID and IEEE address). Frame filtering is available in Basic and Extended Operating Mode, refer to section 6.2. Leaving state RX_ON is only possible by writing a state change command to register bits TRX_CMD in register 0x02 (TRX_STATE). 5.1.2.6 RX_ON_NOCLK – RX Listen State without CLKM If the radio transceiver is listening for an incoming frame and the microcontroller is not running an application, the microcontroller may be powered down to decrease the total system power consumption. This specific power-down scenario for systems running in clock synchronous mode (see section 4), is supported by the AT86RF212 using the state RX_ON_NOCLK. This state can only be entered by setting pin 11 (SLP_TR) = H while the radio transceiver is in RX_ON state, refer to chapter 0. Pin 17 (CLKM) is disabled 35 clock cycles after the rising edge at the SLP_TR pin, see Figure 4-16. This allows the microcontroller to complete its power-down sequence. 32 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Note that for CLKM clock rates 250 kHz and symbol clock rates (CLKM_CTRL values 6 and 7; register 0x03, TRX_CTRL_0) the master clock signal CLKM is switched off immediately after rising edge of SLP_TR. The reception of a frame shall be indicated to the microcontroller by an interrupt indicating the receive status. CLKM is turned on again, and the radio transceiver enters the BUSY_RX state (see section 4.6 and Figure 4-16). When using RX_ON_NOCLK, it is essential to enable at least one interrupt request indicating the reception status. After the receive transaction has been completed, the radio transceiver enters the RX_ON state. The radio transceiver only reenters the RX_ON_NOCLK state, when the next rising edge of pin SLP_TR pin occurs. If the AT86RF212 is in the RX_ON_NOCLK state, and pin SLP_TR is reset to logic low, it enters the RX_ON state, and it starts to supply clock on the CLKM pin again. A reset in state RX_ON_NOCLK further requires to reset pin SLP_TR to logic low, otherwise the radio transceiver enters directly the SLEEP state. Note • A reset in state RX_ON_NOCLK further requires to reset pin SLP_TR to logic low, otherwise the radio transceiver enters directly the SLEEP state. 5.1.2.7 BUSY_TX – Transmit State A transmission can only be initiated in state PLL_ON. There are two ways to start a transmission: • Rising edge of pin 11 (SLP_TR) • TX_START command written TRX_STATE). to register bits TRX_CMD (register 0x02, Either of these forces the radio transceiver into the BUSY_TX state. During the transition to BUSY_TX state, the PLL frequency shifts to the transmit frequency. The actual transmission of the first data chip of the SHR starts after 1 symbol period (refer to section 7.1.3) in order to allow PLL settling and PA ramp-up, see Figure 5-6. After transmission of the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame length of zero, the transmission is aborted immediately after the PHR field. After the frame transmission has been completed, the AT86RF212 automatically turns off the power amplifier, generates an IRQ_3 (TRX_END) interrupt and returns into PLL_ON state. 5.1.2.8 RESET State The RESET state is used to set back the state machine and to reset all registers of the AT86RF212 to their default values, exception are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see section 7.7.4. A reset forces the radio transceiver into TRX_OFF state. If, however, the device is in P_ON state it remains in P_ON state. A reset is initiated with pin /RST = L and the state returns after setting /RST = H. The reset pulse should have a minimum length as specified in section 10.4, parameter 10.4.13. 33 8168B-MCU Wireless-02/09 During reset, the microcontroller has to set the radio transceiver control pins SLP_TR and /SEL to their default values. An overview of the register reset values is provided in Table 11-2. 5.1.3 Interrupt Handling All interrupts provided by the AT86RF212 (see Table 4-15) are supported in Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. When being in receive mode, IRQ_2 (RX_START) indicates the detection of a non-zero PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame reception. During transmission IRQ_3 (TRX_END) indicates the completion of the frame transmission. Figure 5-2 shows an example for a transmit/receive transaction between two devices and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame containing a MAC header, MAC payload, and a valid FCS. The end of the frame transmission is indicated by IRQ_3 (TRX_END). The frame is received by Device 2. Interrupt IRQ_2 (RX_START) indicates the detection of a valid PHR field, and IRQ_3 (TRX_END) the completion of the frame reception. If the frame passes the Frame Filter, refer to 6.2, an address match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR). Processing delay tIRQ is a typical value, refer to section 10.4. Figure 5-2. Timing of RX_START, AMI, and TRX_END Interrupts in Basic Operating Mode for O-QPSK 250 kbit/s Mode -tTR10 0 128 160 192 192+(m+n+2)*32 Time [µs] TRX_STATE SLP_TR IRQ Processing Delay PLL_ON BUSY_TX PLL_ON TX (Device1) TRX_END IRQ_3 (TRX_END) tTR10 Frame on Air 4 Preamble 1 SFD 1 PHR m MHR n MSDU 2 FCS Number of Octets Frame Content TRX_STATE IRQ Interrupt latency IRQ_2 (RX_START) IRQ_5 (AMI) tIRQ tIRQ tIRQ 34 AT86RF212 8168B-MCU Wireless-02/09 RX (Device 2) RX_ON BUSY_RX RX_ON AT86RF212 5.1.4 Timing The following paragraphs depict state transitions and their timing properties. Timings are explained in Table 5-1 and section 10.4. 5.1.4.1 Power-on Procedure The power-on procedure during P_ON state is shown in Figure 5-3. Figure 5-3. Power-on Procedure during P_ON State 0 EVDD on P_ON XOSC, DVREG tTR1 100 400 CLKM on Time [µs] Event State Block Time When the external supply voltage (EVDD) is supplied to the AT86RF212, the radio transceiver enables the crystal oscillator (XOSC) and the internal 1.8 V voltage regulator for the digital domain (DVREG). After tTR1, the master clock signal is available at pin 17 (CLKM) at default rate of 1 MHz. If CLKM is available, the SPI has already been enabled and can be used to control the transceiver. 5.1.4.2 Wake-up Procedure The wake-up procedure from SLEEP state is shown in Figure 5-4. Figure 5-4. Wake-up Procedure from SLEEP State 0 SLP_TR = L SLEEP XOSC, DVREG tTR2 100 200 CLKM on IRQ_4 (AWAKE_END) TRX_OFF FTN XOSC, DVREG 400 Time [µs] Event State Block Time The radio transceiver’s SLEEP state is left by releasing pin SLP_TR to logic low. This restarts the XOSC and DVREG. After tTR2, the radio transceiver enters TRX_OFF state. The internal clock signal is available and provided to pin 17 (CLKM), if enabled. This procedure is similar to power-on, however, the radio transceiver automatically ends in TRX_OFF state. During this the filter-tuning network (FTN) calibration is performed. Entering TRX_OFF state is signaled by IRQ_4 (AWAKE_END), if this interrupt was enabled by the appropriate mask register bit. 5.1.4.3 State Change from TRX_OFF to PLL_ON / RX_ON The transition from TRX_OFF to PLL_ON or RX_ON mode and further to RX_ON or PLL_ON is shown in Figure 5-5. 35 8168B-MCU Wireless-02/09 Figure 5-5. Transition from TRX_OFF to PLL_ON/RX_ON State and further to RX_ON/PLL_ON 0 100 IRQ_0 (PLL_LOCK) TRX_OFF AVREG PLL_ON / RX_ON tTR4 / tTR6 PLL RX_ON / PLL_ON tTR8/tTR9 PLL_ON / RX_ON RX_ON / PLL_ON Time [µs] Event State Block Command Time Note: If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately, even if the PLL has not settled. In TRX_OFF state, entering the commands PLL_ON or RX_ON initiates a ramp-up sequence of the internal 1.8 V voltage regulator for the analog domain (AVREG). RX_ON state can be entered any time from PLL_ON state, regardless whether the PLL has already locked, which is indicated by IRQ_0 (PLL_LOCK). Likewise, PLL_ON state can be entered any time from RX_ON state. When TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is already set in TRX_OFF state, the analog voltage regulator is turned on immediately and the ramp up sequence to PLL_ON or RX_ON can be accelerated. 5.1.4.4 State Change from PLL_ON via BUSY_TX to RX_ON States The transition from PLL_ON to BUSY_TX state and subsequently to RX_ON state is shown in Figure 5-6. Figure 5-6. PLL_ON to BUSY_TX to RX_ON Timing for O-QPSK 250 kbit/s Mode 0 16 TRX_CMD=RX_ON x x + 32 Time [µs] Event State Block Time PLL_ON SLP_TR=H or TRX_CMD =TX_START BUSY_TX IRQ_3 (TRX_END) RX_ON TX tTR10 PLL tTR11 RX Starting from PLL_ON, it is further assumed that the PLL has already been locked. A transmission is initiated either by a rising edge of pin 11 (SLP_TR) or by command TX_START. The PLL settles to the transmit frequency and the PA is enabled. After the duration of tTR10 (1 symbol period), the AT86RF212 changes into BUSY_TX state, transmitting the internally generated SHR and the PSDU data of the Frame Buffer. 36 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 After completing the frame transmission, indicated by IRQ_3 (TRX_END), the PLL settles back to the receive frequency within tTR11 and returns to state PLL_ON. If during BUSY_TX the radio transmitter is requested to change to a receive state, it automatically proceeds to state RX_ON upon completion of the transmission, refer to Figure 5-6. 5.1.4.5 Reset Procedure The radio transceiver reset procedure is shown in Figure 5-7. Figure 5-7. Reset Procedure 0 x x + 10 x + 40 [IRQ_4 (AWAKE_END)] any undefined FTN TRX_OFF Time [µs] Event State Block Pin /RST Time t10 t11 tTR13 /RST = L sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0), refer to section 7.7.4. After releasing the reset pin (/RST = H) the wake-up sequence including an FTN calibration cycle is performed, refer to section 7.9. After that the TRX_OFF state is entered. Figure 5-7 illustrates the reset procedure once P_ON state was left and the radio transceiver was not in SLEEP state. The reset procedure is identical for all originating radio transceiver states except of state P_ON and SLEEP state. Instead, the procedures described in section 5.1.2.1 and 5.1.2.2 must be followed to enter the TRX_OFF state. If the radio transceiver was in SLEEP state, the XOSC and DVREG are enabled before entering TRX_OFF state. Notes • The reset impulse should have a minimum length t10 as specified in section 10.4, see parameter 10.4.13. • An access to the device should not occur earlier than t11 after releasing the pin /RST; refer to section 10.4, parameter 10.4.14. • A reset overrides an SPI command that might be queued. 5.1.4.6 State Transition Timing Summary Transition timings are listed in Table 5-1 and do not include SPI access time if not otherwise stated. See measurement setup in Figure 3-1. 37 8168B-MCU Wireless-02/09 Table 5-1. State Transition Timing Symbol tTR1 tTR2 P_ON SLEEP Transition until CLKM available TRX_OFF Time, typ. 330 µs 380 µs Comments Depends on crystal oscillator setup (Siward A207-011, CL = 10 pF) and external capacitor at DVDD (1 µF nom.) Depends on crystal oscillator setup (Siward A207-011, CL = 10 pF) and external capacitor at DVDD (1 µF nom.) TRX_OFF state indicated by IRQ_4 (AWAKE_END) For fCLKM > 250 kHz Depends on external capacitor at AVDD (1 µF nom.); register bit TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is not set Depends on external capacitor at AVDD (1 µF nom.); register bit TRX_OFF_AVDD_EN (register 0x0c, TRX_CTRL_2) is not set tTR3 tTR4 tTR5 tTR6 tTR7 tTR8 tTR9 tTR10 TRX_OFF TRX_OFF PLL_ON TRX_OFF RX_ON PLL_ON RX_ON PLL_ON SLEEP PLL_ON TRX_OFF RX_ON TRX_OFF RX_ON PLL_ON BUSY_TX 35 cycles of CLKM 110 µs 1 µs 110 µs 1 µs 1 µs 1 µs Transition time is also valid for TX_ARET_ON, RX_AACK_ON 1 symbol period When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START first symbol transmission is delayed by 1 symbol period (PLL settling and PA ramp up), refer to section 7.1.3. 32 µs 1 µs 26 µs 1 µs PLL settling time Using TRX_CMD = FORCE_TRX_OFF (see register 0x02, TRX_STATE); not valid for SLEEP state Not valid for P_ON or SLEEP state Using TRX_CMD = FORCE_PLL_ON (see register 0x02, TRX_STATE); not valid for SLEEP, P_ON, RESET, TRX_OFF, and *_NO_CLK tTR11 tTR12 tTR13 tTR14 BUSY_TX All states RESET Various states PLL_ON TRX_OFF TRX_OFF PLL_ON The state transition timing is calculated based on the timing of the individual blocks shown in Figure 5-3 to Figure 5-7. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations, see Table 5-2. Table 5-2. Analog Block Initialization and Settling Times Symbol tTR15 tTR16 tTR17 tTR18 tTR19 tTR20 tTR21 tTR22 tTR23 Block XOSC FTN DVREG AVREG PLL, initial PLL, settling PLL, CF cal. PLL, DCU cal. PLL, RX TX 60 µs 60 µs 96 µs 11 µs 8 µs 10 µs 16 µs Time, typ. 330 µs Time, max. 1000 µs 25 µs 1000 µs 1000 µs 276 µs 42 µs 270 µs Comments Leaving SLEEP state, depends on crystal Q factor and load capacitor Filter tuning time Depends on external bypass capacitor at DVDD (CB3 = 1 µF nom., 10 µF worst case), and on EVDD voltage Depends on external bypass capacitor at AVDD (CB1 = 1 µF nom., 10 µF worst case) , and on EVDD voltage PLL settling time TRX_OFF settling time PLL_ON, including 60 µs AVREG Duration of channel switch within frequency band PLL center frequency calibration, refer to section 7.8.4 PLL DCU calibration, refer to section 7.8.4 PLL settling time RX TX 38 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Symbol tTR24 tTR25 Block PLL, TX RSSI RX Time, typ. 32 µs BPSK-20: 32 µs BPSK-40: 24 µs O-QPSK: 8 µs 8 symbol periods Time, max. Comments PLL settling time TX RX RSSI update period in receive states, refer to section 6.4.2 tTR26 ED ED measurement period, refer to section 6.5 Different timing with High Data Rate Modes, see sections 6.5.5 and 7.1.4.3 CCA measurement period, refer to section 6.6.2 Random value update period, refer to section 9.2.1 tTR28 tTR29 CCA Random value 8 symbol periods 1 µs 5.1.5 Register Description Register 0x01 (TRX_STATUS): A read access to TRX_STATUS register signals the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively, a state transition can be initiated by the rising edge of pin 11 (SLP_TR) in the appropriate state. This register is used for Basic and Extended Operating Mode, refer to section 5.2. Table 5-3. Register 0x01 (TRX_STATUS) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 CCA_DONE R 0 3 TRX_STATUS[3] R 0 6 CCA_STATUS R 0 2 TRX_STATUS[2] R 0 5 Reserved R 0 1 TRX_STATUS[1] R 0 4 TRX_STATUS[4] R 0 0 TRX_STATUS[0] R 0 • Bit 7 – CCA_DONE Refer to section 6.6 • Bit 6 – CCA_STATUS Refer to section 6.6 • Bit 5 – Reserved • Bit 4:0 – TRX_STATUS The register bits TRX_STATUS signal the current radio transceiver status. If the requested state transition is not completed yet, the TRX_STATUS returns STATE_TRANSITION_IN_PROGRESS. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. State transition timings are defined in Table 5-1. Table 5-4. Radio Transceiver Status, Register Bits TRX_STATUS Register Bits TRX_STATUS Value 0x00 0x01 State Description P_ON BUSY_RX 39 8168B-MCU Wireless-02/09 Register Bits Value 0x02 0x06 0x08 0x09 0x0F 0x11 0x12 0x16 (3) (1) (1) (1) State Description BUSY_TX RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) SLEEP BUSY_RX_AACK BUSY_TX_ARET RX_AACK_ON TX_ARET_ON RX_ON_NOCLK RX_AACK_ON_NOCLK BUSY_RX_AACK_NOCLK STATE_TRANSITION_IN_PROGRESS All other values are reserved 0x19(1) 0x1C 0x1D 0x1E 0x1F Notes: (1) (1) (2) 1. Extended Operating Mode only, refer to section 5.2. 2. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. 3. In SLEEP state register not accessible. Register 0x02 (TRX_STATE): Radio transceiver state changes can be initiated by writing register bits TRX_CMD. This register is used for Basic and Extended Operating Mode, refer to section 5.2. Table 5-5. Register 0x02 (TRX_STATE) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 TRAC_STATUS R 0 3 TRX_CMD[3] R/W 0 6 TRAC_STATUS R 0 2 TRX_CMD[2] R/W 0 5 TRAC_STATUS R 0 1 TRX_CMD[1] R/W 0 4 TRX_CMD[4] R/W 0 0 TRX_CMD[0] R/W 0 • Bit 7:5 – TRAC_STATUS Refer to section 5.2.6. • Bit 4:0 – TRX_CMD A write access to register bits TRX_CMD initiates a radio transceiver state transition. Table 5-6. State Control Command, Register Bits TRX_CMD Register Bits TRX_CMD Value 0x00 0x02 0x03 State Transition towards NOP TX_START FORCE_TRX_OFF 40 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Register Bits Value 0x04 0x06 0x08 0x09 0x16 0x19 Notes: (2) (2) (1) State Transition towards FORCE_PLL_ON RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) RX_AACK_ON TX_ARET_ON All other values are reserved and mapped to NOP 1. FORCE_PLL_ON is not valid for states SLEEP, RESET, and all *_NOCLK states, as well as STATE_TRANSITION_IN_PROGRESS towards these states. 2. Extended Operating Mode only, refers to section 5.2.6. 5.2 Extended Operating Mode The Extended Operating Mode is a hardware MAC accelerator and goes beyond the basic radio transceiver functionality provided by the Basic Operating Mode. It handles time critical MAC tasks, requested by the IEEE 802.15.4-2003/2006 standard, such as automatic acknowledgement, automatic CSMA-CA, and retransmission. This results in a more efficient IEEE 802.15.4-2003/2006 software MAC implementation including reduced code size and may allow the use of a smaller microcontroller. The Extended Operating Mode is designed to support IEEE 802.15.4-2003/2006 standard compliant frames and comprises the following procedures: Automatic acknowledgement (RX_AACK transaction) divides into the tasks: • • • • • • Frame reception and automatic FCS check Configurable addressing fields check Interrupt indicating address match Interrupt indicating frame reception, if it passes frame filtering and FCS check Automatic acknowledgment (ACK) frame transmission, if applicable Support of slotted acknowledgment using SLP_TR pin (used for beacon-enabled operation) Automatic CSMA-CA and Retransmission (TX_ARET transaction) divides into the tasks: • • • • • CSMA-CA including automatic CCA retry and random backoff Frame transmission and automatic FCS field generation Reception of ACK frame (if ACK was requested) Automatic retry of transmissions if ACK was expected but not received or accepted Interrupt signaling with transaction status An AT86RF212 state diagram including the Extended Operating Mode states is shown in Figure 5-8. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode. 41 8168B-MCU Wireless-02/09 Figure 5-8. Extended Operating Mode State Diagram P_ON (Power-on after EVDD) XOSC=ON Pull=ON SLEEP (Sleep State) XOSC=OFF Pull=OFF =L SL P_ TR P_ TR =H 3 (from all states) /RST = L FORCE_TRX_OFF 12 TRX_OFF (Clock State) XOSC=ON Pull=OFF SL (all modes except SLEEP) N _O TR 6 SHR Detected Frame End R _T =H X_ OF F RX F OF X_ TR 1 2 13 /RST = H (all modes except P_ON) RESET ON L_ PL 7 5 OF X_ TR F 4 8 BUSY_RX (Receive State) RX_ON (Rx Listen State) RX_ON PLL_ON 9 PLL_ON (PLL State) 14 SLP_TR=H or TX_START 11 10 Frame End BUSY_TX (Transmit State) SHR Detected SL P_ T P SL R =L ON K_ ON TX_ARET_ON FORCE_PLL_ON see notes From TRX_OFF L_ (Rx Listen State) RX _A AC K_ O CLKM=OFF RX _A RX_ON_NOCLK N From TRX_OFF PLL_ON PL AC TX _A R SHR Detected BUSY_RX_AACK Transaction Finished RX_AACK_ON TX_ARET_ON ET _O N SLP_TR=H or TX_START Frame End BUSY_TX_ARET SLP_TR=H SLP_TR=L Frame Accepted BUSY_RX_ AACK_NOCLK CLKM=OFF SHR Detected Frame Rejected RX_AACK_ ON_NOCLK CLKM=OFF Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event Basic Operating Mode States Extended Operating Mode States 42 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 5.2.1 State Control The Extended Operating Modes RX_AACK and TX_ARET are controlled via register bits TRX_CMD (register 0x02, TRX_STATE), which receives the state transition commands. The corresponding states, RX_AACK_ON and TX_ARET_ON, respectively, are to be entered from states TRX_OFF or PLL_ON as illustrated by Figure 5-8. The success of the state change shall be confirmed by reading register 0x01 (TRX_STATUS). RX_AACK - Receive with Automatic ACK A state transition to RX_AACK_ON from PLL_ON or TRX_OFF is initiated by writing the command RX_AACK_ON to register bits TRX_CMD (register 0x02, TRX_STATE). On success reading register 0x01 (TRX_STATUS) returns RX_AACK_ON or BUSY_RX_AACK. The latter one is returned if a frame is currently about being received. The RX_AACK Extended Operating Mode is terminated by writing command PLL_ON to the register bits TRX_CMD. If the AT86RF212 is within a frame receive or acknowledgment procedure (BUSY_RX_AACK) the state change is executed after finish. Alternatively, the commands FORCE_TRX_OFF or FORCE_PLL_ON can be used to cancel the RX_AACK transaction and change into transceiver state TRX_OFF or PLL_ON, respectively. TX_ARET - Transmit with Automatic Retry and CSMA-CA Retry Similarly, a state transition to TX_ARET_ON from PLL_ON or TRX_OFF is initiated by writing command TX_ARET_ON to register bits TRX_CMD (register 0x02, TRX_STATE). The radio transceiver is in the TX_ARET_ON state when register 0x01 (TRX_STATUS) returns TX_ARET_ON. The TX_ARET transaction is actually started with a rising edge of pin 11 (SLP_TR) or by writing the command TX_START to register bits TRX_CMD. The TX_ARET Extended Operating Mode is terminated by writing the command PLL_ON to the register bits TRX_CMD. If the AT86RF212 is within a CSMA-CA, a frame-transmit or an acknowledgment procedure (BUSY_TX_ARET) the state change is executed after finish. Alternatively, the command FORCE_PLL_ON can be used to instantly terminate the TX_ARET transaction and change into transceiver state PLL_ON. Note • A state change request from TRX_OFF to RX_AACK_ON or TX_ARET_ON internally passes the state PLL_ON to initiate the radio transceiver front end. Thus the readiness to receive or transmit data is delayed accordingly (see Table 5-1). In that case it is recommended to use interrupt IRQ_0 (PLL_LOCK) as an indicator. 5.2.2 Configuration As the usage of the Extended Operating Mode is based on Basic Operating Mode functionality only features beyond the basic radio transceiver functionality are described in the following sections. For details of the Basic Operating Mode refer to section 5.1. When using the RX_AACK or TX_ARET modes, the following registers need to be configured. 43 8168B-MCU Wireless-02/09 RX_AACK configuration steps: • Setup Frame Filter: registers 0x20 – 0x2B o Short address, PAN ID and IEEE address • Configure acknowledgement generation registers 0x2C, 0x2E o Handling of Frame Version Subfield o Handling of Pending Data o Automatic or slotted ACK generation • Additional Frame Filtering Properties register 0x17 o Frame Filter Version Control o Characterize the device as PAN coordinator, if required o Promiscuous Mode o Handling of reserved frame types The configuration of Frame Filter is described in section 6.2.1. The addresses for the address match algorithm are to be stored in the appropriate address registers. Additional control of the RX_AACK mode is done with register 0x17 (XAH_CTRL_1) and register 0x2E (CSMA_SEED_1). Configuration examples for different device operating modes and handling of various frame types can be found in section 5.2.3.1. TX_ARET configuration steps: • Enable automatic FCS handling, if necessary • Configure CSMA-CA o MAX_FRAME_RETRIES o MAX_CSMA_RETRIES o CSMA_SEED o MAX_BE, MIN_BE • Configure CCA (see section 6.6) register 0x04 register 0x2C register 0x2C registers 0x2D, 0x2E register 0x2F MAX_FRAME_RETRIES (register 0x2C, XAH_CTRL_0) defines the maximum number of frame retransmissions. The register bits MAX_CSMA_RETRIES (register 0x2C) configure the maximum number of CSMA-CA retries after a busy channel is detected. The CSMA_SEED_0 and CSMA_SEED_1 register bits (registers 0x2D, 0x2E) define a random seed for the backoff time random-number generator in the AT86RF212. The register bits MAX_BE and MIN_BE (register 0x2F) define the maximum and minimum CSMA backoff exponent, respectively. 5.2.3 RX_AACK_ON – Receive with Automatic ACK The RX_AACK Extended Operating Mode handles reception and automatic acknowledgement of IEEE 802.15.4 compliant frames. The general flow of the RX_AACK algorithm is shown in Figure 5-9. Here the gray shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4 compliant frames, refer to 5.2.3.2. All other procedures are exceptions for specific operating modes or frame formats, refer to section 5.2.3.3. 44 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 In RX_AACK_ON state, the AT86RF212 listens for incoming frames. After detecting a non-zero PHR, the AT86RF212 changes into BUSY_RX_AACK state and parses the frame content of the MAC header (MHR), refer to section 6.1.2. If the content of the MAC addressing fields of the received frame (refer to IEEE 802.15.4 frame format, section 7.2.1) passes the frame filter, an address match interrupt IRQ_5 (AMI) is issued. The reference address values are to be stored in registers 0x20 – 0x2B (Short address, PAN ID and IEEE address). The Frame Filter operations are described in detail in section 6.2. Generally, at nodes, configured as a normal device or PAN coordinator, a frame is indicated by interrupt IRQ_3 (TRX_END) if the frame passes the Frame Filter and the FCS is valid. The interrupt is issued after the completion of the frame reception. The microcontroller can then read the frame data. An exception applies if promiscuous mode is enabled; see section 5.2.3.2. In that case, an interrupt IRQ_3 is issued for all frames. During reception, the AT86RF212 parses bit 5 (ACK Request) of the frame control field of the received data or MAC command frame to check if an acknowledgement (ACK) response is expected. In that case and if the frame matches the third level filtering rules (see IEEE 802.15.4-2006, section 7.5.6.2) the radio transceiver automatically generates and transmits an ACK frame and proceeds back to RX_AACK_ON state. By default, the acknowledgment frame is transmitted aTurnaroundTime (12 symbols, see IEEE 802.15.4, section 6.4.1) after the reception of the last symbol of a data or MAC command frame. Optionally, for non-compliant networks this delay can be reduced to 2 symbols by register bit AACK_ACK_TIME (register 0x2E, XAH_CTRL_1). The content of the frame pending subfield of the ACK response is set according to register bit AACK_SET_PD (register 0x2E, CSMA_SEED_1). The sequence number is copied from the received frame accordingly. If the register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) is set, no acknowledgement frame is sent, even if requested. For slotted operation, the start of the transmission of acknowledgement frames is controlled by pin 11 (SLP_TR), refer to 5.2.3.5. The status of the RX_AACK transaction is indicated by register subfield TRAC_STATUS (register 0x02, TRX_STATE). Table 5-7 lists corresponding values. Table 5-7. RX_AACK interpretation of TRAC_STATUS Register Bits Value 0 2 Name SUCCESS SUCCESS_WAIT_FOR_ACK Description The transaction has finished with success The transaction either waits aTurnaroundTime symbols until the ACK is transmitted or expects the rising edge on pin 11 (SLP_TR) to start the transmission (slotted operation) Default value, when RX_AACK transaction is invoked 7 INVALID Note that generally the AT86RF212 PHY modes as well as the Extended Feature Set work independent from RX_AACK Extended Operating Mode. 45 8168B-MCU Wireless-02/09 Figure 5-9. Flow Diagram of RX_AACK TRX_STATE = RX_AACK_ON, TRAC_STATUS = INVALID Detect SHR TRX_STATE = BUSY_RX_AACK Issue IRQ_2 (RX_START) Scan MHR Note 1: Address match, Promiscuous Mode and Reserved Frames: - A radio transceiver in promiscuous mode or configured to receive reserved frames handles received frames passing the third level of filtering - for details refer to the descritption of Promiscuous Mode and Reserved Frame Types Promiscuous Mode Reserved Frames Address match? Y Îssue IRQ_5 (AMI) N AACK_PROM_MODE == 1 ? Y N FCF[2:0] >3? Y Receive PSDU Receive PSDU Receive PSDU N FCS valid || AACK_PROM_MODE ? Y Issue IRQ_3 (TRX_END) N AACK_UPLD_RES_FT == 1 ? Y N FCS valid ? Y N Note 2: Additional conditions: - ACK requested & - ACK_DIS_ACK==0 & - frame_version MAX_CSMA_RETRIES ? Y ACK requested ? Y ACK receive until timeout Y N frm_ctr > MAX_FRAME_RETRIES ? N ACK valid? Y N Y Data Pending ? N TRAC_STATUS = NO_ACK TRAC_STATUS = SUCCESS_DATA_PENDING TRAC_STATUS = SUCCESS TRAC_STATUS = CHANNEL_ACCESS_FAILURE Issue IRQ_3 (TRX_END) TRX_STATE = TX_ARET_ON 55 8168B-MCU Wireless-02/09 Table 5-15. TX_ARET Interpretation of TRAC_STATUS Register Bits Value 0 Name SUCCESS Description The transaction was responded by a valid ACK, or, if no ACK is requested, after a successful frame transmission. Equivalent to SUCCESS and indicating that the Frame Pending bit (see section 6.1.2.2) of the received acknowledgment frame was set. Channel is still busy after MAX_CSMA_RETRIES of CSMA-CA. No acknowledgement frame was received during all retry attempts. Entering TX_ARET mode until IRQ_3 (TRX_END). 1 SUCCESS_DATA_PENDING 3 5 7 CHANNEL_ACCESS_FAILURE NO_ACK INVALID A value of MAX_CSMA_RETRIES = 7 initiates an immediate TX_ARET transaction without performing CSMA-CA. This supports beacon-enabled network operation. Furthermore by ignoring the value of MAX_FRAME_RETRIES only a single attempt is made to transmit the frame. Note that the acknowledgment receive procedure does not overwrite the Frame Buffer content. Transmit data in the Frame Buffer is not modified during the entire TX_ARET transaction. Received frames other than the expected ACK frame are discarded automatically. 5.2.4.1 Acknowledgment Timeout If an acknowledgment (ACK) frame is expected after frame transmission, the AT86RF212 sets a timeout until which a valid ACK frame must have been arrived. This timeout macAckWaitDuration is defined according to [1] as follows: macAckWaitDuration [symbol periods] = aUnitBackoffPeriod + aTurnaroundTime + phySHRDuration + 6 · phySymbolsPerOctet, where 6 represents the number of PHY header octets plus the number of PSDU octets in an acknowledgment frame. Specifically for the implemented PHY Modes (see section 7.1), this formula results in the following values: • • BPSK: O-QPSK: macAckWaitDuration = 120 symbol periods macAckWaitDuration = 54 symbol periods Note that for any PHY Mode the unit [symbol period] refers to the symbol duration of the appropriate synchronization header, see section 7.1.3 for further information regarding symbol period. 5.2.4.2 Timing A timing example of a TX_ARET transaction is shown in Figure 5-13. In the example shown, a data frame with an acknowledgment request is to be transmitted. The frame 56 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 transmission is started by pin 11 (SLP_TR). As MIN_BE is set to zero, the initial CSMACA backoff period has length zero too. Thus the CSMA-CA duration time tCSMA-CA only consists of 8 symbols of CCA measurement period. If CCA returns IDLE (assumed here), the frame is transmitted. After that, the AT86RF212 switches to receive mode and expects an acknowledgement response, which is indicated by register subfield TRAC_STATUS (register 0x02, TRX_STATE) set to SUCCESS_WAIT_FOR_ACK. After a period of aTurnaroundTime + aUnitBackoff the transmission of the ACK frame must have started. During the entire transaction including frame transmit, wait for ACK and ACK receive, the radio transceiver status register TRX_STATUS (register 0x01, TRX_STATUS) signals BUSY_TX_ARET. A successful reception of the acknowledgment frame is indicated by interrupt IRQ_3 (TRX_END). The status register TRX_STATUS (register 0x01, TRX_STATUS) changes back to TX_ARET_ON. At the same time, register TRAC_STATUS changes to SUCCESS or to SUCCESS_DATA_PENDING, if the frame pending subfield of the acknowledgment frame was set to 1. Figure 5-13. Example Timing of a TX_ARET Transaction (without Pending Data Bit set in ACK Frame) time FrameType Data Frame (ACK=1) ACK Frame ACK start timeout 20 symbols TRX_STATE RX/TX SLP_TR IRQ Typ. Delays TX_ARET_ON CSMA-CA TX BUSY_TX_ARET RX RX 32 µs TX_ARET_ON TRX_END tCSMA-CA (8 symbols) 16 µs aTurnaroundTime (12 symbols) tIRQ TRAC_STATUS SUCC. / INVALID INVALID SUCCESS Register settings: 0x2C: MAX_FRAME_RETRIES=0 0x2C: MAX_CSMA_RETRIES=0 0x2E: MIN_BE=0 5.2.5 Interrupt Handling The interrupt handling in the Extended Operating Mode is similar to the Basic Operating Mode. Interrupts can be enabled by setting the appropriate bit in register 0x0E (IRQ_MASK). For RX_AACK and TX_ARET the following interrupts inform about the status of a frame reception and transmission: • IRQ_2 (RX_START) • IRQ_3 (TRX_END) • IRQ_5 (AMI) For RX_AACK mode, it is recommended to enable only interrupt IRQ_3 (TRX_END). This interrupt is issued only if the Frame Filter (see section 6.2) reports a matching address and the FCS is valid (see section 6.3). The usage of other interrupts is optional. 57 8168B-MCU Wireless-02/09 Frame on Air On reception of a frame, the RX_START interrupt indicates the detection of a correct synchronization header (SHR) and a non-zero PHY header (PHR). This interrupt is issued after the PHR. AMI indicates address match, refer to filter rules in section 6.2. The TRX_END interrupt is always generated after completing a TX_ARET transaction. After that, the return code can be read from subfield TRAC_STATUS (register 0x02, TRX_STATE). Several interrupts are automatically suppressed by the radio transceiver during TX_ARET transaction. In contrast to section 6.6, the CCA algorithm (part of CSMA-CA) does not generate interrupt IRQ_4 (CCA_ED_DONE). Furthermore, the interrupts RX_START and AMI are not generated during the TX_ARET acknowledgment receive process. 5.2.6 Register Description Register Summary The following registers control the Extended Operating Mode: Table 5-16. Register Summary Reg.-Addr. 0x01 0x02 0x04 0x08 0x09 0x17 0x20 – 0x2B Register Name TRX_STATUS TRX_STATE TRX_CTRL_1 PHY_CC_CCA CCA_THRES XAH_CTRL_1 Description Radio transceiver status, CCA result Radio transceiver state control, TX_ARET status TX_AUTO_CRC_ON CCA mode control, see section 6.6.6 CCA ED threshold settings, see section 6.6.6 RX_AACK control Frame Filter configuration - Short address, PAN ID and IEEE address - See section 6.2.3 XAH_CTRL_0 CSMA_SEED_0 CSMA_SEED_1 CSMA_BE TX_ARET control, retries value control CSMA-CA seed value CSMA-CA seed value, RX_AACK control CSMA-CA backoff exponent control 0x2C 0x2D 0x2E 0x2F Register 0x01 (TRX_STATUS): The read-only register TRX_STATUS provides the current state of the radio transceiver. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Table 5-17. Register 0x01 (TRX_STATUS) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 CCA_DONE R 0 3 TRX_STATUS[3] R 0 6 CCA_STATUS R 0 2 TRX_STATUS[2] R 0 5 Reserved R 0 1 TRX_STATUS[1] R 0 4 TRX_STATUS[4] R 0 0 TRX_STATUS[0] R 0 58 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 • Bit 7 – CCA_DONE Refer to section 6.6, not updated in Extended Operating Mode • Bit 6 – CCA_STATUS Refer to section 6.6, not updated in Extended Operating Mode • Bit 5 – Reserved • Bit 4:0 – TRX_STATUS The register bits TRX_STATUS signals the current radio transceiver status. Table 5-18. Radio Transceiver Status Register Bits TRX_STATUS Value 0x00 0x01 0x02 0x06 0x08 0x09 0x0F(1) 0x11 0x12 0x16 0x19 0x1C 0x1D 0x1E 0x1F(2) Notes: State Description P_ON BUSY_RX BUSY_TX RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) SLEEP BUSY_RX_AACK BUSY_TX_ARET RX_AACK_ON TX_ARET_ON RX_ON_NOCLK RX_AACK_ON_NOCLK BUSY_RX_AACK_NOCLK STATE_TRANSITION_IN_PROGRESS All other values are reserved 1. In SLEEP state registers are not accessible. 2. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. Register 0x02 (TRX_STATE): The AT86RF212 radio transceiver states are controlled via register TRX_STATE using register bits TRX_CMD. A successful state transition shall be confirmed by reading register bits TRX_STATUS (register 0x01, TRX_STATUS). The read-only register bits TRAC_STATUS indicate the status or result of an Extended Operating Mode transaction. Table 5-19. Register 0x02 (TRX_STATE) Bit Name Read/Write Reset Value 7 TRAC_STATUS[2] R 0 6 TRAC_STATUS[1] R 0 5 TRAC_STATUS[0] R 0 4 TRX_CMD[4] R/W 0 59 8168B-MCU Wireless-02/09 Bit Name Read/Write Reset Value 3 TRX_CMD[3] R/W 0 2 TRX_CMD[2] R/W 0 1 TRX_CMD[1] R/W 0 0 TRX_CMD[0] R/W 0 • Bit 7:5 – TRAC_STATUS The status of the RX_AACK and TX_ARET procedure is indicated by register bits TRAC_STATUS. Details of the algorithm and a description of the status information are given in sections 5.2.3 and 5.2.4. Table 5-20. TRAC_STATUS Transaction Status Register Bits TRAC_STATUS Value 0 1 2 3 5 7(1) Note: (1) Description SUCCESS SUCCESS_DATA_PENDING SUCCESS_WAIT_FOR_ACK CHANNEL_ACCESS_FAILURE NO_ACK INVALID All other values are reserved RX_AACK X X TX_ARET X X X X X X 1. Even though the reset value for register bits TRAC_STATUS is 0, the RX_AACK and TX_ARET procedures set the register bits to TRAC_STATUS = 7 (INVALID) when it is started. • Bit 4:0 – TRX_CMD A write access to register bits TRX_CMD initiates a radio transceiver state transition: Table 5-21. State Control Register Register Bits TRX_CMD Value 0x00 0x02 0x03 0x04 0x06 0x08 0x09 0x16 0x19 Note: (1) State Description NOP TX_START FORCE_TRX_OFF FORCE_PLL_ON RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) RX_AACK_ON TX_ARET_ON All other values are reserved and mapped to NOP 1. FORCE_PLL_ON is not valid for states SLEEP, P_ON, RESET, TRX_OFF, and all *_NOCLK states, as well as STATE_TRANSITION_IN_PROGRESS towards these states. Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver. 60 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 5-22. Register 0x04 (TRX_CTRL_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 PA_EXT_EN R/W 0 3 SPI_CMD_MODE R/W 0 6 IRQ_2_EXT_EN R/W 0 2 SPI_CMD_MODE R/W 0 5 TX_AUTO_CRC_ON 4 RX_BL_CTRL R/W 0 0 IRQ_POLARITY R/W 0 R/W 1 1 SPI_CMD_MODE R/W 0 • Bit 7 – PA_EXT_EN Refer to section 9.4. • Bit 6 – IRQ_2_EXT_EN Refer to section 9.5. • Bit 5 – TX_AUTO_CRC_ON If set, register bit TX_AUTO_CRC_ON enables the automatic FCS generation. For further details refer to section 6.3. • Bit 4 – RX_BL_CTRL Refer to section 9.6. • Bit 3:2 – SPI_CMD_MODE Refer to section 4.4.1. • Bit 1 – IRQ_MASK_MODE Refer to section 4.7. • Bit 0 – IRQ_POLARITY Refer to section 4.7. Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a control register for Extended Operating Mode. Table 5-23. Register 0x17 (XAH_CTRL_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 Reserved R/W 0 3 Reserved R 0 6 CSMA_LBT_MODE R/W 0 2 AACK_ACK_TIME R/W 0 5 AACK_FLTR_RES_FT 4 AACK_UPLD_RES_FT R/W 0 1 AACK_PROM_MODE R/W 0 0 Reserved R 0 R/W 0 • Bit 7 – Reserved • Bit 6 – CSMA_LBT_MODE Refer to section 6.7.3. 61 8168B-MCU Wireless-02/09 • Bit 5 – AACK_FLTR_RES_FT This register bit shall only be set if AACK_UPLD_RES_FT = 1. If AACK_FLTR_RES_FT = 1, reserved frame types are filtered like data frames as specified in IEEE 802.15.4-2006. Reserved frame types are explained in IEEE 802.15.4 section 7.2.1.1.1. Interrupt IRQ_5 (AMI) is issued upon passing the frame filter, see section 6.2. If AACK_FLTR_RES_FT = 0, the received reserved frame is only checked for a valid FCS. • Bit 4 – AACK_UPLD_RES_FT If AACK_UPLD_RES_FT = 1, received frames marked as reserved frames are further processed. For these frames, interrupt IRQ_3 (TRX_END) is generated, if the FCS is valid. In conjunction with the configuration bit AACK_FLTR_RES_FT set, these frames are handled like IEEE 802.15.4 compliant data frames during RX_AACK transaction. Otherwise, if AACK_UPLD_RES_FT = 0, frames with a reserved frame type are blocked. • Bit 3 – Reserved • Bit 2 – AACK_ACK_TIME According to IEEE 802.15.4, section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is achieved with the reset value of the register bit AACK_ACK_TIME. Alternatively, if AACK_ACK_TIME = 1, the acknowledgment response time is reduced according to Table 5-24. Table 5-24. Short ACK Response Time (AACK_ACK_TIME = 1) PHY Mode BPSK-20, OQPSK-{100,200,400} BPSK-40, OQPSK-{250,500,1000} ACK response time [symbol periods] 2 3 The reduced ACK response time is particularly useful for the High Data Rate Modes, refer to section 7.1.4. • Bit 1 – AACK_PROM_MODE Register bit AACK_PROM_MODE enables the promiscuous mode, within the RX_AACK mode; refer to IEEE 802.15.4-2006 section 7.5.6.5. If this bit is set, incoming frames with a valid PHR generate interrupt IRQ_3 (TRX_END) even if the third level filter rules do not match or the FCS is not valid. However, register bit RX_CRC_VALID (register 0x06) is set accordingly. If a frame passes the third level filter rules, an acknowledgement frame is generated and transmitted unless disabled by register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1). • Bit 0 – Reserved Register 0x2C (XAH_CTRL_0): Register 0x2C (XAH_CTRL_0) is a control register for Extended Operating Mode. 62 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 5-25. Register 0x2C (XAH_CTRL_0) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 1 0 0 3 0 2 7 6 5 MAX_FRAME_RETRIES[3:0] R/W 1 1 1 0 SLOTTED_OPERATION 4 MAX_CSMA_RETRIES[2:0] R/W 0 R/W 0 • Bit 7:4 – MAX_FRAME_RETRIES The setting of MAX_FRAME_RETRIES specifies the number of attempts in TX_ARET mode to automatically retransmit a frame, when it was not acknowledged by the recipient. • Bit 3:1 – MAX_CSMA_RETRIES MAX_CSMA_RETRIES specifies the number of retries in TX_ARET mode to repeat the CSMA-CA procedure before the transaction gets cancelled. According to IEEE 802.15.4, the valid range of MAX_CSMA_RETRIES is [0, 1, …, 5]. A value of MAX_CSMA_RETRIES = 7 initiates an immediate frame transmission without performing CSMA-CA. This may especially be required for slotted acknowledgement operation. MAX_CSMA_RETRIES = 6 is reserved. • Bit 0 – SLOTTED_OPERATION If set, register bit SLOTTED_OPERATION enables RX_AACK acknowledgment generation in slotted operation mode, refer to section 5.2.3.5. Using RX_AACK mode in networks operating in beacon or slotted mode, refer to IEEE 802.15.4-2006, section 5.5.1, register bit SLOTTED_OPERATION indicates that acknowledgement frames are to be sent on backoff slot boundaries (slotted acknowledgement). If this register bit is set, the acknowledgement frame transmission is initiated by the microcontroller, using the rising edge of pin 11 (SLP_TR). Register 0x2D (CSMA_SEED_0): The CSMA_SEED_0 register is a control register for TX_ARET and contains a part of the CSMA seed for the CSMA-CA algorithm. Table 5-26. Register 0x2D (CSMA_SEED_0) Bit Name Read/Write Reset Value 1 1 1 0 7 6 5 4 3 2 1 0 CSMA_SEED[7:0] R/W 1 0 1 0 • Bit 7:0 – CSMA_SEED This register contains the lower 8 bit of the CSMA_SEED, bits [7:0]. The higher 3 bit are part of register bits CSMA_SEED_1 (register 0x2E, CSMA_SEED_1). CSMA_SEED is 63 8168B-MCU Wireless-02/09 the seed for the random number generation that determines the length of the backoff period in the CSMA-CA algorithm. It is recommended to initialize registers CSMA_SEED with random values. This can be done using register bits RND_VALUE (register 0x06, PHY_RSSI), refer to section 9.2. Register 0x2E (CSMA_SEED_1): The CSMA_SEED_1 register contains a part of the CSMA seed for the CSMA-CA algorithm, as well as control bits for the Frame Filter and RX_AACK transaction. Table 5-27. Register 0x2E (CSMA_SEED_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 AACK_FVN_MODE R/W 0 3 AACK_I_AM_COORD 6 AACK_FVN_MODE R/W 1 2 CSMA_SEED[10] R/W 0 5 AACK_SET_PD R/W 0 1 CSMA_SEED[9] R/W 1 4 AACK_DIS_ACK R/W 0 0 CSMA_SEED[8] R/W 0 R/W 0 • Bit 7:6 – AACK_FVN_MODE The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of AACK_FVN_MODE specifies the frame filtering and acknowledgement behavior of the AT86RF212. According to the content of these register bits the radio transceiver passes frames with a specific frame version number, number group, or independent of the frame version number. Thus the register bit AACK_FVN_MODE defines the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the Frame Filter and thus are not acknowledged. Table 5-28. Frame Version Subfield dependent Frame Acknowledgment Register Bits AACK_FVN_MODE Value 0 1 2 3 Description Acknowledge frames with version number 0 Acknowledge frames with version number 0 or 1 Acknowledge frames with version number 0 or 1 or 2 Acknowledge independent of frame version number Note that the frame version field of the acknowledgment frame is set to 0x00 according to IEEE 802.15.4-2006, section 7.2.2.3.1 Acknowledgment frame MHR fields. • Bit 5 – AACK_SET_PD The content of AACK_SET_PD bit is copied into the frame pending subfield of the acknowledgment frame if the ACK is the answer to a data request MAC command frame. In addition, if register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) are configured to accept frames with a frame version other than 0 or 1, the content of register bit AACK_SET_PD is also copied into the frame pending subfield of the acknowledgment frame for any MAC command frame with a frame version of 2 or 3 that 64 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 have the security enabled subfield set to 1. This is done in the assumption that a future version of the standard [1] might change the length or structure of the auxiliary security header, so it would not possible to safely detect whether the MAC command frame is actually a data request command or not. • Bit 4 – AACK_DIS_ACK If this bit is set, no acknowledgment frames are transmitted in RX_AACK Extended Operating Mode, even if requested. • Bit 3 – AACK_I_AM_COORD This register bit has to be set if the node is a PAN coordinator. It is used for frame filtering in RX_AACK. If I_AM_COORD = 1 and if only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId, for details refer to IEEE 802.15.4, section 7.5.6.2 (third-level filter rule 6). • Bit 2:0 – CSMA_SEED These register bits are the higher 3-bit of the CSMA_SEED, bits [10:8]. The lower part is in register 0x2D (CSMA_SEED_0), see register CSMA_SEED_0 for details. Register 0x2F (CSMA_BE): Table 5-29. Register 0x2F (CSMA_BE) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 MAX_BE[3] R/W 0 3 MIN_BE[3] R/W 0 6 MAX_BE[2] R/W 1 2 MIN_BE[2] R/W 0 5 MAX_BE[1] R/W 0 1 MIN_BE[1] R/W 1 4 MAX_BE[0] R/W 1 0 MIN_BE[0] R/W 1 • Bit 7:4 – MAX_BE Register bits MAX_BE defines the maximum value of the backoff exponent in the CSMA-CA algorithm. It equals macMaxBE, refer to [1], section 7.5.1.4, Table 71. Valid values are [4’d8, 4’d7, … , 4’d3]. • Bit 3:0 – MIN_BE Register bits MIN_BE defines the minimum value of the backoff exponent in the CSMACA algorithm. It equals to macMinBE, refer to [1], section 7.5.1.4, Table 71. Valid values are [MAX_BE, (MAX_BE – 1), … , 4’d0]. Note • If MIN_BE = 0 and MAX_BE = 0, the CCA backoff period is always set to 0. 65 8168B-MCU Wireless-02/09 6 Functional Description 6.1 Introduction – IEEE 802.15.4-2006 Frame Format Figure 6-1 provides an overview of the physical layer (PHY) frame structure as defined by the IEEE 802.15.4-2006 standard. Figure 6-2 shows the medium access control layer (MAC) frame structure. Figure 6-1. IEEE 802.15.4 Frame Format – PHY Layer Frame Structure PHY Protocol Data Unit (PPDU) Preamble Sequence 5 octets Synchronization Header (SHR) SFD Frame Length 1 octet (PHR) PHY Payload max. 127 octets PHY Payload PHY Service Data Unit (PSDU) MAC Protocol Data Unit (MPDU) 6.1.1 PHY Protocol Data Unit (PPDU) 6.1.1.1 Synchronization Header (SHR) The SHR consists of a four-octet preamble field (all zero), followed by a single octet start-of-frame delimiter (SFD). During transmit, the SHR is automatically generated by the AT86RF212, thus the Frame Buffer shall contain PHR and PSDU only, see section 4.3.2. The transmission of the SHR requires 40 symbols for a transmission with BPSK modulation and 10 symbols for a transmission with O-QPSK modulation, respectively. Table 6-1 illustrates the SHR duration depending on the selected data rate, see also section 10.5. As the SPI data rate is usually higher than the over-the-air data rate, this allows the microcontroller to initiate a transmission before the frame buffer write access is completed. During frame reception, the SHR is used for synchronization purposes. The matching SFD determines the beginning of the PHR and the following PSDU payload data. 6.1.1.2 PHY Header (PHR) The PHY header is a single octet following the SHR. The least significant 7 bits denote the frame length of the following PSDU, while the most significant bit of that octet is reserved, and shall be set to 0 for IEEE 802.15.4 compliant frames. Even though the MSB is reserved, AT86RF212 is able to transmit and receive this bit. In transmit mode, the PHR needs to be supplied as the first octet during Frame Buffer write access, see section 4.3.2. In receive mode, the PHR is returned as the first octet during Frame Buffer read access, see section 4.3.2. 6.1.1.3 PHY Payload (PHY Service Data Unit, PSDU) The PSDU has a variable length between one and 127 octets. The PSDU contains the MAC protocol data unit (MPDU), where the last two octets are used for the Frame Check Sequence (FCS), see section 6.3. 66 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 6.1.1.4 Timing Summary Table 6-1 shows timing information for the above mentioned frame structure depending on the selected data rate. Table 6-1. PPDU Timing PHY Mode PSDU Bit Rate [kbit/s] 20 40 O-QPSK O-QPSK (1) Header Bit Rate [kbit/s] 20 40 100 250 100 100 250 250 Duration SHR [µs] 2000 1000 300 160 300 300 160 160 PHR [µs] 400 200 80 32 80 80 32 32 Max. PSDU [ms] 50.8 25.4 10.16 4.064 5.08 2.54 2.032 1.016 BPSK (1) 100 250 200 400 500 1000 (2) Notes: 1. Compliant to IEEE 802.15.4-2006, see [1] 2. High Data Rate Modes, see chapter 7.1.4 6.1.2 MAC Protocol Data Unit (MPDU) Figure 6-2 shows the frame structure of the MAC layer. Figure 6-2. IEEE 802.15.4-2006 Frame Format – MAC Layer Frame Structure MAC Protocol Data Unit (MPDU) FCF Sequence Number Addressing Fields MAC Header (MHR) MAC Payload MAC Service Data Unit (MSDU) FCS (MFR) Destination PAN ID Destination Source address PAN ID 0/4/6/8/10/12/14/16/18/20 octets Source address Auxiliary Security Header 0/5/6/10/14 octets CRC-16 2 octets 0 1 Frame Type 2 3 Security Enabled 4 Frame Pending 5 ACK Request 6 7 8 9 10 11 12 13 14 15 PAN ID Reserved Compr. Frame Control Field 2 octets Destination Addressing Mode Frame Version Source Addressing Mode 6.1.2.1 MAC Header (MHR) The MAC header consists of the Frame Control Field (FCF), a sequence number, and the addressing fields of variable length. 6.1.2.2 Frame Control Field (FCF) The FCF occupies the first two octets of the MPDU. Bit [2:0]: describe the “Frame Type”. Table 6-2 summarizes frame types defined by [1], section 7.2.1.1.1. 67 8168B-MCU Wireless-02/09 Table 6-2. Frame Type Field Frame Type Value b2 b1 b0 000 001 010 011 100 – 111 Value 0 1 2 3 4–7 Beacon Data Acknowledge MAC command Reserved Description These bits are used for frame filtering by the third level filter rules, refer to section 7.2.1.1.1 of [1]. Bit 3 indicates whether security processing applies to this frame. This field is evaluated by the Frame Filter. Bit 4 is the “Frame Pending” subfield. This field can be set in an acknowledgment frame to indicate to the node receiving the acknowledgment frame that the node sent the acknowledgment frame has more data to send. Bit 5 forms the “Acknowledgment Request” subfield. If this bit is set within a data or MAC command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time specified by IEEE 802.15.4 (i.e. within 12 symbols for nonbeacon-enabled networks). Bit 6: The “PAN ID Compression” subfield indicates that in a frame where both the destination and source addresses are present, the PAN ID is omitted from the source addressing field. This bit is evaluated by the Frame Filter of the AT86RF212. Bit [9:7]: Reserved Bit [11:10]: The “Destination Addressing Mode” subfield describes the format of the destination address of the frame. The values of the address modes are summarized in Table 6-3, according to IEEE 802.15.4: Table 6-3. Destination and Source Addressing Mode Addressing Mode Value b11 b10 00 01 10 11 Value 0 1 2 3 PAN identifier and address fields are not present. Reserved Address field contains a 16-bit short address. Address field contains a 64-bit extended address. Description If the destination address mode is either 2 or 3, i.e. if the destination address is present, the addressing field consists of a 16-bit PAN ID first, followed by either the 16-bit or 64bit address as defined by the mode. Bit [13:12]: The “Frame Version” subfield specifies the version number corresponding to the frame, see Table 6-4. These bits are reserved in IEEE-802.15.4-2003. This subfield shall be set to 0x00 to indicate a frame compatible with IEEE 802.15.4-2003 and 0x01 to indicate an IEEE 802.15.4 frame. All other subfield values shall be reserved for future use. See [1], section 7.2.3 for details on frame compatibility. 68 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 6-4. Frame Version Field Frame Version Value b13 b12 00 01 10 11 Value 0 1 2 3 Frames are compatible with IEEE 802.15.4-2003 Frames are compatible with IEEE 802.15.4-2006 Reserved Reserved Description Bit [15:14] is the “Source Addressing Mode” subfield, with similar meaning as “Destination Addressing Mode”. The addressing field description bits of the FCF (Bits 0–2, 3, 6, 10–15) affect the AT86RF212 Frame Filter, see section 6.2. 6.1.2.3 Frame Compatibility between IEEE 802.15.4 Rev. 2003 and 2006 All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003, with two exceptions: a coordinator realignment command frame with the Channel Page field present (see [1], section 7.3.8) and any frame with a MAC Payload field larger than aMaxMACSafePayloadSize octets. Compatibility for secured frames is shown in Table 6-5, which identifies the security operating modes for IEEE 802.15.4-2003 and IEEE 802.15.4-2006. Table 6-5. Frame Compatibility Frame Control Field Bit Assignments Security Enabled b3 0 0 1 Frame Version b13 b12 00 01 00 No security. Frames are compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006. No security. Frames are not compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006. Secured frame formatted according to IEEE 802.15.4-2003. This type of frame is not supported in IEEE 802.15.4-2006. Secured frame formatted according to IEEE 802.15.4-2006 Description 1 01 6.1.2.4 Sequence Number The one-octet sequence number following the FCF identifies a particular frame, so that duplicated frame transmissions can be detected. While operating in RX_AACK states, the received frame content of this field is copied into the acknowledgment frame. 6.1.2.5 Addressing Fields The addressing field carries several addresses used for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the PAN ID and a device address. If both addresses are present, and the “PAN ID compression” subfield in the FCF is set to one, the source PAN ID is omitted. 69 8168B-MCU Wireless-02/09 Note that in addition to these general rules, IEEE 802.15.4 further restricts the valid address combinations for the different MAC frame types. For example, the situation where both addresses are omitted (source addressing mode = 0 and destination addressing mode = 0) is only allowed for acknowledgment frames. The Frame Filter in the AT86RF212 has been designed to apply to IEEE 802.15.4 compliant frames. It can be configured to handle other frame formats and exceptions. 6.1.2.6 Auxiliary Security Header The Auxiliary Security Header terminates the MHR. This field has a variable length and specifies information required for security processing, including how the frame is actually protected (security level) and which keying material from the MAC security PIB is used (see [1], section 7.6.1). This field shall be present only if the Security Enabled subfield b3, see 6.1.2.3, is set to one. For details on formatting, see 7.6.2 of [1]. 6.1.2.7 MAC Service Data Unit (MSDU) This is the actual MAC payload. It is usually structured according to the individual frame type descriptions in IEEE 802.15.4 standard. 6.1.2.8 MAC Footer (MFR) The MAC footer consists of a two-octet Frame Checksum (FCS), for details refer to section 6.3. 6.2 Frame Filter Frame Filtering is a procedure that evaluates whether or not a received frame matches predefined criteria, like source or destination address or frame types. A filtering procedure as described in IEEE 802.15.4-2006 chapter 7.5.6.2 (third level of filtering) is applied to the frame to accept a received frame and to generate the address match interrupt IRQ_5 (AMI). The AT86RF212 Frame Filter passes only frames that satisfy all of the following requirements/rules (quote from IEEE 802.15.4-2006, 7.5.6.2): 1. The Frame Type subfield shall not contain a reserved frame type. 2. The Frame Version subfield shall not contain a reserved value. 3. If a destination PAN identifier is included in the frame, it shall match macPANId or shall be the broadcast PAN identifier (0xFFFF). 4. If a short destination address is included in the frame, it shall match either macShortAddress or the broadcast address (0xFFFF). Otherwise, if an extended destination address is included in the frame, it shall match aExtendedAddress. 5. If the frame type indicates that the frame is a beacon frame, the source PAN identifier shall match macPANId unless macPANId is equal to 0xffff, in which case the beacon frame shall be accepted regardless of the source PAN identifier. 6. If only source addressing fields are included in a data or MAC command frame, the frame shall be accepted only if the device is the PAN coordinator and the source PAN identifier matches macPANId. Moreover the AT86RF212 has two additional requirements: 7. The frame type shall indicate that the frame is not an acknowledgment (ACK) frame. 8. At least one address field must be configured. 70 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Address matching, indicated by interrupt IRQ_5 (AMI), is furthermore controlled by the FCF of a received frame according to the following rule: If Destination Addressing Mode is 0/1 and Source Addressing Mode is 0, see section 6.1.2.2, no interrupt IRQ_5 is generated. This causes that no acknowledgement frame is announced. For backward compatibility with IEEE 802.15.4-2003, the third level filter rule 2 (Frame Version) can be disabled by register bits AACK_FVN_MODE (register 0x2E, CSMA_SEED_1). Frame filtering is available in Extended and Basic Operating Modes. A frame that passes the Frame Filter generates the interrupt IRQ_5 (AMI), if not masked. Notes • Filter rule 1 is affected by register bits AACK_FLTR_RES_FT AACK_UPLD_RES_FT, see section 6.2.3. • Filter rule 2 is affected by register bits AACK_FVN_MODE, see section 6.2.3. 6.2.1 Configuration and The Frame Filter is configured by setting the appropriate address variables and several additional properties as described in Table 6-6. Table 6-6. Frame Filter Configuration Register Address 0x20,0x21 0x22,0x23 0x24 … 0x2B 0x17 0x17 0x17 Register Bits 7:0 Name SHORT_ADDR_0/1 PAN_ADDR_0/1 IEEE_ADDR_0 … IEEE_ADDR_7 AACK_PROM_MODE AACK_UPLD_RES_FT AACK_FLTR_RES_FT Description Set macShortAddress, macPANId aExtendedAddress as described in [1] 1 4 5 0: disable promiscuous mode 1: enable promiscuous mode 0: disable reserved frame type reception 1: enable reserved frame type reception Filter reserved frame types like data frame type, see section 6.2.2 0: disable 1: enable Frame acceptance criteria depending on FCF frame version number b00: accept only frames with version number 0, i.e. according to IEEE 802.15.4-2003 frames b01: accept only frames with version number 0 or 1, i.e. frames according to IEEE 802.15.4-2006 b10: accept only frames with version number 0 or 1 or 2 b11: accept all frames, independent of the FCF frame version number 0x2E 7:6 AACK_FVN_MODE 71 8168B-MCU Wireless-02/09 6.2.2 Handling of Reserved Frame Types Reserved frame types as described in 5.2.3.3 are treated according to bits AACK_UPLD_RES_FT and AACK_FLTR_RES_FT of register 0x17 (XAH_CTRL_1) with 3 options: 1. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 0: Frames of reserved frame type with correct FCS are indicated by the interrupt IRQ_3 (TRX_END). No further frame filtering is applied on these frames. Interrupt IRQ_5 (AMI) is never generated and no acknowledgment is sent. 2. AACK_UPLD_RES_FT = 1, AACK_FLTR_RES_FT = 1: If AACK_FLTR_RES_FT = 1, any frame with a reserved frame type is treated by the RX_AACK Frame Filter as an IEEE 802.15.4 compliant data frame. This implies the generation of the interrupt IRQ_5 (AMI) upon address matches. 3. AACK_UPLD_RES_FT = 0 Any frame with a reserved frame type is blocked. 6.2.3 Register Description Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a control register for Extended Operating Mode. Table 6-7. Register 0x17 (XAH_CTRL_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 Reserved R/W 0 3 Reserved R 0 6 CSMA_LBT_MODE R/W 0 2 AACK_ACK_TIME R/W 0 5 AACK_FLTR_RES_FT 4 AACK_UPLD_RES_FT R/W 0 1 AACK_PROM_MODE R/W 0 0 Reserved R 0 R/W 0 • Bit 7 – Reserved • Bit 6 – CSMA_LBT_MODE Refer to section 6.7.3. • Bit 5 – AACK_FLTR_RES_FT This register bit shall only be set if AACK_UPLD_RES_FT = 1. If AACK_FLTR_RES_FT = 1, any frame with a reserved frame type is treated by the RX_AACK Frame Filter as an IEEE 802.15.4 compliant data frame. If AACK_FLTR_RES_FT = 0, the received reserved frame is only checked for a valid FCS. See 6.2.2 for details. • Bit 4 – AACK_UPLD_RES_FT If AACK_UPLD_RES_FT = 1, received frames which are identified as reserved frames will not be blocked. See 6.2.2 for details. • Bit 3 – Reserved 72 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 • Bit 2 – AACK_ACK_TIME Refer to section 5.2.3.3. • Bit 1 – AACK_PROM_MODE Refer to section 5.2.6. • Bit 0 – Reserved Register 0x20 (SHORT_ADDR_0): This register contains the lower 8 bit of the 16-bit short address for Frame Filter address recognition, bits [7:0]. Table 6-8. Register 0x20 (SHORT_ADDR_0) Bit Name Read/Write Reset Value 1 1 1 1 7 6 5 4 3 2 1 0 SHORT_ADDRESS_0[7:0] R/W 1 1 1 1 Register 0x21 (SHORT_ADDR_1): This register contains the higher 8 bit of the 16-bit short address for Frame Filter address recognition, bits [15:8]. Table 6-9. Register 0x21 (SHORT_ADDR_1) Bit Name Read/Write Reset Value 1 1 1 1 7 6 5 4 3 2 1 0 SHORT_ADDRESS_1[7:0] R/W 1 1 1 1 Register 0x22 (PAN_ID_0): This register contains the lower 8 bit of the MAC PAN ID for Frame Filter address recognition, bits [7:0]. Table 6-10. Register 0x22 (PAN_ID_0) Bit Name Read/Write Reset Value 1 1 1 1 7 6 5 4 3 PAN_ID_0[7:0] R/W 1 1 1 1 2 1 0 Register 0x23 (PAN_ID_1): This register contains the higher 8 bit of the MAC PAN ID for Frame Filter address recognition, bits [15:8]. Table 6-11. Register 0x23 (PAN_ID_1) Bit Name Read/Write Reset Value 1 1 1 1 7 6 5 4 3 PAN_ID_1[7:0] R/W 1 1 1 1 2 1 0 73 8168B-MCU Wireless-02/09 Register 0x24 (IEEE_ADDR_0): This register contains bits [7:0] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-12. Register 0x24 (IEEE_ADDR_0) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 IEEE_ADDR_0[7:0] R/W 0 0 0 0 Register 0x25 (IEEE_ADDR_1): This register contains bits [15:8] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-13. Register 0x25 (IEEE_ADDR_1) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 IEEE_ADDR_1[7:0] R/W 0 0 0 0 Register 0x26 (IEEE_ADDR_2): This register contains bits [23:16] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-14. Register 0x26 (IEEE_ADDR_2) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 IEEE_ADDR_2[7:0] R/W 0 0 0 0 Register 0x27 (IEEE_ADDR_3): This register contains bits [31:24] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-15. Register 0x27 (IEEE_ADDR_3) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 IEEE_ADDR_3[7:0] R/W 0 0 0 0 Register 0x28 (IEEE_ADDR_4): This register contains bits [39:32] of the 64-bit IEEE extended address for Frame Filter address recognition. 74 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 6-16. Register 0x28 (IEEE_ADDR_4) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 IEEE_ADDR_4[7:0] R/W 0 0 0 0 Register 0x29 (IEEE_ADDR_5): This register contains bits [47:40] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-17. Register 0x29 (IEEE_ADDR_5) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 IEEE_ADDR_5[7:0] R/W 0 0 0 0 Register 0x2A (IEEE_ADDR_6): This register contains bits [55:48] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-18. Register 0x2A (IEEE_ADDR_6) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 IEEE_ADDR_6[7:0] R/W 0 0 0 0 Register 0x2B (IEEE_ADDR_7): This register contains bits [63:56] of the 64-bit IEEE extended address for Frame Filter address recognition. Table 6-19. Register 0x2B (IEEE_ADDR_7) Bit Name Read/Write Reset Value 0 0 0 0 7 6 5 4 3 2 1 0 IEEE_ADDR_7[7:0] R/W 0 0 0 0 Register 0x2E (CSMA_SEED_1): The CSMA_SEED_1 register is a control register for RX_AACK and contains a part of the CSMA seed for the CSMA-CA algorithm, as well as control bits for the Frame Filter and RX_AACK transaction. Table 6-20. Register 0x2E (CSMA_SEED_1) Bit Name Read/Write Reset Value 7 AACK_FVN_MODE R/W 0 6 AACK_FVN_MODE R/W 1 5 AACK_SET_PD R/W 0 4 AACK_DIS_ACK R/W 0 75 8168B-MCU Wireless-02/09 Bit Name Read/Write Reset Value 3 AACK_I_AM_COORD 2 CSMA_SEED_1 R/W 0 1 CSMA_SEED_1 R/W 1 0 CSMA_SEED_1 R/W 0 R/W 0 • Bit 7:6 – AACK_FVN_MODE The frame control field of the MAC header (MHR) contains a frame version subfield. The setting of AACK_FVN_MODE specifies the frame filtering and acknowledgement behavior of the AT86RF212. According to the content of these register bits the radio transceiver passes frames with a specific set of frame version numbers. Thus the register bit AACK_FVN_MODE defines the maximum acceptable frame version. Received frames with a higher frame version number than configured do not pass the Frame Filter and thus are not acknowledged. Table 6-21. Frame Version Subfield dependent Frame Acceptance Register Bits AACK_FVN_MODE Value 0 1 2 3 Description Accept frames with version number 0 Accept frames with version number 0 or 1 Accept frames with version number 0 or 1 or 2 Accept frames independent of frame version number • Bit 5 – AACK_SET_PD Refer to section 5.2.6. • Bit 4 – AACK_ DIS_ACK Refer to section 5.2.6. • Bit 3 – AACK_I_AM_COORD Refer to section 5.2.6. • Bit 2:0 – CSMA_SEED_1 Refer to section 5.2.6. 6.3 Frame Check Sequence (FCS) A FCS mechanism employing a 16-bit International Telecommunication Union Telecommunication Standardization Sector (ITU-T) cyclic redundancy check (CRC) can be used to detect errors in frames. 6.3.1 Overview The FCS is intended for use at the MAC layer in order to detect corrupted frames. It is computed by applying an ITU-T CRC polynomial to all transmitted/received bytes following the length field (MHR and MSDU fields). The FCS has a length of 16 bit and is located in the last two octets of the PSDU. By default, the AT86RF212 generates and inserts the FCS octets autonomously during transmit process. This behavior can be disabled by setting register bit TX_AUTO_CRC_ON = 0 (register 0x04, TRX_CTRL_1). An automatic FCS check is always performed during frame reception. 76 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 6.3.2 CRC Calculation The CRC polynomial used in IEEE 802.15.4 networks is defined by G16 ( x) = x16 + x12 + x 5 + 1 . The FCS shall be calculated for transmission using the following algorithm: Let M ( x) = b0 x k −1 + b1 x k −2 + K + bk −2 x + bk −1 be the polynomial representing the sequence of bits for which the checksum is to be 16 computed. Multiply M(x) by x , giving the polynomial N ( x) = M ( x) ⋅ x16 . Divide N ( x) modulo 2 by the generator polynomial, G16 ( x ) , to obtain the remainder polynomial, R ( x) = r0 x15 + r1 x14 + ... + r14 x + r15 The FCS field is given by the coefficients of the remainder polynomial, R ( x) . Example: Considering a 5-octet ACK frame, the MHR field consists of 0100 0000 0000 0000 0101 0110 . The leftmost bit (b0) is transmitted first in time. The FCS would be 0010 0111 1001 1110 . The leftmost bit (r0) is transmitted first in time. 6.3.3 Automatic FCS Generation The automatic FCS generation is enabled with register bit TX_AUTO_CRC_ON = 1. This allows the AT86RF212 to compute the FCS autonomously. For a frame with a frame length field specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS octets are transmitted in place of the last two octets of the Frame Buffer. 6.3.4 Automatic FCS Check Basic and Extended Operating Modes are provided with an automatic FCS check for received frames. Register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set to one, if the FCS of a received frame is valid. In addition, bit 7 of byte RX_STATUS is set accordingly, refer to section 4.3.2. In Extended Operating Mode, the RX_AACK procedure does not accept a frame, if the corresponding FCS is not valid, and no TRX_END interrupt is issued. When operating in TX_ARET mode, the FCS of a received ACK is automatically checked. If it is not correct, the ACK is not accepted, refer to section 5.2.4 for automated retries. 6.3.5 Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi-purpose register to control various operating modes and settings of the radio transceiver, see Table 6-22. 77 8168B-MCU Wireless-02/09 Table 6-22. Register 0x04 (TRX_CTRL_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 PA_EXT_EN R/W 0 3 SPI_CMD_MODE R/W 0 6 IRQ_2_EXT_EN R/W 0 2 SPI_CMD_MODE R/W 0 5 TX_AUTO_CRC_ON 4 RX_BL_CTRL R/W 0 0 IRQ_POLARITY R/W 0 R/W 1 1 IRQ_MASK_MODE R/W 0 • Bit 7 – PA_EXT_EN Refer to section 9.4.3. • Bit 6 – IRQ_2_EXT_EN Refer to section 9.5.2. • Bit 5 – TX_AUTO_CRC_ON The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1, which is the reset value. • Bit 4 – RX_BL_CTRL Refer to section 9.6.2. • Bit 3:2 – SPI_CMD_MODE Refer to section 4.4.1. • Bit 1 – IRQ_MASK_MODE Refer to section 4.7.2. • Bit 0 – IRQ_POLARITY Refer to section 4.7.2. Register 0x06 (PHY_RSSI): The PHY_RSSI register is a multi-purpose register to indicate FCS validity, to provide random numbers, and a RSSI value. Table 6-23. Register 0x06 (PHY_RSSI) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 RX_CRC_VALID R 0 3 RSSI[3] R 0 6 RND_VALUE R 0 2 RSSI[2] R 0 5 RND_VALUE R 0 1 RSSI[1] R 0 4 RSSI[4] R 0 0 RSSI[0] R 0 78 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 • Bit 7 – RX_CRC_VALID Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated at the same time the IRQ_3 (TRX_END) is issued and remains valid until the next SHR detection. A value of “1” corresponds to a valid FCS, a value of “0” corresponds to an invalid FCS. • Bit 6:5 – RND_VALUE Refer to register description in section 9.1.8. • Bit 4:0 – RSSI Refer to register description in section 6.4.4. 6.4 Received Signal Strength Indicator (RSSI) The Received Signal Strength Indicator is characterized by: • a dynamic range of 85 dB • a minimum RSSI value of 0 • a maximum RSSI value of 28 6.4.1 Overview The RSSI is a 5-bit value indicating the received signal power in the selected channel, in steps of 3 dB. No attempt is made to distinguish IEEE 802.15.4 signals from others, only the received signal strength is evaluated. The RSSI provides the basis for an ED measurement, see 6.5. 6.4.2 Reading RSSI In Basic Operating Modes, the RSSI value is valid in any receive state, and is updated at time intervals according to Table 6-24. The current RSSI value can be accessed by reading register bits RSSI of register 0x06 (PHY_RSSI). Table 6-24. RSSI Update Interval PHY Mode BPSK-20 BPSK-40 O-QPSK Update Interval [µs] 32 24 8 It is not recommended reading the RSSI value when using the Extended Operating Modes. Instead, the automatically generated ED value should be used, see section 6.5. 6.4.3 Data Interpretation The RSSI value is a 5-bit value, indicating the receiver input power, in steps of 3 dB and with a range of 0 - 28. A RSSI value of 0 indicates a receiver input power less than RSSI_BASE_VAL [dBm]. The value RSSI_BASE_VAL itself depends on the PHY mode, refer to section 7.1. For typical conditions, it is shown in Table 6-25. Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.), RSSI_BASE_VAL has a maximum tolerance of ±5 dB. This should be considered as a constant offset over the measurement range. 79 8168B-MCU Wireless-02/09 Table 6-25. RSSI_BASE_VAL PHY Mode BPSK with 300 kchip/s BPSK with 600 kchip/s O-QPSK with 400 kchip/s O-QPSK with 1000 kchip/s, sine shaping (SIN) O-QPSK with 1000 kchip/s, raised cosine shaping (RC-0.8) RSSI_BASE_VAL [dBm] -100 -99 -98 -97 -97 Maximum Tolerance [dB] ±5 ±5 ±5 ±5 ±5 For a RSSI value in the range of 1 to 28, the receiver input power can be calculated as follows: PRF = RSSI_BASE_VAL [dBm] + 3.2 • (RSSI - 1) [dBm] Figure 6-3. Mapping between RSSI Value and Receiver Input Power -5 -15 [dBm] Received Input Power P RF -25 -35 -45 -55 -65 -75 -85 -95 -105 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 RSSI BPSK with 300 kchip/s BPSK with 600 kchip/s O-QPSK with 400 kchip/s O-QPSK with 1000 kchip/s (SIN) O-QPSK with 1000 kchip/s (RC-0.8) 6.4.4 Register Description Register 0x06 (PHY_RSSI) Table 6-26. Register 0x06 (PHY_RSSI) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 RX_CRC_VALID R 0 3 RSSI[3] R 0 6 RND_VALUE R 0 2 RSSI[2] R 0 5 RND_VALUE R 0 1 RSSI[1] R 0 4 RSSI[4] R 0 0 RSSI[0] R 0 80 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 • Bit 7 – RX_CRC_VALID Refer to register description in section 6.3.5. • Bit 6:5 – RND_VALUE Refer to register description in section 9.1.8. • Bit 4:0 – RSSI The result of the automated RSSI measurement is stored in register bits RSSI. The value is updated at time intervals according to Table 6-24 at any receive state. The value is a number between 0 and 28, indicating the received signal strength as a linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. A RSSI value of 0 indicates a receiver input power less than RSSI_BASE_VAL [dBm] (see Table 6-25), a value of 28 an input power equal or larger than (RSSI_BASE_VAL + 85) [dBm]. 6.5 Energy Detection (ED) The Energy Detection (ED) module is characterized by: • 85 unique energy levels defined • 1 dB resolution 6.5.1 Overview The receiver ED measurement (ED scan procedure) can be used as a part of a channel selection algorithm. It is an estimation of the received signal power within the bandwidth of an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on the channel. The ED value is calculated by averaging RSSI values over 8 symbol periods, with the exception of the High Data Rate Modes, refer to 7.1.4. 6.5.2 Measurement Description There are two ways to initiate an ED measurement: • Manually, by writing an arbitrary value to register 0x07 (PHY_ED_LEVEL), or • Automatically, after detection of a valid SHR of an incoming frame. For manually initiated ED measurements, the radio transceiver needs to be either in the state RX_ON or BUSY_RX. The end of the ED measurement time (8 symbol periods) is indicated by the interrupt IRQ_4 (CCA_ED_DONE) and the measurement result is stored in register 0x07 (PHY_ED_LEVEL). In order to avoid interference with an automatically initiated ED measurement, the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to section 7.2. Note that it is not recommended to manually initiate an ED measurement when using the Extended Operating Mode. An automated ED measurement is started upon SHR detection. The end of the automated measurement is not signaled by an interrupt. When using the Basic Operating Mode, a valid ED value (register 0x07, PHY_ED_LEVEL) of the currently received frame is accessible not later than 8 symbol periods after IRQ_2 (RX_START) plus a processing time of 12 µs. The ED value remains valid until a new RX_START interrupt is generated by the next incoming frame or until another ED measurement is initiated. 81 8168B-MCU Wireless-02/09 When using the Extended Operating Mode, it is useful to mask IRQ_2 (RX_START), thus the interrupt cannot be used as timing reference. A successful frame reception is signalized by interrupt IRQ_3 (TRX_END). In this case, the ED value needs to be read within the time span of a next SHR detection plus the ED measurement time in order to avoid overwrite of the current ED value. The values of the register 0x07 (PHY_ED_LEVEL) are: Table 6-27. Register Bit PHY_ED_LEVEL Interpretation PHY_ED_LEVEL 0xFF 0x00 … 0x54 Description Reset value ED measurement result of the last ED measurement 6.5.3 Data Interpretation The PHY_ED_LEVEL (ED) is an 8-bit register. The ED value of the AT86RF212 has a valid range from 0x00 to 0x54 (0 to 84) with a resolution of 1 dB. Values 0x55 to 0xFE do not occur and a value of 0xFF indicates the reset value. A value of PHY_ED_LEVEL = 0 indicates that the measured receiver input power is less than or equal to RSSI_BASE_VAL [dBm] (refer to Table 6-25). For an ED value in the range of 0 to 84, the receiver input power can be calculated as follows: PRF = RSSI_BASE_VAL [dBm] + 1.05 • ED [dBm] Figure 6-4. Mapping between Receiver Input Power and ED Value -5 -15 [dBm] Received Input Power P RF -25 -35 -45 -55 -65 -75 -85 -95 -105 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 PHY_ED_LEVEL (register 0x07) BPSK with 300 kchip/s BPSK with 600 kchip/s O-QPSK with 400 kchip/s O-QPSK with 1000 kchip/s (SIN) O-QPSK with 1000 kchip/s (RC-0.8) 6.5.4 Interrupt Handling Interrupt IRQ_4 (CCA_ED_DONE) is issued at the end of a manually initiated ED measurement. 82 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Note that an ED measurement should only be initiated in RX states but not in RX_AACK states. Otherwise, the radio transceiver generates an IRQ_4 (CCA_ED_DONE) without actually performing an ED measurement. 6.5.5 Register Description Register 0x07 (PHY_ED_LEVEL) The PHY_ED_LEVEL register contains the result of an ED measurement. Table 6-28. Register 0x07 (PHY_ED_LEVEL) Bit Name Read/Write Reset Value 1 1 1 1 7 6 5 4 3 ED_LEVEL[7:0] R (1) 2 1 0 1 1 1 1 Note: 1. A write access is required for initiation of a manual ED measurement. Bit 7:0 – ED_LEVEL The minimum ED value (ED_LEVEL = 0) indicates a receiver input power less than or equal to RSSI_BASE_VAL [dBm]. The range is 85 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to the register. A value 0xFF indicates that a measurement has never been started yet (reset value). The measurement duration is 8 symbol periods, see section 7.1.3. For High Data Rate Modes, the automated measurement duration is reduced to 2 symbol periods, refer to 7.1.4. For manually initiated ED measurements in these modes, the measurement time is still 8 symbol periods as long as the receiver is in RX_ON state. A value out of {0x00, …, 0x54} indicates the result of the last ED measurement. 6.6 Clear Channel Assessment (CCA) The main features of the Clear Channel Assessment (CCA) module are: • All four CCA modes are provided as defined in IEEE 802.15.4-2006 • Adjustable threshold for energy detection algorithm 6.6.1 Overview A CCA measurement is used to detect a clear channel. Four CCA modes are specified by IEEE 802.15.4-2006: Table 6-29. CCA Mode Overview CCA Mode 1 Description Energy above threshold. CCA shall report a busy medium upon detecting any energy above the ED threshold. Carrier sense only. CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an IEEE 802.15.4 compliant signal. The signal strength may be above or below the ED threshold. 2 83 8168B-MCU Wireless-02/09 CCA Mode 0, 3 Description Carrier sense with energy above threshold. CCA shall report a busy medium using a logical combination of - Detection of a signal with the modulation and spreading characteristics of this standard and/or - Energy above the ED threshold. Where the logical operator may be configured as either OR (mode 0) or AND (mode 3). 6.6.2 Configuration and Request The CCA modes are configurable via register 0x08 (PHY_CC_CCA). When being in Basic Operating Mode, a CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the AT86RF212 is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible through register 0x01 (TRX_STATUS). The end of a manually initiated CCA (8 symbol periods plus 12 µs processing delay), is indicated by the interrupt IRQ_4 (CCA_ED_DONE). The sub-register CCA_ED_THRES of register 0x09 (CCA_THRES) defines the receive power threshold of the “Energy above threshold” algorithm. The threshold is calculated by V_THRES = (RSSI_BASE_VAL + 2 • CCA_ED_THRES) [dBm]. Any received power above this level is interpreted as a busy channel. Note that it is not recommended to manually initiate a CCA request when using the Extended Operating Mode. 6.6.3 Data Interpretation The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible through register 0x01 (TRX_STATUS). Note that register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA_REQUEST. The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radio transceiver detected no signal (idle channel) during the CCA evaluation period, the CCA_STATUS bit is set to 1, otherwise, it is set to 0. When using the “Energy above threshold” algorithm, a received power above V_THRES level is interpreted as a busy channel. When using the “carrier sense” algorithm (i.e. CCA_MODE = 0, 2, and 3), the AT86RF212 reports a busy channel upon detection of a (PHY mode specific) IEEE 802.15.4 signal above the RSSI_BASE_VAL (see Table 6-25). The AT86RF212 is also capable of detecting signals below this value, but the detection probability decreases with decreasing signal power. It is almost zero at the radio transceivers sensitivity level (see chapter 0). 6.6.4 Interrupt Handling Interrupt IRQ_4 (CCA_ED_DONE) is issued at the end of a manually initiated CCA measurement. 84 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Note • A CCA request should only be initiated in Basic Operating Mode RX states. Otherwise, the radio transceiver generates IRQ_4 (CCA_ED_DONE) and sets the register bit CCA_DONE = 1, without actually performing a CCA measurement. 6.6.5 Measurement Time The response time of a manually initiated CCA measurement depends on the receiver state. In RX_ON state, the CCA measurement is done over eight symbol periods and the result is accessible upon the event IRQ_4 (CCA_ED_DONE) or upon CCA_DONE=1 (register 0x01, TRX_STATUS). In BUSY_RX state, the CCA measurement duration depends on the CCA mode and the CCA request relative to the detection of the SHR. The end of the CCA measurement is indicated by IRQ_4 (CCA_ED_DONE). The variation of a CCA measurement period in BUSY_RX state is described in Table 6-30. Table 6-30. CCA Measurement Period and Access in BUSY_RX State CCA Mode 1 Request within ED Measurement(1) Energy above threshold. CCA result is available after finishing automated ED measurement period. 2 3 Carrier sense only. CCA result is immediately available after request. Carrier sense with Energy above threshold (AND). CCA result is available after finishing automated ED measurement period. 0 CCA result is available after finishing automated ED measurement period. Note: CCA result is immediately available after request. CCA result is immediately available after request. CCA result is immediately available after request. Request after ED Measurement Carrier sense with Energy above threshold (OR). 1. After detecting the SHR, an automated ED measurement is started with a length of 8 symbol periods (2 symbol periods for high rate PHY modes), refer to 7.1.3. This automated ED measurement must be finished to provide a result for the CCA measurement. Only one automated ED measurement per frame is performed. It is recommended to perform CCA measurements in RX_ON state only. To avoid switching accidentally to BUSY_RX state, the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to section 7.2. The receiver remains in RX_ON state to perform a CCA measurement until the register bit RX_PDT_DIS is set back to continue the frame reception. In this case, the CCA measurement duration is 8 symbol periods. 6.6.6 Register Description Register 0x01 (TRX_STATUS): Two register bits of register 0x01 (TRX_STATUS) indicate the status of the CCA measurement. 85 8168B-MCU Wireless-02/09 Table 6-31. Register 0x01 (TRX_STATUS) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 CCA_DONE R 0 3 TRX_STATUS R 0 6 CCA_STATUS R 0 2 TRX_STATUS R 0 5 Reserved R 0 1 TRX_STATUS R 0 4 TRX_STATUS R 0 0 TRX_STATUS R 0 • Bit 7 – CCA_DONE This register indicates completion a CCA measurement, which is additionally indicated by the interrupt IRQ_4 (CCA_ED_DONE). Note that register bit CCA_DONE is cleared in response to a CCA_REQUEST. Table 6-32. CCA Algorithm Status Register Bit CCA_DONE Value 0 1 Description CCA calculation not finished CCA calculation finished • Bit 6 – CCA_STATUS After a CCA request is completed, the result of the CCA measurement is available in register bit CCA_STATUS. Note that register bit CCA_STATUS is cleared in response to a CCA_REQUEST. Table 6-33. CCA Status Result Register Bit CCA_STATUS Value 0 1 Description Channel indicated as busy Channel indicated as idle • Bit 5 – Reserved • Bit 4:0 – TRX_STATUS Refer to section 5.1.5 and 5.2.6. Register 0x08 (PHY_CC_CCA): This register is provided to initiate and control a CCA measurement. Table 6-34. Register 0x08 (PHY_CC_CCA) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 CCA_REQUEST W 0 3 CHANNEL R/W 0 6 CCA_MODE[1] R/W 0 2 CHANNEL R/W 1 5 CCA_MODE[0] R/W 1 1 CHANNEL R/W 0 4 CHANNEL R/W 0 0 CHANNEL R/W 1 86 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 • Bit 7 – CCA_REQUEST A manual CCA measurement is initiated by setting CCA_REQUEST = 1. The register bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST = 1. • Bit 6:5 – CCA_MODE The CCA mode can be selected using register bits CCA_MODE. Table 6-35. CCA Mode Register Bits CCA_MODE Value 0 1 2 3 Description Carrier sense OR Energy above threshold Energy above threshold Carrier sense only Carrier sense AND Energy above threshold Note that IEEE 802.15.4–2006 CCA mode 3 defines the logical combination of CCA mode 1 and 2 with the logical operators AND or OR. This can be selected with: o CCA_MODE = 0 o CCA_MODE = 3 • Bit 4:0 – CHANNEL Refer to section 7.8. Register 0x09 (CCA_THRES): for logical operation OR, and for logical operation AND. This register sets the ED threshold level for CCA. Table 6-36. Register 0x09 (CCA_THRES) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 Reserved R/W 0 3 CCA_ED_THRES R/W 0 6 Reserved R/W 1 2 CCA_ED_THRES R/W 1 5 Reserved R/W 1 1 CCA_ED_THRES R/W 1 4 Reserved R/W 1 0 CCA_ED_THRES R/W 1 • Bit 7:5 – Reserved • Bit 4:0 – CCA_ED_THRES The CCA mode 1 request indicates a busy channel if the measured received power is above (RSSI_BASE_VAL + 2 • CCA_ED_THRES) [dBm]. CCA modes 0 and 3 are logically related to this result. 87 8168B-MCU Wireless-02/09 6.7 Listen Before Talk (LBT) 6.7.1 Overview Equipment using the AT86RF212 shall conform to the established regulations. With respect to the regulations in Europe, CSMA-CA based transmission according to IEEE 802.15.4 is not appropriate. In principle, transmission is subject to low duty cycles (0.1 to 1 %). However, according to [4], equipment employing listen before talk (LBT) and adaptive frequency agility (AFA) does not have to comply with duty cycle conditions. Hence, LBT can be attractive in order to reduce network latency. Minimum Listening Time A device with LBT needs to comply with a minimum listening time, refer to chapter 9.1.1.2 of [4]. Prior transmission, the device must listen for a receive signal at or above the LBT threshold level to determine whether the intended channel is available for use, unless transmission is pursuing acknowledgement. A device using LBT needs to listen for a fixed period of 5 ms. If after this period the channel is free, transmission may immediately commence (i.e. no CSMA is required). Otherwise, a new listening period of a randomly selected time span between 5 and 10 ms is required. The time resolution shall be approximately 0.5 ms. The last step needs to be repeated until a free channel is available. LBT Threshold According to [4], the maximum LBT threshold for an IEEE 802.15.4 signal is presumably -82 dBm, assuming a channel spacing of 1 MHz. 6.7.2 LBT Mode The AT86RF212 supports the previously described LBT specific listening mode when operating in the Extended Operating Mode. In particular, during TX_ARET (see section 5.2.4), the CSMA-CA algorithm can be replaced by the LBT listening mode, when setting register bit CSMA_LBT_MODE (register 0x17, XAH_CTRL_1). In this case, however, the register bits MAX_CSMA_RETRIES (register 0x2C, XAH_CTRL_0) as well as MIN_BE and MAX_BE (register 0x2F, CSMA_BE) are ignored, implying that the listening mode will sustain, unless a clear channel has been found or the TX_ARET transaction will be canceled. The latter can be achieved by setting TRX_CMD to either FORCE_PLL_ON or FORCE_TRX_OFF (register 0x02, TRX_STATE). All other aspects of TX_ARET remain unchanged; refer to section 5.2.4. The LBT threshold can be configured in the same way as for CCA, i.e. via register bits CCA_MODE (register 0x08, PHY_CC_CCA) and register bits CCA_ED_THRES (register 0x09, CCA_THRES), refer to section 6.6. 6.7.3 Register Description Register 0x08 (PHY_CC_CCA): This register is relevant for the measurement mode when using LBT, i.e. selecting Energy above threshold or Carrier sense (CS) or combination of both. 88 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 6-37. Register 0x08 (PHY_CC_CCA) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 CCA_REQUEST W 0 3 CHANNEL R/W 0 6 CCA_MODE[1] R/W 0 2 CHANNEL R/W 1 5 CCA_MODE[0] R/W 1 1 CHANNEL R/W 0 4 CHANNEL R/W 0 0 CHANNEL R/W 1 • Bit 7 – CCA_REQUEST Not applicable for LBT, see section 6.6.6. • Bit 6:5 – CCA_MODE The CCA mode can be used in order to select the appropriate LBT measurement mode by using register bits CCA_MODE, refer to section 6.6. • Bit 4:0 – CHANNEL Refer to section 7.8. Register 0x09 (CCA_THRES): This register is relevant for the ED threshold when using LBT. Table 6-38. Register 0x09 (CCA_THRES) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 Reserved R/W 0 3 CCA_ED_THRES R/W 0 6 Reserved R/W 1 2 CCA_ED_THRES R/W 1 5 Reserved R/W 1 1 CCA_ED_THRES R/W 1 4 Reserved R/W 1 0 CCA_ED_THRES R/W 1 • Bit 7:5 – Reserved • Bit 4:0 – CCA_ED_THRES For CCA_MODE = 1, a busy channel is indicated if the measured received power is above (RSSI_BASE_VAL + 2 • CCA_ED_THRES) [dBm]. CCA_MODE = 0 and 3 are logically related to this result. Register 0x17 (XAH_CTRL_1): This register is relevant for enabling or disabling the LBT mode. 89 8168B-MCU Wireless-02/09 Table 6-39. Register 0x17 (XAH_CTRL_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 Reserved R/W 0 3 Reserved R 0 6 CSMA_LBT_MODE R/W 0 2 AACK_ACK_TIME R/W 0 5 AACK_FLTR_RES_FT 4 AACK_UPLD_RES_FT R/W 0 1 AACK_PROM_MODE R/W 0 0 Reserved R 0 R/W 0 • Bit 7 – Reserved • Bit 6 – CSMA_LBT_MODE If set to 0 (default), CSMA-CA algorithm is used during TX_ARET for clear channel assessment. Otherwise, the LBT specific listening mode is applied. • Bit 5 – AACK_FLTR_RES_FT Refer to section 5.2.6. • Bit 4 – AACK_UPLD_RES_FT Refer to section 5.2.6. • Bit 3 – Reserved • Bit 2 – AACK_ACK_TIME Refer to section 5.2.6. • Bit 1 – AACK_PROM_MODE Refer to section 5.2.6. • Bit 0 – Reserved 6.8 Link Quality Indication (LQI) 6.8.1 Requirements The IEEE 802.15.4 standard defines the LQI as a characterization of the strength and/or quality of a received frame. The use of the LQI result by the network or application layer is not specified in this standard. The LQI value shall be an integer ranging from 0 to 255, with at least 8 unique values. The minimum and maximum LQI values (0 and 255) should be associated with the lowest and highest quality compliant signals, respectively, and LQI values in between should be uniformly distributed between these two limits. 6.8.2 Implementation During symbol detection within frame reception, the AT86RF212 uses correlation results of multiple symbols in order to compute an estimate of the LQI value. This is motivated by the fact, that the mean value of the correlation result is inversely related to the probability of a detection error. LQI computation is automatically performed for each received frame, once the SHR has been detected. LQI values are integers ranging from 0 to 255 as required by the IEEE 802.15.4 standard. 90 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 6.8.3 Obtaining the LQI Value The LQI value is available, once the corresponding frame has been completely received. This is indicated by the interrupt IRQ_3 (TRX_END). The value can be obtained by means of a frame buffer read access, see section 4.3.2. 6.8.4 Remarks The reason for a low LQI value can be twofold: a low signal strength and/or high signal distortions, e.g. by interference and/or multipath propagation. High LQI values, however, indicate a sufficient signal strength and low signal distortions. Note that the LQI value is almost always 255 for scenarios with very low signal distortions and a signal strength much greater than the sensitivity level. In this case, the packet error rate tends towards zero and increase of the signal strength, i.e. by increasing the transmission power, cannot decrease the error rate any further. Received signal strength indication (RSSI) or energy detection (ED) can be used to evaluate the signal strength and the link margin. ZigBee networks often require identification of the “best” routing between two nodes. LQI and RSSI/ED can be applied, depending on the optimization criteria. If a low frame error rate (corresponding to a high throughput) is the optimization criteria, then the LQI value should be taken into consideration. If, however, the target is a low transmission power, then the RSSI/ED value is also helpful. Various combinations of LQI and RSSI/ED are possible for routing decisions. As a rule of thumb, information on RSSI/ED is useful in order to differentiate between links with high LQI values. However, transmission links with low LQI values should be discarded for routing decisions even if the RSSI/ED values are high, since it is merely an information about the received signal strength whereas the source can be an interferer. 91 8168B-MCU Wireless-02/09 7 Module Description 7.1 Physical Layer Modes 7.1.1 Spreading, Modulation, and Pulse Shaping The AT86RF212 supports various physical layer (PHY) modes independent of the RF channel selection. Symbol mapping along with chip spreading, modulation, and pulse shaping is part of the digital base band processor, see Figure 7-1. Figure 7-1. Base Band Transmitter Architecture PPDU Symbol Mapping & Chip Spreading Modulation BPSK/O-QPSK Pulse Shaping DAC The combination of spreading, modulation, and pulse shaping are restricted to several combinations as shown in Table 7-1. The AT86RF212 is fully compliant to the IEEE 802.15.4 low data rate modes of 20 kbit/s or 40 kbit/s, employing binary phase-shift keying (BPSK) and spreading with a fixed chip rate of 300 kchip/s or 600 kchip/s, respectively. The symbol rate is 20 ksymbol/s or 40 ksymbol/s, respectively. In both cases, pulse shaping is approximating a raised cosine filter with roll-off factor 1.0 (RC-1.0). For optional data rates according to IEEE 802.15.4-2006, offset quadrature phase-shift keying (O-QPSK) is supported by the AT86RF212 with a fixed chip rate of either 400 kchip/s or 1000 kchip/s. At a chip rate of 400 kchip/s, pulse shaping is always a combination of both, half-sine shaping (SIN) and raised cosine filtering with roll-off factor 0.2 (RC-0.2), according to IEEE 802.15.4-2006 for the 868.3 MHz band. At a chip rate of 1000 kchip/s, pulse shaping is either half-sine filtering (SIN) as specified in IEEE 802.15.4-2006 [1], or, alternatively, raised cosine filtering with roll-off factor 0.8 (RC-0.8) as specified in IEEE P802.15.4c [3]. For O-QPSK, the AT86RF212 supports spreading according to IEEE 802.15.4-2006 with data rates of either 100 kbit/s or 250 kbit/s depending on the chip rate, leading to a symbol rate of either 25 ksymbol/s or 62.5 ksymbol/s, respectively. Additionally, the AT86RF212 supports two more spreading codes for O-QPSK with shortened code lengths. This leads to higher but non IEEE 802.15.4-2006 compliant data rates during the PSDU part of the frame with 200, 400, 500, and 1000 kbit/s. The proprietary High Data Rate Modes are outlined in more detail in section 7.1.4. Table 7-1. Modulation and Pulse Shaping Modulation Chip Rate [kchip/s] 300 600 O-QPSK 400 1000 Supported Data Rate for PPDU Header [kbit/s] 20 40 100 250 Supported Data Rates for PSDU [kbit/s] 20 40 100, 200, 400 250, 500, 1000 Pulse Shaping BPSK RC-1.0 RC-1.0 SIN and RC-0.2 SIN or RC-0.8 92 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 7.1.2 Configuration The PHY mode can be selected by setting appropriate register bits of register 0x0C (TRX_CTRL_2), refer to section 7.1.5. During configuration, the transceiver needs to be in state TRX_OFF. 7.1.3 Symbol Period Within IEEE 802.15.4 and, accordingly, within this document, time references are often specified in units of symbol periods, leading to a PHY mode independent description. Table 7-2 shows the duration of the symbol period. Note that for the proprietary High Data Rate Modes, the symbol period is (by definition) the same as the symbol period of the corresponding base mode. Table 7-2. Duration of the Symbol Period Modulation BPSK O-QPSK PSDU Data Rate [kbit/s] 20 40 100, 200, 400 250, 500, 1000 Duration of Symbol Period [µs] 50 25 40 16 7.1.4 Proprietary High Data Rate Modes The main features are: • High data rates up to 1000 kbit/s • Support of Basic and Extended Operating Mode • Reduced ACK timing (optional) 7.1.4.1 Overview The AT86RF212 supports alternative data rates of {200, 400, 500, 1000} kbit/s for applications not necessarily targeting IEEE 802.15.4 compliant networks. The High Data Rate Modes utilize the same RF channel bandwidth as the IEEE 802.15.4-2006 sub-1 GHz O-QPSK modes. Higher data rates are achieved by modified O-QPSK spreading codes having reduced code lengths. The lengths are reduced by the factor 2 or by the factor 4. For O-QPSK with 400 kchip/s, this leads to a data rate of 200 kbit/s (2-fold) and 400 kbit/s (4-fold), respectively. For O-QPSK with 1000 kchip/s, the resulting data rate is 500 kbit/s (2-fold) and 1000 kbit/s (4-fold), respectively. Due to the decreased spreading factor, the sensitivity of the receiver is reduced. Section 10.7, parameter 10.7.1, shows typical values of the sensitivity for different data rates. Note that the sensitivity values of the High Data Rate Modes are provided for a maximum PSDU length of 127 octets. 7.1.4.2 High Data Rate Frame Structure In order to allow robust frame synchronization, high data rate modulation is restricted to the PSDU part only. The PPDU header (the preamble, the SFD, and the PHR field) are transmitted with the IEEE 802.15.4 O-QPSK rate of either 100 kbit/s or 250 kbit/s (basic rates), see Figure 7-2. 93 8168B-MCU Wireless-02/09 Figure 7-2. High Date Rate Frame Structure Basic Rate Transmission: 100 kbit/s 250 kbit/s Preamble SFD PHR High Rate Transmission: {200, 400} kbit/s {500, 1000} kbit/s PSDU Due to the overhead caused by the PPDU header and the FCS, the effective data rate is less than the selected data rate, depending on the length of the PSDU. A graphical representation of the effective data rate is shown in Figure 7-3. Figure 7-3. Effective Data Rate of the O-QPSK Modes Netto bit rate B 900 1000 kbit/s 800 700 600 B [kbit/s] 500 250 kbit/s 400 300 200 100 0 200 kbit/s 100 kbit/s 500 kbit/s 400 kbit/s 0 20 40 60 80 PSDU length in octets 100 120 Consequently, high data rate transmission is useful for large PSDU lengths due to the higher effective data rate, or in order to reduce the power consumption of the system. 7.1.4.3 High Date Rate Mode Options Reduced Acknowledgment Time If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set, the acknowledgment time is reduced to the duration of 2 symbol periods for 200 and 400 kbit/s, and to 3 symbol periods for 500 and 1000 kbit/s, refer to Table 5-24. Otherwise, it defaults to 12 symbol periods according to IEEE 802.15.4. Receiver Sensitivity Control The different data rates between PPDU header (SHR and PHR) and PHY payload (PSDU) cause a different sensitivity between header and payload. This can be adjusted by defining sensitivity threshold levels of the receiver. With a sensitivity threshold level set, the AT86RF212 does not synchronize to frames with an RSSI level below that threshold. Refer to section 7.2.3 for a configuration of the sensitivity threshold with register 0x15 (RX_SYN). 94 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Scrambler For data rates 1000 kbit/s and 400 kbit/s, additional chip scrambling is applied per default, in order to mitigate data dependent spectral properties. Scrambling can be disabled if bit OQPSK_SCRAM_EN (register 0x0C, TRX_CTRL_2) is set to 0. Energy Detection The ED measurement time span is 8 symbol periods according to IEEE 802.15.4, see section 7.1.3. For frames operated at a higher data rate, the ED measurement period is reduced to 2 symbol periods taking reduced frame durations into account. This means, the ED measurement time is 80 µs for modes 200 kbit/s and 400 kbit/s, and 32 µs for modes 500 kbit/s and 1000 kbit/s. Carrier Sense For clear channel assessment, IEEE 802.15.4-2006 specifies several modes which may either apply Energy above threshold or Carrier sense (CS) or a combination of both. Since signals of the High Data Rate Modes are not compliant to IEEE 802.15.4-2006, CS is not supported, when the AT86RF212 is operating in these modes. However, “Energy above threshold” is supported. Link Quality Indicator (LQI) For the High Data Rate Modes, the link quality value does not contain useful information and should be discarded. 7.1.5 Register Description Register 0x0C (TRX_CTRL_2): The TRX_CTRL_2 register controls the PHY mode settings. Note that during configuration, the transceiver needs to be in state TRX_OFF. Table 7-3. Register 0x0C (TRX_CTRL_2) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 RX_SAFE_MODE R/W 0 3 BPSK_OQPSK R/W 0 6 TRX_OFF_AVDD_EN 5 OQPSK_SCRAM_EN 4 OQPSK_SUB1_RC_EN R/W 0 2 SUB_MODE R/W 1 R/W 1 1 OQPSK_DATA_RATE R/W 0 0 OQPSK_DATA_RATE R/W 0 R/W 0 • Bit 7 – RX_SAFE_MODE Refer to section 9.7.2. • Bit 6 – TRX_OFF_AVDD_EN Refer to section 5.1.4.3. 95 8168B-MCU Wireless-02/09 • Bit 5 – OQPSK_SCRAM_EN If set to 1 (reset value), the scrambler is enabled for OQPSK_DATA_RATE = 2 and BPSK_OQPSK = 1 (O-QPSK is active). Otherwise, the scrambler is disabled. Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly required to align different transceivers with OQPSK_SCRAM_EN in order to assure interoperability. • Bit 4 – OQPSK_SUB1_RC_EN The bit is only relevant for SUB_MODE = 1 and BPSK_OQPSK = 1. If set to 0 (reset value), pulse shaping is half-sine filtering for O-QPSK. If set to 1, pulse shaping is RC-0.8 filtering for O-QPSK transmission with 1000 kchip/s. Compared with half-sine filtering, side-lobes are reduced at the expense of an increased peak to average ratio (~ 1 dB). This mode is particularly suitable for the Chinese 780 MHz band. Note that during reception, this bit is not evaluated within the AT86RF212, so it is not explicitly required to align different transceivers with OQPSK_SUB1_RC_EN in order to assure interoperability. It is very likely, that this also holds for any IEEE 802.15.4-2006 compliant O-QPSK transceiver in the 915 MHz band, since the IEEE 802.15.4-2006 requirements are fulfilled for both types of shaping. • Bit 3 – BPSK_OQPSK If set to 0 (reset value), BPSK transmission and reception is applied. If set to 1, O-QPSK transmission and reception is applied. Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly required to align different transceivers with BPSK_OQPSK in order to assure interoperability. • Bit 2 – SUB_MODE If set to 1 (reset value), the chip rate is 1000 kchip/s for BPSK_OQPSK = 1 and 600 kchip/s for BPSK_OQPSK = 0. It permits data rates out of {250, 500, 1000} kbit/s, or 40 kbit/s, respectively. This mode is particularly suitable for the 915 MHz band. For OQPSK transmission, pulse shaping is either half-sine shaping or RC-0.8 shaping, depending on OQPSK_SUB1_RC_EN. If set to 0, the chip rate is 400 kchip/s for BPSK_OQPSK = 1 and 300 kchip/s for BPSK_OQPSK = 0. It permits data rates out of {100, 200, 400} kbit/s, or 20 kbit/s, respectively. This mode is particularly suitable for the 868.3 MHz band. For O-QPSK transmission, pulse shaping is always the combination of half-sine shaping and RC-0.2 shaping. Note that during reception, this bit is evaluated within the AT86RF212, so it is explicitly required to align different transceivers with SUB_MODE in order to assure interoperability. • Bit 1:0 – OQPSK_DATA_RATE These register bits control the O-QPSK data rate during the PSDU part of the frame, as depicted by Table 7-4. The reset value is OQPSK_DATA_RATE = 0. Note that during reception, these bits are evaluated within the AT86RF212, so it is explicitly required to align different transceivers with OQPSK_DATA_RATE in order to assure interoperability. 96 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 7-4. O-QPSK Data Rate during PSDU Register Bits OQPSK_DATA_RATE Value 0 1 2, 3 O-QPSK Data Rate [kbit/s] SUB_MODE = 0 100 200 400 SUB_MODE = 1 250 500 1000 In Table 7-5, all PHY modes supported by the AT86RF212 are summarized with the relevant setting for each bit of register TRX_CTRL_2. The character ‘-‘ means, the bit entry is not relevant for the particular PHY mode. Table 7-5. Register 0x0C (TRX_CTRL_2) Bit Alignment PHY Mode Register 0x0C, Bit 7 BPSK-20 BPSK-40 OQPSK-SIN-RC-100 OQPSK-SIN-RC-200 OQPSK-SIN-RC-400-SCR-ON OQPSK-SIN-RC-400-SCR-OFF OQPSK-SIN-250 OQPSK-SIN-500 OQPSK-SIN-1000-SCR-ON OQPSK-SIN-1000-SCR-OFF OQPSK-RC-250 OQPSK-RC-500 OQPSK-RC-1000-SCR-ON OQPSK-RC-1000-SCR-OFF - Compliance 1 0 0 1 1 0 0 1 1 0 0 1 1 6 - 5 1 0 1 0 1 0 4 0 0 0 0 1 1 1 1 3 0 0 1 1 1 1 1 1 1 1 1 1 1 1 2 0 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 IEEE 802.15.4: channel page 0, channel 0 IEEE 802.15.4: channel page 0, channel 1 to 10 IEEE 802.15.4-2006: channel page 2, channel 0 Proprietary Proprietary, scrambler on Proprietary, scrambler off IEEE 802.15.4-2006: channel page 2, channel 1 to 10 Proprietary Proprietary, scrambler on Proprietary, scrambler off IEEE P802.15.4c (China): channel page 5, channel 0 to 3 Proprietary Proprietary, scrambler on Proprietary, scrambler off 7.2 Receiver (RX) 7.2.1 Overview The AT86RF212 transceiver is split into an analog radio front-end and a digital domain, see Figure 1-1. Referring to the receiver part of the analog section, the differential RF signal is amplified by a low noise amplifier (LNA) and split into quadrature signals by a poly-phase filter (PPF). Two mixer circuits convert the quadrature signal down to an intermediate frequency. Channel selectivity is achieved by an integrated band-pass filter (BPF). The subsequent analog-to-digital converter (ADC) samples the receive signal and additionally generates a digital RSSI signal, see section 6.4. The ADC output is then further processed by the digital baseband receiver (RX BBP) which is part of the digital domain. 97 8168B-MCU Wireless-02/09 The BBP performs further filtering and signal processing. In RX_ON state the receiver searches for the synchronization header. Once the synchronization is established and the SFD is found the received signal is demodulated and provided to the Frame Buffer. The receiver performs a state change indicated by register bits TRX_STATUS (register 0x01, TRX_STATUS) to BUSY_RX. Once the whole frame is received, the receiver switches back to RX_ON to listen on the channel. A similar scheme applies to the Extended Operating Mode. The receiver is designed to handle frequency and symbol rate errors up to ±60 ppm, refer to section 10.5, parameter 10.5.7. Several status information are generated during the receive process: LQI, ED, and RX_STATUS. They are automatically appended during Frame Read Access, refer to section 4.3.2. Some information is also available through register access, e.g. ED value (register 0x07, PHY_ED_LEVEL) and FCS correctness (register 0x06, PHY_RSSI). The Extended Operating Mode of the AT86RF212 supports frame filtering and pending data indication. The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in section 8.1. 7.2.2 Configuration In Basic Operating Mode, the receiver is enabled by writing command RX_ON to register bits TRX_CMD (register 0x02, TRX_STATE) in states TRX_OFF or PLL_ON. In Extended Operating Mode, the receiver is enabled for RX_AACK operation from state PLL_ON by writing the command RX_AACK_ON. There is no additional configuration required to receive IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the frame reception in the Extended Operating Mode requires further register configurations. For details refer to section 5.2.2. For specific applications the receiver can be configured to handle critical environments, to simplify the interaction with the microcontroller or to operate different data rates. The AT86RF212 receiver has an outstanding sensitivity performance. At certain conditions (interference floor, High Data Rate Modes, refer to section 7.1.4), it may be useful to manually decrease this sensitivity. This is achieved by adjusting the synchronization header detector threshold using register bits RX_PDT_LEVEL (register 0x15, RX_SYN). Received signals with a RSSI value below the threshold do not activate the demodulation process. Furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. A Dynamic Frame Buffer Protection is enabled with register bit RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) set, see section 9.7. The receiver remains in RX_ON or RX_AACK_ON state until the whole frame is uploaded by the microcontroller, indicated by /SEL = H during the SPI Frame Receive Mode. The Frame Buffer content is only protected if the FCS is valid. A Static Frame Buffer Protection is enabled with register bit RX_PDT_DIS (register 0x15, RX_SYN) set. The receiver remains in RX_ON or RX_AACK_ON state and no further SHR is detected until the register bit RX_PDT_DIS is set back. 98 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 7.2.3 Register Description Table 7-6. Register 0x19 (RF_CTRL_1) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 RF_MC[3] R/W 0 3 Reserved R/W 0 6 RF_MC[2] R/W 0 2 Reserved R/W 0 5 RF_MC[1] R/W 0 1 Reserved R/W 0 4 RF_MC[0] R/W 0 0 Reserved R/W 0 • Bit 7:4 – RF_MC These register bits provide the matching control of the differential RF pins (RFN, RFP) by switching capacitances to ground, see Figure 2-2. Each step increases the capacitance by 36 fF at each pin. The capacitance setting at the RF pins is valid for both RX and TX operation. Table 7-7. RF Pin Matching Control Register Bits RF_MC Value 0 1 2 3 … 15 540 Capacitance at RF Pins [fF] 0 36 72 108 • Bit 3:0 – Reserved Register 0x15 (RX_SYN): This register controls the sensitivity threshold of the receiver. Table 7-8. Register 0x15 (RX_SYN) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 RX_PDT_DIS R/W 0 3 RX_PDT_LEVEL[3] R/W 0 6 Reserved R 0 2 RX_PDT_LEVEL[2] R/W 0 5 Reserved R 0 1 RX_PDT_LEVEL[1] R/W 0 4 Reserved R 0 0 RX_PDT_LEVEL[0] R/W 0 • Bit 7 – RX_PDT_DIS RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive mode. An ongoing frame reception is not affected. 99 8168B-MCU Wireless-02/09 • Bit 6:4 – Reserved • Bit 3:0 – RX_ PDT_LEVEL With these register bits, the receiver can be desensitized such that frames with an RSSI level below the threshold level (if RX_PDT_LEVEL > 0) are not received. The threshold level can be calculated according to the following formula: RX_THRES = RSSI_BASE_VAL + 3 ⋅ RX_PDT_LEVEL, for RX_PDT_LEVEL > 0 The RSSI_BASE_VALUE is described in section 6.4.3. If register bits RX_PDT_LEVEL = 0 (reset value), this feature is disabled which corresponds to the highest sensitivity. If register bits RX_PDT_LEVEL > 0, the current consumption of the receiver in states RX_ON and RX_AACK_ON is reduced by 500 µA. 7.3 Transmitter (TX) 7.3.1 Overview The AT86RF212 transmitter utilizes a direct up-conversion topology. The digital transmitter (TX BBP) generates the in-phase (I) and quadrature (Q) component of the modulation signal. A digital-to-analog converter (DAC) forms the analog modulation signal. A quadrature mixer pair converts the analog modulation signal to the RF domain. The power amplifier (PA) provides signal power delivered to the differential antenna pins (RFP, RFN). Both, the LNA the PA are internally connected to the bidirectional differential antenna pins so that no external antenna switch is needed. Using the default settings, the PA incorporates an equalizer to improve its linearity. The enhanced linearity keeps the spectral side lobes of the transmit spectrum low in order to meet the requirements of the European 868.3 MHz band. If the PA boost mode is turned on, the equalizer is disabled. This allows to deliver a higher transmit power of up to 10 dBm at the cost of higher spectral side lobes and higher harmonic power. In Basic Operating Mode a transmission is started from PLL_ON state by either writing TX_START to register bits TRX_CMD (register 0x02, TRX_STATE) or by a rising edge of SLP_TR. In Extended Operating Modes, a transmission might be started automatically depending on the transaction phase of either RX_AACK or TX_ARET, refer to section 5.2. 7.3.2 Frame Transmit Procedure The frame transmit procedure including writing PSDU data into the Frame Buffer and initiating a transmission is described in section 8.2. 7.3.3 Spectrum Masks The AT86RF212 can be operated in different frequency bands, using different power levels, modulation schemes, chip rates, and pulse shaping filters. The occupied bandwidth of transmit signals depends on the chosen mode of operation, refer to Table 7-9. Knowledge of modulation bandwidth, power spectrum, and side lobes is essential for proper system setup, i.e. non-overlapping channel spacing. 100 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 7-9. Modulation, Pulse Shaping, and Occupied Bandwidth Modulation Chip Rate [kchip/s] 300 600 O-QPSK 400 1000 Pulse Shaping 99% Occupied Bandwidth [kHz] 385 750 370 1210 1210 6 dB Bandwidth [kHz] 310 535 290 840 870 20 dB Bandwidth [kHz] 430 825 400 1230 1300 BPSK RC-1.0 RC-1.0 SIN and RC-0.2 SIN RC-0.8 Figure 7-4 to Figure 7-8 show power spectra for different parameter combinations listed in Table 7-9. Note that not all combinations are compliant with IEEE 802.15.4-2006. The spectra were captured using default settings of AT86RF212. The resolution bandwidth of the spectrum analyzer was set to 30 kHz. The video bandwidth was set to 10 kHz. Figure 7-4. Spectrum of BPSK with Chip Rate of 300 kchip/s 0 -10 -20 Power [dBm] -30 -40 -50 -60 -70 912 913 914 Frequency [MHz] 915 916 101 8168B-MCU Wireless-02/09 Figure 7-5. Spectrum of BPSK with Chip Rate of 600 kchip/s 0 -10 -20 Power [dBm] -30 -40 -50 -60 -70 912 913 914 Frequency [MHz] 915 916 Figure 7-6. Spectrum of O-QPSK with Chip Rate of 400 kchip/s 0 -10 -20 Power [dBm] -30 -40 -50 -60 -70 912 913 914 Frequency [MHz] 915 916 102 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Figure 7-7. Spectrum of O-QPSK with Chip Rate of 1000 kchip/s and Sinewave Pulse Shaping 0 -10 -20 Power [dBm] -30 -40 -50 -60 -70 910 912 914 Frequency [MHz] 916 918 Figure 7-8. Spectrum of O-QPSK with Chip Rate of 1000 kchip/s and Raised Cosine Pulse Shaping 0 -10 -20 Power [dBm] -30 -40 -50 -60 -70 910 912 914 Frequency [MHz] 916 918 103 8168B-MCU Wireless-02/09 Figure 7-4 to Figure 7-8 illustrate typical spectra of the transmitted signals of the AT86RF212 and do not claim any limits. Refer to the local authority bodies (FCC, ETSI etc.) for further details about definition of power spectral density masks, definition of spurious emission, allowed modulation bandwidth, transmit power, and its limits. 7.3.4 TX Output Power The maximum output power of the transmitter is typically 5 dBm in normal mode and 10 dBm in boost mode. The TX output power can be set via register bits TX_PWR (register 0x05, PHY_TX_PWR). The output power of the transmitter can be controlled down to -11 dBm dB with 1 dB resolution. To meet the spectral requirements of the European 868.3 MHz band it is necessary to limit the TX power by appropriate setting of TX_PWR, GC_PA (register 0x05, PHY_TX_PWR) and GC_TX_OFFS (register 0x16, TX_CTRL_0), see Table 7-15 and Table 7-16. 7.3.5 TX Power Ramping To optimize the output power spectral density (PSD), individual transmitter blocks are enabled sequentially. A transmit action is started by either the rising edge of pin SLP_TR or the command TX_START in register 0x02. One symbol period later the data transmission begins. During this time period, the PLL settles to the frequency used for transmission. The PA is enabled prior to the data transmission start. This PA lead time can be adjusted with the value PA_LT in register 0x16 (RF_CTRL_0).The PA is always enabled at the lowest gain value corresponding to GC_PA=0. Then the PA gain is increased automatically to the value set by GC_PA in register 0x16 (RF_CTRL_0). After transmission is completed, TX power ramping down is performed in an inverse order. The control signals associated with TX power ramping are shown in Figure 7-9. In this example, the transmission is initiated with the rising edge of pin 11 (SLP_TR). The radio transceiver state changes from PLL_ON to BUSY_TX. Figure 7-9. TX Power Ramping Example (O-QPSK 250 kbit/s Mode) 0 2 4 6 8 10 12 14 16 18 Length [µs] SLP_TR State PA MODULATION PLL_ON BUSY_TX PA_LT 1 10 1 1 0 01 1 Using an external RF front-end (refer to section 9.4) it may be required to adjust the startup time of the external PA relative to the internal building blocks to optimize the overall PSD. This can be achieved using register bits PA_LT (register 0x16, RF_CTRL_0). 104 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 7.3.6 Register Description Register 0x16 (RF_CTRL_0): This register contains control signals to configure the transmit path. Table 7-10. Register 0x16 (RF_CTRL_0) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 PA_LT[1] R/W 0 3 Reserved R 0 6 PA_LT[0] R/W 0 2 Reserved R 0 5 Reserved R/W 1 1 GC_TX_OFFS[1] R/W 0 4 Reserved R/W 1 0 GC_TX_OFFS[0] R/W 1 • Bit 7:6 – PA_LT These register bits control the lead time of the PA enable signal relative to the TX data start, see Figure 7-9. This allows to enable the PA 2, 4, 6 or 8 µs before the transmit signal starts. The PA enable signal can also be output at pin DIG3/DIG4 to provide a control signal for an external RF front-end, for details refer to section 9.4. Table 7-11. PA Enable Time Relative to the TX start Register Bits PA_LT Value 0 1 2 3 PA Enable Lead Time [μs] 2 4 6 8 Setting PA_LT is only effective in TRX_OFF, PLL_ON and TX_ARET_ON mode. • Bit 5:2 – Reserved • Bit 1:0 – GC_TX_OFFS These register bits provide an offset between the TX power control word TX_PWR (register 0x05, PHY_TX_PWR) and the actual TX power. This 2-bit word is added to the TX power control word before it is applied to the circuit block which adjusts the TX power. It can be used to compensate differences of the average TX power depending of the modulation format, see Table 7-16 . Table 7-12. TX Power Offset Register Bits GC_TX_OFFS Value 0 1 2 3 TX Power Offset [dB] -1 0 +1 +2 Register 0x05 (PHY_TX_PWR): This register controls the transmitter output power. 105 8168B-MCU Wireless-02/09 Table 7-13. Register 0x05 (PHY_TX_PWR) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 PA_BOOST R/W 0 3 TX_PWR[3] R/W 0 6 GC_PA[1] R/W 1 2 TX_PWR[2] R/W 0 5 GC_PA[0] R/W 1 1 TX_PWR[1] R/W 0 4 TX_PWR[4] R/W 0 0 TX_PWR[0] R/W 0 • Bit 7 – PA_BOOST This bit enables the PA boost mode where the TX output power is increased by approximately 5 dB when PA_BOOST=1. In PA boost mode the PA linearity is decreased compared to the normal mode when PA_BOOST=0. This leads to higher spectral side lobes of the TX power spectrum and higher power of the harmonics. Consequently, the higher TX power settings do not fulfill the regulatory requirements of the European 868.3 MHz band regarding spurious emissions in adjacent frequency bands (see ETSI EN 300 220, ERC/REC 70-03, and ERC/DEC/(01)04). • Bit 6:5 – GC_PA These register bits control the gain of the PA by changing its bias current. GC_PA needs to be set in TRX_OFF mode only. It can be used to reduce the supply current in TX mode when a reduced TX power is selected with the TX_PWR control word. A reduced PA bias current causes lower RF gain and lowers the 1 dB- compression point of the PA. Hence, it is advisable to use a reduced bias current of the PA only in combination with lower values of TX_PWR. A reasonable combination of TX_PWR and GC_PA is shown in Table 7-15. Table 7-14. AT86RF212 PA Gain Reduction Relative to the Gain at GC_PA=3 Register Bits GC_PA Value 0 1 2 3 PA Gain [dB] -2.9 -1.3 -0.9 0 • Bit 4:0 – TX_PWR These register bits control the transmitter output power. The value of TX_PWR describes the power reduction relative to the maximum output power. The value GC_TX=0 provides the maximum output power. The resolution is 1 dB per step. Since TX_PWR adjusts the gain in the TX path prior to the PA, the PA bias setting is not optimal for increased values of TX_PWR regarding PA efficiency. PA power efficiency can be improved when PA bias is reduced (decreased GC_PA value) along with the TX power setting (increased TX_PWR value). A recommended combination of TX power control (TX_PWR), PA bias control (GC_PA) and PA boost mode (PA_BOOST) is listed in Table 7-15. It is a recommended mapping of intended TX power to the 8-bit word in register 0x05. The value of TX_PWR shall be within the range of 0 to 12 to guarantee the transmit signal quality. 106 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table 7-15. Recommended PHY_TX_PWR (register 0x05) 915 MHz North American Band PHY Modes: BPSK-40, OQPSK-SIN{250,500,1000} 0xc0 0xa1 0x81 0x82 0x83 0x60 0x61 0x41 0x42 0x22 0x23 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c 0x63 0x64 0x65 0x66 0x46 0x26 0x05 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c Note 5 Note 4 Note 3 0xe7 0xe8 0xe9 0xea 0xcb 0xab 0xac 0xad 0x48 0x27 0x06 0x07 0x08 0x09 0x0a 0x0b 0x0c Note 5 Note 4 0xe7 0xe8 0xe9 0xea 0xca 0xaa 0xab 0x45 0x25 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0a Note 2 Note 1 Mapping of TX Power, Frequency Band, and PHY_TX_PWR (register 0x05) TX Power [dBm] 868.3 MHz European Band PHY Modes: BPSK-20, OQPSK-SIN-RC-{100,200,400} EU1 EU2 780 MHz Chinese Band PHY Modes: OQPSK-RC{250,500,1000} 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 Note 1: Power settings can be used with BPSK 40 kbit/s mode and O-QPSK 250 kbit/s mode. It is recommended to limit the maximum output power of the O-QPSK 500/1000 kbit/s modes because these modes are more sensitive to nonlinearities than the 250 kbit/s mode with larger spreading. Note 2: Power settings can be used with BPSK 40 kbit/s mode and O-QPSK 250/500 kbit/s modes. Note 3: Power settings can be used with all modes. Note 4: Power settings can be used with BPSK 20 kbit/s mode. Spectral side lobes remain < -40dBm. Note 5: Power settings can be used with both BPSK 20 kbit/s mode and O-QPSK 100/200/400 kbit/s modes. Spectral side lobes remain < -40 dBm. 107 8168B-MCU Wireless-02/09 The North American mapping table is optimized for lowest supply current. The more relaxed spectral side lobe requirements of the IEEE 802.15.4 standard are fulfilled. The EU1 and EU2 mapping tables take into account that linearity is needed to keep the out-of-band spurious emissions below the ETSI requirements. The map EU1 takes more supply current than the North American map and uses the normal (linearized) PA mode to provide medium output power up to -1 dBm for O-QPSK 100/200/400 kbit/s modes and 2 dBm for BPSK 20 kbit/s mode. The map EU2 uses the boost mode to provide higher TX power levels at the expense of higher supply current. As a result, the maximum TX power is 3 dBm for O-QPSK with 100/200/400 kbit/s and 5 dBm for BPSK with 20 kbit/s. The Chinese mapping table takes into account that spectral side lobes must remain < -36 dBm according to the requirements defined by the Radio Management of P.R. of China in the Technical Requirements for Micropower (Short Distance) Radio Equipment. Values of Table 7-15 are based on a mode dependent setting of GC_TX_OFFS (register 0x16, RF_CTRL_0), which is shown in Table 7-16. Table 7-16. Mode-dependent setting of GC_TX_OFFS Mode GC_TX_OFFS BPSK 3 O-QPSK 2 Figure 7-10. Supply Current for O-QPSK Modulation depending on TX Power Setting 26 24 22 Supply Current [mA] 20 18 16 14 12 10 -11 -9 -7 -5 -3 -1 1 3 5 North America EU1 EU2 China 7 9 11 TX Pow er [dBm] 108 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 7.4 Frame Buffer The AT86RF212 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other one to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. The Frame Buffer utilizes the SRAM address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and can keep a single IEEE 802.15.4 RX or a single TX frame of maximum length at a time. Frame Buffer access modes are described in section 4.3.2. Frame Buffer access conflicts are indicated by an underrun interrupt IRQ_6 (TRX_UR). Note that this interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame Buffer (overflow). In this case, the content of the Frame Buffer is undefined. Frame Buffer access is only possible if the digital voltage regulator is turned on. This is valid in all device states except in SLEEP state. An access in P_ON state is possible once pin 17 (CLKM) provides the 1 MHz master clock. 7.4.1 Data Management Data in Frame Buffer (received data or data to be transmitted) can be changed by: • • • • Frame Buffer or SRAM write access over SPI Receiving a new frame in BUSY_RX or BUSY_RX_AACK state A change into SLEEP state A RESET By default, there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is received during Frame Buffer read access of a previously received frame, interrupt IRQ_6 (TRX_UR) is issued and the stored data might be overwritten. Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air data rate. For a data rate of 250 kbit/s, a minimum SPI clock rate of 1 MHz is recommended. Finally the microcontroller should check the transferred frame data integrity by an FCS check. To protect the Frame Buffer content against being overwritten by newly incoming frames the radio transceiver state should be changed to PLL_ON state after reception. This can be achieved by writing the command PLL_ON to register bits TRX_CMD (register 0x02, TRX_STATE) while or immediately after receiving the frame. Alternatively, Dynamic Frame Buffer Protection can be used to protect received frames against overwriting, for details refer to section 9.7. Both procedures do not protect the Frame Buffer from overwriting by the microcontroller. In Extended Operating Mode during TX_ARET operation, see 5.2.4, the radio transceiver switches to receive state, if an acknowledgement of a previously transmitted frame was requested. During this period, received frames are evaluated but not stored in the Frame Buffer. This allows the radio transceiver to wait for an acknowledgement frame and retry the frame transmission without writing the frame again. A radio transceiver state change, except a transition to SLEEP state or a reset, does not affect the Frame Buffer content. If the radio transceiver is taken into SLEEP, the Frame Buffer is powered off and the stored data get lost. 109 8168B-MCU Wireless-02/09 7.4.2 Frame Content The AT86RF212 supports an IEEE 802.15.4 compliant frame format as shown in Figure 7-11. Figure 7-11. AT86RF212 Frame Structure 0 Length [octets] 4 5 6 n+3 n+5 n+6 n+7 n+8 Frame Duration Preamble Sequence 4 octets SHR not accessible PHY generated SFD 1 SFD_VALUE PHR Payload n octets (n 0) 14 18 24 9.0 8.5 4.7 0.4 0.2 mA mA mA mA mA mA mA μA 10.8.2 IRX_ON Supply current RX_ON (listen) state 10.8.3 10.8.4 10.8.5 IPLL_ON ITRX_OFF ISLEEP Supply current PLL_ON state Supply current TRX_OFF state Supply current SLEEP state 10.9 Crystal Parameter Requirements No. Symbol Parameter Condition Min. Typ. Max. Units 10.9.1 10.9.2 10.9.3 10.9.4 f0 CL C0 ESR Crystal frequency Load capacitance Crystal shunt capacitance Series resistance 8 16 14 7 100 MHz pF pF Ω 154 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 11 Register Reference The AT86RF212 provides a register space of 64 8-bit registers, used to configure, control, and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value. Bit 5 - Table 11-1. Register Summary Addr. 0x00 0x01 0x02 0x03 0x04 Name TRX_STATUS TRX_STATE TRX_CTRL_0 TRX_CTRL_1 Bit 7 CCA_DONE Bit 6 CCA_STATUS Bit 4 TRX_STATUS[4] TRX_CMD[4] PAD_IO_CLKM[0] RX_BL_CTRL Bit 3 TRX_STATUS[3] TRX_CMD[3] CLKM_SHA_SEL SPI_CMD_MODE[1] Bit 2 TRX_STATUS[2] TRX_CMD[2] CLKM_CTRL[2] SPI_CMD_MODE[0] Bit 1 TRX_STATUS[1] TRX_CMD[1] CLKM_CTRL[1] IRQ_MASK_MODE Bit 0 TRX_STATUS[0] TRX_CMD[0] CLKM_CTRL[0] IRQ_POLARITY Page 39,58,86 TRAC_STATUS[2] TRAC_STATUS[1] TRAC_STATUS[0] PAD_IO[1] PA_EXT_EN PAD_IO[0] IRQ_2_EXT_EN PAD_IO_CLKM[1] TX_AUTO_CRC_ON 40,59 8,120 20,27,61, 78,142, 144,146 0x05 0x06 PHY_TX_PWR PHY_RSSI PA_BOOST RX_CRC_VALID GC_PA[1] RND_VALUE[1] GC_PA[0] RND_VALUE[0] TX_PWR[4] RSSI[4] TX_PWR[3] RSSI[3] TX_PWR[2] RSSI[2] TX_PWR[1] RSSI[1] TX_PWR[0] RSSI[0] 106 78,80, 139 0x07 0x08 PHY_ED_LEVEL ED_LEVEL[7] CCA_REQUEST ED_LEVEL[6] CCA_MODE[1] ED_LEVEL[5] CCA_MODE[0] ED_LEVEL[4] CHANNEL[4] ED_LEVEL[3] CHANNEL[3] ED_LEVEL[2] CHANNEL[2] ED_LEVEL[1] CHANNEL[1] ED_LEVEL[0] CHANNEL[0] 83 86,89, 125 PHY_CC_CCA 0x09 0x0A 0x0B 0x0C CCA_THRES SFD_VALUE TRX_CTRL_2 SFD_VALUE[7] RX_SAFE_MODE SFD_VALUE[6] TRX_OFF_AVDD_EN JCM_EN SFD_VALUE[5] OQPSK_SCRAM_ EN SFD_VALUE[4] OQPSK_SUB1_ RC_EN MASK_CCA_ED_DONE CCA_ED_THRES[3] CCA_ED_THRES[2] CCA_ED_THRES[1] CCA_ED_THRES[0] 87,89 SFD_VALUE[3] BPSK_OQPSK SFD_VALUE[2] SUB_MODE SFD_VALUE[1] OQPSK_DATA_RATE[1] SFD_VALUE[0] 148 OQPSK_DATA_RATE[0] 95,114, 147 ANT_EXT_SW_EN ANT_CTRL[1] ANT_CTRL[0] 140 26 26 113 116 121 126 126 99 105 61,72,90 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 ANT_DIV IRQ_MASK IRQ_STATUS VREG_CTRL BATMON XOSC_CTRL CC_CTRL_0 CC_CTRL_1 RX_SYN RF_CTRL_0 XAH_CTRL_1 FTN_CTRL RF_CTRL_1 PLL_CF PLL_DCU PART_NUM MASK_BAT_LOW BAT_LOW AVREG_EXT XTAL_MODE[3] CC_NUMBER[7] RX_PDT_DIS PA_LT[1] - MASK_TRX_UR TRX_UR AVDD_OK XTAL_MODE[2] CC_NUMBER[6] PA_LT[0] CSMA_LBT_MODE MASK_AMI AMI BATMON_OK XTAL_MODE[1] CC_NUMBER[5] - MASK_TRX_END MASK_RX_START MASK_PLL_UNLOCK MASK_PLL_LOCK TRX_END DVREG_EXT BATMON_VTH[3] XTAL_TRIM[3] CC_NUMBER[3] RX_START DVDD_OK BATMON_VTH[2] XTAL_TRIM[2] CC_NUMBER[2] CC_BAND[2] PLL_UNLOCK BATMON_VTH[1] XTAL_TRIM[1] CC_NUMBER[1] CC_ BAND[1] PLL_LOCK BATMON_VTH[0] XTAL_TRIM[0] CC_NUMBER[0] CC_ BAND[0] CCA_ED_DONE BATMON_HR XTAL_MODE[0] CC_NUMBER[4] - RX_PDT_LEVEL[3] RX_PDT_LEVEL[2] RX_PDT_LEVEL[1] RX_PDT_LEVEL[0] PLL_CF[3] PART_NUM[3] AACK_ACK_TIME PLL_CF[2] PART_NUM[2] GC_TX_OFFS[1] AACK_PROM_MODE GC_TX_OFFS[0] PLL_CF[0] PART_NUM[0] AACK_FLTR_RES_FT AACK_UPLD_RES_FT FTN_START RF_MC[3] PLL_CF_START PLL_DCU_START PART_NUM[7] RF_MC[2] PART_NUM[6] RF_MC[1] PART_NUM[5] RF_MC[0] PLL_CF[4] PART_NUM[4] PLL_CF[1] PART_NUM[1] 128 99 126 127 21 21 21 22 73 73 73 VERSION_NUM VERSION_NUM[7] VERSION_NUM[6] VERSION_NUM[5] VERSION_NUM[4] VERSION_NUM[3] VERSION_NUM[2] VERSION_NUM[1] VERSION_NUM[0] MAN_ID_0 MAN_ID_1 SHORT_ADDR_0 SHORT_ADDR_1 MAN_ID_0[7] MAN_ID_1[7] SHORT_ADDR_0[7] SHORT_ADDR_1[7] MAN_ID_0[6] MAN_ID_1[6] SHORT_ADDR_0[6] SHORT_ADDR_1[6] MAN_ID_0[5] MAN_ID_1[5] SHORT_ADDR_0[5] SHORT_ADDR_1[5] MAN_ID_0[4] MAN_ID_1[4] SHORT_ADDR_0[4] SHORT_ADDR_1[4] MAN_ID_0[3] MAN_ID_1[3] SHORT_ADDR_0[3] SHORT_ADDR_1[3] MAN_ID_0[2] MAN_ID_1[2] SHORT_ADDR_0[2] SHORT_ADDR_1[2] MAN_ID_0[1] MAN_ID_1[1] SHORT_ADDR_0[1] SHORT_ADDR_1[1] MAN_ID_0[0] MAN_ID_1[0] SHORT_ADDR_0[0] SHORT_ADDR_1[0] PAN_ID_0 PAN_ID_0[7] PAN_ID_0[6] PAN_ID_0[5] PAN_ID_0[4] PAN_ID_0[3] PAN_ID_0[2] PAN_ID_0[1] PAN_ID_0[0] 155 8168B-MCU Wireless-02/09 Addr. 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F …. Name PAN_ID_1 IEEE_ADDR_0 IEEE_ADDR_1 IEEE_ADDR_2 IEEE_ADDR_3 IEEE_ADDR_4 IEEE_ADDR_5 IEEE_ADDR_6 IEEE_ADDR_7 Bit 7 PAN_ID_1[7] IEEE_ADDR_0[7] IEEE_ADDR_1[7] IEEE_ADDR_2[7] IEEE_ADDR_3[7] IEEE_ADDR_4[7] IEEE_ADDR_5[7] IEEE_ADDR_6[7] IEEE_ADDR_7[7] Bit 6 PAN_ID_1[6] IEEE_ADDR_0[6] IEEE_ADDR_1[6] IEEE_ADDR_2[6] IEEE_ADDR_3[6] IEEE_ADDR_4[6] IEEE_ADDR_5[6] IEEE_ADDR_6[6] IEEE_ADDR_7[6] Bit 5 PAN_ID_1[5] IEEE_ADDR_0[5] IEEE_ADDR_1[5] IEEE_ADDR_2[5] IEEE_ADDR_3[5] IEEE_ADDR_4[5] IEEE_ADDR_5[5] IEEE_ADDR_6[5] IEEE_ADDR_7[5] Bit 4 PAN_ID_1[4] IEEE_ADDR_0[4] IEEE_ADDR_1[4] IEEE_ADDR_2[4] IEEE_ADDR_3[4] IEEE_ADDR_4[4] IEEE_ADDR_5[4] IEEE_ADDR_6[4] IEEE_ADDR_7[4] Bit 3 PAN_ID_1[3] IEEE_ADDR_0[3] IEEE_ADDR_1[3] IEEE_ADDR_2[3] IEEE_ADDR_3[3] IEEE_ADDR_4[3] IEEE_ADDR_5[3] IEEE_ADDR_6[3] IEEE_ADDR_7[3] Bit 2 PAN_ID_1[2] IEEE_ADDR_0[2] IEEE_ADDR_1[2] IEEE_ADDR_2[2] IEEE_ADDR_3[2] IEEE_ADDR_4[2] IEEE_ADDR_5[2] IEEE_ADDR_6[2] IEEE_ADDR_7[2] Bit 1 PAN_ID_1[1] IEEE_ADDR_0[1] IEEE_ADDR_1[1] IEEE_ADDR_2[1] IEEE_ADDR_3[1] IEEE_ADDR_4[1] IEEE_ADDR_5[1] IEEE_ADDR_6[1] IEEE_ADDR_7[1] Bit 0 PAN_ID_1[0] IEEE_ADDR_0[0] IEEE_ADDR_1[0] IEEE_ADDR_2[0] IEEE_ADDR_3[0] IEEE_ADDR_4[0] IEEE_ADDR_5[0] IEEE_ADDR_6[0] IEEE_ADDR_7[0] Page 73 74 74 74 74 75 75 75 75 63 63 64,75 65 XAH_CTRL_0 MAX_FRAME_RETRIES[3] MAX_FRAME_RETRIES[2] MAX_FRAME_RETRIES[1] MAX_FRAME_RETRIES[0] MAX_CSMA_RETRIES[2] MAX_CSMA_RETRIES[1] MAX_CSMA_RETRIES[0] SLOTTED_OPERATION CSMA_SEED_0 CSMA_SEED_0[7] CSMA_SEED_0[6] CSMA_SEED_0[5] CSMA_SEED_0[4] CSMA_SEED_0[3] CSMA_SEED_0[2] CSMA_SEED_0[1] CSMA_SEED_0[0] CSMA_SEED_1 AACK_FVN_MODE[1] CSMA_BE MAX_BE[3] AACK_FVN_MODE[0] AACK_SET_PD MAX_BE[1] - AACK_DIS_ACK MAX_BE[0] - AACK_I_AM_COORD CSMA_SEED_1[2] CSMA_SEED_1[1] CSMA_SEED_1[0] MAX_BE[2] - MIN_BE[3] - MIN_BE[2] - MIN_BE[1] - MIN_BE[0] - The reset values of the AT86RF212 registers in state P_ON(1, 2, 3) are shown in Table 11-2. Note: All reset values in Table 11-2 are only valid after a power on reset. After a reset procedure (/RST = L) as described in section 5.1.4.5, the reset values of selected registers (e.g. registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 11-2. Reset Value Address Reset Value Address Reset Value Table 11-2. Register Summary – Reset Values Address Reset Value Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x00 0x00 0x00 0x19 0x20 0x60 0x00 0xFF 0x25 0x77 0x17 0xA7 0x24 0x01 0x00 0x00 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Notes: 0x00 0x02 0x00 0x00 0x00 0x31 0x00 0x58 0x00 0x48 0x40 0x06 0x01 (1) (2) 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x38 0xEA 0x42 0x53 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x00(3) 0x00 0x00 0x00 0x3F 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x00 0x00 0x00 0xF0 0x1F 0x00 1. While the reset value of register 0x10 is 0x00, any practical access to the register is only possible when DVREG is active. So this register is always read out as 0x04. For details refer to section 7.5. 2. While the reset value of register 0x11 is 0x02, any practical access to the register is only possible when BATMON is activated. So this register is always read out as 0x22 in P_ON state. For details refer to section 7.6. 156 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 3. While the reset value of register 0x30 is 0x00, any practical access to the register is only possible when the radio transceiver is accessible. So the register is usually read out as: a) 0x11 after a reset in P_ON state b) 0x07 after a reset in any other state 157 8168B-MCU Wireless-02/09 12 Abbreviations ACK ADC AES AGC AVREG AWGN BATMON BBP BPF BPSK CBC CCA CF CRC CS CSMA-CA CW DAC DVREG ECB ED ESD FCF FCS FIFO FTN IC IF I/O IRQ ISM LBT LDO LNA LO LPF LQI LSB MAC MHR MIC MISO MOSI MSB MSDU O-QPSK PA PAN PER PHR PHY PLL 158 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Acknowledgement Analog-to-Digital Converter Advanced Encryption Standard Automatic Gain Control Analog Voltage Regulator Additive White Gaussian Noise Battery Monitor Base-Band Processor Band-Pass Filter Binary Phase Shift Keying Cipher Block Chaining Clear Channel Assessment Center Frequency Cyclic Redundancy Check Carrier Sense Carrier Sense Multiple Access – Collision Avoidance Continuous Wave Digital-to-Analog Converter Digital Voltage Regulator Electronic Code Book Energy Detect Electro Static Discharge Frame Control Field Frame Check Sequence First In First Out Filter Tuning Integrated Circuit Intermediate Frequency Input/Output Interrupt Request Industrial Scientific Medical Listen Before Talk Low Dropout Low-Noise Amplifier Local Oscillator Low-Pass Filter Link Quality Indication Least Significant Bit Medium Access Control MAC Header Message Integrity Code Master Input Slave Output Master Output Slave Input Most Significant Bit MAC Service Data Unit Offset Quadrature Phase Shift Keying Power Amplifier Personal Area Network Packet Error Rate PHY Header Physical Layer Phase-Looked Loop AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 PPDU PPF PRBS PSD PSDU QFN RC RF RSSI RX SFD SHR SPI SRAM SRD TRX TX VCO WPAN XOSC XTAL — — — — — — — — — — — — — — — — — — — — — PHY Protocol Data Unit Poly-Phase Filter Pseudo Random Binary Sequence Power Spectrum Density PHY Service Data Unit Quad Flat No-Lead Package Raised Cosine Radio Frequency Received Signal Strength Indicator Receiver Start-Of-Frame Delimiter Synchronization Header Serial Peripheral Interface Static Random Access Memory Short Range Device Transceiver Transmitter Voltage Controlled Oscillator Wireless Personal Area Network Crystal Oscillator Crystal 159 8168B-MCU Wireless-02/09 13 Ordering Information Ordering Code Package Voltage Range Temperature Range AT86RF212-ZU QN 1.8V – 3.6V Industrial (-40° C to +85° C) Lead-free/Halogen-free Package Type Description QN 32QN2, 32-lead 5.0x5.0 mm Body, 0.50 mm Pitch, Quad Flat No-lead Package (QFN) Sawn Note: T&R quantity 4,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities. 14 Soldering Information Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C. 15 Package Thermal Properties Thermal Resistance Velocity [m/s] 0 1 2.5 Theta ja [K/W] 40.9 35.7 32.0 160 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 16 Package Drawing – 32QN2 161 8168B-MCU Wireless-02/09 Appendix A – Continuous Transmission Test Mode A.1 – Overview The AT86RF212 offers a Continuous Transmission Test Mode to support application / production tests as well as certification tests. Using this test mode, the radio transceiver transmits continuously a previously transferred frame (PRBS mode) or a continuous wave signal (CW mode). In CW mode four different signal frequencies per channel can be transmitted: • • • • f1 = fCH + 0.25 MHz f2 = fCH - 0.25 MHz f3 = fCH + 0.1 MHz f4 = fCH - 0.1 MHz using O-QPSK 1000 kbit/s mode using O-QPSK 1000 kbit/s mode using O-QPSK 400 kbit/s mode using O-QPSK 400 kbit/s mode fCH is the channel center frequency, refer to section 7.8.2. Note, in CW mode it is not possible to transmit an RF signal directly on the channel center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR (see section 6.1). It is recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data for the PRBS mode. After transmission of two symbols, PSDU data is repeated continuously. A.2 – Configuration Before enabling Continuous Transmission Test Mode all register configurations shall be done as follows: • TX channel setting (optional) • TX output power setting (optional) • Mode selection (PRBS / CW) Register write accesses to register 0x36 and 0x1C enable the Continuous Transmission Test Mode. The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the TX_START command to register 0x02. Even for CW signal transmission it is required to write valid PSDU data to the Frame Buffer. For PRBS mode it is recommended to write a frame of maximum length. The detailed programming sequence is shown in Table A-1. The column R/W informs about writing (W) or reading (R) a register or the Frame Buffer. The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum length for the PSDU data. To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer, for details refer to Table A-2. 162 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Table A-1. Continuous Transmission Programming Sequence Step Action Register R/W Value Description 1 2 3 4 5 6 7 8 9 RESET Register Access Register Access Register Access Register Access Register Access Register Access Register Access Register Access 0x01 0x36 0x0C 0x0E 0x04 0x02 W W W W W R W W 0x08 0x0F 0x01 0x00 0x03 Reset AT86RF212 Set IRQ mask register, enable IRQ_0 (PLL_LOCK) Disable TX_AUTO_CRC_ON Set radio transceiver state TRX_OFF Set channel, refer to section 7.8.2. Set TX output power, refer to section 7.3.4 Verify TRX_OFF state Enable Continuous Transmission Test Mode – step # 1 CW mode: Enable High Data Rate Mode without scrambler, 400 kbit/s or 1000 kbit/s (register values 0x0A or 0X0E, respectively) PRBS mode: Select modulation scheme, refer to section 7.1.5 10 Frame Buffer Write Access Register Access Register Access Register Access Interrupt event Register Access Measurement Register Access RESET 0x1C 0x1C 0x1C 0x02 0x0F 0x02 W Write PSDU data (even for CW mode), refer to Table A-2. Frame Buffer content varies for different modulation schemes. 0x54 0x46 0x09 0x01 0x02 Enable Continuous Transmission Test Mode – step # 2 Enable Continuous Transmission Test Mode – step # 3 Enable PLL_ON state Wait for IRQ_0 (PLL_LOCK) Initiate Transmission, enter BUSY_TX state Perform measurement Disable Continuous Transmission Test Mode Reset AT86RF212 11 12 13 14 15 16 17 18 W W W R W W 0x00 Table A-2. Frame Buffer Content for various Continuous Transmission Modulation Schemes Step Action Frame Content Comment 10 Frame Buffer Access Random Sequence 0x00 (each byte) 0xFF (each byte) modulated RF signal fCH – 0.1 MHz, CW signal fCH – 0.25 MHz, CW signal fCH + 0.1 MHz, CW signal fCH + 0.25 MHz, CW signal 163 8168B-MCU Wireless-02/09 A.3 – Register Description Register 0x36 (TST_CTRL_DIGI): Register TST_CTRL_DIGI enables the continuous transmission test mode. Table A-3. Register 0x36 (TST_CTRL_DIGI) Bit Name Read/Write Reset Value Bit Name Read/Write Reset Value 7 Reserved R/W 0 3 TST_CTRL_DIG R/W 0 6 Reserved R/W 0 2 TST_CTRL_DIG R/W 0 5 Reserved R/W 0 1 TST_CTRL_DIG R/W 0 4 Reserved R/W 0 0 TST_CTRL_DIG R/W 0 • Bit 7:4 – Reserved • Bit 3:0 – TX_CTRL_DIG These register bits enable continuous transmission: Table A-4. Continuous Transmission Register Bits Value Description TST_CTRL_DIG 0x0 0xF 0x1 – 0xE Continuous Transmission disabled Continuous Transmission enabled Reserved 164 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Appendix B – Errata AT86RF212 Rev. A No known errata. 165 8168B-MCU Wireless-02/09 References [1] IEEE Standard 802.15.4TM-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs) IEEE Standard 802.15.4TM-2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (WPANs) IEEE P802.15.4cTM/D6, November 2008: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs): Amendment 2: Alternative Physical Layer Extension to support one or more of the Chinese 314-316 MHz, 430-434 MHz, and 779-787 MHz bands. ETSI EN 300 220-1 V2.2.1 (2008-04): Electromagnetic compatibility and Radio spectrum Matters (ERM); Short Range Devices (SRD); Radio equipment to be used in the 25 MHz to 1 000 MHz frequency range with power levels ranging up to 500 mW; Part 1: Technical characteristics and test methods ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Human Body Model (HBM). ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing – Charged Device Model (CDM). NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 [2] [3] [4] [5] [6] [7] 166 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 Data Sheet Revision History Rev. 8168B-MCU Wireless-02/09 1. Operation in the Chinese 780 MHz band added 2. Section 7.7.5 on Clock Jitter added 3. Update of Table 7-15 and parameters in section 10 4. Editorial changes Rev. 8168A-AVR-06/08 1. Initial release 167 8168B-MCU Wireless-02/09 Table of Contents 1 Overview ..............................................................................................2 1.1 General Circuit Description .................................................................................... 2 2 Pin Configuration................................................................................4 2.1 Pin-out Diagram...................................................................................................... 4 2.2 Pin Description ....................................................................................................... 4 3 Application Circuits ..........................................................................10 3.1 Basic Application Schematic ................................................................................ 10 3.2 Extended Feature Set Application Schematic...................................................... 11 4 Microcontroller Interface ..................................................................13 4.1 Overview............................................................................................................... 13 4.2 SPI Timing Description......................................................................................... 14 4.3 SPI Protocol.......................................................................................................... 15 4.4 PHY Status Information........................................................................................ 20 4.5 Radio Transceiver Identification ........................................................................... 21 4.6 Sleep/Wake-up and Transmit Signal (SLP_TR)................................................... 22 4.7 Interrupt Logic....................................................................................................... 24 5 Operating Modes...............................................................................29 5.1 Basic Operating Mode.......................................................................................... 29 5.2 Extended Operating Mode ................................................................................... 41 6 Functional Description .....................................................................66 6.1 Introduction – IEEE 802.15.4-2006 Frame Format .............................................. 66 6.2 Frame Filter .......................................................................................................... 70 6.3 Frame Check Sequence (FCS) ............................................................................ 76 6.4 Received Signal Strength Indicator (RSSI) .......................................................... 79 6.5 Energy Detection (ED) ......................................................................................... 81 6.6 Clear Channel Assessment (CCA)....................................................................... 83 6.7 Listen Before Talk (LBT) ...................................................................................... 88 6.8 Link Quality Indication (LQI) ................................................................................. 90 7 Module Description...........................................................................92 7.1 Physical Layer Modes .......................................................................................... 92 7.2 Receiver (RX) ....................................................................................................... 97 7.3 Transmitter (TX) ................................................................................................. 100 7.4 Frame Buffer....................................................................................................... 109 7.5 Voltage Regulators (AVREG, DVREG).............................................................. 111 7.6 Battery Monitor (BATMON) ................................................................................ 115 168 AT86RF212 8168B-MCU Wireless-02/09 AT86RF212 7.7 Crystal Oscillator (XOSC) and Clock Output (CLKM) ........................................ 117 7.8 Frequency Synthesizer (PLL)............................................................................. 122 7.9 Automatic Filter Tuning (FTN) ............................................................................ 127 8 Radio Transceiver Usage ...............................................................129 8.1 Frame Receive Procedure ................................................................................. 129 8.2 Frame Transmit Procedure ................................................................................ 130 9 Extended Feature Set .....................................................................131 9.1 Security Module (AES) ....................................................................................... 131 9.2 Random Number Generator............................................................................... 138 9.3 Differential Output supporting Software controlled Antenna Diversity ............... 139 9.4 RX/TX Indicator .................................................................................................. 141 9.5 RX Frame Time Stamping.................................................................................. 143 9.6 Frame Buffer Empty Indicator ............................................................................ 145 9.7 Dynamic Frame Buffer Protection ...................................................................... 146 9.8 Configurable Start-Of-Frame Delimiter (SFD).................................................... 148 10 Electrical Characteristics .............................................................149 10.1 Absolute Maximum Ratings.............................................................................. 149 10.2 Operating Range .............................................................................................. 149 10.3 Digital Pin Specifications .................................................................................. 149 10.4 Digital Interface Timing Characteristics............................................................ 150 10.5 General Transceiver Specifications ................................................................. 151 10.6 Transmitter Characteristics .............................................................................. 152 10.7 Receiver Characteristics .................................................................................. 153 10.8 Current Consumption Specifications................................................................ 154 10.9 Crystal Parameter Requirements ..................................................................... 154 11 Register Reference .......................................................................155 12 Abbreviations ................................................................................158 13 Ordering Information ....................................................................160 14 Soldering Information...................................................................160 15 Package Thermal Properties........................................................160 16 Package Drawing – 32QN2 ...........................................................161 Appendix A – Continuous Transmission Test Mode ...................... 162 A.1 – Overview ......................................................................................................... 162 A.2 – Configuration................................................................................................... 162 A.3 – Register Description........................................................................................ 164 Appendix B – Errata...........................................................................165 169 8168B-MCU Wireless-02/09 AT86RF212 Rev. A .................................................................................................. 165 References..........................................................................................166 Data Sheet Revision History .............................................................167 Rev. 8168B-MCU Wireless-02/09 ............................................................................ 167 Rev. 8168A-AVR-06/08............................................................................................ 167 Table of Contents...............................................................................168 170 AT86RF212 8168B-MCU Wireless-02/09 Disclaimer Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Request www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. 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