AT86RF231

Features • High Performance RF-CMOS 2.4 GHz Radio Transceiver Targeted for IEEE 802.15.4™, ZigBee™ and ISM Applications • Industry Leading Link Budget (104 dB) – Receiver Sensitivity -101 dBm – Programmable Output Power from -17 dBm up to +3 dBm • Ultra-Low Current Consumption: – SLEEP = 0.02 µA – TRX_OFF = 0.4 mA – RX_ON = 13.2 mA – BUSY_TX = 14.3 mA (at max. Transmit Power of +3 dBm) • Ultra-Low Supply Voltage (1.8V to 3.6V) with Internal Regulator • Optimized for Low BoM Cost and Ease of Production: – Few External Components Necessary (Crystal, Capacitors and Antenna) – Excellent ESD Robustness Easy to Use Interface: – Registers, Frame Buffer and AES Accessible through Fast SPI – Only Two Microcontroller GPIO Lines Necessary – One Interrupt Pin from Radio Transceiver – Clock Output with Prescaler from Radio Transceiver Radio Transceiver Features: – 128-byte FIFO (SRAM) for Data Buffering – Programmable Clock Output, to Clock the Host Microcontroller or as Timer Reference – Integrated RX/TX Switch – Fully Integrated, Fast Settling PLL to support Frequency Hopping – Battery Monitor – Fast Wake-Up Time < 0.25 msec Special IEEE 802.15.4-2006 Hardware Support: – FCS Computation and Clear Channel Assessment – RSSI Measurement, Energy Detection and Link Quality Indication MAC Hardware Accelerator: – Automated Acknowledgement, CSMA-CA and Retransmission – Automatic Address Filtering – Automated FCS Check Extended Feature Set Hardware Support: – AES 128bit Hardware Accelerator – RX/TX Indication (external RF Front-End Control) – RX Antenna Diversity – Supported PSDU data rates: 250 kb/s, 500 kb/s, 1 Mb/s and 2 Mb/s – True Random Number Generation for Security Application Industrial Temperature Range: – -40° C to +85° C I/O and Packages: – 32-pin Low-Profile QFN Package 5 x 5 x 0.9 mm³ – RoHS/Fully Green Compliant to IEEE 802.15.4-2006 and IEEE 802.15.4-2003 Compliant to EN 300 328/440, FCC-CFR-47 Part 15, ARIB STD-66, RSS-210 • • Low power 2.4 GHz Transceiver for ZigBee, IEEE 802.15.4, and ISM Applications • AT86RF231 Preliminary • • • • • • 8111A–AVR–05/08 1. Pin-out Diagram Figure 1-1. AT86RF231 Pin-out Diagram X TA L 1 X TA L 2 A V DD E V DD AVSS AVSS AVSS AVSS D IG 3 D IG 4 AVSS R FP R FN AVSS D VSS /R S T 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 exposed paddle IR Q /SEL M OSI D VSS M IS O SC LK D VSS C LKM AVSS 23 22 21 20 19 18 A T86 R F2 3 1 17 9 10 11 12 13 14 15 16 D VSS S L P _ TR Note: The exposed paddle is electrically connected to the die inside the package. It shall be soldered to the board to ensure electrical and thermal contact and good mechanical stability. 2 AT86RF231 8111A–AVR–05/08 DE V D D DV D D DV D D D VSS DI G 1 DI G 2 AT86RF231 1.1 Pin Descriptions Pin Description AT86RF231 Name DIG3 DIG4 AVSS RFP RFN AVSS DVSS /RST DIG1 Type Digital output (Ground) Digital output (Ground) Ground RF I/O RF I/O Ground Ground Digital input Digital output (Ground) Description 1. RX/TX Indicator, see Section 11.5 2. If disabled, pull-down enabled (AVSS) 1. RX/TX indicator (DIG3 inverted), see Section 11.5 2. If disabled, pull-down enabled (AVSS) Ground for RF signals Differential RF signal Differential RF signal Ground for RF signals Digital ground Chip reset; active low 1. Antenna Diversity RF switch control, see Section 11.4 2. If disabled, pull-down enabled (DVSS) 1. Antenna Diversity RF switch control (DIG1 inverted), see Section 11.4 2. Signal IRQ_2 (RX_START) for RX Frame Time Stamping, see Section 11.6 3. If functions disabled, pull-down enabled (DVSS) Controls sleep, transmit start, receive states; active high, see Section 6.5 Digital ground Regulated 1.8V voltage regulator; digital domain, see Section 9.4 Regulated 1.8V voltage regulator; digital domain, see Section 9.4 External supply voltage; digital domain Digital ground Master clock signal output; low if disabled, see Section 9.6 Digital ground SPI clock SPI data output (Master Input Slave Output) Digital ground SPI data input (Master Output Slave Input) SPI select, active low 1. Interrupt request signal; active high or active low; configurable 2. Frame Buffer Empty Indicator; active high, see Section 11.7 Crystal pin, see Section 9.6 Crystal pin or external clock supply, see Section 9.6 Analog ground External supply voltage, analog domain Table 1-1. Pins 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 DIG2 SLP_TR DVSS DVDD DVDD DEVDD DVSS CLKM DVSS SCLK MISO DVSS MOSI /SEL IRQ XTAL2 XTAL1 AVSS EVDD Digital output (Ground) Digital input Ground Supply Supply Supply Ground Digital output Ground Digital input Digital output Ground Digital input Digital input Digital output Analog input Analog input Ground Supply 3 8111A–AVR–05/08 Table 1-1. Pins 29 30 31 32 Paddle Pin Description AT86RF231 (Continued) Name AVDD AVSS AVSS AVSS AVSS Type Supply Ground Ground Ground Ground Description Regulated 1.8V voltage regulator; analog domain, see Section 9.4 Analog ground Analog ground Analog ground Analog ground; Exposed paddle of QFN package 4 AT86RF231 8111A–AVR–05/08 AT86RF231 1.2 1.2.1 Analog and RF Pins Supply and Ground Pins EVDD, DEVDD EVDD and DEVDD are analog and digital supply voltage pins of the AT86RF231 radio transceiver. AVDD, DVDD AVDD and DVDD are outputs of the internal 1.8V voltage regulators. The voltage regulators are controlled independently by the radio transceivers state machine and are activated dependent on the current radio transceiver state. The voltage regulators can be configured for external supply. For details, refer to Section 9.4 “Voltage Regulators (AVREG, DVREG)” on page 110. AVSS, DVSS AVSS and DVSS are analog and digital ground pins respectively. The analog and digital power domains should be separated on the PCB. 1.2.2 RF Pins RFN, RFP A differential RF port (RFP/RFN) provides common-mode rejection to suppress the switching noise of the internal digital signal processing blocks. At board-level, the differential RF layout ensures high receiver sensitivity by rejecting any spurious emissions originated from other digital ICs such as a microcontroller. The RF port is designed for a 100Ω differential load. A DC path between the RF pins is allowed. A DC path to ground or supply voltage is not allowed. Therefore, when connecting an RF-load providing a DC path to the power supply or ground, AC-coupling is required as indicated in Table 1-2 on page 6. A simplified schematic of the RF front end is shown in Figure 1-2 on page 5. Figure 1-2. Simplified RF Front-end Schematic PCB AT86RF231 LNA RX RFP RFN PA TX 0.9V M0 CM Feedback RXTX 5 8111A–AVR–05/08 The RF port DC values depend on the operating state, refer to Section 7. “Operating Modes” on page 33. In TRX_OFF state, when the analog front-end is disabled (see Section 7.1.2.3 “TRX_OFF Clock State” on page 35), the RF pins are pulled to ground, preventing a floating voltage. In transmit mode, a control loop provides a common-mode voltage of 0.9V. Transistor M0 is off, allowing the PA to set the common-mode voltage. The common-mode capacitance at each pin to ground shall be < 30 pF to ensure the stability of this common-mode feedback loop. In receive mode, the RF port provides a low-impedance path to ground when transistor M0, see Figure 1-2 on page 5, pulls the inductor center tap to ground. A DC voltage drop of 20 mV across the on-chip inductor can be measured at the RF pins. 1.2.3 Crystal Oscillator Pins XTAL1, XTAL2 The pin XTAL1 is the input of the reference oscillator amplifier (XOSC), XTAL2 is the output. A detailed description of the crystal oscillator setup and the related XTAL1/XTAL2 pin configuration can be found in Section 9.6 “Crystal Oscillator (XOSC)” on page 116. When using an external clock reference signal, XTAL1 shall be used as input pin. For further details, refer to Section 9.6.3 “External Reference Frequency Setup” on page 117. 1.2.4 Analog Pin Summary Table 1-2. Pin RFP/RFN Analog Pin Behavior - DC values Values and Conditions VDC = 0.9V (BUSY_TX) VDC = 20 mV (receive states) VDC = 0 mV (otherwise) VDC = 0.9V at both pins CPAR = 3 pF VDC = 1.8V (all states, except SLEEP) VDC = 0 mV (otherwise) VDC = 1.8V (all states, except P_ON, SLEEP, RESET, and TRX_OFF) VDC = 0 mV (otherwise) Comments DC level at pins RFP/RFN for various transceiver states AC coupling is required if an antenna with a DC path to ground is used. Serial capacitance and capacitance of each pin to ground must be < 30 pF. DC level at pins XTAL1/XTAL2 for various transceiver states Parasitic capacitance (CPAR) of the pins must be considered as additional load capacitance to the crystal. DC level at pin DVDD for various transceiver states Supply pins (voltage regulator output) for the digital 1.8V voltage domain, recommended bypass capacitor 1 µF. DC level at pin AVDD for various transceiver states Supply pin (voltage regulator output) for the analog 1.8V voltage domain, recommended bypass capacitor 1 µF. XTAL1/ XTAL2 DVDD AVDD 6 AT86RF231 8111A–AVR–05/08 AT86RF231 1.3 Digital Pins The AT86RF231 provides a digital microcontroller interface. The interface comprises a slave SPI (/SEL, SCLK, MOSI and MISO) and additional control signals (CLKM, IRQ, SLP_TR, /RST and DIG2). The microcontroller interface is described in detail in Section 6. “Microcontroller Interface” on page 16. Additional digital output signals DIG1...DIG4 are provided to control external blocks, i.e. for Antenna Diversity RF switch control or as an RX/TX Indicator, see Section 11.4 “Antenna Diversity” on page 142 and Section 11.5 “RX/TX Indicator” on page 147. After reset, these pins are pulled-down to digital ground (DIG1/DIG2) or analog ground (DIG3/DIG4). 1.3.1 Driver Strength Settings The driver strength of all digital output pins (MISO, IRQ, DIG1, DIG2, DIG3, DIG4) and CLKM pin can be configured using register 0x03 (TRX_CTRL_0), see Table 1-3 on page 7. Digital Output Driver Configuration Default Driver Strength 2 mA 4 mA Recommendation/Comment Adjustable to 2 mA, 4 mA, 6 mA and 8 mA Adjustable to 2 mA, 4 mA, 6 mA and 8 mA Table 1-3. Pins MISO, IRQ, DIG1,....., DIG4 CLKM The capacitive load should be as small as possible as, not larger than 50 pF when using the 2 mA minimum driver strength setting. Generally, the output driver strength should be adjusted to the lowest possible value in order to keep the current consumption and the emission of digital signal harmonics low. 1.3.2 Pull-Up and Pull-Down Configuration Pulling resistors are internally connected to all digital input pins in radio transceiver state P_ON, see Section 7.1.2.1 “P_ON - Power-On after VDD” on page 34. Table 1-4 on page 7 summarizes the pull-up and pull-down configuration. Table 1-4. Pull-Up / Pull-Down Configuration of Digital Input Pins in P_ON State Pins /RST /SEL SCLK MOSI SLP_TR ˆ ˆ H = pull-up, L = pull-down H H L L L In all other states, there are no pull-up or pull-down resistors connected to any of the digital input pins. In RESET state, the pull-up or pull-down resistors are not enabled. 7 8111A–AVR–05/08 1.3.3 Register Description Register 0x03 (TRX_CTRL_0): The TRX_CTRL_0 register controls the drive current of the digital output pads and the CLKM clock rate. Bit 7 PAD_IO 6 5 PAD_IO_CLKM 4 3 CLKM_SHA_SEL 2 1 CLKM_CTRL 0 TRX_CTRL_0 R/W 1 Read/Write Initial Value R/W 0 R/W 0 R/W 0 R/W 1 R/W 1 R/W 0 R/W 0 • Bit [7:6] - PAD_IO The register bits set the output driver current of all digital output pads, except CLKM. Table 1-5. Register Bit PAD_IO Digital Output Driver Strength Value 0(1) 1 2 3 Description 2 mA 4 mA 6 mA 8 mA Note: 1. Reset values of register bits are underlined characterized in the document. • Bit [5:6] - PAD_IO_CLKM The register bits set the output driver current of pin CLKM. Refer also to Section 9.6 “Crystal Oscillator (XOSC)” on page 116. Table 1-6. Register Bit PAD_IO_CLKM CLKM Driver Strength Value 0 1 2 3 Description 2 mA 4 mA 6 mA 8 mA • Bit 3 - CLKM_SHA_SEL Refer to Section 9.6 “Crystal Oscillator (XOSC)” on page 116. • Bit [2:0] - CLKM_CTRL Refer to Section 9.6 “Crystal Oscillator (XOSC)” on page 116. 8 AT86RF231 8111A–AVR–05/08 AT86RF231 2. Disclaimer Typical values contained in this datasheet are based on simulations and testing. Min and Max values are available when the radio transceiver has been fully characterized. 3. Overview The AT86RF231 is a feature rich, low-power 2.4 GHz radio transceiver designed for industrial and consumer ZigBee/IEEE 802.15.4 and high data rate 2.4 GHz ISM band applications. The radio transceiver is a true SPI-to-antenna solution. All RF-critical components except the antenna, crystal and de-coupling capacitors are integrated on-chip. Therefore, the AT86RF231 is particularly suitable for applications like: • 2.4 GHz IEEE 802.15.4 and ZigBee systems • Wireless sensor networks • Industrial Control • Residential and commercial automation • Health care • Consumer electronics • PC peripherals The AT86RF231 can be operated by using an external microcontroller like Atmel's AVR microcontrollers. A comprehensive software programming description can be found in reference [6], AT86RF231 Software Programming Model. 9 8111A–AVR–05/08 4. General Circuit Description This single-chip radio transceiver provides a complete radio transceiver interface between an antenna and a microcontroller. It comprises the analog radio, digital modulation and demodulation including time and frequency synchronization and data buffering. The number of external components is minimized such that only the antenna, the crystal and decoupling capacitors are required. The bidirectional differential antenna pins (RFP, RFN) are used for transmission and reception, thus no external antenna switch is needed. The AT86RF231 block diagram is shown in Figure 4-1 on page 10. Figure 4-1. AT86RF231 Block Diagram XTAL1 XTAL2 XOSC AVREG DIG3/4 ext. PA and Power Control Configuration Registers PA PLL TX Data TX BBP DVREG SPI (Slave) /SEL MISO MOSI SCLK RFP FTN, BATMON RFN LNA PPF BPF Limiter ADC RX BBP AES Frame Buffer IRQ CLKM DIG2 AGC AD DIG1/2 Analog Domain Antenna Diversity RSSI Control Logic /RST SLP_TR Digital Domain The received RF signal at pins RFN and RFP is differentially fed through the low-noise amplifier (LNA) to the RF filter (PPF) to generate a complex signal, driving the integrated channel filter (BPF). The limiting amplifier provides sufficient gain to drive the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled by the digital base band receiver (RX BBP). The transmit modulation scheme is offset-QPSK (O-QPSK) with half-sine pulse shaping and 32length block coding (spreading) according to [1] and [2]. The modulation signal is generated in the digital transmitter (TX BBP) and applied to the fractional-N frequency synthesis (PLL), to ensure the coherent phase modulation required for demodulation of O-QPSK signals. The frequency-modulated signal is fed to the power amplifier (PA). A differential pin pair DIG3/DIG4 can be enabled to control an external RF front-end. Two on-chip low-dropout voltage regulators (A|DVREG) provide the analog and digital 1.8V supply. 10 AT86RF231 8111A–AVR–05/08 AT86RF231 An internal 128-byte RAM for RX and TX (Frame Buffer) buffers the data to be transmitted or the received data. The configuration of the AT86RF231, reading and writing of Frame Buffer is controlled by the SPI interface and additional control lines. The AT86RF231 further contains comprehensive hardware-MAC support (Extended Operating Mode) and a security engine (AES) to improve the overall system power efficiency and timing. The stand-alone 128-bit AES engine can be accessed in parallel to all PHY operational transactions and states using the SPI interface, except during SLEEP state. For applications not necessarily targeting IEEE 802.15.4 compliant networks, the radio transceiver also supports alternative data rates up to 2 Mb/s. For long-range applications or to improve the reliability of an RF connection the RF performance can further be improved by using an external RF front-end or Antenna Diversity. Both operation modes are supported by the AT86RF231 with dedicated control pins without the interaction of the microcontroller. Additional features of the Extended Feature Set, see Section 11. “AT86RF231 Extended Feature Set” on page 128, are provided to simplify the interaction between radio transceiver and microcontroller. 11 8111A–AVR–05/08 5. Application Circuits 5.1 Basic Application Schematic A basic application schematic of the AT86RF231 with a single-ended RF connector is shown in Figure 5-1 on page 12. The 50Ω single-ended RF input is transformed to the 100Ω differential RF port impedance using balun B1. The capacitors C1 and C2 provide AC coupling of the RF input to the RF port, capacitor C4 improve matching. Figure 5-1. Basic Application Schematic CB2 VDD CB1 32 AVSS 31 AVSS 30 29 AVDD AVSS 28 EVDD 27 AVSS 26 XTAL1 25 XTAL2 CX1 XTAL CX2 1 DIG3 2 DIG4 C1 RF B1 C4 C2 3 AVSS 4 RFP IRQ 24 /SEL 23 MOSI 22 DVSS 21 AT86RF231 5 RFN 6 AVSS 7 DVSS SLP_TR DVDD DVDD DVSS DIG1 DVSS 8 /RST DIG2 DEVDD MISO 20 SCLK 19 DVSS 18 CLKM 17 C3 R1 9 10 11 12 13 14 15 16 VDD CB3 CB4 The power supply decoupling capacitors (CB2, CB4) are connected to the external analog supply pin (EVDD, pin 28) and external digital supply pin (DEVDD, pin 15). Capacitors CB1 and CB3 are bypass capacitors for the integrated analog and digital voltage regulators to ensure stable operation. All decoupling and bypass capacitors should be placed as close as possible to the pins and should have a low-resistance and low-inductance connection to ground to achieve the best performance. The crystal (XTAL), the two load capacitors (CX1, CX2), and the internal circuitry connected to pins XTAL1 and XTAL2 form the crystal oscillator. To achieve the best accuracy and stability of 12 AT86RF231 8111A–AVR–05/08 Digital Interface AT86RF231 the reference frequency, large parasitic capacitances should be avoided. Crystal lines should be routed as short as possible and not in proximity of digital I/O signals. This is especially required for the High Data Rate Modes, refer to Section 11.3 “High Data Rate Modes” on page 137. Crosstalk from digital signals on the crystal pins or the RF pins can degrade the system performance. Therefore, a low-pass filter (C3, R1) is placed close to the CLKM output pin to reduce the emission of CLKM signal harmonics. This is not needed if the CLKM pin is not used as a microcontroller clock source. In that case, the output should be turned off during device initialization. The ground plane of the application board should be separated into four independent fragments, the analog, the digital, the antenna and the XTAL ground plane. The exposed paddle shall act as the reference point of the individual grounds. Table 5-1. Designator B1 CB1 CB3 CB2 CB4 CX1, CX2 Example Bill of Materials (BoM) for Basic Application Schematic Description SMD balun LDO VREG bypass capacitor 1 µF Power Supply decoupling Crystal load capacitor 12 pF AVX Murata Epcos Epcos AVX AVX Murata Johnstech Designed for fCLKM=1 MHz ACAL Taitjen Siward XWBBPL-F-1 A207-011 06035A120JA GRP1886C1H120JA01 B37930 B37920 06035A220JAT2A 06035A229DA GRP1886C1H2R0DA01 COG (0603) COG 5% 5% 50V (0402 or 0603) COG (0603) ±0.5 pF Value 2.4 GHz Manufacture Wuerth Part Number 748421245 Comment AVX Murata 0603YD105KAT2A GRM188R61C105KA12D X5R (0603) 10% 16V C1, C2 RF coupling capacitor 22 pF C3 CLKM low-pass filter capacitor RF matching CLKM low-pass filter resistor Crystal 2.2 pF Designed for fCLKM=1 MHz C4 R1 XTAL 0.47 pF 680Ω CX-4025 16 MHz SX-4025 16 MHz 13 8111A–AVR–05/08 5.2 Extended Feature Set Application Schematic The AT86RF231 supports additional features like: • • • • • Security Module (AES) High Data Rate Mode Antenna Diversity RX/TX indicator RX Frame Time Stamp uses pins DIG1/2 uses pins DIG3/4 uses pin DIG2 see Section 11.1 see Section 11.3 see Section 11.4 see Section 11.5 see Section 11.6 An extended feature set application schematic illustrating the use of the AT86RF231 Extended Feature Set, see Section 11. “AT86RF231 Extended Feature Set” on page 128, is shown in Figure 5-2 on page 14. Although this example shows all additional hardware features combined, it is possible to use all features separately or in various combinations. Figure 5-2. Extended Feature Application Schematic CB2 VDD CB1 32 AVSS 31 AVSS 30 29 AVDD AVSS 28 EVDD 27 AVSS 26 XTAL1 25 XTAL2 CX1 XTAL CX2 1 DIG3 2 DIG4 N2 RFSwitch RFSwitch Balun LNA PA N1 3 AVSS 4 RFP IRQ 24 /SEL 23 MOSI 22 DVSS 21 SW2 AT86RF231 5 RFN 6 AVSS MISO 20 SCLK 19 DVSS 18 SLP_TR DVDD DVDD DEVDD DVSS DIG2 DVSS CLKM 17 C3 R1 SW1 B1 7 DVSS DIG1 8 /RST ANT1 9 10 11 12 13 14 15 16 VDD CB3 CB4 In this example, a balun (B1) transforms the differential RF signal at the radio transceiver RF pins (RFP/RFN) to a single ended RF signal, similar to the Basic Application Schematic; refer to Figure 5-1 on page 12. The RF-Switches (SW1, SW2) separate between receive and transmit path in an external RF front-end. These switches are controlled by the RX/TX Indicator, represented by the differential pin pair DIG3/DIG4, refer to Section 11.5 “RX/TX Indicator” on page 147. During receive the radio transceiver searches for the most reliable RF signal path using the Antenna Diversity algorithm. One antenna is selected (SW2) by the Antenna Diversity RF switch 14 AT86RF231 8111A–AVR–05/08 Digital Interface ANT0 AT86RF231 control pins DIG1/DIG2, the RF signal is amplified by an optional low-noise amplifier (N2) and fed to the radio transceiver using the second RX/TX switch (SW1). During transmit the AT86RF231 TX signal is amplified using an external PA (N1) and fed to the antennas via an RF switch (SW2). In this example RF switch SW2 further supports Antenna Diversity controlled by the differential pin pair DIG1/DIG2. The security engine (AES) and High Data Rate Modes do not require specific circuitry to operate. The security engine (AES) has to be configured in advance, for details refer to Section 11.1 “Security Module (AES)” on page 128. The High Data Rate Modes are enabled by register bits OQPSK_DATA_RATE (register 0x0C, TRX_CTRL_2), for details refer to Section 11.3 “High Data Rate Modes” on page 137. 15 8111A–AVR–05/08 6. Microcontroller Interface This section describes the AT86RF231 to microcontroller interface. The interface comprises a slave SPI and additional control signals; see Figure 6-1 on page 16. The SPI timing and protocol are described below. Figure 6-1. Microcontroller to AT86RF231 Interface Microcontroller SPI - Master /SEL MOSI MISO SCLK SPI /SEL MOSI MISO SCLK CLKM IRQ SLP_TR /RST DIG2 AT86RF231 MOSI MISO SCLK CLKM IRQ SLP_TR /RST DIG2 SPI - Slave /SEL GPIO1/CLK GPIO2/IRQ GPIO3 GPIO4 GPIO5 Microcontrollers with a master SPI such as Atmel's AVR family interface directly to the AT86RF231. The SPI is used for register, Frame Buffer, SRAM and AES access. The additional control signals are connected to the GPIO/IRQ interface of the microcontroller. Table 6-1 on page 16 introduces the radio transceiver I/O signals and their functionality. Table 6-1. Signal /SEL MOSI MISO SCLK CLKM Signal Description of Microcontroller Interface Description SPI select signal, active low SPI data (master output slave input) signal SPI data (master input slave output) signal SPI clock signal Clock output, refer to Section 9.6.4 usable as: -microcontroller clock source -high precision timing reference -MAC timer reference Interrupt request signal, further used as: -Frame Buffer Empty Indicator, refer to Section 11.7 IRQ 16 AT86RF231 8111A–AVR–05/08 AT86RF231 Table 6-1. SLP_TR Signal Description of Microcontroller Interface (Continued) Multipurpose control signal (functionality is state dependent, see Section 6.5): -Sleep/Wakeup enable/disable SLEEP state -TX start BUSY_TX_(ARET) state -disable/enable CLKM RX_(AACK)_ON state AT86RF231 reset signal, active low Optional, IRQ_2 (RX_START) for RX Frame Time Stamping, see Section 11.6 /RST DIG2 6.1 SPI Timing Description Pin 17 (CLKM) can be used as a microcontroller master clock source. If the microcontroller derives the SPI master clock (SCLK) directly from CLKM, the SPI operates in synchronous mode, otherwise in asynchronous mode. In synchronous mode, the maximum SCLK frequency is 8 MHz. In asynchronous mode, the maximum SCLK frequency is limited to 7.5 MHz. The signal at pin CLKM is not required to derive SCLK and may be disabled to reduce power consumption and spurious emissions. Figure 6-2 on page 17 and Figure 6-3 on page 17 illustrate the SPI timing and introduces its parameters. The corresponding timing parameter definitions t1 - t9 are defined in Section 12.4 “Digital Interface Timing Characteristics” on page 157. Figure 6-2. SPI Timing, Global Map and Definition of Timing Parameters t5, t6, t8 and t9 t9 t8 /SEL SCLK MOSI 7 6 5 4 3 2 1 0 t5 7 6 5 4 3 2 1 0 t6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MISO Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Figure 6-3. SPI Timing, Detailed Drawing of Timing Parameter t1 to t4 /SEL SCLK t3 t4 Bit 6 t2 Bit 7 Bit 6 Bit 5 Bit 5 MOSI t1 Bit 7 MISO 17 8111A–AVR–05/08 The SPI is based on a byte-oriented protocol and is always a bidirectional communication between master and slave. The SPI master starts the transfer by asserting /SEL = L. Then the master generates eight SPI clock cycles to transfer one byte to the radio transceiver (via MOSI). At the same time, the slave transmits one byte to the master (via MISO). When the master wants to receive one byte of data from the slave it must also transmit one byte to the slave. All bytes are transferred with MSB first. An SPI transaction is finished by releasing /SEL = H. An SPI register access consists of two bytes, a Frame Buffer or SRAM access of at least two or more bytes as described in Section 6.2 “SPI Protocol” on page 19. /SEL = L enables the MISO output driver of the AT86RF231. The MSB of MISO is valid after t1 (see Section 12.4 “Digital Interface Timing Characteristics” on page 157 parameter 12.4.3) and is updated at each falling edge of SCLK. If the driver is disabled, there is no internal pull-up resistor connected to it. Driving the appropriate signal level must be ensured by the master device or an external pull-up resistor. Note, when both /SEL and /RST are active, the MISO output driver is also enabled. Referring to Figure 6-2 on page 17 and Figure 6-3 on page 17 MOSI is sampled at the rising edge of the SCLK signal and the output is set at the falling edge of SCLK. The signal must be stable before and after the rising edge of SCLK as specified by t3 and t4, refer to Section 12.4 “Digital Interface Timing Characteristics” on page 157 parameters 12.4.5 and 12.4.6. This SPI operational mode is commonly known as "SPI mode 0". 18 AT86RF231 8111A–AVR–05/08 AT86RF231 6.2 SPI Protocol Each SPI sequence starts with transferring a command byte from the SPI master via MOSI (see Table 6-2 on page 19) with MSB first. This command byte defines the SPI access mode and additional mode-dependent information. Table 6-2. Bit 7 1 1 0 0 0 0 SPI Command Byte definition Bit 6 0 1 0 1 0 1 1 1 0 0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access Mode Register access Register address [5:0] Reserved Frame Buffer access Reserved Reserved SRAM access Reserved Write access Write access Read access Write access Read access Access Type Read access Register address [5:0] Each SPI transfer returns bytes back to the SPI master on MISO. The content of the first byte (see value "PHY_STATUS" in Figure 6-4 on page 19 to Figure 6-14 on page 23) is set to zero after reset. To transfer status information of the radio transceiver to the microcontroller, the content of the first byte can be configured with register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). For details, refer to Section 6.3.1 “Register Description - SPI Control” on page 24. In Figure 6-4 on page 19 to Figure 6-14 on page 23 and the following chapters logic values stated with XX on MOSI are ignored by the radio transceiver, but need to have a valid logic level. Return values on MISO stated as XX shall be ignored by the microcontroller. The different access modes are described within the following sections. 6.2.1 Register Access Mode A register access mode is a two-byte read/write operation initiated by /SEL = L. The first transferred byte on MOSI is the command byte including an identifier bit (bit7 = 1), a read/write select bit (bit 6), and a 6-bit register address. On read access, the content of the selected register address is returned in the second byte on MISO (see Figure 6-4 on page 19). Figure 6-4. Packet Structure - Register Read Access byte 1 (command byte) byte 2 (data byte) MOSI MISO Note: 1 0 ADDRESS[5:0] PHY_STATUS(1) XX READ DATA[7:0] 1. Each SPI access can be configured to return radio controller status information (PHY_STATUS) on MISO, for details refer to Section 6.3 “Radio Transceiver Status information” on page 24. On write access, the second byte transferred on MOSI contains the write data to the selected address (see Figure 6-6 on page 20). 19 8111A–AVR–05/08 Figure 6-5. Packet Structure - Register Write Access byte 1 (command byte) byte 2 (data byte) MOSI MISO 1 1 ADDRESS[5:0] PHY_STATUS WRITE DATA[7:0] XX Each register access must be terminated by setting /SEL = H. Figure 6-6 on page 20 illustrates a typical SPI sequence for a register access sequence for write and read respectively. Figure 6-6. Example SPI Sequence - Register Access Mode Register Read Access Register Write Access /SEL SCLK MOSI MISO WRITE COMMAND PHY_STATUS WRITE DATA XX READ COMMAND PHY_STATUS XX READ DATA 6.2.2 Frame Buffer Access Mode The 128 byte Frame Buffer can hold the PHY service data unit (PSDU) data of one IEEE 802.15.4 compliant RX or one TX frame of maximum length at a time. A detailed description of the Frame Buffer can be found in Section 9.3 “Frame Buffer” on page 107. An introduction to the IEEE 802.15.4 frame format can be found in Section 8.1 “Introduction - IEEE 802.15.4 2006 Frame Format” on page 79. Frame Buffer read and write accesses are used to read or write frame data (PSDU and additional information) from or to the Frame Buffer. Each access starts with /SEL = L followed by a command byte on MOSI. If this byte indicates a frame read or write access, the next byte PHR[7:0] indicates the frame length followed by the PSDU data, see Figure 6-7 on page 20 and Figure 6-8 on page 21. On Frame Buffer read access, PHY header (PHR) and PSDU are transferred via MISO starting with the second byte. After the PSDU data, one more byte is transferred containing the link quality indication (LQI) value of the received frame, for details refer to Section 8.6 “Link Quality Indication (LQI)” on page 99. Figure 6-7 on page 20 illustrates the packet structure of a Frame Buffer read access. Figure 6-7. Packet Structure - Frame Read Access byte 2 (data byte) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) byte 1 (command byte) MOSI MISO 0 0 1 reserved[5:0] PHY_STATUS XX PHR[7:0] XX PSDU[7:0] XX PSDU[7:0] XX LQI[7:0] 20 AT86RF231 8111A–AVR–05/08 AT86RF231 Note, the Frame Buffer read access can be terminated at any time without any consequences by setting /SEL = H, e.g. after reading the PHR byte only. On Frame Buffer write access the second byte transferred on MOSI contains the frame length (PHR field) followed by the payload data (PSDU) as shown by Figure 6-8 on page 21. Figure 6-8. Packet Structure - Frame Write Access byte 2 (data byte) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) byte 1 (command byte) MOSI MISO 0 1 1 reserved[5:0] PHY_STATUS PHR[7:0] XX PSDU[7:0] XX PSDU[7:0] XX PSDU[7:0] XX The number of bytes n for one frame access is calculated as follows: • Read Access: n = 3 + frame_length [PHY_STATUS, PHR byte, PSDU data, and LQI byte] • Write Access: n = 2 + frame_length [command byte, PHR byte, and PSDU data] The maximum value of frame_length is 127 bytes. That means that n ≤ 130 for Frame Buffer read and n ≤ 129 for Frame Buffer write accesses. Each read or write of a data byte increments automatically the address counter of the Frame Buffer until the access is terminated by setting /SEL = H. A Frame Buffer read access may be terminated (/SEL = H) at any time without affecting the Frame Buffer content. Another Frame Buffer read operation starts again at the PHR field. The content of the Frame Buffer is only overwritten by a new received frame or a Frame Buffer write access. Figure 6-9 on page 21 and Figure 6-10 on page 22 illustrate an example SPI sequence of a Frame Buffer access to read and write a frame with 4-byte PSDU respectively. Figure 6-9. /SEL SCLK MOSI MISO COMMAND XX XX XX XX XX XX Example SPI Sequence - Frame Buffer Read of a Frame with 4-byte PSDU PHY_STATUS PHR PSDU 1 PSDU 2 PSDU 3 PSDU 4 LQI 21 8111A–AVR–05/08 Figure 6-10. Example SPI Sequence - Frame Buffer Write of a Frame with 4 byte PSDU /SEL SCLK MOSI MISO COMMAND PHR PSDU 1 PSDU 2 PSDU 3 PSDU 4 PHY_STATUS XX XX XX XX XX Access violations during a Frame Buffer read or write access are indicated by interrupt IRQ_6 (TRX_UR). For further details, refer to Section 9.3 “Frame Buffer” on page 107. Notes • The Frame Buffer is shared between RX and TX; therefore, the frame data are overwritten by new incoming frames. If the TX frame data are to be retransmitted, it must be ensured that no frame was received in the meanwhile. • To avoid overwriting during receive Dynamic Frame Buffer Protection can be enabled, refer to Section 11.8 “Dynamic Frame Buffer Protection” on page 154. • It is not possible to retransmit received frames without a Frame Buffer read and write access cycle. • For exceptions, e.g. receiving acknowledgement frames in Extended Operating Mode (TX_ARET) refer to Section 7.2.4 “TX_ARET_ON - Transmit with Automatic Retry and CSMA-CA Retry” on page 64. 6.2.3 SRAM Access Mode The SRAM access mode allows accessing dedicated bytes within the Frame Buffer. This may reduce the SPI traffic. The SRAM access mode is useful, for instance, if a transmit frame is already stored in the Frame Buffer and dedicated bytes (e.g. sequence number, address field) need to be replaced before retransmitting the frame. Furthermore, it can be used to access only the LQI value after frame reception. A detailed description of the user accessible frame content can be found in Section 9.3 “Frame Buffer” on page 107. Each SRAM access starts with /SEL = L. The first transferred byte on MOSI shall be the command byte and must indicate an SRAM access mode according to the definition in Table 6-2 on page 19. The following byte indicates the start address of the write or read access. The address space is 0x00 to 0x7F for radio transceiver receive or transmit operations. On SRAM read access, one or more bytes of read data are transferred on MISO starting with the third byte of the access sequence (see Figure 6-11 on page 22). Figure 6-11. Packet Structure - SRAM Read Access byte 1 (command byte) byte 2 (address) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI MISO 0 0 0 reserved[5:0] PHY_STATUS ADDRESS[7:0] XX XX DATA[7:0] XX DATA[7:0] XX DATA[7:0] 22 AT86RF231 8111A–AVR–05/08 AT86RF231 On SRAM write access, one or more bytes of write data are transferred on MOSI starting with the third byte of the access sequence (see Figure 6-12 on page 23). On SRAM read or write accesses do not attempt to read or write bytes beyond the SRAM buffer size. Figure 6-12. Packet Structure - SRAM Write Access byte 1 (command byte) byte 2 (address) byte 3 (data byte) byte n-1 (data byte) byte n (data byte) MOSI MISO 0 1 0 reserved[5:0] PHY_STATUS ADDRESS[7:0] XX DATA[7:0] XX DATA[7:0] XX DATA[7:0] XX As long as /SEL = L, every subsequent byte read or byte write increments the address counter of the Frame Buffer until the SRAM access is terminated by /SEL = H. Figure 6-13 on page 23 and Figure 6-14 on page 23 illustrate an example SPI sequence of a SRAM access to read and write a data package of 5-byte length respectively. Figure 6-13. Example SPI Sequence - SRAM Read Access of a 5 byte Data Package /SEL SCLK MOSI MISO COMMAND ADDRESS XX XX XX XX XX PHY_STATUS XX DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 Figure 6-14. Example SPI Sequence - SRAM Write Access of a 5 byte Data Package /SEL SCLK MOSI MISO COMMAND ADDRESS DATA 1 DATA 2 DATA 3 DATA 4 DATA 5 PHY_STATUS XX XX XX XX XX XX Notes • The SRAM access mode is not intended to be used as an alternative to the Frame Buffer access modes (see Section 6.2.2 “Frame Buffer Access Mode” on page 20). • If the SRAM access mode is used to read PSDU data, the Frame Buffer contains all PSDU data except the frame length byte (PHR). The frame length information can be accessed only using Frame Buffer access. • Frame Buffer access violations are not indicated by a TRX_UR interrupt when using the SRAM access mode, for further details refer to Section 9.3.3 “Interrupt Handling” on page 109. 23 8111A–AVR–05/08 6.3 Radio Transceiver Status information Each SPI access can be configured to return status information of the radio transceiver (PHY_STATUS) to the microcontroller using the first byte of the data transferred via MISO. The content of the radio transceiver status information can be configured using register bits SPI_CMD_MODE (register 0x04, TRX_CTRL_1). After reset, the content on the first byte send on MISO to the microcontroller is set to 0x00. 6.3.1 Register Description - SPI Control Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit +0x04 Read/Write Initial Value 7 PA_EXT_EN R/W 0 6 IRQ_2_EXT_EN R/W 0 5 TX_AUTO_CRC_ON R/W 1 4 RX_BL_CTRL R/W 0 3 SPI_CMD_MODE R/W 0 2 1 IRQ_MASK_MODE R/W 0 0 IRQ_POLARITY R/W 0 TRX_CTRL_1 R/W 0 • Bit 7 - PA_EXT_EN Refer to Section 11.5 “RX/TX Indicator” on page 147. • Bit 6 - IRQ_2_EXT_EN Refer to Section 11.6 “RX Frame Time Stamping” on page 150. • Bit 5 - TX_AUTO_CRC_ON Refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85. • Bit 4 - RX_BL_CTRL Refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152. • Bit [3:2] - SPI_CMD_MODE Each SPI transfer returns bytes back to the SPI master. The content of the first byte can be configured using register bits SPI_CMD_MODE. The transfer of the following status information can be configured as follows: Table 6-3. Register Bit SPI_CMD_MODE Radio Transceiver Status Information - PHY_STATUS Value 0 1 2 3 Description default (empty, all bits 0x00) monitor TRX_STATUS register; see Section 7.1.5 monitor PHY_RSSI register; see Section 8.3 monitor IRQ_STATUS register; see Section 6.6 • Bit 1 - IRQ_MASK_MODE Refer to Section 6.6 “Interrupt Logic” on page 29. • Bit 0 - IRQ_POLARITY Refer to Section 6.6 “Interrupt Logic” on page 29. 24 AT86RF231 8111A–AVR–05/08 AT86RF231 6.4 Radio Transceiver Identification The AT86RF231 can be identified by four registers. One register contains a unique part number and one register the corresponding version number. Two additional registers contain the JEDEC manufacture ID. 6.4.1 Register Description - AT86RF231 Identification Register 0x1C (PART_NUM): Bit +0x1C Read/Write Reset Value R 0 R 0 R 0 7 6 5 4 3 2 1 0 PART_NUM R 0 R 1 R 1 PART_NUM[7:0] R 0 R 0 • Bit [7:0] - PART_NUM This register contains the radio transceiver part number. Table 6-4. Register Bit PART_NUM Radio Transceiver Part Number Value 3 Description AT86RF231 part number Register 0x1D (VERSION_NUM): Bit +0x1D Read/Write Reset Value R 0 R 0 R 0 7 6 5 4 3 2 1 0 VERSION_NUM R 0 R 1 R 0 VERSION_NUM[7:0] R 0 R 0 • Bit [7:0] - VERSION_NUM This register contains the radio transceiver version number. Table 6-5. Register Bit VERSION_NUM Radio Transceiver Version Number Value 2 Description Revision A Register 0x1E (MAN_ID_0): Bit +0x1E Read/Write Reset Value R 0 R 0 R 0 7 6 5 4 3 2 1 0 MAN_ID_O R 1 R 1 R 1 MAN_ID_0[7:0] R 1 R 1 • Bit [7:0] - MAN_ID_0 Bits [7:0] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_0. Bits [15:8] are stored in register 0x1F (MAN_ID_1). The highest 16 bits of the ID are not stored in registers. 25 8111A–AVR–05/08 Table 6-6. Register Bit MAN_ID_0 JEDEC Manufacturer ID - Bits [7:0] Value 0x1F Description Atmel JEDEC manufacturer ID, Bits [7:0] of 32 bit manufacturer ID: 00 00 00 1F Register 0x1F (MAN_ID_1): Bit +0x1F Read/Write Reset Value R 0 R 0 R 0 7 6 5 4 3 2 1 0 MAN_ID_1 R 0 R 0 R 0 MAN_ID_1[7:0] R 0 R 0 • Bit [7:0] - MAN_ID_1 Bits [15:8] of the 32-bit JEDEC manufacturer ID are stored in register bits MAN_ID_1. Bits [7:0] are stored in register 0x1E (MAN_ID_0). The higher 16 bits of the ID are not stored in registers. Table 6-7. Register Bit MAN_ID_1 JEDEC Manufacturer ID - Bits [15:8] Value 0x00 Description Atmel JEDEC manufacturer ID, Bits [15:8] of 32 bit manufacturer ID: 00 00 00 1F 26 AT86RF231 8111A–AVR–05/08 AT86RF231 6.5 Sleep/Wake-up and Transmit Signal (SLP_TR) Pin 11 (SLP_TR) is a multi-functional pin. Its function relates to the current state of the AT86RF231 and is summarized in Table 6-8 on page 27. The radio transceiver states are explained in detail Section 7. “Operating Modes” on page 33. Table 6-8. SLP_TR Multi-functional Pin Function TX start TX start Sleep Wakeup Disable CLKM Enable CLKM Disable CLKM Enable CLKM Transition Description Starts frame transmission Starts TX_ARET transaction Takes the radio transceiver into SLEEP state, CLKM disabled Takes the radio transceiver back into TRX_OFF state, level sensitive Takes the radio transceiver into RX_ON_NOCLK state and disables CLKM Takes the radio transceiver into RX_ON state and enables CLKM Takes the radio transceiver into RX_AACK_ON_NOCLK state and disables CLKM Takes the radio transceiver into RX_AACK_ON state and enables CLKM Transceiver Status PLL_ON TX_ARET_ON TRX_OFF SLEEP RX_ON RX_ON_NOCLK RX_AACK_ON RX_AACK_ON_NOCLK L⇒H L⇒H L⇒H H⇒L L⇒H H⇒L L⇒H H⇒L In states PLL_ON and TX_ARET_ON, pin SLP_TR is used as trigger input to initiate a TX transaction. Here pin SLP_TR is sensitive on rising edge only. After initiating a state change by a rising edge at pin SLP_TR in radio transceiver states TRX_OFF, RX_ON or RX_AACK_ON, the radio transceiver remains in the new state as long as the pin is logical high and returns to the preceding state with the falling edge. SLEEP state The SLEEP state is used when radio transceiver functionality is not required, and thus the AT86RF231 can be powered down to reduce the overall power consumption. A power-down scenario is shown in Figure 6-15 on page 28. When the radio transceiver is in TRX_OFF state the microcontroller forces the AT86RF231 to SLEEP by setting SLP_TR = H. If pin 17 (CLKM) provides a clock to the microcontroller this clock is switched off after 35 clock cycles. This enables a microcontroller in a synchronous system to complete its power-down routine and prevent deadlock situations. The AT86RF231 awakes when the microcontroller releases pin SLP_TR. This concept provides the lowest possible power consumption. The CLKM clock frequency settings for 250 kHz and 62.5 kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering SLEEP state. 27 8111A–AVR–05/08 Figure 6-15. Sleep and Wake-up Initiated by Asynchronous Microcontroller Timer SLP_TR CLKM 35 CLKM clock cycles CLKM off tTR2 async timer elapses (microcontroller) Note: Timing figure tTR2 refer to section Table 7-1 on page 42. RX_ON and RX_AACK_ON states For synchronous systems, where CLKM is used as a microcontroller clock source and the SPI master clock (SCLK) is directly derived from CLKM, the AT86RF231 supports an additional power-down mode for receive operating states (RX_ON and RX_AACK_ON). If an incoming frame is expected and no other applications are running on the microcontroller, it can be powered down without missing incoming frames. This can be achieved by a rising edge on pin SLP_TR that turns off the CLKM. Then the radio transceiver state changes from RX_ON or RX_AACK_ON (Extended Operating Mode) to RX_ON_NOCLK or RX_AACK_ON_NOCLK respectively. In case that a frame is received (e.g. indicated by an IRQ_2 (RX_START) interrupt) the clock output CLKM is automatically switched on again. This scenario is shown in Figure 6-16 on page 28. In RX_ON state, the clock at pin 17 (CLKM) is switched off after 35 clock cycles when setting the pin SLP_TR = H. The CLKM clock frequency settings for 250 kHz and 62.5 kHz are not intended to directly clock the microcontroller. When using these clock rates, CLKM is turned off immediately when entering RX_ON_NOCLK and RX_AACK_ON_NOCLK respectively. In states RX_(AACK)_ON_NOCLK and RX_(AACK)_ON, the radio transceiver current consumptions are equivalent. However, the RX_(AACK)_ON_NOCLK current consumption is reduced by the current required for driving pin 17 (CLKM). Figure 6-16. Wake-Up Initiated by Radio Transceiver Interrupt radio transceiver IRQ issued IRQ typ. 5 µs SLP_TR CLKM 35 CLKM clock cycles CLKM off 28 AT86RF231 8111A–AVR–05/08 AT86RF231 6.6 6.6.1 Interrupt Logic Overview The AT86RF231 differentiates between nine interrupt events (eight physical interrupt registers, one shared by two functions). Each interrupt is enabled by setting the corresponding bit in the interrupt mask register 0x0E (IRQ_MASK). Internally, each pending interrupt is stored in a separate bit of the interrupt status register. All interrupt events are OR-combined to a single external interrupt signal (IRQ, pin 24). If an interrupt is issued (pin IRQ = H), the microcontroller shall read the interrupt status register 0x0F (IRQ_STATUS) to determine the source of the interrupt. A read access to this register clears the interrupt status register and thus the IRQ pin, too. Interrupts are not cleared automatically when the event that caused them vanishes. Exceptions are IRQ_0 (PLL_LOCK) and IRQ_1 (PLL_UNLOCK) because the occurrence of one clears the other. The supported interrupts for the Basic Operating Mode are summarized in Table 6-9 on page 29. Table 6-9. IRQ Name Interrupt Description in Basic Operating Mode Description Indicates a supply voltage below the programmed threshold. Indicates a Frame Buffer access violation. Indicates address matching. Multi-functional interrupt: 1. AWAKE_END: • Indicates radio transceiver reached TRX_OFF state after P_ON, RESET, or SLEEP states. 2. CCA_ED_READY: • Indicates the end of a CCA or ED measurement. Section Section 9.5.4 Section 9.3.3 Section 7.2.3.5 Section 7.1.2.3 IRQ_7 (BAT_LOW) IRQ_6 (TRX_UR) IRQ_5 (AMI) IRQ_4 (CCA_ED_READY) Section 8.4.4 Section 8.5.4 Section 7.1.3 Section 7.1.3 Section 7.1.3 Section 9.7.5 Section 9.7.5 IRQ_3 (TRX_END) IRQ_2 (RX_START) IRQ_1 (PLL_UNLOCK) IRQ_0 (PLL_LOCK) RX: Indicates the completion of a frame reception. TX: Indicates the completion of a frame transmission. Indicates the start of a PSDU reception. The TRX_STATE changes to BUSY_RX, the PHR is valid to read from Frame Buffer. Indicates PLL unlock. If the radio transceiver is BUSY_TX / BUSY_TX_ARET state, the PA is turned off immediately. Indicates PLL lock. The interrupt IRQ_4 has two meanings, depending on the current radio transceiver state, refer to register 0x01 (TRX_STATUS). After P_ON, SLEEP, or RESET, the radio transceiver issues an interrupt IRQ_4 (AWAKE_END) when it enters state TRX_OFF. The second meaning is only valid for receive states. If the microcontroller initiates an energydetect (ED) or clear-channel-assessment (CCA) measurement, the completion of the measurement is indicated by interrupt IRQ_4 (CCA_ED_READY), refer to Section 8.4.4 “Interrupt Handling” on page 92 and Section 8.5.4 “Interrupt Handling” on page 95 for details. After P_ON or RESET all interrupts are disabled. During radio transceiver initialization it is recommended to enable IRQ_4 (AWAKE_END) to be notified once the TRX_OFF state is entered. 29 8111A–AVR–05/08 Note that AWAKE_END interrupt can usually not be seen when the transceiver enters TRX_OFF state after RESET, because register 0x0E (IRQ_MASK) is reset to mask all interrupts. In this case, state TRX_OFF is normally entered before the microcontroller could modify the register. The interrupt handling in Extended Operating Mode is described in Section 7.2.5 “Interrupt Handling” on page 67. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However, in that case no timing information for this interrupt is provided. The IRQ pin polarity can be configured with register bit IRQ_POLARITY (register 0x04, TRX_CTRL_1). The default behavior is active high, which means that pin IRQ = H issues an interrupt request. If "Frame Buffer Empty Indicator" is enabled during Frame Buffer read access the IRQ pin has an alternative functionality, refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152 for details. 6.6.2 Register Description Register 0x0E (IRQ_MASK): he IRQ_MASK register is used to enable or disable individual interrupts. An interrupt is enabled if the corresponding bit is set to 1. All interrupts are disabled after power up sequence (P_ON state) or reset (RESET state). Bit +0x0E Read/Write Reset Value 7 MASK_BAT_LOW R/W 0 6 MASK_TRX_UR R/W 0 5 MASK_AMI R/W 0 4 MASK_CCA_ED_READY R/W 0 3 MASK_TRX_END R/W 0 2 1 0 MASK_RX_START R/W 0 MASK_PLL_UNLOCK R/W 0 MASK_PLL_LOCK R/W 0 IRQ_MASK If an interrupt is enabled it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history. Register 0x0F (IRQ_STATUS): The IRQ_STATUS register contains the status of the pending interrupt requests. Bit +0x0F Read/Write Initial Value 7 BAT_LOW R 0 6 TRX_UR R 0 5 AMI R 0 4 CCA_ED_READY R 0 3 TRX_END R 0 2 RX_START R 0 1 PLL_UNLOCK R 0 0 PLL_LOCK R 0 IRQ_STATUS By reading the register after an interrupt is signaled at pin 24 (IRQ) the source of the issued interrupt can be identified. A read access to this register resets all interrupt bits, and so clears the IRQ_STATUS register. If register bit IRQ_MASK_MODE (register 0x04, TRX_CTRL_1) is set, an interrupt event can be read from IRQ_STATUS register even if the interrupt itself is masked. However in that case no timing information for this interrupt is provided. If register bit IRQ_MASK_MODE is set, it is recommended to read the interrupt status register 0x0F (IRQ_STATUS) first to clear the history. 30 AT86RF231 8111A–AVR–05/08 AT86RF231 Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit +0x04 Read/Write Reset Value 7 PA_EXT_EN R/W 0 6 IRQ_2_EXT_EN R/W 0 5 TX_AUTO_CRC_ON R/W 1 4 RX_BL_CTRL R/W 0 3 SPI_CMD_MODE R/W 0 R/W 0 2 1 IRQ_MASK_MODE R/W 0 0 IRQ_POLARITY R/W 0 TRX_CTRL_1 • Bit 7 - PA_EXT_EN Refer to Section 11.5 “RX/TX Indicator” on page 147. • Bit 6 - IRQ_2_EXT_EN The timing of a received frame can be determined by a separate pin. If register bit IRQ_2_EXT_EN is set to 1, the reception of a PHR is directly issued on pin 10 (DIG2), similar to interrupt IRQ_2 (RX_START). Note that this pin is also active even if the corresponding interrupt event IRQ_2 (RX_START) mask bit in register 0x0E (IRQ_MASK) is set to 0. The pin remains at high level until the end of the frame receive procedure. For further details refer to Section 11.6 “RX Frame Time Stamping” on page 150. • Bit 5 - TX_AUTO_CRC_ON Refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85. • Bit 4 - RX_BL_CTRL Refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152. • Bit [3:2] - SPI_CMD_MODE Refer to Section 6.3 “Radio Transceiver Status information” on page 24. • Bit 1 - IRQ_MASK_MODE The AT86RF231 supports polling of interrupt events. Interrupt polling can be enabled by register bit IRQ_MASK_MODE. Even if an interrupt request is masked by the corresponding bit in register 0x0E (IRQ_MASK), the event is indicated in register 0x0F (IRQ_STATUS). Table 6-10. Register Bit IRQ_MASK_MODE Interrupt Polling Configuration Value 0 1 Description Interrupt polling disabled Interrupt polling enabled 31 8111A–AVR–05/08 • Bit 0 - IRQ_POLARITY The default polarity of the IRQ pin is active high. The polarity can be configured to active low via register bit IRQ_POLARITY, see Table 6-11 on page 32. Table 6-11. Register Bit IRQ_POLARITY Configuration of Pin 24 (IRQ) Value 0 1 Description pin IRQ high active pin IRQ low active This setting does not affect the polarity of the Frame Buffer Empty Indicator, refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152. The Frame Buffer Empty Indicator is always active high. 32 AT86RF231 8111A–AVR–05/08 AT86RF231 7. Operating Modes 7.1 Basic Operating Mode This section summarizes all states to provide the basic functionality of the AT86RF231, such as receiving and transmitting frames, the power up sequence and sleep. The Basic Operating Mode is designed for IEEE 802.15.4 and ISM applications; the corresponding radio transceiver states are shown in Figure 7.1 on page 33. Figure 7-1. Basic Operating Mode State Diagram (for timing refer to Table 7-1 on page 42) P_ON (Power-on after VDD) XOSC=ON Pull=ON SLEEP (Sleep State) XOSC=OFF Pull=OFF = L SL P_ TR 3 = H SL P_ T R (from all states) /RST = L F OF X_ TR 1 2 FORCE_TRX_OFF 12 TRX_OFF (Clock State) XOSC=ON Pull=OFF 13 /RST = H (all states except SLEEP) (all states except P_ON) RESET O L_ PL _O N 7 _O FF TR X 5 X TR FF _O RX N 6 SHR Detected Frame End 4 Frame End 8 BUSY_RX (Receive State) RX_ON (Rx Listen State) RX_ON PLL_ON 9 11 PLL_ON (PLL State) BUSY_TX (Transmit State) 10 SLP_TR = H or TX_START SHR Detected TR = H SL P_ FORCE_PLL_ON 14 Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event Basic Operating Mode States X State transition number, see Table 7-1 = L RX_ON_NOCLK (Rx Listen State) CLKM=OFF 7.1.1 State Control The radio transceiver states are controlled either by writing commands to register bits TRX_CMD (register 0x02, TRX_STATE), or directly by two signal pins: pin 11 (SLP_TR) and SL P_ (all states except SLEEP, P_ON, TRX_OFF, RX_ON_NOCLK) TR 33 8111A–AVR–05/08 pin 8 (/RST). A successful state change can be verified by reading the radio transceiver status from register 0x01 (TRX_STATUS). If TRX_STATUS = 0x1F (STATE_TRANSITION_IN_PROGRESS) the AT86RF231 is on a state transition. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. Pin SLP_TR is a multifunctional pin, refer to Section 6.5 “Sleep/Wake-up and Transmit Signal (SLP_TR)” on page 27. Dependent on the radio transceiver state, a rising edge of pin SLP_TR causes the following state transitions: • TRX_OFF • RX_ON • PLL_ON • SLEEP • RX_ON_NOCLK ⇒ ⇒ ⇒ SLEEP RX_ON_NOCLK BUSY_TX (level sensitive) (level sensitive) Whereas the falling edge of pin SLP_TR causes the following state transitions: ⇒ ⇒ TRX_OFF RX_ON (level sensitive) (level sensitive) Pin 8 (/RST) causes a reset of all registers (register bits CLKM_CTRL are shadowed, for details refer to Section 9.6.4 “Master Clock Signal Output (CLKM)” on page 117) and forces the radio transceiver into TRX_OFF state. However, if the device was in P_ON state it remains in the P_ON state. For all states except SLEEP, the state change commands FORCE_TRX_OFF or TRX_OFF lead to a transition into TRX_OFF state. If the radio transceiver is in active receive or transmit states (BUSY_*), the command FORCE_TRX_OFF interrupts these active processes, and forces an immediate transition to TRX_OFF. In contrast a TRX_OFF command is stored until an active state (receiving or transmitting) has been finished. After that the transition to TRX_OFF is performed. For a fast transition from receive or active transmit states to PLL_ON state the command FORCE_PLL_ON is provided. In contrast to FORCE_TRX_OFF this command does not disable the PLL and the analog voltage regulator AVREG. It is not available in states SLEEP, P_ON, RESET, TRX_OFF, and all *_NOCLK states. The completion of each requested state change shall always be confirmed by reading the register bits TRX_STATUS (register 0x01, TRX_STATUS). 7.1.2 7.1.2.1 Basic Operating Mode Description P_ON - Power-On after VDD When the external supply voltage (VDD) is firstly applied to the AT86RF231, the radio transceiver goes into the P_ON state performing an on-chip reset. The crystal oscillator is activated and the default 1 MHz master clock is provided at pin 17 (CLKM) after the crystal oscillator has stabilized. CLKM can be used as a clock source to the microcontroller. The SPI interface and digital voltage regulator are enabled. The on-chip power-on-reset sets all registers to their default values. A dedicated reset signal from the microcontroller at pin 8 (/RST) is not necessary, but recommended for hardware / software synchronization reasons. 34 AT86RF231 8111A–AVR–05/08 AT86RF231 All digital inputs have pull-up or pull-down resistors during P_ON state, refer to Section 1.3.2 “Pull-Up and Pull-Down Configuration” on page 7. This is necessary to support microcontrollers where GPIO signals are floating after power on or reset. The input pull-up and pull-down resistors are disabled when the radio transceiver leaves the P_ON state. Output pins DIG1/DIG2 are pulled-down to digital ground, whereas pins DIG3/DIG4 are pulled-down to analog ground, unless their configuration is changed. Prior to leaving P_ON, the microcontroller must set the pins to the default operating values: SLP_TR = L, /RST = H and /SEL = H. All interrupts are disabled by default. Thus, interrupts for state transition control are to be enabled first, e.g. enable IRQ_4 (AWAKE_END) to indicate a state transition to TRX_OFF state or interrupt IRQ_0 (PLL_LOCK) to signal a locked PLL in PLL_ON state. In P_ON state a first access to the radio transceiver registers is possible after a default 1 MHz master clock is provided at pin 17 (CLKM), refer to Table 7-1 on page 42. Once the supply voltage has stabilized and the crystal oscillator has settled (see Section 12.5 “General RF Specifications” on page 158, parameter 12.5.7), a valid SPI write access to register bits TRX_CMD (register 0x02, TRX_STATE) with the command TRX_OFF or FORCE_TRX_OFF initiate a state change from P_ON towards TRX_OFF state, which is then indicated by an AWAKE_END interrupt if enabled. 7.1.2.2 SLEEP - Sleep State In SLEEP state, the entire radio transceiver is disabled. No circuitry is operating. The radio transceiver current consumption is reduced to leakage current only. This state can only be entered from state TRX_OFF, by setting the pin SLP_TR = H. If CLKM is enabled, the SLEEP state is entered 35 CLKM cycles after the rising edge at pin 11 (SLP_TR). At that time CLKM is turned off. If the CLKM output is already turned off (bits CLKM_CTRL = 0 in register 0x03), the SLEEP state is entered immediately. At clock rates 250 kHz and 62.5 kHz, the main clock at pin 17 (CLKM) is turned off immediately. Setting SLP_TR = L returns the radio transceiver to the TRX_OFF state. During SLEEP the register contents remains valid while the content of the Frame Buffer and the security engine (AES) are cleared. /RST = L in SLEEP state returns the radio transceiver to TRX_OFF state and thereby sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4 “Master Clock Signal Output (CLKM)” on page 117. 7.1.2.3 TRX_OFF - Clock State In TRX_OFF the crystal oscillator is running and the master clock is available at pin 17 (CLKM) after the crystal oscillator has stabilized. The SPI interface and digital voltage regulator are enabled, thus the radio transceiver registers, the Frame Buffer and security engine (AES) are accessible (see Section 9.3 “Frame Buffer” on page 107 and Section 11.1 “Security Module (AES)” on page 128). In contrast to P_ON state pull-up and pull-down resistors are disabled. Pin 11 (SLP_TR) and pin 8 (/RST) are available for state control. Note that the analog front-end is disabled during TRX_OFF. 35 8111A–AVR–05/08 Entering the TRX_OFF state from P_ON, SLEEP, or RESET state is indicated by interrupt IRQ_4 (AWAKE_END). 7.1.2.4 PLL_ON - PLL State Entering the PLL_ON state from TRX_OFF state enables the analog voltage regulator (AVREG) first. After the voltage regulator has been settled, the PLL frequency synthesizer is enabled. When the PLL has been settled at the receive frequency to a channel defined by register bits CHANNEL (register 0x08, PHY_CC_CCA), a successful PLL lock is indicated by issuing an interrupt IRQ_0 (PLL_LOCK). If an RX_ON command is issued in PLL_ON state, the receiver is immediately enabled. If the PLL has not been settled before the state change nevertheless takes place. Even if the register bits TRX_STATUS (register 0x01, TRX_STATUS) indicates RX_ON, actual frame reception can only start once the PLL has locked. The PLL_ON state corresponds to the TX_ON state in IEEE 802.15.4. 7.1.2.5 RX_ON and BUSY_RX - RX Listen and Receive State In RX_ON state the receiver blocks and the PLL frequency synthesizer are enabled. The AT86RF231 receive mode is internally separated into RX_ON state and BUSY_RX state. There is no difference between these states with respect to the analog radio transceiver circuitry, which are always turned on. In both states the receiver and the PLL frequency synthesizer are enabled. During RX_ON state the receiver listens for incoming frames. After detecting a valid synchronization header (SHR), the AT86RF231 automatically enters the BUSY_RX state. The reception of a valid PHY header (PHR) generates an IRQ_2 (RX_START) and receives and demodulates the PSDU data. During PSDU reception the frame data are stored continuously in the Frame Buffer until the last byte was received. The completion of the frame reception is indicated by an interrupt IRQ_3 (TRX_END) and the radio transceiver reenters the state RX_ON. At the same time the register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is updated with the result of the FCS check (see Section 8.2 “Frame Check Sequence (FCS)” on page 85). Received frames are passed to the frame filtering unit, refer to Section 7.2.3.5 “Frame Filtering” on page 61. If the content of the MAC addressing fields (refer to IEEE 802.15.4, Section 7.2.1) of a frame matches to the expected addresses, which is further dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to Section 6.6 “Interrupt Logic” on page 29. The expected address values are to be stored in registers 0x20 - 0x2B (Short address, PAN-ID and IEEE address). Frame filtering is available in Basic and Extended Operating Mode, refer to Section 7.2.3.5 “Frame Filtering” on page 61. Leaving state RX_ON is only possible by writing a state change command to register bits TRX_CMD in register 0x02 (TRX_STATE). 7.1.2.6 RX_ON_NOCLK - RX Listen State without CLKM If the radio transceiver is listening for an incoming frame and the microcontroller is not running an application, the microcontroller may be powered down to decrease the total system power consumption. This specific power-down scenario for systems running in clock synchronous mode (see Section 6. “Microcontroller Interface” on page 16), is supported by the AT86RF231 using the state RX_ON_NOCLK. 36 AT86RF231 8111A–AVR–05/08 AT86RF231 This state can only be entered by setting pin 11 (SLP_TR) = H while the radio transceiver is in the RX_ON state, refer to Section 7.1.2.5 “RX_ON and BUSY_RX - RX Listen and Receive State” on page 36. Pin 17 (CLKM) is disabled 35 clock cycles after the rising edge at the SLP_TR pin, see Figure 6-16 on page 28. This allows the microcontroller to complete its powerdown sequence. Note that for CLKM clock rates 250 kHz and 62.5 kHz the master clock signal CLKM is switched off immediately after rising edge of SLP_TR. The reception of a frame shall be indicated to the microcontroller by an interrupt indicating the receive status. CLKM is turned on again, and the radio transceiver enters the BUSY_RX state (see Section 6.5 “Sleep/Wake-up and Transmit Signal (SLP_TR)” on page 27 and Figure 6-16 on page 28). Using this radio transceiver state it is essential to enable at least one interrupt indicating the reception status. Otherwise the reception of a frame does not activate CLKM and the microcontroller remains in its power-down mode. After the receive transaction has been completed, the radio transceiver enters the RX_ON state. The radio transceiver only reenters the RX_ON_NOCLK state, when the next rising edge of pin SLP_TR pin occurs. If the AT86RF231 is in the RX_ON_NOCLK state, and pin SLP_TR is reset to logic low, it enters the RX_ON state, and it starts to supply clock on the CLKM pin again. In states RX_ON_NOCLK and RX_ON, the radio transceiver current consumptions are equivalent. However, the RX_ON_NOCLK current consumption is reduced by the current required for driving pin 17 (CLKM). Note • A reset in state RX_ON_NOCLK requires further to reset pin SLP_TR to logic low, otherwise the radio transceiver enters directly the SLEEP state. 7.1.2.7 BUSY_TX - Transmit State A transmission can only be initiated in state PLL_ON. There are two ways to start a transmission: • Rising edge of pin 11 (SLP_TR) • TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE). Either of these causes the radio transceiver into the BUSY_TX state. During the transition to BUSY_TX state, the PLL frequency shifts to the transmit frequency. The actual transmission of the first data chip of the SHR starts after 16 µs to allow PLL settling and PA ramp-up, see Figure 7-6 on page 41. After transmission of the SHR, the Frame Buffer content is transmitted. In case the PHR indicates a frame length of zero, the transmission is aborted. After the frame transmission has completed, the AT86RF231 automatically turns off the power amplifier, generates an IRQ_3 (TRX_END) interrupt and returns into PLL_ON state. 7.1.2.8 RESET State The RESET state is used to set back the state machine and to reset all registers of the AT86RF231 to their default values, exception are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0). These register bits require a specific treatment, for details see Section 9.6.4 “Master Clock Signal Output (CLKM)” on page 117. 37 8111A–AVR–05/08 A reset forces the radio transceiver into TRX_OFF state. If the device is still in the P_ON state it remains in the P_ON state though. A reset is initiated with pin /RST = L and the state is left after setting /RST = H. The reset pulse should have a minimum length as specified in Section 12.4 “Digital Interface Timing Characteristics” on page 157 see parameter 12.4.13. During reset the microcontroller has to set the radio transceiver control pins SLP_TR and /SEL to their default values. An overview about the register reset values is provided in Table 14-1 on page 167. 7.1.3 Interrupt Handling All interrupts provided by the AT86RF231 (see Table 6-9 on page 29) are supported in Basic Operating Mode. For example, interrupts are provided to observe the status of radio transceiver RX and TX operations. On receive IRQ_2 (RX_START) indicates the detection of a valid PHR first, IRQ_5 (AMI) an address match and IRQ_3 (TRX_END) the completion of the frame reception. On transmit IRQ_3 (TRX_END) indicates the completion of the frame transmission. Figure 7-2 on page 39 shows an example for a transmit/receive transaction between two devices and the related interrupt events in Basic Operating Mode. Device 1 transmits a frame containing a MAC header (in this example of length 7), payload and valid FCS. The frame is received by Device 2 which generates the interrupts during the processing of the incoming frame. The received frame is stored in the Frame Buffer. The first interrupt IRQ_2 (RX_START) signals the reception of a valid PHR. If the received frame passes the address filter, refer to Section 7.2.3.5 “Frame Filtering” on page 61, an address match interrupt IRQ_5 (AMI) is issued after the reception of the MAC header (MHR). In Basic Operating Mode the third interrupt IRQ_3 (TRX_END) is issued at the end of the received frame. In Extended Operating Mode, refer to Section 7.2 “Extended Operating Mode” on page 47; the interrupt is only issued if the received frame passes the address filter and the FCS is valid. Further exceptions are explained in Section 7.2 “Extended Operating Mode” on page 47. Processing delay fIRQ is a typical value, refer to Section 12.4 “Digital Interface Timing Characteristics” on page 157. 38 AT86RF231 8111A–AVR–05/08 AT86RF231 Figure 7-2. Timing of RX_START, AMI and TRX_END Interrupts in Basic Operating Mode -16 0 128 160 192 192+(9+m)*32 Time [µs] TRX_STATE SLP_TR IRQ Typ. Processing Delay PLL_ON BUSY_TX PLL_ON TX (Device1) TRX_END IRQ_3 (TRX_END) 16 µs Frame Content Preamble SFD PHR MHR MSDU FCS TRX_STATE IRQ Interrupt latency IRQ_2 (RX_START) IRQ_5 (AMI) tIRQ tIRQ tIRQ 7.1.4 Basic Operating Mode Timing The following paragraphs depict state transitions and their timing properties. Timing figures are explained in Table 7-1 on page 42 and Section 12.4 “Digital Interface Timing Characteristics” on page 157. Power-on Procedure The power-on procedure to P_ON state is shown in Figure 7-3 on page 39. Figure 7-3. Power-on Procedure to P_ON State 0 100 400 Time [µs] 7.1.4.1 Event State Block Time VDD on P_ON XOSC, DVREG tTR1 CLKM on When the external supply voltage (VDD) is firstly supplied to the AT86RF231, the radio transceiver enables the crystal oscillator (XOSC) and the internal 1.8V voltage regulator for the digital domain (DVREG). After t TR1 = 380 µs (typ.), the master clock signal is available at pin 17 (CLKM) at default rate of 1 MHz. If CLKM is available the SPI is already enabled and can be used to control the transceiver. As long as no state change towards state TRX_OFF is performed the radio transceiver remains in P_ON state. RX (Device 2) RX_ON BUSY_RX RX_ON Frame on Air Number of Octets 4 1 1 7 m 2 39 8111A–AVR–05/08 7.1.4.2 Wake-up Procedure The wake-up procedure from SLEEP state is shown in Figure 7-4 on page 40. Figure 7-4. Wake-up Procedure from SLEEP State 0 SLP_TR = L SLEEP XOSC, DVREG tTR2 100 200 CLKM on IRQ_4 (AWAKE_END) TRX_OFF FTN XOSC, DVREG 400 Time [µs] Event State Block Time The radio transceivers SLEEP state is left by releasing pin SLP_TR to logic low. This restarts the XOSC and DVREG. After tTR2 = 240 µs (typ.) the radio transceiver enters TRX_OFF state. The internal clock signal is available and provided to pin 17 (CLKM), if CLKM was enabled. This procedure is similar to the Power-On Procedure. However the radio transceiver continues the state change automatically to the TRX_OFF state. During this the filter-tuning network (FTN) calibration is performed. Entering TRX_OFF state is signaled by IRQ_4 (AWAKE_END), if this interrupt was enabled by the appropriate mask register bit. 7.1.4.3 PLL_ON and RX_ON States The transition from TRX_OFF to PLL_ON and RX_ON mode is shown in Figure 7-5 on page 40. Figure 7-5. Transmission from TRX_OFF to PLL_ON and RX_ON State 0 100 IRQ_0 (PLL_LOCK) TRX_OFF AVREG PLL_ON tTR4 PLL PLL_ON RX_ON RX R_ON tTR8 Time [µs] Event State Block Command Time Note: If TRX_CMD = RX_ON in TRX_OFF state RX_ON state is entered immediately, even if the PLL has not settled. In TRX_OFF state, entering the commands PLL_ON or RX_ON initiates a ramp-up sequence of the internal 1.8V voltage regulator for the analog domain (AVREG). RX_ON state can be entered any time from PLL_ON state regardless whether the PLL has already locked, which is indicated by IRQ_0 (PLL_LOCK). 40 AT86RF231 8111A–AVR–05/08 AT86RF231 7.1.4.4 BUSY_TX and RX_ON States The transition from PLL_ON to BUSY_TX state and subsequent to RX_ON state is shown in Figure 7-6 on page 41. Figure 7-6. PLL_ON to BUSY_TX to RX_ON Timing 0 16 x x + 32 Time [µs] Pin State Block Command Time PLL_ON PLL SLP_TR BUSY_TX PA PA, TX RX_ON tTR11 RX_ON PLL RX or command TX_START tTR10 Starting from PLL_ON state it is further assumed that the PLL is already locked. A transmission is initiated either by a rising edge of pin 11 (SLP_TR) or by command TX_START. The PLL settles to the transmit frequency and the PA is enabled. tTR10 = 16 µs after initiating the transmission the AT86RF231 changes into BUSY_TX state and the internally generated SHR is transmitted. After that the PSDU data are transmitted from the Frame Buffer. After completing the frame transmission, indicated by IRQ_3 (TRX_END), the PLL settles back to the receive frequency within tTR11 = 32 µs in state PLL_ON. If during TX_BUSY the radio transmitter is programmed to change to a receive state it automatically proceeds the state change to RX_ON state after finishing the transmission. 7.1.4.5 Reset Procedure The radio transceiver reset procedure is shown in Figure 7-7 on page 41. Figure 7-7. Reset Procedure 0 x x + 10 x + 40 Time [µs] Event State Block Pin /RST Time >t10 >t11 tTR13 various XOSC, DVREG FTN [IRQ_4 (AWAKE_END)] TRX_OFF XOSC, DVREG Note: Timing figure tTR13 refers to Table 7-1 on page 42, t10, t11 refers to Section 12.4 “Digital Interface Timing Characteristics” on page 157. 41 8111A–AVR–05/08 /RST = L sets all registers to their default values. Exceptions are register bits CLKM_CTRL (register 0x03, TRX_CTRL_0), refer to Section 9.6.4 “Master Clock Signal Output (CLKM)” on page 117. After releasing the reset pin (/RST = H) the wake-up sequence including an FTN calibration cycle is performed, refer to Section 9.8 “Automatic Filter Tuning (FTN)” on page 125. After that the TRX_OFF state is entered. Figure 7-7 on page 41 illustrates the reset procedure once the P_ON state was left and the radio transceiver was not in SLEEP state. The reset procedure is identical for all originating radio transceiver states except of state P_ON and SLEEP state. Instead, here the procedure described in Section 7.1.2.1 “P_ON - Power-On after VDD” on page 34 must be followed to enter the TRX_OFF state. If the radio transceiver was in SLEEP state, the XOSC and DVREG are enabled before entering TRX_OFF state. If register TRX_STATUS indicates STATE_TRANSITION_IN_PROGRESS during system initialization until the AT86RF231 reaches TRX_OFF, do not try to initiate a further state change while the radio transceiver is in this state. Notes • The reset impulse should have a minimum length t10 = 625 ns as specified in Section 12.4 “Digital Interface Timing Characteristics” on page 157, see parameter 12.4.13. • An access to the device should not occur earlier than t11 ≥ 625 ns after releasing the pin /RST; refer to Section 12.4 “Digital Interface Timing Characteristics” on page 157, parameter 12.4.14. • A reset overrides an SPI command request that might be queued. 7.1.4.6 State Transition Timing Summary The transition numbers correspond to Figure 7-1 on page 33 and do not include SPI access time if not otherwise stated. See measurement setup in Figure 5-1 on page 12. Table 7-1. No 1 Symbol tTR1 State Transition Timing Transition P_ON Time [µs], (type) 380 Comments Depends on external capacitor at DVDD (1 µF nom) and crystal oscillator setup (CL = 10 pF) Depends on external capacitor at DVDD (1 µF nom) and crystal oscillator setup (CL = 10 pF) TRX_OFF state indicated by IRQ_4 (AWAKE_END) For fCLKM > 250 kHz Depends on external capacitor at AVDD (1 µF nom) ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ ⇒ until CLKM available TRX_OFF SLEEP PLL_ON TRX_OFF RX_ON TRX_OFF RX_ON PLL_ON 2 3 4 5 6 7 8 9 tTR2 tTR3 tTR4 tTR5 tTR6 tTR7 tTR8 tTR9 SLEEP TRX_OFF TRX_OFF PLL_ON TRX_OFF RX_ON PLL_ON RX_ON 240 35*1/fCLKM 110 1 110 1 1 1 Depends on external capacitor at AVDD (1 µF nom) Transition time is also valid for TX_ARET_ON, RX_AACK_ON 42 AT86RF231 8111A–AVR–05/08 AT86RF231 Table 7-1. No 10 11 12 13 14 Symbol tTR10 tTR11 tTR12 tTR13 tTR14 PLL_ON BUSY_TX All modes RESET Various States State Transition Timing (Continued) Transition Time [µs], (type) 16 32 1 37 1 Comments When asserting pin 11 (SLP_TR) or TRX_CMD = TX_START first symbol transmission is delayed by 16 µs delay (PLL settling and PA ramp up) PLL settling time from TX_BUSY to PLL_ON state Using TRX_CMD = FORCE_TRX_OFF (see register 0x02, TRX_STATE), Not valid for SLEEP state Valid for P_ON or SLEEP state Using TRX_CMD = FORCE_PLL_ON (see register 0x02, TRX_STATE), Not valid for SLEEP, P_ON, RESET, TRX_OFF and *_NO_CLK ⇒ ⇒ ⇒ ⇒ ⇒ BUSY_TX PLL_ON TRX_OFF TRX_OFF PLL_ON The state transition timing is calculated based on the timing of the individual blocks shown in Figure 7-3 on page 39 to Figure 7-7 on page 41. The worst case values include maximum operating temperature, minimum supply voltage, and device parameter variations. Table 7-2. No 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Symbol tTR15 tTR16 tTR17 tTR18 tTR19 tTR20 tTR21 tTR22 tTR23 tTR24 tTR25 tTR26 tTR27 tTR28 tTR29 Analog Block Initialization and Settling Time Block XOSC FTN DVREG AVREG PLL, initial PLL settling PLL, CF cal PLL, DCU cal PLL, RX ⇒TX PLL, TX ⇒RX RSSI, update ED SHR, sync CCA Random value 96 140 1 60 60 110 11 35 6 16 32 2 140 Time [µs], (type) 215 Time [µs], (max) 1000 25 1000 1000 155 24 Comment Leaving SLEEP state, depends on crystal Q factor and load capacitor FTN tuning time fixed Depends on external bypass capacitor at DVDD (CB3 = 1 µF nom., 10 µF worst case), depends on VDD Depends on external bypass capacitor at AVDD (CB1 = 1 µF nom, 10 µF worst case), depends on VDD PLL settling time TRX_OFF ⇒PLL_ON, including 60 µs AVREG settling time Settling time between channels switch PLL center frequency calibration, refer to Section 9.7.4 PLL DCU calibration, refer to Section 9.7.4 Maximum PLL settling time RX ⇒TX Maximum PLL settling time TX ⇒RX RSSI update period in receive states, refer to Section 8.3.2 ED measurement period, refer to Section 8.4.2 Typical SHR synchronisation period, refer to Section 8.4.2 CCA measurement period, refer to Section 8.5.2 Random value update period, refer to Section 11.2.1 43 8111A–AVR–05/08 7.1.5 Register Description Register 0x01 (TRX_STATUS): A read access to TRX_STATUS register signals the current radio transceiver state. A state change is initiated by writing a state transition command to register bits TRX_CMD (register 0x02, TRX_STATE). Alternatively a state transition can be initiated by the rising edge of pin 11 (SLP_TR) in the appropriate state. This register is used for Basic and Extended Operating Mode, refer to Section 7.2 “Extended Operating Mode” on page 47. Bit +0x01 Read/Write Reset Value 7 CCA_DONE R 0 6 CCA_STATUS R 0 5 Reserved R 0 4 3 2 TRX_STATUS 1 0 TRX_STATUS R 0 R 0 R 0 R 0 R 0 • Bit 7 - CCA_DONE Refer to Section 8.5 “Clear Channel Assessment (CCA)” on page 94. • Bit 6 - CCA_STATUS Refer to Section 8.5 “Clear Channel Assessment (CCA)” on page 94. • Bit 5 - Reserved • Bit [4:0] - TRX_STATUS The register bits TRX_STATUS signals the current radio transceiver status. If the requested state transition is not completed yet, the TRX_STATUS returns STATE_TRANSITION_IN_PROGRESS. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS. State transition timings are defined in Table 7-1 on page 42. 44 AT86RF231 8111A–AVR–05/08 AT86RF231 Table 7-3. Register Bits TRX_STATUS Radio Transceiver Status, Register Bits TRX_STATUS Value 0x00 0x01 0x02 0x06 0x08 0x09 0x0F 0x11 0x12 (3) State Description P_ON BUSY_RX BUSY_TX RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) SLEEP BUSY_RX_AACK BUSY_TX_ARET RX_AACK_ON TX_ARET_ON RX_ON_NOCLK RX_AACK_ON_NOCLK BUSY_RX_AACK_NOCLK STATE_TRANSITION_IN_PROGRESS All other values are reserved (1) (1) 0x16(1) 0x19 (1) 0x1C 0x1D (1) 0x1E(1) 0x1F(2) Notes: 1. Extended Operating Mode only, refers to Section 7.2 “Extended Operating Mode” on page 47. 2. Do not try to initiate a further state change while the radio transceiver is in STATE_TRANSITION_IN_PROGRESS state. 3. In SLEEP state register not accessible. 45 8111A–AVR–05/08 Register 0x02 (TRX_STATE): The radio transceiver states are controlled via register bits TRX_CMD, which receives the state transition commands. This register is used for Basic and Extended Operating Mode, refer to Section 7.2 “Extended Operating Mode” on page 47. Bit +0x02 Read/Write Reset Value R 0 7 6 TRAC_STATUS R 0 R 0 R/W 0 R/W 0 5 4 3 2 TRX_CMD R/W 0 R/W 0 R/W 0 1 0 TRX_STATE • Bit [7:5] - TRAC_STATUS Refer to Section 7.2.7 “Register Description - Control Registers” on page 68. • Bit [4:0] - TRX_CMD A write access to register bits TRX_CMD initiate a radio transceiver state transition towards the new state as defined by the write access: Table 7-4. Register Bit TRX_CMD State Control Command, Register Bits TRX_CMD Value 0x00 0x02 0x03 0x04(1) 0x06 0x08 0x09 0x16 0x19 (2) (2) State Description NOP TX_START FORCE_TRX_OFF FORCE_PLL_ON RX_ON TRX_OFF (CLK Mode) PLL_ON (TX_ON) RX_AACK_ON TX_ARET_ON All other values are reserved and mapped to NOP Notes: 1. FORCE_PLL_ON is not valid for states SLEEP, P_ON, RESET, TRX_OFF, and all *_NOCLK states, as well as STATE_TRANSITION_IN_PROGRESS towards these states. 2. Extended Operating Mode only, refers to Section 7.2.7 “Register Description - Control Registers” on page 68. 46 AT86RF231 8111A–AVR–05/08 AT86RF231 7.2 Extended Operating Mode The Extended Operating Mode is a hardware MAC accelerator and goes beyond the basic radio transceiver functionality provided by the Basic Operating Mode. It handles time critical MAC tasks, requested by the IEEE 802.15.4 standard, by hardware, such as automatic acknowledgement, automatic CSMA-CA and retransmission. This results in a more efficient IEEE 802.15.4 software MAC implementation including reduced code size and may allow the use of a smaller microcontroller or to operate at low clock rates. The Extended Operating Mode is designed to support IEEE 802.15.4-2006 compliant frames; the mode is backward compatible to IEEE 802.15.4-2003 and supports non IEEE 802.15.4 compliant frames. This mode comprises the following procedures: Automatic acknowledgement (RX_AACK) divides into the tasks: • Frame reception and automatic FCS check • Configurable addressing fields check • Interrupt indicating address match • Interrupt indicating frame reception, if it passes address filtering and FCS check • Automatic ACK frame transmission (if the received frame passed the address filter and FCS check and if an ACK is required by the frame type and ACK request) • Support of slotted acknowledgment using SLP_TR pin Automatic CSMA-CA and Retransmission (TX_ARET) divides into the tasks: • CSMA-CA including automatic CCA retry and random back-off • Frame transmission and automatic FCS field generation • Reception of ACK frame (if an ACK was requested) • Automatic frame retry if ACK was expected but not received • Interrupt signaling with transaction status Automatic FCS check and generation, refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85, is used by the RX_AACK and TX_ARET modes. In RX_AACK mode, an automatic FCS check is always performed for incoming frames. In TX_ARET mode, an ACK, received within the time required by IEEE 802.15.4, is accepted if the FCS is valid, and if the sequence number of the ACK matches the sequence number of the previously transmitted frame. Dependent on the value of the frame pending subfield in the received acknowledgement frame the transaction status is set, see Table 7-16 on page 70. An AT86RF231 state diagram including the Extended Operating Mode states is shown in Figure 7-8 on page 48. Yellow marked states represent the Basic Operating Mode; blue marked states represent the Extended Operating Mode. 47 8111A–AVR–05/08 Figure 7-8. Extended Operating Mode State Diagram P_ON (Power-on after VDD) XOSC=ON Pull=ON SLEEP (Sleep State) XOSC=OFF Pull=OFF SL P_ TR = L _T R= H 3 (from all states) /RST = L FORCE_TRX_OFF 12 TRX_OFF (Clock State) XOSC=ON Pull=OFF SL P (all modes except SLEEP) N _O TR 6 SHR Detected X_ OF F RX X TR FF _O 1 2 13 /RST = H (all modes except P_ON) RESET PL 7 5 X_ TR F OF ON L_ 4 8 BUSY_RX (Receive State) Frame End TR =H RX_ON (Rx Listen State) RX_ON PLL_ON PLL_ON (PLL State) 9 14 SLP_TR=H or TX_START 11 10 Frame End BUSY_TX (Transmit State) SHR Detected SL P_ TR P_ SL =L N N (Rx Listen State) CLKM=OFF RX _A RX_ON_NOCLK From / To TRX_OFF SHR Detected BUSY_RX_AACK Transaction Finished RX_AACK_ON TX_ARET_ON Frame End TX_ARET_ON TX _A RE T_ TR ON X_ OF F L_ O AC K_ O FORCE_PLL_ON see notes PLL_ON PL RX _ AA CK _O TR N X_ OF F From / To TRX_OFF SLP_TR=H or TX_START BUSY_TX_ARET SLP_TR=H SLP_TR=L Frame Accepted BUSY_RX_ AACK_NOCLK CLKM=OFF SHR Detected RX_AACK_ ON_NOCLK CLKM=OFF Legend: Blue: SPI Write to Register TRX_STATE (0x02) Red: Control signals via IC Pin Green: Event Basic Operating Mode States Extended Operating Mode States Frame Rejected 48 AT86RF231 8111A–AVR–05/08 AT86RF231 7.2.1 State Control The Extended Operating Mode states RX_AACK and TX_ARET are controlled via register bits TRX_CMD (register 0x02, TRX_STATE), which receives the state transition commands. The states are entered from TRX_OFF or PLL_ON state as illustrated by Figure 7-8 on page 48. The completion of each state change command shall always be confirmed by reading the register 0x01 (TRX_STATUS). RX_AACK - Receive with Automatic ACK A state transition to RX_AACK_ON from PLL_ON or TRX_OFF is initiated by writing the command RX_AACK_ON to the register bits TRX_CMD. The state change can be confirmed by reading register 0x01 (TRX_STATUS), those changes to RX_AACK_ON or BUSY_RX_AACK on success. The latter one is returned if a frame is currently about being received. The RX_AACK state is left by writing command TRX_OFF or PLL_ON to the register bits TRX_CMD. If the AT86RF231 is within a frame receive or acknowledgment procedure (BUSY_RX_AACK) the state change is executed after finish. Alternatively, the commands FORCE_TRX_OFF or FORCE_PLL_ON can be used to cancel the RX_AACK transaction and change into radio transceiver state TRX_OFF or PLL_ON, respectively. TX_ARET - Transmit with Automatic Retry and CSMA-CA Retry Similarly, a state transition to TX_ARET_ON from PLL_ON or TRX_OFF is initiated by writing command TX_ARET_ON to register bits TRX_CMD. The radio transceiver is in the TX_ARET_ON state after TRX_STATUS (register 0x01) changes to TX_ARET_ON. The TX_ARET transaction is started with a rising edge of pin 11 (SLP_TR) or writing the command TX_START to register bits TRX_CMD. The TX_ARET state is left by writing the command TRX_OFF or PLL_ON to the register bits TRX_CMD. If the AT86RF231 is within a CSMA-CA, a frame-transmit or an acknowledgment procedure (BUSY_TX_ARET) the state change is executed after finish. Alternatively the command FORCE_TRX_OFF or FORCE_PLL_ON can be used to instantly terminate the TX_ARET transaction and change into radio transceiver state TRX_OFF or PLL_ON, respectively. Note • A state change request from TRX_OFF to RX_AACK_ON or TX_ARET_ON internally passes the state PLL_ON to initiate the radio transceiver. Thus the readiness to receive or transmit data is delayed accordingly. It is recommended to use interrupt IRQ_0 (PLL_LOCK) as an indicator. 49 8111A–AVR–05/08 7.2.2 Configuration The use of the Extended Operating Mode is based on Basic Operating Mode functionality. Only features beyond the basic radio transceiver functionality are described in the following sections. For details on the Basic Operating Mode refer to Section 7.1 “Basic Operating Mode” on page 33. When using the RX_AACK or TX_ARET modes, the following registers needs to be configured. RX_AACK configuration steps: • Short address, PAN-ID and IEEE address • Configure RX_AACK properties – Handling of Frame Version Subfield – Handling of Pending Data Indicator – Characterize as PAN coordinator – Handling of Slotted Acknowledgement • Additional Frame Filtering Properties – Promiscuous Mode – Enable or disable automatic ACK generation – Handling of reserved frame types The addresses for the address match algorithm are to be stored in the appropriate address registers. Additional control of the RX_AACK mode is done with register 0x17 (XAH_CTRL_1) and register 0x2E (CSMA_SEED_1). As long as a short address has not been set, only broadcast frames and frames matching the IEEE address can be received. Configuration examples for different device operating modes and handling of various frame types can be found in Section 7.2.3.1 “Description of RX_AACK Configuration Bits” on page 54. registers 0x17, 0x2E registers 0x20 - 0x2B registers 0x2C, 0x2E TX_ARET configuration steps: • Leave register bit TX_AUTO_CRC_ON = 1 • Configure CSMA-CA – MAX_FRAME_RETRIES – MAX_CSMA_RETRIES – CSMA_SEED – MAX_BE, MIN_BE • Configure CCA (see Section 8.5) M A X _ F R A M E _ R E T R IE S ( re g i s te r 0 x 2 C) d e fi n e s t h e m a x i m u m n u m b e r o f f ra m e retransmissions. The register bits MAX_CSMA_RETRIES (register 0x2C) configure the number of CSMA-CA retries after a busy channel is detected. register 0x2C, XAH_CTRL_0 register 0x2C, XAH_CTRL_0 registers 0x2D, 0x2E register 0x2F, CSMA_BE register 0x04, TRX_CTRL_1 50 AT86RF231 8111A–AVR–05/08 AT86RF231 The CSMA_SEED_0 and CSMA_SEED_1 register bits (registers 0x2D, 0x2E) define a random seed for the back-off-time random-number generator in theAT86RF231. The MAX_BE and MIN_BE register bits (register 0x2F) sets the maximum and minimum CSMA back-off exponent (according to [1]). 7.2.3 RX_AACK_ON - Receive with Automatic ACK The general functionality of the RX_AACK procedure is shown in Figure 7-9 on page 53. The gray shaded area is the standard flow of an RX_AACK transaction for IEEE 802.15.4 compliant frames, refer Section 7.2.3.2 “Configuration of IEEE Scenarios” on page 55. All other procedures are exceptions for specific operating modes or frame formats, refer to Section 7.2.3.3 “Configuration of non IEEE 802.15.4 Compliant Scenarios” on page 58. The frame filtering operations is described in detail in Section 7.2.3.5 “Frame Filtering” on page 61. In RX_AACK_ON state, the radio transceiver listens for incoming frames. After detecting a valid PHR, the radio transceiver parses the frame content of the MAC header (MHR), refer to Section 8.1.2 “MAC Protocol Layer Data Unit (MPDU)” on page 80. Generally, at nodes, configured as a normal device or PAN coordinator, a frame is not indicated if the frame filter does not match and the FCS is invalid. Otherwise, the interrupt IRQ_3 (TRX_END) is issued after the completion of the frame reception. The microcontroller can then read the frame. An exception applies if promiscuous mode is enabled; see Section 7.2.3.2 “Configuration of IEEE Scenarios” on page 55, in that case an IRQ_3 (TRX_END) interrupt is issued, even if the FCS fails. If the content of the MAC addressing fields of the received frame (refer to IEEE 802.15.4 section 7.2.1) matches one of the configured addresses, dependent on the addressing mode, an address match interrupt IRQ_5 (AMI) is issued, refer to Section 7.2.3.5 “Frame Filtering” on page 61. The expected address values are to be stored in registers 0x20 - 0x2B (Short address, PAN-ID and IEEE address). Frame filtering as described in Section 7.2.3.5 “Frame Filtering” on page 61 is also valid for Basic Operating Mode. During reception the AT86RF231 parses bit [5] (ACK Request) of the frame control field of the received data or MAC command frame to check if an ACK reply is expected. In that case and if the frame passes the third level of filtering, see IEEE 802.15.4-2006, section 7.5.6.2, the radio transceiver automatically generates and transmits an ACK frame. The content of the frame pending subfield of the ACK response is set by register bit AACK_SET_PD (register 0x2E, CSMA_SEED_1) when the ACK frame is sent in response to a data request MAC command frame, otherwise this subfield is set to 0. The sequence number is copied from the received frame. Optionally, the start of the transmission of the acknowledgement frame can be influenced by register bit AACK_ACK_TIME. Default value (according to standard IEEE 802.15.4) is 12 symbol times after the reception of the last symbol of a data or MAC command frame. If the register bit AACK_DIS_ACK (register 0x2E, CSMA_SEED_1) is set, no acknowledgement frame is sent even if an acknowledgment frame was requested. This is useful for operating the MAC hardware accelerator in promiscuous mode, see Section 7.2.3.2 “Configuration of IEEE Scenarios” on page 55. 51 8111A–AVR–05/08 The status of the RX_AACK operation is indicated by register bits TRAC_STATUS (register 0x02, TRAC_STATUS), see Section 7.2.7 “Register Description - Control Registers” on page 68. During the operations described above the AT86RF231 remains in BUSY_RX_AACK state. 52 AT86RF231 8111A–AVR–05/08 AT86RF231 Figure 7-9. Flow Diagram of RX_AACK TRX_STATE = RX_AACK_ON N SHR detected Y TRX_STATE = BUSY_RX_AACK Generate IRQ_2 (RX_START) Scanning MHR Promiscuous Mode Reserved Frames Frame Filtering Note 1: Address match, Promiscuous Mode and Reserved Frames: - A radio transceiver in Promiscuous Mode, or configured to receive Reserved Frames handles received frames passing the third level of filtering - For details refer to the description of Promiscuous Mode and Reserved Frame Types N Y (see Note 1) Frame reception Generate IRQ_5 (AMI) N Frame reception AACK_PROM_MODE == 1 Y N FCS valid (see Note 2) N FCF[2:0] >3 Y Note 2: FCS check is omitted for Promiscous Mode Y Generate IRQ_3 (TRX_END) N N Note 3: Additional conditions: - ACK requested & - ACK_DIS_ACK==0 & - frame_version 3) can be received if register bit AACK_UPLD_RES_FT (register 0x17, XAH_CTRL_1) is set, for details refer to Section 7.2.3.3 “Configuration of non IEEE 802.15.4 Compliant Scenarios” on page 58. Address filtering is also provided in Basic Operating Mode, refer to Section 7.1 “Basic Operating Mode” on page 33. • Bit 3: indicates whether security processing applies to this frame. • Bit 4: is the "Frame Pending" subfield. This field can be set in an acknowledgment frame (ACK) in response to a data request MAC command frame. This bit indicates that the node, which transmitted the ACK, has more data to send to the node receiving the ACK. For acknowledgment frames automatically generated by the AT86RF231, this bit is set according to the content of register bit AACK_SET_PD in register 0x2E (CSMA_SEED_1) if the received frame was a data request MAC command frame. • Bit 5: forms the "Acknowledgment Request" subfield. If this bit is set within a data or MAC command frame that is not broadcast, the recipient shall acknowledge the reception of the frame within the time specified by IEEE 802.15.4 (i.e. within 192 µs for non beacon-enabled networks). The radio transceiver parses this bit during RX_AACK mode and transmits an acknowledgment frame if necessary. In TX_ARET mode this bit indicates if an acknowledgement frame is expected after transmitting a frame. If this is the case, the receiver waits for the acknowledgment frame, otherwise the TX_ARET transaction is finished. 81 8111A–AVR–05/08 • Bit 6: The "Intra-PAN" subfield indicates that in a frame, where both, the destination and source addresses are present, the PAN-ID of the source address field is omitted. In RX_AACK mode, this bit is evaluated by the address filter logic of the AT86RF231. • Bit [11:10]: the "Destination Addressing Mode" subfield describes the format of the destination address of the frame. The values of the address modes are summarized in Table 8-3 on page 82, according to IEEE 802.15.4. Table 8-3. Frame Control Field - Destination and Source Addressing Mode Description Frame Control Field Bit Assignments Addressing Mode b11 b10 b15 b14 00 01 10 11 Value 0 1 2 3 PAN identifier and address fields are not present Reserved Address field contains a 16-bit short address Address field contains a 64-bit extended address If the destination address mode is either 2 or 3 (i.e. if the destination address is present), it always consists of a 16-bit PAN ID first, followed by either the 16-bit or 64-bit address as described by the mode. • Bit [13:12]: the "Frame Version" subfield specifies the version number corresponding to the frame. These register bits are reserved in IEEE 802.15.4-2003. This subfield shall be set to 0 to indicate a frame compatible with IEEE 802.15.4-2003 and 1 to indicate an IEEE 802.15.4-2006 frame. All other subfield values shall be reserved for future use. RX_AACK register bit AACK_FVN_MODE (register 0x2E, CSMA_SEED_1) controls the behavior of frame acknowledgements. This register determines if, depending on the Frame Version Number, a frame is acknowledged or not. This is necessary for backward compatibility to IEEE 802.15.4-2003 and for future use. Even if frame version numbers 2 and 3 are reserved, it can be handled by the radio transceiver, for details refer to Section 7.2.7 “Register Description - Control Registers” on page 68. See IEEE 802.15.4-2006, section 7.2.3 for details on frame compatibility. Table 8-4. Frame Control Field - Frame Version Subfield Description Frame Control Field Bit Assignments Frame Version b13 b12 00 01 10 11 Value 0 1 2 3 Frames are compatible with IEEE 802.15.4 2003 Frames are compatible with IEEE 802.15.4-2006 Reserved Reserved 82 AT86RF231 8111A–AVR–05/08 AT86RF231 • Bit [15:14]: the "Source Addressing Mode" subfield, with similar meaning as "Destination Addressing Mode", see Table 8-3 on page 82. The subfields of the FCF (Bits 0-2, 3, 6, 10-15) affect the address filter logic of the AT86RF231 while operating in RX_AACK operation, see Section 7.2.3 “RX_AACK_ON - Receive with Automatic ACK” on page 51. 8.1.2.3 Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006 All unsecured frames according to IEEE 802.15.4-2006 are compatible with unsecured frames compliant with IEEE 802.15.4-2003 with two exceptions: a coordinator realignment command frame with the "Channel Page" field present (see IEEE 802.15.4-2006, section 7.3.8) and any frame with a MAC Payload field larger than aMaxMACSafePayloadSize octets. Compatibility for secured frames is shown in Table 8-5 on page 83, which identifies the security operating modes for IEEE 802.15.4-2006. Table 8-5. Frame Control Field - Security and Frame Version Description Frame Control Field Bit Assignments Security Enabled b3 0 0 1 1 Frame Version b13 b12 00 01 00 01 No security. Frames are compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006. No security. Frames are not compatible between IEEE 802.15.4-2003 and IEEE 802.15.4-2006. Secured frame formatted according to IEEE 802.15.4-2003. This frame type is not supported in IEEE 802.15.4-2006. Secured frame formatted according to IEEE 802.15.4-2006 8.1.2.4 Sequence Number The one-octet sequence number following the FCF identifies a particular frame, so that duplicated frame transmissions can be detected. While operating in RX_AACK mode, the content of this field is copied from the frame to be acknowledged into the acknowledgment frame. Addressing Fields The addressing fields of the MPDU are used by the AT86RF231 for address matching indication. The destination address (if present) is always first, followed by the source address (if present). Each address field consists of the Intra PAN ID and a device address. If both addresses are present, and the "Intra PAN-ID compression" subfield in the FCF is set to one, the source Intra PAN ID is omitted. Note that in addition to these general rules, IEEE 802.15.4 further restricts the valid address combinations for the individual possible MAC frame types. For example, the situation where both addresses are omitted (source addressing mode = 0 and destination addressing mode = 0) is only allowed for acknowledgment frames. The address filter in the AT86RF231 has been designed to apply to IEEE 802.15.4 compliant frames. It can be configured to handle other frame formats and exceptions. 8.1.2.5 83 8111A–AVR–05/08 8.1.2.6 Auxiliary Security Header Field The Auxiliary Security Header specifies information required for security processing and has a variable length. This field determines how the frame is actually protected (security level) and which keying material from the MAC security PIB is used (see IEEE 802.15.4-2006, section 7.6.1). This field shall be present only if the Security Enabled subfield b3, see Section 8.1.2.3 “Frame Compatibility between IEEE 802.15.4-2003 and IEEE 802.15.4-2006” on page 83, is set to one. For details of its structure, see IEEE 802.15.4-2006, section 7.6.2. Auxiliary security header. MAC Service Data Unit (MSDU) This is the actual MAC payload. It is usually structured according to the individual frame type. A description can be found in IEEE 802.15.4-2006, section 5.5.3.2. MAC Footer (MFR) Fields The MAC footer consists of a two-octet Frame Checksum (FCS), for details refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85. 8.1.2.7 8.1.2.8 84 AT86RF231 8111A–AVR–05/08 AT86RF231 8.2 Frame Check Sequence (FCS) The Frame Check Sequence (FCS) is characterized by: • Indicate bit errors, based on a cyclic redundancy check (CRC) of length 16 bit • Uses International Telecommunication Union (ITU) CRC polynomial • Automatically evaluated during reception • Can be automatically generated during transmission 8.2.1 Overview The FCS is intended for use at the MAC layer to detect corrupted frames at a first level of filtering. It is computed by applying an ITU CRC polynomial to all transferred bytes following the length field (MHR and MSDU fields). The frame check sequence has a length of 16 bit and is located in the last two bytes of a frame (MAC footer, see Figure 8-2 on page 80). The AT86RF231 applies an FCS check on each received frame. The FCS check result is stored in register bit RX_CRC_VALID in register 0x06 (PHY_RSSI). On transmit the radio transceiver generates and appends the FCS bytes during the frame transmission. This behavior can be disabled by setting register bit TX_AUTO_CRC_ON = 0 (register 0x04, TRX_CTRL_1). 8.2.2 CRC Calculation The CRC polynomial used in IEEE 802.15.4 networks is defined by: G 16 ( x ) = x 16 +x 12 +x +1 5 The FCS shall be calculated for transmission using the following algorithm: Let M ( x ) = b0 x k–1 + b1 x k–2 + b2 x k–3 + … + bk – 2 x + bk – 1 be the polynomial representing the sequence of bits for which the checksum is to be computed. Multiply M(x) by x16, giving the polynomial N(x) = M( x) • x 16 Divide N(x) modulo 2 by the generator polynomial, G16(x), to obtain the remainder polynomial, R ( x ) = r0 x 15 + r1 x 14 + … + r 14 x + r 15 The FCS field is given by the coefficients of the remainder polynomial, R(x). Example: Considering a 5 octet ACK frame. The MHR field consists of 0100 0000 0000 0000 0101 0110. The leftmost bit (b0) is transmitted first in time. The FCS is in this case 0010 0111 1001 1110. The leftmost bit (r0) is transmitted first in time. 85 8111A–AVR–05/08 8.2.3 Automatic FCS generation The automatic FCS generation is performed with register bit TX_AUTO_CRC_ON = 1 (reset value). This allows the AT86RF231 to compute the FCS autonomously. For a frame with a frame length specified as N (3 ≤ N ≤ 127), the FCS is calculated on the first N-2 octets in the Frame Buffer, and the resulting FCS field is transmitted in place of the last two octets from the Frame Buffer. If the radio transceivers automatic FCS generation is enabled, the Frame Buffer write access can be stopped right after MAC payload. There is no need to write FCS dummy bytes. In RX_AACK mode, when a received frame needs to be acknowledged, the FCS of the ACK frame is always automatically generated by the AT86RF231, independent of the TX_AUTO_CRC_ON setting. Example: A frame transmission of length five with TX_AUTO_CRC_ON set, is started with a Frame Buffer write access of five bytes (the last two bytes can be omitted). The first three bytes are used for FCS generation; the last two bytes are replaced by the internally calculated FCS. 8.2.4 Automatic FCS check An automatic FCS check is applied on each received frame with a frame length N ≥ 2. Register bit RX_CRC_VALID (register 0x06, PHY_RSSI) is set if the FCS of a received frame is valid. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt caused by a new frame reception. In RX_AACK mode, if FCS of the received frame is not valid, the radio transceiver rejects the frame and the TRX_END interrupt is not issued. In TX_ARET mode, the FCS and the sequence number of an ACK is automatically checked. If one of these is not correct, the ACK is not accepted. 86 AT86RF231 8111A–AVR–05/08 AT86RF231 8.2.5 Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit +0x04 Read/Write Reset Value 7 PA_EXT_EN R/W 0 6 IRQ_2_EXT_EN R/W 0 5 TX_AUTO_CRC_ON R/W 1 4 RX_BL_CTRL R/W 0 3 2 1 IRQ_MASK_MODE R/W 0 0 IRQ_POLARITY R/W 0 TRX_CTRL_1 SPI_CMD_MODE R/W 0 R/W 0 • Bit 7 - PA_EXT_EN Refer to Section 11.5 “RX/TX Indicator” on page 147. • Bit 6 - IRQ_2_EXT_EN Refer to Section 11.6 “RX Frame Time Stamping” on page 150. • Bit 5 - TX_AUTO_CRC_ON Register bit TX_AUTO_CRC_ON controls the automatic FCS generation for TX operations. The automatic FCS algorithm is performed autonomously by the radio transceiver if register bit TX_AUTO_CRC_ON = 1. • Bit 4 - RX_BL_CTRL Refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152. • Bit [3:2] - SPI_CMD_MODE Refer to Section 6.3 “Radio Transceiver Status information” on page 24. • Bit 1 - IRQ_MASK_MODE Refer to Section 6.6 “Interrupt Logic” on page 29. • Bit 0 - IRQ_POLARITY Refer to Section 6.6 “Interrupt Logic” on page 29. Register 0x06 (PHY_RSSI): The PHY_RSSI register is a multi purpose register that indicates FCS validity, provides random numbers and shows the actual RSSI value. Bit +0x06 Read/Write Reset Value 7 RX_CRC_VALID R 0 6 5 4 3 2 RSSI R 0 R 0 R 0 R 0 R 0 1 0 PHY_RSSI RND_VALUE R 0 R 0 87 8111A–AVR–05/08 • Bit 7 - RX_CRC_VALID Reading this register bit indicates whether the last received frame has a valid FCS or not. The register bit is updated when issuing interrupt IRQ_3 (TRX_END) and remains valid until the next TRX_END interrupt is issued, caused by a new frame reception. Table 8-6. Register Bit RX_CRC_VALID RX Frame FCS Check Value 0 1 State Description FCS is not valid FCS is valid • Bit [6:5] - RND_VALUE Refer to register description in Section 11.2.2 “Register Description” on page 136. • Bit [4:0] - RSSI Refer to register description in Section 8.3.4 “Register Description” on page 90. 88 AT86RF231 8111A–AVR–05/08 AT86RF231 8.3 Received Signal Strength Indicator (RSSI) The Received Signal Strength Indicator is characterized by: • Minimum RSSI level is -90 dBm (RSSI_BASE_VAL) • Dynamic range is 81 dB • Minimum RSSI value is 0 • Maximum RSSI value is 28 8.3.1 Overview The RSSI is a 5-bit value indicating the receive power in the selected channel, in steps of 3 dB. No attempt is made to distinguish IEEE 802.15.4 signals from others, only the received signal strength is evaluated. The RSSI provides the basis for an ED measurement, see Section 8.4 “Energy Detection (ED)” on page 91. 8.3.2 Reading RSSI In Basic Operating Mode the RSSI value is valid in any receive state, and is updated every tTR25 = 2 µs to register 0x06 (PHY_RSSI). It is not recommended to read the RSSI value when using the Extended Operating Mode. The automatically generated ED value should be used alternatively, see Section 8.4 “Energy Detection (ED)” on page 91. 8.3.3 Data Interpretation The RSSI value is a 5-bit value indicating the receive power, in steps of 3 dB and with a range of 0 -28. An RSSI value of 0 indicates a receiver RF input power of PRF < -90 dBm. For an RSSI value in the range of 1 to 28, the RF input power can be calculated as follows: PRF = RSSI_BASE_VAL + 3*(RSSI -1) [dBm] 89 8111A–AVR–05/08 Figure 8-4. 10 0 Receiver Input Power PRF [dBm] -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 Mapping between RSSI Value and Received Input Power Measured Ideal 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 RSSI 8.3.4 Register Description Register 0x06 (PHY_RSSI): Bit +0x06 Read/Write Reset Value 7 RX_CRC_VALID R 0 6 5 4 3 2 RSSI R 0 R 0 R 0 R 0 R 0 1 0 PHY_RSSI RND_VALUE R 0 R 0 • Bit 7 - RX_CRC_VALID Refer to register description in Section 8.2.5 “Register Description” on page 87. • Bit [6:5] - RND_VALUE Refer to register description in section Section 11.2.2 “Register Description” on page 136. • Bit [4:0] - RSSI The result of the automated RSSI measurement is stored in register bits RSSI. The value is updated every 2 µs in receive states. The read value is a number between 0 and 28 indicating the received signal strength as a linear curve on a logarithmic input power scale (dBm) with a resolution of 3 dB. An RSSI value of 0 indicates an RF input power of PRF < -90 dBm (see parameter 12.7.16), a value of 28 a power of PRF ≥ 10 dBm (see parameter 12.7.18). 90 AT86RF231 8111A–AVR–05/08 AT86RF231 8.4 Energy Detection (ED) The Energy Detection (ED) module is characterized by: • 85 unique energy levels defined • 1 dB resolution 8.4.1 Overview The receiver ED measurement is used by the network layer as part of a channel selection algorithm. It is an estimation of the received signal power within the bandwidth of an IEEE 802.15.4 channel. No attempt is made to identify or decode signals on the channel. The ED value is calculated by averaging RSSI values over eight symbols (128 µs). For High Data Rate Modes the automated ED measurement duration is reduced to 32 µs, refer to Section 11.3 “High Data Rate Modes” on page 137. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. 8.4.2 Measurement Description There are two ways to initiate an ED measurement: • Manually, by writing an arbitrary value to register 0x07 (PHY_ED_LEVEL), or • Automatically, after detection of a valid SHR of an incoming frame. For manually initiated ED measurements the radio transceiver needs to be in one of the states RX_ON or BUSY_RX state. The end of the ED measurement is indicated by an interrupt IRQ_4 (CCA_ED_READY). An automated ED measurement is started if an SHR is detected. The end of the automated measurement is not signaled by an interrupt. The measurement result is stored after tTR26 = 140 µs (128 µs measurement duration and processing delay) in register 0x07 (PHY_ED_LEVEL). Thus by using Basic Operating Mode, a valid ED value from the currently received frame is accessible 108 µs after IRQ_2 (RX_START) and remains valid until a new RX_START interrupt is generated by the next incoming frame or until another ED measurement is initiated. By using the Extended Operating Mode, it is recommended to mask IRQ_2 (RX_START), thus the interrupt cannot be used as timing reference. A successful frame reception is signalized by interrupt IRQ_3 (TRX_END). The minimum time span between a TRX_END interrupt and a following SFD detection is t TR27 = 9 6 µs due to the length of the SHR. Including the ED measurement time, the ED value needs to be read within 224 µs after the TRX_END interrupt; otherwise, it could be overwritten by the result of the next measurement cycle. This is important for time critical applications or if interrupt IRQ_2 (RX_START) is not used to indicate the reception of a frame. Note, it is not recommended to manually initiate an ED measurement when using the Extended Operating Mode. The values of the register 0x07 (PHY_ED_LEVEL) are: Table 8-7. Register Bit PHY_ED_LEVEL Interpretation Description Reset value ED measurement result of the last ED measurement PHY_ED_LEVEL 0xFF 0x00.... 0x54 91 8111A–AVR–05/08 8.4.3 Data Interpretation The PHY_ED_LEVEL is an 8-bit register. The ED value of the AT86RF231 has a valid range from 0x00 to 0x54 with a resolution of 1 dB. All other values do not occur; a value of 0xFF indicates the reset value. A value of PHY_ED_LEVEL = 0 indicates that the measured energy is less than -90 dBm (see parameter 12.7.16 RSSI_BASE_VAL, Section 12.7 “Receiver Characteristics” on page 160). Due to environmental conditions (temperature, voltage, semiconductor parameters, etc.) the calculated ED value has a maximum tolerance of ±5 dB, this is to be considered as constant offset over the measurement range. An ED value of 0 indicates an RF input power of PRF ≤ -90 dBm. For an ED value in the range of 0 to 84, the RF input power can be calculated as follows: PRF = -90 + ED [dBm] Figure 8-5. 10 0 Receiver Input Power PRF [dBm] -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 0 Mapping between Received Input Power and ED Value Measured Ideal 10 20 30 40 50 60 70 80 90 PHY_ED_LEVEL (register 0x07) 8.4.4 Interrupt Handling Interrupt IRQ_4 (CCA_ED_READY) is issued at the end of a manually initiated ED measurement. Note that an ED request should only be initiated in receive states. Otherwise the radio transceiver generates an IRQ_4 (CCA_ED_READY); however no ED measurement was performed. 92 AT86RF231 8111A–AVR–05/08 AT86RF231 8.4.5 Register Description Register 0x07 (PHY_ED_LEVEL): The ED_LEVEL register contains the result of an ED measurement. Bit +0x07 Read/Write Reset Value R 1 R 1 R 1 7 6 5 4 3 2 1 0 ED_LEVEL R 1 R 1 R 1 ED_LEVEL[7:0] R 1 R 1 • Bit [7:0] - ED_LEVEL The minimum ED value (ED_LEVEL = 0) indicates receiver power less than or equal to RSSI_BASE_VAL. The range is 84 dB with a resolution of 1 dB and an absolute accuracy of ±5 dB. A manual ED measurement can be initiated by a write access to the register. A value 0xFF signals that a measurement has never been started yet (reset value). The measurement duration is 8 symbol periods (128 µs) for a data rate of 250 kb/s. For High Data Rate Modes the automated measurement duration is reduced to 32 µs, refer to Section 11.3 “High Data Rate Modes” on page 137. For manually initiated ED measurements in these modes the measurement period is still 128 µs as long as the receiver is in RX_ON state. A value other than 0xFF indicates the result of the last ED measurement. 93 8111A–AVR–05/08 8.5 Clear Channel Assessment (CCA) The main features of the Clear Channel Assessment (CCA) module are: • All 4 modes are available as defined by IEEE 802.15.4-2006 in section 6.9.9 • Adjustable threshold for energy detection algorithm 8.5.1 Overview A CCA measurement is used to detect a clear channel. Four modes are specified by IEEE 802.15.4 - 2006: Table 8-8. CCA Mode 1 2 CCA Mode Overview Description Energy above threshold. CCA shall report a busy medium upon detecting any energy above the ED threshold. Carrier sense only. CCA shall report a busy medium only upon the detection of a signal with the modulation and spreading characteristics of an IEEE 802.15.4 compliant signal. The signal strength may be above or below the ED threshold. Carrier sense with energy above threshold. CCA shall report a busy medium using a logical combination of 0, 3 – Detection of a signal with the modulation and spreading characteristics of this standard and – Energy above the ED threshold. Where the logical operator may be configured as either OR (mode 0) or AND (mode 3). 8.5.2 Configuration and Request The CCA modes are configurable via register 0x08 (PHY_CC_CCA). Using the Basic Operating Mode, a CCA request can be initiated manually by setting CCA_REQUEST = 1 (register 0x08, PHY_CC_CCA), if the AT86RF231 is in any RX state. The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). The CCA evaluation is done over eight symbol periods and the result is accessible tTR28 = 140 µs (128 µs measurement duration and processing delay) after the request. The end of a manually initiated CCA measurement is indicated by an interrupt IRQ_4 (CCA_ED_READY). The sub-register CCA_ED_THRES of register 0x09 (CCA_THRES) defines the received power threshold of the " Energy above threshold " algorithm. The threshold is calculated by RSSI_BASE_VAL + 2 * CCA_ED_THRES [dBm]. Any received power above this level is interpreted as a busy channel. Note, it is not recommended to manually initiate a CCA measurement when using the Extended Operating Mode. 94 AT86RF231 8111A–AVR–05/08 AT86RF231 8.5.3 Data Interpretation The current channel status (CCA_STATUS) and the CCA completion status (CCA_DONE) are accessible in register 0x01 (TRX_STATUS). Note, register bits CCA_DONE and CCA_STATUS are cleared in response to a CCA_REQUEST. The completion of a measurement cycle is indicated by CCA_DONE = 1. If the radio transceiver detected no signal (idle channel) during the measurement cycle, the CCA_STATUS bit is set to 1. When using the "ene rg y above th re shold" algorith m, any received power abov e CCA_ED_THRES level is interpreted as a busy channel. The "carrier sense" algorithm reports a busy channel when detecting an IEEE 802.15.4 signal above the RSSI_BASE_VAL (see parameter 12.7.16). The radio transceiver is also able to detect signals below this value, but the detection probability decreases with the signal power. It is almost zero at the radio transceivers sensitivity level (see parameter 12.7.1). 8.5.4 Interrupt Handling Interrupt IRQ_4 (CCA_ED_READY) is issued at the end of a manually initiated CCA measurement. Notes • A CCA request should only be initiated in Basic Operating Mode receive states. Otherwise the radio transceiver generates an IRQ_4 (CCA_ED_READY) and sets the register bit CCA_DONE = 1, even though no CCA measurement was performed. • Requesting a CCA measurement in BUSY_RX state and during an ED measurement, an IRQ_4 (CCA_ED_READY) could be issued immediately after the request. If in this case register bit CCA_DONE = 0, an additional interrupt CCA_ED_READY is issued after finishing the CCA measurement and register bit CCA_DONE is set to 1. 8.5.5 Measurement Time The response time for a manually initiated CCA measurement depends on the receiver state. In RX_ON state the CCA measurement is done over eight symbol periods and the result is accessible 140 µs after the request (see above). In BUSY_RX state the CCA measurement duration depends on the CCA Mode and the CCA request relative to the reception of an SHR. The end of the CCA measurement is indicated by an IRQ_4 (CCA_ED_READY). The variation of a CCA measurement period in BUSY_RX state is described in Table 8-9 on page 95. Table 8-9. CCA Mode 1 CCA Measurement Period and Access in BUSY_RX state Request within ED measurement(1) Energy above threshold. CCA result is available after finishing automated ED measurement period. CCA result is immediately available after request. Request after ED measurement 2 Carrier sense only. CCA result is immediately available after request. 95 8111A–AVR–05/08 Table 8-9. 3 CCA Measurement Period and Access in BUSY_RX state Carrier sense with Energy above threshold (AND). CCA result is available after finishing automated ED measurement period. CCA result is immediately available after request. 0 Carrier sense with Energy above threshold (OR). CCA result is available after finishing automated ED measurement period CCA result is immediately available after request. Note: 1. After receiving the SHR an automated ED measurement is started with a length of 8 symbol periods (PSDU rate 250 kb/s), refer to Section 8.4 “Energy Detection (ED)” on page 91. This automated ED measurement must be finished to provide a result for the CCA measurement. Only one automated ED measurement per frame is performed. It is recommended to perform CCA measurements in RX_ON state only. To avoid switching accidentally to BUSY_RX state the SHR detection can be disabled by setting register bit RX_PDT_DIS (register 0x15, RX_SYN), refer to Section 9.1 “Receiver (RX)” on page 101. The receiver remains in RX_ON state to perform a CCA measurement until the register bit RX_PDT_DIS is set back to continue the frame reception. In this case the CCA measurement duration is 8 symbol periods. 96 AT86RF231 8111A–AVR–05/08 AT86RF231 8.5.6 Register Description Register 0x01 (TRX_STATUS): Two register bits of register 0x01 (TRX_STATUS) signal the status of the CCA measurement. Bit +0x01 Read/Write Reset Value 7 CCA_DONE R 0 6 CCA_STATUS R 0 5 Reserved R 0 R 0 R 0 4 3 2 TRX_STATUS R 0 R 0 R 0 1 0 TRX_STATUS • Bit 7 - CCA_DONE This register indicates if a CCA request is completed. This is also indicated by an interrupt IRQ_4 (CCA_ED_READY). Note, register bit CCA_DONE is cleared in response to a CCA_REQUEST. Table 8-10. Register Bit CCA_DONE CCA Algorithm Status Value 0 1 State Description CCA calculation not finished CCA calculation finished • Bit 6 - CCA_STATUS After a CCA request is completed the result of the CCA measurement is available in register bit CCA_STATUS. Note, register bit CCA_STATUS is cleared in response to a CCA_REQUEST. Table 8-11. Register Bit CCA_STATUS CCA Status Result Value 0 1 State Description Channel indicated as busy Channel indicated as idle • Bit 5 - Reserved • Bit [4:0] - TRX_STATUS Refer to Section 7.1.5 “Register Description” on page 44 and Section 7.2.7 “Register Description - Control Registers” on page 68. Register 0x08 (PHY_CC_CCA): This register is provided to initiate and control a CCA measurement. Bit +0x08 Read/Write Reset Value 7 CCA_REQUEST W 0 R/W 0 6 CCA_MODE R/W 1 R/W 0 R/W 1 5 4 3 2 CHANEL R/W 0 R/W 1 R/W 1 1 0 PHY_CC_CCA • Bit 7 - CCA_REQUEST A manual CCA measurement is initiated with setting CCA_REQUEST = 1. The end of the CCA measurement is indicated by interrupt IRQ_4 (CCA_ED_READY). Register bits CCA_DONE and CCA_STATUS (register 0x01, TRX_STATUS) are updated after a CCA_REQUEST. The 97 8111A–AVR–05/08 register bit is automatically cleared after requesting a CCA measurement with CCA_REQUEST = 1. • Bit [6:5] - CCA_MODE The CCA mode can be selected using register bits CCA_MODE. Table 8-12. Register Bit CCA_MODE CCA Status Result Value 0 1 2 3 State Description Mode 3a, Carrier sense OR energy above threshold Mode 1, Energy above threshold Mode 2, Carrier sense only Mode 3b, Carrier sense AND energy above threshold Note that IEEE 802.15.4-2006 CCA Mode 3 defines the logical combination of CCA Mode 1 and 2 with the logical operators AND or OR. This can be selected with: • CCA_MODE = 0 • CCA_MODE = 3 for logical operation OR, and for logical operation AND. • Bit [4:0] - CHANNEL Refer to Section 9.7 “Frequency Synthesizer (PLL)” on page 121. Register 0x09 (CCA_THRES): This register sets the ED threshold level for CCA. Bit +0x09 Read/Write Reset Value R/W 1 R/W 1 7 6 Reserved R/W 0 R/W 0 R/W 0 5 4 3 2 CCA_ED_THRES R/W 1 R/W 1 R/W 1 1 0 CCA_THRES • Bit [7:5] - Reserved • Bit [4:0] - CCA_ED_THRES The CCA Mode 1 request indicates a busy channel if the measured received power is above RSSI_BASE_VAL + 2 * CCA_ED_THRES [dBm]. CCA Modes 0 and 3 are logical related to this result. 98 AT86RF231 8111A–AVR–05/08 AT86RF231 8.6 Link Quality Indication (LQI) According to IEEE 802.15.4, the LQI measurement is a characterization of the strength and/or quality of a received packet. The measurement may be implemented using receiver ED, a signal-to-noise ratio estimation, or a combination of these methods. The use of the LQI result by the network or application layers is not specified in this standard. LQI values shall be an integer ranging from 0x00 to 0xFF. The minimum and maximum LQI values (0x00 and 0xFF) should be associated with the lowest and highest quality compliant signals, respectively, and LQI values in between should be uniformly distributed between these two limits. 8.6.1 Overview The LQI measurement of the AT86RF231 is implemented as a measure of the link quality which can be described with the packet error rate (PER) for this link. An LQI value can be associated with an expected packet error rate. The PER is the ratio of erroneous received frames to the total number of received frames. A PER of zero indicates no frame error, whereas at a PER of one no frame was received correctly. The radio transceiver uses correlation results of multiple symbols within a frame to determine the LQI value. This is done for each received frame. The minimum frame length for a valid LQI value is two octets PSDU. LQI values are integers ranging from 0 to 255. As an example, Figure 8-6 on page 99 shows the conditional packet error when receiving a certain LQI value. Figure 8-6. 1 0.9 0.8 0.7 0.6 Conditional Packet Error Rate versus LQI PER 0.5 0.4 0.3 0.2 0.1 0 0 50 100 150 200 250 LQI The values are taken from received frames of PSDU length of 20 octets on transmission channels with reasonable low multipath delay spreads. If the transmission channel characteristic has higher multipath delay spread than assumed in the example, the PER is slightly higher for a cer99 8111A–AVR–05/08 tain LQI value. Since the packet error rate is a statistical value, the PER shown in Section 8-6 “Conditional Packet Error Rate versus LQI” on page 99 is based on a huge number of transactions. A reliable estimation of the packet error rate cannot be based on a single or a small number of LQI values. 8.6.2 Request an LQI Measurement The LQI byte can be obtained after a frame has been received by the radio transceiver. One additional byte is automatically attached to the received frame containing the LQI value. This information can also be read via Frame Buffer read access, see Section 6.2.2 “Frame Buffer Access Mode” on page 20. The LQI byte can be read after IRQ_3 (TRX_END) interrupt. Data Interpretation According to IEEE 802.15.4 a low LQI value is associated with low signal strength and/or high signal distortions. Signal distortions are mainly caused by interference signals and/or multipath propagation. High LQI values indicate a sufficient high signal power and low signal distortions. Note, the received signal power as indicated by received signal strength indication (RSSI) value or energy detection (ED) value of the AT86RF231 do not characterize the signal quality and the ability to decode a signal. As an example, a received signal with an input power of about 6 dB above the receiver sensitivity likely results in a LQI value close to 255 for radio channels with very low signal distortions. For higher signal power the LQI value becomes independent of the actual signal strength. This is because the packet error rate for these scenarios tends towards zero and further increased signal strength, i.e. increasing the transmission power does not decrease the error rate any further. In this case RSSI or ED can be used to evaluate the signal strength and the link margin. ZigBee networks often require the identification of the "best" routing between two nodes. Both, the LQI and the RSSI/ED can be used for this, dependent on the optimization criteria. If a low packet error rate (corresponding to high throughput) is the optimization criteria then the LQI value should be taken into consideration. If a low transmission power or the link margin is the optimization criteria then the RSSI/ED value is also helpful. Combinations of LQI, RSSI and ED are possible for routing decisions. As a rule of thumb RSSI and ED values are useful to differentiate between links with high LQI values. Transmission links with low LQI values should be discarded for routing decisions even if the RSSI/ED values are high. This is because RSSI/ED does not say anything about the possibility to decode a signal. It is only an information about the received signal strength whereas the source can be an interferer. 8.6.3 100 AT86RF231 8111A–AVR–05/08 AT86RF231 9. Module Description 9.1 9.1.1 Receiver (RX) Overview The AT86RF231 receiver is split into an analog radio front end and a digital base band processor (RX BBP), see Figure 9-1 on page 101. Figure 9-1. Receiver Block Diagram LO Analog Domain Frame Buffer Digital Domain RFP LNA RFN RSSI µC I/F PPF BPF Limiter ADC RX BBP SPI SPI I/F AGC Control, Registers The differential RF signal is amplified by a low noise amplifier (LNA), filtered (PPF) and down converted to an intermediate frequency by a mixer. Channel selectivity is performed using an integrated band pass filter (BPF). A limiting amplifier (Limiter) provides sufficient gain to overcome the DC offset of the succeeding analog-to-digital converter (ADC) and generates a digital RSSI signal. The ADC output signal is sampled and processed further by the digital base band receiver (RX BBP). The RX BBP performs additional signal filtering and signal synchronization. The frequency offset of each frame is calculated by the synchronization unit and is used during the remaining receive process to correct the offset. The receiver is designed to handle frequency and symbol rate deviations up to ±120 ppm, caused by combined receiver and transmitter deviations. For details refer to Section 12.5 “General RF Specifications” on page 158 parameter 12.5.8. Finally the signal is demodulated and the data are stored in the Frame Buffer. In Basic Operating Mode, refer to Section 7.1 “Basic Operating Mode” on page 33, the reception of a frame is indicated by an interrupt IRQ_2 (RX_START). Accordingly its end is signalized by an interrupt IRQ_3 (TRX_END). Based on the quality of the received signal a link quality indicator (LQI) is calculated and appended to the frame, refer to Section 8.6 “Link Quality Indication (LQI)” on page 99. Additional signal processing is applied to the frame data to provide further status information like ED value (register 0x07, ED_LEVEL) and FCS correctness (register 0x06, PHY_RSSI). Beyond these features the Extended Operating Mode of the AT86RF231 supports address filtering and pending data indication. For details refer to Section 7.2 “Extended Operating Mode” on page 47. 101 8111A–AVR–05/08 9.1.2 Frame Receive Procedure The frame receive procedure including the radio transceiver setup for reception and reading PSDU data from the Frame Buffer is described in Section 10.1 “Frame Receive Procedure” on page 126. Configuration In Basic Operating Mode the receiver is enabled by writing command RX_ON to register bits TRX_CMD (register 0x02, TRX_STATE) in states TRX_OFF or PLL_ON. Similarly in Extended Operating Mode, the receiver is enabled for RX_AACK operation from states TRX_OFF or PLL_ON by writing the command RX_AACK_ON. There is no additional configuration required to receive IEEE 802.15.4 compliant frames when using the Basic Operating Mode. However, the frame reception in the Extended Operating Mode requires further register configurations, for details refer to Section 7.2 “Extended Operating Mode” on page 47. The AT86RF231 receiver has an outstanding sensitivity performance of -101 dBm. At certain environmental conditions or for High Data Rate Modes, refer to Section 11.3 “High Data Rate Modes” on page 137, it may be useful to manually decrease this sensitivity. This is achieved by adjusting the synchronization header detector threshold using register bits RX_PDT_LEVEL (register 0x15, RX_SYN). Received signals with an RSSI value below the threshold do not activate the demodulation process. Furthermore, it may be useful to protect a received frame against overwriting by subsequent received frames. A Dynamic Frame Buffer Protection is enabled with register bit RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) set, see Section 11.8 “Dynamic Frame Buffer Protection” on page 154. The receiver remains in RX_ON or RX_AACK_ON state until the whole frame is read by the microcontroller, indicated by /SEL = H during the SPI Frame Receive Mode. The Frame Buffer content is only protected if the FCS is valid. A Static Frame Buffer Protection is enabled with register bit RX_PDT_DIS (register 0x15, RX_SYN) set. The receiver remains in RX_ON or RX_AACK_ON state and no further SHR is detected until the register bit RX_PDT_DIS is set back. 9.1.3 102 AT86RF231 8111A–AVR–05/08 AT86RF231 9.1.4 Register Description Register 0x15 (RX_SYN): This register controls the sensitivity threshold of the receiver. Bit +0x15 Read/Write Reset Value 7 RX_PDT_DIS R/W 0 6 5 Reserved 4 3 2 RX_PDT_LEVEL 1 0 RX_SYN R/W 0 R 0 R 0 R 0 R/W 0 R/W 0 R/W 0 • Bit 7 - RX_PDT_DIS RX_PDT_DIS = 1 prevents the reception of a frame even if the radio transceiver is in receive modes. An ongoing frame reception is not affected. This operation mode is independent of the setting of register bits RX_PDT_LEVEL. • Bit [6:4] - Reserved • Bit [3:0] - RX_ PDT_LEVEL These register bits desensitize the receiver such that frames with an RSSI level below the RX_PDT_LEVEL threshold level (if RX_PDT_LEVEL > 0) are not received. The threshold level can be calculated according to the following formula: RX_THRES = RSSI_BASE_VAL + 3 * (RX_PDT_LEVEL -1), for RX_PDT_LEVEL > 0 Examples for certain register settings are given in Table 9-1 on page 103 Table 9-1. Receiver Desensitization Threshold Level - RX_PDT_LEVEL RX Input Threshold Level RSSI_BASE_VAL + 0 * 3 Value [dBm] RSSI value not considered > -90 Value [Register] 0x0 0x1 ... 0xE 0xF > RSSI_BASE_VAL + 13 * 3 > RSSI_BASE_VAL + 14 * 3 > -51 > -48 If register bits RX_PDT_LEVEL > 0 the current consumption of the receiver in states RX_ON and RX_AACK_ON is reduced by 500 µA, refer to Section 12.8 “Current Consumption Specifications” on page 161 parameter 12.8.3. If register bits RX_PDT_LEVEL = 0 (reset value) all frames with a valid SHR and PHR are received, independently of their signal strength. 103 8111A–AVR–05/08 9.2 9.2.1 Transmitter (TX) Overview The AT86RF231 transmitter consists of a digital base band processor (TX BBP) and an analog radio front end, see Figure 9-2 on page 104. Figure 9-2. Transmitter Block Diagram µC I/F DIG3/4 Ext. RF front-end and Output Power Control Control, Registers RFP PA RFN Buf PLL – TX Modulation TX Data TX BBP SPI SPI I/F Frame Buffer Analog Domain Digital Domain The TX BBP reads the frame data from the Frame Buffer and performs the bit-to-symbol and symbol-to-chip mapping as specified by IEEE 802.15.4 in section 6.5.2. The O-QPSK modulation signal is generated and fed into the analog radio front end. The fractional-N frequency synthesizer (PLL) converts the baseband transmit signal to the RF signal, which is amplified by the power amplifier (PA). The PA output is internally connected to bidirectional differential antenna pins (RFP, RFN), so that no external antenna switch is needed. 9.2.2 Frame Transmit Procedure The frame transmit procedure including writing PSDU data in the Frame Buffer and initiating a transmission is described in Section 10.2 “Frame Transmit Procedure” on page 127, Frame Transmit Procedure. Configuration The maximum output power of the transmitter is typically +3 dBm. The output power can be configured via register bits TX_PWR (register 0x05, PHY_TX_PWR). The output power of the transmitter can be controlled over a range of 20 dB. A transmission can be started from PLL_ON or TX_ARET_ON state by a rising edge of pin SLP_TR or by writing TX_START command to register bits TRX_CMD (register 0x02, TRX_STATE). 9.2.4 TX Power Ramping To optimize the output power spectral density (PSD), the PA buffer and PA are enabled sequentially. This is illustrated by a timing example using default settings, shown in Figure 9-3 on page 105. In this example the transmission is initiated with the rising edge of pin 11 (SLP_TR). The radio transceiver state changes from PLL_ON to BUSY_TX. The modulation starts 16 µs after SLP_TR. 9.2.3 104 AT86RF231 8111A–AVR–05/08 AT86RF231 Figure 9-3. TX Power Ramping 0 2 4 6 8 10 12 14 16 18 Length [µs] TRX_STATE SLP_TR PA buffer PA Modulation PLL_ON BUSY_TX PA_BUF_LT PA_LT 1 10 1 10 01 1 When using an external RF front-end (refer to Section 11.5 “RX/TX Indicator” on page 147) it may be required to adjust the startup time of the external PA relative to the internal building blocks to optimize the overall PSD. This can be achieved using register bits PA_BUF_LT and PA_LT. 9.2.5 Register Description Register 0x05 (PHY_TX_PWR): This register controls the output power and the ramping of the transmitter. Bit +0x05 Read/Write Reset Value 7 PA_BUF_LT R/W 1 6 5 PA_LT 4 3 2 TX_PWR 1 0 PHY_TX_PWR R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 • Bit [7:6] - PA_BUF_LT These register bits control the enable lead time of the internal PA buffer relative to the enable time of the internal PA. This time is further used to derive a control signal for an external RF front-end to switch between receive and transmit, for details refer to Section 11.5. Table 9-2. Register Bits PA_BUF_LT PA Buffer Enable Time Relative to the PA Value 0 1 2 3 PA Buffer Lead Time [µs] 0 2 4 6 105 8111A–AVR–05/08 • Bit [5:4] - PA_LT These register bits control the enable lead time of the internal PA relative to the beginning of the transmitted frame. Table 9-3. Register Bits PA_LT PA Enable Time Relative to the Start of the Frame (SHR) Value 0 1 2 3 PA Lead Time [µs] 2 4 6 8 • Bit [3:0] - TX_PWR These register bits determine the TX output power of the AT86RF231. Table 9-4. Register Bits TX_PWR AT86RF231 TX Output Power Setting Value 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF TX Output Power [dBm] 3.0 2.8 2.3 1.8 1.3 0.7 0.0 -1 -2 -3 -4 -5 -7 -9 -12 -17 106 AT86RF231 8111A–AVR–05/08 AT86RF231 9.3 Frame Buffer The AT86RF231 contains a 128 byte dual port SRAM. One port is connected to the SPI interface, the other to the internal transmitter and receiver modules. For data communication, both ports are independent and simultaneously accessible. The Frame Buffer uses the address space 0x00 to 0x7F for RX and TX operation of the radio transceiver and can keep one IEEE 802.15.4 RX or one TX frame of maximum length at a time. Frame Buffer access modes are described in Section 6.6.2 “Register Description” on page 30. Frame Buffer access conflicts are indicated by an under run interrupt IRQ_6 (TRX_UR). Note that this interrupt also occurs on the attempt to write frames longer than 127 octets to the Frame Buffer. In that case the content of the Frame Buffer cannot be guaranteed. Frame Buffer access is only possible if the digital voltage regulator is turned on. This is valid in all device states except in SLEEP state. An access in P_ON state is possible if pin 17 (CLKM) provides the 1 MHz master clock. 9.3.1 Data Management Data in Frame Buffer (received data or data to be transmitted) remains valid as long as: • No new frame or other data are written into the buffer over SPI • No new frame is received (in any BUSY_RX state) • No state change into SLEEP state is made • No RESET took place By default there is no protection of the Frame Buffer against overwriting. Therefore, if a frame is received during Frame Buffer read access of a previously received frame, interrupt IRQ_6 (TRX_UR) is issued and the stored data might be overwritten. Even so, the old frame data can be read, if the SPI data rate is higher than the effective over air data rate. For a data rate of 250 kb/s a minimum SPI clock rate of 1 MHz is recommended. Finally the microcontroller should check the transferred frame data integrity by an FCS check. To protect the Frame Buffer content against being overwritten by newly incoming frames the radio transceiver state should be changed to PLL_ON state after reception. This can be achieved by writing immediately the command PLL_ON to register bits TRX_CMD (register 0x02, TRX_STATE) after receiving the frame, indicated by IRQ_3 (TRX_END). Alternatively Dynamic Frame Buffer Protection can be used to protect received frames against overwriting, for details refer to Section 11.8 “Dynamic Frame Buffer Protection” on page 154. Both procedures do not protect the Frame Buffer from overwriting by the microcontroller. In Extended Operating Mode during TX_ARET operation, see Section 7.2.4 “TX_ARET_ON Transmit with Automatic Retry and CSMA-CA Retry” on page 64, the radio transceiver switches to receive, if an acknowledgement of a previously transmitted frame was requested. During this period received frames are evaluated, but not stored in the Frame Buffer. This allows the radio transceiver to wait for an acknowledgement frame and retry the frame transmission without writing them again. A radio transceiver state change, except a transition to SLEEP state or a reset, does not affect the Frame Buffer contents. If the radio transceiver is forced into SLEEP, the Frame Buffer is powered off and the stored data gets lost. 107 8111A–AVR–05/08 9.3.2 User accessible Frame Content The AT86RF231 supports an IEEE 802.15.4 compliant frame format as shown in Figure 9-4 on page 108. AT86RF231 Frame Structure Length [octets] 4 5 6 n+3 n+5 n+6 Figure 9-4. 0 Frame Duration Preamble Sequence 4 octets / 128 µs SHR not accesible PHY generated SFD 1 PHR(1) Payload n octets / n • 32 µs (n 0), the receiver does not receive frames with an RSSI level below that threshold. Under these operating conditions the receiver current consumption is reduced by 500 µA, refer to Section 12.8 “Current Consumption Specifications” on page 161 parameter 12.8.3. A description of the settings to control the sensitivity threshold with register 0x15 (RX_SYN) can be found in Section 9.1.4 “Register Description” on page 103. Reduced Acknowledgment Timing On higher data rates the IEEE 802.15.4 compliant acknowledgment frame response time of 192 µs significantly reduces the effective data rate of the network. To minimize this influence in Extended Operating Mode RX_AACK, refer to Section 7.2.3 “RX_AACK_ON - Receive with Automatic ACK” on page 51, the acknowledgment frame response time can be reduced to 32 µs. Figure 11-9 on page 140 illustrates an example for a reception and acknowledgement of a frame with a data rate of 2000 kb/s and a PSDU length of 80 symbols. The PSDU length of the acknowledgment frame is 5 octets according to IEEE 802.15.4. 139 8111A–AVR–05/08 Figure 11-9. High Data Rate AACK Timing 0 192 512 544 704 916 time [µs] PHR AACK_ACK_TIME = 0 PSDU: 80 octets PHR SFD SFD 192 µs ACK PHR AACK_ACK_TIME = 1 PSDU: 80 octets 32 µs PHR SFD SFD ACK If register bit AACK_ACK_TIME (register 0x17, XAH_CTRL_1) is set the acknowledgment time is reduced from 192 µs to 32 µs. 11.3.6 Register Description Register 0x0C (TRX_CTRL_2): The TRX_CTRL_2 register controls the data rate setting Bit +0x0C Read/Write Reset Value 7 RX_SAFE_MODE R/W 0 6 5 4 Reserved 3 2 1 OQPSK_DATA_RATE 0 TRX_CTRL_2 R/W 0 R 0 R 0 R 0 R 0 R 0 R/W 0 • Bit 7 - RX_SAFE_MODE Refer to Section 11.8.2 “Register Description” on page 154. • Bit [6:2] - Reserved • Bit [1:0] - OQPSK_DATA_RATE A write access to these register bits sets the OQPSK PSDU data rate used by the radio transceiver. The reset value OQPSK_DATA_RATE = 0 is the PSDU data rate according to IEEE 802.15.4. Table 11-9. Register Bits OQPSK_DATA_RATE OQPSK Data Rate Value 0 1 2 3 OQPSK Data Rate 250 kb/s 500 kb/s 1000 kb/s 2000 kb/s Comment IEEE 802.15.4 compliant 140 AT86RF231 8111A–AVR–05/08 AT86RF231 Register 0x17 (XAH_CTRL_1): The XAH_CTRL_1 register is a multi-purpose control register for various RX_AACK settings. Bit +0x17 Read/Write Reset Value R/W 0 7 Reserved R 0 6 5 AACK_FLTR_RES_FT R/W 1 4 AACK_UPLD_RES_FT R/W 0 3 Reserved R 0 2 AACK_ACK_TIME R/W 0 1 AACK_PROM_MODE R/W 0 0 Reserved R 0 XAH_CTRL_1 • Bit [7:6] - Reserved • Bit 5 - AACK_FLTR_RES_FT Refer to 7.2.7 “Register Description - Control Registers” on page 68. • Bit 4 - AACK_UPLD_RES_FT Refer to Section 7.2.7 “Register Description - Control Registers” on page 68. • Bit 3 - Reserved • Bit 2 - AACK_ACK_TIME According to IEEE 802.15.4, section 7.5.6.4.2 the transmission of an acknowledgment frame shall commence 12 symbol periods (aTurnaroundTime) after the reception of the last symbol of a data or MAC command frame. This is fulfilled with the reset value of the register bit [2] (AACK_ACK_TIME). If AACK_ACK_TIME = 1 an acknowledgment frame is sent 32 µs after the reception of the last symbol of a data or MAC command frame. This may be applied to proprietary networks including networks using the High Data Rate Modes to improve the overall data throughput. • Bit 1 - AACK_PROM_MODE Refer to Section 7.2.7 “Register Description - Control Registers” on page 68. • Bit 0 - Reserved 141 8111A–AVR–05/08 11.4 Antenna Diversity The Antenna Diversity implementation is characterized by: • Improves signal path robustness between nodes • AT86RF231 self-contained antenna diversity algorithm • Direct register based antenna selection 11.4.1 Overview Due to multipath propagation effects between network nodes, the receive signal strength may vary and affect the link quality, even for small changes of the antenna location. These fading effects can result in an increased error floor or loss of the connection between devices. To improve the reliability of an RF connection between network nodes Antenna Diversity can be applied to reduce effects of multipath propagation and fading. Antenna Diversity uses two antennas to select the most reliable RF signal path. This is done by the radio transceiver during preamble field search without the need for microcontroller interaction. To ensure highly independent receive signals on both antennas, the antennas should be carefully separated from each other. If a preamble field is detected on one antenna, this antenna is selected for reception. Otherwise the search is continued on the other antenna and vice versa. Antenna Diversity can be used in Basic and Extended Operating Modes and can also be combined with other features and operating modes like High Data Rate Mode and RX/TX Indication. 11.4.2 Antenna Diversity Application Example A block diagram for an application using an antenna switch is shown in Figure 11-10 on page 142. Figure 11-10. Antenna Diversity - Block Diagram ANT0 1 DIG3 AT86RF231 2 DIG4 SW1 RFSwitch B1 Balun 3 AVSS 4 RFP 5 RFN 6 AVSS ... 9 ANT1 10 DIG2 DIG1 142 AT86RF231 8111A–AVR–05/08 AT86RF231 Generally, the Antenna Diversity algorithm is enabled with register bit ANT_DIV_EN (register 0x0D, ANT_DIV) set. In this case the control of an antenna diversity switch must be enabled by register bit ANT_EXT_SW_EN (register 0x0D, ANT_DIV). The internal connection to digital ground of the control pins pin 9 (DIG1) and pin 10 (DIG2) is disabled (refer to section 4.2), and they feed the antenna switch signal and its inverse to the differential inputs of the RF Switch (SW1). Upon reception of a frame the AT86RF231 selects one antenna during preamble field detection. The selected antenna is then indicated by register bit ANT_SEL (register 0x0D, ANT_DIV). After the frame reception is completed, the antenna selection continues searching for new frames on both antennas. However, the register bit ANT_SEL maintains its previous value (from the last received frame) until a new SHR has been found, and the selection algorithm locked into one antenna again. At this time the register bit ANT_SEL is updated again. For transmission the antenna defined by register bits ANT_CTRL (register 0x0D, ANT_DIV) is selected. If for example the same antenna is to be used for transmission as being selected for reception, the antenna must be set using register bits ANT_CTRL, based on the value read from register bit ANT_SEL. It is recommended to read register bit ANT_SEL after IRQ_2 (RX_START). The autonomous search and selection allows the use of Antenna Diversity during reception even if the microcontroller does currently not control the radio transceiver, for instance in Extended Operating Mode. A microcontroller defined selection of a certain antenna can be done by disabling the automated Antenna Diversity algorithm (ANT_DIV_EN = 0) and selecting one antenna using register bit ANT_CTRL. If the AT86RF231 is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1/DIG2 are pulled-down to digital ground. 11.4.3 Antenna Diversity Sensitivity Control Due to a different receive algorithm used by the Antenna Diversity algorithm, the correlator threshold of the receiver has to be adjusted. It is recommended to set register bits PDT_THRES (register 0x0A, RX_CTRL) to 3. 11.4.4 Register Description Register 0x0A (RX_CTRL): The RX_CTRL controls the sensitivity of the Antenna Diversity Mode Bit +0x0A Read/Write Reset Value 7 6 Reserved 5 4 3 2 PDT_THRES 1 0 RX_CTRL R/W 1 R/W 0 R/W 1 R/W 1 R/W 0 R/W 1 R/W 1 R/W 1 • Bit [7:4] - Reserved 143 8111A–AVR–05/08 • Bit [3:0] - PDT_THRES These register bits control the sensitivity of the receiver correlation unit. If the Antenna Diversity algorithm is enabled, the value shall be set to PDT_THRES = 3, otherwise it shall be set back to the reset value. Table 11-10. Receiver Sensitivity Control Register Bit PDT_THRES Value 0x7 0x3 Other Description Reset value, to be used if Antenna Diversity algorithm is disabled Recommended correlator threshold for Antenna Diversity operation Reserved Register 0x0D (ANT_DIV): The ANT_DIV register controls Antenna Diversity. Bit +0x0D Read/Write Reset Value 7 ANT_SEL R 0 R 0 6 5 Reserved R 0 R 0 4 3 ANT_DIV_EN R/W 0 2 ANT_EXT_SW_EN R/W 0 R/W 1 1 ANT_CTRL R/W 1 0 ANT_DIV • Bit 7 - ANT_SEL This register bit signals the currently selected antenna path. The selection may be based either on the last antenna diversity cycle (ANT_DIV_EN = 1) or on the content of register bits ANT_CTRL, for details refer to Section 11.4.2 “Antenna Diversity Application Example” on page 142. Table 11-11. Antenna Diversity - Antenna Status Register Bit ANT_SEL Value 0 1 Description Antenna 0 Antenna 1 • Bit [6:4] - Reserved • Bit 3 - ANT_DIV_EN If register bit ANT_DIV_EN is set, the Antenna Diversity algorithm is enabled. On reception of a frame the algorithm selects an antenna autonomously during SHR search. This selection is kept until: • A new SHR search starts • Leaving receive states • Manually programmed register bits ANT_CTRL 144 AT86RF231 8111A–AVR–05/08 AT86RF231 Table 11-12. Antenna Diversity Control Register Bit ANT_DIV_EN Value 0 1 Note: Description Antenna Diversity algorithm disabled Antenna Diversity algorithm enabled If ANT_DIV_EN = 1 register bit ANT_EXT_SW_EN shall be set to 1, too. • Bit 2 - ANT_EXT_SW_EN If enabled, pin 9 (DIG1) and pin 10 (DIG2) become output pins and provide a differential control signal for an Antenna Diversity switch. The selection of a specific antenna is done either by the automated Antenna Diversity algorithm (ANT_DIV_EN = 1), or according to register bits ANT_CTRL if Antenna Diversity algorithm is disabled. Do not enable Antenna Diversity RF switch control (ANT_EXT_SW_EN = 1) and RX Frame Time Stamping (IRQ_2_EXT_EN = 1) at the same time, see Section 11.6 “RX Frame Time Stamping” on page 150. If the register bit is set the control pins DIG1/DIG2 are activated in all radio transceiver states as long as register bit ANT_EXT_SW_EN is set. If the AT86RF231 is not in a receive or transmit state, it is recommended to disable register bit ANT_EXT_SW_EN to reduce the power consumption or avoid leakage current of an external RF switch, especially during SLEEP state. If register bit ANT_EXT_SW_EN = 0, output pins DIG1 and DIG2 are pulled-down to digital ground. Table 11-13. Antenna Diversity RF Switch Enable Register Bit ANT_EXT_SW_EN Value 0 1 Note: Description Antenna Diversity RF Switch Control disabled Antenna Diversity RF Switch Control enabled If ANT_DIV_EN = 1 register bit ANT_EXT_SW_EN shall be set to 1, too. • Bit [1:0] - ANT_CTRL These register bits provide a static control of an Antenna Diversity switch. Setting ANT_DIV_EN = 0 (Antenna Diversity disabled), this register setting defines the selected antenna. 145 8111A–AVR–05/08 Table 11-14. Antenna Diversity Switch Control Register Bit ANT_CTRL Value 0 1 Description Reserved Antenna 1 DIG1 = H DIG2 = L Antenna 0 DIG1 = L DIG2 = H Default value for ANT_EXT_SW_EN = 0. Mandatory setting for applications not using Antenna Diversity. 2 3 Note: Register values 1 and 2 are valid for ANT_EXT_SW_EN = 1. 146 AT86RF231 8111A–AVR–05/08 AT86RF231 11.5 RX/TX Indicator The main features are: • RX/TX Indicator to control an external RF Front-End • Microcontroller independent RF Front-End Control • Provide TX Timing Information 11.5.1 Overview While IEEE 802.15.4 is a low cost, low power standard, solutions supporting higher transmit output power are occasionally desirable. To simplify the control of an optional external RF frontend, a differential control pin pair can indicate that the AT86RF231 is currently in transmit mode. The control of an external RF front-end is done via digital control pins DIG3/DIG4. The function of this pin pair is enabled with register bit PA_EXT_EN (register 0x04, TRX_CTRL_1). While the transmitter is turned off pin 1 (DIG3) is set to low level and pin 2 (DIG4) to high level. If the radio transceiver starts to transmit, the two pins change the polarity. This differential pin pair can be used to control PA, LNA, and RF switches. If the AT86RF231 is not in a receive or transmit state, it is recommended to disable register bit PA_EXT_EN (register 0x04, TRX_CTRL_1) to reduce the power consumption or avoid leakage current of external RF switches and other building blocks, especially during SLEEP state. If register bits PA_EXT_EN = 0, output pins DIG3/DIG4 are pulled-down to analog ground. 11.5.2 External RF-Front End Control Using an external RF front-end including a power amplifier (PA) it may be required to adjust the setup time of the external PA relative to the internal building blocks to optimize the overall power spectral density (PSD) mask. Figure 11-11. TX Power Ramping Control for RF Front-Ends 0 2 4 6 8 10 12 14 16 18 Length [µs] TRX_STATE SLP_TR PA buffer PA Modulation DIG3 DIG4 PLL_ON BUSY_TX PA_BUF_LT PA_LT 1 10 1 1 0 0 1 1 The start-up sequence of the individual building blocks of the internal transmitter is shown in Figure 11-11 on page 147, where transmission is actually initiated by the rising edge of pin 11 (SLP_TR). The radio transceiver state changes from PLL_ON to BUSY_TX and the PLL settles 147 8111A–AVR–05/08 to the transmit frequency within 16 µs. The modulation starts 16 µs after the rising edge of SLP_TR. During this time, the PA buffer and the internal PA are enabled. The control of an external PA is done via differential pin pair DIG3/DIG4. DIG3 = H / DIG4 = L indicates that the transmission starts and can be used to enable an external PA. The timing of pins DIG3/DIG4 can be adjusted relative to the start of the frame and the activation of the internal PA buffer. This is controlled using register bits PA_BUF_LT and PA_LT. For details refer to Section 9.2.4 “TX Power Ramping” on page 104. 11.5.3 Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit +0x04 Read/Write Reset Value 7 PA_EXT_EN R/W 0 6 IRQ_2_EXT_EN R/W 0 5 TX_AUTO_CRC_ON R/W 1 4 RX_BL_CTRL R/W 0 3 SPI_CMD_MODE R/W 0 2 1 IRQ_MASK_MODE R/W 0 0 IRQ_POLARITY R/W 0 TRX_CTRL_1 • Bit 7 - PA_EXT_EN This register bit enables pin 1 (DIG3) and pin 2 (DIG4) to indicate the transmit state of the radio transceiver. Table 11-15. RF Front-End Control Pins PA_EXT_EN 0 State n/a Pin DIG3 DIG4 1 (1) Value L L H L L H Description External RF front-end control disabled TX_BUSY DIG3 DIG4 External RF front-end control enabled Other DIG3 DIG4 Note: 1. It is recommended to set PA_EXT_EN = 1 only in receive or transmit states to reduce the power consumption or avoid leakage current of external RF switches or other building blocks, especially during SLEEP state. • Bit 6 - IRQ_2_EXT_EN Refer to Section 11.6 “RX Frame Time Stamping” on page 150. • Bit 5 - TX_AUTO_CRC_ON Refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85. • Bit 4 - RX_BL_CTRL Refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152. • Bit [3:2] - SPI_CMD_MODE Refer to Section 6.3 “Radio Transceiver Status information” on page 24. 148 AT86RF231 8111A–AVR–05/08 AT86RF231 • Bit 1 - IRQ_MASK_MODE Refer to Section 6.6 “Interrupt Logic” on page 29. • Bit 0 - IRQ_POLARITY Refer to Section 6.6 “Interrupt Logic” on page 29. 149 8111A–AVR–05/08 11.6 11.6.1 RX Frame Time Stamping Overview To determine the exact timing of an incoming frame, e.g. for beaconing networks, the reception of this frame can be signaled to the microcontroller via pin 10 (DIG2). The pin turns from L to H after a detection of a valid PHR. When enabled, DIG2 is set to DIG2 = H at the same time as IRQ_2 (RX_START), even if IRQ_2 is disabled. The pin remains high for the length of the frame receive procedure, see Figure 11-3 on page 130. Figure 11-12. Timing of RX_START and DIG2 for RX Frame Time Stamping 0 128 160 192 192 + m * 32 Time [µs] Number of Octets Frame Content Preamble SFD PHR PSDU (250 kb/s) TRX_STATE DIG2 (RX Frame Time Stamp) IRQ Interrupt latency RX_ON BUSY_RX RX_ON RX IRQ_2 (RX_START) TRX_END tIRQ tIRQ Note: Timing figures refer to 12.4 “Digital Interface Timing Characteristics” on page 157. This function is enabled with register bit IRQ_2_EXT_EN (register 0x04) set. Pin 10 (DIG2) could be connected to a timer capture unit of the microcontroller. If this pin is not used for RX Frame Time Stamping it can be configured for Antenna Diversity. Otherwise this pin is pulled-down to digital ground. 150 AT86RF231 8111A–AVR–05/08 Frame on Air 4 1 1 m < 128 AT86RF231 11.6.2 Register Description Register 0x04 (TRX_CTRL_1): Register 0x04 (TRX_CTRL_1) is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit +0x04 Read/Write Reset Value 7 PA_EXT_EN R/W 0 6 IRQ_2_EXT_EN R/W 0 5 TX_AUTO_CRC_ON R/W 1 4 RX_BL_CTRL R/W 0 3 SPI_CMD_MODE R/W 0 2 1 IRQ_MASK_MODE R/W 0 0 IRQ_POLARITY R/W 0 TRX_CTRL_1 • Bit 7 - PA_EXT_EN Refer to Section 11.5 “RX/TX Indicator” on page 147. • Bit 6 - IRQ_2_EXT_EN If this register bit is set the RX Frame Time Stamping Mode is enabled. An incoming frame with a valid PHR is signaled via pin 10 (DIG2). The pin remains at high level until the end of the frame receive procedure, see Figure 11-12 on page 150. Do not enable RX Frame Time Stamping (IRQ_2_EXT_EN = 1) and Antenna Diversity (ANT_EXT_SW_EN = 1) at the same time, see Section 11.4 “Antenna Diversity” on page 142. • Bit 5 - TX_AUTO_CRC_ON Refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85. • Bit 4 - RX_BL_CTRL Refer to Section 11.7 “Frame Buffer Empty Indicator” on page 152. • Bit [3:2] - SPI_CMD_MODE Refer to Section 6.3 “Radio Transceiver Status information” on page 24. • Bit 1 - IRQ_MASK_MODE Refer to Section 6.6 “Interrupt Logic” on page 29. • Bit 0 - IRQ_POLARITY Refer to Section 6.6 “Interrupt Logic” on page 29. 151 8111A–AVR–05/08 11.7 11.7.1 Frame Buffer Empty Indicator Overview For time critical applications that want to start reading the frame data as early as possible, the Frame Buffer status can be indicated to the microcontroller through a dedicated pin. This pin indicates to the microcontroller if an access to the Frame Buffer is not possible since valid PSDU data are missing. Pin 24 (IRQ) can be configured as a Frame Buffer Empty Indicator during a Frame Buffer read access. This mode is enabled by register bit RX_BL_CTRL (register 0x04, TRX_CTRL_1). The IRQ pin turns into Frame Buffer Empty Indicator after the Frame Buffer read access command, see note (1) in Figure 11-13 on page 152, has been transferred on the SPI bus until the Frame Buffer read procedure has finished indicated by /SEL = H, see note (4). Figure 11-13. Timing Diagram of Frame Buffer Empty Indicator /SEL SCLK MOSI MISO IRQ Notes Command XX Command XX XX XX XX XX Command XX PHY_STATUS IRQ_STATUS PHY_STATUS PHR[7:0] PSDU[7:0] PSDU[7:0] PSDU[7:0] LQI[7:0] PHY_STATUS IRQ_STATUS Frame Buffer Empty Indicator IRQ_2 (RX_START) tTR15 IRQ_3 (TRX_END) (1) (2) (3) (4) The microcontroller has to observe the IRQ pin during the Frame Buffer read procedure. A Frame Buffer read access can proceed as long as pin IRQ = L, see note (2). Pin IRQ = H indicates that the Frame Buffer is currently not ready for another SPI cycle, note (3), and thus the Frame Buffer read procedure has to wait for valid data accordingly. The access indicator pin 24 (IRQ) shows a valid access signal (either access is allowed or denied) not before tTR15 = 450 nsec after the rising edge of last SCLK clock of the Frame Buffer read command byte. After finishing the SPI frame receive procedure, and the SPI has been released by /SEL = H, note (4), pending interrupts are indicated immediately by pin IRQ. During all other SPI accesses, except during a SPI frame receive procedure with RX_BL_CTRL = 1, pin IRQ only indicates interrupts. If a receive error occurs during the Frame Buffer read access the Frame Buffer Empty Indicator locks on 'empty' (pin IRQ = H) too. To prevent possible deadlocks, the microcontroller should impose a timeout counter that checks whether the Frame Buffer Empty Indicator remains logic high for more than 64 µs. Presuming a PHY data rate of 250 kb/s a new byte must have been arrived at the frame buffer during that period. If not, the Frame Buffer read access should be aborted. 152 AT86RF231 8111A–AVR–05/08 AT86RF231 11.7.2 Register Description Register 0x04 (TRX_CTRL_1): The TRX_CTRL_1 register is a multi purpose register to control various operating modes and settings of the radio transceiver. Bit +0x04 Read/Write Reset Value 7 PA_EXT_EN R/W 0 6 IRQ_2_EXT_EN R/W 0 5 TX_AUTO_CRC_ON R/W 1 4 RX_BL_CTRL R/W 0 3 SPI_CMD_MODE R/W 0 2 1 IRQ_MASK_MODE R/W 0 0 IRQ_POLARITY R/W 0 TRX_CTRL_1 • Bit 7 - PA_EXT_EN Refer to Section 11.5 “RX/TX Indicator” on page 147. • Bit 6 - IRQ_2_EXT_EN Refer to Section 11.6 “RX Frame Time Stamping” on page 150. • Bit 5 - TX_AUTO_CRC_ON Refer to Section 8.2 “Frame Check Sequence (FCS)” on page 85. • Bit 4 - RX_BL_CTRL If this register bit is set the Frame Buffer Empty Indicator is enabled. After sending a Frame Buffer read command, refer to Section 6.2 “SPI Protocol” on page 19, pin 24 (IRQ) indicates to the microcontroller that an access to the Frame Buffer is not possible since valid PSDU data are missing. Pin IRQ does not indicate any interrupts during this time. Table 11-16. Frame Buffer Empty Indicator Register Bit RX_BL_CTRL Value 0 1 Description Frame Buffer Empty Indicator disabled Frame Buffer Empty Indicator enabled • Bit [3:2] - SPI_CMD_MODE Refer to Section 6.3 “Radio Transceiver Status information” on page 24. • Bit 1 - IRQ_MASK_MODE Refer to Section 6.6 “Interrupt Logic” on page 29. • Bit 0 - IRQ_POLARITY Refer to Section 6.6 “Interrupt Logic” on page 29. 153 8111A–AVR–05/08 11.8 11.8.1 Dynamic Frame Buffer Protection Overview The AT86RF231 continues the reception of incoming frames as long as it is in any receive state. When a frame was successfully received and stored into the Frame Buffer, the following frame will overwrite the Frame Buffer content again. To relax the timing requirements for a Frame Buffer read access the Dynamic Frame Buffer Protection prevents that a new valid frame passes to the Frame Buffer until a Frame Buffer read access has ended (indicated by /SEL = H, refer to Section 6.2 “SPI Protocol” on page 19). A received frame is automatically protected against overwriting: • in Basic Operating Mode, if its FCS is valid • in Extended Operating Mode, if an IRQ_3 (TRX_END) is generated The Dynamic Frame Buffer Protection is enabled, if register bit RX_SAFE_MODE (register 0x0C, TRX_CTRL_2) is set and the transceiver state is RX_ON or RX_AACK_ON. Note that Dynamic Frame Buffer Protection only prevents write accesses from the air interface not from the SPI interface. A Frame Buffer or SRAM write access may still modify the Frame Buffer content. 11.8.2 Register Description Register 0x0C (TRX_CTRL_2): The TRX_CTRL_2 register is a multi purpose register to control various settings of the radio transceiver. Bit +0x0C Read/Write Reset Value 7 RX_SAFE_MODE R/W 0 6 5 4 Reserved 3 2 1 OQPSK_DATA_RATE 0 TRX_CTRL_2 R/W 0 R 0 R 1 R 0 R 0 R 0 R/W 0 • Bit 7 - RX_SAFE_MODE If this bit is set Dynamic Frame Buffer Protection is enabled: Table 11-17. Dynamic Frame Buffer Protection Mode Register Bit RX_SAFE_MODE (1) Value 0 1 Description Disable Dynamic Frame Buffer Protection Enable Dynamic Frame Buffer Protection Note: 1. Dynamic Frame Buffer Protection is released with the rising edge of pin23 (/SEL) of a Frame Buffer read access, see Section 6.2.2 “Frame Buffer Access Mode” on page 20, or radio transceiver state changing from RX_ON or RX_AACK_ON to another state. This operation mode is independent of the setting of register bits RX_PDT_LEVEL, refer to Section 9.1.3 “Configuration” on page 102. • Bit [6:2] - Reserved 154 AT86RF231 8111A–AVR–05/08 AT86RF231 • Bit [1:0] - OQPSK_DATA_RATE Refer to Section 11.3 “High Data Rate Modes” on page 137. 11.9 11.9.1 Configurable Start-Of-Frame Delimiter Overview The SFD is a field indicating the end of the SHR and the start of the packet data. The length of the SFD is 1 octet (2 symbols). This octet is used for byte synchronization only and is not included in the Frame Buffer. The value of the SFD could be changed if it is needed to operate non IEEE 802.15.4 compliant networks. An IEEE 802.15.4 compliant network node does not synchronize to frames with a different SFD value. Due to the way the SHR is formed, it is not recommended to set the low-order 4 bits to 0. 11.9.2 Register Description Register 0x0B (SFD_VALUE): This register contains the one octet start-of-frame delimiter (SFD) to synchronize to a received frame. Bit +0x0B Read/Write Reset Value R/W 1 R/W 0 R/W 1 7 6 5 4 3 2 1 0 SFD_VALUE R/W 1 R/W 1 R/W 1 SFD_VALUE[7:0] R/W 0 R/W 0 • Bit [7:0] - SFD_VALUE For compliant IEEE 802.15.4 networks set SFD_VALUE = 0xA7, as specified by [1] and [2]. This is the default value of the register. To establish non IEEE 802.15.4 compliant networks the SFD value can be changed to any other value. If enabled an IRQ_2 (RX_START) is issued only if the received SFD matches the register content of register SFD_VALUE and a valid PHR is received. 155 8111A–AVR–05/08 12. Electrical Characteristics 12.1 Absolute Maximum Ratings Note: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. . Table 12-1. No. 12.1.1 12.1.2 Absolute Maximum Ratings Parameter Storage temperature Lead temperature T = 10s, (soldering profile compliant with IPC/JEDEC J STD 020B) Compl. to [3], Compl. to [4] 4 750 +14 -0.3 -0.3 VDD+0.3 2.0 Condition Min. -50 Typ. Max 150 260 Units °C °C Symbol TSTOR TLEAD 12.1.3 12.1.4 12.1.5 12.1.6 VESD PRF VDIG VANA ESD robustness Input RF level Voltage on all pins (except pins 4, 5, 13, 14, 29) Voltage on pins 4, 5, 13, 14, 29 kV V dBm V V 12.2 Recommended Operating Range Recommended Operating Range Parameter Operating temperature range Supply voltage Supply voltage (on pins 13, 14, 29) Voltage on pins 15, 28(2) External voltage supply(1) Condition Min. -40 1.8 1.7 3.0 1.8 Typ. Max +85 3.6 1.9 Units °C V V Table 12-2. No. 12.2.1 12.2.2 12.2.3 Notes: Symbol TOP VDD VDD1.8 1. Register 0x10 (VREG_CTRL) needs to be programmed to disable internal voltage regulators and supply blocks by an external 1.8V supply, refer to section 9.4. 2. Even if an implementation uses the external 1.8V voltage supply VDD1.8 it is required to connect VDD. 156 AT86RF231 8111A–AVR–05/08 AT86RF231 12.3 Digital Pin Characteristics .Test Conditions: TOP = 25°C (unless otherwise stated) Table 12-3. No. 12.3.1 12.3.2 12.3.3 12.3.4 Digital Pin Characteristics Parameter High level input voltage (1) Symbol VIH VIL VOH VOL Condition Min. VDD - 0.4 Typ. Max Units V Low level input voltage(1) High level output voltage (1) 0.4 For all output driver strengths defined in TRX_CTRL_0 For all output driver strengths defined in TRX_CTRL_0 VDD - 0.4 0.4 V V V Low level output voltage(1) Note: 1. The capacitive load should not be larger than 50 pF for all I/Os when using the default driver strength settings, refer to Section 1.3.1 “Driver Strength Settings” on page 7. Generally, large load capacitances increase the overall current consumption. 12.4 Digital Interface Timing Characteristics Test Conditions: TOP = 25°C, VDD = 3.0V, CL = 50 pF (unless otherwise stated). Digital Interface Timing Characteristics Parameter SCLK frequency SCLK frequency /SEL low to MISO active SCLK to MISO out MOSI setup time MOSI hold time LSB last byte to MSB next byte /SEL high to MISO tri state SLP_TR pulse width SCLK to /SEL high TX start trigger SPI Read/Write, standard SRAM and Frame Buffer access modes, Idle time between consecutive SPI accesses Fast SRAM read/write access mode, refer to Section 11.1.5, Idle time between consecutive SPI accesses 62.5 250 data hold time 25 10 10 250 (2) Table 12-4. No. 12.4.1 12.4.2 12.4.3 12.4.4 12.4.5 12.4.6 12.4.7 12.4.8 12.4.9 12.4.10 Symbol fsync fasync t1 t2 t3 t4 t5 t6 t7 t8 Condition synchronous operation asynchronous operation Min. Typ. Max 8 7.5 180 Units MHz MHz ns ns ns ns ns 10 Note(1) ns ns ns 12.4.11 t8 SCLK to /SEL high 500 ns 12.4.12 12.4.13 12.4.14 t9 t10 t11 Last SCLK to /SEL high Reset pulse width SPI access latency after reset ≥ 10 clock cycles at 16 MHz ≥ 10 clock cycles at 16 MHz 250 625 625 9 ns ns ns 157 8111A–AVR–05/08 Table 12-4. 12.4.15 12.4.16 12.4.17 Digital Interface Timing Characteristics (Continued) t12 tIRQ fCLKM AES core cycle time Interrupt event latency Clock frequency at pin 17 (CLKM) Relative to the event to be indicated Configurable in register 0x03 (TRX_CTRL_0) 24 9 0 1 2 4 8 16 250 62.5 µs µs MHz MHz MHz MHz MHz MHz kHz kHz Notes: 1. Maximum pulse width less than (TX frame length + 16 µs) 2. For Fast SRAM read/write accesses on address space 0x82 - 0x94 the time t5 (Min.) increases to 450 ns. 12.5 General RF Specifications Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2.45 GHz, TOP = 25°C, Measurement setup see Figure 5-1 on page 12. Table 12-5. No. 12.5.1 12.5.2 12.5.3 12.5.4 General RF Specifications Parameter Frequency range Channel spacing Header bit rate (SHR, PHR) PSDU bit rate Condition As specified in [1], [2] As specified in [1], [2] As specified in [1], [2] As specified in [1], [2] OQPSK_DATA_RATE = 1 OQPSK_DATA_RATE = 2 OQPSK_DATA_RATE = 3 As specified in [1], [2] Reference oscillator Leaving SLEEP state to clock available at pin 17 (CLKM) PSDU bit rate 250 kb/s PSDU bit rate 500 kb/s PSDU bit rate 1000 kb/s PSDU bit rate 2000 kb/s -60(1) -40 -40 -30 2.8 Min. 2405 5 250 250 500 1000 2000 2000 16 215 1000 +60 +40 +40 +30 Typ. Max 2480 Units MHz MHz kb/s kb/s kb/s kb/s kb/s kchip/s MHz µs ppm ppm ppm ppm MHz Symbol fRF fCH fHDR fPSDU 12.5.5 12.5.6 12.5.7 12.5.8 fCHIP fCLK fXTAL Chip rate Crystal oscillator frequency Reference oscillator settling time Symbol rate deviation Reference frequency accuracy for correct functionality 12.5.9 Note: B20dB 20 dB bandwidth 1. A reference frequency accuracy of ±40 ppm is required by [1], [2]. 158 AT86RF231 8111A–AVR–05/08 AT86RF231 12.6 Transmitter Characteristics Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2.45 GHz, TOP = 25°C, Measurement setup see Figure 5-1 on page 12. Table 12-6. No. 12.6.1 Transmitter Characteristics Parameter TX Output power Condition Maximum configurable TX output power value Register bit TX_PWR = 0 16 steps, configurable in register 0x05 (PHY_TX_PWR) Min. 0 Typ. +3 Max +6 Units dBm Symbol PTX 12.6.2 12.6.3 12.6.4 12.6.5 12.6.6 PRANGE PACC Output power range Output power tolerance TX Return loss EVM 20 ±3 dB dB dB %rms dBm dBm dBm dBm dBm dBm 100Ω differential impedance, PTX = +3 dBm 10 8 -38 -45 PHARM Harmonics 2nd harmonic 3rd harmonic Spurious Emissions 30 - ≤ 1000 MHz >1 - 12.75 GHz 1.8 - 1.9 GHz 5.15 - 5.3 GHz Complies with EN 300 328/440, FCC-CFR-47 part 15, ARIB STD-66, RSS-210 12.6.7 PSPUR -36 -30 -47 -47 159 8111A–AVR–05/08 12.7 Receiver Characteristics Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2.45 GHz, TOP = 25°C, PSDU bit rate = 250 kb/s, Measurement setup see Figure 5-1 on page 12. Table 12-7. No. 12.7.1 Receiver Characteristics Parameter Receiver sensitivity 250 kb/s 500 kb/s 1000 kb/s 2000 kb/s Antenna Diversity Condition AWGN channel, PER ≤ 1%, PSDU length 20 octets High Data Rate Modes: PSDU length 20 octets 250 kb/s, PSDU 20 octets 100Ω differential impedance Min. Typ. -101 -97 -95 -89 -99 10 6 PER ≤ 1%, PSDU length of 20 octets PER ≤ 1%, PSDU length of 20 octets, PRF = -82 dBm PER ≤ 1%, PSDU length of 20 octets, PRF = -82 dBm PER ≤ 1%, PSDU length of 20 octets, PRF = -82 dBm PER ≤ 1%, PSDU length of 20 octets, PRF = -82 dBm 10 29 35 47 47 Max Units dBm dBm dBm dBm dBm Symbol PSENS 12.7.2 12.7.3 12.7.4 12.7.5 12.7.6 12.7.7 12.7.8 12.7.9 RL NF PRXMX PACRN PACRP PAACRN PAACRP PSPUR Return loss Noise figure Maximum RX input level Adjacent channel rejection: -5 MHz Adjacent channel rejection: +5 MHz Alternate channel rejection: -10 MHz Alternate channel rejection: +10 MHz Spurious emissions: LO leakage 30 - ≤1000 MHz >1 - 12.75 GHz TX/RX carrier frequency offset 3 - order intercept point rd -71 -57 -47 Sensitivity loss < 2 dB At maximum gain Offset freq. interf. 1 = 5 MHz Offset freq. interf. 2 = 10 MHz At maximum gain Offset freq. interf. 1 = 60 MHz Offset freq. interf. 2 = 62 MHz Tolerance within gain step 81 3 Defined as RSSI_BASE_VAL PRF ≤ RSSI_BASE_VAL PRF > RSSI_BASE_VAL + 81 dB -90 0 28 -300(1) -14 +300 dBm dBm dBm kHz dBm 12.7.10 12.7.11 fRXTXOFFS IIP3 12.7.12 IIP2 2nd - order intercept point 17 dBm 12.7.13 12.7.14 12.7.15 12.7.16 12.7.17 12.7.18 Note: RSSI tolerance RSSI dynamic range RSSI resolution RSSI sensitivity Minimum RSSI value Maximum RSSI value 1. Offset equals ±120 ppm. ±5 dB dB dB dBm 160 AT86RF231 8111A–AVR–05/08 AT86RF231 12.8 Current Consumption Specifications Test Conditions (unless otherwise stated): VDD = 3.0V, fRF = 2.45 GHz, TOP = 25°C, Measurement setup see Figure 5-1 on page 12. Table 12-8. No. 12.8.1 Current Consumption Specifications Parameter Supply current transmit state Condition PTX = 3 dBm PTX = 1 dBm PTX = - 3 dBm PTX = -17 dBm (current consumption is reduced at VDD = 1.8V for each output power level) RX_ON state RX_ON state, with register setting RX_PDT_LEVEL > 0(1) PLL_ON state TRX_OFF state SLEEP state Min. Typ. 14.3 10 9 8 Max Units mA mA mA mA Symbol IBUSY_TX 12.8.2 12.8.3 12.8.4 12.8.5 12.8.6 Note: IRX_ON IPLL_ON_P IPLL_ON ITRX_OFF ISLEEP Supply current RX_ON state Supply current RX_ON state Supply current PLL_ON state Supply current TRX_OFF state Supply current SLEEP state 13.2 12.7 5.7 0.4 0.02 mA mA mA mA µA 1. Refer to Section 9.1 “Receiver (RX)” on page 101. 12.9 Crystal Parameter Requirements. Crystal Parameter Requirements Parameter Crystal frequency Load capacitance Static capacitance Series resistance 8 Condition Min. Typ. 16 14 7 100 Max Units MHz pF pF Ω Table 12-9. No. 12.9.1 12.9.2 12.9.3 12.9.4 Symbol f0 CL C0 R1 161 8111A–AVR–05/08 13. Typical Characteristics 13.1 Active Supply Current The following charts showing each a typical behavior of the AT86RF231. These figures are not tested during manufacturing. All power consumption measurements are performed with pin 17 (CLKM) disabled, unless otherwise stated. The measurement setup used for the measurements is shown in Figure 5-1 on page 12. Power consumption for the microcontroller required to program the radio transceiver is not included in the measurement results. The power consumption in SLEEP state mode is independent from CLKM master clock rate selection. The current consumption is a function of several factors such as: operating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, and ambient temperature. The dominating factors are operating voltage and ambient temperature. If possible the measurement results are not affected by current drawn from I/O pins. Register, SRAM or Frame Buffer read or write accesses are not performed during current consumption measurements. 13.1.1 TRX_OFF state Figure 13-1. Current Consumption in TRX_OFF State Current Consumption in TRX_OFF State 0.50 85 °C 25 °C 0 °C -40 °C 0.40 Current Consumption (mA) 0.30 0.20 0.10 0.00 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 EVDD (V) 162 AT86RF231 8111A–AVR–05/08 AT86RF231 13.1.2 PLL_ON state Figure 13-2. Current Consumption in PLL_ON State Current Consumption in PLL_ON State 7.0 6.5 85 °C Current Consumption (mA) 6.0 25 °C 5.5 0 °C -40 °C 5.0 4.5 4.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 EVDD (V) 13.1.3 RX_ON state Figure 13-3. Current Consumption in RX_ON State Current Consumption in RX_ON State 15.5 15.0 85 °C Current Consumption (mA) 14.5 14.0 13.5 13.0 25 °C 0 °C 12.5 12.0 -40 °C 11.5 11.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 EVDD (V) 163 8111A–AVR–05/08 13.1.4 TX_BUSY state Figure 13-4. Current Consumption in RX_BUSY State Current Consumption in RX_BUSY State 16.0 85 °C 15.0 Current Consumption (mA) 25 °C 14.0 0 °C 13.0 -40 °C 12.0 11.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 EVDD (V) 13.2 State Transition Timing Figure 13-5. Transition Time from EVDD to P_ON (CLKM available) Transition Time from EVDD to P_ON (CLKM available) 500 450 400 Start-Up Time (µs) 350 300 250 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 85 °C 25 °C 0 °C -40 °C 3.8 EVDD (V) 164 AT86RF231 8111A–AVR–05/08 AT86RF231 Figure 13-6. Transition Time from SLEEP to TRX_OFF (AWAKE_END) Transition Time from SLEEP to TRX_OFF (AWAKE_END) 500 450 State Transition Time (µs) 400 350 300 250 200 150 100 50 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 85 °C 25 °C 0 °C -40 °C EVDD (V) Figure 13-7. Transition Time from TRX_OFF to PLL_ON Transition Time from TRX_OFF to PLL_ON 140 120 85 °C 25 °C 0 °C -40 °C State Transition Time (µs) 100 80 60 40 20 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 EVDD (V) 165 8111A–AVR–05/08 14. Register Summary The AT86RF231 provides a register space of 64 8-bit registers, used to configure, control and monitor the radio transceiver. Note: All registers not mentioned within the following table are reserved for internal use and must not be overwritten. When writing to a register, any reserved bits shall be overwritten only with their reset value. Bit6 CCA_STATUS TRAC_STATUS[0] PAD_IO[0] IRQ_2_EXT_EN PA_BUF_LT[0] RND_VALUE[1] ED_LEVEL[6] CCA_MODE[1] SFD_VALUE[6] MASK_TRX_UR TRX_UR AVDD_OK XTAL_MODE[2 PART_NUM[6] VERSION_NUM[6] MAN_ID_0[6] MAN_ID_1[6] SHORT_ADDR_0[6] SHORT_ADDR_1[6] PAN_ID_0[6] PAN_ID_1[6] IEEE_ADDR_0[6] IEEE_ADDR_1[6] IEEE_ADDR_2[6] IEEE_ADDR_3[6] IEEE_ADDR_4[6] IEEE_ADDR_5[6] IEEE_ADDR_6[6] IEEE_ADDR_7[6] MAX_FRAME_RETRES[2] Bit5 TRAC_STATUS[0] PAD_IO[1] TX_AUTO_CRC_ON PA_LT[1] RND_VALUE[0] ED_LEVEL[5] CCA_MODE[0] SFD_VALUE[5] MASK_AMI AMI BATMON_OK XTAL_MODE[1 AACK_FLTR_RES_FT PART_NUM[5] VERSION_NUM[5] MAN_ID_0[5] MAN_ID_1[5] SHORT_ADDR_0[5] SHORT_ADDR_1[5] PAN_ID_0[5] PAN_ID_1[5] IEEE_ADDR_0[5] IEEE_ADDR_1[5] IEEE_ADDR_2[5] IEEE_ADDR_3[5] IEEE_ADDR_4[5] IEEE_ADDR_5[5] IEEE_ADDR_6[5] IEEE_ADDR_7[5] MAX_FRAME_RETRES[1] Bit4 TRX_STATUS[4] TRX_CMD[4] PAD_IO_CLKM[0] RX_BL_CTRL PA_LT[0] RSSI[4] ED_LEVEL[4] CHANNEL[4] SFD_VALUE[4] MASK_CCA_ED_READY CCA_ED_READY BATMON_HR XTAL_MODE[0] AACK_UPLD_RES_FT PART_NUM[4] VERSION_NUM[4] MAN_ID_0[4] MAN_ID_1[4] SHORT_ADDR_0[4] SHORT_ADDR_1[4] PAN_ID_0[4] PAN_ID_1[4] IEEE_ADDR_0[4] IEEE_ADDR_1[4] IEEE_ADDR_2[4] IEEE_ADDR_3[4] IEEE_ADDR_4[4] IEEE_ADDR_5[4] IEEE_ADDR_6[4] IEEE_ADDR_7[4] MAX_FRAME_RETRES[0] Bit3 TRX_STATUS[3] TRX_CMD[3] CLKM_SHA_SEL SPI_CMD_MODE[1] TX_PWR[3] RSSI[3] ED_LEVEL[3] CHANNEL[3] CCA_ED_THRES[3] PDT_THRES[3] SFD_VALUE[3] ANT_DIV_EN MASK_TRX_END RX_END DVREG_EXT BATMON_VTH[3] XTAL_TRIM[3] RX_PDT_LEVEL[3] PART_NUM[3] VERSION_NUM[3] MAN_ID_0[3] MAN_ID_1[3] SHORT_ADDR_0[3] SHORT_ADDR_1[3] PAN_ID_0[3] PAN_ID_1[3] IEEE_ADDR_0[3] IEEE_ADDR_1[3] IEEE_ADDR_2[3] IEEE_ADDR_3[3] IEEE_ADDR_4[3] IEEE_ADDR_5[3] IEEE_ADDR_6[3] IEEE_ADDR_7[3] MAX_CSMA_RETRES[2] Bit2 TRX_STATUS[2] TRX_CMD[2] CLKM_CTRL[2] SPI_CMD_MODE[0] TX_PWR[2] RSSI[2] ED_LEVEL[2] CHANNEL[2] CCA_ED_THRES[2] PDT_THRES[2] SFD_VALUE[2] ANT_EXT_SW_EN MASK_TRX_START RX_START DVDD_OK BATMON_VTH[2] XTAL_TRIM[2] RX_PDT_LEVEL[2] AACK_ACK_TIME PART_NUM[2] VERSION_NUM[2] MAN_ID_0[2] MAN_ID_1[2] SHORT_ADDR_0[2] SHORT_ADDR_1[2] PAN_ID_0[2] PAN_ID_1[2] IEEE_ADDR_0[2] IEEE_ADDR_1[2] IEEE_ADDR_2[2] IEEE_ADDR_3[2] IEEE_ADDR_4[2] IEEE_ADDR_5[2] IEEE_ADDR_6[2] IEEE_ADDR_7[2] MAX_CSMA_RETRES[1] Bit1 TRX_STATUS[1] TRX_CMD[1] CLKM_CTRL[1] IRQ_MASK_MODE TX_PWR[1] RSSI[1] ED_LEVEL[1] CHANNEL[1] CCA_ED_THRES[1] PDT_THRES[1] SFD_VALUE[1] OQPSK_DATA_RATE[1] ANT_CTRL[1] MASK_PLL_UNLOCK PLL_UNLOCK BATMON_VTH[1] XTAL_TRIM[1] RX_PDT_LEVEL[1] AACK_PROM_MODE PART_NUM[1] VERSION_NUM[1] MAN_ID_0[1] MAN_ID_1[1] SHORT_ADDR_0[1] SHORT_ADDR_1[1] PAN_ID_0[1] PAN_ID_1[1] IEEE_ADDR_0[1] IEEE_ADDR_1[1] IEEE_ADDR_2[1] IEEE_ADDR_3[1] IEEE_ADDR_4[1] IEEE_ADDR_5[1] IEEE_ADDR_6[1] IEEE_ADDR_7[1] MAX_CSMA_RETRES[0] Bit0 TRX_STATUS[0] TRX_CMD[0] CLKM_CTRL[0] IRQ_POLARITY TX_PWR[0] RSSI[0] ED_LEVEL[0] CHANNEL[0] CCA_ED_THRES[0] PDT_THRES[0] SFD_VALUE[0] OQPSK_DATA_RATE[0] ANT_CTRL[0] MASK_PLL_LOCK PLL_LOCK BATMON_VTH[0] XTAL_TRIM[0] RX_PDT_LEVEL[0] PART_NUM[0] VERSION_NUM[0] MAN_ID_0[0] MAN_ID_1[0] SHORT_ADDR_0[0] SHORT_ADDR_1[0] PAN_ID_0[0] PAN_ID_1[0] IEEE_ADDR_0[0] IEEE_ADDR_1[0] IEEE_ADDR_2[0] IEEE_ADDR_3[0] IEEE_ADDR_4[0] IEEE_ADDR_5[0] IEEE_ADDR_6[0] IEEE_ADDR_7[0] SLOTTED_OPERATION 122 122 25 25 25 25 76 76 76 76 76 76 76 76 76 76 76 76 68 68,140 125 103 Page 44,68,97 33,44,68 8,118, 24,30,148 105 90,136 93 97 97 140 155 154 143 30 30 111 113 116 Addr 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C Name TRX_STATUS TRX_STATE TRX_CTRL_0 TRX_CTRL_1 PHY_TX_PWR PHY_RSSI PHY_ED_LEVEL PHY_CC_CCA CCA_THRES RX_CTRL SFD_VALUE TRX_CTRL_2 ANT_DIV IRQ_MASK IRQ_STATUS VREG_CTRL BATMON XOSC_CTRL RX_SYN XAH_CTRL_1 FTN_CTRL PLL_CF PLL_DCU PART_NUM VERSION_NUM MAN_ID_0 MAN_ID_1 SHORT_ADDR_0 SHORT_ADDR_1 PAN_ID_0 PAN_ID_1 IEEE_ADDR_0 IEEE_ADDR_1 IEEE_ADDR_2 IEEE_ADDR_3 IEEE_ADDR_4 IEEE_ADDR_5 IEEE_ADDR_6 IEEE_ADDR_7 XAH_CTRL_0 Bit7 CCA_DONE TRAC_STATUS[1] PAD_IO[1] PA_EXT_EN PA_BUF_LT[1] RX_CRC_VALID ED_LEVEL[7] CCA_REQUEST SFD_VALUE[7] RX_SAFE_MODE ANT_SEL MASK_BAT_LOW BAT_LOW AVREG_EXT XTAL_MODE[3] RX_PDT_DIS FTN_START PLL_CF_START PLL_DCU_START PART_NUM[7] VERSION_NUM[7] MAN_ID_0[7] MAN_ID_1[7] SHORT_ADDR_0[7] SHORT_ADDR_1[7] PAN_ID_0[7] PAN_ID_1[7] IEEE_ADDR_0[7] IEEE_ADDR_1[7] IEEE_ADDR_2[7] IEEE_ADDR_3[7] IEEE_ADDR_4[7] IEEE_ADDR_5[7] IEEE_ADDR_6[7] IEEE_ADDR_7[7] MAX_FRAME_RETRES[3] 166 AT86RF231 8111A–AVR–05/08 AT86RF231 0x2D 0x2E 0x2F .... CSMA_SEED_0 CSMA_SEED_1 CSMA_BE CSMA_SEED_0[7] AACK_FVN_MODE[1] MAX_BE[3] CSMA_SEED_0[6] AACK_FVN_MODE[0] MAX_BE[2] CSMA_SEED_0[5] AACK_SET_PD MAX_BE[1] CSMA_SEED_0[4] AACK_DIS_ACK MAX_BE[0] CSMA_SEED_0[3] AACK_I_AM_COORD MIN_BE[3] CSMA_SEED_0[2] CSMA_SEED_1[2] MIN_BE[2] CSMA_SEED_0[1] CSMA_SEED_1[1] MIN_BE[1] CSMA_SEED_0[0] CSMA_SEED_1[0] MIN_BE[0] 68 68 68 The reset values of the AT86RF231 registers in state P_ON(1, 2, 3) are shown in Table 14-1 on page 167. Note: All reset values in Table 14-1 on page 167 are only valid after a power on reset. After a reset procedure (/RST = L) as described in Section 7.1.4.5 “Reset Procedure” on page 41 the reset values of selected registers (e.g. registers 0x01, 0x10, 0x11, 0x30) can differ from that in Table 14-1 on page 167. Table 14-1. Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F Notes: Register Summary - Reset Values Reset Value 0x00 0x00 0x00 0x19 0x20 0xC0 0x00 0xFF 0x2B 0xC7 0xB7 0xA7 0x00 0x03 0x00 0x00 Address 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Reset Value 0x00(1) 0x02(2) 0xF0 0x00 0x00 0x00 0x00 0x00 0x58 0x55 0x57 0x20 0x03 0x02 0x1F 0x00 Address 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F Reset Value 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x38 0xEA 0x42 0x53 Address 0x30 0x31 0x32 0x34 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F Reset Value 0x00(3) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x00 0x00 0x00 1. While the reset value of register 0x10 is 0x00, any practical access to the register is only possible when DVREG is active. So this register is normally always read out as 0x04. For details refer to Section 9.4 “Voltage Regulators (AVREG, DVREG)” on page 110. 2. While the reset value of register 0x11 is 0x02, any practical access to the register is only possible when BATMON is activated. So this register is normally always read out as 0x22 in P_ON state. For details refer to Section 9.5 “Battery Monitor (BATMON)” on page 113. 3. While the reset value of register 0x30 is 0x00, any practical access to the register is only possible when the radio transceiver is accessible. So the register is normally read out as: a) 0x11 after a reset in P_ON state b) 0x07 after a reset in any other state 167 8111A–AVR–05/08 15. Abbreviations AACK ACK ADC AD AGC AES ARET AVREG AWGN BATMON BBP BPF CBC CRC CCA CSMA-CA CW DVREG ECB ED ESD EVM FCF FCS FIFO FTN GPIO ISM LDO LNA LO LQI LSB MAC MFR Automatic acknowledgement Acknowledgement Analog-to-digital converter Antenna diversity Automated gain control Advanced encryption standard Automatic retransmission Voltage regulator for analog building blocks Additive White Gaussian Noise Battery monitor Base band processor Band pass filter Cipher block chaining Cyclic redundancy check Clear channel assessment Carrier sense multiple access/Collision avoidance Continuous wave Voltage regulator for digital building blocks Electronic code book Energy detection Electrostatic discharge Error vector magnitude Frame control field Frame check sequence First in first out Filter tuning network General purpose input output Industrial, scientific, and medical Low-drop output Low-noise amplifier Local oscillator Link quality indicator Least significant bit Medium access control MAC footer 168 AT86RF231 8111A–AVR–05/08 AT86RF231 MHR MISO MOSI MSB MSDU MPDU MSK O-QPSK PA PAN PCB PER PHR PHY PLL POR PPF PRBS PSDU PSD QFN RF RSSI RX SCLK /SEL SFD SHR SPI SRAM SSBF TX VCO VREG XOSC MAC header SPI Interface: Master input slave output SPI Interface: Master output slave input Most significant bit MAC service data unit MAC protocol data unit Minimum shift keying Offset - quadrature phase shift keying Power amplifier Personal area network Printed circuit board Packet error rate PHY header Physical layer Phase locked loop Power-on reset Poly-phase filter Pseudo random bit sequence PHY service data unit Power spectral mask Quad flat no-lead package Radio frequency Received signal strength indicator Receiver SPI Interface: SPI clock SPI Interface: SPI select Start-of-frame delimiter Synchronization header Serial peripheral interface Static random access memory Single side band filter Transmitter Voltage controlled oscillator Voltage regulator Crystal oscillator 169 8111A–AVR–05/08 16. Ordering Information Ordering Code AT86RF231-ZU Package QN Voltage Range 1.8V - 3.6V Temperature Range Industrial (-40° C to +85° C) Lead-free/Halogen-free Package Type QN Description 32QN2, 32 lead 5.0x5.0 mm Body, 0.50 mm Pitch, Quad Flat No-lead Package (QFN) Sawn Note: T&R quantity 4,000. Please contact your local Atmel sales office for more detailed ordering information and minimum quantities. 17. Soldering Information Recommended soldering profile is specified in IPC/JEDEC J-STD-.020C. 18. Package Thermal Properties Thermal Resistance Velocity [m/s] 0 1 2.5 Theta ja [K/W] 40.9 35.7 32.0 170 AT86RF231 8111A–AVR–05/08 AT86RF231 19. Package Drawing - 32QN2 D A A3 E Pin 1 Corner A1 A2 Top View Pin Pin 1 Corner Side View COMMON DIMENSIONS (Unit of Measure = mm) D2 SYMBOL D E MIN NOM 5.00 BSC 5.00 BSC MAX NOTE E2 e D2 E2 A L 3.20 3.20 0.80 0.0 0.0 3.30 3.30 0.90 0.02 0.65 0.20 REF 3.40 3.40 1.00 0.05 1.00 A1 A2 A3 b L e 0.30 0.40 0.50 BSC 0.50 Bottom View Notes: b 0.18 0.23 0.30 2 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation VHHD-6, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. GPC TITLE 32QN2, 32-lead 5.0 x 5.0 mm Body, 0.50 mm Pitch, Package Drawing Contact: ZJZ packagedrawings@atmel.com Quad Flat No Lead Package (QFN) Sawn 11/26/07 DRAWING NO. REV. 32QN2 A 171 8111A–AVR–05/08 20. Appendix A - Continuous Transmission Test Mode 20.1 Overview The AT86RF231 offers a Continuous Transmission Test Mode to support final application / production tests as well as certification tests. Using this test mode the radio transceiver transmits continuously a previously transferred frame (PRBS mode) or a continuous wave signal (CW mode). In CW mode two different signal frequencies per channel can be transmitted: • f1 = fCH + 0.5 MHz • f2 = fCH - 0.5 MHz Here fCH is the channel center frequency programmed by register 0x08 (PHY_CC_CCA). Note, in CW mode it is not possible to transmit an RF signal directly on the channel center frequency. PSDU data in the Frame Buffer must contain at least a valid PHR (see Section 8.1 “Introduction - IEEE 802.15.4 - 2006 Frame Format” on page 79). It is recommended to use a frame of maximum length (127 bytes) and arbitrary PSDU data for the PRBS mode. The SHR and the PHR are not transmitted. The transmission starts with the PSDU data and is repeated continuously. 20.2 Configuration Before enabling Continuous Transmission Test Mode all register configurations shall be done as follow: • TX channel setting (optional) • TX output power setting (optional) • Mode selection (PRBS / CW) A register access to register 0x36 and 0x1C enables the Continuous Transmission Test Mode. The transmission is started by enabling the PLL (TRX_CMD = PLL_ON) and writing the TX_START command to register 0x02. Even for CW signal transmission it is required to write valid PSDU data to the Frame Buffer. For PRBS mode it is recommended to write a frame of maximum length. The detailed programming sequence is shown in Table 20-1 on page 172. The column R/W informs about writing (W) or reading (R) a register or the Frame Buffer. Table 20-1. Step 1 2 3 4 5 6 7 Action RESET Register Access Register Access Register Access Register Access Register Access Register Access 0X0E 0x04 0x02 0x03 0x08 0x05 W W W W W W 0x01 0x00 0x03 0x01 0x33 0x00 Continuous Transmission Programming Sequence. Register R/W Value Description Reset AT86RF231 Set IRQ mask register, enable IRQ_0 (PLL_LOCK) Disable TX_AUTO_CRC_ON Set radio transceiver state TRX_OFF Set clock at pin 17 (CLKM) Set IEEE 802.15.4 CHANNEL, e.g. 19 Set TX output power, e.g. to Pmax 172 AT86RF231 8111A–AVR–05/08 AT86RF231 8 9 10(1) 11(1) 12(2) 13 14 15 16 17 18 19 20 Register Access Register Access Register Access Register Access Frame Buffer Write Access Register Access Register Access Register Access Interrupt event Register Access Measurement Register Access RESET 0x1C W 0x00 0x1C 0x1C 0x02 0x0F 0x02 0x01 0x036 0x0C 0x0A R W W W W W W W R W 0x54 0x46 0x09 0x01 0x02 0x08 0x0F 0x03 0xA7 Verify TRX_OFF state Enable Continuous Transmission Test Mode - step # 1 Enable High Data Rate Mode, 2 Mb/s Configure High Data Rate Mode Write PSDU data (even for CW mode), refer to Table A-2 Enable Continuous Transmission Test Mode - step # 2 Enable Continuous Transmission Test Mode - step # 3 Enable PLL_ON state Wait for IRQ_0 (PLL_LOCK) Initiate Transmission, enter BUSY_TX state Perform measurement Disable Continuous Transmission Test Mode Reset AT86RF231 Note: 1. Only required for CW mode, do not configure for PRBS mode. 2. Frame Buffer content varies for different modulation schemes. The content of the Frame Buffer has to be defined for Continuous Transmission PRBS mode or CW mode. To measure the power spectral density (PSD) mask of the transmitter it is recommended to use a random sequence of maximum length for the PSDU data. To measure CW signals it is necessary to write either 0x00 or 0xFF to the Frame Buffer, for details refer to Table 20-2 on page 173. Table 20-2. Step 12 Action Frame Buffer Access Frame Buffer Content for various Continuous Transmission Modulation Schemes Frame Content Random Sequence 0x00 (each byte) 0xFF (each byte) Comment modulated RF signal fCH - 0.5 MHz, CW signal fCH + 0.5 MHz, CW signal 173 8111A–AVR–05/08 20.3 Register Description Register 0x36 (TST_CTRL_DIGI): Register TST_CTRL_DIG enables the continuous transmission test mode. Bit +0x36 Read/Write Reset Value 7 6 Reserved 5 4 3 2 TST_CTRL_DIG 1 0 TST_CTRL_DIGI R/W 0 R/W 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 • Bit [7:4] - Reserved • Bit [3:0] - TST_CTRL_DIG These register bits enable continuous transmission: Table 20-3. Register Bit TST_CTRL_DIG Continuous Transmission Value 0x0 0xF 0x1 - 0xE Description Continuous Transmission disabled Continuous Transmission enabled Reserved 174 AT86RF231 8111A–AVR–05/08 AT86RF231 21. Appendix B - Errata 21.1 AT86RF231 Rev.A No known errata 175 8111A–AVR–05/08 References [1] [2] [3] [4] [5] [6] IEEE Std 802.15.4™-2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) IEEE Std 802.15.4™-2003: Wireless Medium Access Control (MAC) and Physical Layer (PHY) Specifications for Low-Rate Wireless Personal Area Networks (LR-WPANs) ANSI / ESD-STM5.1-2001: ESD Association Standard Test Method for electrostatic discharge sensitivity testing - Human Body Model (HBM). ESD-STM5.3.1-1999: ESD Association Standard Test Method for electrostatic discharge sensitivity testing - Charged Device Model (CDM). NIST FIPS PUB 197: Advanced Encryption Standard (AES), Federal Information Processing Standards Publication 197, US Department of Commerce/NIST, November 26, 2001 AT86RF231 Software Programming Model 176 AT86RF231 8111A–AVR–05/08 AT86RF231 Table of Contents Features ..................................................................................................... 1 1 Pin-out Diagram ....................................................................................... 2 1.1 1.2 1.3 Pin Descriptions .................................................................................................3 Analog and RF Pins ...........................................................................................5 Digital Pins .........................................................................................................7 2 3 4 5 Disclaimer ................................................................................................. 9 Overview ................................................................................................... 9 General Circuit Description ................................................................... 10 Application Circuits ............................................................................... 12 5.1 5.2 Basic Application Schematic ...........................................................................12 Extended Feature Set Application Schematic .................................................14 6 Microcontroller Interface ....................................................................... 16 6.1 6.2 6.3 6.4 6.5 6.6 SPI Timing Description ....................................................................................17 SPI Protocol .....................................................................................................19 Radio Transceiver Status information .............................................................24 Radio Transceiver Identification ......................................................................25 Sleep/Wake-up and Transmit Signal (SLP_TR) ..............................................27 Interrupt Logic ..................................................................................................29 7 Operating Modes .................................................................................... 33 7.1 7.2 Basic Operating Mode .....................................................................................33 Extended Operating Mode ...............................................................................47 8 Functional Description .......................................................................... 79 8.1 8.2 8.3 8.4 8.5 8.6 Introduction - IEEE 802.15.4 - 2006 Frame Format ........................................79 Frame Check Sequence (FCS) .......................................................................85 Received Signal Strength Indicator (RSSI) .....................................................89 Energy Detection (ED) .....................................................................................91 Clear Channel Assessment (CCA) ..................................................................94 Link Quality Indication (LQI) ............................................................................99 9 Module Description .............................................................................. 101 9.1 9.2 Receiver (RX) ................................................................................................101 Transmitter (TX) ............................................................................................104 i 8111A–AVR–05/08 9.3 9.4 9.5 9.6 9.7 9.8 Frame Buffer ..................................................................................................107 Voltage Regulators (AVREG, DVREG) .........................................................110 Battery Monitor (BATMON) ...........................................................................113 Crystal Oscillator (XOSC) ..............................................................................116 Frequency Synthesizer (PLL) ........................................................................121 Automatic Filter Tuning (FTN) .......................................................................125 10 Radio Transceiver Usage .................................................................... 126 10.1 10.2 Frame Receive Procedure .............................................................................126 Frame Transmit Procedure ............................................................................127 11 AT86RF231 Extended Feature Set ...................................................... 128 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Security Module (AES) ..................................................................................128 Random Number Generator ..........................................................................136 High Data Rate Modes ..................................................................................137 Antenna Diversity ..........................................................................................142 RX/TX Indicator .............................................................................................147 RX Frame Time Stamping .............................................................................150 Frame Buffer Empty Indicator ........................................................................152 Dynamic Frame Buffer Protection .................................................................154 Configurable Start-Of-Frame Delimiter ..........................................................155 12 Electrical Characteristics .................................................................... 156 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Absolute Maximum Ratings ...........................................................................156 Recommended Operating Range ..................................................................156 Digital Pin Characteristics ..............................................................................157 Digital Interface Timing Characteristics .........................................................157 General RF Specifications .............................................................................158 Transmitter Characteristics ............................................................................159 Receiver Characteristics ................................................................................160 Current Consumption Specifications .............................................................161 Crystal Parameter Requirements. .................................................................161 13 Typical Characteristics ........................................................................ 162 13.1 13.2 Active Supply Current ....................................................................................162 State Transition Timing ..................................................................................164 14 Register Summary ............................................................................... 166 15 Abbreviations ....................................................................................... 168 ii AT86RF231 8111A–AVR–05/08 AT86RF231 16 Ordering Information ........................................................................... 170 17 Soldering Information .......................................................................... 170 18 Package Thermal Properties ............................................................... 170 19 Package Drawing - 32QN2 ................................................................... 171 20 Appendix A - Continuous Transmission Test Mode ......................... 172 20.1 20.2 20.3 Overview ........................................................................................................172 Configuration .................................................................................................172 Register Description ......................................................................................174 21 Appendix B - Errata .............................................................................. 175 21.1 AT86RF231 Rev.A ........................................................................................175 References............................................................................................. 176 Table of Contents....................................................................................... i iii 8111A–AVR–05/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support avr@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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