AT87C5112

Features • 80C51 Compatible – Five I/O Ports – Two 16-bit Timer/Counters – 256 Bytes RAM 8K Bytes ROM/OTP Program Memory with 64 Bytes Encryption Array and 3 Security Levels High-Speed Architecture – 33 MHz at 5V (66 MHz Equivalent) – X2 Speed Improvement Capability (6 Clocks/Machine Cycle) 10-bit, 8 Channels A/D Converter Hardware Watchdog Timer with Reset-out Programmable I/O Mode: Standard C51, Input Only, Push-pull, Open Drain Asynchronous Port Reset Full Duplex Enhanced UART with Baud Rate Generator SPI, Master Mode Dual System Clock – Crystal or Ceramic Oscillator (33/40 MHz) – Internal RC Oscillator (12 MHz) – Programmable Prescaler Programmable Counter Array with High-speed Output, Compare/Capture, Pulse Width Modulation and Watchdog Timer Capabilities Interrupt Structure – 8 Interrupt Sources – 4 Interrupt Priority Levels Power Control Modes – Idle Mode – Power-down Mode – Power-off Flag Power Supply: 2.7 - 5.5V Temperature Range: Industrial (-40 To 85°C) Package: LQFP48 (Body 7*7*1.4 mm), PLCC52 • • • • • • • • • 8-bit Microcontroller with A/D Converter • • • AT80C5112 AT83C5112 AT87C5112 • • • Description The AT8xC5112 is a high performance ROM/OTP version of the 80C51 8-bit microcontroller. The AT8xC5112 retains all the features of the standard 80C51 with 8 Kbytes ROM/OTP program memory, 256 bytes of internal RAM, a 8-source, 4-level interrupt system, an on-chip oscillator and two timer/counters. The AT8xC5112 is dedicated for analog interfacing applications. For this, it has a 10bit, 8 channels A/D converter and a five channels Programmable Counter Array. In addition, the AT8xC5112 has a Hardware Watchdog Timer, a versatile serial channel that facilitates multiprocessor communication (EUART) with an independent baud rate generator, a SPI serial bus controller and a X2 speed improvement mechanism. The X2 feature allows to keep the same CPU power at a divided by two oscillator frequency. The fully static design of the AT8xC5112 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. Rev. 4191C–8051–02/08 The AT8xC5112 has 3 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode, the CPU is frozen while the peripherals are still operating. In the quiet mode, the A/D converter is only operating. In the Power-down mode, the RAM is saved and all other functions are inoperative. Two oscillators source, crystal and RC, provide a versatile power management. The AT8xC5112 is proposed in 48-/52-pin count packages with Port 0 and Port 2 (address/ data buses). Block Diagram CEX0-4 RxD TxD Vcc Vss ECI SPSCK MISO MOSI (2) (2) XTAL1 XTAL2 (2) (2) Xtal Osc EUART BRG (1) (1) (3)(3) (3) (3) RAM 256 x8 ROM /OTP PCA SPI SS Watch Dog 8 K *8 RC Osc C51 CORE IB-bus CPU RST EA ALE PSEN Timer 0 Timer 1 INT Ctrl A/D Converter Parallel I/O Ports Port 1 Port 3 Port 4 Port 0 Port 2 INT0 INT1 AIN0-7 (2) VPP (2) (3) T0 T1 (2) (3) Vref (3) P4 P0 P1 P3 P2 4191C–8051–02/08 Notes: 1. Alternate function of Port 1. 2. Alternate function of Port 3. 3. Alternate function of Port 4. 2 AT8xC5112 AT8xC5112 SFR Mapping The Special Function Registers (SFRs) of the AT8xC5112 belong to the following categories: • • • • • • • • • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2 Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1 Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON, CKRL Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1 Watchdog Timer: WDTRST, WDTPRG SPI: SPCON, SPSTA, SPDAT PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H, CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF • 3 4191C–8051–02/08 Table 1. SFR Addresses and Reset Values 0/8 F8h B 0000 0000 CL 0000 0000 ACC 0000 0000 CCON 00X0 0000 PSW 0000 0000 CMOD X000 0000 1/9 CH 0000 0000 72/A CCAP0H XXXX XXXX ADCLK 0000 0000 CCAP0L XXXX XXXX P1M2 0000 0000 CCAPM0 00XX X000 CCAPM1 X000 0000 3/B CCAP1H XXXX XXXX ADCON 0000 0000 CCAP1L XXXX XXXX 4/C CCAP2H XXXX XXXX ADDL XXXXXX00 CCAP2L XXXX XXXX P3M2 0000 0000 CCAPM2 X000 0000 P1M1 0000 0000 5/D CCAP3H XXXX XXXX ADDH 0000 0000 CCAP3L XXXX XXXX P4M2 0000 0000 CCAPM3 X000 0000 P3M1 0000 0000 CCAPM4 X000 0000 P4M1 0000 0000 6/E CCAP4H XXXX XXXX ADCF 0000 0000 CCAP4L XXXX XXXX CONF 7/F FFh F0h F7h E8h EFh E0h E7h D8h DFh D0h D7h C8h P4 1111 1111 IPL0 0000 0000 P3 1111 1111 IE0 0000 0000 SADEN 0000 0000 IE1 0000 0000 SADDR 0000 0000 AUXR1 XXXXXXX0 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 TMOD 0000 0000 SP 0000 0111 0/8 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B 4/C TH0 0000 0000 TH1 0000 0000 CKSEL XXXX XXX1 5/D OSCCON XXXX XX01 6/E SBUF XXXX XXXX BRL 0000 0000 BDRCON 0000 0000 CKRL 1111 1111 CKCON0 X000X000 PCON 00X1 0000 7/F WDRST 0000 0000 IPL1 0000 0000 IPH1 0000 0000 IPH0 X000 0000 CKCON1 XXXX XXX0 WDTPRG 0000 0000 SPCON 0001 0100 SPSTA XXXXXXXX SPDAT XXXX XXXX CFh C0h C7h B8h BFh B0h B7h A8h AFh A0h A7h 98h 9Fh 90h 97h 88h 8Fh 80h 87h Reserved 4 AT8xC5112 4191C–8051–02/08 AT8xC5112 Pin Configurations P4.6/AIN6/SPSCK P4.4/AIN4/MISO P4.5/AIN5/MOSI P4.3/AIN3/INT1 P4.2/AIN2/SS P4.1/AIN1/T1 P4.0/AIN0 P4.7/AIN7 P1.0/WR 48 47 46 45 44 43 42 41 40 39 38 37 VREF VSS + AVSS P2.7 P2.6 P2.5 P2.4 P2.3 V2.2 VCC + AVCC P2.1 P2.0 P3.7 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 P3.0/RxD P3.1/TxD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.2/ECI P1.3/CEX0 P1.1/RD RST EA LQFP48 7*7*1.4 mm 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 XTAL2 XTAL1 P1.7/CEX4 P1.6/CEX3 ALE PSEN VPP P3.6 P3.2/INT0 P1.5/CEX2 P3.3/T0 P1.4/CEX1 P4.6/AIN6/SPSCK P4.4/AIN4/MISO P4.5/AIN5/MOSI P4.3/AIN3/INT1 P4.2/AIN2/SS P4.1/AIN1/T1 P4.7/AIN7 7 6 5 4 3 2 1 52 51 50 49 48 47 VSS AVSS P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 AVCC + VCC P2.1 P2.0 P3.7 VPP P4.0/AIN0 P1.0/WR P1.1/RD VREF RST EA 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 XTAL2 XTAL1 P1.7/CEX4 P1.6/CEX3 ALE PSEN P3.2/INT0 P1.5/CEX2 P3.3/T0 P1.4/CEX1 P3.6 P3.5 P3.4 46 45 44 43 42 41 40 39 38 37 36 35 34 NIC P3.0/RxD P3.1/TxD P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P1.2/ECI P1.3/CEX0 PLCC52 *NIC: No Internal Connection 5 4191C–8051–02/08 Table 2. Pin Description PIN NUMBER LQFP Mnemonic VSS VCC AVSS AVCC VREF X X 48 X X PLCC 52 X X X I I I I I Name and Function Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle and power-down operation. Analog Ground: 0V reference. Analog Power Supply: This is the power supply voltage for normal and idle operation of the A/D VREF : A/D converter positive reference input. Vpp : Programming Supply Voltage: VPP X X I This pin also receives the 12V programming pulse which will start the EPROM programming and the manufacturer test modes. Port 1: Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. Alternate functions for Port 1 include: I/O I/O I/O I/O I/O I/O I/O I/O P3.0 - P3.7 X X I/O WR (P1.0): External data memory write strobe RD (P1.1): External data memory readstrobe ECI (P1.2): External Clock for the PCA CEX0 (P1.3): Capture/Compare External I/O for PCA module 0 CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 Port 3: Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. P3.6 is an input only pin. Port 3 also serves the special features of the 80C51 family, as listed below. I/O I/O I/O I/O I/O I/O I/O RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt 0 T0 (P3.3): Timer 0 external input Port 4: Port 4 is an 8-bit bi-directional I/O port. Each bit can be set as pure CMOS input or as push-pull output. Port 4 is also the input port of the analog-to-digital converter and used for oscillator and reset. AIN0 (P4.0): A/D converter input 0 AIN1 (P4.1): A/D converter input 1 T1: Timer 1 external input AIN2 (P4.2): A/D converter input 2 SS: Slave select input of the SPI controller AIN3 (P4.3): A/D converter input 3 INT1: External interrupt 1 TYPE P1.0 - P1.7 X X I/O P4.0-P4.7 X X I/O I/O 6 AT8xC5112 4191C–8051–02/08 AT8xC5112 Table 2. Pin Description (Continued) PIN NUMBER LQFP Mnemonic 48 PLCC 52 I/O Name and Function AIN4 (P4.4): A/D converter input 4 MISO: Master IN, Slave OUT of the SPI controller AIN5 (P4.5): A/D converter input 5 MOSI: Master OUT, Slave IN of the SPI controller AIN6 (P4.6): A/D converter input 6 SPSCK: Clock I/O of the SPI controller AIN7 (P4.7): A/D converter input 7 Port 0: Port 0 is an open-drain, bi-directional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 2: Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX atDPTR). In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX atRi), port 2 emits the contents of the P2 SFR. RST: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. If the hardware watchdog reaches its time-out, the reset pin becomes an output during the time the internal reset is activated. Address Latch Enable: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. Program Store Enable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 1FFFH . If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 1FFFH. EA must be held low for ROMless devices. If security level 1 is programmed, EA will be internally latched on Reset. XTAL1 : Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 : Output from the inverting oscillator amplifier. TYPE I/O I/O I/O P0.0-P0.7 X X I/O P2.0-P2.7 X X I/O RST X X I ALE X X O PSEN X X O EA X X I XTAL1 XTAL2 X X I O 7 4191C–8051–02/08 AT8xC5112 Clock System The AT8xC5112 oscillator system provides a reliable clocking system with full mastering of speed versus CPU power trade off. Several clock sources are possible: • • • External clock input High-speed crystal or ceramic oscillator Integrated high-speed RC oscillator The selected clock source can be divided by 2 - 512 before clocking the CPU and the peripherals. When X2 function is set, the CPU needs 6 clock periods per cycle. Clocking is controlled by several SFR registers: OSCON, CKCON0, CKCON1, CKRL. Blocks Description The AT8xC5112 includes the following oscillators: • • Crystal oscillator Integrated high-speed RC oscillator, with typical frequency of 12 MHz Crystal Oscillator: OSCA The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output. Both crystal and ceramic resonators can be used. An oscillator source on XTAL1 is mandatory to start the product. OSCAEN in OSCCON register is an enable signal for the crystal oscillator or the external oscillator input. Integrated High-speed RC Oscillator: OSCB The high-speed RC oscillator typical frequency is 12 MHz. Note that the on chip oscillator has a ±50% frequency tolerance and may not be suitable for use in some applications. OSCBEN in OSCCON register is an enable signal for the high-speed RC oscillator. Clock Selector CKS bit in CKS register is used to select from crystal to RC oscillator. OSCBEN bit in OSCCON register is used to enable the RC oscillator. OSCAEN bit in OSCCON register is used to enable the crystal oscillator or the external oscillator input. Clock Prescaler Before supplying the CPU and the peripherals, the main clock is divided by a factor of 2 to 512, as defined by the CKRL register. The CPU needs from 12 to 256*12 clock periods per instruction. This allows: • • to accept any cyclic ratio to be accepted on XTAL1 input. to reduce the CPU power consumption. The X2 bit allows to bypass the clock prescaler; in this case, the CPU needs only 6 clock periods per machine cycle. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. 7 4191C–8051–02/08 Functional Block Diagram Timer 0 Clock : 128 ResetB Reload Sub Clock Ckrl WD Clock Xtal1 Xtal2 OSCAEN OSCBEN PwdOsc CKS RC_Osc OSCB X2 PwdRC CPU Clock Ck Xtal_Osc OSCA 1 A/D Clock Mux + Filter OscOut 8-bit Prescaler-Divider 0 1 CkOut CkAdc Peripherals Clock CkIdle 0 Quiet Pwd Idle Operating Modes Functional Modes Normal Modes • • • CPU and Peripheral clocks depend on the software selection using CKCON0, CKCON1, CKSEL and CKRL registers. CKS bit selects either Xtal_Osc or RC_Osc. CKRL register determines the frequency of the selected clock, unless X2 bit is set. In this case the prescaler/divider is not used, so CPU core needs only 6 clock periods per machine cycle. According to the value of the peripheral X2 individual bit, each peripheral needs 6 or 12 clock periods per instruction. It is always possible to switch dynamically by software from Xtal_Osc to RC_Osc, and vice versa by changing CKS bit, a synchronization cell allowing to avoid any spike during transition. IDLE modes are achieved by using any instruction that writes into PCON.0 sfr IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 register: – – • • • IDLE MODE A: Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1) IDLE MODE B: RC_Osc is running (OSCBEN = 1) and selected (CKS = 0) • Idle Modes • • The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing OSCAEN or OSCBEN, respectively. Exit from IDLE mode is achieved by Reset, or by activation of an enabled interrupt. In both cases, PCON.0 is cleared by hardware. 8 AT8xC5112 4191C–8051–02/08 AT8xC5112 • Exit from IDLE modes will leave the oscillator control bits OSCAEN, OSCBEN and CKS unchanged. POWER-DOWN modes are achieved by using any instruction that writes into PCON.1 sfr Exit from POWER-DOWN mode is achieved either by a hardware Reset, or by an external interruption. By RST signal: The CPU will restart on OSCA. By INT0 or INT1 interruptions, if enabled. The oscillators control bits OSCAEN, OSCBEN and CKS will not be changed, so the selected oscillator before entering into Power-down will be activated. Power-down Modes • • • • Table 1. Power Modes PD 0 X 0 X 0 IDLE 0 X 0 X 1 CKS 1 1 0 0 1 OSCBEN X X 1 0 X OSCAEN Selected Mode 1 0 X X 1 Comment NORMAL MODE A OSCA: XTAL clock INVALID No active clock NORMAL MODE B OSCB: high-speed RC clock INVALID IDLE MODE A The CPU is off, OSCA supplies the peripherics The CPU is off, OSCB supplies the peripherics The CPU is off, OSCA and OSCB are stopped 0 1 0 1 X IDLE MODE B TOTAL POWERDOWN 1 X X X X Prescaler Divider • An hardware RESET selects the prescaler divider: – – CKRL = FFh: internal clock = OscOut/2 (Standard C51 feature) X2 = 0, • After Reset, any value between FFh down to 00h can be written by software into CKRL sfr in order to divide frequency of the selected oscillator: – – CKRL = 00h: minimum frequency = OscOut/512 CKRL = FFh: maximum frequency = OscOut/2 The frequency of the CPU and peripherals clock CkOut is related to the frequency of the main oscillator OscOut by the following formula: FCkOut = FOscOut/(512 - 2*CKRL) Some examples can be found in the table below: FOscOut MHz 12 12 12 X2 0 0 1 CKRL FF FE x FCkOut (Mhz) 6 3 12 • A software instruction which sets X2 bit de-activates the prescaler/divider, so the internal clock is either Xtal_Osc or RC_Osc depending on SEL_OSC bit. 9 4191C–8051–02/08 Timer 0: Clock Inputs CkIdle T0 pin Sub Clock :6 0 1 C/T TMOD SCLKT0 OSCCON Gate INT0 TR0 0 1 Control Timer 0 The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This allows to perform a Real-Time Clock function. SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode). SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input. When the subclock input is selected for Timer 0 and the crystal oscillator is selected for CPU and peripherals, the CKRL prescaler must be set to FF (division factor 2) in order to assure a proper count on Timer 0. With an external a 32 kHz oscillator, the timer interrupt can be set from 1/256 to 256 seconds to perform a Real-Time Clock (RTC) function. The power consumption will be very low as the CPU is in idle mode at 32 kHz most of the time. When more CPU power is needed, the internal RC oscillator is activated and used by the CPU and the others peripherals. Registers Clock Control Register The clock control register is used to define the clock system behavior. Table 2. OSCCON - Clock Control Register (8Fh) 7 Bit Number 7 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. 5 4 3 2 SCLKT0 1 OSCBEN 0 OSCAEN 6 - 5 - 4 - 3 - 10 AT8xC5112 4191C–8051–02/08 AT8xC5112 Bit Number Bit Mnemonic Description Sub Clock Timer0 2 SCLKT0 Cleared by software to select T0 pin Set by software to select T0 Sub Clock Enable RC oscillator This bit is used to enable the high-speed RC oscillator 0: The oscillator is disabled 1: The oscillator is enabled. Enable crystal oscillator This bit is used to enable the crystal oscillator 0: The oscillator is disabled 1: The oscillator is enabled. 1 OSCBEN 0 OSCAEN Reset value = 0XXX X001b Not bit addressable Clock Selection Register The clock selection register is used to define the clock system behavior Table 3. CKSEL - Clock Selection Register (85h) 7 6 Bit Number 7 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Active oscillator selection This bit is used to select the active oscillator. 1: The crystal oscillator is selected. 0: The high-speed RC oscillator is selected. 5 4 3 2 1 0 CKS 6 - 5 - 4 - 3 - 2 - 1 - 0 CKS Reset value = XXXX XXX 1 b Not bit addressable 11 4191C–8051–02/08 Clock Prescaler Register This register is used to reload the clock prescaler of the CPU and peripheral clock. Table 4. CKRL - Clock Prescaler Register (97h) 7 6 5 4 M Bit Number Bit Mnemonic Description 0000 0000b: Division factor equal 512 7: 0 CKRL 1111 1111b: Division factor equal 2 M: Division factor equal 2*(256-M) 3 2 1 0 Reset value = 1111 1111b Not bit addressable Clock Control Register This register is used to control the X2 mode of the CPU and peripheral clock. Table 5. CKCON0 Register (8Fh) 7 Bit Number 7 6 WdX2 Bit Mnemonic Description Reserved Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 3 Reserved Timer 1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle Timer 0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 5 PcaX2 4 SiX2 3 2 T1X2 1 T0X2 0 X2 6 WdX2 5 PcaX2 4 SiX2 2 T1X2 1 T0X2 12 AT8xC5112 4191C–8051–02/08 AT8xC5112 Bit Number Bit Mnemonic Description CPU clock 0 X2 Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits. Reset value = X000 0000b Not bit addressable Table 6. CKCON1 Register (AFh) 7 Bit Number 7 6 5 4 3 2 Bit Mnemonic Description Reserved Reserved Reserved Reserved Reserved Reserved BRG clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect). Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. SPI clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect) Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle. 6 5 4 3 2 1 BRGX2 0 SPIX2 1 BRGX2 0 SPIX2 Reset value = XXXX XX00b Not bit addressable 13 4191C–8051–02/08 AT8xC5112 Reset and Power Management The power monitoring and management can be used to supervise the Power Supply (VDD) and to start up properly when AT8xC5112 is powered up. It consists of the features listed below and explained hereafter: • • • • Power-off flag Idle mode Power-down mode Reduced EMI mode All these features are controlled by several registers, the Power Control register (PCON) and the Auxiliary register (AUXR) detailed at the end of this section. AUX register not available on all versions. Functional Description Figure 1 shows the block diagram of the possible sources of microcontroller reset. Figure 1. Reset Sources RST Pin(1) Hardware WD Reset RST Pin(2) PCA WD Notes: 1. RST pin available only on 48 and 52 pins versions. 2. RST pin available only on LPC versions. Power-off Flag When the power is turned off or fails, the data retention is not guaranteed. A Power-off Flag (POF, Table 8 on page 15) allows to detect this condition. POF is set by hardware during a reset which follows a power-up or a power-fail. This is a cold reset. A warm reset is an external or a watchdog reset without power failure, hence which preserves the internal memory content and POF. To use POF, test and clear this bit just after reset. Then it will be set only after a cold reset. 14 4191C–8051–02/08 Registers PCON: Power Configuration Register Table 1. PCON Register (87h) 7 SMOD1 Bit Number 6 SMOD0 Bit Mnemonic 5 – 4 POF 3 GF1 2 GF0 1 PD 0 IDL Description Double Baud Rate bit Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is selected in SCON register. SCON Select bit When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write accesses to SCON.6 are to SM1 bit. When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to SCON.6 are to OVR bit. SCON is Serial Port Control register. Reserved Must be cleared. Power-off flag Set by hardware when VDD rises above VRET+ to indicate that the Power Supply has been set off. Must be cleared by software. General Purpose flag 1 One use is to indicate wether an interrupt occurred during normal operation or during Idle mode. General Purpose flag 0 One use is to indicate wether an interrupt occurred during normal operation or during Idle mode. Power-down Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Power-down mode. If IDL and PD are both set, PD takes precedence. Idle Mode bit Cleared by hardware when an interrupt or reset occurs. Set to activate the Idle mode. If IDL and PD are both set, PD takes precedence. 7 SMOD1 6 SMOD0 5 – 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset value = 0000 0000b Port Pins The value of port pins in the different operating modes is shown on Table 9. Table 2. Pin Conditions in Special Operating Modes Mode Reset Idle Power-down Program Memory Don’t care Internal Internal Port 1 Pins Weak High Data Data Port 3 Pins Weak High Data Data Port 4 Pins Weak High Data Data 15 AT8xC5112 4191C–8051–02/08 AT8xC5112 Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 11. AUXR Register AUXR - Auxiliary Register (8Eh) 7 Bit Number 7 6 Bit Mnemonic 5 4 3 2 1 0 AO Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. 6 - 5 - 4 - 3 - 2 - 1 - 0 AO Reset value = XXXX XXX0b Not bit addressable 17 4191C–8051–02/08 AT8xC5112 Hardware Watchdog Timer (WDT) The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the Watchdog Timer Reset (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle (6 internal clock periods) and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). The T0 bit of the WDTPRG register is used to select the overflow after 10 or 14 bits. When WDT overflows, it will generate an internal reset. It will also drive an output RESET HIGH pulse at the emulator RST-pin. The length of the reset pulse is 24 clock periods of the WD clock. To enable the WDT, the user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 96 x TOSC, where TOSC = 1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16 ms to 2s at FOSC = 12 MHz and T0 = 0. To manage this feature, refer to WDTPRG register description, Table 11 (SFR0A7h). Table 1. WDTRST Register WDTRST Address (0A6h) 7 Reset value X 6 X 5 X 4 X 3 X 2 X 1 X Using the WDT Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. 16 4191C–8051–02/08 Table 2. WDTPRG Register WDTPRG Address (0A7h) 7 T4 Bit Number 7 6 5 4 6 T3 Bit Mnemonic T4 T3 T2 T1 WDT overflow select bit 3 T0 0: Overflow after 14 bits 1: Overflow after 10 bits 2 1 0 S2 S1 S0 WDT Time-out select bit 2 WDT Time-out select bit 1 WDT Time-out select bit 0 S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Selected Time-out with T0 = 0 (214 - 1) machine cycles, 16.3 ms at 12 MHz (215 - 1) machine cycles, 32.7 ms at 12 MHz (216 - 1) machine cycles, 65.5 ms at 12 MHz (217 - 1) machine cycles, 131 ms at 12 MHz (218 - 1) machine cycles, 262 ms at 12 MHz (219 - 1) machine cycles, 542 ms at 12 MHz (220 - 1) machine cycles, 1.05 s at 12 MHz (221 - 1) machine cycles, 2.09 s at 12 MHz Reserved Do not try to set this bit. 5 T2 4 T1 3 T0 2 S2 1 S1 0 S0 Description Reset value = XXX0 0000 Write only register WDT During Power-down and Idle Power-down In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode the user does not need to service the WDT. There are 2 methods of exiting Power-down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as normal whenever the AT8xC5112 is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of power-down, it is best to reset the WDT just before entering power-down. Idle Mode In Idle mode, the oscillator continues to run. To prevent the WDT from resetting the AT8xC5112 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. 17 AT8xC5112 4191C–8051–02/08 AT8xC5112 Ports All port 1, port 3 and port 4 I/O port pins on the AT8xC5112 may be software configured to one of four types on a bit-by-bit basis, as shown in Table 14. These are: Quasi bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two configuration registers for each port choose the output type for each port pin. Table 14. Port Output Configuration settings using PxM1 and PxM2 registers PxM1.y Bit 0 0 1 1 PxM2.y Bit 0 1 0 1 Port Output Mode Quasi bi-directional Push-pull Input-only (High Impedance) Open Drain Port Types Quasi bi-directional Output Configuration The default port output configuration for standard AT8xC5112 I/O ports is the Quasi bidirectional output that is common on the 80C51 and most of its derivatives. This output type can be used as both an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly and able to sink a fairly large current. These features are somewhat similar to an open drain output except that there are three pull-up transistors in the Quasi bi-directional output that serve different purposes. One of these pull-ups, called the "very weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. The very weak pull-up sources a very small current that will pull the pin high if it is left floating. A second pullup, called the "weak" pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a Quasi bi-directional pin that is outputting a 1. If a pin that has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pullup remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and take the voltage on the port pin below its input threshold. The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up low-to-high transitions on a Quasi bi-directional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time, two CPU clocks, in order to pull the port pin high quickly. Then it turns off again. The Quasi bi-directional port configuration is shown in Figure 2. 20 4191C–8051–02/08 Figure 2. Quasi bi-directional Output 2 CPU CLOCK DELAY P Strong P Very Weak P Weak Pin Port latch Data N Input Data Open Drain Output Configuration The open-drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to VDD. The pull-down for this mode is the same as for the Quasi bi-directional mode. The open-drain port configuration is shown in Figure 3. Figure 3. Open-drain Output Pin Port latch Data N Input Data Push-pull Output Configuration The push-pull output configuration has the same pull-down structure as both the open drain and the Quasi bi-directional output modes, but provides a continuous strong pullup when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output. The push-pull port configuration is shown in Figure 4. 21 AT8xC5112 4191C–8051–02/08 AT8xC5112 Figure 4. Push-pull Output P Strong Pin Port Latch Data N Input Data Input-only Configuration The input-only configuration is a pure input with neither pull-up nor pull-down. The input-only configuration is shown in Figure 4. Figure 5. Input-only Input Data Pin Ports Description Ports P1, P3 and P4 Every output on the AT8xC5112 may potentially be used as a 20 mA sink LED drive output. However, there is a maximum total output current for all ports which must not be exceeded. All ports pins of the AT8xC5112 have slew rate controlled outputs. This is to limit noise generated by quickly switching output signals. The slew rate is factory set to approximately 10 ns rise and fall times. The inputs of each I/O port of the AT8xC5112 are TTL level Schmitt triggers with hysteresis. Ports P0 and P2 High pin-count version of the AT8xC5112 has standard address and data ports P0 and P2. These ports are standard C51 ports (Quasi bi-directional I/O). The control lines are provided on the pins: ALE, PSEN, EA, Reset; RD and WR signals are on the bits P1.1 and P1.0. 22 4191C–8051–02/08 Registers Table 15. P1M1 Register P1M1 Address (D4h) 7 P1M1.7 Bit Number 7: 0 6 P1M1.6 5 P1M1.5 Bit Mnemonic P1M1.x Description Port Output configuration bit See Table 10 for configuration definition 4 P1M1.4 3 P1M1.3 2 P1M1.2 1 P1M1.1 0 P1M1.0 Reset value = 0000 00XX Table 16. P1M2 Register P1M2 Address (E2h) 7 P1M2.7 Bit Number 7: 0 6 P1M2.6 5 P1M2.5 Bit Mnemonic P1M2.x Description Port Output configuration bit See Table 10 for configuration definition 4 P1M2.4 3 P1M2.3 2 P1M2.2 1 P1M2.1 0 P1M2.0 Reset value = 0000 00XX Table 17. P3M1 Register P3M1 Address (D5h) 7 P3M1.7 Bit Number 7: 0 6 P3M1.6 5 P3M1.5 Bit Mnemonic P3M1.x Description Port Output configuration bit See Table 10 for configuration definition 4 P3M1.4 3 P3M1.3 2 P3M1.2 1 P3M1.1 0 P3M1.0 Reset value = 0000 0000 23 AT8xC5112 4191C–8051–02/08 AT8xC5112 Table 18. P3M2 Register P3M2 Address (E4h) 7 P3M2.7 Bit Number 7: 0 6 P3M2.6 5 P3M2.5 Bit Mnemonic P3M2.x Description Port Output configuration bit See Table 10 for configuration definition 4 P3M2.4 3 P3M2.3 2 P3M2.2 1 P3M2.1 0 P3M2.0 Reset value = 0000 0000 Table 19. P4M1 Register P4M1 Address (D6h) 7 P4M1.7 Bit Number 7: 0 6 P4M1.6 5 P4M1.5 Bit Mnemonic P4M1.x Description Port Output configuration bit See Table 10 for configuration definition 4 P4M1.4 3 P4M1.3 2 P4M1.2 1 P4M1.1 0 P4M1.0 Reset value = 0000 0000 Table 20. P4M2 Register P4M2 Address (E5h) 7 P4M2.7 Bit Number 7: 0 6 P4M2.6 5 P4M2.5 Bit Mnemonic P4M2.x Description Port Output configuration bit See Table 10 for configuration definition 4 P4M2.4 3 P4M2.3 2 P4M2.2 1 P4M2.1 0 P4M2.0 Reset value = 0000 0000 24 4191C–8051–02/08 AT8xC5112 Dual Data Pointer Register The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called DPS = AUXR1/bit0 (see Table 19) that allows the program code to switch between them (See Figure 6). Figure 1. Use of Dual Pointer External Data Memory 7 0 DPS DPTR1 DPTR0 AUXR1(A2H) DPH(83H) DPL(82H) Table 1. AUXR1: Auxiliary Register 1 7 Bit Number 7 6 5 4 3 2 1 0 DPS Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection Clear to select DPTR0. Set to select DPTR1. 6 - 5 - 4 - 3 - 2 - 1 - 0 DPS Note: User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 23 4191C–8051–02/08 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST 0008 LOOP: 0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,atDPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX atDPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. 24 AT8xC5112 4191C–8051–02/08 AT8xC5112 Serial I/O Ports Enhancements The serial I/O ports in the AT8xC5112 are compatible with the serial I/O port in the 80C52. They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates. Serial I/O ports include the following enhancements: • • Framing error detection Automatic address recognition Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (see Figure 7). Figure 1. Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON for UART (98h) (SCON_1 for UART_1 (C0h)) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1 for UART) SM0 to UART mode control (SMOD0 = 0 for UART) SMOD1 SMOD0 POF GF1 GF0 PD IDL PCON for UART (87h) (SMOD bits for UART_1 are located in BDRCON_1) To UART framing error control When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (see Table 25) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (see Figure 8 and Figure 9). Figure 2. UART Timings in Mode 1 RXD Start Bit RI SMOD0 = X FE SMOD0 = 1 D0 D1 D2 D3 D4 D5 D6 D7 Data Byte Stop Bit 25 4191C–8051–02/08 Figure 3. UART Timings in Modes 2 and 3 D0 D1 D2 D3 RXD Start Bit RI SMOD0 = 0 RI SMOD0 = 1 FE SMOD0 = 1 D4 D5 D6 D7 D8 Data Byte Ninth Stop Bit Bit Automatic Address Recognition The automatic address recognition feature is enabled for each UART when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. Note: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e., setting SM2 bit in SCON register in mode 0 has no effect). Given Address Each UART has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t care bits (defined by zeros) to form the device’s given address. The don’t care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR0101 0110b SADEN1111 1100b Given0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0010b SADEN1111 1101b Given1111 00X1b 26 AT8xC5112 4191C–8051–02/08 AT8xC5112 The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b Broadcast = SADDR OR SADEN1111 111Xb The use of don’t care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A:SADDR1111 0001b SADEN1111 1010b Broadcast1111 1X11b, Slave B:SADDR1111 0011b SADEN1111 1001b Broadcast1111 1X11B, Slave C:SADDR = 1111 0010b SADEN1111 1101b Broadcast1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON registers. Baud Rate Selection for UART for Modes 1 and 3 27 4191C–8051–02/08 Figure 4. Baud Rate Selection TIMER1_BRG 0 1 / 16 Rx Clock INT_BRG RBCK TIMER1_BRG 0 1 / 16 Tx Clock INT_BRG TBCK Table 1. Baud Rate Selection Table for UART TBCK 0 1 0 1 RBCK 0 0 1 1 Clock Source for UART Tx Timer 1 INT_BRG Timer 1 INT_BRG Clock Source UART Rx Timer 1 Timer 1 INT_BRG INT_BRG Internal Baud Rate Generator (BRG) When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the BRL reload value, the X2 bit in CKON0 register, the value of SPD bit (Speed Mode) in BDRCON register and the value of the SMOD1 bit in PCON register (for UART). Figure 5. Internal Baud Rate Generator SMOD1 /2 0 Auto Reload Counter BRG Overflow 1 INT_BRG Peripheral Clock /6 0 1 BRL SPD BRR 28 AT8xC5112 4191C–8051–02/08 AT8xC5112 for UART: Baud_Rate = 2SMOD1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)] 2SMOD1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x Baud_Rate Example of computed value when X2 = 1, SMOD1 = 1, SPD = 1 Baud Rates FXTAL = 16.384 MHz BRL 115200 57600 38400 28800 19200 9600 4800 247 238 229 220 203 149 43 Error (%) 1.23 1.23 1.23 1.23 0.63 0.31 1.23 BRL 243 230 217 204 178 100 FXTAL = 24 MHz Error (%) 0.16 0.16 0.16 0.16 0.16 0.16 - (BRL) = 256 - Example of computed value when X2 = 0, SMOD1 = 0, SPD = 0 Baud Rates FOSC = 16.384 MHz BRL 4800 2400 1200 600 247 238 220 185 Error (%) 1.23 1.23 1.23 0.16 BRL 243 230 202 152 FOSC = 24 MHz Error (%) 0.16 0.16 3.55 0.16 The baud rate generator can be used for mode 1 or 3 (See Figure 10), but also for mode 0 for both UARTs, thanks to the bit SRC located in BDRCON register (see Table 27). 29 4191C–8051–02/08 UART Registers Table 2. SADEN - Slave Address Mask Register for UART (B9h) 7 6 5 4 3 2 1 0 Reset value = 0000 0000b Table 3. SADDR - Slave Address Register for UART (A9h) 7 6 5 4 3 2 1 0 Reset value = 0000 0000b Table 4. SBUF - Serial Buffer Register for UART (99h) 7 6 5 4 3 2 1 0 Reset value = XXXX XXXXb Table 5. BRL - Baud Rate Reload Register for the Internal Baud Rate Generator, UART - UART(9Ah) 7 6 5 4 3 2 1 0 Reset value = 0000 0000b 30 AT8xC5112 4191C–8051–02/08 AT8xC5112 Table 6. SCON Register SCON - Serial Control Register for UART (98h) 7 FE/SM0 6 SM1 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI Bit Bit Number Mnemonic Description Framing Error bit (SMOD0 = 1) for UART Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit Serial Port Mode bit 0 (SMOD0 = 0) for UART Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit Serial Port Mode bit 1 for UART SM0 SM1 Mode Description Baud Rate 6 SM1 0 0 1 1 0 1 0 1 0 1 2 3 Shift Register 8-bit UART 9-bit UART 9-bit UART FXTAL/12 (FXTAL/6 X2 mode) Variable FXTAL/64 or FXTAL/32 (FXTAL/32 or FXTAL/16 X2 mode) Variable 7 FE SM0 5 SM2 Serial Port Mode 2 bit/Multiprocessor Communication Enable bit for UART Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. Reception Enable bit for UART Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3 for UART. 4 REN 3 TB8 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8/Ninth bit received in modes 2 and 3 for UART Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Transmit Interrupt flag for UART Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag for UART Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 8 and Figure 9 in the other modes. 2 RB8 1 TI 0 RI Reset value = 0000 0000b Bit addressable 31 4191C–8051–02/08 Table 7. PCON Register PCON - Power Control Register (87h) 7 SMOD1 Bit Number 7 6 SMOD0 5 RSTD 4 POF 3 GF1 2 GF0 1 PD 0 IDL Bit Mnemonic Description SMOD1 Serial Port Mode bit 1 for UART Set to select double baud rate in mode 1, 2 or 3. Serial Port Mode bit 0 for UART Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. Reset Detector Disable Bit 6 SMOD0 5 RSTD Clear to disable PFD. Set to enable PFD. Power-off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General-purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General-purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-down Mode bit Cleared by hardware when reset occurs. Set to enter Power-down mode. Idle Mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset value = 0001 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. 32 AT8xC5112 4191C–8051–02/08 AT8xC5112 Table 8. BDRCON Register BDRCON - Baud Rate Control Register (9Bh) 7 Bit Number 7 6 Bit Mnemonic 5 4 BRR 3 TBCK 2 RBCK 1 SPD 0 SRC Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Baud Rate Run Control bit Clear to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator. Transmission Baud rate Generator Selection bit for UART Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Reception Baud Rate Generator Selection bit for UART Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator. Baud Rate Speed Control bit for UART Clear to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator. Baud Rate Source Select bit in Mode 0 for UART 6 - 5 - 4 BRR 3 TBCK 2 RBCK 1 SPD 0 SRC Clear to select FOSC/12 as the Baud Rate Generator (FOSC/6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0. Reset value = XXX0 0000b 33 4191C–8051–02/08 AT8xC5112 Serial Port Interface (SPI) Features The Serial Peripheral Interface (SPI) module which allows full-duplex, synchronous, serial communication between the MCU and peripheral devices, including other MCUs. Features of the SPI module include the following: • • • • • • Full-duplex, three-wire synchronous transfers Master operation Eight programmable Master clock rates Serial clock with programmable polarity and phase Master Mode fault error flag with MCU interrupt capability Write collision flag protection Signal Description Figure 12 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus is made of three wires connecting all the devices: Figure 1. Typical SPI bus MISO MOSI SCK SS 0 1 2 3 Slave 1 MISO MOSI SCK SS VDD Master PORT MISO MOSI SCK SS Slave 4 MISO MOSI SCK SS Slave 3 Slave 2 The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS pins of the Slave devices. Master Output Slave Input (MOSI) This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last. This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines. Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave device by software through port 34 4191C–8051–02/08 Master Input Slave Output (MISO) SPI Serial Clock (SCK) Slave Select (SS) MISO MOSI SCK SS pins (see Figure 12). To prevent bus conflicts on the MISO line, only one slave should be selected at a time by the Master for a transmission. In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and SCK (see Error Conditions). Baud Rate In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of seven clock rates resulting from the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128, or an external clock. Table 28 gives the different clock rates selected by SPR2:SPR1:SPR0. Table 1. SPI Master Baud Rate Selection SPR2:SPR1:SPR0 000 001 010 011 100 101 110 111 Clock Rate FCkIdle /2 FCkIdle /4 FCkIdle/8 FCkIdle/16 FCkIdle /32 FCkIdleH /64 FCkIdle /128 External clock Baud Rate Divisor (BD) 2 4 8 16 32 64 128 Output of BRG 35 AT8xC5112 4191C–8051–02/08 AT8xC5112 Functional Description Figure 13 shows a detailed structure of the SPI module. Figure 2. SPI Module Block Diagram Internal Bus SPDAT CkIdle Shift Register 7 6 5 4 3 2 1 0 Clock Divider /2 /4 /8 /16 /32 /64 /128 Receive Data Register Pin Control Logic M S MOSI MISO External Clk Clock Select Clock Logic SCK SS SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0 SPCON SPI Interrupt Request SPI Control 8-bit Bus 1-bit Signal SPSTA SPIF WCOL - MODF - - - - Operating Modes The Serial Peripheral Interface can be configured as Master mode only. The configuration and initialization of the SPI module is made through one register: • • • • The Serial Peripheral CONtrol register (SPCON) SPCON The Serial Peripheral STAtus register (SPSTA) The Serial Peripheral DATa register (SPDAT) Once the SPI is configured, the data exchange is made using: During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in synchronized with the same clock (Figure 14). 36 4191C–8051–02/08 Figure 3. Full-Duplex Master-slave Interconnection 8-bit Shift register MISO MOSI MISO MOSI SCK 8-bit Shift register SPI Clock Generator SCK SS VDD SS VSS Master MCU Slave MCU Master Mode The SPI operates in Master mode. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT. When the pin SS is pulled down during a transmission, the data is interrupted and when the transmission is established again, the data present in the SPDAT is present. Transmission Formats Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock POLarity (CPOL ( 1) ) and the Clock PHAse (CPHA(1)). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 15 and Figure 16). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device. Figure 4. Data Transmission Format (CPHA = 0) SCK Cycle Number SPEN (Internal) 1 2 3 4 5 6 7 8 SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB 1. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’). 37 AT8xC5112 4191C–8051–02/08 AT8xC5112 Figure 16 shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 17). This format may be preferable in systems having only one Master and only one Slave driving the MISO data line. Figure 5. Data Transmission Format (CPHA = 1) SCK Cycle Number SPEN (Internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture Point MSB MSB bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 LSB LSB 1 2 3 4 5 6 7 8 Figure 15 shows the first SCK edge is the MSB capture strobe. Therefore, the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each byte transmitted (Figure 17). Figure 6. CPHA/SS Timing MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) Byte 1 Byte 2 Byte 3 38 4191C–8051–02/08 Error Conditions Mode Fault (MODF) The following flags in the SPSTA signal SPI error conditions: Mode Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with the actual mode of the device. MODF is set to warn that there may be a multi-master conflict for system control. In this case, the SPI system is affected in the following ways: • • • An SPI receiver/error CPU interrupt request is generated. The SPEN bit in SPCON is cleared. This disables the SPI. The MSTR bit in SPCON is cleared. The MODF flag is set when the SS signal becomes ’0’. However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there is no way that another Master is attempting to drive the network. In this case, clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared. Write Collision (WCOL) A Write Collision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit sequence. WCOL does not cause an interruption, and the transfer continues uninterrupted. Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT. Overrun Condition An overrun condition occurs when the Master device tries to send several data bytes and the Slave device has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost. This condition is not detected by the SPI peripheral. Interrupts Two SPI status flags can generate a CPU interrupt request: Table 2. SPI Interrupts Flag SPIF (SP data transfer) MODF (Mode Fault) Request SPI Transmitter Interrupt request SPI Receiver/Error Interrupt Request (if SSDIS = ’0’) Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF bit generates transmitter CPU interrupt requests. Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode of the SPI. MODF generates receiver/error CPU interrupt requests. 39 AT8xC5112 4191C–8051–02/08 AT8xC5112 Figure 18 gives a logical view of the above statements. Figure 7. SPI Interrupt Requests Generation SPIF SPI Transmitter CPU Interrupt Request SPI Receiver/Error CPU Interrupt Request SSDIS SPI CPU Interrupt Request MODF 40 4191C–8051–02/08 Registers There are three registers in the module that provide control, status and data storage functions. These registers are described in the following paragraphs. The Serial Peripheral Control Register does the following: • • • Selects one of the Master clock rates Selects serial clock polarity and phase Enables the SPI module Serial Peripheral Control Register (SPCON) Table 30 describes this register and explains the use of each bit: Table 3. Serial Peripheral Control Register 7 SPR2 Bit Number 7 6 SPEN Bit Mnemonic SPR2 5 – 4 – 3 CPOL 2 CPHA 1 SPR1 0 SPR0 R/W Mode RW Description Serial Peripheral Rate 2 Bit with SPR1 and SPR0 define the clock rate Serial Peripheral Enable 6 SPEN RW Clear to disable the SPI interface Set to enable the SPI interface 5 - RW Reserved Leave this Bit at 0. Reserved Leave this Bit at 1. Clock Polarity 4 - RW 3 CPOL RW Clear to have the SCK set to ’0’ in idle state Set to have the SCK set to ’1’ in idle low Clock Phase 2 CPHA RW Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL) Set to have the data sampled when the SPSCK returns to idle state (see CPOL) Serial Peripheral Rate (SPR2:SPR1:SPR0) 000: FCkIdle /2 1 SPR1 RW 001: FCkIdle /4 010: FCkIdle /8 011: FCkIdle /16 100: FCkIdle /32 0 SPR0 RW 101: FCkIdle /64 110: FCkIdle /128 111: External clock, output of BRG Reset value = 00010100b 41 AT8xC5112 4191C–8051–02/08 AT8xC5112 Serial Peripheral Status Register (SPSTA) The Serial Peripheral Status Register contains flags to signal the following conditions. • • • Data transfer complete Write collision Inconsistent logic level on SS pin (mode fault error) Table 31 describes the SPSTA register and explains the use of every bit in the register: Table 4. Serial Peripheral Status and Control Register 7 SPIF Bit Number 6 WCOL Bit Mnemonic 5 R/W Mode 4 MODF 3 2 1 0 - Description Serial Peripheral data transfer flag 7 SPIF R Cleared by hardware to indicate data that transfer is in progress or has been approved by a clearing sequence. Set by hardware to indicate that the data transfer has been completed. Write Collision flag 6 WCOL R Cleared by hardware to indicate that no collision has occurred or has been approved by a clearing sequence. Set by hardware to indicate that a collision has been detected. 5 - RW Reserved The value read from this bit is indeterminate. Do not set this bit Mode Fault 4 MODF R Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been approved by a clearing sequence. Set by hardware to indicate that the SS pin is at inappropriate logic level 3 - RW Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit Reserved The value read from this bit is indeterminate. Do not set this bit 2 - RW 1 - RW 0 - RW Reset value = 00X0XXXXb 42 4191C–8051–02/08 Serial Peripheral Data Register (SPDAT) The Serial Peripheral Data Register (Table 32) is a read/write buffer for the receive data register. A write to SPDAT places data directly into the shift register. No transmit buffer is available in this model. A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register. Table 5. Serial Peripheral Data Register 7 R7 6 R6 5 R5 4 R4 3 R3 2 R2 1 R1 0 R0 Reset value = XXXX XXXXb R7:R0: Receive data bits SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange. However, special care should be taken when writing to them while a transmission is on-going: • • • • • Do not change SPR2, SPR1 and SPR0 Do not change CPHA and CPOL Do not change MSTR Clearing SPEN would immediately disable the peripheral Writing to the SPDAT will cause an overflow 43 AT8xC5112 4191C–8051–02/08 AT8xC5112 Analog-to-Digital Converter (ADC) This section describes the on-chip 10-bit analog-to-digital converter of the T89C51RB2/RC2. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC to select one of the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-cascaded potentiometric ADC. Three kind of conversions are available: • • • Standard conversion (7-8 bits). Precision conversion (8-9 bits). Accurate conversion (10 bits). For the precision conversion, set bits PSIDLE and ADSST in ADCON register to start the conversion. The chip is in a pseudo-idle mode, the CPU doesn’t run but the peripherals are always running. This mode allows digital noise to be lower, to ensure precise conversion. For the accurate conversion, set bits QUIETM and ADSST in ADCON register to start the conversion. The chip is in a quiet mode, the AD is the only peripheral running. This mode allows digital noise to be as low as possible, to ensure high precision conversion. For these modes it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip. If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended. Features • • • • • • • • • • 8 channels with multiplexed inputs 10-bit cascaded potentiometric ADC Conversion time down to 10 micro-seconds Zero Error (offset) ± 2 LSB max External Positive Reference Voltage Range 2.4 to VCC ADCIN Range 0 to VCC Integral non-linearity typical 1 LSB, max. 2 LSB (with 0.9*VCC