AT87C54X2-3CSUM

Features • • • • • • • • 80C52 Compatible 8051 pin and instruction compatible Four 8-bit I/O ports Three 16-bit timer/counters 256 bytes scratchpad RAM High-Speed Architecture 40 MHz @ 5V, 30MHz @ 3V X2 Speed Improvement capability (6 clocks/machine cycle) – 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to – 60 MHz @ 5V, 40 MHz @ 3V) Dual Data Pointer On-chip ROM/EPROM (16K-bytes, 32K-bytes) Programmable Clock Out and Up/Down Timer/Counter 2 Hardware Watchdog Timer (One-time enabled with Reset-Out) Asynchronous port reset Interrupt Structure with 6 Interrupt sources 4 level priority interrupt system Full duplex Enhanced UART Framing error detection Automatic address recognition Low EMI (inhibit ALE) Power Control modes Idle mode Power-down mode Power-off Flag Once mode (On-chip Emulation) Power supply: 4.5-5.5V, 2.7-5.5V Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85 oC) Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 F1, CQPJ44 (window), CDIL40 (window) • • • • • • • • • • • • • • • • • • • • 8-bit CMOS Microcontroller 16/32 Kbytes ROM/OTP TS80C54/58X2 TS87C54/58X2 AT80C54/58X2 AT87C54/58X2 1. Description TS80C54/58X2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS8 0C54/58X2 retains a ll fe atures of the Atmel 80 C51 with e xtend ed ROM/EPROM capacity (16/32 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C54/58X2 a Hardware Watchdog Timer, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a X2 speed improvement mechanism. The fully static design of the TS80C54/58X2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. Rev. 4431E–8051–04/06 The TS80C54/58X2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. PDIL40 PLCC44 PQFP44 F1 VQFP44 1.4 TS80C54X2 TS80C58X2 TS87C54X2 TS87C58X2 ROM (bytes) 16k 32k 0 0 EPROM (bytes) 0 0 16k 32k 2. Block Diagram T2EX (1) P3 RxD TxD Vcc Vss T2 (1) Watch Dog (2) (2) XTAL1 XTAL2 ALE/ PROG PSEN CPU EA/VPP RD WR (2) (2) Timer 0 Timer 1 INT Ctrl Parallel I/O Ports Port 0 Port 1 Port 2 Port 3 EUART RAM 256x8 ROM /EPROM 16/32Kx8 Timer2 C51 CORE IB-bus (2) (2) T0 RESET T1 (2) (2) P1 INT0 INT1 P0 P2 (1): Alternate function of Port 1 (2): Alternate function of Port 3 2 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 4. SFR Mapping The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories: • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 • I/O port registers: P0, P1, P2, P3 • Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H • Serial I/O port registers: SADDR, SADEN, SBUF, SCON • Power and clock control registers: PCON • HDW Watchdog Timer Reset: WDTRST, WDTPRG • Interrupt system registers: IE, IP, IPH • Others: AUXR, CKCON 3 4431E–8051–04/06 Table 4-1. Bit addressable 0/8 1/9 All SFRs with their address and their reset value Non Bit addressable 2/A 3/B 4/C 5/D 6/E 7 /F F8h F0h B 0000 0000 FFh F7h E8h E0h ACC 0000 0000 EFh E7h D8h D0h PSW 0000 0000 T2CON 0000 0000 T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 DFh D7h C8h C0h CFh C7h B8h IP XX00 0000 SADEN 0000 0000 IPH XX00 0000 SADDR 0000 0000 AUXR1 XXXX 0XX0 SBUF XXXX XXXX WDTRST XXXX XXXX WDTPRG XXXX X000 BFh B0h P3 1111 1111 B7h A8h IE 0X00 0000 AFh A0h P2 1111 1111 A7h 98h SCON 0000 0000 9Fh 90h P1 1111 1111 97h TMOD 0000 0000 SP 0000 0111 1/9 88h TCON 0000 0000 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B TH0 0000 0000 TH1 0000 0000 AUXR XXXX XXX0 CKCON XXXX XXX0 PCON 00X1 0000 8Fh 80h P0 1111 1111 0/8 87h 4/C 5/D 6/E 7 /F reserved 4 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 5. Pin Configuration P1.0 / T2 P1.1 / T2EX P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0 / A0 VSS1/NIC* P1.1/T2EX P0.2/AD2 P0.3/AD3 39 38 37 36 35 34 33 32 31 30 29 P0.0/AD0 P0.1/AD1 P1.0/T2 P0.1 / A1 P0.2 / A2 P0.3 / A3 P0.4 / A4 P0.5 / A5 P0.6 / A6 P0.7 / A7 EA/VPP ALE/PROG PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13 P2.4 / A12 P2.3 / A11 P2.2 / A10 P2.1 / A9 P2.0 / A8 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 P1.4 P1.3 P1.2 6 5 4 3 2 1 44 43 42 41 40 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 PDIL/ CDIL40 PLCC/CQPJ 44 18 19 20 21 22 23 24 25 26 27 28 P3.6/WR P2.2/A10 P2.3/A11 P2.4/A12 NIC* P2.0/A8 P3.7/RD XTAL2 P2.1/A9 XTAL1 VSS VSS1/NIC* P1.1/T2EX P0.0/AD0 P0.1/AD1 P0.2/AD2 44 43 42 41 40 39 38 37 36 35 34 P1.5 P1.6 P1.7 RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA/VPP NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 PQFP44 F1 VQFP44 1.4 12 13 14 15 16 17 18 19 20 21 22 P3.6/WR P2.2/A10 P2.3/A11 XTAL1 P3.7/RD P2.1/A9 P2.0/A8 XTAL2 P2.4/A12 NIC* VSS *NIC: No Internal Connection P0.3/AD3 P1.0/T2 VCC P1.4 P1.3 P1.2 VCC 5 4431E–8051–04/06 Table 5-1. Pin Description for 40/44 pin packages PIN NUMBER TYPE MNEMONIC VSS Vss1 VCC P0.0-P0.7 DIL 20 LCC 22 1 VQFP 1.4 16 39 38 37-30 I I I I/O Ground: 0V reference Name And Function Optional Ground: Contact the Sales Office for ground connection. Power Supply: This is the power supply voltage for normal, idle and power-down operation Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 pins must be polarized to Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM programming. External pull-ups are required during program verification during which P0 outputs the code bytes. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pull-ups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for Port 1 include: 40 39-32 44 43-36 P1.0-P1.7 1-8 2-9 40-44 1-3 I/O 1 2 P2.0-P2.7 21-28 2 3 24-31 40 41 18-25 I/O I I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pull-ups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 for A8 to A13 P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pull-ups. Some Port 3 pin P3.4 receive the high order address bits during EPROM programming and verification for TS8xC58X2 devices. Port 3 also serves the special features of the 80C51 family, as listed below. 10 11 12 13 14 15 16 17 11 13 14 15 16 17 18 19 5 7 8 9 10 11 12 13 I O I I I I O O RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe P3.4 also receives A14 during TS87C58X2 EPROM Programming. Reset 9 10 4 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. 6 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Table 5-1. Pin Description for 40/44 pin packages PIN NUMBER TYPE MNEMONIC MNEMONIC ALE/PROG 30 DIL LCC VQFP 1.4 TYPE 27 O (I) NAME AND FUNCTION Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. Program Store ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H and 3FFFH (54X2) or 7FFFH (58X2). If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH (54X2) or 7FFFH (58X2). This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. If security level 1 is programmed, EA will be internally latched on Reset. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier Name And Function PIN NUMBER 33 PSEN 29 32 26 O EA/VPP 31 35 29 I XTAL1 19 21 15 I XTAL2 18 20 14 O 7 4431E–8051–04/06 6. TS80C54/58X2 Enhanced Features In comparison to the original 80C52, the TS80C54/58X2 implements some new features, which are: • The X2 option. • The Dual Data Pointer. • The Watchdog. • The 4 level interrupt priority system. • The power-off flag. • The ONCE mode. • The ALE disabling. • Some enhanced features are also located in the UART and the timer 2. 6.1 X2 Feature The TS80C54/58X2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following advantages: • Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power. • Save power consumption while keeping same CPU power (oscillator power saving). • Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes. • Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software. 6.1.1 Description The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 6-2. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode switching waveforms. Figure 6-1. Clock Generation Diagram XTAL1 FXTAL 2 XTAL1:2 0 1 FOSC X2 state machine: 6 clock cycles. CPU control CKCON reg 8 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Figure 6-2. Mode Switching Waveforms XTAL1 XTAL1:2 X2 bit CPU clock STD Mode X2 Mode STD Mode The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature (X2 mode). CAUTION In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals using clock frequency as time reference (UART, timers) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate. 9 4431E–8051–04/06 Table 6-1. CKCON Register CKCON - Clock Control Register (8Fh) 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. CPU and peripheral clock bit Clear to select 12 clock periods per machine cycle (STD mode, FOSC =FXTAL/2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC =FXTAL). 5 4 3 2 1 0 X2 7 Bit Number 7 6 5 4 3 2 1 0 X2 Reset Value = XXXX XXX0b Not bit addressable For further details on the X2 fe ature, please refer to ANM072 ava ilable on the web (http://www.atmel.com) 10 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 7. Dual Data Pointer Register Ddptr The additional data pointer can be used to speed up code execution and reduce code size in a number of ways. The dual DPTR structure is a way by which the chip will specify the address of an external data memory location. There are two 16-bit DPTR registers that address the external memory, and a single bit called D PS = AUXR1/bit0 (See Table 7-1.) that allows the program code to switch between them (Refer to Figure 7-1). Figure 7-1. Use of Dual Pointer External Data Memory 7 0 DPS DPTR1 DPTR0 AUXR1(A2H) DPH(83H) DPL(82H) 11 4431E–8051–04/06 Table 7-1. 7 Bit Number 7 6 5 4 3 2 1 AUXR1: Auxiliary Register 1 6 Bit Mnemonic GF3 0 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. This bit is a general purpose user flag Reserved Always stuck at 0. Reserved The value read from this bit is indeterminate. Do not set this bit. Data Pointer Selection Clear to select DPTR0. Set to select DPTR1. 5 4 3 GF3 2 0 1 0 DPS 0 DPS Reset Value = XXXX 00X0 Not bit addressable User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 12 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 7.1 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’ pointer and the other one as a "destination" pointer. ASSEMBLY LANGUAGE ; Block move using dual data pointers ; D estroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added ; 00A2 AUXR1 EQU 0A2H ; 0000 909000 MOV DPTR,#SOURCE 0003 05A2 INC AUXR1 0005 90A000 MOV DPTR,#DEST 0008 LOOP: 0008 05A2 INC AUXR1 000A E0 MOVX A,@DPTR 000B A3 INC DPTR 000C 05A2 INC AUXR1 000E F0 MOVX @DPTR,A 000F A3 INC DPTR 0010 70F6 JNZ LOOP 0012 05A2 INC AUXR1 ; address of SOURCE ; switch data pointers ; address of DEST ; switch data pointers ; get a byte from SOURCE ; increment SOURCE address ; switch data pointers ; write the byte to DEST ; increment DEST address ; check for 0 terminator ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state. 13 4431E–8051–04/06 8. Timer 2 The timer 2 in the TS80C54/58X2 is compatible with the timer 2 in the 80C52. It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in cascade. It is controlled by T2CON register (See Table 8-1) and T2MOD register (See Table 8-2). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects FOSC/12 (timer operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description. Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of Capture and Baud Rate Generator Modes. In TS80C54/58X2 Timer 2 includes the following enhancements: • Auto-reload mode with up or down counter • Programmable clock-output 8.1 Auto-Reload Mode The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in Figure 8-1. In this mode the T2EX pin controls the direction of count. When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2. When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh into the timer registers. The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution 14 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Figure 8-1. Auto-Reload Mode Up/Down Counter (DCEN = 1) XTAL1 FXTAL FOSC T2 (DOWN COUNTING RELOAD VALUE) FFh FFh (8-bit) (8-bit) (UP COUNTING RELOAD VALUE) 8.1.1 Programmable Clock-Output In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 8-2) . The input clock increments TL2 at frequency F OSC/2. The timer repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system oscillator frequency and the value in the RCAP2H and RCAP2L registers : For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz (FOSC/216) to 4 MHz (FOSC/4). The generated clock signal is brought out to T2 pin (P1.0). Timer 2 is programmed for the clock-out mode as follows: • Set T2OE bit in T2MOD register. • Clear C/T2 bit in T2CON register. • Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers. 4431E–8051–04/06 – - ------------------------------------------- = -------------------------------------------- 4 × ( 65536 L P A CR H P A C R cs o F )edom 2X ni 6:( :12 TL2 (8-bit) 0 1 C/T2 T2CONreg TR2 T2CONreg T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN TOGT2CONreg EXF2 TH2 (8-bit) TF2 T2CONreg TIMER 2 INTERRUPT RCAP2L RCAP2H (8-bit) (8-bit) y c n euq e r F tuO – k co l C 2 ⁄ 2) 15 • Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. • To start the timer, set TR2 run control bit in T2CON register. It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers. Figure 8-2. Clock-Out Mode C/T2 = 0 XTAL1 :2 T2 Q D T2OE T2MOD reg T2EX EXEN2 T2CON reg EXF2 T2CON reg INTERRUPT 16 AT/TS8xC54/8X2 4431E–8051–04/06 2 REMIT )edom 2X ni 1:( TR2 T2CON reg TL2 (8-bit) TH2 (8-bit) OVERFLOW RCAP2L (8-bit) Toggle RCAP2H (8-bit) AT/TS8xC54/8X2 Table 8-1. 7 TF2 Bit Number 7 T2CON Register T2CON - Timer 2 Control Register (C8h) 6 EXF2 Bit Mnemonic TF2 Description Timer 2 overflow Flag Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Timer 2 External Flag Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1) Receive Clock bit Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Transmit Clock bit Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Timer 2 External Enable bit Clear to ignore events on T2EX pin for timer 2 operation. Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to clock the serial port. Timer 2 Run control bit Clear to turn off timer 2. Set to turn on timer 2. Timer/Counter 2 select bit Clear for timer operation (input from internal clock system: FOSC ). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. Timer 2 Capture/Reload bit If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1. 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 C/T2# 0 CP/RL2# Reset Value = 0000 0000b Bit addressable 17 4431E–8051–04/06 Table 8-2. 7 Bit Number 7 6 5 4 3 2 T2MOD Register T2MOD - Timer 2 Mode Control Register (C9h) 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 Output Enable bit Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output. Down Counter Enable bit Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter. 5 4 3 2 1 T2OE 0 DCEN 1 T2OE 0 DCEN Reset Value = XXXX XX00b Not bit addressable 18 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 9. TS80C54/58X2 Serial I/O Port The serial I/O port in the TS80C54/58X2 is compatible with the serial I/O port in the 80C52. It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously and at different baud rates Serial I/O port includes the following enhancements: • Framing error detection • Automatic address recognition 9.1 Framing Error Detection Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1). Figure 9-1. Framing Error Block Diagram SM0/FE SM1 SM2 REN TB8 RB8 TI RI SCON (98h) Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1) SM0 to UART mode control (SMOD = 0) SMOD1SMOD0 POF GF1 GF0 PD IDL PCON (87h) To UART framing error control When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table 9-3.) bit is set. Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 92. and Figure 9-3.). Figure 9-2. RXD Start bit RI SMOD0=X FE SMOD0=1 UART Timings in Mode 1 D0 D1 D2 D3 D4 D5 D6 D7 Stop bit Data byte 19 4431E–8051–04/06 Figure 9-3. RXD UART Timings in Modes 2 and 3 D0 Start bit D1 D2 D3 D4 D5 D6 D7 D8 Ninth Stop bit bit Data byte RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 9.1.1 Automatic Address Recognition The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled (SM2 bit in SCON register is set). Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the serial port to examine the address of each incoming command frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU is not interrupted by command frames addressed to other devices. If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect). 9.1.2 Given Address Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be 1111 1111b. For example: SADDR SADEN Given 0101 0110b 1111 1100b 0101 01XXb 20 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 The following is an example of how to use given addresses to address different slaves: Slave A: SADDR SADEN Given SADDR SADEN Given SADDR SADEN Given 1111 0001b 1111 1010b 1111 0X0Xb 1111 0011b 1111 1001b 1111 0XX1b 1111 0010b 1111 1101b 1111 00X1b Slave B: Slave C: The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b). 9.1.3 Broadcast Address A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR SADEN Broadcast =SADDR OR SADEN 0101 0110b 1111 1100b 1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN 1111 1010b Broadcast 1111 1X11b, SADDR 1111 0011b SADEN 1111 1001b Broadcast 1111 1X11B, SADDR= 1111 0010b SADEN 1111 1101b Broadcast 1111 1111b Slave B: Slave C: For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh. 9.1.4 Reset Addresses On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition. 21 4431E–8051–04/06 Table 9-1. 7 SADEN - Slave Address Mask Register (B9h) 6 5 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable Table 9-2. 7 SADDR - Slave Address Register (A9h) 6 5 4 3 2 1 0 Reset Value = 0000 0000b Not bit addressable 22 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Table 9-3. 7 FE/SM0 Bit Number SCON Register SCON - Serial Control Register (98h) 6 SM1 Bit Mnemonic Description Framing Error bit (SMOD0=1) Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. SMOD0 must be set to enable access to the FE bit SM0 Serial port Mode bit 0 Refer to SM1 for serial port mode selection. SMOD0 must be cleared to enable access to the SM0 bit Serial port Mode bit 1 SM0 SM1Mode Description Baud Rate Shift RegisterFXTAL/12 (/6 in X2 mode) 8-bit UARTVariable 9-bit UARTFXTAL/64 or FXTAL/32 (/32, /16 in X2 mode) 9-bit UARTVariable 5 SM2 4 REN 3 TB8 2 RB8 1 TI 0 RI 7 FE 6 SM1 0 0 1 1 0 1 0 1 0 1 2 3 5 SM2 Serial port Mode 2 bit / Multiprocessor Communication Enable bit Clear to disable multiprocessor communication feature. Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should be cleared in mode 0. Reception Enable bit Clear to disable serial reception. Set to enable serial reception. Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3. 4 REN 3 TB8 Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit. Receiver Bit 8 / Ninth bit received in modes 2 and 3 Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used. Transmit Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other modes. Receive Interrupt flag Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in the other modes. 2 RB8 1 TI 0 RI Reset Value = 0000 0000b Bit addressable 23 4431E–8051–04/06 Table 9-4. Table 9-5. 7 SMOD1 Bit Number 7 PCON Register PCON - Power Control Register (87h) 6 SMOD0 Bit Mnemonic SMOD1 Description Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL 6 SMOD0 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset Value = 00X1 0000b Not bit addressable Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit. 24 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 10. Interrupt System The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown in Figure 10-1. Figure 10-1. Interrupt Control System IPH, IP 3 INT0 IE0 0 3 TF0 0 3 INT1 IE1 0 3 TF1 0 RI TI TF2 EXF2 3 0 3 0 Interrupt polling sequence, decreasing from high to low priority High priority interrupt Individual Enable Global Disable Low priority interrupt Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt Enable register (See Table 10-2.). This register also contains a global disable bit, which must be cleared to disable all interrupts at once. Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Priority High register (See Table 10-4.). shows the bit values and priority levels associated with each combination. Table 10-1. Priority Level Bit Values IPH.x 0 0 1 1 IP.x 0 1 0 1 Interrupt Level Priority 0 (Lowest) 1 2 3 (Highest) A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. 25 4431E–8051–04/06 If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence. Table 10-2. 7 EA Bit Number Bit Mnemonic Description Enable All interrupt bit Clear to disable all interrupts. S et to enable all interrupts. If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt enable bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 overflow interrupt Enable bit Clear to disable timer 2 overflow interrupt. S et to enable timer 2 overflow interrupt. Serial port Enable bit Clear to disable serial port interrupt. S et to enable serial port interrupt. Timer 1 overflow interrupt Enable bit Clear to disable timer 1 overflow interrupt. S et to enable timer 1 overflow interrupt. External interrupt 1 Enable bit Clear to disable external interrupt 1. Set to enable external interrupt 1. Timer 0 overflow interrupt Enable bit Clear to disable timer 0 overflow interrupt. S et to enable timer 0 overflow interrupt. External interrupt 0 Enable bit Clear to disable external interrupt 0. Set to enable external interrupt 0. IE Register IE - Interrupt Enable Register (A8h) 6 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 7 EA 6 - 5 ET2 4 ES 3 ET1 2 EX1 1 ET0 0 EX0 Reset Value = 0X00 0000b Bit addressable 26 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Table 10-3. 7 Bit Number 7 6 5 4 3 2 1 0 Bit Mnemonic PT2 PS PT1 PX1 PT0 PX0 Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 overflow interrupt Priority bit Refer to PT2H for priority level. Serial port Priority bit Refer to PSH for priority level. Timer 1 overflow interrupt Priority bit Refer to PT1H for priority level. External interrupt 1 Priority bit Refer to PX1H for priority level. Timer 0 overflow interrupt Priority bit Refer to PT0H for priority level. External interrupt 0 Priority bit Refer to PX0H for priority level. IP Register IP - Interrupt Priority Register (B8h) 6 5 PT2 4 PS 3 PT1 2 PX1 1 PT0 0 PX0 Reset Value = XX00 0000b Bit addressable 27 4431E–8051–04/06 Table 10-4. 7 Bit Number 7 6 IPH Register IPH - Interrupt Priority High Register (B7h) 6 Bit 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H Mnemonic - Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Timer 2 overflow interrupt Priority High bit PT2H PT2 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Serial port Priority High bit PSH PS Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 1 overflow interrupt Priority High bit PT1H PT1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 1 Priority High bit P X1H PX1 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest Timer 0 overflow interrupt Priority High bit PT0H PT0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest External interrupt 0 Priority High bit P X0H PX0 Priority Level 0 0 Lowest 0 1 1 0 1 1 Highest 5 PT2H 4 PSH 3 PT1H 2 PX1H 1 PT0H 0 PX0H Reset Value = XX00 0000b Not bit addressable 28 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 11. Idle mode An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was activated. ALE and PSEN hold at logic high levels. There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to be executed will be the one following the instruction that put the device into idle. The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can examine the flag bits. The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running, the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset. 11.1 Power-Down Mode To save maximum power, a power-down mode can be invoked by software (Refer to Table 9-4., PCON register). In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. VCC can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from power-down. To properly terminate powerdown, the reset or external interrupt should not be executed before VCC is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 11-1. When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power down exit will be completed when the first input will be released. In this case the higher priority interrupt service routine is executed. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction that put TS80C54/58X2 into power-down mode. 29 4431E–8051–04/06 Figure 11-1. Power-Down Exit Waveform INT0 INT1 XTAL1 Active phase Power-down phase Oscillator restart phase Active phase Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect the SFRs. Exit from power-down by either reset or external interrupt does not affect the internal RAM content. NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is not entered. Table 11-1. The state of ports during idle and power-down modes Program Memory Internal External Internal External Mode Idle Idle Power Down Power Down ALE 1 1 0 0 PSEN 1 1 0 0 PORT0 Port Data* Floating Port Data* Floating PORT1 Port Data Port Data Port Data Port Data PORT2 Port Data Address Port Data Port Data PORT3 Port Data Port Data Port Data Port Data 30 AT/TS8xC54/8X2 4431E–8051–04/06 .gnitaolf trop evael lli w leveL "eno" A .level "orez" a ecrof nac 0 tro P * AT/TS8xC54/8X2 12. Hardware Watchdog Timer The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin. 12.1 Using the WDT To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x TOSC , where TOSC = 1/FOSC . To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset. To have a more powerful WDT, a 27 counter has been added to extend the Time-out capability, ranking from 16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 12-2. (SFR0A7h). Table 12-1. WDTRST Register W DTRST Address (0A6h) 7 Reset value X 6 X 5 X 4 X 3 X 2 X 1 X Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence. 31 4431E–8051–04/06 Table 12-2. 7 T4 Bit Number 7 6 5 4 3 2 1 0 WDTPRG Register W DTPRG Address (0A7h) 6 T3 Bit 5 T2 4 T1 3 T0 2 S2 1 S1 0 S0 Mnemonic T4 T3 T2 T1 T0 S2 S1 S0 WDT Time-out select bit 2 WDT Time-out select bit 1 WDT Time-out select bit 0 S2S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 Reserved Do not try to set or clear this bit. Description Selected Time-out 0 (214 - 1) machine cycles, 16.3 ms @ 12 MHz 1 (215 - 1) machine cycles, 32.7 ms @ 12 MHz 0 (216 - 1) machine cycles, 65.5 ms @ 12 MHz 1 (217 - 1) machine cycles, 131 ms @ 12 MHz 0 (218 - 1) machine cycles, 262 ms @ 12 MHz 1 (219 - 1) machine cycles, 542 ms @ 12 MHz 0 (220 - 1) machine cycles, 1.05 s @ 12 MHz 1 (221 - 1) machine cycles, 2.09 s @ 12 MHz Reset value XXXX X000 12.1.1 WDT during Power Down and Idle In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C54/58X2 is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the WDT just before entering powerdown. In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C54/58X2 while in Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode. 32 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 13. ONCETM Mode (ON Chip Emulation) The ONCE mode facilitates testing and debugging of systems using TS80C54/58X2 without removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the TS80C54/58X2; the following sequence must be exercised: • Pull ALE low while the device is in reset (RST high) and PSEN is high. • Hold ALE low as RST is deactivated. While the TS80C54/58X2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 13-1 shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied. Table 13-1. ALE Weak pull-up External Pin Status during ONCE Mode PSEN Weak pull-up Port 0 Float Port 1 Weak pull-up Port 2 Weak pull-up Port 3 Weak pull-up XTAL1/2 Active 33 4431E–8051–04/06 14. Power-Off Flag The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. A cold start reset is the one induced by VCC switch-on. A warm start reset occurs while VCC is still applied to the device and could be generated for example by an exit from power-down. The power-off flag (POF) is located in PCON register (See Table 14-1.). POF is set by hardware when VCC rises from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type of reset. The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will return indeterminate value. Table 14-1. 7 SMOD1 Bit Number 7 PCON Register PCON - Power Control Register (87h) 6 SMOD0 Bit 5 4 POF 3 GF1 2 GF0 1 PD 0 IDL Mnemonic SMOD1 Description Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 Clear to select SM0 bit in SCON register. Set to to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Clear to recognize next reset type. Set by hardware when VCC r ises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. General purpose Flag Cleared by user for general purpose usage. Set by user for general purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Clear by hardware when interrupt or reset occurs. Set to enter idle mode. 6 SMOD0 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL Reset Value = 00X1 0000b Not bit addressable 34 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 15. Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 15-1. 7 Bit Number 7 6 5 4 3 2 1 AUXR Register AUXR - Auxiliary Register (8Eh) 6 Bit Mnemonic Description Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. ALE Output bit Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches. 5 4 3 2 1 RESERVED 0 AO 0 AO Reset Value = XXXX XXX0b Not bit addressable 35 4431E–8051–04/06 16. TS80C54/58X2 ROM 16.1 ROM Structure The TS80C54/58X2 ROM memory is in three different arrays: • the code array:16/32 Kbytes. • the encryption array:64 bytes. • the signature array:4 bytes. 16.2 ROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 16.2.1 Encryption Array Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 16.2.2 Program Lock Bits The lock bits when programmed according to Table 16-1. will provide different level of protection for the on-chip code and data. Table 16-1. Program Lock bits Program Lock Bits Security level 1 LB1 U LB2 U LB3 U Protection Description No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset. 2 P U U U: unprogrammed P: programmed 16.2.3 Signature bytes The TS80C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 8.3. Verify Algorithm Refer to 17.3.4 16.2.4 36 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 17. TS87C54/58X2 EPROM 17.1 EPROM Structure The TS87C54/58X2 EPROM is divided in two different arrays: • the code array:16/32 Kbytes. • the encryption array:64 bytes. • In addition a third non programmable array is implemented: • the signature array: 4 bytes. 17.2 EPROM Lock System The program Lock system, when programmed, protects the on-chip program against software piracy. 17.2.1 Encryption Array Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state, will return the code in its original, unmodified form. When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a verification routine will display the content of the encryption array. For this reason all the unused code bytes should be programmed with random values. This will ensure program protection. 17.2.2 Program Lock Bits The three lock bits, when programmed according to Table 17-1., will provide different level of protection for the on-chip code and data. Table 17-1. Program Lock bits Program Lock Bits Security level 1 LB1 U LB2 U LB3 U Protection Description No program lock features enabled. Code verify will still be encrypted by the encryption array if programmed. MOVC instruction executed from external program memory returns non encrypted data. MOVC instruction executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the EPROM is disabled. Same as 2, also verify is disabled. Same as 3, also external execution is disabled. 2 P U U 3 4 U U P U U P U: unprogrammed, P: programmed WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. 37 4431E–8051–04/06 17.2.3 Signature bytes The TS87C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described in section 8.3. 17.3 17.3.1 EPROM Programming Set-up modes In order to program and verify the EPROM or to read the signature bytes, the TS87C54/58X2 is placed in specific set-up modes (See Figure 17-1.). Control and program signals must be held at the levels indicated in Table 17-2. 17.3.2 Definition of terms Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4 respectively TS87C54X2, P3.4 (A14) for TS87C58X2). Data Lines:P0.0-P0.7 for D0-D7 Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7. Program Signals:ALE/PROG, EA/VPP. Table 17-2. Mode Program Code data for A0-A14 (P2.5 (A13) for EPROM Set-Up Modes RST PSEN ALE/PR OG EA /VPP P2.6 P2.7 P3.3 P3.6 P3.7 Verify Code data Program Encryption Array Address 0-3Fh Read Signature Bytes Program Lock bit 1 Program Lock bit 2 Program Lock bit 3 38 AT/TS8xC54/8X2 4431E–8051–04/06 1 0 1 0 0 1 1 0 0 1 0 1 1 1 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 1 0 0 V57.21 V57.21 V57.21 V57.21 V57.21 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 AT/TS8xC54/8X2 Figure 17-1. Set-Up Modes Configuration PROGRAM SIGNALS* EA/VPP ALE/PROG VCC P0.0-P0.7 RST PSEN P2.6 P2.7 P3.3 P3.6 P3.7 XTAL1 P1.0-P1.7 P2.0-P2.5, CON TRO L SIGNALS* 4 to 6 MHz VSS GND * See Table 31. for proper value on these inputs 17.3.3 Programming Algorithm The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses applied during byte programming from 25 to 1. To program the TS80C54/58X2 the following sequence must be exercised: • Step 1: Activate the combination of control signals. • Step 2: Input the valid address on the address lines. • Step 3: Input the appropriate data on the data lines. • Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V). • Step 5: Pulse ALE/PROG once. • Step 6: Lower EA/VPP from VPP to VCC Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 17-2.). 17.3.4 Verify algorithm Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of th e p rog ra mmed array will ensure reliable programming of the TS87C54/58X2. P 2.7 is used to enable data output. To verify the TS87C54/58X2 code the following sequence must be exercised: • Step 1: Activate the combination of program and control signals. • Step 2: Input the valid address on the address lines. • Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 17-2.) 4431E–8051–04/06 V5+ D0-D7 A0-A7 A8-A14 39 The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. Figure 17-2. Programming and Verification Signal’s Waveform Programming Cycle A0-A12 D0-D7 Data In s Read/Verify Cycle Data Out μ ALE/PROG 12.75V 5V 0V EA/VPP C ont rol signals 17.4 EPROM Erasure (Windowed Packages Only) Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full functionality. Erasure leaves all the EPROM cells in a 1’s state (FF). 17.4.1 Erasure Characteristics The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15 W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000 μW/cm2 rating for 30 minutes, at a distance of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque label be placed over the window. 18. Signature Bytes The TS87C54/58X2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure for EPROM verify but activate the control lines provided in Table 31. for Read Signature Bytes. Table 18-1. shows the content of the signature byte for the TS80C54/58X2. 40 AT/TS8xC54/8X2 4431E–8051–04/06 001 AT/TS8xC54/8X2 Table 18-1. Signature Bytes Content Contents 58h 57h 37h B7h 3Bh BBh FFh Location 30h 31h 60h 60h 60h 60h 61h Comment Manufacturer Code: Atmel Wireless & Microcontrollers Family Code: C51 X2 Product name: TS80C58X2 Product name: TS87C58X2 Product name: TS80C54X2 Product name: TS87C54X2 Product revision number 41 4431E–8051–04/06 19. Electrical Characteristics 19.1 Absolute Maximum Ratings (1) Ambiant Temperature Under Bias: C = commercial0°C to 70°C I = industrial -40°C to 85°C Storage Temperature-65°C to + 150°C Voltage on VCC to VSS-0.5 V to + 7 V Voltage on VPP to VSS-0.5 V to + 13 V Voltage on Any Pin to VSS-0.5 V to VCC + 0.5 V Power Dissipation1 W(2) 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package. 19.2 Power consumption measurement Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In Atmel new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, Atmel presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc. 19.3 DC Parameters for Standard Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 5 V ± 10%; F = 0 to 40 MHz. Table 19-1. DC Parameters in Standard Voltage Min -0.5 0.2 VCC + 0.9 0.7 VCC (6) Symbol VIL VIH VIH1 VOL Input Low Voltage Parameter Typ Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.3 0.45 1.0 Unit V V V V V V Test Conditions Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST IOL = 100 μA(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) Output Low Voltage, ports 1, 2, 3 42 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Symbol Parameter (6) Min Typ Max 0.3 Unit V V V V V V V V V Test Conditions IOL = 200 μA(4) IOL = 3.2 mA(4) IOL = 7.0 mA(4) IOL = 100 μA(4) IOL = 1.6 mA(4) IOL = 3.5 mA(4) IOH = -10 μA IOH = -30 μA IOH = -60 μA V CC = 5 V ± 10% IOH = -200 μA IOH = -3.2 mA IOH = -7.0 mA VCC = 5 V ± 10% IOH = -100 μA IOH = -1.6 mA IOH = -3.5 mA VCC = 5 V ± 10% VOL1 Output Low Voltage, port 0 0.45 1.0 0.3 VOL2 Output Low Voltage, ALE, PSEN 0.45 1.0 VCC - 0.3 VOH Output High Voltage, ports 1, 2, 3 VCC - 0.7 VCC - 1.5 VCC - 0.3 V V V VOH1 Output High Voltage, port 0 VCC - 0.7 VCC - 1.5 VCC - 0.3 V V V 90 (5) 200 -50 ±10 -650 10 20 (5) 50 1 + 0.4 Freq (MHz) @12MHz 5.8 @16MHz 7.4 kΩ μA μA μA pF μA VOH2 Output High Voltage,ALE, PSEN VCC - 0.7 VCC - 1.5 RRST IIL ILI ITL CIO IPD ICC under RESET RST Pulldown Resistor Logical 0 Input Current ports 1, 2 and 3 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 Capacitance of I/O Buffer Power Down Current Power Supply Current Maximum values, X1 mode: (7) 50 Vin = 0.45 V 0.45 V < Vin < VCC Vin = 2.0 V Fc = 1 MHz TA = 25°C 2.0 V < VCC < 5.5 V(3) mA V CC = 5.5 V(1) ICC operating Power Supply Current Maximum values, X1 mode: (7) 3 + 0.6 Freq (MHz) @12MHz 10.2 @16MHz 12.6 mA V CC = 5.5 V(8) ICC idle Power Supply Current Maximum values, X1 mode: (7) 0.25+0.3 Freq (MHz) @12MHz 3.9 @16MHz 5.1 mA V CC = 5.5 V(2) 43 4431E–8051–04/06 19.4 DC Parameters for Low Voltage TA = 0°C to +70°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. TA = -40°C to +85°C; VSS = 0 V; VCC = 2.7 V to 5.5 V ± 10%; F = 0 to 30 MHz. Table 19-2. DC Parameters for Low Voltage Min -0.5 0.2 VCC + 0.9 0.7 VCC (6) Symbol VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ILI ITL RRST CIO Input Low Voltage Parameter Typ Max 0.2 VCC - 0.1 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V Test Conditions Input High Voltage except XTAL1, RST Input High Voltage, XTAL1, RST Output Low Voltage, ports 1, 2, 3 IOL = 0.8 mA(4) IOL = 1.6 mA(4) IOH = -10 μ A IOH = -40 μ A Vin = 0.45 V 0.45 V < Vin < VCC Vin = 2.0 V Output Low Voltage, port 0, ALE, PSEN (6) Output High Voltage, ports 1, 2, 3 Output High Voltage, port 0, ALE, PSEN Logical 0 Input Current ports 1, 2 and 3 Input Leakage Current Logical 1 to 0 Transition Current, ports 1, 2, 3 RST Pulldown Resistor Capacitance of I/O Buffer 50 90 (5) 0.9 VCC 0.9 VCC -50 ±10 -650 200 10 μA μA μA kΩ pF Fc = 1 MHz TA = 25°C VCC = 2.0 V to 5.5 V(3) VCC = 2.0 V to 3.3 V(3) IPD Power Down Current 20 (5) 10 (5) 50 30 μA ICC under RESET Power Supply Current Maximum values, X1 mode: (7) 1 + 0.2 Freq (MHz) @12MHz 3.4 @16MHz 4.2 mA VCC = 3.3 V(1) ICC operating Power Supply Current Maximum values, X1 mode: (7) 1 + 0.3 Freq (MHz) @12MHz 4.6 @16MHz 5.8 mA VCC = 3.3 V(8) ICC idle Power Supply Current Maximum values, X1 mode: (7) 0.15 Freq (MHz) + 0.2 @12MHz 2 @16MHz 2.6 mA VCC = 3.3 V(2) 1. ICC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 19-5.), VIL = V SS + 0.5 V, VIH = V CC - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = VCC. ICC would be slightly higher if a crystal oscillator used.. 2. Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns, V IL = VSS + 0.5 V, VIH = V CC - 0.5 V; XTAL2 N.C; Port 0 = VCC; EA = RST = VSS (see Figure 19-3.). 3. Power Down I CC is measured with all output pins disconnected; EA = VSS, PORT 0 = VCC; XTAL2 NC.; RST = VSS (see Figure 19-4.). 4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOLs of ALE and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V. A Schmitt Trigger use is not necessary. 44 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V. 6. Under steady state (non-transient) conditions, I OL must be externally limited as follows: Maximum IOL per port pin: 10 mA Maximum IOL per 8-bit port: Port 0: 26 mA Ports 1, 2 and 3: 15 mA Maximum total IOL for all output pins: 71 mA If I OL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 7. For other values, please contact your sales office. 8. Operating I CC is measured with all output pins disconnected; XTAL1 driven with TCLCH, TCHCL = 5 ns (see Figure 19-5.), VIL = V SS + 0.5 V, VIH = V CC - 0.5V; XTAL2 N.C.; EA = Port 0 = VCC; RST = VSS. The internal ROM runs the code 80 FE (label: SJMP label). ICC would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. Figure 19-1. ICC Test Condition, under reset VCC ICC VCC VCC RST (NC) C LOC K SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. P0 EA VCC Figure 19-2. Operating ICC Test Condition VCC ICC VCC P0 RST (NC) C LOC K SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA e slu p h gi h a r et fa s s V = t e s eR VCC 4431E–8051–04/06 s el c y c kc ol c 42 t sa el ta gn iru d 45 Figure 19-3. ICC Test Condition, Idle Mode VCC ICC VCC P0 RST (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS All other pins are disconnected. EA e slup h gi h a re t fa s s V = t e s eR VCC Figure 19-4. ICC Test Condition, Power-Down Mode VCC ICC VCC P0 s el c y c kc ol c 42 t sa el ta gni ru d es lu p h gi h a r et fa s s V = t e s eR Figure 19-5. Clock Signal Waveform for ICC Tests in Active and Idle Modes 46 AT/TS8xC54/8X2 4431E–8051–04/06 se l cy c k co lc 42 t sa e l ta g nirud VCC RST XTAL2 XTAL1 VSS EA (NC) All other pins are disconnected. VCC-0.5V 0.45V TCLCH TCHCL TCLCH = TCHCL = 5ns. 0.7VCC 0.2VCC-0.1 AT/TS8xC54/8X2 19.5 19.5.1 AC Parameters Explanation of the AC Symbols Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters, depending on their positions, stand for the name of a signal or the logical status of that signal. The following is a list of all the characters and what they stand for. Example:TAVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA = 0 to +70°C (commercial temperature range); VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges. TA = -40°C to +85°C (industrial temperature range); VSS = 0 V; VCC = 5 V ± 10%; -M and -V ranges. TA = 0 to +70°C (commercial temperature range); VSS = 0 V; 2.7 V < VCC < 5.5 V; -L range. TA = -40°C to +85°C (industrial temperature range); V SS = 0 V; 2.7 V < VCC < 5.5 V; -L range. Table 19-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN s ignals. Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings will then be degraded. Table 19-3. Load Capacitance versus speed range, in pF -M Port 0 Port 1, 2, 3 ALE / PSEN 100 80 100 -V 50 50 30 -L 100 80 100 Table 19-5., Table 19-8. and Table 19-11. give the description of each AC symbols. Table 19-6., Table 19-9. and Table 19-12. give for each range the AC parameter. T able 19-7., Table 19-10. and Table 19-13. give the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be limited to the corresponding speed grade: Table 19-4. Max frequency for derating formula regarding the speed grade -M X1 mode Freq (MHz) T (ns) 40 25 -M X2 mode 20 50 -V X1 mode 40 25 -V X2 mode 30 33.3 -L X1 mode 30 33.3 -L X2 mode 20 50 Example: TLLIV in X2 mode for a -V part at 20 MHz (T = 1/20E6 = 50 ns): x= 22 (Table 19-7.) T= 50ns TLLIV= 2T - x = 2 x 50 - 22 = 78ns 47 4431E–8051–04/06 19.5.2 External Program Memory Characteristics Table 19-5. Symbol Description Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TPXAV TAVIV TPLAZ Oscillator clock period ALE pulse width Address Valid to ALE Address Hold After ALE ALE to Valid Instruction In ALE to PSEN PSEN Pulse Width PSEN to Valid Instruction In Input Instruction Hold After PSEN Input Instruction FloatAfter PSEN PSEN to Address Valid Address to Valid Instruction In PSEN Low to Address Float Parameter Table 19-6. AC Parameters for Fix Clock -V X2 mode -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv. Min 25 42 12 12 45 9 35 17 60 25 0 0 12 53 10 20 95 10 50 0 10 80 10 78 10 50 30 0 18 122 10 Max Min 50 35 5 5 65 18 75 55 Max -L standard mode 30 MHz Min 33 52 13 13 98 Max ns ns ns ns ns ns ns ns ns ns ns ns Units -M Speed Symbol T TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ 0 18 85 10 15 55 35 40 MHz Min 25 40 10 10 70 Max 30 MHz 60 MHz equiv. Min 33 25 4 4 Max 48 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Table 19-7. Symbol TLHLL TAVLL TLLAX TLLIV TLLPL TPLPH TPLIV TPXIX TPXIZ TAVIV TPLAZ AC Parameters for a Variable Clock: derating formula Type Min Min Min Max Min Min Max Min Max Max Max Standard Clock 2T-x T-x T-x 4T-x T-x 3T-x 3T-x x T-x 5T-x x X2 Clock T-x 0.5 T - x 0.5 T - x 2T-x 0.5 T - x 1.5 T - x 1.5 T - x x 0.5 T - x 2.5 T - x x -M 10 15 15 30 10 20 40 0 7 40 10 -V 8 13 13 22 8 15 25 0 5 30 10 -L 15 20 20 35 15 25 45 0 15 45 10 Units ns ns ns ns ns ns ns ns ns ns ns 19.5.3 External Program Memory Read Cycle Figure 19-6. External Program Memory Read Cycle 12 TCLCL TLHLL ALE TLLIV TLLPL TPLPH PSEN TLLAX TAVLL PORT 0 INSTR IN A0-A7 TAVIV PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 ADDRESS A8-A15 TPLIV TPLAZ TPXIX INSTR IN A0-A7 INSTR IN TPXAV TPXIZ 49 4431E–8051–04/06 19.5.4 External Data Memory Characteristics Table 19-8. Symbol Description Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH RD Pulse Width WR Pulse Width RD to Valid Data In Data Hold After RD Data Float After RD ALE to Valid Data In Address to Valid Data In ALE to WR or RD Address to WR or RD Data Valid to WR Transition Data set-up to WR High Data Hold After WR RD Low to Address Float RD or WR H igh to ALE high Parameter Table 19-9. AC Parameters for a Fix Clock -V X2 mode -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv. Min 135 135 60 0 0 18 98 100 30 47 7 107 9 70 55 80 15 165 17 0 7 27 15 0 35 5 35 165 175 95 45 70 5 155 10 0 45 13 102 0 25 155 160 105 70 103 13 213 18 0 53 Max Min 125 125 95 0 42 222 235 130 Max Min 175 175 137 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns -L standard mode 30 MHz Units Speed -M 40 MHz 30 MHz 60 MHz equiv. Min 85 85 100 Max Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH Min 130 130 Max 0 30 160 165 50 75 10 160 15 0 10 40 100 50 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Table 19-10. AC Parameters for a Variable Clock: derating formula Symbol TRLRH TWLWH TRLDV TRHDX TRHDZ TLLDV TAVDV TLLWL TLLWL TAVWL TQVWX TQVWH TWHQX TRLAZ TWHLH TWHLH Type Min Min Max Min Max Max Max Min Max Min Min Min Min Max Min Max Standard Clock 6T-x 6T-x 5T-x x 2T-x 8T-x 9T-x 3T-x 3T+x 4T-x T-x 7T-x T-x x T-x T+x X2 Clock 3T-x 3T-x 2.5 T - x x T-x 4T -x 4.5 T - x 1.5 T - x 1.5 T + x 2T-x 0.5 T - x 3.5 T - x 0.5 T - x x 0.5 T - x 0.5 T + x -M 20 20 25 0 20 40 60 25 25 25 15 15 10 0 15 15 -V 15 15 23 0 15 35 50 20 20 20 10 10 8 0 10 10 -L 25 25 30 0 25 45 65 30 30 30 20 20 15 0 20 20 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 19.5.5 External Data Memory Write Cycle Figure 19-7. External Data Memory Write Cycle ALE TWHLH PSEN TLLWL TWLWH WR TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 ADDRESS A8-A15 OR SFR P2 TQVWX TQVWH DATA OUT TWHQX 51 4431E–8051–04/06 19.5.6 External Data Memory Read Cycle Figure 19-8. External Data Memory Read Cycle ALE TLLDV TWHLH PSEN TLLWL V D L RT TRLRH RD TLLAX PORT 0 A0-A7 TAVWL PORT 2 ADDRESS OR SFR-P2 TAVDV TRHDZ TRHDX DATA IN TRLAZ ADDRESS A8-A15 OR SFR P2 19.5.7 Serial Port Timing - Shift Register Mode Table 19-11. Symbol Description Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Parameter Serial port clock cycle time Output data set-up to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge to input data valid Table 19-12. AC Parameters for a Fix Clock -V X2 mode -M Speed Symbol TXLXL TQVHX TXHQX TXHDX TXHDV 40 MHz Min 300 200 30 0 117 Max 30 MHz 60 MHz equiv. Min 200 117 13 0 34 Max Min 300 200 30 0 117 Max -V standard mode 40 MHz -L X2 mode 20 MHz 40 MHz equiv. Min 300 200 30 0 117 Max Min 400 283 47 0 200 Max ns ns ns ns ns -L standard mode 30 MHz Units 52 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Table 19-13. AC Parameters for a Variable Clock: derating formula Symbol TXLXL TQVHX TXHQX TXHDX TXHDV Type Min Min Min Min Max Standard Clock 12 T 10 T - x 2T-x x 10 T - x X2 Clock 6T 5T-x T-x x 5 T- x 50 20 0 133 50 20 0 133 50 20 0 133 -M -V -L Units ns ns ns ns ns 19.5.8 Shift Register Timing Waveforms Figure 19-9. Shift Register Timing Waveforms INSTRUCTION ALE 0 1 2 3 4 5 6 7 8 TXLXL CLOCK TQVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI 0 TXHDV TXHQX 1 2 TXHDX 3 4 5 6 7 SET TI SET RI 4431E–8051–04/06 DILAV 53 DILAV DILAV DILAV DILAV DILAV DILAV DILAV 19.5.9 EPROM Programming and Verification Characteristics TA = 21°C to 27°C; VSS = 0V; VCC = 5V ± 10% while programming. VCC = operating range while verifying Table 19-14. EPROM Programming Parameters Symbol VPP IPP 1/TCLCL TAVGL TGHAX TDVGL TGHDX TEHSH TSHGL TGHSL TGLGH TAVQV TELQV TEHQZ Parameter Programming Supply Voltage Programming Supply Current Oscillator Frquency Address Setup to PROG Low Adress Hold after PROG Data Setup to PROG Low 4 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL 48 TCLCL 10 10 90 110 48 TCLCL 48 TCLCL 0 48 TCLCL μs μs μs Min 12.5 Max 13 75 6 Units V mA MHz . Data Hold after PROG (Enable) High to VPP VPP Setup to PROG Low VPP Hold after PROG PROG Width Address to Valid Data ENABLE Low to Data Valid Data Float after ENABLE 19.5.10 EPROM Programming and Verification Waveforms Figure 19-10. EPROM Programming and Verification Waveforms PROGRAMMING P1.0-P1.7 P2.0-P2.5 P 3.4-P3.5* P P0 TDVGL TAVGL ALE/PROG TSHGL TGLGH EA/VPP CONTROL S IGNALS (ENABLE) VCC TEHSH VPP TGHSL VCC TELQV ADDRESS VERIFICATION ADDRESS TAVQV DATA IN TGHDX TGHAX DATA OUT TEHQZ 54 5.3P ot pu :BK46 ,4.3P ot pu :BK23 ,5.2P ot pu :BK61 ,4.2P ot pu :BK8 * AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 19.5.11 External Clock Drive Characteristics (XTAL1) Table 19-15. AC Parameters Symbol TCLCL TCHCX TCLCX TCLCH TCHCL TCHCX/TCLCX Parameter Oscillator Period High Time Low Time Rise Time Fall Time Cyclic ratio in X2 mode 40 Min 25 5 5 5 5 60 Max Units ns ns ns ns ns % 19.5.12 External Clock Drive Waveforms Figure 19-11. External Clock Drive Waveforms 4431E–8051–04/06 HC LC T XC H CT L CL C T X CL C T CCV2.0 V 1.0CC V7.0 LC HC T V 5 .0- V 54 .0 CC V 55 19.5.13 AC Testing Input/Output Waveforms Figure 19-12. AC Testing Input/Output Waveforms AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”. 19.5.14 Float Waveforms Figure 19-13. Float Waveforms For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level occurs. IOL/IOH ≥ ± 20mA. 19.5.15 Clock Waveforms Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. 56 AT/TS8xC54/8X2 4431E–8051–04/06 V 1 .0 + D A O LV V 1.0D A O LV 9 .0+ 1.0- CC V2.0 CC V2.0 D A O LV TAOLF V 1. 0 + V 1 .0- V 54.0 V 5 .0- H OV L OV CC V TUP TUO /TUPN I AT/TS8xC54/8X2 Figure 19-14. Clock Waveforms STATE4 P1P2 STATE5 P1P2 STATE6 P1P2 STATE1 P1P2 STATE2 P1P2 STATE3 P1P2 STATE4 P1P2 STATE5 P1P2 P2 (EXT) MOV DEST PORT (P1, P2, P3) (INCLUDES INT0, INT1, TO, T1) 4431E–8051–04/06 HCTEF YROMEM MARGORP LANRETXE KCOLC TFIHS TROP LAIRES NOITAREPO TROP ELCYC ETIRW ELCYC DAER MOV DEST P0 P1, P2, P3 PINS SAMPLED P1, P2, P3 PINS SAMPLED LANRETNI CLOCK XTAL2 ALE PSEN P0 RD P0 P2 WR P0 P2 THESE SIGNALS ARE NOT ACTIVATED DURING THE EXECUTION OF A MOVX INSTRUCTION DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT DATA SAMPLED FLOAT PCL OUT INDICATES ADDRESS PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) DPL OR Rt FLOAT INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (EVEN IF PROGRAM MEMORY IS INTERNAL) DPL OR Rt OUT DATA OUT INDICATES DPH OR P2 SFR TO PCH TRANSITION PCL OUT (IF PROGRAM MEMORY IS EXTERNAL) OLD DATA P0 PINS SAMPLED NEW DATA P0 PINS SAMPLED RXD SAMPLED RXD SAMPLED TXD (MODE 0) This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin loading. Propagation also varies from output to output and component. Typically though (TA=25 °C fully loaded) RD a nd WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated in the AC specifications. 57 20. Ordering Information Table 20-1. Part Number TS80C54X2xxx-MCA TS80C54X2xxx-MCB TS80C54X2xxx-MCC TS80C54X2xxx-MCE TS80C54X2xxx-VCA TS80C54X2xxx-VCB TS80C54X2xxx-VCC TS80C54X2xxx-VCE TS80C54X2xxx-LCA TS80C54X2xxx-LCB TS80C54X2xxx-LCC TS80C54X2xxx-LCE TS80C54X2xxx-MIA TS80C54X2xxx-MIB TS80C54X2xxx-MIC TS80C54X2xxx-MIE TS80C54X2xxx-VIA TS80C54X2xxx-VIB TS80C54X2xxx-VIC TS80C54X2xxx-VIE TS80C54X2xxx-LIA TS80C54X2xxx-LIB TS80C54X2xxx-LIC TS80C54X2xxx-LIE Possible Ordering Entries Temperature Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Package PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 Packing Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Supply Voltage -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% AT80C54X2zzz-3CSUM AT80C54X2zzz-SLSUM AT80C54X2zzz-RLTUM AT80C54X2zzz-3CSUL AT80C54X2zzz-SLSUL AT80C54X2zzz-RLTUL AT80C54X2zzz-3CSUV AT80C54X2zzz-SLSUV AT80C54X2zzz-RLTUV -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green PDIL40 PLCC44 VQFP44 PDIL40 PLCC44 VQFP44 PDIL40 PLCC44 VQFP44 Stick Stick Tray Stick Stick Tray Stick Stick Tray TS87C54X2-MCA TS87C54X2-MCB 5V ±10% 5V ±10% Commercial Commercial PDIL40 PLCC44 Stick Stick 58 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Part Number TS87C54X2-MCC TS87C54X2-MCE TS87C54X2-VCA TS87C54X2-VCB TS87C54X2-VCC TS87C54X2-VCE TS87C54X2-LCA TS87C54X2-LCB TS87C54X2-LCC TS87C54X2-LCE TS87C54X2-MIA TS87C54X2-MIB TS87C54X2-MIC TS87C54X2-MIE TS87C54X2-VIA TS87C54X2-VIB TS87C54X2-VIC TS87C54X2-VIE TS87C54X2-LIA TS87C54X2-LIB TS87C54X2-LIC TS87C54X2-LIE Supply Voltage 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V Temperature Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Package PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 Packing Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray AT87C54X2-3CSUM AT87C54X2-SLSUM AT87C54X2-RLTUM AT87C54X2-3CSUL AT87C54X2-SLSUL AT87C54X2-RLTUL AT87C54X2-3CSUV AT87C54X2-SLSUV AT87C54X2-RLTUV 5V ±10% 5V ±10% 5V ±10% 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V 5V ±10% 5V ±10% 5V ±10% Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green PDIL40 PLCC44 VQFP44 PDIL40 PLCC44 VQFP44 PDIL40 PLCC44 VQFP44 Stick Stick Tray Stick Stick Tray Stick Stick Tray 59 4431E–8051–04/06 P art Number TS80C58X2xxx-MCA TS80C58X2xxx-MCB TS80C58X2xxx-MCC TS80C58X2xxx-MCE TS80C58X2xxx-VCA TS80C58X2xxx-VCB TS80C58X2xxx-VCC TS80C58X2xxx-VCE TS80C58X2xxx-LCA TS80C58X2xxx-LCB TS80C58X2xxx-LCC TS80C58X2xxx-LCE TS80C58X2xxx-MIA TS80C58X2xxx-MIB TS80C58X2xxx-MIC TS80C58X2xxx-MIE TS80C58X2xxx-VIA TS80C58X2xxx-VIB TS80C58X2xxx-VIC TS80C58X2xxx-VIE TS80C58X2xxx-LIA TS80C58X2xxx-LIB TS80C58X2xxx-LIC TS80C58X2xxx-LIE Supply Voltage -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% Temperature Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Package PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 Packing Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray AT80C58X2zzz-3CSUM AT80C58X2zzz-SLSUM AT80C58X2zzz-RLTUM AT80C58X2zzz-3CSUL AT80C58X2zzz-SLSUL AT80C58X2zzz-RLTUL AT80C58X2zzz-3CSUV AT80C58X2zzz-SLSUV AT80C58X2zzz-RLTUV -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% -5 to +/-10% Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green PDIL40 PLCC44 VQFP44 PDIL40 PLCC44 VQFP44 PDIL40 PLCC44 VQFP44 Stick Stick Tray Stick Stick Tray Stick Stick Tray TS87C58X2-MCA TS87C58X2-MCB TS87C58X2-MCC 5V ±10% 5V ±10% 5V ±10% Commercial Commercial Commercial PDIL40 PLCC44 PQFP44 Stick Stick Tray 60 AT/TS8xC54/8X2 4431E–8051–04/06 AT/TS8xC54/8X2 Part Number TS87C58X2-MCE TS87C58X2-VCA TS87C58X2-VCB TS87C58X2-VCC TS87C58X2-VCE TS87C58X2-LCA TS87C58X2-LCB TS87C58X2-LCC TS87C58X2-LCE TS87C58X2-MIA TS87C58X2-MIB TS87C58X2-MIC TS87C58X2-MIE TS87C58X2-VIA TS87C58X2-VIB TS87C58X2-VIC TS87C58X2-VIE TS87C58X2-LIA TS87C58X2-LIB TS87C58X2-LIC TS87C58X2-LIE Supply Voltage 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 5V ±10% 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V Temperature Range Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Package VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 PDIL40 PLCC44 PQFP44 VQFP44 Packing Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray Stick Stick Tray Tray AT87C58X2-3CSUM AT87C58X2-SLSUM AT87C58X2-RLTUM AT87C58X2-3CSUL AT87C58X2-SLSUL AT87C58X2-RLTUL AT87C58X2-3CSUV AT87C58X2-SLSUV AT87C58X2-RLTUV 5V ±10% 5V ±10% 5V ±10% 2.7 to 5.5V 2.7 to 5.5V 2.7 to 5.5V 5V ±10% 5V ±10% 5V ±10% Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green Industrial & Green PDIL40 PLCC44 VQFP44 PDIL40 PLCC44 VQFP44 PDIL40 PLCC44 VQFP44 Stick Stick Tray Stick Stick Tray Stick Stick Tray 21. Datasheet Revision History 21.1 Changes from Rev. C 01/01 to Rev. D 11/05 1. Added green product Ordering Information. 21.2 Changes from Rev. D 11/05 to Rev. E 04/06 1. Changed value of AUXR register. 61 4431E–8051–04/06 A tmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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