AT88SA102S-TSU-T

Features • Secure authentication & key exchange • Superior SHA-256 Hash Algorithm • Best in class 256-bit key length • Guaranteed Unique 48-bit Serial Number • High speed single wire interface • Supply Voltage: 2.7 – 5.25V • 1.8 – 5.5 V Communications • 4.5V See Section 5.3 for more details. SecureDelay Parameter Parsing Delay t PARSE t EXEC_MAC t EXEC_READ t EXEC_FUSE MacDelay MemoryDelay Fuse Delay 30 3 700 t EXEC_SECURE 36 ms Max delay to execute BurnSecure command at Vcc > 4.5V See Section 5.5 for more details. PersonalizeDelay t PERSON EXEC 13 ms Delay to execute GenPersonalizationKey In this document, t the chip. is used as shorthand for the delay corresponding to whatever command has been sent to 4.1.2. Transmit Flag The Transmit flag is used to turn around the signal so that the Atmel® AT88SA102S can send data back to the system, depending on its current state. The bytes that the AT88SA102S returns to the system depend on its current state as follows: 10 Atmel AT88SA102S 8584F–SMEM–8/10 Atmel AT88SA102S Table 4-1. Return Codes Error/Status 0x11 – Description Indication that a proper Wake token has been received by Atmel AT88SA102S Return bytes per “Output Parameters” in Command section of this document. In some cases this is a single byte with a value of 0x00 indicating success. The Transmit flag can be resent to Atmel AT88SA102S repeatedly if a re-read of the output is necessary. Command was properly received but could not be executed by Atmel AT88SA102S. Changes in Atmel AT88SA102S state or the value of the command bits must happen before it is re-attempted. Command was NOT properly received by Atmel AT88SA102S and should be re-issued by the system. No attempt was made to execute the command State Description After Wake, but prior to first command After successful command execution Execution error 0x0F After CRC or other communications error 0xFF AT88SA102S always transmits complete blocks to the system, so in the above table the status/error bytes result in 4-bytes going to the system – count, status/error, CRC x 2. After receipt of a command block, AT88SA102S will parse the command for errors, a process which takes t PARSE (Refer to Section 4.1.1). After this interval the system can send a Transmit token to AT88SA102S – if there was an error then AT88SA102S will respond with an error code. If there is no error then AT88SA102S internally transitions automatically from tPARSE to tEXEC and will not respond to any Transmit tokens until both delays are complete. 4.1.3. Sleep Flag The sleep flag is used to transition AT88SA102S to the low power state, which causes a complete reset of AT88SA102S’ internal command engine and input/output buffer. It can be sent to AT88SA102S at any time when AT88SA102S will accept a flag. To achieve the specified ISLEEP, Atmel recommends that the input signal be brought below VIL when the chip is asleep. To achieve ISLEEP if the sleep state of the input pin is high, the voltage on the input signal should be within 0.5V of VCC to avoid additional leakage on the input circuit of the chip. The system must calculate the total time required for all commands to be sent to AT88SA102S during a single session, including any inter-bit/byte delays. If this total time exceeds tWATCHDOG then the system must issue a partial set of commands, then a Sleep flag, then a Wake token, and finally after the Wake delay the remaining commands. 4.1.4. Pause State The pause state is entered via the PauseLong command and can be exited only when the watchdog timer has expired and the chip transitions to a sleep state. When in the pause state, the chip ignores all transitions on the signal pin but does not enter a low power consumption mode. The pause state provides a mechanism for multiple AT88SA102S chips on the same wire to be selected and to exchange data with the host microprocessor. The PauseLong command includes an optional address field which is compared to the values in Fuses 84-87. If the two matches, then the chip enter the pause state, otherwise it continues to monitor the bus for subsequent commands. The host would selectively put all but one AT88SA102S’ in the pause state before executing the MAC command on the active chip. After the end of the watchdog interval all the chips will have entered the sleep state and the selection process can be started with a Wake token (which will then be honored by all chips) and selection of a subsequent chip. 11 8584F–SMEM–8/10 4.2. IO Blocks Commands are sent to the chip, and responses received from the chip, within a block that is constructed in the following way: Byte 0 Name Count Meaning Number of bytes to be transferred to the chip in the block, including count, packet and checksum, so this byte should always have a value of (N+1). The maximum size block is 39 and the minimum size block is 4. Values outside this range will cause unpredictable operation. Command, parameters and data, or response. Refer to Section 4.1.2 and Section 5 for more details. CRC-16 verification of the count and packet bytes. The CRC polynomial is 0x8005, the initial register value should be 0 and after the last bit of the count and packet have been transmitted the internal CRC register should have a value that matches that in the block. The first byte transmitted (N-1) is the least significant byte of the CRC value so the last byte of the block is the most significant byte of the CRC. 1 to (N-2) N-1, N Packet Checksum 4.3. IO Flow The general IO flow for the MAC command is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. System sends Wake token System sends Transmit flag Receive 0x11 value from the Atmel® AT88SA102S to verify proper wakeup synchronization System sends Command flag System sends complete command block System waits tPARSE for the AT88SA102S to check for command formation errors System sends Transmit flag. If command format is OK, the AT88SA102S ignores this flag because the computation engine is busy. If there was an error, the AT88SA102S responds with an error code System waits tEXEC, refer to Section 4.1.1 System sends Transmit flag Receive output block from the AT88SA102S, system checks CRC If CRC from the AT88SA102S is incorrect, indication transmission error, system resends Transmit flag System sends sleep flag to the AT88SA102S All commands other than MAC have a short execution delay. In these cases, the system should omit steps six, seven and eight and replace this with a wait of duration tPARSE + tEXEC. 4.4. Synchronization Because the communications protocol is half duplex, there is the possibility that the system and AT88SA102S will fall out of synchronization with each other. In order to speed recovery, AT88SA102S implements a timeout that forces the chip to sleep. 4.4.1. IO Timeout After a leading transition for any data token has been received, AT88SA102S will expect the remaining bits of the token to be properly received by the chip within the tTIMEOUT interval. Failure to send enough bits or the transmission of an illegal token (a low pulse exceeding tZLO) will cause the chip to enter the sleep state after the tTIMEOUT interval. The same timeout applies during the transmission of the command block. After the transmission of a legal command flag, the IO Timeout circuitry is enabled until the last expected data bit is received. The timeout counter is reset after every legal token, so the total time to transmit the command may exceed the tTIMEOUT interval while the time between bits may not. 12 Atmel AT88SA102S 8584F–SMEM–8/10 Atmel AT88SA102S In order to limit the active current if Atmel® AT88SA102S is inadvertently awakened, the IO Timeout circuitry is also enabled when AT88SA102S receives a wake-up. If the first token does not come within the tTIMEOUT interval, then AT88SA102S will go back to the sleep mode without performing any operations. The IO Timeout circuitry is disabled when the chip is busy executing a command. 4.4.2. Synchronization Procedures When the system and the AT88SA102S fall out of synchronization, the system will ultimately end up sending a Transmit flag which will not generate a response from AT88SA102S. The system should implement its own timeout which waits for tTIMEOUT during which time AT88SA102S should go to sleep automatically. At this point, the system should send a Wake token and after tWLO + tWHI, a Transmit token. The 0x11 status indicates that the resynchronization was successful. It may be possible that the system does not get the 0x11 code from Atmel® AT88SA102S for one of the following reasons: 1. The system did not wait a full tTIMEOUT delay with the IO signal idle in which case AT88SA102S may have interpreted the Wake token and Transmit flag as data bits. Recommended resolution is to wait twice the tTIMEOUT delay and re-issue the Wake token. 2. AT88SA102S went into the sleep mode for some reason while the system was transmitting data. In this case, AT88SA102S will interpret the next data bit as a Wake token, but ignore some of the subsequently transmitted bits during its wake-up delay. If any bytes are transmitted after the wake-up delay, they may be interpreted as a legal flag, though the following bytes would not be interpreted as a legal command due to an incorrect count or the lack of a correct CRC. Recommended resolution is to wait the tTIMEOUT delay and reissue the Wake token. 3. There is some internal error condition within AT88SA102S which will be automatically reset after a tWATCHDOG interval, see below. There is no way to externally reset AT88SA102S – the system should leave the IO pin idle for this interval and issue the Wake token. 4.5. Watchdog Failsafe After the Wake token has been received by AT88SA102S, a watchdog counter is started within the chip. After tWATCHDOG, the chip will enter sleep mode, regardless of whether it is in the middle of execution of a command and/or whether some IO transmission is in progress. There is no way to reset the counter other than to put the chip to sleep and wake it up again. This is implemented as a fail-safe so that no matter what happens on either the system side or inside the various state machines of AT88SA102S including any IO synchronization issue, power consumption will fall to the low sleep level automatically. 4.6. Byte and Bit Ordering AT88SA102S is a little-endian chip: • All multi-byte aggregate elements within this spec are treated as arrays of bytes and are processed in the order received • Data is transferred to/from AT88SA102S least significant bit first on the bus • In this document, the most significant bit and/or byte appears towards the left hand side of the page 13 8584F–SMEM–8/10 5. Commands The command packet is broken down in the following way: Byte 0 1 2-3 4+ Name Opcode Param1 Param2 Data Meaning The Command code The first parameter – always present The second parameter – always present Optional remaining input data If a command fails because the CRC within the block is incorrect or there is some other communications error then immediately after tPARSE the system will be able to retrieve an error response block containing a single byte packet. The value of that byte will be all ones. In this situation, the system should re-transmit the command block including the proceeding Transmit flag – providing there is sufficient time before the expiration of the watchdog timeout. If the opcode is invalid, one of the parameters is illegal, or Atmel® AT88SA102S is in an illegal state for the execution of this command then immediately after tPARSE the system will be able to retrieve an error response block containing a single byte packet. The value of that byte will be 0x0F. In this situation, the condition must be corrected before the (modified) command is sent back to AT88SA102S. If a command is received successfully then after the appropriate execution delay the system will be able to retrieve the output block as described in the individual command descriptions below. In the individual command description tables below, the Size column describes the number of bytes in the parameter documented in each particular row. The total size of the block for each of the commands is fixed, though that value is different for each command. If the block size for a particular command is incorrect, the chip will not attempt the command execution and return an error. 5.1. MAC Computes a SHA-256 digest of a key stored inside the chip, an input challenge and other information on the chip. The output of this command is the digest of this message. If the message includes the serial number of the chip, then the response is said to be diversified. Protocols that utilize diversified responses may be more secure because two AT88SA102S chips with same key will return different responses to an identical challenge based on their unique serial number. Table 5-1. Input Parameters Name Opcode Param1 Param2 Data MAC Mode KeyID Challenge Size 1 1 2 32 Notes 0x08 Controls which fields within the chip are used in the message Which internal key is to be used in the message Input portion of message to be digested 14 Atmel AT88SA102S 8584F–SMEM–8/10 Atmel AT88SA102S Table 5-2. Name Response Output Parameters Size 32 Notes SHA-256 digest Regardless of the value of the first 512-bit block of the message that will be hashed with the SHA-256 algorithm will consist of: 256-bits 256-bits key[KeyID] challenge The second block consists of the following information: 8-bits 8-bits 16-bits 64-bits 24-bits 8-bits 32-bits 16-bits 16-bits 1-bit 255-bit 64-bit Opcode (always 0x08) Mode KeyID Secret Fuses including BurnFuse and BurnSecure enable (or 0’s, see below) Status Fuses including FuseDisable (or 0’s, see below) Fuse MfrID fuses, (Fuse[88:95]) (never zero’d out) Fuse SN, (Fuse[96:127]) (or 0’s, see below) ROM MfrID (never zero’d out) ROM SN (or 0’s, see below) ‘1’ pad ‘0’ pad total length of message in bits (512+192=704), excluding pad and length Mode is encoded as follows: Table 5-3. Bits 7 6 Should be zero If set; include the 48-bit serial number (combination of fuses and ROM values) in the message Otherwise, the corresponding message bits are set to zero 5 If set and Fuse[87] is burned; include the 64-secret fuses (Fuse[0] through Fuse[63]) in the message Otherwise, the corresponding message bits are set to Zero If Mode[4] is set, then the value of this mode bit is ignored 4 If set and Fuse[87] is burned; include the 64-secret fuses and 24-status fuses (Fuse[0] through Fuse[87]) in the message Ootherwise, the corresponding message bits are set to zero 3-0 Should be zero Mode Encoding Meaning 15 8584F–SMEM–8/10 5.2. Read Reads 4-bytes from Fuse or ROM. Returns an error if an attempt is made to read any fuse address that is illegal. Table 5-1. Input Parameters Name Opcode Param1 Param2 Data Table 5-2. Name Contents Table 5-3. Name ROM Fuse Mode Encoding Value 0x00 0x01 Notes Reads four bytes from the ROM. Bit one of the address parameter must be zero Reads the value of 32-fuses. Bit one of the address parameter must be one. The input address parameter 4.5V, must be 0x80 00 otherwise 16 Atmel AT88SA102S 8584F–SMEM–8/10 Atmel AT88SA102S Table 5-2. Name Success Output Parameters Size 1 Notes Upon successful execution, a value of 0 will be returned by the Atmel AT88SA102S 5.4. GenPersonalizationKey Loads a personalization key into internal memory and then uses that key along with an input seed to generate a decryption digest using SHA-256. Neither the key nor the decryption digest can be read from the chip. Upon completion, an internal bit is set indicating that a secure personalization digest has been loaded and is ready for use by BurnSecure. This bit is cleared (and the digest lost) when the watchdog timer expires or the power is cycled. This command will fail if Fuse[87] has been burned. Table 5-1. Input Parameters Name Opcode Param1 Param2 Data GenPers Zero KeyID Seed Size 1 1 2 16 Notes 0x20 Must be 0x00 Identification number of the personalization key to be loaded Seed for digest generation. The least significant bit of the last byte is ignored by the Atmel AT88SA102S Table 5-2. Name Success Output Parameters Size 1 Notes Upon successful execution of HOST0, a value of 0 will be returned by the Atmel AT88SA102S The SHA-256 message body used to create the resulting digest internally stored in the chip consists of the following 512-bits: 256-bits 64-bits 127-bits 1-bits 64-bits PersonalizeKey[KeyID] Fixed value of all ones Seed from input stream ‘1’ pad Length of message in bits, fixed at 447 5.5. BurnSecure Burns any combination of the first 88-fuse bits. Verification that the proper secret fuse bits have been burned must occur using the MAC command – there is no way to read the values in the first 64-fuses to verify their state. The 24-status fuses can be verified with the Read command. The fuses to be burned are specified by the 88-bit input map parameter. If a bit in the map is set to a ‘1’, then the corresponding fuse is burned. If a bit in the map parameter is zero, then the corresponding fuse is left in its current state. The first bit sent to the Atmel® AT88SA102S corresponds to Fuse[0] and so on up to Fuse[87]. Note: Since a ‘1’ bit in the Map parameter results in a ‘0’ data value in the actual fuse array, the value in the Map parameter should generally be the inverse of the desired secret or status value. See Section 1.3 for more details. 17 8584F–SMEM–8/10 To facilitate secure personalization of the AT88SA102S, this map may be encrypted before being sent to the chip. If this mode is desired, then the Decrypt parameter should be set to one in the input parameter list. The decryption (transport) key is computed by the GenPersonalizationKey command, which must have been run immediately prior to the execution of BurnSecure. In this case, prior to burning any fuses, the input Map parameter is XOR’d with the first 88 bits of that digest from the GenPersonalizationKey command. The GenPersonalizationKey and BurnSecure commands must be run within a single Wake cycle prior to the expiration of the watchdog timer. The power supply pin must meet the VBURN specification during the entire BurnSecure command in order to burn fuses reliably. If VCC is greater than 4.5V, then the BurnTime parameter should be set to 0x00 and the internal burn time will be 250µs. If VCC is less than 4.5V but greater than VBURN then the BurnTime parameter should be set to 0x8000 and the internal burn time will be 190ms per fuse bit burned. The chip does NOT internally check the supply voltage level. The total BurnSecure execution delay is directly proportional to the total number of fuses being burned. If VCC is less than 4.5V, then the total BurnSecure execution time may exceed the interval remaining before the expiration of the watchdog timer. In this case, the BurnSecure command should be run repeatedly, with each repetition burning only as many fuses as there is time available. The system software is responsible for counting the number of ‘1’ bits in the clear-text version of the map parameter sent to the chip – no error is returned if the fuse burn count is too high. Other than Fuse[87] (see below), the fuses may be burned in any order. Prior to execution of BurnSecure, the AT88SA102S verifies that Fuse[87] is un-burned. If it has been burned, then the BurnSecure command will return an error. Fuse[87] can either be burned during the last repetition of BurnSecure or it can be individually burned with BurnFuse. There are a series of very small intervals during tEXEC_SECURE when the fuse element is actually being burned. The power supply must not be removed during this interval and the watchdog timer must not be allowed to expire during this interval, or the fuse may end up in a state where it reads as un-burned but cannot be burned. Table 5-2. Input Parameters Name Opcode Param1 Param2 Data Table 5-3. Name Success BURNSECURE Decrypt BurnTime Map Output Parameters Size 1 Notes Upon successful execution, a value of 0 will be returned by the Atmel AT88SA102S. Size 1 1 2 11 Notes 0x10 If 1, decrypt Map data before usage. If 0, the map is transmitted in plain text Must be 0x00 00 if VCC > 4.5V, must be 0x80 00 otherwise Which fuses to burn, may be encrypted 18 Atmel AT88SA102S 8584F–SMEM–8/10 Atmel AT88SA102S 5.6. PauseLong Forces the chip into the pause state until the watchdog timer expires, after which it will automatically enter into the sleep state. During execution of this command and while in the pause state the chip will ignore all activity on the IO signal. This command is used to prevent bus conflicts in a system that also includes other Atmel® AT88SA102S chips or an Atmel CryptoAuthentication host chip sharing the same signal wire. Table 5-1. Input Parameters Name Opcode Param1 Param2 Data PAUSELONG Selector Zero Ignored Size 1 1 2 0 Notes 0x01 Which chip to put into the pause state, 0x00 for all Atmel AT88SA102S chips Must be 0x00 00 The Selector parameter provides a mechanism to select which device will pause if there are multiple devices on the bus: If the Selector parameter is 0x00, then every AT88SA102S chip receiving this command will go into the pause state and no chip will return a success code. If any of the bits of the Selector parameter are set, then the chip will read the values of Fuse[84-87] and go into the pause state only if those fuse values match the least significant 4-bits of the Selector parameter. If the chip does NOT go into the pause state, it returns an error code of 0x0F. Otherwise it goes into the pause state and never returns any code. 6. Pinout Table 6-1. Pin # 1 SOT Pin Definitions Name Signal Description IO channel to the system, open drain output. It is expected that an external pull-up resistor will be provided to pull this signal up to VCC for proper communications. When the chip is not in use this pin can be pulled to either VCC or VSS. Power supply, 2.7 – 5.25V. This pin should be bypassed with a high quality 0.1µF capacitor close to this pin with a short trace to VSS Additional applications information at www.atmel.com 3 VSS Connect to system ground 2 VCC 19 8584F–SMEM–8/10 7. Packaging Information 3TS1 – Shrink SOT 3 GND C L E1 E SDA 1 e1 2 VCC Top View End View b A2 SEATING PLANE A e D A1 Side View L1 Notes: 1. Dimension D does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.25mm per end. Dimension E1 does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25mm per side. 2. The package top may be smaller than the package bottom. Dimensions D and E1 are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 3. These dimensions apply to the flat section of the lead between 0.08 mm and 0.15mm from the lead tip. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE This drawing is for general information only. Refer to JEDEC Drawing TO-236, Variation AB for additional information. A A1 A2 D E E1 L1 e1 b 0.89 0.01 0.88 2.80 2.10 1.20 2.90 1.30 0.54 REF 1.90 BSC 0.30 - 1.12 0.10 1.02 3.04 2.64 1.40 1,2 1,2 0.50 3 12/11/09 TITLE R Package Drawing Contact: packagedrawings@atmel.com GPC DRAWING NO. REV. 3TS1, 3-lead, 1.30mm Body, Plastic Thin Shrink Small Outline Package (Shrink SOT) TBG 3TS1 B 20 Atmel AT88SA102S 8584F–SMEM–8/10 Atmel AT88SA102S 8A2 – TSSOP 3 21 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D MIN 2.90 NOM 3.00 6.40 BSC 4.30 – 0.80 0.19 4.40 – 1.00 – 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5 b A E E1 A e D A2 A2 b e L L1 Side View Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15mm (0.006in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25mm (0.010in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/19/10 TITLE GPC DRAWING NO. 8A2 REV. E Package Drawing Contact: 8A2, 8-lead 4.4mm Body, Plastic Thin packagedrawings@atmel.com Shrink Small Outline Package (TSSOP) TNR 21 8584F–SMEM–8/10 8S1 – SOIC END VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL A A1 b C D E1 E e MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM – – – – – – – 1.27 BSC 0.40 0° – – 1.27 8° 5/19/10 TITLE GPC DRAWING NO. 8S1 REV. F MAX 1.75 0.25 0.51 0.25 5.05 3.99 6.20 NOTE Notes: This drawing is for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. L Package Drawing Contact: 8S1, 8-lead (0.150” Wide Body), Plastic Gull packagedrawings@atmel.com Wing Small Outline (JEDEC SOIC) SWB 22 Atmel AT88SA102S 8584F–SMEM–8/10 Atmel AT88SA102S 8. Ordering Codes Atmel AT24C256C Ordering Information Ordering Code AT88SA102S-TSU-T Package Type SOT, Tape & Reel Voltage Range 2.7V–5.25V Operating Range Green compliant (exceeds RoHS)/Industrial (−40°C to 85°C) AT88SA102S-TH-T TSSOP, Tape & Reel 2.7V–5.25V Green compliant (exceeds RoHS)/Industrial (−40°C to 85°C) AT88SA102S-SH-T SOIC, Tape & Reel 2.7V–5.25V Green compliant (exceeds RoHS)/Industrial (−40°C to 85°C) 9. Revision History Doc. Rev. Date Comments 8584F 8584E 8584D 8584C 8584B 8584A 08/2010 06/2010 05/2010 04/2010 02/2010 03/2009 Update IO Timeout description Update to Table 3: AC Parameters Expansion of IO Timeout specification Added 8ld TSSOP Updated parameter tables and added 8ld SOIC Initial document release 23 8584F–SMEM–8/10 H e ad q ua rt e rs Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: (+1) (408) 441-0311 Fax: (+1) (408) 487-2600 www.atmel.com I n t er n at io n al Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. 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Atmel®, Atmel logo and combinations thereof, and others are registered trademarks, CryptoAuthentication™ and others, are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 8584F–SMEM–8/10