AT88SC0404C-PU

Features • One of a Family of 9 Devices with User Memories from 1 Kbit to 256-Kbit • 4-Kbit (512-byte) EEPROM User Memory ⎯ Four 128-byte (1-Kbit) Zones ⎯ Self-timed Write Cycle ⎯ Single Byte or 16-byte Page Write Mode ⎯ Programmable Access Rights for Each Zone • 2-Kbit Configuration Zone ⎯ 37-byte OTP Area for User-defined Codes ⎯ 160-byte Area for User-defined Keys and Passwords • High Security Features ⎯ 64-bit Mutual Authentication Protocol (Under license of ELVA) ⎯ Encrypted Checksum ⎯ Stream Encryption ⎯ Four Key Sets for Authentication and Encryption ⎯ Eight Sets of Two 24-bit Passwords ⎯ Anti-tearing Function ⎯ Voltage and Frequency Monitor • Smart Card Features ⎯ ISO 7816 Class A (5V) or Class B (3V) Operation ⎯ ISO 7816-3 Asynchronous T = 0 Protocol (Gemplus® Patent) * ⎯ Multiple Zones, Key Sets and Passwords for Multi-application Use ⎯ Synchronous 2-wire Serial Interface for Faster Device Initialization * ⎯ Programmable 8-byte Answer-To-Reset Register ⎯ ISO 7816-2 Compliant Modules • Embedded Application Features ⎯ Low Voltage Operation: 2.7V to 5.5V ⎯ Secure Nonvolatile Storage for Sensitive System or User Information ⎯ 2-wire Serial Interface ⎯ 1.0 MHz Compatibility for Fast Operation ⎯ Standard 8-lead Plastic Packages, Green Compliant (exceeds RoHS) ⎯ Same Pinout as 2-wire Serial EEPROMs • High Reliability ⎯ Endurance: 100,000 Cycles ⎯ Data Retention: 10 years ⎯ ESD Protection: 4,000V min CryptoMemory® 4 Kbit AT88SC0404C Summary * Note: Modules available with either T=0 / 2-wire modes or 2-wire mode only. 2023KS–SMEM–10/09 Table 1. Pad VCC GND SCL/CLK SDA/IO RST Figure 1. VCC=C1 RST=C2 SCL/CLK=C3 NC=C4 Pin Assignment Description Supply Voltage Ground Serial Clock Input Serial Data Input/Output Reset Input Pin Configuration ISO Smart Card Module C5=GND C6=NC C7=SDA/IO C8=NC 8-lead SOIC, PDIP NC NC NC GND 1 2 3 4 8 7 6 5 ISO Module C1 C5 C3 C7 C2 TWI Module C1 C5 C3 C7 NC Standard Package Pin 8 4 6 5 NC VCC NC SCL SDA TWI Smart Card Module VCC=C1 NC=C2 SCL/CLK=C3 NC=C4 C5=GND C6=NC C7=SDA/IO C8=NC 1. Description The AT88SC0404C member of the CryptoMemory® family is a high-performance secure memory providing 4 Kbits of user memory with advanced security and cryptographic features built in. The user memory is divided into four 128-byte zones, each of which may be individually set with different security access rights or effectively combined together to provide space for 1 to 4 data files. 1.1. Smart Card Applications The AT88SC0404C provides high security, low cost, and ease of implementation without the need for a microprocessor operating system. The embedded cryptographic engine provides for dynamic and symmetric mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. Up to four unique key sets may be used for these operations. The AT88SC0404C offers the ability to communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gemplus Patent) defined in ISO 7816-3. 1.2. Embedded Applications Through dynamic and symmetric mutual authentication, data encryption, and the use of encrypted checksums, the AT88SC0404C provides a secure place for storage of sensitive information within a system. With its tamper detection circuits, this information remains safe even under attack. A 2-wire serial interface running at 1.0 MHz is used for fast and efficient communications with up to 15 devices that may be individually addressed. The AT88SC0404C is available in industry standard 8-lead packages with the same familiar pinout as 2-wire serial EEPROMs. 2 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C Figure 2. Block Diagram VCC GND Power Management Authentication, Encryption and Certification Unit Random Generator Synchronous Interface Data Transfer SCL/CLK SDA/IO RST Asynchronous ISO Interface Password Verification EEPROM Reset Block Answer to Reset 2. 2.1. Pin Descriptions Supply Voltage (VCC) The VCC input is a 2.7V to 5.5V positive voltage supplied by the host. 2.2. Clock (SCL/CLK) In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a carrier frequency f. The nominal length of one bit emitted on I/O is defined as an “elementary time unit” (ETU) and is equal to 372/ f. When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge clock data out of the device. 2.3. Reset (RST) The AT88SC0404C provides an ISO 7816-3 compliant asynchronous answer to reset sequence. When the reset sequence is activated, the device will output the data programmed into the 64-bit answer-to-reset register. An internal pull-up on the RST input pad allows the device to be used in synchronous mode without bonding RST. The AT88SC0404C does not support the synchronous answer-to-reset sequence. 2.4. Serial Data (SDA/IO) The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wired with any number of other open drain or open collector devices. An external pull-up resistor should be connected between SDA and VCC. The value of this resistor and the system capacitance loading the SDA bus will determine the rise time of SDA. This rise time will determine the maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while drawing higher average power. SDA/IO information applies to both asynchronous and synchronous protocols. When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data into the device and negative edge clock data out of the device. 3 2023KS–SMEM–10/09 3. *Absolute Maximum Ratings Operating Temperature............................. −40°C to +85°C Storage Temperature ............................ −65°C to + 150°C Voltage on Any Pin with Respect to Ground ....................... − 0.7 to VCC +0.7V Maximum Operating Voltage.......................................6.0V DC Output Current ..................................................5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Table 2. DC Characteristics Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40°C to +85°C (unless otherwise noted) Symbol VCC(2) ICC ICC ICC ICC ISB VIL VIL VIL (1) (1) (1) Parameter Supply Voltage Supply Current (VCC = 5.5V) Supply Current (VCC = 5.5V) Supply Current (VCC = 5.5V) Supply Current (VCC = 5.5V) Standby Current (VCC = 5.5V) SDA/IO Input Low Threshold SCL/CLK Input Low Threshold RST Input Low Threshold SDA/IO Input High Threshold SCL/CLK Input High Threshold RST Input High Threshold SDA/IO Input Low Current SCL/CLK Input Low Current RST Input Low Current SDA/IO Input High Current SCL/CLK Input High Current RST Input High Current SDA/IO Output High Voltage SDA/IO Output Low Voltage SDA/IO Output High Current Test Condition Async READ at 3.57MHz Async WRITE at 3.57MHz Synch READ at 1MHz Synch WRITE at 1MHz VIN = VCC or GND Min 2.7 Typ Max 5.5 5 5 5 5 100 Units V mA mA mA mA mA V V V V V V μA μA μA μA μA μA V V μA 0 0 0 VCC x 0.7 VCC x 0.7 VCC x 0.7 0 < VIL < VCC x 0.15 0 < VIL < VCC x 0.15 0 < VIL < VCC x 0.15 VCC x 0.7 < VIH < VCC VCC x 0.7 < VIH < VCC VCC x 0.7 < VIH < VCC 20K ohm external pull-up IOL = 1mA VOH VCC x 0.7 0 VCC x 0.2 VCC x 0.2 VCC x 0.2 VCC VCC VCC 15 15 50 20 100 150 VCC VCC x 0.15 20 VIH(1)(2) VIH(1)(2) VIH(1)(2) IIL IIL IIL IIH IIH IIH VOH VOL IOH Notes: 1. VIL min and VIH max are reference only and are not tested. 2. To prevent Latch Up Conditions from occurring during Power Up of the AT88SCxxxxC, VCC must be turned on before applying VIH. For Powering Down, VIH must be removed before turning VCC off. 4 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C Table 3. AC Characteristics Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40°C to +85°C, CL = 30pF (unless otherwise noted) Symbol fCLK fCLK fCLK Parameter Async Clock Frequency (VCC Range: +4.5 - 5.5V) Async Clock Frequency (VCC Range: +2.7 - 3.3V) Synch Clock Frequency Clock Duty cycle tR tF tR tF tAA tHD.STA tSU.STA tHD.DAT tSU.DAT tSU.STO tDH tWR tWR Rise Time - I/O, RST Fall Time - I/O, RST Rise Time - CLK Fall Time - CLK Clock Low to Data Out Valid Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Stop Set-up Time Data Out Hold Time Write Cycle Time (at 25°C) Write Cycle Time (-40° to +85°C) 200 200 10 100 200 20 5 7 Min 1 1 0 40 Max 5 4 1 60 1 1 9% x period 9% x period 35 Units MHZ MHZ MHZ % μS μS μS μS nS nS nS nS nS nS nS mS mS 4. Device Operation for Synchronous Protocols CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 5 on page 7). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: STOP CONDITION: ACKNOWLEDGE: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 6 on page 7). A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 6 on page 7). All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle. After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: 1. 2. 3. Clock up to 9 cycles. Look for SDA high in each cycle while SCL is high. Create a start condition. MEMORY RESET: 5 2023KS–SMEM–10/09 Figure 3. Bus Timing for 2 wire communications: SCL: Serial Clock, SDA – Serial Data I/O tF tHIGH tLOW tR SCL tSU.STA tHD.STA tLOW tHD.DAT tSU.DAT tSU.STO SDA IN tAA tDH tBUF SDA OUT Figure 4. Write Cycle Timing: SCL: Serial Clock, SDA – Serial Data I/O SCL SDA 8th BIT WORDn ACK twr STOP CONDITION (1) START CONDITION Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 6 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C Figure 5. Data Validity SDA SCL DATA STABLE DATA CHANGE ALLOWED DATA STABLE Figure 6. Start and Stop Definitions SDA SCL START STOP Figure 7. Output Acknowledge SCL 1 8 9 DATA IN DATA OUT START ACKNOWLEDGE 7 2023KS–SMEM–10/09 5. 5.1. Device Architecture User Zones The EEPROM user memory is divided into 4 zones of 1024 bits each. Multiple zones allow for different types of data or files to be stored in different zones. Access to the user zones is allowed only after security requirements have been met. These security requirements are defined by the user during the personalization of the device in the configuration memory. If the same security requirements are selected for multiple zones, then these zones may effectively be accessed as one larger zone. Figure 8. User Zones Zone $00 User 0 ─ ─ $78 $00 User 1 ─ ─ $78 $00 User 2 ─ ─ $78 $00 User 3 ─ ─ $78 128 Bytes 128 Bytes 128 Bytes 128 Bytes $0 $1 $2 $3 $4 $5 $6 $7 6. Control Logic Access to the user zones occurs only through the control logic built into the device. This logic is configurable through access registers, key registers and keys programmed into the configuration memory during device personalization. Also implemented in the control logic is a cryptographic engine for performing the various higher-level security functions of the device. 8 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C 7. Configuration Memory The configuration memory consists of 2048 bits of EEPROM memory used for storing passwords, keys and codes and for defining security levels to be used for each user zone. Access rights to the configuration memory are defined in the control logic and may not be altered by the user. Figure 9. $00 $08 $10 $18 $20 $28 $30 $38 $40 $48 $50 $58 $60 $68 $70 $78 $80 $88 $90 $98 $A0 $A8 $B0 $B8 $C0 $C8 $D0 $D8 $E0 $E8 $F0 $F8 PAC PAC PAC PAC PAC PAC PAC PAC Write 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write 6 Write 7 PAC PAC PAC PAC PAC PAC PAC PAC Reserved Read 0 Read 1 Read 2 Read 3 Read 4 Read 5 Read 6 Read 7 Forbidden Password For Authentication and Encryption use Secret For Authentication and Encryption use Cryptography Issuer Code Reserved Access Control DCR AR0 PR0 AR1 Fab Code MTZ Lot History Code Identification Number Nc PR1 AR2 PR2 AR3 PR3 Configuration Memory $0 $1 $2 $3 $4 $5 $6 $7 Identification Read Only Answer to Reset Card Manufacturer Code 9 2023KS–SMEM–10/09 8. Security Fuses There are three fuses on the device that must be blown during the device personalization process. Each fuse locks certain portions of the configuration memory as OTP memory. Fuses are designed for the module manufacturer, card manufacturer and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be performed at one final step. 9. Protocol selection The AT88SC0404C supports two different communication protocols. • • Smart Card Applications: The asynchronous T = 0 protocol defined by ISO 7816-3 is used for compatibility with the industry’s standard smart card readers. Embedded Applications: A 2-wire serial interface is used for fast and efficient communication with logic or controllers. The power-up sequence determines which of the two communication protocols will be used. 9.1. Asynchronous T = 0 Protocol This power-up sequence complies with ISO 7816-3 for a cold reset in smart card applications. • • • • VCC goes high; RST, I/O-SDA and CLK-SCL are low. Set I/O-SDA in receive mode. Provide a clock signal to CLK-SCL. RST goes high after 400 clock cycles. The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory density within the CryptoMemory family. Once the asynchronous mode has been selected, it is not possible to switch to the synchronous mode without powering off the device. Figure 10. Asynchronous T = 0 Protocol (Gemplus Patent) Vcc I/O-SDA RST CLK-SCL ATR 10 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C 9.2. Synchronous 2-wire Serial Interface The synchronous mode is the default after powering up VCC due to an internal pull-up on RST. For embedded applications using CryptoMemory in standard plastic packages, this is the only communication protocol. • • Power-up VCC, RST goes high also. After stable VCC, CLK-SCL and I/O-SDA may be driven. Synchronous 2-wire Protocol Figure 11. Vcc I/O-SDA RST CLK-SCL Note: 1 2 3 4 5 Five clock pulses must be sent before the first command is issued. 10. Communication Security Modes Communications between the device and host operate in three basic modes. Standard mode is the default mode for the device after power-up. Authentication mode is activated by a successful authentication sequence. Encryption mode is activated by a successful encryption activation following a successful authentication. Table 4. Mode Standard Authentication Encryption Note: Communication Security Modes Configuration Data clear clear clear (1) User Data clear clear encrypted Passwords clear encrypted encrypted Data Integrity Check MDC(1) MAC(1) MAC(1) 1. Configuration data include viewable areas of the Configuration Zone except the passwords: MDC: Modification Detection Code MAC: Message Authentication Code. 11 2023KS–SMEM–10/09 11. 11.1. Security Options Anti-tearing In the event of a power loss during a write cycle, the integrity of the device’s stored data may be recovered. This function is optional: the host may choose to activate the anti-tearing function, depending on application requirements. When anti-tearing is active, write commands take longer to execute, since more write cycles are required to complete them, and data are limited to eight bytes. Data are written first to a buffer zone in EEPROM instead of the intended destination address, but with the same access conditions. The data are then written in the required location. If this second write cycle is interrupted due to a power loss, the device will automatically recover the data from the system buffer zone at the next power-up. In 2-wire mode, the host is required to perform ACK polling for up to 8 ms after write commands when anti-tearing is active. At power-up, the host is required to perform ACK polling, in some cases for up to 2 ms, in the event that the device needs to carry out the data recovery process. 11.2. Write Lock If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte for the bytes of that page. Example: The write lock byte at $080 controls the bytes from $080 to $087. Figure 12. $080 Write Lock Example $0 11011001 $1 xxxx xxxx locked $2 xxxx xxxx locked $3 xxxx xxxx $4 xxxx xxxx $5 xxxx xxxx locked $6 xxxx xxxx $7 xxxx xxxx Address The write lock byte may also be locked by writing its least significant (rightmost) bit to “0”. Moreover, when write lock mode is activated, the write lock byte can only be programmed — that is, bits written to “0” cannot return to “1”. In the write lock configuration, only one byte can be written at a time. Even if several bytes are received, only the first byte will be taken into account by the device. 12 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C 12. Password Verification Passwords may be used to protect read and/or write access of any user zone. When a valid password is presented, it is memorized and active until power is turned off, unless a new password is presented or RST becomes active. There are eight password sets that may be used to protect any user zone. Only one password is active at a time, but write passwords give read access also. 12.1. Authentication Protocol The access to a user zone may be protected by an authentication protocol. Any one of four keys may be selected to use with a user zone. The authentication success is memorized and active as long as the chip is powered, unless a new authentication is initialized or RST becomes active. If the new authentication request is not validated, the card loses its previous authentication and it should be presented again. Only the last request is memorized. Note: Password and authentication may be presented at any time and in any order. If the trials limit has been reached (after four consecutive incorrect attempts), the password verification or authentication process will not be taken into account. Password and Authentication Operations Figure 13. Device (Card) Card Number VERIFY A COMPUTE Challenge B Challenge B READ ACCESS VERIFY RPW DATA Checksum (CS) VERIFY WPW VERIFY CS Write DATA WRITE ACCESS AUTHENTICATION Host (Reader) COMPUTE Challenge A Challenge A VERIFY B Read Password (RPW) VERIFY CS Write Password (WPW) DATA CS 13 2023KS–SMEM–10/09 12.2. Checksum The AT88SC0404C implements a data validity check function in the form of a checksum, which may function in standard, authentication or encryption modes. In the standard mode, the checksum is implemented as a Modification Detection Code (MDC), in which the host may read an MDC from the device in order to verify that the data sent was received correctly. In the authentication and encryption modes, the checksum becomes more powerful since it provides a bidirectional data integrity check and data origin authentication capability in the form of a Message Authentication Code (MAC). Only the host/device that carried out a valid authentication is capable of computing a valid MAC. While operating in the authentication or encryption modes, the use of a MAC is required. For an ingoing command, if the device calculates a MAC different from the MAC transmitted by the host, not only is the command abandoned but the mode is also reset. A new authentication and/or encryption activation will be required to reactivate the MAC. 12.3. Encryption The data exchanged between the device and the host during read, write and verify password commands may be encrypted to ensure data confidentiality. The issuer may choose to require encryption for a user zone by settings made in the configuration memory. Any one of four keys may be selected for use with a user zone. In this case, activation of the encryption mode is required in order to read/write data in the zone and only encrypted data will be transmitted. Even if not required, the host may elect to activate encryption provided the proper keys are known. 12.4. Supervisor Mode Enabling this feature allows the holder of one specific password to gain full access to all eight password sets, including the ability to change passwords. 12.5. Modify Forbidden No write access is allowed in a user zone protected with this feature at any time. The user zone must be written during device personalization prior to blowing the security fuses. 12.6. Program Only For a user zone protected by this feature, data within the zone may be changed from a “1” to a “0”, but never from a “0” to a “1”. 13. Initial Device Programming To enable the security features of CryptoMemory, the device must first be personalized to set up several registers and load in the appropriate passwords and keys. This is accomplished through programming the configuration memory of CryptoMemory using simple write and read commands. To gain access to the configuration memory, the secure code must first be successfully presented. For the AT88SC0404C device, the secure code is $60 57 34. After writing and verifying data in the configuration memory, the security fuses must be blown to lock this information in the device. For additional information on personalizing CryptoMemory, please see the application notes Programming CryptoMemory for Embedded Applications and Initializing CryptoMemory for Smart Card Applications (at www.Atmel.com). 14 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C 14. Ordering Information Ordering Code AT88SC0404C-MJ AT88SC0404C-MP AT88SC0404C-MJTG AT88SC0404C-MPTG AT88SC0404C-PU AT88SC0404C-SU AT88SC0404C-WI Package M2 – J Module - ISO M2 – P Module - ISO M2 – J Module - TWI M2 – P Module - TWI 8P3 8S1 7 mil wafer Voltage Range 2.7V–5.5V Temperature Range Commercial (0°C–70°C) Green compliant (exceeds RoHS)/Industrial (−40°C–85°C) Industrial (−40°C–85°C) 2.7V–5.5V 2.7V–5.5V Package Type(1) (2) M2 – J Module : ISO or TWI M2 – P Module : ISO or TWI 8P3 8S1 Note: M2 ISO 7816 Smart Card Module Description M2 ISO 7816 Smart Card Module with Atmel® Logo 8-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC) 1. Formal drawings may be obtained from an Atmel sales office. 2. Both the J and P Module Packages are used for either ISO (T=0 / 2-wire mode) or TWI (2-wire mode only). 15 2023KS–SMEM–10/09 15. Packaging Information Ordering Code: MJ or MJTG Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Round - ∅ 8.5 [mm] Thickness: 0.58 [mm] Pitch: 14.25 mm *Note: Ordering Code: MP or MPTG Module Size: M2 Dimension*: 12.6 x 11.4 [mm] Glob Top: Square - 8.8 x 8.8 [mm] Thickness: 0.58 [mm] Pitch: 14.25 mm The module dimensions listed refer to the dimensions of the exposed metal contact area. The actual dimensions of the module after excise or punching from the carrier tape are generally 0.4 mm greater in both directions (i.e., a punched M2 module will yield 13.0 x 11.8 mm). 16 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C 15.1. Ordering Code: SU 8S1 – JEDEC SOIC C 1 E E1 N L Top View End View e b A A1 SYMBOL A A1 b C D E1 E e L COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 0.40 0˚ NOM – – – – – – – 1.27 BSC – – 1.27 8˚ MAX 1.75 0.25 0.51 0.25 5.05 3.99 6.20 NOTE D Side View Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 3/17/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. C 17 2023KS–SMEM–10/09 15.2. Ordering Code: PU 8P3 – PDIP 1 E E1 N Top View c eA End View COMMON DIMENSIONS (Unit of Measure = inches) D D1 e A2 A SYMBOL A A2 b b2 b3 c D D1 E E1 e eA L MIN − 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 NOM − 0.130 0.018 0.060 0.039 0.010 0.365 − 0.310 0.250 0.100 BSC 0.300 BSC MAX 0.210 0.195 0.022 0.070 0.045 0.014 0.400 − 0.325 0.280 NOTE 2 5 6 6 3 3 4 3 4 b2 b3 4 PLCS L b Side View 0.115 0.130 0.150 2 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information. 2. Dimensions A and L are measured with the pa ckage seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protusions. Mold Flash or protrusions shall not r exceed 0.010 inch. 4. E and eA measured with the leads constained to be perpendicular to datum. r 5. Pointed or rounded lead tips are pre ferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar prot usions. Dambar protrusions shall not exceed r 0.010 (0.25 mm). 01/09/02 REV. B R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 18 AT88SC0404C 2023KS–SMEM–10/09 AT88SC0404C Appendix A. Revision History Doc. Rev. 2023KS 2023JS Date 08/2009 03/2009 SB - TWI Package update Features Section – add ‘Green compliant (exceeds RoHS) to end of ‘Standard 8-lead Plastic Packages’ bullet Added Note to DC Characteristics table and applied to VCC and all 3 instances of Vih symbols in table. Ordering Information page: Add ‘Green compliant (exceeds RoHS) to middle row of Temperature Range Replace ‘Lead-free/Halogen-free. Keep industrial Updated to 2009 Copyright.. 2023IS 2023HS 2023HS 11/2008 04/2007 03/2007 Updated timing diagrams. Final release version. Implemented revision history. Removed Industrial package offerings. Removed 8Y4 offering. Replaced User Zone, Memory Configuration, and Write Lock Example tables with new information Comments 19 2023KS–SMEM–10/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support securemem@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2009 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 2023KS–SMEM–10/09