AT90S1200

Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 89 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 12 MIPS Throughput at 12 MHz Data and Non-volatile Program Memory – 1K Byte of In-System Programmable Flash Endurance: 1,000 Write/Erase Cycles – 64 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – SPI Serial Interface for In-System Programming Special Microcontroller Features – Low-power Idle and Power-down Modes – External and Internal Interrupt Sources – Selectable On-chip RC Oscillator for Zero External Components Specifications – Low-power, High-speed CMOS Process Technology – Fully Static Operation Power Consumption at 4 MHz, 3V, 25°C – Active: 2.0 mA – Idle Mode: 0.4 mA – Power-down Mode: 1 XTAL1 clock cycle High: > 4 XTAL1 clock cycles Serial Programming Algorithm When writing serial data to the AT90S1200, data is clocked on the rising edge of SCK. When reading data from the AT90S1200, data is clocked on the falling edge of SCK. See Figure 35 and Table 20 for timing details. To program and verify the AT90S1200 in the Serial Programming mode, the following sequence is recommended (See 4-byte instruction formats in Table 17): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. If a crystal is not connected across pins XTAL1 and XTAL2 or the device is not running from the Internal RC Oscillator, apply a clock signal to the XTAL1 pin. If the programmer can not guarantee that SCK is held low during power-up, RESET must be given a positive pulse after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the MOSI (PB5) pin. 44 AT90S1200 0838H–AVR–03/02 AT90S1200 3. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2. See Table 21 on page 47 for tWD_ERASE value. 4. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Wait tWD_PROG after transmitting the instruction. In an erased device, no $FFs in the data file(s) needs to be programmed. See Table 22 on page 47 for tWD_PROG value. 5. Any memory location can be verified by using the Read instruction which returns the content at the selected address at the serial output MISO (PB6) pin. At the end of the programming session, RESET can be set high to commence normal operation. 6. Power-off sequence (if needed): Set XTAL1 to “0” (if a crystal is not used or the device is running from the Internal RC Oscillator). Set RESET to “1”. Turn VCC power off. Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2. See Table 18 for P1 and P2 values. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time tWD_PROG before programming the next byte. See Table 22 for tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device. Table 18. Read Back Value during EEPROM Polling Part AT90S1200 P1 $00 P2 $FF Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $FF. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $FF, so when programming this value, the user will have to wait for at least tWD_PROG before programming the next byte. As a chiperased device contains $FF in all locations, programming of addresses that are meant to contain $FF, can be skipped. 45 0838H–AVR–03/02 Figure 35. Serial Programming Waveforms Table 19. Serial Programming Instruction Set for AT90S1200 Instruction Format Instruction Programming Enable Chip Erase Read Program Memory Write Program Memory Read EEPROM Memory Write EEPROM Memory Write Lock Bits Byte 1 1010 1100 1010 1100 0010 H000 0100 H000 1010 0000 1100 0000 1010 1100 Byte 2 0101 0011 100x xxxx 0000 000a 0000 000a 0000 0000 0000 0000 1111 1211 Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb bbbb bbbb 00bb bbbb 00bb bbbb xxxx xxxx Byte4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii oooo oooo iiii iiii xxxx xxxx Operation Enable serial programming while RESET is low. Chip erase both Flash and EEPROM memory arrays. Read H (high or low) byte o from program memory at word address a:b. Write H (high or low) byte i to program memory at word address a:b. Read data o from EEPROM memory at address b. Write data i to EEPROM memory at address b. Write Lock bits. Set bits 1,2 = “0” to program Lock bits. Read Signature 0011 0000 xxxx xxxx xxxx xxbb oooo oooo Read signature byte o from address b.(1) Byte Note: a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High byte, o = data out, i = data in, x = don’t care, 1 = Lock Bit 1, 2 = Lock Bit 2 Note: 1. The signature bytes are not readable in lock mode 3 (i.e., both Lock bits programmed). 46 AT90S1200 0838H–AVR–03/02 AT90S1200 Serial Programming Characteristics Figure 36. Serial Programming Timing MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH Table 20. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 2.7 - 6.0V (unless otherwise noted) Symbol 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Parameter Oscillator Frequency (VCC = 2.7 - 4.0V) Oscillator Period (VCC = 2.7 - 4.0V) Oscillator Frequency (VCC = 4.0 - 6.0V) Oscillator Period (VCC = 4.0 - 6.0V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Min 0 250.0 0 83.3 4.0 tCLCL tCLCL 1.25 tCLCL 2.5 tCLCL 10.0 16.0 32.0 12.0 Typ Max 4.0 Units MHz ns MHz ns ns ns ns ns ns Table 21. Minimum Wait Delay after the Chip Erase Instruction Symbol tWD_ERASE 3.2V 18 ms 3.6V 14 ms 4.0V 12 ms 5.0V 8 ms Table 22. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol tWD_PROG 3.2V 9 ms 3.6V 7 ms 4.0V 6 ms 5.0V 4 ms 47 0838H–AVR–03/02 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin Except RESET with Respect to Ground ...............................-1.0V to VCC+0.5V Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins................................ 200.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40×C to 85×C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST RI/O ICC Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Output Low Voltage(3) (Ports B, D) Output High Voltage(4) (Ports B, D) Input Leakage Current I/O pin Input Leakage Current I/O pin Reset Pull-up Resistor I/O Pin Pull-up Resistor Power Supply Current Active Mode, VCC = 3V, 4 MHz Idle Mode VCC = 3V, 4 MHz ICC Power-down mode (5) Condition (Except XTAL1) (XTAL1) (Except XTAL1, RESET) (XTAL1) (RESET) IOL = 20 mA, VCC = 5V IOL = 10 mA, VCC = 3V IOH = -3 mA, VCC = 5V IOH = -1.5 mA, VCC = 3V VCC = 6V, pin low (absolute value) VCC = 6V, pin high (absolute value) Min -0.5 -0.5 0.6 VCC 0.7 VCC 0.85 (2) (2) Typ Max 0.3 VCC (1) Units V V V V V V V V V 0.3 VCC(1) VCC + 0.5 VCC + 0.5 VCC + 0.5 0.6 0.5 VCC(2) 4.3 2.3 8.0 980.0 100.0 35.0 500.0 120.0 3.0 1.0 9.0