AT90S2313-10SC

Features • Utilizes the AVR® RISC Architecture • AVR – High-performance and Low-power RISC Architecture – 118 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Up to 10 MIPS Throughput at 10 MHz Data and Non-volatile Program Memory – 2K Bytes of In-System Programmable Flash Endurance 1,000 Write/Erase Cycles – 128 Bytes of SRAM – 128 Bytes of In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles – Programming Lock for Flash Program and EEPROM Data Security Peripheral Features – One 8-bit Timer/Counter with Separate Prescaler – One 16-bit Timer/Counter with Separate Prescaler, Compare, Capture Modes and 8-, 9-, or 10-bit PWM – On-chip Analog Comparator – Programmable Watchdog Timer with On-chip Oscillator – SPI Serial Interface for In-System Programming – Full Duplex UART • Special Microcontroller Features – Low-power Idle and Power-down Modes – External and Internal Interrupt Sources • Specifications – Low-power, High-speed CMOS Process Technology – Fully Static Operation Power Consumption at 4 MHz, 3V, 25°C – Active: 2.8 mA – Idle Mode: 0.8 mA – Power-down Mode: 2 XTAL1 clock cycle High: > 2 XTAL1 clock cycles Serial Programming Algorithm When writing serial data to the AT90S2313, data is clocked on the rising edge of SCK. When reading data from the AT90S2313, data is clocked on the falling edge of SCK. See Figure 54, Figure and Table 29 for timing details. To program and verify the AT90S2313 in the Serial Programming mode, the following sequence is recommended (See 4-byte instruction formats in Table 28): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to “0”. If a crystal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held low during Power-up. In this case, RESET must be given a positive pulse of at least two XTAL1 cycles duration after SCK has been set to “0”. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to the MOSI (PB5) pin. 3. The serial programming instructions will not work if the communication is out of synchronization. When in sync, the second byte ($53) will echo back when issu- 68 AT90S2313 0839I–AVR–06/02 AT90S2313 ing the third byte of the Programming Enable instruction. Whether the echo is correct or not, all four bytes of the instruction must be transmitted. If the $53 did not echo back, give SCK a positive pulse and issue a new Programming Enable instruction. If the $53 is not seen within 32 attempts, there is no functional device connected. 4. If a Chip Erase is performed (must be done to erase the Flash), wait tWD_ERASE after the instruction, give RESET a positive pulse, and start over from step 2. See Table 30 for tWD_ERASE value. 5. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. Use Data Polling to detect when the next byte in the Flash or EEPROM can be written. If polling is not used, wait tWD_PROG before transmitting the next instruction. See Table 31 for tWD_PROG value. In an erased device, no $FFs in the data file(s) need to be programmed. 6. Any memory location can be verified by using the Read instruction that returns the content at the selected address at the serial output MISO (PB6) pin. 7. At the end of the programming session, RESET can be set high to commence normal operation. 8. Power-off sequence (if needed): Set XTAL1 to “0” (if a crystal is not used). Set RESET to “1”. Turn VCC power off. Data Polling EEPROM When a byte is being programmed into the EEPROM, reading the address location being programmed will give the value P1 until the auto-erase is finished, and then the value P2. See Table 27 for P1 and P2 values. At the time the device is ready for a new EEPROM byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the values P1 and P2, so when programming these values, the user will have to wait for at least the prescribed time tWD_PROG before programming the next byte. See Table 30 for tWD_PROG value. As a chip-erased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. This does not apply if the EEPROM is reprogrammed without first chip-erasing the device. Table 27. Read Back Value during EEPROM Polling Part AT90S2313 P1 $80 P2 $7F 69 0839I–AVR–06/02 Data Polling Flash When a byte is being programmed into the Flash, reading the address location being programmed will give the value $7F. At the time the device is ready for a new byte, the programmed value will read correctly. This is used to determine when the next byte can be written. This will not work for the value $7F, so when programming this value, the user will have to wait for at least tWD_PROG before programming the next byte. As a chiperased device contains $FF in all locations, programming of addresses that are meant to contain $FF can be skipped. Figure 54. Serial Programming Waveforms Table 28. Serial Programming Instruction Set Instruction Format Instruction Programming Enable Chip Erase Byte 1 1010 1100 1010 1100 0010 H000 Read Program Memory 0100 H000 Write Program Memory Read EEPROM Memory Write EEPROM Memory Write Lock Bits Read Signature Bytes Note: Note: 1010 0000 1100 0000 1010 1100 0011 0000 xxxx xxxx xxxx xxxx 111x x21x xxxx xxxx xbbb bbbb xbbb bbbb xxxx xxxx xxxx xxbb oooo oooo iiii iiii xxxx xxxx oooo oooo xxxx xxaa bbbb bbbb iiii iiii Byte 2 0101 0011 100x xxxx xxxx xxaa Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb Byte4 xxxx xxxx xxxx xxxx oooo oooo Operation Enable serial programming while RESET is low. Chip erase Flash and EEPROM memory arrays. Read H (high or low) data o from program memory at word address a:b. Write H (high or low) data i to program memory at word address a:b. Read data o from EEPROM memory at address b. Write data i to EEPROM memory at address b. Write Lock bits. Set bits 1,2 = “0” to program Lock bits. Read signature byte o at address b.(1) a = address high bits, b = address low bits, H = 0 – Low byte, 1 – High Byte, o = data out, i = data in, x = don’t care, 1 = Lock bit 1, 2 = Lock bit 2. 1. The signature bytes are not readable in lock mode 3, i.e. both Lock bits programmed. 70 AT90S2313 0839I–AVR–06/02 AT90S2313 Serial Programming Characteristics Figure 55. Serial Programming Timing MOSI tOVSH SCK MISO tSLIV tSHSL tSHOX tSLSH Table 29. Serial Programming Characteristics, TA = -40°C to 85°C, V CC = 2.7 - 6.0V (unless otherwise noted) Symbol 1/tCLCL tCLCL 1/tCLCL tCLCL tSHSL tSLSH tOVSH tSHOX tSLIV Parameter Oscillator Frequency (VCC = 2.7 - 6.0V) Oscillator Period (VCC = 2.7 - 6.0V) Oscillator Frequency (VCC = 4.0 - 6.0V) Oscillator Period (VCC = 4.0 - 6.0V) SCK Pulse Width High SCK Pulse Width Low MOSI Setup to SCK High MOSI Hold after SCK High SCK Low to MISO Valid Min 0 250.0 0 100.0 2.0 tCLCL 2.0 tCLCL tCLCL 2.0 tCLCL 10.0 16.0 32.0 10.0 Typ Max 4.0 Units MHz ns MHz ns ns ns ns ns ns Table 30. Minimum Wait Delay after the Chip Erase Instruction Symbol tWD_ERASE 3.2V 18 ms 3.6V 14 ms 4.0V 12 ms 5.0V 8 ms Table 31. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol tWD_PROG 3.2V 9 ms 3.6V 7 ms 4.0V 6 ms 5.0V 4 ms 71 0839I–AVR–06/02 Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55°C to +125°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin Except RESET with Respect to Ground ...............................-1.0V to VCC +0.5V Voltage on RESET with Respect to Ground ....-1.0V to +13.0V Maximum Operating Voltage ............................................ 6.6V DC Current per I/O Pin ............................................... 40.0 mA DC Current VCC and GND Pins ................................ 200.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol VIL VIL1 VIH VIH1 VIH2 VOL VOH IIL IIH RRST RI/O ICC Parameter Input Low Voltage Input Low Voltage Input High Voltage Input High Voltage Input High Voltage Output Low Voltage(3) (Ports B, D) Output High Voltage(4) (Ports B, D) Input Leakage Current I/O pin Input Leakage Current I/O pin Reset Pull-up Resistor I/O Pin Pull-up Resistor Power Supply Current Active Mode, V CC = 3V, 4 MHz Idle Mode VCC = 3V, 4 MHz Power-down Mode(5) Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current Analog Comparator Propagation Delay WDT enabled, VCC = 3V WDT disabled, VCC = 3V VCC = 5V Vin = VCC /2 VCC = 5V Vin = VCC/2 VCC = 2.7V VCC = 4.0V -50.0 750.0 500.0 9.0