AT91CAP9S500A_1

Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Additional Embedded Memories – One 32 Kbyte Internal ROM, Two-cycle Access at Maximum Matrix Speed – One 32 Kbyte Internal SRAM, Single-cycle Access at Maximum Matrix Speed External Bus Interface (EBI) – EBI Supports Mobile DDR, SDRAM, Low Power SDRAM, Static Memory, Synchronous CellularRAM, ECC-enabled NAND Flash and CompactFlash™ Metal Programmable (MP) Block – 500,000 Gates/250,000 Gates Metal Programmable Logic (through 5 Metal Layers) for AT91CAP9S500A/AT91CAP9S250A Respectively – Ten 512 x 36-bit Dual Port RAMs – Eight 512 x 72-bit Single Port RAMs – High Connectivity for Up to Three AHB Masters and Four AHB Slaves – Up to Seven AIC Interrupt Inputs – Up to Four DMA Hardware Handshake Interfaces – Delay Lines for Double Data Rate Interface – UTMI+ Full Connection – Up to 77 Dedicated I/Os LCD Controller – Supports Passive or Active Displays – Up to 24 Bits per Pixel in TFT Mode, Up to 16 Bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Wider Screen Buffers Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format USB 2.0 Full Speed (12 Mbits per second) OHCI Host Double Port – Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels USB 2.0 High Speed (480 Mbits per second) Device Port – On-chip Transceiver, 4 Kbyte Configurable Integrated DPRAM – Integrated FIFOs and Dedicated DMA Channels – Integrated UTMI+ Physical Interface Ethernet MAC 10/100 Base T – Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – 128-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Multi-Layer Bus Matrix – Twelve 32-bit-layer Matrix, Allowing a Maximum of 38.4 Gbps of On-chip Bus Bandwidth at Maximum 100 MHz System Clock Speed – Boot Mode Select Option, Remap Command Fully-featured System Controller, Including – Reset Controller, Shutdown Controller • • • Customizable Microcontroller Processor AT91CAP9S500A AT91CAP9S250A • Preliminary • • • • • • 6264C–CAP–24-Mar-09 • • • • • • • • • • • • • • • • – Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-Time Timer Reset Controller (RSTC) – Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDC) – Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) – Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 8 to 16 MHz On-chip Oscillator – Two PLLs up to 240 MHz – One USB 480 MHz PLL Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-Time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD) – 128 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output DMA Controller (DMAC) – Acts as one Bus Matrix Master – Embeds 4 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control – Supports Four External DMA Requests and Four Internal DMA Requests from the Metal Programmable Block (MPBlock) Twenty-two Peripheral DMA Controller Channels (PDC) One 2.0A and 2.0B Compliant CAN Controller – 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two Multimedia Card Interfaces (MCI) – SDCard/SDIO and MultiMedia™ Card 3.31 Compliant – Supports SDHC Devices – Automatic Protocol Control and Fast Automatic Data Transfers with PDC Two Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One AC97 Controller (AC97C) – 6-channel Single AC97 Analog Front End Interface, Slot Assigner 2 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects – Synchronous Communications at Up to 90 Mbits/sec One Three-channel 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 20-bit PWM Controller (PWMC) One Two-wire Interface (TWI) – Master and Slave Mode Support, All Two-wire Atmel EEPROMs Supported One 8-channel, 10-bit Analog-to-Digital Converter (ADC) – Eight Channels Multiplexed with Digital I/Os IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: – 1.08V to 1.32V for VDDCORE and VDDBU, VDDUPLL and VDDUTMIC – 3.0V to 3.6V for VDDOSC, VDDPLL and VDDIOP0 (Peripheral I/Os) and VDDANA (ADC) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOP1 (Peripheral I/Os), VDDIOM (Memory I/Os) and VDDMPIOA/VDDMPIOB (MP Block I/Os) Available in 400-ball LFBGA RoHS-compliant Package Can also be Delivered in a 324-ball TFBGA RoHS-compliant Package According to User Needs • • • • • • • • • 1. Description The AT91CAP9S500A/AT91CAP9S250A family is based on the integration of an ARM926EJ-S processor with fast ROM and SRAM memories, and a wide range of peripherals. By providing up to 500K gates of metal programmable logic, AT91CAP9S500A/AT91CAP9S250A is the ideal platform for creating custom designs. The AT91CAP9S500A/AT91CAP9S250A embeds a USB High-speed Device, a 2-port USB OHCI Host, an LCD Controller, a 4-channel DMA Controller, and one Image Sensor Interface. It also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM generators, Multimedia Card interface, and one CAN Controller. The AT91CAP9S500A/AT91CAP9S250A is architectured on a 12-layer matrix, allowing a maximum internal bandwidth of twelve 32-bit buses. It also features one external memory bus (EBI) capable of interfacing with a wide range of memory devices. The AT91CAP9S500A/AT91CAP9S250A is packaged in a 400-ball LFBGA RoHS-compliant package. It can also be delivered in a 324-ball TFBGA RoHS-compliant package according to the customer’s requirements. 3 6264C–CAP–24-Mar-09 TST UTMI+ Transc. Transc. Transc. V B PL G HSLR C HSDP D FM S FSDP DM HD HDPA M HD A HDPB M IS B I IS _P IC IS _D K I _O IS HS -IS I I IS _VSYN _D1 I_ Y C 1 M LC CKNC LD C D0 LCDV -LC S LCDH YN DD S LCDD Y C 23 ON LCDD TCC DCEN K C ER ET XC ECXE K-E NT ERRS -E XC T ERXE -EC XE K/E RO ET X0 -E L R REF -R CK EMX0 ER XD -X EMDCETX 3 V 3 ED F1 IO 0 BM 0 S System Controller JTAG Boundary Scan LCD Controller 10/100 Ethernet MAC USB High-Speed Device USB OHCI In-Circuit Emulator TD TDI TMO TC S RTK C NT K R JT ST AG SE L Note: EBI CompactFlash NAND Flash & ECC Figure 2-1. 2. AT91CAP9S500A/AT91CAP9S250A Block Diagram -D 3 CD CK O A3 1 D0 PI -M O A0 PI M TW TW D CK CT RTS0 SC S0-CT RD K0 -R S2 T TXX0 -SCS2 D0-RDK2 -T X XD2 2 CA CA NT NRX NP X NPCS NPCS3 NPCS2 C1 SP S0 M CK O M SI PW IS O M 0PW M TC 3 L TI K0 OTI A0 TC O -T LK B0 IO 2 -T A IO 2 AC B2 AC97 AC 97CK AC97 FS 9 RX TK 7TX TF0-T TD 0- K1 T RD 0-T F1 DM R0 D A RQ R F0-RD1 0- K0 -RF1 DM -R 1 AK R1 AD Q3 0AD AD 7 TR IG AD VDVR E G DA F ND N ANA A M PI 1. For information on signal multiplexing refer to Table 22-3, “EBI Pins and External Device Connections”. ARM926EJ-S Processor ICache 16K bytes MMU Bus Interface DCache 16K bytes O MCI0_, MCI1_ SPI0_, SPI1_ B 0M PI O B4 4 4 FIFO LUT FIFO FIFO DMA I D FIFO DMA DMA DMA DMA MASTER SLAVE FIQ IRQ0-IRQ1 AIC DBGU DRXD DTXD PCK0-PCK3 PDC Image Sensor Interface PMC PLLRCA PLLA PLLRCB PLLB XIN XOUT 12-layer Matrix OSC DDRSDR Controller WDT PIT Burst Cellular Memory Controller PIOA PIOB PIOC PIOD APB 10x DPR 512x36 PDC PDC CAN SPI0 SPI1 PWMC TC0 TC1 TC2 AC97C USART0 USART1 USART2 SSC0 SSC1 PDC PDC PDC TWI PDC 8-channel 10-bit ADC Metal Programable Block 500K Gates (CAP9500) 250K Gates (CAP9250) 8x SPR 512x72 ROM 32Kbytes Peripheral Bridge SRAM 32Kbytes 4-channel DMA 4 GPREG D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A22 A16/BA0 A17/BA1 NCS0 NCS1/BCCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKN SDCS DQS0, DQS1 SDCKE/BCCRE RAS/BCADV, CAS/BCOE SDWE/BCWE, SDA10 NANDOE, NANDWE BCOWAIT XIN32 XOUT32 OSC RTT Static Memory Controller SHDN WKUP 24-channel Peripheral DMA SHDC AT91CAP9S500A/AT91CAP9S250A Block Diagram VDDBU POR RSTC VDDCORE POR NWAIT A23-A24 NCS2 NCS3/NANDCS NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 D16-D31 AT91CAP9S500A/AT91CAP9S250A D L L NRST PDC MCI0 MCI1 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Name Signal Description List Function Power Supplies Type Active Level Comments VDDIOM VDDIOP0 VDDIOP1 VDDIOMPA VDDIOMPB VDDBU VDDPLL VDDUTMII VDDUTMIC VDDUPLL VDDANA VDDCORE GND GNDPLL GNDUTMII GNDUTMIC GNDUPLL GNDANA GNDBU GNDTHERMAL EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Peripherals I/O Lines Power Supply MP Block I/O A Lines Power Supply MP Block I/O B Lines Power Supply Backup I/O Lines Power Supply PLL Power Supply USB UTMI+ Interface Power Supply USB UTMI+ Core Power Supply USB UTMI+ PLL Power Supply ADC Analog Power Supply Core Chip Power Supply Ground PLL Ground USB UTMI+ Interface Ground USB UTMI+ Core Ground USB UTMI+ PLL Ground ADC Analog Ground Backup Ground Thermal Ground Ball Power Power Power Power Power Power Power Power Power Power Power Power Ground Ground Ground Ground Ground Ground Ground Ground 1.65V to 3.6V 3.0V to 3.6V 1.65V to 3.6V 1.65V to 3.6V 1.65V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 1.08V to 1.32V 3.0V to 3.6V 1.08V to 1.32V Thermally coupled with package substrate Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output PLL A Filter PLL B Filter Programmable Clock Output Input Output Input Output Input Input Output Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-Up Input Output Input Do not tie over VDDBU Accept between 0V and VDDBU 5 6264C–CAP–24-Mar-09 Table 3-1. Signal Name Signal Description List (Continued) Function ICE and JTAG Type Active Level Comments NTRST TCK TDI TDO TMS JTAGSEL RTCK Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Return Test Clock Reset/Test Input Input Input Output Input Input Output Low No pull-up resistor No pull-up resistor No pull-up resistor No pull-up resistor Pull-down resistor NRST TST BMS Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit - DBGU I/O Input Input Low Pull-up resistor Pull-down resistor Pull-up resistor DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input Input Input PIO Controller - PIOA - PIOB - PIOC - PIOD PA0 - PA31 PB0 - PB31 PC0 - PC31 PD0 - PD31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D I/O I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Direct Memory Access Controller - DMA DMARQ0-DMARQ3 DMA Requests Input External Bus Interface - EBI D0 - D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset 0 at reset Static Memory Controller - SMC NCS0 - NCS5 NWR0 - NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output Low Low Low Low Low 6 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Table 3-1. Signal Name Signal Description List (Continued) Function CompactFlash Support Type Active Level Comments CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines NAND Flash Support Output Output Output Output Output Output Output Low Low Low Low Low Low NANDCS NANDOE NANDWE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable DDR/SDRAM Controller Output Output Output Low Low Low SDCK SDCKN DQS0 - DQS1 DQM0 - DQM1 DQM2 - DQM3 SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 DDR/SDRAM Clock DDR Inverted Clock DDR Data Qualifier Strobes DDR/SDRAM Data Masks DDR/SDRAM Data Masks DDR/SDRAM Clock Enable DDR/SDRAM Controller Chip Select DDR/SDRAM Bank Select DDR/SDRAM Write Enable DDR/SDRAMRow and Column Signal DDR/SDRAM Address 10 Line Output Output I/O Output Output Output Output Output Output Output Output Low Low High Low Burst CellularRAM Controller BCCK BCCRE BCADV BCWE BCOE BCOWAIT Burst CellularRAM Clock Burst CellularRAM Enable Burst CellularRAM Burst Advance Signal Burst CellularRAM Write Enable Burst CellularRAM Output Enable Burst CellularRAM Output Wait Output Output Output Output Output Input Multimedia Card Interface MCI MCIx_CK MCIx_CD MCIx_D0 - D3 Multimedia Card Clock Multimedia Card Command Multimedia Card Data Output I/O I/O 7 6264C–CAP–24-Mar-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Comments Universal Synchronous Asynchronous Receiver Transmitter USART SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send I/O I/O Input Output Input Synchronous Serial Controller - SSC TDx RDx TKx RKx TFx RFx SSCx Transmit Data SSCx Receive Data SSCx Transmit Clock SSCx Receive Clock SSCx Transmit Frame Sync SSCx Receive Frame Sync AC97 Controller - AC97C AC97RX AC97TX AC97FS AC97CK AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Timer/Counter - TC TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Input Output Output Input Output Input I/O I/O I/O I/O Pulse Width Modulation Controller- PWMC PMWx Pulse Width Modulation Output Output Serial Peripheral Interface - SPI SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1 - SPIx_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select Two-Wire Interface - TWI TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O I/O I/O I/O I/O Output Low Low 8 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Table 3-1. Signal Name Signal Description List (Continued) Function CAN Controller Type Active Level Comments CANRX CANTX CAN input CAN output LCD Controller - LCDC Input Output LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control Ethernet 10/100 EMAC Input Output Output Output Output Output ETXCK/EREFCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Transmit Clock or Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. USB High Speed Device Input Input Output Output Output Input Input Input Input Input Output I/O Output High MII only, REFCK in RMII MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII MII only MII only RMII only FSDM FSDP HSDM HSDP VBG PLLRCU USB Full Speed Data USB Full Speed Data + USB High Speed Data USB High Speed Data + Bias Voltage Reference USB PLL Test Pad Analog Analog Analog Analog Analog Analog 9 6264C–CAP–24-Mar-09 Table 3-1. Signal Name Signal Description List (Continued) Function OHCI USB Host Port Type Active Level Comments HDPA HDMA HDPB HDMB USB Host Port A Data + USB Host Port A Data USB Host Port B Data + USB Host Port B Data ADC Analog Analog Analog Analog AD0-AD7 ADVREF ADTRIG Analog Inputs ADC Voltage Reference ADC Trigger Analog Analog Input Image Sensor Interface - ISI ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data Clock MPBLOCK - MPB Input Output Input Input Input MPIOA0-MPIOA31 MPIOB0-MPIOB44 MPBlock I/Os A MPBlock I/Os B I/O I/O 10 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 4. Package and Pinout The AT91CAP9S500A/AT91CAP9S250A is available in two packages: • a 400-ball RoHS-compliant LFBGA package, 17 x 17 mm, 0.8 mm ball pitch • a 324-ball RoHS-compliant TFBGA package, 15 x 15 mm, 0.8 mm ball pitch 4.1 400-ball LFBGA Package Outline Figure 4-1 shows the orientation of the 400-ball BGA Package. A detailed mechanical description is given in the section “AT91CAP9S500A/AT91CAP9S250A Mechanical Characteristics” of the product datasheet. Figure 4-1. 400-ball LFBGA Package Outline and Marking (Top View) Top View 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CAP9 ABCDEF GHJ KL MNPRT UV W A1 Corner Y A1 Corner 11 6264C–CAP–24-Mar-09 4.2 400-ball LFBGA Package Pinout AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package Pin F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 Signal Name PA3 PA4 PA8 PA5 PA6 VDDIOM VDDIOP0 PC24 NC VDDCORE GNDIO PB23 PB6 NC NC NC GNDPLL WKUP0 SHDW PLLRCA PA7 PA10 PA11 PA9 PA12 PD10 GNDIO GNDCORE VDDIOP0 PC8 PB25 PB21 PB8 PB0 PB2 NC VDDPLL Pin L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 L19 L20 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 M17 Signal Name PA22 PA25 PA29 PA31 PD6 GNDIO GNDCORE PA18 GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDCORE GNDIO VDDCORE MPIOB28 MPIOB32 MPIOB34 MPIOB31 MPIOB29 PA26 PA30 PD11 PD12 PD13 PD15 GNDCORE PA28 GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL NRD MPIOB26 GNDIO MPIOB16 GNDCORE Pin T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PD22 PD23 PD30 VDDCORE SDCS DQS0 D4 D11 D14 SDA10 VDDCORE MPIOA0 MPIOA9 GNDIO MPIOA25 MPIOA24 MPIOA29 MPIOB3 MPIOB17 MPIOB18 PD25 PD31 BCCLK A0 D0 D1 NWR1 DQS1 A7 A13 A20 GNDIO MPIOA4 MPIOA11 MPIOA16 VDDMPIOA MPIOA23 Table 4-1. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 PC5 PC3 PC2 PC1 PC0 BMS NRST Signal Name GNDCORE PB18 PB17 PB14 PB15 GNDANA PB26 VDDIOP0 GNDIO FSDP FSDM HSDP HSDM PC17 PC16 PC14 PC11 PC10 PC9 TDO TCK PB20 PB19 PB13 ADVREF PB16 PB27 PB24 HDMA VDDIOP0 12 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Table 4-1. Pin B18 B19 B20 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 GNDIO VDDUTMII GNDUTMII PC23 PC22 PC21 PC20 PC18 PC15 PC12 PC6 NTRST TDI VDDANA PB12 PB29 PB9 PB7 HDPA HDPB VDDUPLL VDDUTMIC VBG PC29 PC28 PC27 PC26 PC25 PC19 NANDOE PC7 GNDIO TMS NC PB31 PB22 VDDCORE PB3 AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package (Continued) Pin G18 G19 G20 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 Signal Name GNDCORE TST PLLRCB PA13 PA14 PD0 PA15 PD1 VDDIOP1 VDDCORE GNDIO GNDIO PB10 PB4 VDDMPIOB JTAGSEL GNDCORE GNDPLL NC VDDCORE MPIOB44 XOUT32 XIN32 PD3 PD2 PD5 PA17 PA19 VDDIOP0 PA16 GNDCORE GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDIO GNDBU GNDBU Pin M18 M19 M20 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 Signal Name MPIOB27 MPIOB25 MPIOB24 PD7 PD8 PD16 PD19 PD20 PD29 GNDIO VDDIOM NCS1 VDDCORE A3 A6 VDDCORE MPIOB11 MPIOB13 MPIOB12 MPIOB14 MPIOB15 MPIOB22 MPIOB23 PD9 PD14 PD18 PD27 PD28 VDDIOM NWR3 D8 D10 GNDIO A9 A12 NC MPIOB8 MPIOB0 Pin U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Signal Name MPIOA28 MPIOB6 MPIOB9 PD26 RAS SDCKE D3 VDDIOM D5 D9 D15 A11 GNDCORE A22 MPIOA1 MPIOA6 MPIOA10 MPIOA13 MPIOA17 MPIOA20 MPIOA27 MPIOB5 VDDMPIOB SDWE BCOWAIT NANDWE GNDIO D6 A2 A5 A14 A17 A19 NWR0 MPIOA2 MPIOA5 MPIOA8 MPIOA12 Signal Name 13 6264C–CAP–24-Mar-09 Table 4-1. Pin D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 PB1 HDMB AT91CAP9S500A/AT91CAP9S250A Pinout for 400-ball BGA Package (Continued) Pin J16 J17 J18 J19 J20 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 Signal Name MPIOB42 MPIOB39 MPIOB43 MPIOB41 GNDIO PD4 PA21 PA24 PA27 PA23 GNDIO PA20 VDDCORE GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDTHERMAL GNDCORE MPIOB33 MPIOB30 MPIOB35 MPIOB38 MPIOB40 MPIOB37 MPIOB36 Pin P16 P17 P18 P19 P20 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 Signal Name MPIOB1 MPIOB7 MPIOB10 MPIOB21 VDDMPIOB PD21 PD17 PD24 CAS VDDCORE D2 D7 VDDIOM D13 D12 VDDIOM A16 VDDIOM NC NC NC MPIOB2 MPIOB4 MPIOB19 MPIOB20 Pin W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name MPIOA15 MPIOA21 MPIOA22 GNDIO VDDCORE SDCK SDCKN A1 GNDCORE A4 A8 A10 A15 A18 A21 NCS0 MPIOA3 MPIOA7 VDDMPIOA MPIOA14 MPIOA18 MPIOA19 MPIOA26 MPIOA30 MPIOA31 Signal Name PLLRCU GNDUTMIC GNDUPLL PC30 PA2 PA1 PA0 PC31 GNDIO VDDCORE PC13 PC4 RTCK VDDIOP0 PB30 PB28 PB11 PB5 NC VDDPLL VDDBU XIN XOUT 14 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 4.3 324-ball TFBGA Package Outline Figure 4-2 shows the orientation of the 324-ball TFBGA green package. A detailed mechanical description is given in the section “AT91CAP9S500A/AT91CAP9S250A Mechanical Characteristics” of the product datasheet. Figure 4-2. 324-ball TFBGA Package Outline and Marking (Top View) Top View 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJ KLMNPRTUV A1 Corner A1 Corner CAP9 4.4 324-ball TFBGA Package Pinout The pin assignment for the 324-ball TFBGA package is customizable and dependent upon the needs of the user. Important: It is possible to partially or totally remove the connections to dedicated Metal Programmable I/0s: MPIOAO-MPIOA31 and MPIOB0-MPIOB44. Likewise, PA16-PA31, PB21PB31, PDC0-PC27, PD0-PD10 can be partially or totally disconnected. However, it is incumbent upon the user to ensure that the associated functionality removed is not needed for the intended application. Refer to Section 10.3.1 on page 42, Section 10.3.2 on page 43, Section 10.3.3 on page 44, Section 10.3.4 on page 45 for information on PIO multiplexing and to verify functionality before disconnecting signals. 15 6264C–CAP–24-Mar-09 5. Power Considerations 5.1 Power Supplies The AT91CAP9S500A/AT91CAP9S250A has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage range between1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). • VDDIOP0 pins: Power the Peripherals I/O lines and the USB transceivers; voltage range between 3.0V and 3.6V, 3.3V nominal. • VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. • VDDIOMPA pins: Power the MP Block I/O A lines; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. • VDDIOMPB pins: Power the dedicated MP Block I/O B lines; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage range between1.08V and 1.32V, 1.2V nominal. • VDDPLL pin: Powers the PLL cells; voltage ranges between 3.0V to 3.6V, 3.3V nominal. • VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V to 3.6V, 3.3V nominal. • VDDUTMIC pin: Powers the UTMI+ core; voltage ranges between 1.08V and 1.32V, 1.2V nominal. • VDDUPLL pin: Powers the USB PLL cell; voltage ranges between 1.08V and 1.32V, 1.2V nominal. • VDDANA pin: Powers the ADC cell; voltage ranges between 3.0V and 3.6V, 3.3V nominal. The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GNDIO are common to VDDIOM, VDDIOP0, VDDIOP1, VDDIOMPA and VDDIOMPB pin power supplies. Separated ground pins are provided for VDDCORE, VDDBU, VDDPLL, VDDUTMII, VDDUTMIC, VDDUPLL and VDDANA. These ground pins are, respectively, GNDBU, GNDOSC, GNDPLL, GNDUTMII, GNDUTMIC, GNDUPLL and GNDANA. Special GNDTHERMAL ground balls are thermally coupled with package substrate. 5.2 Power Consumption The AT91CAP9S500A/AT91CAP9S250A consumes about 190 µA of static current on VDDCORE at 25°C. On VDDBU, the current does not exceed 4 µA @25°C. For dynamic power consumption and more details, refer to the Power Consumption section and tables in the Electrical Characteristics section of the product datasheet. 16 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 5.3 Programmable I/O Lines Power Supplies The power supply pins VDDIOM, VDDMPIOA and VDDMPIOB accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The target maximum speed is 100 MHz on the pin DDR/SDR and MPIOA or MPIOB pins loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address and data signals) do not go over 50 MHz. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. Obviously, the device cannot reach its maximum speed if the voltage supplied to the pins is 1.8V only. The user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode. 17 6264C–CAP–24-Mar-09 6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU so that it can be left unconnected for normal operations. The NTRST signal is described in Section 6.3 “Reset Pins” on page 18. All the JTAG signals are supplied with VDDIOP0. 6.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU. 6.3 Reset Pins NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells that manage the processor and the JTAG reset, the NRST pin can be left unconnected. The NRST pin integrates a permanent pull-up resistor of 90 kΩ minimum to VDDIOP0. The NRST signal is inserted in the Boundary Scan. 6.4 PIO Controllers All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up resistor of 90 kΩ minimum. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those multiplexed with the External Bus Interface signals that must be enabled as Peripheral at reset. This is indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shutdown Logic Pins The SHDN pin is an output only, which is driven by the Shutdown Controller only at low level. It can be tied high with an external pull-up resistor at VDDBU only. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 18 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 7. Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • DSP Instruction Extensions • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 16-Kbyte Data Cache, 16-Kbyte Instruction Cache – Virtually-addressed 4-way Associative Cache – Eight words per line – Write-through and Write-back Operation – Pseudo-random or Round-robin Replacement • Write Buffer – Main Write Buffer with 16-word Data Buffer and 4-address Buffer – DCache Write-back Buffer with 8-word Entries and a Single Address Entry – Software Control Drain • Standard ARM v4 and v5 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for each quarter of the page – 16 embedded domains • Bus Interface Unit (BIU) – Arbitrates and Schedules AHB Requests – Separate Masters for both instruction and data access providing complete Matrix system flexibility – Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) 7.2 Bus Matrix • 12-layer Matrix, handling requests from 12 masters • Programmable Arbitration strategy – Fixed-priority Arbitration 19 6264C–CAP–24-Mar-09 – Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master • Burst Management – Breaking with Slot Cycle Limit Support – Undefined Burst Length Support • One Address Decoder provided per Master – Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap • Boot Mode Select – Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory – Allows Handling of Dynamic Exception Vectors 7.3 Matrix Masters The Bus Matrix of the AT91CAP9S500A/AT91CAP9S250A manages twelve Masters and thus each master can perform an access concurrently with the others, assuming that the slave it accesses is available. Each Master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decoding. Table 7-1. Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 Master 6 Master 7 Master 8 Master 9 Master 10 Master 11 List of Bus Matrix Masters ARM926™ Instruction ARM926 Data Peripheral DMA Controller LCD Controller USB High Speed Device Controller Image Sensor Interface DMA Controller Ethernet MAC OHCI USB Host Controller MP Block Master 0 MP Block Master 1 MP Block Master 2 7.4 Matrix Slaves The Bus Matrix of the AT91CAP9S500A/AT91CAP9S250A manages ten Slaves. Each Slave has its own arbiter, thus permitting a different arbitration per Slave to be programmed. 20 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A The LCD Controller, the USB Host and the USB High Speed Device have a user interface mapped as a Slave of the Matrix. They share the same layer, as programming them does not require a high bandwidth. Table 7-2. Slave 0 Slave 1 List of Bus Matrix Slaves Internal SRAM 32 Kbytes MP Block Slave 0 (MP Block Internal Memories) Internal ROM LCD Controller User Interface Slave 2 USB High Speed Device Interface OHCI USB Host Interface Slave 3 Slave 4 Slave 5 Slave 6 Slave 7 Slave 8 Slave 9 MP Block Slave 1 (MP Block Internal Memories) External Bus Interface DDR Controller Port 2 DDR Controller Port 3 MP Block Slave 2 (MP Block External Chip Selects) MP Block Slave 3 (MP Block Internal Peripherals) Internal Peripherals for AT91CAP9 7.5 Master-to-Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in Table 7-3, “AT91CAP9S500A/AT91CAP9S250A Masters to Slaves Access,” on page 22. 21 6264C–CAP–24-Mar-09 Table 7-3. Master AT91CAP9S500A/AT91CAP9S250A Masters to Slaves Access 0 ARM926 Instruction 1 2 Peripheral DMA Ctrl 3 4 5 Image Sensor Interface 6 7 8 OHCI USB Host Ctrl 9 MP Block Master 0 10 MP Block Master 1 11 MP Block Master 2 X X X X X X X X X(1) X(1) X X X USB High Speed Device Ctrl ARM926 Data Slave 0 1 Internal SRAM 32 Kbytes MP Block Slave 0 Internal ROM LCD Controller User Interface X X X X X X X X X X X - X X X - X X X - X X X - X X X - X X X - Ethernet MAC DMA Ctrl LCDCtrl X X X - X X X X X X X X 2 USB High Speed Device Interface OHCI USB Host Interface X X - - - - X - - X X X X X X X X X X X X X X X X X X X X X X X X X X X X 3 4 5 6 MPBlock Slave 1 External Bus Interface DDR Port 0 DDR Port 1 DDR Port 2 DDR Port 3 X - X X (1) X (1) X (1) X (1) X (1) X (1) X (1) X (1) X (1) X(1) X X X X X X X X X X(1) X X - X(1) X X - X(1) X X - X(1) X X X X(1) X X - X(1) X X - X(1) X X X X(1) X X X 7 8 9 MPBlock Slave 2 MPBlock Slave 3 Internal Peripherals Note: 1. DDR Port 2 or Port 3 is selectable for each master through the Matrix Remap Control Register. 22 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 7.6 Peripheral DMA Controller • Acting as one Matrix Master • Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. • Next Pointer Support, forbids strong real-time constraints on buffer management. • Twenty-two Channels – Two for each USART – Two for the Debug Unit – One for the TWI – One for the ADC Controller – Two for the AC97 Controller – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for the each Multimedia Card Interface The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): – DBGU Transmit Channel – USART2 Transmit Channel – USART1 Transmit Channel – USART0 Transmit Channel – AC97 Transmit Channel – SPI1 Transmit Channel – SPI0 Transmit Channel – SSC1 Transmit Channel – SSC0 Transmit Channel – DBGU Receive Channel – TWI Transmit/Receive Channel – ADC Receive Channel – USART2 Receive Channel – USART1 Receive Channel – USART0 Receive Channel – AC97 Receive Channel – SPI1 Receive Channel – SPI0 Receive Channel – SSC1 Receive Channel – SSC0 Receive Channel – MCI1 Transmit/Receive Channel – MCI0 Transmit/Receive Channel 23 6264C–CAP–24-Mar-09 7.7 DMA Controller • Acting as one Matrix Master • Embeds 4 unidirectional channels with programmable priority • Address Generation – Source / destination address programming – Address increment, decrement or no change – DMA chaining support for multiple non-contiguous data blocks through use of linked lists – Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of data into non-contiguous fields in system memory – Gather support for extracting fields from a system memory area into a contiguous transfer – User enabled auto-reloading of source, destination and control registers from initially programmed values at the end of a block transfer – Auto-loading of source, destination and control registers from system memory at end of block transfer in block chaining mode – Unaligned system address to data transfer width supported in hardware • Channel Buffering – 8-word FIFO – Automatic packing/unpacking of data to fit FIFO width • Channel Control – Programmable multiple transaction size for each channel – Support for cleanly disabling a channel without data loss – Suspend DMA operation – Programmable DMA lock transfer support • Transfer Initiation – Support four External DMA Requests and four Internal DMA request from the MP Block – Support for Software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface • Interrupt – Programmable Interrupt generation on DMA Transfer completion Block Transfer completion, Single/Multiple transaction completion or Error condition 7.8 Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART 24 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 25 6264C–CAP–24-Mar-09 8. Memories Figure 8-1. AT91CAP9S500A/AT91CAP9S250A Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF Internal Memory Mapping 0x0000 0000 0x0010 0000 0x0020 0000 Boot Memory (1) SRAM MPB SLAVE0 MPB SLAVE0 ROM LCDC Notes : (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and RCB0, RCB1 256M Bytes 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 0x0030 0000 256M Bytes 0x0040 0000 0x0050 0000 0x2000 0000 EBI Chip Select 1/ EBI BCRAMC 256M Bytes 0x0060 0000 0x0070 0000 UDPHS USB HOST 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 256M Bytes 0x0080 0000 MPB SLAVE1 0x0090 0000 MPB SLAVE1 0x00A0 0000 0x4000 0000 EBI Chip Select 3/ NAND Flash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 EBI DDRSDRC 256M Bytes 0x00B0 0000 MPB SLAVE1 MPB SLAVE1 0x4FFF FFFF 0x5000 0000 256M Bytes 0xFF00 0000 Peripheral Mapping Reserved 0xFFF7 8000 UDPHS 0xFFF7 C000 TCO, TC1, TC2 0xFFF8 0000 MCI0 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF EC00 SSC1 0xFFFA 0000 AC97C 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FC00 EMAC 0xFFFC 0000 ADCC 0xFFFC 4000 ISI 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FFFF 16K Bytes 16K Bytes 0xFFFF FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 0xFFFF FD70 SYSC 0xFFFF FFFF PMC RSTC SHDC RTT PIT WDT SCKCR GPBR Reserved 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16K Bytes 0xFFFF EE00 DBGU 0xFFFF F000 AIC SPI0 0xFFFA 8000 SPI1 0xFFFA C000 CAN0 0xFFFB 0000 Reserved 0xFFFB 4000 Reserved 0xFFFF F800 0xFFFF FA00 0xFFFF F600 PIOC PIOD Reserved 512 bytes 512 bytes 512 bytes 0xFFFF F200 0xFFFF F400 PIOB 512 Bytes PIOA 512 bytes 512 bytes 512 Bytes 0xFFFF E200 0xFFFF E400 0xFFFF E600 0xFFFF E800 0xFFFF EA00 0xFFFF EB10 SSC0 16K Bytes Reserved 16K Bytes 16K Bytes 0x5FFF FFFF 0x6000 0000 System Controller Mapping 0xFFFF C000 256M Bytes 0x6FFF FFFF 0x7000 0000 256M Bytes 0xFFF8 4000 MCI1 0xFFF8 8000 TWI ECC BCRAMC DDRSDRC SMC MATRIX 512 Bytes CCFG DMA 512 Bytes 512 Bytes 512 Bytes 512 bytes 512 Bytes 0x7FFF FFFF 0x8000 0000 MPB SLAVE2 Chip Select 0 0x8FFF FFFF 256M Bytes 0xFFF8 C000 USART0 0xFFF9 0000 USART1 0x9000 0000 MPB SLAVE 2 Chip Select 1 0x9FFF FFFF 256M Bytes 0xFFF9 4000 USART2 0xFFF9 8000 0xA000 0000 MPB SLAVE 2 Chip Select 2 0xAFFF FFFF 256M Bytes 0xFFF9 C000 0xB000 0000 MPB SLAVE 2 Chip Select 3 0xBFFF FFFF 256M Bytes 0xFFFA 4000 0xC000 0000 Undefined (Abort) 768M Bytes 0xFFFB 8000 PWMC 0xFFFB C000 0xEFFF FFFF Undefined (Abort) 0xFCFF FFFF 0xFD00 0000 MPB SLAVE3 0xFE00 0000 MPB SLAVE3 0xFF00 0000 Internal Peripherals 0xFFFF FFFF 0xF000 0000 0xFFFC 8000 208M Bytes 16M Bytes 16M Bytes 16M Bytes Reserved 0xFFFC C000 Reserved 0xFFFF C000 26 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High-performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects NCS0 to NCS5 and SDCS. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M byte of internal memory area. The banks 8 to 11 are directed to MP Block (Slave 2) and may be used to address external memories. The bank 15 is split into three parts, one reserved for the peripherals that provides access to the Advanced Peripheral Bus (APB), the two others are directed to MP Block (Slave 3) and may provide access to the MP Block APB or to other AHB peripherals. Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot and one after remap. Refer to Table 8 -1, “Internal Memory Mapping,” on page 2 8 for details. 8.1 Embedded Memories • 32 Kbyte ROM – Two Cycle Access at full matrix speed • 32 Kbyte Fast SRAM – Single Cycle Access at full matrix speed • 20 Kbyte MP Block Fast Dual Port RAM (ten 512x36 DPR instances) – Used as Dual Port RAM completely managed by MP Block • 32 Kbyte MP Block Fast Single Port RAM (eight 512x72 SPR instances) – Used as Single Port RAM completely managed by MP Block 27 6264C–CAP–24-Mar-09 8.1.1 Internal Memory Mapping Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap Command Bit (RBC) status and the BMS state at reset. REMAP allows the user to layout the internal SRAM bank to 0x0 to ease development. This is done by software once the system boots. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done by way of hardware at reset. Table 8-1. Address Internal Memory Mapping ARM926 I RCB0 = 0 RCB0 = 1 BMS = 0 SRAM NCS0 ARM926 D RCB1 = 0 BMS = 1 ROM SRAM Abort RCB1 = 1 Other Masters 0x0000 0000 BMS = 0 NCS0 BMS = 1 ROM 8.1.1.1 Internal 32 Kbyte Fast SRAM The AT91CAP9S500A/AT91CAP9S250A integrates a 32 Kbyte SRAM, mapped at address 0x0010 0000, which is accessible from the AHB bus. This SRAM is single cycle accessible at full matrix speed. Internal ROM The AT91CAP9S500A/AT91CAP9S250A embeds an Internal ROM, which contains the SAM-BA® program. At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset and before the Remap Command. Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters. The AT91CAP9S500A/AT91CAP9S250A Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 26. 8.1.1.2 8.1.2 If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on Chip Select 0 of the External Bus Interface. 8.1.2.1 BMS = 1, boot on embedded ROM The system boots on Boot Program. • Boot on on-chip RC oscillator • Auto baudrate detection • Downloads and runs an application from external storage media into internal SRAM • Downloaded code size depends on embedded SRAM size • Automatic detection of valid application 28 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • Bootloader on a non-volatile memory – NAND Flash – SDCard on MCI0 – SPI DataFlash®/Serial Flash connected on NPCS0 and NPCS1 of the SPI0 – EEPROM on TWI • SAM-BA Boot in case no valid program is detected in external NVM, supporting: – Serial communication on a DBGU – USB Device HS Port 8.1.2.2 BMS = 0, boot on external memory • Boot on on-chip RC • Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. For optimization purposes, nothing else is done. To speed up the boot sequence user programmed software should perform a complete configuration: • Program the PMC (main oscillator enable or bypass mode) • Program and Start the PLL • Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock • Switch the main clock to the new value 8.2 External Memories The external memories are accessed through the External Bus Interfaces. Each Chip Select line has a 256 Mbyte memory area assigned. Refer to Figure 8-1 on page 26. 8.2.1 External Bus Interface The AT91CAP9S500A/AT91CAP9S250A features one External Bus Interface to offer high bandwidth to the system and to prevent any bottleneck while accessing the external memories. • Optimized for Application Memory Space support • Integrates four External Memory Controllers: – Static Memory Controller – 4-port DDR/SDRAM Controller – Burst/Cellular RAM Controller – SLC NAND Flash ECC Controller • Additional logic for NAND Flash and CompactFlashTM • Optional Full 32-bit External Data Bus • Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select) • Up to 6 chip selects, configurable assignment: – Static Memory Controller on NCS0 – Burst/CellularRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 29 6264C–CAP–24-Mar-09 – Static Memory Controller on NCS3, Optional NAND Flash support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support • One dedicated chip select: – DDR/SDRAM Controller on SDCS 8.2.2 Static Memory Controller • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability – Compliant with LCD Module – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported 8.2.3 DDR/SDRAM Controller • Supported devices: – Standard and Low Power SDRAM (Mobile SDRAM) – Mobile DDR • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path – Mobile DDR with four Internal Banks – Mobile DDR with 16-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable – Multiport (4 Ports) • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • DDR/SDRAM Power-up Initialization by software 30 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • SDRAM CAS Latency of 1, 2 and 3 supported • DDR CAS latency of 3 supported • Auto Precharge Command not used 8.2.4 Burst Cellular RAM Controller • Supported devices: – Synchronous Cellular RAM version 1.0, 1.5 and 2.0 • Numerous configurations supported – 64K, 128K, 256K, 512K Row Address Memory Parts – Cellular RAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Timing parameters specified by software – Only Continuous read or write burst supported • Energy-saving capabilities – Standby and Deep Power Down (DPD) modes supported – Low Power features (PASR/TCSR) supported • Cellular RAM Power-up Initialization by hardware • Cellular RAM CAS latency of 2 and 3 supported (Version 1.0) • Cellular RAM CAS latency of 2, 3, 4, 5 and 6 supported (Version 1.5 and 2.0) • Cellular RAM variable or fixed latency supported (Version 1.5 and 2.0) • Multiplexed address/data bus supported (Version 2.0) • Asynchronous and Page mode not supported 8.2.5 NAND Flash Error Corrected Code Controller • Hardware Error Corrected Code (ECC) Generation – Detection and Correction by Software • Supports NAND Flash and SmartMedia™ Devices with 8- or 16-bit Data Path • Supports NAND Flash/SmartMedia with Page Sizes of 528, 1056, 2112 and 4224 Bytes Specified by Software • Supports 1 bit correction for a page of 512,1024,2048 and 4096 Bytes with 8- or 16-bit Data Path • Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path • Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 Bytes with 8-bit Data Path 31 6264C–CAP–24-Mar-09 9. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that allow configuration of the Matrix and a set of registers for the chip configuration. The chip configuration registers are used to configure: – EBI chip select assignment and voltage range for external memories – MP Block The System Controller peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF C000 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. This allows all the registers of the System Controller to be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instructions have an indexing mode of ± 4 Kbytes. Figure 9-1 on page 33 shows the System Controller block diagram. Figure 8-1 on page 26 shows the mapping of the User Interfaces of the System Controller peripherals. 32 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 9.1 System Controller Block Diagram AT91CAP9S500A/AT91CAP9S250A System Controller Block Diagram System Controller VDDCORE Powered irq0-irq1 fiq periph_irq[2..29] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE POR por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK Real-Time Timer rtt_irq rtt_alarm Debug Unit Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq Figure 9-1. dbgu_irq dbgu_txd proc_nreset PCK debug pit_irq jtag_nreset wdt_irq MCK periph_nreset Bus Matrix Boundary Scan TAP Controller VDDBU POR SLCK backup_nreset SLCK SHDN WKUP backup_nreset XIN32 XOUT32 SLOW CLOCK OSC rtt_alarm Shut-Down Controller Voltage Controller battery_save UDPHSCK 4 General-purpose Backup Registers periph_clk[28] periph_nreset USB High-speed Device Port SLCK UTMI PLL XIN XOUT PLLRCA PLLRCB MAIN OSC PLLA PLLB periph_nreset int UDPHSCK Power Management Controller periph_clk[2..31] pck[0-3] PCK periph_irq[28] MAINCK UHPCK MCK pmc_irq idle UHPCK periph_clk[29] periph_nreset periph_irq[29] USB Host Port PLLACK PLLBCK periph_clk[7..31] periph_nreset periph_clk[2] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD31 periph_irq[2] irq0-irq1 fiq dbgu_txd periph_nreset periph_irq[7..27] in out enable Embedded Peripherals PIO Controllers 33 6264C–CAP–24-Mar-09 9.2 Reset Controller • Based on two Power-on-Reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset • Controls the internal resets and the NRST pin output – Allows shaping a reset signal for the external devices 9.3 Shutdown Controller • Shutdown and Wake-Up logic – Software programmable assertion of the SHDN pin – Deassertion Programmable on a WKUP pin level change or on alarm 9.4 Clock Generator • Embeds a low power 32,768 Hz Slow Clock Oscillator and a low power RC oscillator – Provides the permanent Slow Clock SLCK to the system • Embeds the Main Oscillator – Oscillator bypass feature – Supports 8 to 16 MHz crystals – 12 MHz crystal is required for USB High-Speed Device • Embeds 2 programmable PLLs – Output 80 to 240 MHz clocks – Integrates an input divider to increase output accuracy • Embeds 1 UTMI PLL – 480 MHz Fixed frequency from 12 MHz input clock – Integrated filter 34 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 9-2. Clock Generator Block Diagram Clock Generator XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK PLLRCA PLL and Divider A PLL and Divider B Status Control PLLA Clock PLLACK PLLB Clock PLLBCK PLLRCB Power Management Controller 9.5 Slow Clock Selection The AT91CAP9S500A/AT91CAP9S250A slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external slow clock on XIN32. Configuration is located in the slow clock control register (SCKCR) located at address 0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is present. Refer to the “Clock Generator” section for more details. 9.6 Power Management Controller • Provides: – the Processor Clock PCK – the Master Clock MCK, in particular to the Matrix and the memory interfaces – the USB High-speed Device Clock UDPHSCK – the USB Host Clock UHPCK – independent peripheral clocks, typically at the frequency of MCK – four programmable clock outputs: PCK0 to PCK3 • Five flexible operating modes: – Normal Mode, processor and peripherals running at a programmable frequency – Idle Mode, processor stopped waiting for an interrupt – Slow Clock Mode, processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt – Backup Mode, Main Power Supplies off, VDDBU powered by a battery 35 6264C–CAP–24-Mar-09 Figure 9-3. AT91CAP9S500A/AT91CAP9S250A Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Divider /1,/2,/4 Peripherals Clock Controller ON/OFF DDRCK Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] Idle Mode MCK PCK int periph_clk[..] USB Clock Controller PLLBCK Divider /1,/2,/4 ON/OFF UHPCK 9.7 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real-time OS or Linux®/WinCE® compliant tick generator 9.8 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • Windowed, prevents the processor to be in a dead-lock on the watchdog access 9.9 Real-time Timer • Two Real-time Timers, allowing backup of time with different accuracies – 32-bit Free-running back-up Counter – Integrates a 16-bit programmable prescaler running on the embedded 32,768 Hz oscillator – Alarm Register to generate a wake-up of the system through the Shutdown Controller 9.10 General-Purpose Backup Registers • Four 32-bit backup general-purpose registers 36 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 9.11 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive • Four External Sources plus the Fast Interrupt signal • 8-level Priority Controller – Drives the Normal Interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode – Easy debugging by preventing automatic operations when protect models are enabled • Fast Forcing – Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 9.12 Debug Unit • Composed of two functions – Two-pin UART – Debug Communication Channel (DCC) support • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE Interface 37 6264C–CAP–24-Mar-09 9.13 Chip Identification • Chip ID: 0x039A03A1 (for DevChip) • JTAG ID: 0x15B1B03F • ARM926 TAP ID: 0x0792603F 9.14 PIO Controllers • 4 PIO Controllers, PIOA to PIOD, controlling a total of 128 I/O Lines • Each PIO Controller controls up to 32 programmable I/O Lines – PIOA has 32 I/O Lines – PIOB has 32 I/O Lines – PIOC has 32 I/O Lines – PIOD has 32 I/O Lines • Fully programmable through Set/Clear Registers • Multiplexing of two peripheral functions per I/O Line • For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 38 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 10. Peripherals 10.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each user peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 26. 10.2 Identifiers The AT91CAP9S500A/AT91CAP9S250A embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the AT91CAP9S500A/AT91CAP9S250A. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA-D MPB0 MPB1 MPB2 MPB3 MPB4 US0 US1 US2 MCI0 MCI1 CAN TWI SPI0 SPI1 SSC0 SSC1 AC97 TC0, TC1, TC2 PWMC EMAC Reserved Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A to D MP Block Peripheral 0 MP Block Peripheral 1 MP Block Peripheral 2 MP Block Peripheral 3 MP Block Peripheral 4 USART 0 USART 1 USART 2 Multimedia Card Interface 0 Multimedia Card Interface 1 CAN Controller Two-Wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 AC97 Controller Timer/Counter 0, 1 and 2 Pulse Width Modulation Controller Ethernet MAC Reserved External Interrupt FIQ 39 6264C–CAP–24-Mar-09 Table 10-1. Peripheral ID 24 25 26 27 28 29 30 31 AT91CAP9S500A/AT91CAP9S250A Peripheral Identifiers (Continued) Peripheral Mnemonic ADCC ISI LCDC DMA UDPHS UHP AIC AIC Peripheral Name ADC Controller Image Sensor Interface LCD Controller DMA Controller USB High Speed Device Port USB Host Port Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 External Interrupt 10.2.1 10.2.1.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the DDR/SDRAM Controller • the BCRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-Time Timer • the Watchdog Timer • the Reset Controller • the Power Management Controller • the MP Block The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. Timer Counter Interrupts The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 19 of the Advanced Interrupt Controller. This forces the programmer to read all Timer Counter status registers before branching the right Interrupt Service Routine. The Timer Counter channels clocks cannot be deactivated independently. Switching off the clock of the Peripheral 19 disables the clock of the 3 channels. 10.2.1.3 40 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 10.2.2 DMA Controller Request Signals The requests to the DMA Controller may come from eight different sources: • four external requests • four internal requests from the MPBlock Table 10-2. DMA Controller Request Source and Signal Names Internal DMA Request from MPBlock External DMA Request Channel 3 DMARQ3 Channel 2 DMARQ2 Channel 1 DMARQ1 Channel 0 DMARQ0 Channel 7 MP_DMARQ3 Channel 6 MP_DMARQ2 Channel 5 MP_DMARQ1 Channel 4 MP_DMARQ0 Each request source is selected through the DMAC Channel x Configuration Register. It is also necessary to choose the hardware handshaking interface from the SRC_H2SEL and DST_H2SEL fields. (For more details, see the DMA Controller (DMAC) section and DMAC User Interface in the product datasheet.) 10.3 Peripheral Signal Multiplexing on I/O Lines The AT91CAP9S500A/AT91CAP9S250A features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only may be duplicated within both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 41 6264C–CAP–24-Mar-09 10.3.1 PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A Application Usage Comments Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PWM1 PWM3 PCK0 I/O I/O I/O I/O IRQ1 PCK2 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_HSYNC ISI_VSYNC ISI_MCK ISI_D8 ISI_D9 ISI_D10 ISI_D11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed Function 324-BGA pkg Options(1) Table 10-3. I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Note: Peripheral A MCI0_D0 MCI0_CD MCI0_CK MCI0_D1 MCI0_D2 MCI0_D3 AC97FS AC97CK AC97TX AC97RX IRQ0 DMARQ0 CANTX CANRX TCLK2 DMARQ3 MCI1_CK MCI1_CD MCI1_D0 MCI1_D1 MCI1_D2 MCI1_D3 TXD0 RXD0 RTS0 CTS0 SCK0 PCK1 SPI0_NPCS3 TIOA0 TIOB0 DMARQ1 Peripheral B SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS0 1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application. 42 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 10.3.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Note: Peripheral A TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 PWM0 PWM1 ETXCK/EREFCK ERXDV ETX0 ETX1 ERX0 ERX1 ERXER ETXEN EMDC EMDIO ADTRIG EF100 TCLK0 PWM3 TIOA2 TIOB2 PCK3 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 TWD TWCK TIOA1 TIOB1 PWM2 LCDCC PCK1 Peripheral B Comments Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Application Usage Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed Function 324-BGA pkg Options(1) Table 10-4. 1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application. 43 6264C–CAP–24-Mar-09 10.3.3 PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C Application Usage Comments Reset State I/O I/O I/O PWM1 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 ETX2 ETX3 ERX2 ERX3 ETXER ECRS ECOL ERXCK TCLK1 PWM2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function 324-BGA pkg Options(1) can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed Table 10-5. I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Note: Peripheral A LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM0 PCK0 DRXD DTXD Peripheral B 1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application. 44 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 10.3.4 PIO Controller D Multiplexing Multiplexing on PIO Controller D PIO Controller D I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 Note: Peripheral A TXD1 RXD1 TXD2 RXD2 FIQ DMARQ2 NWAIT NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 NCS2 A23 A24 A25/CFRNW NCS3/NANDCS D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 RTS2 CTS2 RTS1 CTS1 SCK2 SCK1 Peripheral B SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS2 SPI1_NPCS3 Comments Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A23 A24 A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Application Usage Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function 324-BGA pkg Options(1) can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed can be removed Table 10-6. 1. The user must ensure that removing the designated pins does not have an adverse effect on the intended application. 45 6264C–CAP–24-Mar-09 10.4 10.4.1 Embedded Peripherals Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device 10.4.2 Two-wire Interface • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations 10.4.3 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit 46 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.4.4 Synchronous Serial Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.4.5 AC97 Controller • Compatible with AC97 Component Specification V2.2 • Capable to Interface with a Single Analog Front end • Three independent RX Channels and three independent TX Channels – One RX and one TX channel dedicated to the AC97 Analog Front end control – One RX and one TX channel for data transfers, associated with a PDC – One RX and one TX channel for data transfers with no PDC • Time Slot Assigner allowing to assign up to 12 time slots to a channel • Channels support mono or stereo up to 20 bit sample length – Variable sampling rate AC97 Codec Interface (48KHz and below) 10.4.6 Timer Counter • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 47 6264C–CAP–24-Mar-09 10.4.7 Pulse Width Modulation Controller • 4 channels, one 16-bit counter per channel • Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter outputs • Independent channel programming – Independent Enable Disable Commands – Independent Clock Selection – Independent Period and Duty Cycle, with Double Buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 10.4.8 Multimedia Card Interface • 2 double-channel Multimedia Card Interface, allowing concurrent transfers with 2 cards • Compatibility with MultiMedia Card Specification Version 3.31 • Compatibility with SD Memory Card Specification Version 1.0 • Compatibility with SDIO Specification Version V1.0. • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used • Each MCI has one slot supporting – One MultiMediaCard bus (up to 30 cards) or – One SD Memory Card – One SDIO Card • Support for stream, block and multi-block data read and write 10.4.9 CAN Controller • Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers • Bit rates up to 1Mbit/s. • Object-oriented mailboxes, each with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message – Object Configurable as receive (with overwrite or not) or transmit – Local Tag and Mask Filters up to 29-bit Identifier/Channel – 32 bits access to Data registers for each mailbox data object – Uses a 16-bit time stamp on receive and transmit message – Hardware concatenation of ID unmasked bitfields to speedup family ID processing – 16-bit internal timer for Time Stamping and Network synchronization – Programmable reception buffer length up to 16 mailbox object – Priority Management between transmission mailboxes – Autobaud and listening mode – Low power mode and programmable wake-up on bus activity or by the application – Data, Remote, Error and Overload Frame handling 48 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 10.4.10 USB Host Port • Compliance with OHCI Rev 1.0 Specification • Compliance with USB V2.0 Full-speed and Low-speed Specification • Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps devices • Root hub integrated with two downstream USB ports • Two embedded USB transceivers • Supports power management • Operates as a master on the Matrix • Internal DMA Controller, operating as a Master on Bus Matrix 10.4.11 USB High Speed Device Port • USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver • Embedded 4K-byte dual-port RAM for endpoints • Embedded 6 channels DMA controller • Suspend/Resume logic • Up to 2 or 3 banks for isochronous and bulk endpoints • Seven endpoints: – Endpoint 0: 64 bytes – Endpoint 1 & 2: 1024 bytes, 3 banks mode, HS isochronous capable – Endpoint 3 & 4: 1024 bytes, 2 banks mode, HS isochronous capable – Endpoint 5 & 6: 1024 bytes, 2 banks mode – Endpoint 7: 1024 bytes, 2 banks mode 10.4.12 LCD Controller • Single and Dual scan color and monochrome passive STN LCD panels supported • Single scan active TFT LCD panels supported • 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported • Up to 24-bit single scan TFT interfaces supported • Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays • 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN • 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN • 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048x2048 • 2D-DMA Controller for management of virtual Frame Buffer – Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer • Automatic resynchronization of the frame buffer pointer to prevent flickering 49 6264C–CAP–24-Mar-09 10.4.13 Ethernet 10/100 MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 MBits per second data throughput capability • Full- and half-duplex operations • MII or RMII interface to the physical layer • Register Interface to address, data, status and control registers • Internal DMA Controller, operating as a Master on Bus Matrix • Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Support promiscuous mode where all valid frames are copied to memory • Support physical layer management through MDIO interface control of alarm and update time/calendar data in 10.4.14 Image Sensor Interface • ITU-R BT. 601/656 8-bit mode external interface support • Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image • Programmable frame capture rate • Internal DMA Controller, operating as a Master on Bus Matrix 10.4.15 Analog-to-digital Converter • 8-channel ADC • 10-bit 440K samples/sec. Successive Approximation Register ADC • -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity • Individual enable and disable of each channel • External voltage reference for better accuracy on low voltage inputs • Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 and TIOB0 to TIOB2 triggers • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals 50 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 11. Metal Programmable Block The Metal Programmable Block (MPBlock) is connected to internal resources as the AHB bus or interrupts and to external resources as dedicated I/O pads or UTMI+ core. The MPBlock may be used to implement the Advanced High-speed Bus (AHB) or Advanced Peripheral Bus (APB) custom peripherals. The MPBlock adds approximately 500K or 250K gates of standard cell custom logic to the AT91CAP9S500A/AT91CAP9S250A base design. Figure 11-1 shows the MPBlock and its connections to internal or external resources. Figure 11-1. MPBlock Connectivity ITs DMA AHB MASTERS AHB SLAVES MPBlock Test Wrapper 10x CLOCKS CAN, MACB, OHCI ENABLE MPBLOCK 500K Gates (CAP9500) 250K Gates (CAP9250) DPR 512x36 8x SPR 512x72 CHIP ID JTAG ID UTMI+ PHY Chip Boundary Scan MPIOA[31:0] MPIOB[44:0] 11.1 Internal Connectivity In order to connect the MPBlock custom peripheral to the AT91CAP9S500A/AT91CAP9S250A base design, the following connections are made. 11.1.1 Clocks The MPBlock receives the following clocks: • 32,768 Hz Slow Clock • 8 to 16 MHz Main Oscillator Clock • PLLA Clock • PLLB Clock • 48 MHz USB Clock • 12 MHz USB Clock 51 6264C–CAP–24-Mar-09 • 30 or 60 MHz UTMI+ USB Clock • MCK System Clock • DDRCK Dual Rate System Clock • PCK Processor Clock • 5 Gated Peripheral Clocks (for AHB and/or APB peripherals) corresponding to Peripheral ID 3 to 7 11.1.2 AHB Master Buses The MPBlock may implement up to three AHB masters, each having a dedicated AHB master bus connected to the Bus Matrix. AHB Slave Buses The MPBlock receives four different AHB slave buses coming from the Bus Matrix. Each bus has two or four select signals that can implement up to 12 AHB slaves. Interrupts The MPBlock is connected to 5 dedicated interrupt lines corresponding to Peripheral ID 3 to 9. It is also connected to two other interrupt lines (through OR gate) corresponding to Peripheral ID 1 and 2 11.1.5 DMA Channels The MPBlock is connected to 4 DMA hardware handshaking interfaces, allowing it to implement up to 4 DMA enabled peripherals. Peripheral DMA Channels The MPBlock is not connected to the Peripheral DMA Controller. In order to implement Peripheral DMA Controller (PDC) enabled APB peripherals, a PDC and an AHB-to-APB Bridge must be integrated into the MPBlock using one AHB master and one AHB slave bus. MPBlock Single Port RAMs The MPBlock is connected to eight instances of 512x72 High-Speed Single Port RAMs. The MPBlock has control over all memory connections. 11.1.8 MPBlock Dual Port RAMs The MPBlock is connected to ten instances of 512x36 High-Speed Dual Port RAMs. The MPBlock has control over all memory connections. 11.1.9 Optional Peripherals Enable The MPBlock drives the enable of the optional peripherals, and so can enable or disable any of the optional peripherals. 11.1.3 11.1.4 11.1.6 11.1.7 52 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 11.2 External Connectivity The MPBlock is connected to the following external resources. 11.2.1 Dedicated I/O Lines The MPBlock is directly connected to 77 (32 MPIOA and 45 MPIOB lines) dedicated I/O Pads with the following features: • Supply/Drive control pin (needed for high-speed or low voltage interfaces) • Pull-up control pin • Supported logic levels include: – LVCMOS33 at 100 MHz maximum frequency – LVCMOS25 at 50 MHz maximum frequency – LVCMOS18 at 100 MHz maximum frequency 11.2.2 UTMI+ Transceiver The MPBlock may be connected to the UTMI+ transceiver. As only one UTMI+ transceiver is available, the USB High-speed Device and the MPBlock do not have access to the UTMI+ at the same time. However, a dual role Master-Slave USB High-Speed may be implemented by using the USB High-speed Device and integrating a High-speed Host in the MPBlock as the switching between both is generated inside the MPBlock. 11.3 Prototyping Solution In order to prototype the final custom design, a Prototyping Platform version of the AT91CAP9S500A/AT91CAP9S250A design has been created. The platform maps APB and AHB masters or slaves into the FPGA located outside the chip with the following features and restrictions: • AT91CAP9S500A/AT91CAP9S250A to FPGA interface is provided to prototype AHB masters and slave into the external FPGA exactly as if it were in MPBlock. • Prototyped AHB Masters – Prototyped AHB Masters have access to AT91CAP9S500A/AT91CAP9S250A slave resources. – Prototyped AHB Masters have access to MPBlock (FPGA) slave resources. • Prototyped AHB Slaves – Prototyped AHB Slaves may be accessed from AT91CAP9S500A/AT91CAP9S250A master resources. – Prototyped AHB Slaves may be accessed from MPBlock (FPGA) resources. • Prototyped APB Slaves – APB bus must be created locally in the FPGA by implementing AHB to APB bridge. Peripheral DMA controller may also be necessary to implement locally in the FPGA in order to prototype PDC enabled APB peripherals. Figure 11-2 shows a typical prototyping solution. 53 6264C–CAP–24-Mar-09 Figure 11-2. Typical Prototyping Solution CAP9500 CAP9250 MASTERS ARM926EJ-S EBI Bus Matrix 4-channel DMA Metal Programmable Block 500K Gates (CAP9500) 250K Gates (CAP9250) FPGA Interface MPIOA[31:0] MPIOB[44:0] FPGA CAP9500/CAP9250 FPGA Interface Local AHB Matrix AHB MASTER DPR AHB 2 APB BRIDGE PDC RAM AHB MASTER AHB SLAVE DPR APB DPR APB SLAVE APB SLAVE MPBlock Emulation Area 54 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 12. ARM926EJ-S Processor Overview 12.1 Overview The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multitasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Javapowered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S™ integer core • a Memory Management Unit (MMU) • separate instruction and data AMBA AHB bus interfaces • separate instruction and data TCM interfaces 55 6264C–CAP–24-Mar-09 12.2 Block Diagram Figure 12-1. ARM926EJ-S Internal Functional Block Diagram External Coprocessors ETM9 CP15 System Configuration Coprocessor External Coprocessor Interface Trace Port Interface Write Data ARM9EJ-S Processor Core Instruction Fetches Read Data Data Address MMU Instruction Address DTCM Interface Data TLB Instruction TLB ITCM Interface Data TCM Instruction TCM Data Address Data Cache AHB Interface and Write Buffer Instruction Address Instruction Cache AMBA AHB 56 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 12.3 12.3.1 ARM9EJ-S Processor ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: • ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 12.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC • ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 12.3.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 12.3.4 Memory Access The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data. 12.3.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. 57 6264C–CAP–24-Mar-09 Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 12.3.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: • User mode is the usual ARM program execution state. It is used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling • Supervisor mode is a protected mode for the operating system • Abort mode is entered after a data or instruction prefetch abort • System mode is a privileged user mode for the operating system • Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 12.3.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers. • 31 general-purpose 32-bit registers • 6 32-bit status registers Table 12-1 shows all the registers in all modes. Table 12-1. User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 ARM9TDMI Modes and Registers Layout Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ 58 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Table 12-1. User and System Mode R12 R13 R14 PC ARM9TDMI Modes and Registers Layout Supervisor Mode R12 R13_SVC R14_SVC PC Abort Mode R12 R13_ABORT R14_ABORT PC Undefined Mode R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R12_FIQ R13_FIQ R14_FIQ PC CPSR CPSR SPSR_SVC CPSR SPSR_ABOR T CPSR SPSR_UNDE F CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines: • constraints on the use of registers • stack conventions • argument passing and result return For more details, refer to ARM Software Development Kit. The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC • CPSR 59 6264C–CAP–24-Mar-09 There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, revision r1p2 page 2-12). 12.3.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode Figure 12-2. Status Register Format 31 30 29 28 27 24 765 0 NZCVQ J Reserved I FT Mode Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than Mode bits Thumb state bit FIQ disable IRQ disable Figure 12-2 shows the status register format, where: • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. • The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where: – J = 0: The processor is in ARM or Thumb state, depending on the T bit – J = 1: The processor is in Jazelle state. • Mode: five bits to encode the current processor mode 12.3.7.2 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi- leged mode. The types of exceptions are: • Fast interrupt (FIQ) • Normal interrupt (IRQ) • Data and Prefetched aborts (Abort) • Undefined instruction (Undefined) • Software interrupt and Reset (Supervisor) 60 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order: • Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. Note that there is one exception in the priority scheme: when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: – ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). – THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the 61 6264C–CAP–24-Mar-09 pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 12.3.8 ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions • Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the ARM Technical Reference Manual. Table 12-2 gives the ARM instruction mnemonic list. Table 12-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Mnemonic MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR Operation Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word 62 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Table 12-2. Mnemonic LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP ARM Instruction Mnemonic List (Continued) Operation Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Coprocessor Data Processing Mnemonic STRH STRB STRBT STRT STM SWPB MRC STC Operation Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor 12.3.9 New ARM Instruction Set . Table 12-3. Mnemonic BXJ BLX (1) SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB New ARM Instruction Mnemonic List Operation Branch and exchange to Java Branch, Link and exchange Signed Multiply Accumulate 16 * 16 bit Signed Multiply Accumulate Long Signed Multiply Accumulate 32 * 16 bit Signed Multiply 16 * 16 bit Signed Multiply 32 * 16 bit Saturated Add Saturated Add with Double Saturated subtract Saturated Subtract with double Mnemonic MRRC MCR2 MCRR CDP2 BKPT PLD STRD STC2 LDRD LDC2 CLZ Operation Move double from coprocessor Alternative move of ARM reg to coprocessor Move double to coprocessor Alternative Coprocessor Data Processing Breakpoint Soft Preload, Memory prepare to load from address Store Double Alternative Store from Coprocessor Load Double Alternative Load to Coprocessor Count Leading Zeroes Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 12.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions 63 6264C–CAP–24-Mar-09 • Load and Store multiple instructions • Exception-generating instruction For further details, see the ARM Technical Reference Manual. Table 12-4 gives the Thumb instruction mnemonic list. Table 12-4. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch Mnemonic MVN ADC SBC CMN NEG BIC ORR LSR ROR BLX BL SWI STR STRH STRB LDRSB STMIA POP BKPT Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right Branch, Link, and Exchange Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Breakpoint 64 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 12.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S • Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 12-5. Table 12-5. Register 0 0 0 1 2 3 4 5 5 6 7 8 9 9 10 11 12 13 13 14 15 Notes: CP15 Registers Name ID Code (1) (1) Access Read/Unpredictable Read/Unpredictable Read/Unpredictable Read-write Read-write Read-write None (1) (1) Cache type TCM status(1) Control Translation Table Base Domain Access Control Reserved Data fault Status Read-write Read-write Read-write Read-write Unpredictable/Write Instruction fault status Fault Address Cache Operations TLB operations cache lockdown TCM region TLB lockdown Reserved Reserved FCSE PID (1) (2) Read-write Read-write Read-write None None Read-write Read-write None Read-write Context ID(1) Reserved Test configuration 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. 65 6264C–CAP–24-Mar-09 12.4.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 27 26 25 24 cond 23 22 21 20 1 19 1 18 1 17 0 16 opcode_1 15 14 13 L 12 11 10 CRn 9 8 Rd 7 6 5 4 1 3 1 2 1 1 1 0 opcode_2 1 CRm • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. • opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. • Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM. 66 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 12.5 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS, WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 7 shows the different attributes of each page in the physical memory. Table 12-6. Mapping Details Mapping Size 1M byte 64K bytes 4K bytes 1K byte Access Permission By Section 4 separated subpages 4 separated subpages Tiny Page Subpage Size 16K bytes 1K byte - Mapping Name Section Large Page Small Page Tiny Page The MMU consists of: • Access control logic • Translation Look-aside Buffer (TLB) • Translation table walk hardware 12.5.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 12.5.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modi- 67 6264C–CAP–24-Mar-09 fied Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 12.5.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Pagemapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. 12.5.4 MMU Faults The MMU generates an abort on the following types of faults: • Alignment faults (for data accesses only) • Translation faults • Domain faults • Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual. 68 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 12.6 Caches and Write Buffer The ARM926EJ-S contains a 16KB Instruction Cache (ICache), a 16KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 12.6.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 12.6.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause line fills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the 69 6264C–CAP–24-Mar-09 12.6.2.1 cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 12.6.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and writeback region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. 12.6.2.3 Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 12.6.2.4 Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 70 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 12.7 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: • It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. • Each AHB layer becomes simple because it only has one master, so no arbitration or masterto-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. • The arbitration becomes effective when more than one master wants to access the same slave simultaneously. 12.7.1 Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 12-7. HBurst[2:0] Supported Transfers Description Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT, or WB that has missed in DCache) SINGLE Single transfer • data read (NCNB or NCB) • NC instruction fetch (prefetched and non-prefetched) • page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. Cache linefill INCR4 INCR8 WRAP8 Four-word incrementing burst Eight-word incrementing burst Eight-word wrapping burst 12.7.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time. Address Alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. 12.7.3 71 6264C–CAP–24-Mar-09 72 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 13. Debug and Test 13.1 Description The AT91CAP9 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 73 6264C–CAP–24-Mar-09 13.2 Block Diagram Figure 13-1. Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP JTAGSEL TDO Boundary Port RTCK Reset and Test POR TST DTXD PIO DBGU ARM9EJ-S ICE-RT DRXD ARM926EJ-S PDC TAP: Test Access Port 74 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 13.3 13.3.1 Application Examples Debug Environment Figure 13-2 on page 75 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 13-2. Application Debug and Trace Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector AT91CAP9 RS232 Connector Terminal AT91CAP9-based Application 13.3.2 Test Environment Figure 13-3 on page 75 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 13-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91CAP9 Chip 1 AT91CAP9-based Application Board In Test 75 6264C–CAP–24-Mar-09 13.4 Debug and Test Pin Description Table 13-1. Pin Name Debug and Test Pin List Function Reset/Test Type Active Level NRST TST Microcontroller Reset Test Mode Select ICE and JTAG Input/Output Input Low High TCK TDI TDO TMS RTCK NTRST JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock Test Reset JTAG Selection Debug Unit Input Input Output Input Output Input Input Low DRXD DTXD Debug Receive Data Debug Transmit Data Input Output 13.5 13.5.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 13.5.2 Embedded In-circuit Emulator The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a storemultiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the EmbeddedICE-RT™. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document: ARM9EJ-S Technical Reference Manual (DDI 0222A). 76 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 13.5.3 JTAG Signal Description • TMS is the Test Mode Select input which controls the transitions of the test interface state machine. • TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). • TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. • NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. • TCK is the Test Clock input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. • RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and ignore the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 13.5.4 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91CAP9 Debug Unit Chip ID value is 0x039A 03A0 on 32-bit width. For further details on the Debug Unit, see the section “Debug Unit”. 77 6264C–CAP–24-Mar-09 13.5.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 13.5.6 ID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B1_B03F. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B1B • VERSION[31:28]: Product Version Number Set to 0x0. 78 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 14. Boot Program 14.1 Description The Boot Program is contained in the embedded ROM. It is also called “Rom Code” or “First Level Bootloader”. At power on, if BMS is detected at 1, the boot memory is the embedded ROM and the Boot Program is executed. (see Section 8.1.2 “Boot Strategies”). The Boot Program consists of several steps. First, it performs device initialization. Then it attempts to boot from external non-volatile memories (NVM). And finally, if no valid program has been found in NVM, it executes a monitor called SAM-BA® monitor. 14.2 Flow Diagram The Boot Program implements the algorithm in Figure 14-1. Figure 14-1. Boot Program Algorithm Flow Diagram Device Setup Valid boot code found in one NVM Yes Copy and run it in internal SRAM No SAM-BA Monitor 79 6264C–CAP–24-Mar-09 14.3 14.3.1 Device Initialization Clock at Startup At boot startup, the processor clock (PCK) and the master clock (MCK) is the slow clock. The slow clock can be an external 32 kHz crystal oscillator or the internal RC oscillator. By default the slow clock is the internal RC oscillator. If a battery supplies the backup power and if the external 32 kHz crystal oscillator was previously started up and selected, the slow clock at boot is the external 32 kHz crystal oscillator (see Section 29.2 “Slow Clock Crystal Oscillator”). Initialization Sequence Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode. 2. Main Oscillator Detection: (external crystal or external clock on XIN). The Main Oscillator is disabled at startup (MOSCEN=1). First it is bypassed (OSCBYPASS set at 1). Then polling is done on the MAINRDY bit. As soon as this bit is raised, the Main Clock Frequency field is analyzed (MAINF). If the value exceeds 16, an external clock connected on XIN is detected. If not, an external crystal oscillator connected between XIN and XOUT (whose frequency is unknown at this moment) is detected. 3. Main Oscillator Enabling: If an external clock is connected on XIN, the Main Oscillator does not need to be started. Otherwise, If an external clock is not connected on XIN, the OSCBYPASS bit is cleared. The Main Oscillator is enabled with the maximum startup time and a polling is done on the MOSC bit to wait for stabilization. 4. Main Oscillator Selection: The Master Clock source is switched from Slow Clock to the Main Oscillator without prescaler. Polling is done to wait for enabling. PCK and MCK are now the Main Oscillator clock. 5. C variable initialization: Non zero-initialized data are initialized in RAM (copy from ROM to RAM). Zero-initialized data are set to 0 in RAM. 6. PLLA initialization: PLLA is configured to allow communication on the USB link for the SAM-BA monitor. Its configuration depends on the Main Oscillator source (external clock or crystal) and on its frequency. 14.3.2 80 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 14.4 NVM Boot 14.4.1 NVM Bootloader Program Description Figure 14-2. NVM Bootloader Program Start Initialize NVM Initialization OK ? No Restore the reset values for the peripherals and Jump to next boot solution Yes Valid code detection in NVM NVM contains valid code No Yes Copy the valid code from external NVM to internal SRAM. Restore the reset values for the peripherals. Perform the REMAP and set the PC to 0 to jump to the downloaded application End 81 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 14-3. Remap Action after Download Completion 0x0000_0000 Internal ROM 0x0010_0000 Internal SRAM 0x0040_0000 Internal ROM Internal ROM Internal SRAM 0x0040_0000 REMAP Internal SRAM 0x0010_0000 0x0000_0000 The NVM bootloader program initializes the NVM. It initializes the required PIO. It sets the right peripheral, depending on the NVM and tries to access the memory. If the initialization fails, it restores the reset values for the PIO and peripherals, then the next NVM bootloader program is executed. If the initialization is successful, the NVM bootloader program reads the beginning of the NVM and determines if the NVM contains a valid code. If the NVM does not contain a valid code, the NVM bootloader program restores the reset value for the peripherals and then the next NVM bootloader program is executed. If a valid code is found, this code is loaded from NVM into internal SRAM and executed by branching at address 0x0000_0000 after remap. This code may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. 14.4.2 Valid Code Detection There are two kinds of valid code detection. Depending on the NVM bootloader, one or both of them are used. ARM Exception Vectors Check The NVM bootloader program reads and analyzes the first 28 bytes corresponding to the first seven ARM exception vectors. Except for the sixth vector, these bytes must implement the ARM instructions for either branch or load the PC with PC relative addressing. Figure 14-4. LDR Opcode 31 1 1 1 28 27 0 0 1 I 24 23 P U 1 W 20 19 0 Rn 16 15 Rd 12 11 Offset 0 14.4.2.1 82 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 14-5. B Opcode 31 1 1 1 28 27 0 1 0 1 24 23 0 Offset (24 bits) 0 Unconditional instruction: 0xE for bits 31 to 28 Load the PC with PC relative addressing instruction: – Rn = Rd = PC = 0xF – I==0 (12-bit immediate value) – P==1 (pre-indexed) – U offset added (U==1) or subtracted (U==0) – W==1 The sixth vector, at offset 0x14, contains the size of the image to download. This vector must be replaced by the user’s own vector. This information is described below. Figure 14-6. Structure of the ARM Vector 6 31 Size of the code to download in bytes 0 The value has to be less than 28 Kbytes. 28 Kbytes is the maximum size for a valid code. This size is the internal SRAM size minus the stack size used by the ROM Code at the end of the internal SRAM. Example: An example of valid vectors follows: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 ’. • Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal followed by ‘>’ • Send a file (S): Send a file to a specified address – Address: Address in hexadecimal – Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. • Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal – NbOfBytes: Number of bytes in hexadecimal to receive – Output: ‘>’ • Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the Boot Program version – Output: the boot program version, followed by: ‘>’ 89 6264C–CAP–24-Mar-09 14.5.2 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. Supported External Crystal/External Clocks The supported frequencies by the SAM-BA monitor to allow the DBGU communication are: • for external crystal: 12 MHz • for external clock: 1.4 MHz, 2 MHz, 2.8 MHz, 4 MHz, 5.5 MHz, 7.5 MHz, 10 MHz, 14 MHz, 20 MHz, 28 MHz, 40 MHz, 50 MHz. 14.5.2.1 14.5.2.2 Xmodem Protocol The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: – = 01 hex – = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – = 1’s complement of the blk#. – = 2 bytes CRC16 Figure 14-9 shows a transmission using this protocol. Figure 14-9. Xmodem Transfer Example Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device 90 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 14.5.3 14.5.3.1 USB Device Port Supported External Crystal/External Clocks The supported frequencies by the SAM-BA monitor to allow the USB communication are: • for external crystal: 12 MHz • for external clock: 5 MHz, 12 MHz, 27 MHz 14.5.3.2 USB Class The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, from Windows 98SE to Windows XP. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. 14.5.3.3 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration, sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 14-5. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION GET_STATUS SET_FEATURE CLEAR_FEATURE Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature. The device also handles some class requests defined in the CDC class. Table 14-6. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 91 6264C–CAP–24-Mar-09 14.5.3.4 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAMBA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 92 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 15. Reset Controller (RSTC) 15.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 15.2 Block Diagram Figure 15-1. Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR Startup Counter rstc_irq Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager exter_nreset periph_nreset backup_neset WDRPROC wd_fault SLCK 15.3 15.3.1 Functional Description Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • backup_nreset: Affects all the peripherals powered by VDDBU. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 93 6264C–CAP–24-Mar-09 The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 15.3.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 15-2 shows the block diagram of the NRST Manager. Figure 15-2. NRST Manager RSTC_MR RSTC_SR URSTIEN rstc_irq RSTC_MR URSTS NRSTL Other interrupt sources user_reset URSTEN NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset 15.3.2.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 15.3.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. 94 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 15.3.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 15-3. BMS Sampling SLCK Core Supply POR output XXX BMS sampling delay = 3 cycles BMS Signal H or L proc_nreset 15.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 15.3.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 2 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 15-4 shows how the General Reset affects the reset signals. 95 6264C–CAP–24-Mar-09 Figure 15-4. General Reset State SLCK MCK Backup Supply POR output Any Freq. Startup Time Main Supply POR output backup_nreset Processor Startup = 2 cycles proc_nreset RSTTYP periph_nreset XXX 0x0 = General Reset XXX NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles BMS Sampling 96 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 15.3.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 2 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR. Figure 15-5. Wake-up State SLCK MCK Main Supply POR output Any Freq. backup_nreset Resynch. 2 cycles Processor Startup = 2 cycles proc_nreset RSTTYP XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 97 6264C–CAP–24-Mar-09 15.3.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 2-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 15-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 2 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset NRST (nrst_out) >= EXTERNAL RESET LENGTH 98 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 15.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously.) • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 2 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. 99 6264C–CAP–24-Mar-09 Figure 15-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. Processor Startup 1 cycle = 2 cycles proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) Any XXX 0x3 = Software Reset SRCMP in RSTC_SR 15.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 2 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. 100 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 15-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 15.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup Reset • Wake-up Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 101 6264C–CAP–24-Mar-09 15.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. • NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. • URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 15-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 15-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 102 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 15.4 Reset Controller (RSTC) User Interface Register Mapping Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read-write Reset 0x0000_0001 0x0000_0000 0x0000_0000 Back-up Reset Table 15-1. Offset 0x00 0x04 0x08 Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 103 6264C–CAP–24-Mar-09 15.4.1 Name: Address: Access: 31 Reset Controller Control Register RSTC_CR 0xFFFFFD00 Write-only 30 29 28 KEY 27 26 25 24 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 – 19 – 11 – 3 EXTRST 18 – 10 – 2 PERRST 17 – 9 16 – 8 – 0 PROCRST 1 – • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 104 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 15.4.2 Name: Address: Access: 31 – 23 – 15 – 7 – Reset Controller Status Register RSTC_SR 0xFFFFFD04 Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 25 – 17 SRCMP 9 RSTTYP 1 – 24 – 16 NRSTL 8 2 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Reset Type General Reset Wake Up Reset Watchdog Reset Software Reset User Reset Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 105 6264C–CAP–24-Mar-09 15.4.3 Name: Address: Access: 31 Reset Controller Mode Register RSTC_MR 0xFFFFFD08 Read-write 30 29 28 KEY 27 26 25 24 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 20 – 12 – 4 URSTIEN 19 – 11 18 – 10 ERSTL 17 – 9 16 8 3 – 2 – 1 – 0 URSTEN • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 106 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 16. Real-time Timer (RTT) 16.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 16.2 Block Diagram Figure 16-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm 16.3 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 107 6264C–CAP–24-Mar-09 The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). Figure 16-2. RTT Counting APB cycle APB cycle SCLK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 108 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 16.4 Real-time Timer (RTT) User Interface Register Mapping Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read-write Read-write Read-only Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 Table 16-1. Offset 0x00 0x04 0x08 0x0C 109 6264C–CAP–24-Mar-09 16.4.1 Name: Address: Real-time Timer Mode Register RTT_MR 0xFFFFFD20 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RTPRES 7 6 5 4 RTPRES 3 2 1 0 27 – 19 – 11 26 – 18 RTTRST 10 25 – 17 RTTINCIEN 9 24 – 16 ALMIEN 8 Access Type: 31 – 23 – 15 • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216. RTPRES …0: The prescaler period is equal to RTPRES. • ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 110 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 16.4.2 Name: Address: Access: 31 Real-time Timer Alarm Register RTT_AR 0xFFFFFD24 Read/Write 30 29 28 ALMV 27 26 25 24 23 22 21 20 ALMV 19 18 17 16 15 14 13 12 ALMV 11 10 9 8 7 6 5 4 ALMV 3 2 1 0 • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 16.4.3 Name: Address: Access: 31 Real-time Timer Value Register RTT_VR 0xFFFFFD28 Read-only 30 29 28 CRTV 27 26 25 24 23 22 21 20 CRTV 19 18 17 16 15 14 13 12 CRTV 11 10 9 8 7 6 5 4 CRTV 3 2 1 0 • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 111 6264C–CAP–24-Mar-09 16.4.4 Name: Address: Access: 31 – 23 – 15 – 7 – Real-time Timer Status Register RTT_SR 0xFFFFFD2C Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 RTTINC 24 – 16 – 8 – 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 112 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 17. Periodic Interval Timer (PIT) 17.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 17.2 Block Diagram Figure 17-1. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset pit_irq 0 0 1 0 1 12-bit Adder read PIT_PIVR MCK 20-bit Counter Prescaler MCK/16 CPIV PIT_PIVR PICNT CPIV PIT_PIIR PICNT 113 6264C–CAP–24-Mar-09 17.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 17-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. 114 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 17-2. Enabling/Disabling PIT with PITEN APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle CPIV PICNT PITS (PIT_SR) APB Interface 0 1 0 PIV - 1 PIV 1 0 0 1 read PIT_PIVR 115 6264C–CAP–24-Mar-09 17.4 Periodic Interval Timer (PIT) User Interface Register Mapping Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read-write Read-only Read-only Read-only Reset 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 Table 17-1. Offset 0x00 0x04 0x08 0x0C 116 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 17.4.1 Name: Address: Access: 31 – 23 – 15 Periodic Interval Timer Mode Register PIT_MR 0xFFFFFD30 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 PIV 7 6 5 4 PIV 3 2 1 0 27 – 19 26 – 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16 • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 117 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 17.4.2 Name: Address: Access: 31 – 23 – 15 – 7 – Periodic Interval Timer Status Register PIT_SR 0xFFFFFD34 Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 118 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 17.4.3 Name: Address: Access: 31 Periodic Interval Timer Value Register PIT_PIVR 0xFFFFFD38 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 119 6264C–CAP–24-Mar-09 17.4.4 Name: Address: Access: 31 Periodic Interval Timer Image Register PIT_PIIR 0xFFFFFD3C Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 120 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 18. Watchdog Timer (WDT) 18.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 18.2 Block Diagram Figure 18-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WDRSTT reload 1 0 WDV 12-bit Down Counter WDT_MR WDD Current Value reload 1/128 SLCK 1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock 32.4.2 32.4.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 32.4.2.2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. 456 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 32-4. Start Bit Detection Sampling Clock DRXD True Start Detection Baud Rate Clock D0 Figure 32-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 32.4.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 32-6. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 32.4.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 32-7. Receiver Overrun DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 457 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.4.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 32-8. Parity Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 32.4.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 32-9. Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 RSTSTA 32.4.3 32.4.3.1 Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. 458 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.4.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 32-10. Character Transmission Example: Parity enabled Baud Rate Clock DTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 32.4.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 32-11. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register Data 0 Data 1 DTXD S Data 0 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 459 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.4.4 Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR. 32.4.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. 460 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 32-12. Test Modes Automatic Echo Receiver RXD Transmitter Disabled TXD Local Loopback Receiver Disabled RXD VDD Transmitter Disabled TXD Remote Loopback Receiver VDD Disabled RXD Transmitter Disabled TXD 32.4.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 461 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: • EXT - shows the use of the extension identifier register • NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size • ARCH - identifies the set of embedded peripherals • SRAMSIZ - indicates the size of the embedded SRAM • EPROC - indicates the embedded ARM processor • VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 32.4.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible. 462 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5 Debug Unit (DBGU) User Interface Register Mapping Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Force NTRST Register PDC Area Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR – DBGU_CIDR DBGU_EXID DBGU_FNR – Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write – Read-only Read-only Read-write – Reset – 0x0 – – 0x0 – 0x0 – 0x0 – – – 0x0 – Table 32-3. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 - 0x003C 0x0040 0x0044 0x0048 0x0100 - 0x0124 463 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.1 Name: Address: Access: 31 Debug Unit Control Register DBGU_CR 0xFFFFEE00 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 0 – 7 TXDIS – 6 TXEN – 5 RXDIS – 4 RXEN – 3 RSTTX – 2 RSTRX – 1 – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. • RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. • RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. • RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. • TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. • TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. • RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 464 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.2 Name: Address: Access: 31 Debug Unit Mode Register DBGU_MR 0xFFFFEE04 Read-write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CHMODE 7 – 14 – 13 – 12 – 11 – 10 PAR – 9 – 8 – 6 5 – 4 3 – 1 0 2 – – – – – – – – • PAR: Parity Type PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback 465 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.3 Name: Address: Access: 31 COMMRX 23 Debug Unit Interrupt Enable Register DBGU_IER 0xFFFFEE08 Write-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Enable RXRDY Interrupt • TXRDY: Enable TXRDY Interrupt • ENDRX: Enable End of Receive Transfer Interrupt • ENDTX: Enable End of Transmit Interrupt • OVRE: Enable Overrun Error Interrupt • FRAME: Enable Framing Error Interrupt • PARE: Enable Parity Error Interrupt • TXEMPTY: Enable TXEMPTY Interrupt • TXBUFE: Enable Buffer Empty Interrupt • RXBUFF: Enable Buffer Full Interrupt • COMMTX: Enable COMMTX (from ARM) Interrupt • COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 466 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.4 Name: Address: Access: 31 COMMRX 23 Debug Unit Interrupt Disable Register DBGU_IDR 0xFFFFEE0C Write-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Disable RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Disable End of Receive Transfer Interrupt • ENDTX: Disable End of Transmit Interrupt • OVRE: Disable Overrun Error Interrupt • FRAME: Disable Framing Error Interrupt • PARE: Disable Parity Error Interrupt • TXEMPTY: Disable TXEMPTY Interrupt • TXBUFE: Disable Buffer Empty Interrupt • RXBUFF: Disable Buffer Full Interrupt • COMMTX: Disable COMMTX (from ARM) Interrupt • COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 467 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.5 Name: Address: Access: 31 COMMRX 23 Debug Unit Interrupt Mask Register DBGU_IMR 0xFFFFEE10 Read-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Mask RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Mask End of Receive Transfer Interrupt • ENDTX: Mask End of Transmit Interrupt • OVRE: Mask Overrun Error Interrupt • FRAME: Mask Framing Error Interrupt • PARE: Mask Parity Error Interrupt • TXEMPTY: Mask TXEMPTY Interrupt • TXBUFE: Mask TXBUFE Interrupt • RXBUFF: Mask RXBUFF Interrupt • COMMTX: Mask COMMTX Interrupt • COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 468 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.6 Name: Address: Access: 31 COMMRX 23 Debug Unit Status Register DBGU_SR 0xFFFFEE14 Read-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. • TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. • ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active. • ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. • OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. • PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. 469 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active. 470 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.7 Name: Address: Access: 31 Debug Unit Receiver Holding Register DBGU_RHR 0xFFFFEE18 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 RXCHR – 3 – 2 – 1 – 0 • RXCHR: Received Character Last received character if RXRDY is set. 32.5.8 Name: Address: Access: 31 Debug Unit Transmit Holding Register DBGU_THR 0xFFFFEE1C Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 TXCHR – 3 – 2 – 1 – 0 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 471 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.9 Name: Address: Access: 31 Debug Unit Baud Rate Generator Register DBGU_BRGR 0xFFFFEE20 Read-write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 CD – 11 – 10 – 9 – 8 7 6 5 4 CD 3 2 1 0 • CD: Clock Divisor CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16) 472 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.10 Name: Address: Access: 31 EXT 23 22 ARCH 15 14 NVPSIZ2 7 6 EPROC 5 4 3 2 VERSION 13 12 11 10 NVPSIZ 1 0 Debug Unit Chip ID Register DBGU_CIDR 0xFFFFEE40 Read-only 30 29 NVPTYP 21 20 19 18 SRAMSIZ 9 8 28 27 26 ARCH 17 16 25 24 • VERSION: Version of the Device Values depend upon the version of the device. • EPROC: Embedded Processor EPROC 0 0 1 1 0 1 0 0 1 0 0 1 Processor ARM946ES ARM7TDMI ARM920T ARM926EJS • NVPSIZ: Nonvolatile Program Memory Size NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved 473 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved • SRAMSIZ: Internal SRAM Size SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes 6K bytes 112K bytes 4K bytes 80K bytes 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 128K bytes 256K bytes 96K bytes 512K bytes 474 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • ARCH: Architecture Identifier ARCH Hex 0x19 0x29 0x34 0x37 0x39 0x3B 0x40 0x42 0x55 0x60 0x61 0x63 0x70 0x71 0x72 0x73 0x75 0x92 0xF0 Bin 0001 1001 0010 1001 0011 0100 0011 0111 0011 1001 0011 1011 0100 0000 0100 0010 0101 0101 0110 0000 0110 0001 0110 0011 0111 0000 0111 0001 0111 0010 0111 0011 0111 0101 1001 0010 1111 0000 Architecture AT91SAM9xx Series AT91SAM9XExx Series AT91x34 Series CAP7 Series CAP9 Series CAP11 Series AT91x40 Series AT91x42 Series AT91x55 Series AT91SAM7Axx Series AT91SAM7AQxx Series AT91x63 Series AT91SAM7Sxx Series AT91SAM7XCxx Series AT91SAM7SExx Series AT91SAM7Lxx Series AT91SAM7Xxx Series AT91x92 Series AT75Cxx Series • NVPTYP: Nonvolatile Program Memory Type NVPTYP 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 Memory ROM ROMless or on-chip Flash SRAM emulating ROM Embedded Flash Memory ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists. 475 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 32.5.11 Name: Address: Access: 31 Debug Unit Chip ID Extension Register DBGU_EXID 0xFFFFEE44 Read-only 30 29 28 EXID 27 26 25 24 23 22 21 20 EXID 19 18 17 16 15 14 13 12 EXID 11 10 9 8 7 6 5 4 EXID 3 2 1 0 • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 32.5.12 Name: Address: Access: 31 Debug Unit Force NTRST Register DBGU_FNR 0xFFFFEE48 Read-write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FNTRST – – – – – – – • FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low. 476 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33. Parallel Input/Output Controller (PIO) 33.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: • An input change interrupt enabling level change detection on any I/O line. • A glitch filter providing rejection of pulses lower than one-half of clock cycle. • Multi-drive capability similar to an open drain I/O line. • Control of the pull-up of the I/O line. • Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 477 6264C–CAP–24-Mar-09 33.2 Block Diagram Figure 33-1. Block Diagram PIO Controller AIC PIO Interrupt PMC PIO Clock Data, Enable Embedded Peripheral Up to 32 peripheral IOs PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 33-2. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver General Purpose I/Os External Devices 478 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.3 33.3.1 Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. 33.3.2 33.3.3 33.3.4 Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled. 479 6264C–CAP–24-Mar-09 33.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 33-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 33-3. I/O Line Control Logic PIO_OER[0] PIO_OSR[0] PIO_ODR[0] 1 PIO_PUER[0] PIO_PUSR[0] PIO_PUDR[0] Peripheral A Output Enable Peripheral B Output Enable PIO_ASR[0] PIO_ABSR[0] PIO_BSR[0] Peripheral A Output Peripheral B Output 0 0 0 1 PIO_PER[0] PIO_PSR[0] PIO_PDR[0] 0 0 1 PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 0 1 1 PIO_SODR[0] PIO_ODSR[0] PIO_CODR[0] Pad 1 Peripheral A Input Peripheral B Input PIO_PDSR[0] 0 Edge Detector Glitch Filter PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] 1 PIO_ISR[0] (Up to 32 possible inputs) PIO Interrupt PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] 480 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pullup Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. 33.4.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. 33.4.3 Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. 33.4.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). 481 6264C–CAP–24-Mar-09 The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 33.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 33.4.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 33.4.7 Output Line Timings Figure 33-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 33-4 also shows when the feedback in PIO_PDSR is available. 482 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 33-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0 APB Access APB Access PIO_ODSR 2 cycles PIO_PDSR 2 cycles 33.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 33.4.9 Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 33-5. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled. 483 6264C–CAP–24-Mar-09 Figure 33-5. Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 up to 2.5 cycles 1 cycle up to 2 cycles 1 cycle 1 cycle 1 cycle 33.4.10 Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. Figure 33-6. Input Change Interrupt Timings MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 484 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.5 I/O Lines Programming Example The programing example as shown in Table 33-1 below is used to define the following configuration. • 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor • Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor • Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts • Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter • I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor • I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor • I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 33-1. Programming Example Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0 485 6264C–CAP–24-Mar-09 33.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 33-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C Register Mapping Register PIO Enable Register PIO Disable Register PIO Status Register Reserved Output Enable Register Output Disable Register Output Status Register Reserved Glitch Input Filter Enable Register Glitch Input Filter Disable Register Glitch Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register Pin Data Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register(4) Multi-driver Enable Register Multi-driver Disable Register Multi-driver Status Register Reserved Pull-up Disable Register Pull-up Enable Register Pad Pull-up Status Register Reserved PIO_PUDR PIO_PUER PIO_PUSR Write-only Write-only Read-only – – 0x00000000 PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR Write-only Write-only Read-only or(2) Read/Write Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only – (3) Name PIO_PER PIO_PDR PIO_PSR Access Write-only Write-only Read-only Reset – – (1) PIO_OER PIO_ODR PIO_OSR Write-only Write-only Read-only – – 0x0000 0000 PIO_IFER PIO_IFDR PIO_IFSR Write-only Write-only Read-only – – 0x0000 0000 – – – 0x00000000 0x00000000 – – 0x00000000 486 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Table 33-2. Offset 0x0070 0x0074 0x0078 0x007C to 0x009C 0x00A0 0x00A4 0x00A8 0x00AC Notes: Register Mapping (Continued) Register Peripheral A Select Register Peripheral B Select Register AB Status Register Reserved Output Write Enable Output Write Disable Output Write Status Register Reserved PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only – – 0x00000000 (5) (5) (5) Name PIO_ASR PIO_BSR PIO_ABSR Access Write-only Write-only Read-only Reset – – 0x00000000 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register. 487 6264C–CAP–24-Mar-09 33.6.1 Name: PIO Controller PIO Enable Register PIO_PER Addresses: 0xFFFFF200 (PIOA), 0xFFFFF400 (PIOB), 0xFFFFF600 (PIOC), 0xFFFFF800 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 33.6.2 Name: PIO Controller PIO Disable Register PIO_PDR Addresses: 0xFFFFF204 (PIOA), 0xFFFFF404 (PIOB), 0xFFFFF604 (PIOC), 0xFFFFF804 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 488 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.6.3 Name: PIO Controller PIO Status Register PIO_PSR Addresses: 0xFFFFF208 (PIOA), 0xFFFFF408 (PIOB), 0xFFFFF608 (PIOC), 0xFFFFF808 (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive). 33.6.4 Name: PIO Controller Output Enable Register PIO_OER Addresses: 0xFFFFF210 (PIOA), 0xFFFFF410 (PIOB), 0xFFFFF610 (PIOC), 0xFFFFF810 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line. 489 6264C–CAP–24-Mar-09 33.6.5 Name: PIO Controller Output Disable Register PIO_ODR Addresses: 0xFFFFF214 (PIOA), 0xFFFFF414 (PIOB), 0xFFFFF614 (PIOC), 0xFFFFF814 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. 33.6.6 Name: PIO Controller Output Status Register PIO_OSR Addresses: 0xFFFFF218 (PIOA), 0xFFFFF418 (PIOB), 0xFFFFF618 (PIOC), 0xFFFFF818 (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output. 490 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.6.7 Name: PIO Controller Input Filter Enable Register PIO_IFER Addresses: 0xFFFFF220 (PIOA), 0xFFFFF420 (PIOB), 0xFFFFF620 (PIOC), 0xFFFFF820 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 33.6.8 Name: PIO Controller Input Filter Disable Register PIO_IFDR Addresses: 0xFFFFF224 (PIOA), 0xFFFFF424 (PIOB), 0xFFFFF624 (PIOC), 0xFFFFF824 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line. 491 6264C–CAP–24-Mar-09 33.6.9 Name: PIO Controller Input Filter Status Register PIO_IFSR Addresses: 0xFFFFF228 (PIOA), 0xFFFFF428 (PIOB), 0xFFFFF628 (PIOC), 0xFFFFF828 (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 33.6.10 Name: PIO Controller Set Output Data Register PIO_SODR Addresses: 0xFFFFF230 (PIOA), 0xFFFFF430 (PIOB), 0xFFFFF630 (PIOC), 0xFFFFF830 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line. 492 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.6.11 Name: PIO Controller Clear Output Data Register PIO_CODR Addresses: 0xFFFFF234 (PIOA), 0xFFFFF434 (PIOB), 0xFFFFF634 (PIOC), 0xFFFFF834 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 33.6.12 Name: PIO Controller Output Data Status Register PIO_ODSR Addresses: 0xFFFFF238 (PIOA), 0xFFFFF438 (PIOB), 0xFFFFF638 (PIOC), 0xFFFFF838 (PIOD) Access: 31 Read-only or Read-write 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1. 493 6264C–CAP–24-Mar-09 33.6.13 Name: PIO Controller Pin Data Status Register PIO_PDSR Addresses: 0xFFFFF23C (PIOA), 0xFFFFF43C (PIOB), 0xFFFFF63C (PIOC), 0xFFFFF83C (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 33.6.14 Name: PIO Controller Interrupt Enable Register PIO_IER Addresses: 0xFFFFF240 (PIOA), 0xFFFFF440 (PIOB), 0xFFFFF640 (PIOC), 0xFFFFF840 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line. 494 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.6.15 Name: PIO Controller Interrupt Disable Register PIO_IDR Addresses: 0xFFFFF244 (PIOA), 0xFFFFF444 (PIOB), 0xFFFFF644 (PIOC), 0xFFFFF844 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 33.6.16 Name: PIO Controller Interrupt Mask Register PIO_IMR Addresses: 0xFFFFF248 (PIOA), 0xFFFFF448 (PIOB), 0xFFFFF648 (PIOC), 0xFFFFF848 (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line. 495 6264C–CAP–24-Mar-09 33.6.17 Name: PIO Controller Interrupt Status Register PIO_ISR Addresses: 0xFFFFF24C (PIOA), 0xFFFFF44C (PIOB), 0xFFFFF64C (PIOC), 0xFFFFF84C (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 33.6.18 Name: PIO Multi-driver Enable Register PIO_MDER Addresses: 0xFFFFF250 (PIOA), 0xFFFFF450 (PIOB), 0xFFFFF650 (PIOC), 0xFFFFF850 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line. 496 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.6.19 Name: PIO Multi-driver Disable Register PIO_MDDR Addresses: 0xFFFFF254 (PIOA), 0xFFFFF454 (PIOB), 0xFFFFF654 (PIOC), 0xFFFFF854 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line. 33.6.20 Name: PIO Multi-driver Status Register PIO_MDSR Addresses: 0xFFFFF258 (PIOA), 0xFFFFF458 (PIOB), 0xFFFFF658 (PIOC), 0xFFFFF858 (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 497 6264C–CAP–24-Mar-09 33.6.21 Name: PIO Pull Up Disable Register PIO_PUDR Addresses: 0xFFFFF260 (PIOA), 0xFFFFF460 (PIOB), 0xFFFFF660 (PIOC), 0xFFFFF860 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 33.6.22 Name: PIO Pull Up Enable Register PIO_PUER Addresses: 0xFFFFF264 (PIOA), 0xFFFFF464 (PIOB), 0xFFFFF664 (PIOC), 0xFFFFF864 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line. 498 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.6.23 Name: PIO Pull Up Status Register PIO_PUSR Addresses: 0xFFFFF268 (PIOA), 0xFFFFF468 (PIOB), 0xFFFFF668 (PIOC), 0xFFFFF868 (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 33.6.24 Name: PIO Peripheral A Select Register PIO_ASR Addresses: 0xFFFFF270 (PIOA), 0xFFFFF470 (PIOB), 0xFFFFF670 (PIOC), 0xFFFFF870 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function. 499 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.6.25 Name: PIO Peripheral B Select Register PIO_BSR Addresses: 0xFFFFF274 (PIOA), 0xFFFFF474 (PIOB), 0xFFFFF674 (PIOC), 0xFFFFF874 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. 33.6.26 Name: PIO Peripheral A B Status Register PIO_ABSR Addresses: 0xFFFFF278 (PIOA), 0xFFFFF478 (PIOB), 0xFFFFF678 (PIOC), 0xFFFFF878 (PIOD) Access: 31 Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B. 500 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 33.6.27 Name: PIO Output Write Enable Register PIO_OWER Addresses: 0xFFFFF2A0 (PIOA), 0xFFFFF4A0 (PIOB), 0xFFFFF6A0 (PIOC), 0xFFFFF8A0 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 33.6.28 Name: PIO Output Write Disable Register PIO_OWDR Addresses: 0xFFFFF2A4 (PIOA), 0xFFFFF4A4 (PIOB), 0xFFFFF6A4 (PIOC), 0xFFFFF8A4 (PIOD) Access: 31 Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line. 501 6264C–CAP–24-Mar-09 33.6.29 Name: PIO Output Write Status Register PIO_OWSR 0xFFFFF2A8 (PIOA), 0xFFFFF4A8 (PIOB), 0xFFFFF6A8 (PIOC), 0xFFFFF8A8 (PIOD) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line. 502 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34. Serial Peripheral Interface (SPI) 34.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. • Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. • Slave Select (NSS): This control line allows slaves to be turned on and off by hardware. 503 6264C–CAP–24-Mar-09 34.2 Block Diagram Figure 34-1. Block Diagram PDC APB SPCK MISO MCK SPI Interface PIO MOSI NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 PMC SPI Interrupt 34.3 Application Block Diagram Figure 34-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 504 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.4 Signal Description Signal Description Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input Table 34-1. 34.5 34.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. Table 34-2. I/O Lines Signal SPI0_MISO SPI0_MOSI SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS2 SPI0_NPCS3 SPI0_NPCS3 SPI0_SPCK SPI1_MISO SPI1_MOSI SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS2 SPI1_NPCS3 SPI1_NPCS3 SPI1_SPCK I/O Line PA0 PA1 PA5 PA3 PA4 PD0 PA28 PD1 PA2 PB12 PB13 PB15 PB16 PB17 PD2 PB18 PD3 PB14 Peripheral B B B B B B A B B A A A A A B A B A Instance SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 505 6264C–CAP–24-Mar-09 34.5.2 Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI. 34.5.3 Table 34-3. Instance SPI0 SPI1 Peripheral IDs ID 15 16 506 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.6 34.6.1 Functional Description Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode. 34.6.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 34-4 shows the four modes and corresponding parameter settings. Table 34-4. SPI Bus Protocol Mode SPI Mode 0 1 2 3 CPOL 0 0 1 1 NCPHA 1 0 1 0 Figure 34-3 and Figure 34-4 show examples of data transfers. 507 6264C–CAP–24-Mar-09 Figure 34-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 34-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) * MSB 6 5 4 3 2 1 LSB NSS (to slave) * Not defined but normally LSB of previous character transmitted. 508 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 34-5, shows a block diagram of the SPI when operating in Master Mode. Figure 34-6 on page 511 shows a flow chart describing how transfers are handled. 509 6264C–CAP–24-Mar-09 34.6.3.1 Master Mode Block Diagram Figure 34-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL MISO LSB SPI_RDR RD RDRF OVRES Shift Register MSB MOSI SPI_TDR TD SPI_CSR0..3 SPI_RDR CSAAT PS SPI_MR PCS 0 SPI_TDR PCS 1 NPCS0 PCSDEC Current Peripheral PCS NPCS3 NPCS2 NPCS1 TDRE MSTR NPCS0 MODFDIS MODF 510 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.6.3.2 Master Mode Flow Diagram Figure 34-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ? 0 1 CSAAT ? PS ? Variable peripheral yes 0 Fixed peripheral 0 0 PS ? Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral 1 SPI_TDR(PCS) = NPCS ? no NPCS = 0xF SPI_MR(PCS) = NPCS ? no NPCS = 0xF 1 NPCS = SPI_TDR(PCS) Delay DLYBCS Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS), SPI_TDR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT 0 TDRE ? 1 1 CSAAT ? 0 NPCS = 0xF Delay DLYBCS 511 6264C–CAP–24-Mar-09 34.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 34.6.3.4 Transfer Delays Figure 34-7 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: • The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. • The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. • The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 34-7. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 34.6.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: • Fixed Peripheral Select: SPI exchanges data with only one peripheral 512 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the Lisps and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 34.6.3.6 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 34.6.3.7 Peripheral Deselection When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. 513 6264C–CAP–24-Mar-09 Figure 34-8 shows different peripheral deselection cases and the effect of the CSAAT bit. Figure 34-8. Peripheral Deselection CSAAT = 0 CSAAT = 1 TDRE DLYBCT A DLYBCS PCS = A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE DLYBCT A DLYBCS PCS=A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] DLYBCT A DLYBCS PCS = B B A DLYBCT B DLYBCS PCS = B Write SPI_TDR 34.6.3.8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the PIO controller, so that external pull up resistors are needed to guarantee high level. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). 34.6.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). 514 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. (For more information on BITS field, see also, the “SPI Chip Select Register” on page 527.) (Note:) below the register table; Section 34.7.9 When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 34-9 shows a block diagram of the SPI when operating in Slave Mode. Figure 34-9. Slave Mode Functional Bloc Diagram SPCK NSS SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RD RDRF OVRES SPI Clock Shift Register MSB MISO SPI_TDR TD TDRE 515 6264C–CAP–24-Mar-09 34.7 Serial Peripheral Interface (SPI) User Interface Register Mapping Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 – Read-write Read-write Read-write Read-write – 0x0 0x0 0x0 0x0 – Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read-write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0 Table 34-5. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x004C - 0x00F8 0x100 - 0x124 516 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.7.1 Name: SPI Control Register SPI_CR Addresses: 0xFFFA4000 (0), 0xFFFA8000 (1) Access: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 LASTXFER 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. • SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. PDC channels are not affected by software reset. • LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 517 6264C–CAP–24-Mar-09 34.7.2 Name: SPI Mode Register SPI_MR Addresses: 0xFFFA4004 (0), 0xFFFA8004 (1) Access: 31 Read/Write 30 29 28 27 26 25 24 DLYBCS 23 22 21 20 19 18 17 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 LLB – – MODFDIS – PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. • PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14. • MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. • LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) 518 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay: D LYBCS Delay Between Chip Selects = ---------------------MCK 519 6264C–CAP–24-Mar-09 34.7.3 Name: SPI Receive Data Register SPI_RDR Addresses: 0xFFFA4008 (0), 0xFFFA8008 (1) Access: 31 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 RD 7 6 5 4 3 2 1 0 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. 520 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.7.4 Name: SPI Transmit Data Register SPI_TDR Addresses: 0xFFFA400C (0), 0xFFFA800C (1) Access: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 LASTXFER 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 TD 7 6 5 4 3 2 1 0 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. • PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS • LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1). 521 6264C–CAP–24-Mar-09 34.7.5 Name: SPI Status Register SPI_SR Addresses: 0xFFFA4010 (0), 0xFFFA8010 (1) Access: 31 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 SPIENS 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. • TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. • MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. • OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. • ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). • ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). • RXBUFF: RX Buffer Full 0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0. 522 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC. 523 6264C–CAP–24-Mar-09 34.7.6 Name: SPI Interrupt Enable Register SPI_IER Addresses: 0xFFFA4014 (0), 0xFFFA8014 (1) Access: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = No effect. 1 = Enables the corresponding interrupt. • RDRF: Receive Data Register Full Interrupt Enable • TDRE: SPI Transmit Data Register Empty Interrupt Enable • MODF: Mode Fault Error Interrupt Enable • OVRES: Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable • NSSR: NSS Rising Interrupt Enable • TXEMPTY: Transmission Registers Empty Enable 524 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.7.7 Name: SPI Interrupt Disable Register SPI_IDR Addresses: 0xFFFA4018 (0), 0xFFFA8018 (1) Access: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = No effect. 1 = Disables the corresponding interrupt. • RDRF: Receive Data Register Full Interrupt Disable • TDRE: SPI Transmit Data Register Empty Interrupt Disable • MODF: Mode Fault Error Interrupt Disable • OVRES: Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable • NSSR: NSS Rising Interrupt Disable • TXEMPTY: Transmission Registers Empty Disable 525 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.7.8 Name: SPI Interrupt Mask Register SPI_IMR Addresses: 0xFFFA401C (0), 0xFFFA801C (1) Access: 31 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. • RDRF: Receive Data Register Full Interrupt Mask • TDRE: SPI Transmit Data Register Empty Interrupt Mask • MODF: Mode Fault Error Interrupt Mask • OVRES: Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask • NSSR: NSS Rising Interrupt Mask • TXEMPTY: Transmission Registers Empty Mask 526 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 34.7.9 Name: SPI Chip Select Register SPI_CSR0... SPI_CSR3 Addresses: 0xFFFA4030 (0), 0xFFFA8030 (1) Access: 31 Read/Write 30 29 28 27 26 25 24 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 7 6 5 4 3 2 1 0 BITS Note: CSAAT – NCPHA CPOL SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written. • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. • NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. • BITS: Bits Per Transfer (See the (Note:) below the register table; Section 34.7.9 “SPI Chip Select Register” on page 527.) The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 Bits Per Transfer 8 9 10 11 12 13 14 15 527 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A BITS 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCKSPCK Baudrate = -------------SCBR Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: Delay Before SPCK = DLYBS -----------------MCK • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 × DLYBCT Delay Between Consecutive Transfers = -----------------------------------MCK 528 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 35. Two-wire Interface (TWI) 35.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. 20 Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Below, Table 35-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I2C compatible device. Table 35-1. I2C Standard Standard Mode Speed (100 KHz) Fast Mode Speed (400 KHz) 7 or 10 bits Slave Addressing START BYTE (1) Atmel TWI compatibility with i2C Standard Atmel TWI Supported Supported Supported Not Supported Supported Supported Not Supported Supported Supported Repeated Start (Sr) Condition ACK and NACK Management Slope control and input filtering (Fast mode) Clock stretching Multi Master Capability Note: 1. START + b000000001 + Ack + Sr 35.2 List of Abbreviations Table 35-2. Abbreviation TWI A NA P S Sr SADR Abbreviations Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start Slave Address 529 6264C–CAP–24-Mar-09 Table 35-2. Abbreviation ADR R W Abbreviations Description Any address except SADR Read Write 35.3 Block Diagram Figure 35-1. Block Diagram APB Bridge TWCK PIO Two-wire Interface TWD PMC MCK TWI Interrupt AIC 35.4 Application Block Diagram Figure 35-2. Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 I²C RTC Slave 2 I²C LCD Controller Slave 3 I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard 530 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.5 I/O Lines Description I/O Lines Description Pin Name TWD TWCK Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output 35.6 35.6.1 Product Dependencies I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 35-2 on page 530). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following step: • Program the PIO controller to dedicate TWD and TWCK as peripheral lines. The user must not program TWD and TWCK as open-drain. It is already done by the hardware. Table 35-3. Instance TWI TWI I/O Lines Signal TWCK TWD I/O Line PB5 PB4 Peripheral B B 35.6.2 Power Management • Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 35.6.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. Table 35-4. Instance TWI Peripheral IDs ID 14 531 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.7 35.7.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 35-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 35-3). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 35-3. START and STOP Conditions TWD TWCK Start Stop Figure 35-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 35.7.2 Modes of Operation The TWI has six modes of operations: • Master transmitter mode • Master receiver mode • Multi-master transmitter mode • Multi-master receiver mode • Slave transmitter mode • Slave receiver mode These modes are described in the following chapters. 532 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.8 35.8.1 Master Mode Definition The Master is the device that starts a transfer, generates a clock and stops it. 35.8.2 Application Block Diagram Figure 35-5. Master Mode Typical Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 I²C RTC Slave 2 I²C LCD Controller Slave 3 I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard 35.8.3 Programming Master Mode The following registers have to be programmed before entering Master mode: 1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode. 2. CKDIV + CHDIV + CLDIV: Clock Waveform. 3. SVDIS: Disable the slave mode. 4. MSEN: Enable the master mode. 35.8.4 Master Transmitter Mode After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR. 533 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the TWI_THR, the SCL is released and the data is sent. To generate a STOP event, the STOP command must be performed by writing in the STOP field of TWI_CR. After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the TWI_THR or until a STOP command is performed. See Figure 35-6, Figure 35-7, and Figure 35-8. Figure 35-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 35-7. Master Write with Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 534 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent TXRDY is used as Transmit Ready for the PDC transmit channel. 35.8.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after the stop condition. See Figure 35-9. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 35-9. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-tolast data received. See Figure 35-10. For Internal Address usage see Section 35.8.6. Figure 35-9. Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR 535 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel. 35.8.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 35-12. See Figure 35-11 and Figure 35-13 for Master Write operation with internal address. The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0. In the figures below the following abbreviations are used: •S • Sr •P •W •R •A •N • DADR • IADR Start Repeated Start Stop Write Read Acknowledge Not Acknowledge Device Address Internal Address 35.8.6.1 536 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A DATA A P One byte internal address TWD S DADR W A IADR(7:0) A DATA A P Figure 35-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA N P N P One byte internal address TWD S DADR W A IADR(7:0) A Sr DADR R A DATA N P 35.8.6.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) 3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 35-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 35-13. Internal Address Usage S T A R T W R I T E S T O P Device Address 0 M S B FIRST WORD ADDRESS SECOND WORD ADDRESS DATA LRA S/C BW K M S B A C K LA SC BK A C K 537 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.8.7 Using the Peripheral DMA Controller (PDC) The use of the PDC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequences: 35.8.7.1 Data Transmit with the PDC 1. Initialize the transmit PDC (memory pointers, size, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC end TX flag. 5. Disable the PDC by setting the PDC TXDIS bit. 35.8.7.2 Data Receive with the PDC 1. Initialize the receive PDC (memory pointers, size - 1, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC RXTEN bit. 4. Wait for the PDC end RX flag. 5. Disable the PDC by setting the PDC RXDIS bit. 35.8.8 SMBUS Quick Command (Master Mode Only) The TWI interface can perform a Quick Command: 1. Configure the master mode (DADR, CKDIV, etc.). 2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWI_CR. Figure 35-14. SMBUS Quick Command TWD S DADR R/W A P TXCOMP TXRDY Write QUICK command in TWI_CR 35.8.9 Read-write Flowcharts The following flowcharts shown in Figure 35-16 on page 540, Figure 35-17 on page 541, Figure 35-18 on page 542, Figure 35-19 on page 543 and Figure 35-20 on page 544 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. 538 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-15. TWI Write Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Write STOP Command TWI_CR = STOP Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished 539 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-16. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Write STOP command TWI_CR = STOP Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished 540 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-17. TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Read Status register TWI_THR = data to send TXRDY = 1? Yes Data to send? Yes No Write STOP Command TWI_CR = STOP Read Status register Yes No TXCOMP = 1? END 541 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-18. TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? Yes Read Receive Holding Register No Read Status register No TXCOMP = 1? Yes END 542 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-19. TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END 543 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-20. TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) No No Last data to read but one? Yes Stop the transfer TWI_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) Read status register TXCOMP = 1? Yes END No 544 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.9 35.9.1 Multi-master Mode Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 35-22 on page 546. 35.9.2 Different Multi-master Modes Two multi-master modes may be distinguished: 1. TWI is considered as a Master only and will never be addressed. 2. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported. 35.9.2.1 TWI as Master Only In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 3521 on page 546). Note: The state of the bus (busy or free) is not indicated in the user interface. 35.9.2.2 TWI as Master or Slave The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below. 1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed). 2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. 545 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR. Figure 35-21. Programmer Sends Data While the Bus is Busy TWCK STOP sent by the master TWD DATA sent by a master Bus is busy Bus is free TWI DATA transfer Transfer is kept START sent by the TWI DATA sent by the TWI A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 35-22. Arbitration Cases TWCK TWD TWCK Data from a Master Data from TWI TWD S S S 1 1 1 0 0 11 0 1 Arbitration is lost TWI stops sending data P S S 1 1 1 0 1 Arbitration is lost The master stops sending data 0 01 0 01 1 1 Data from the TWI 00 11 Data from the master P S ARBLST Bus is busy Bus is free TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Transfer is stopped Transfer is kept Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 35-23 on page 547 gives an example of read and write operations in Multi-master mode. 546 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-23. Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? No No EOSACC = 1 ? Yes No TXCOMP = 1 ? Yes No Yes GACC = 1 ? No No No SVREAD = 0 ? Yes TXRDY= 1 ? Yes Write in TWI_THR RXRDY= 0 ? Yes Read TWI_RHR No Need to perform a master access ? GENERAL CALL TREATMENT Yes Decoding of the programming sequence Prog seq OK ? Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W No Read Status Register Yes ARBLST = 1 ? No Yes Yes RXRDY= 0 ? No Read TWI_RHR Yes Data to read? No MREAD = 1 ? No TXRDY= 0 ? No Data to send ? No Yes Write in TWI_THR Yes Stop Transfer TWI_CR = STOP Read Status Register Yes No TXCOMP = 0 ? 547 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.10 Slave Mode 35.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 35.10.2 Application Block Diagram Figure 35-24. Slave Mode Typical Application Block Diagram VDD R TWD TWCK R Master Host with TWI Interface Host with TWI Interface Slave 1 Host with TWI Interface Slave 2 LCD Controller Slave 3 35.10.3 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode. 2. MSDIS (TWI_CR): Disable the master mode. 3. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account. 35.10.4 Receiving Data After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set. 35.10.4.1 Read Sequence In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. 548 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Note that a STOP or a repeated START always follows a NACK. See Figure 35-25 on page 550. 35.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 35-26 on page 550. 35.10.4.3 Clock Synchronization Sequence In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 35-28 on page 552 and Figure 35-29 on page 553. 35.10.4.4 General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 35-27 on page 551. 35.10.4.5 PDC As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT recommended in SLAVE mode. 35.10.5 35.10.5.1 Data Transfer Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 35-25 on page 550 describes the write operation. 549 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 35-25. Read Access Ordered by a MASTER SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK ACK/NACK from the Master A DATA NA S/Sr TWD TXRDY NACK SVACC SVREAD EOSVACC S ADR R NA DATA NA P/S/Sr SADR R A DATA A Write THR Read RHR SVREAD has to be taken into account only while SVACC is active Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 35.10.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 35-26 on page 550 describes the Write operation. Figure 35-26. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK Read RHR TWD RXRDY SVACC SVREAD EOSVACC Notes: S ADR W NA DATA NA P/S/Sr SADR W A DATA A A DATA NA S/Sr SVREAD has to be taken into account only while SVACC is active 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. 550 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.10.5.3 General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 35-27 on page 551 describes the General Call access. Figure 35-27. Master Performs a General Call 0000000 + W RESET command = 00000110X WRITE command = 00000100X A TXD S GENERAL CALL A Reset or write DADD A DATA1 A DATA2 A New SADR P New SADR Programming sequence GCACC Reset after read SVACC Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. 551 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 35-28 on page 552 describes the clock synchronization in Read mode. 35.10.5.5 Figure 35-28. Clock Synchronization in Read Mode TWI_THR DATA0 1 DATA1 DATA2 S SADR R A DATA0 A DATA1 A XXXXXXX 2 DATA2 NA S TWCK Write THR CLOCK is tied low by the TWI as long as THR is empty SCLWS TXRDY SVACC SVREAD TXCOMP As soon as a START is detected TWI_THR is transmitted to the shift register 1 2 The data is memorized in TWI_THR until a new value is written Ack or Nack from the master The clock is stretched after the ACK, the state of TWD is undefined during clock stretching Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock synchronization mechanism is started. 552 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.10.5.6 Clock Synchronization in Write Mode The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 35-29 on page 553 describes the clock synchronization in Read mode. Figure 35-29. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full TWD S SADR W A DATA0 A DATA1 A DATA2 NA S ADR TWI_RHR SCLWS DATA0 is not read in the RHR DATA1 DATA2 SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 SVACC SVREAD TXCOMP As soon as a START is detected Rd DATA1 Rd DATA2 Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. 553 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.10.5.7 35.10.5.8 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 35-30 on page 554 describes the repeated start + reversal from Read to Write mode. Figure 35-30. Repeated Start + Reversal from Read to Write Mode TWI_THR DATA0 DATA1 TWD S SADR R A DATA0 A DATA1 NA Sr SADR W A DATA2 A DATA3 A DATA3 P TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP As soon as a START is detected DATA2 Cleared after read 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 35.10.5.9 Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command.Figure 35-31 on page 554 describes the repeated start + reversal from Write to Read mode. Figure 35-31. Repeated Start + Reversal from Write to Read Mode TWI_THR DATA2 DATA3 TWD TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP S SADR W A DATA0 A DATA1 A Sr SADR R A DATA2 A DATA3 NA P DATA0 DATA1 Read TWI_RHR As soon as a START is detected Cleared after read Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 554 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.10.6 Read Write Flowcharts The flowchart shown in Figure 35-32 on page 555 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 35-32. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? No No GACC = 1 ? No SVREAD = 0 ? No EOSACC = 1 ? TXRDY= 1 ? No No Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? END Read TWI_RHR No GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR 555 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11 Two-wire Interface (TWI) User Interface Table 35-5. Offset 0x00 0x04 0x08 0x0C 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 - 0xFC 0x100 - 0x124 Register Mapping Register Control Register Master Mode Register Slave Mode Register Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Reserved for the PDC Name TWI_CR TWI_MMR TWI_SMR TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR – – Access Write-only Read-write Read-write Read-write Read-write Read-only Write-only Write-only Read-only Read-only Write-only – – Reset N/A 0x00000000 0x00000000 0x00000000 0x00000000 0x0000F009 N/A N/A 0x00000000 0x00000000 0x00000000 – – 556 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.1 Name: Address: Access: Reset: 31 – 23 – 15 – TWI Control Register TWI_CR 0xFFF88000 Write-only 0x00000000 30 – 22 – 14 – 6 QUICK 29 – 21 – 13 – 5 SVDIS 28 – 20 – 12 – 4 SVEN 27 – 19 – 11 – 3 MSDIS 26 – 18 – 10 – 2 MSEN 25 – 17 – 9 – 1 STOP 24 – 16 – 8 – 0 START 7 SWRST • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR). • STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In master read mode, if a NACK bit is received, the STOP is automatically performed. – In master data write operation, a STOP condition will be sent after the transmission of the current data is finished. • MSEN: TWI Master Mode Enabled 0 = No effect. 1 = If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. • MSDIS: TWI Master Mode Disabled 0 = No effect. 1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. 557 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 • SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0 = No effect. 1 = If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset. 558 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.2 Name: Address: Access: Reset: 31 – 23 – 15 – 7 – TWI Master Mode Register TWI_MMR 0xFFF88004 Read-write 0x00000000 30 – 22 29 – 21 28 – 20 27 – 19 DADR 11 – 3 – 26 – 18 25 – 17 24 – 16 14 – 6 – 13 – 5 – 12 MREAD 4 – 10 – 2 – 9 IADRSZ 1 – 8 0 – • IADRSZ: Internal Device Address Size IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address One-byte internal device address Two-byte internal device address Three-byte internal device address • MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. • DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode. 559 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.3 Name: Address: Access: Reset: 31 – 23 – 15 – 7 – TWI Slave Mode Register TWI_SMR 0xFFF88008 Read-write 0x00000000 30 – 22 29 – 21 28 – 20 27 – 19 SADR 11 – 3 – 26 – 18 25 – 17 24 – 16 14 – 6 – 13 – 5 – 12 – 4 – 10 – 2 – 9 8 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. 560 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.4 Name: Address: Access: Reset: 31 – 23 TWI Internal Address Register TWI_IADR 0xFFF8800C Read-write 0x00000000 30 – 22 29 – 21 28 – 20 IADR 27 – 19 26 – 18 25 – 17 24 – 16 15 14 13 12 IADR 11 10 9 8 7 6 5 4 IADR 3 2 1 0 • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. 561 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.5 Name: Address: Access: Reset: 31 – 23 TWI Clock Waveform Generator Register TWI_CWGR 0xFFF88010 Read-write 0x00000000 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 25 – 17 CKDIV 9 24 – 16 15 14 13 12 CHDIV 11 10 8 7 6 5 4 CLDIV 3 2 1 0 TWI_CWGR is only used in Master mode. • CLDIV: Clock Low Divider The SCL low period is defined as follows: T low = ( ( CLDIV × 2 CKDIV ) + 4 ) × T MCK • CHDIV: Clock High Divider The SCL high period is defined as follows: T high = ( ( CHDIV × 2 CKDIV ) + 4 ) × T MCK • CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. 562 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.6 Name Address: Access: Reset: 31 – 23 – TWI Status Register TWI_SR 0xFFF88020 Read-only 0x0000F009 30 – 22 – 14 RXBUFF 6 OVRE 29 – 21 – 13 ENDTX 5 GACC 28 – 20 – 12 ENDRX 4 SVACC 27 – 19 – 11 EOSACC 3 SVREAD 26 – 18 – 10 SCLWS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 15 TXBUFE 7 – • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame. 1 = When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 35-8 on page 535 and in Figure 35-10 on page 536. TXCOMP used in Slave mode: 0 = As soon as a Start is detected. 1 = After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 35-28 on page 552, Figure 35-29 on page 553, Figure 35-30 on page 554 and Figure 35-31 on page 554. • RXRDY: Receive Holding Register Ready (automatically set / reset) 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 35-10 on page 536. RXRDY behavior in Slave mode can be seen in Figure 35-26 on page 550, Figure 35-29 on page 553, Figure 35-30 on page 554 and Figure 35-31 on page 554. • TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode: 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 35-8 on page 535. 563 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 35-25 on page 550, Figure 35-28 on page 552, Figure 35-30 on page 554 and Figure 35-31 on page 554. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0 = Indicates that a write access is performed by a Master. 1 = Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 35-25 on page 550, Figure 35-26 on page 550, Figure 35-30 on page 554 and Figure 35-31 on page 554. • SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 35-25 on page 550, Figure 35-26 on page 550, Figure 35-30 on page 554 and Figure 35-31 on page 554. • GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0 = No General Call has been detected. 1 = A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. GACC behavior can be seen in Figure 35-27 on page 551. • OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. • NACK: Not Acknowledged (clear on read) NACK used in Master mode: 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. 564 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 NACK used in Slave Read mode: 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 35-28 on page 552 and Figure 35-29 on page 553. • EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0 = A slave access is being performing. 1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 35-30 on page 554 and Figure 35-31 on page 554 • ENDRX: End of RX buffer This bit is only used in Master mode. 0 = The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR. • ENDTX: End of TX buffer This bit is only used in Master mode. 0 = The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR. • RXBUFF: RX Buffer Full This bit is only used in Master mode. 0 = TWI_RCR or TWI_RNCR have a value other than 0. 1 = Both TWI_RCR and TWI_RNCR have a value of 0. 565 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 • TXBUFE: TX Buffer Empty This bit is only used in Master mode. 0 = TWI_TCR or TWI_TNCR have a value other than 0. 1 = Both TWI_TCR and TWI_TNCR have a value of 0. 566 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.7 Name: Address: Access: Reset: 31 – 23 – TWI Interrupt Enable Register TWI_IER 0xFFF88024 Write-only 0x00000000 30 – 22 – 14 RXBUFF 6 OVRE 29 – 21 – 13 ENDTX 5 GACC 28 – 20 – 12 ENDRX 4 SVACC 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 15 TXBUFE 7 – • TXCOMP: Transmission Completed Interrupt Enable • RXRDY: Receive Holding Register Ready Interrupt Enable • TXRDY: Transmit Holding Register Ready Interrupt Enable • SVACC: Slave Access Interrupt Enable • GACC: General Call Access Interrupt Enable • OVRE: Overrun Error Interrupt Enable • NACK: Not Acknowledge Interrupt Enable • ARBLST: Arbitration Lost Interrupt Enable • SCL_WS: Clock Wait State Interrupt Enable • EOSACC: End Of Slave Access Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 567 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.8 Name: Address: Access: Reset: 31 – 23 – TWI Interrupt Disable Register TWI_IDR 0xFFF88028 Write-only 0x00000000 30 – 22 – 14 RXBUFF 6 OVRE 29 – 21 – 13 ENDTX 5 GACC 28 – 20 – 12 ENDRX 4 SVACC 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 15 TXBUFE 7 – • TXCOMP: Transmission Completed Interrupt Disable • RXRDY: Receive Holding Register Ready Interrupt Disable • TXRDY: Transmit Holding Register Ready Interrupt Disable • SVACC: Slave Access Interrupt Disable • GACC: General Call Access Interrupt Disable • OVRE: Overrun Error Interrupt Disable • NACK: Not Acknowledge Interrupt Disable • ARBLST: Arbitration Lost Interrupt Disable • SCL_WS: Clock Wait State Interrupt Disable • EOSACC: End Of Slave Access Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 568 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.9 Name: Address: Access: Reset: 31 – 23 – TWI Interrupt Mask Register TWI_IMR 0xFFF8802C Read-only 0x00000000 30 – 22 – 14 RXBUFF 6 OVRE 29 – 21 – 13 ENDTX 5 GACC 28 – 20 – 12 ENDRX 4 SVACC 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 15 TXBUFE 7 – • TXCOMP: Transmission Completed Interrupt Mask • RXRDY: Receive Holding Register Ready Interrupt Mask • TXRDY: Transmit Holding Register Ready Interrupt Mask • SVACC: Slave Access Interrupt Mask • GACC: General Call Access Interrupt Mask • OVRE: Overrun Error Interrupt Mask • NACK: Not Acknowledge Interrupt Mask • ARBLST: Arbitration Lost Interrupt Mask • SCL_WS: Clock Wait State Interrupt Mask • EOSACC: End Of Slave Access Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 569 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 35.11.10 TWI Receive Holding Register Name: TWI_RHR Address: Access: Reset: 31 – 23 – 15 – 7 0xFFF88030 Read-only 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • RXDATA: Master or Slave Receive Holding Data 35.11.11 TWI Transmit Holding Register Name: TWI_THR Address: Access: Reset: 31 – 23 – 15 – 7 0xFFF88034 Read-write 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • TXDATA: Master or Slave Transmit Holding Data 570 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36. Universal Synchronous Asynchronous Receiver Transceiver (USART) 36.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 571 6264C–CAP–24-Mar-09 36.2 Block Diagram Figure 36-1. USART Block Diagram Peripheral DMA Controller Channel Channel USART PIO Controller RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS DTR PMC MCK MCK/DIV Modem Signals Control DSR DCD RI SLCK Baud Rate Generator SCK DIV User Interface APB 572 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.3 Application Block Diagram Figure 36-2. Application Block Diagram PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver USART RS232 Drivers Modem PSTN RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers Serial Port Differential Bus 36.4 I/O Lines Description I/O Line Description Description Serial Clock Transmit Serial Data Receive Serial Data Clear to Send Request to Send Type I/O I/O Input Input Output Low Low Active Level Table 36-1. Name SCK TXD RXD CTS RTS 573 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.5 36.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature is used, the internal pull up on TXD must also be enabled. Only USART0 is fully equipped with all the modem signals. 36.5.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. 36.5.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Inter-rupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. Table 36-2. Instance USART0 USART1 USART2 Peripheral IDs ID 8 9 10 574 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.5 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling receiver frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication • High-speed 5- to 9-bit full-duplex synchronous serial communication – MSB- or LSB-first – 1 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication • RS485 with driver control signal • ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • InfraRed IrDA Modulation and Demodulation • Test modes – Remote loopback, local loopback, automatic echo 575 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: • the Master Clock MCK • a division of the Master Clock, the divider being product dependent, but generally set to 8 • the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 36-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC SCK 36.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over ) CD ) This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. 576 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6.1.2 Baud Rate Calculation Example Table 36-3 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Baud Rate Example (OVER = 0) Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 97.66 113.93 6 8 8 12 13 20 20 23 24 30 39 40 40 52 53 54 65 81 98 114 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 38 265.31 38 377.19 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% 0.35% 0.06% Error Table 36-3. Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 60 000 000 70 000 000 The baud rate is calculated with the following formula: BaudRate = MCK ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 – ⎛ --------------------------------------------------⎞ ⎝ ActualBaudRate ⎠ 36.6.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. 577 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = ---------------------------------------------------------------⎛ 8 ( 2 – Over ) ⎛ CD + FP⎞ ⎞ -----⎝ ⎝ 8 ⎠⎠ The modified architecture is presented below: Figure 36-4. Fractional Baud Rate Generator FP USCLKS MCK MCK/DIV SCK Reserved CD Modulus Control FP CD SCK FIDI 0 OVER Sampling Divider 1 1 SYNC USCLKS = 3 Sampling Clock 0 Baud Rate Clock SYNC 0 1 2 3 16-bit Counter glitch-free logic >1 1 0 0 36.6.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. BaudRate = SelectedClock ------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 578 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- × f Fi where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 36-4. Table 36-4. DI field Di (decimal) Binary and Decimal Values for Di 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 36-5. Table 36-5. FI field Fi (decimal Binary and Decimal Values for Fi 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 36-6 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 36-6. Fi/Di 1 2 4 8 16 32 12 20 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 18 6 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). 579 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 36-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 36.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally. 36.6.3 36.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The num580 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A ber of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. Figure 36-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 36-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 36.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 36-8 illustrates this coding scheme. 581 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-8. NRZ to Manchester Encoding NRZ encoded data Manchester encoded data 1 0 1 1 0 0 0 1 Txd The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 36-9 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. Figure 36-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 36-10 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new 582 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A character. The sync waveform is in itself an invalid Manchester waveform as the transition occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information. Figure 36-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data Txd DATA One bit start frame delimiter SFD Manchester encoded data Txd DATA SFD Manchester encoded data Txd Command Sync start frame delimiter DATA Data Sync start frame delimiter 36.6.3.3 Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. 583 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-11. Bit Resynchronization Oversampling 16x Clock RXD Sampling point Expected edge Synchro. Error Synchro. Jump Tolerance Sync Jump Synchro. Error 36.6.3.4 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 36-12 and Figure 36-13 illustrate start detection and character reception when USART operates in asynchronous mode. 584 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-12. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 36-13. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 36.6.3.5 Manchester Decoder When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See Figure 36-9 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 36-14. The sample pulse rejection mechanism applies. 585 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-14. Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 36-15 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. See Figure 36-16 for an example of Manchester error detection during data phase. Figure 36-15. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Preamble Mismatch invalid pattern Manchester encoded data Txd SFD DATA Preamble Length is set to 8 Figure 36-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected 586 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-toone transition. 36.6.3.6 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 36-17. Figure 36-17. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line ASK/FSK downstream transmitter Manchester decoder USART Receiver Downstream Receiver Manchester encoder PA RF filter Mod VCO USART Emitter control The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 36-18 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 36-19. 587 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 36-18. ASK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output ASK Modulator Output Uptstream Frequency F0 0 0 1 Txd Figure 36-19. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 0 0 1 Txd 36.6.3.7 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 36-20 illustrates a character reception in synchronous mode. 588 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-20. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 36.6.3.8 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 36-21. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 589 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6.3.9 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 591. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 36-7 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 36-7. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 36-22 illustrates the parity bit status setting and clearing. 590 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-22. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 36.6.3.10 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. 36.6.3.11 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 36-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 591 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-23. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write US_THR TXRDY TXEMPTY Table 36-8 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 36-8. Maximum Timeguard Length Depending on Baud Rate Bit time µs 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 36.6.3.12 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: • Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state 592 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 36-24 shows the block diagram of the Receiver Time-out feature. Figure 36-24. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 36-9 gives the maximum time-out period for some standard baud rates. Table 36-9. Maximum Time-out Period Bit Time µs 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 593 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Table 36-9. Maximum Time-out Period (Continued) Bit Time 18 17 5 Time-out 1 170 1 138 328 Baud Rate 56000 57600 200000 36.6.3.13 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 36-25. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 36.6.3.14 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 594 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 36-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 36-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write US_CR TXRDY TXEMPTY 36.6.3.15 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 36.6.3.16 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 36-27. 595 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 36-27. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 36-28 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 36-28. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1 Figure 36-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 36-29. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 596 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 36.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 576). The USART connects to a smart card as shown in Figure 36-30. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 36-30. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 d ata bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 608 and “PAR: Parity Type” on page 609. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 36.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 36-31. 597 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 36-32. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 36-31. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 36-32. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 36.6.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 36.6.4.4 36.6.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. 598 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. 36.6.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 36-33. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 36-33. Connection to IrDA Transceivers 36.6.4.7 36.6.5 USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: • Disable TX and Enable RX 599 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). • Receive data 36.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 36-10. Table 36-10. IrDA Pulse Duration Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s Pulse Duration (3/16) 78.13 µs 19.53 µs 9.77 µs 4.88 µs 3.26 µs 1.63 µs Figure 36-34 shows an example of character transmission. Figure 36-34. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1 TXD Bit Period 3 16 Bit Period 36.6.5.2 IrDA Baud Rate Table 36-11 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 36-11. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 CD 2 11 18 22 4 22 36 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 600 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Table 36-11. IrDA Baud Rate Error (Continued) Peripheral Clock 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 57 600 38 400 38 400 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 43 6 33 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.93% 0.00% 1.38% 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 3.26 4.88 4.88 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 36.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 36-35 illustrates the operations of the IrDA demodulator. Figure 36-35. IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 43 Pulse Rejected 5 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 601 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 36-36. Figure 36-36. Typical Connection to a RS485 Bus USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 36-37 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 36-37. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 602 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6.7 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 36.6.7.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 36-38. Normal Mode Configuration RXD Receiver TXD Transmitter 36.6.7.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 36-39. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 36-39. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 36.6.7.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 36-40. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 36-40. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD 603 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.6.7.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 36-41. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 36-41. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 604 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Register Mapping Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Manchester Encoder Decoder Register Reserved Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR – US_FIDI US_NER – US_IF US_MAN – – Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write Read-write Read-write – Read-write Read-only – Read-write Read-write – – Reset – – – – 0x0 – 0x0 – 0x0 0x0 0x0 – 0x174 – – 0x0 0x30011004 – – Table 36-13. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x2C - 0x3C 0x0040 0x0044 0x0048 0x004C 0x0050 0x5C - 0xFC 0x100 - 0x128 605 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.1 Name: USART Control Register US_CR 0xFFF8C000 (0), 0xFFF90000 (1), 0xFFF94000 (2) Write-only 30 – 22 – 14 RSTNACK 6 TXEN 29 – 21 – 13 RSTIT 5 RXDIS 28 – 20 – 12 SENDA 4 RXEN 27 – 19 RTSDIS 11 STTTO 3 RSTTX 26 – 18 RTSEN 10 STPBRK 2 RSTRX 25 – 17 – 9 STTBRK 1 – 24 – 16 – 8 RSTSTA 0 – Addresses: Access: 31 – 23 – 15 RETTO 7 TXDIS • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. 606 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. • RETTO: Rearm Time-out 0: No effect 1: Restart Time-out • RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. 607 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.2 Name: USART Mode Register US_MR 0xFFF8C004 (0), 0xFFF90004 (1), 0xFFF94004 (2) Read-write 30 MODSYNC 22 VAR_SYNC 14 CHMODE 7 CHRL 6 5 USCLKS 29 MAN 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 – 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Addresses: Access: 31 ONEBIT 23 – 15 18 CLKO 10 PAR 2 16 MSBF 8 SYNC 0 1 USART_MODE • USART_MODE USART_MODE 0 0 0 0 0 1 0 0 0 1 1 0 Others 0 0 1 0 1 0 0 1 0 0 0 0 Mode of the USART Normal RS485 Hardware Handshaking IS07816 Protocol: T = 0 IS07816 Protocol: T = 1 IrDA Reserved • USCLKS: Clock Selection USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK/DIV (DIV = 8) Reserved SCK • CHRL: Character Length. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits 608 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • PAR: Parity Type PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode • NBSTOP: Number of Stop Bits NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input. Remote Loopback. RXD pin is internally connected to the TXD pin. • MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. 609 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on SYNC value. 1: The sync field is updated when a character is written into US_THR register. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. • FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). • MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. • MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit. 610 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.3 Name: USART Interrupt Enable Register US_IER 0xFFF8C008 (0), 0xFFF90008 (1), 0xFFF94008 (2) Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 MANE 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITER 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY Addresses: Access: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • ENDRX: End of Receive Transfer Interrupt Enable • ENDTX: End of Transmit Interrupt Enable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Enable • RXBUFF: Buffer Full Interrupt Enable • NACK: Non Acknowledge Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable 611 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.4 Name: USART Interrupt Disable Register US_IDR 0xFFF8C00C (0), 0xFFF9000C (1), 0xFFF9400C (2) Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 MANE 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITER 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY Addresses: Access: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • ENDRX: End of Receive Transfer Interrupt Disable • ENDTX: End of Transmit Interrupt Disable • OVRE: Overrun Error Interrupt Disable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Disable • RXBUFF: Buffer Full Interrupt Disable • NACK: Non Acknowledge Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable 612 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.5 Name: USART Interrupt Mask Register US_IMR 0xFFF8C010 (0), 0xFFF90010 (1), 0xFFF94010 (2) Read-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 MANE 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITER 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY Addresses: Access: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • ENDRX: End of Receive Transfer Interrupt Mask • ENDTX: End of Transmit Interrupt Mask • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Mask • RXBUFF: Buffer Full Interrupt Mask • NACK: Non Acknowledge Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask 613 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.6 Name: USART Channel Status Register US_CSR 0xFFF8C014 (0), 0xFFF90014 (1), 0xFFF94014 (2) Read-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITER 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 MANERR 16 – 8 TIMEOUT 0 RXRDY Addresses: Access: 31 – 23 CTS 15 – 7 PARE • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. • ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. • ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. 614 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITER: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. • TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. • RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. • NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. • CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. • CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. • MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. 615 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.7 Name: USART Receive Holding Register US_RHR 0xFFF8C018 (0), 0xFFF90018 (1), 0xFFF94018 (2) Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 RXCHR 0 Addresses: Access: 31 – 23 – 15 RXSYNH 7 • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. 616 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.8 Name: USART Transmit Holding Register US_THR 0xFFF8C01C (0), 0xFFF9001C (1), 0xFFF9401C (2) Write-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 TXCHR 0 Addresses: Access: 31 – 23 – 15 TXSYNH 7 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. 617 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.9 Name: USART Baud Rate Generator Register US_BRGR 0xFFF8C020 (0), 0xFFF90020 (1), 0xFFF94020 (2) Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CD 7 6 5 4 CD 3 2 1 0 27 – 19 – 11 26 – 18 25 – 17 FP 9 24 – 16 Addresses: Access: 31 – 23 – 15 10 8 • CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 CD 0 1 to 65535 Baud Rate = Selected Clock/16/CD OVER = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816 • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. 618 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.10 Name: USART Receiver Time-out Register US_RTOR 0xFFF8C024 (0), 0xFFF90024 (1), 0xFFF94024 (2) Read-write 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 15 – 22 – 14 – 21 – 13 – 20 – 12 TO – 19 – 11 – 18 – 10 – 17 – 9 – 16 – 8 7 6 5 4 TO 3 2 1 0 • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 619 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.11 Name: USART Transmitter Timeguard Register US_TTGR 0xFFF8C028 (0), 0xFFF90028 (1), 0xFFF94028 (2) Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TG 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Addresses: Access: 31 – 23 – 15 – 7 • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 620 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.12 Name: USART FI DI RATIO Register US_FIDI 0xFFF8C040 (0), 0xFFF90040 (1), 0xFFF94040 (2) Read-write 0x174 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FI_DI_RATIO 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 – 9 FI_DI_RATIO 1 24 – 16 – 8 Addresses: Access: Reset Value: 31 – 23 – 15 – 7 2 0 • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 621 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.13 Name: USART Number of Errors Register US_NER 0xFFF8C044 (0), 0xFFF90044 (1), 0xFFF94044 (2) Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 NB_ERRORS 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Addresses: Access: 31 – 23 – 15 – 7 • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 36.7.14 Name: USART IrDA FILTER Register US_IF 0xFFF8C04C (0), 0xFFF9004C (1), 0xFFF9404C (2) Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IRDA_FILTER 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Addresses: Access: 31 – 23 – 15 – 7 • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 622 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 36.7.15 Name: USART Manchester Configuration Register US_MAN 0xFFF8C050 (0), 0xFFF90050 (1), 0xFFF94050 (2) Read-write 30 DRIFT 22 – 14 – 6 – 29 1 21 – 13 – 5 – 28 RX_MPOL 20 – 12 TX_MPOL 4 – 27 – 19 26 – 18 RX_PL 11 – 3 10 – 2 TX_PL 9 TX_PP 1 0 8 25 RX_PP 17 16 24 Addresses: Access: 31 – 23 – 15 – 7 – This register can only be written if the WPEN bit is cleared in ”USART Write Protect Mode Register” on page 103. • TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1 - 15: The Preamble Length is TX_PL x Bit Period • TX_PP: Transmitter Preamble Pattern TX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (TX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO • TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1 - 15: The detected preamble length is RX_PL x Bit Period • RX_PP: Receiver Preamble Pattern detected RX_PP 0 0 Preamble Pattern default polarity assumed (RX_MPOL field not set) ALL_ONE 623 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 0 1 1 1 0 1 ALL_ZERO ZERO_ONE ONE_ZERO • RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. 624 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37. Synchronous Serial Controller (SSC) 37.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: • CODEC’s in master or slave mode • DAC through dedicated serial interface, particularly I2S • Magnetic card reader 625 6264C–CAP–24-Mar-09 37.2 Block Diagram Figure 37-1. Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK TD SSC Interface PIO RF RK Interrupt Control RD PMC MCK SSC Interrupt 37.3 Application Block Diagram Figure 37-2. Application Block Diagram OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management Serial AUDIO Codec Line Interface 626 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.4 Pin Name List I/O Lines Description Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output Table 37-1. Pin Name RF RK RD TF TK TD 37.5 37.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. Table 37-2. I/O Lines Signal RD0 RF0 RK0 TD0 TF0 TK0 RD1 RF1 RK1 TD1 TF1 TK1 I/O Line PB3 PB5 PB4 PB2 PB0 PB1 PB9 PB11 PB10 PB8 PB6 PB7 Peripheral A A A A A A A A A A A A Instance SSC0 SSC0 SSC0 SSC0 SSC0 SSC0 SSC1 SSC1 SSC1 SSC1 SSC1 SSC1 37.5.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. 627 37.5.3 6264C–CAP–24-Mar-09 All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. Table 37-3. Instance SSC0 SSC1 Peripheral IDs ID 17 18 37.6 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. 628 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 37-3. SSC Functional Block Diagram Transmitter Clock Output Controller TK MCK Clock Divider TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller TX clock Frame Sync Controller TF Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register TD APB User Interface Load Shift Receiver Clock Output Controller RK RK Input TX Clock RF TF Start Selector Receive Clock RX Clock Controller Frame Sync Controller RF Receive Shift Register Receive Holding Register Receive Sync Holding Register RD RX PDC PDC Interrupt Control Load Shift AIC 37.6.1 Clock Management The transmitter clock can be generated by: • an external clock received on the TK I/O pad • the receiver clock • the internal clock divider The receiver clock can be generated by: • an external clock received on the RK I/O pad • the transmitter clock • the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 629 6264C–CAP–24-Mar-09 37.6.1.1 Clock Divider Figure 37-4. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 37-5. Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 Table 37-4. Maximum MCK / 2 Minimum MCK / 8190 37.6.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. 630 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 37-6. Transmitter Clock Management TK (pin) MUX Receiver Clock Tri_state Controller Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Transmitter Clock CKI CKG 37.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. 631 6264C–CAP–24-Mar-09 Figure 37-7. Receiver Clock Management RK (pin) Tri-state Controller MUX Transmitter Clock Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Receiver Clock CKI CKG 37.6.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: – Master Clock divided by 2 if Receiver Frame Synchro is input – Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: – Master Clock divided by 6 if Transmit Frame Synchro is input – Master Clock divided by 2 if Transmit Frame Synchro is output 37.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 634. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 636. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. 632 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 37-8. Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock TF SSC_TFMR.MSBF 0 SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD Start Selector Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR 0 1 SSC_TSHR SSC_TFMR.FSLEN 37.6.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 634. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 636. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. 633 6264C–CAP–24-Mar-09 Figure 37-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF SSC_RFMR.MSBF SSC_RFMR.DATNB Start Selector Receive Shift Register RD SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN SSC_RHR SSC_RFMR.DATLEN 37.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: • Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. • Synchronously with the transmitter/receiver • On detection of a falling/rising edge on TF/RF • On detection of a low level/high level on TF/RF • On detection of a level change or an edge on TF/RF A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). 634 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 37-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF TD (Output) TD (Output) X BO B1 STTDLY Start = Falling Edge on TF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on TF TD (Output) TD (Output) TD (Output) TD (Output) X Start = Rising Edge on TF BO B1 STTDLY Start = Level Change on TF X BO B1 BO B1 STTDLY Start = Any Edge on TF X BO B1 BO B1 STTDLY Figure 37-11. Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF RD (Input) RD (Input) X BO B1 STTDLY Start = Falling Edge on RF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on RF RD (Input) RD (Input) RD (Input) RD (Input) X Start = Rising Edge on RF BO B1 STTDLY Start = Level Change on RF X BO B1 BO B1 STTDLY Start = Any Edge on RF X BO B1 BO B1 STTDLY 635 6264C–CAP–24-Mar-09 37.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 37.6.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out. 37.6.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). Receive Compare Modes Figure 37-12. Receive Compare Modes RK 37.6.6 RD (Input) CMP0 CMP1 CMP2 CMP3 Start Ignored B0 B1 B2 FSLEN Up to 16 Bits (4 in This Example) STDLY DATLEN 636 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.6.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: • the event that starts the data transfer (START) • the delay in number of bit periods between the start event and the first data bit (STTDLY) • the length of the data (DATLEN) • the number of data to be transferred for each start event (DATNB). • the length of synchronization transferred for each start event (FSLEN) • the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. 37.6.7 Table 37-5. Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR Data Frame Registers Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN SSC_RCMR SSC_RCMR PERIOD STTDLY Up to 512 Up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number of words transmitted in frame Most significant bit first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay 637 6264C–CAP–24-Mar-09 Figure 37-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start PERIOD Start TF/RF (1) FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored TD (If FSDEN = 0) RD DATNB Note: 1. Example of input on falling edge of TF/RF. Figure 37-14. Transmit Frame Format in Continuous Mode Start TD Data From SSC_THR DATLEN Data From SSC_THR DATLEN Default Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 37-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Data To SSC_RHR DATLEN Data To SSC_RHR DATLEN Note: 1. STTDLY is set to 0. 638 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.6.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 37.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. Figure 37-16. Interrupt Block Diagram SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear SSC Interrupt 639 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 37-17. Audio Application Block Diagram Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER Clock SCK Word Select WS Data SD MSB Left Channel LSB MSB Right Channel Figure 37-18. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend Serial Data In 640 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 37-19. Time Slot Application Block Diagram SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend Serial Data in 641 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8 Synchronous Serial Controller (SSC) User Interface Register Mapping Register Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Receive Compare 0 Register Receive Compare 1 Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Name SSC_CR SSC_CMR – – SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR – – SSC_RSHR SSC_TSHR SSC_RC0R SSC_RC1R SSC_SR SSC_IER SSC_IDR SSC_IMR – – Access Write-only Read-write – – Read-write Read-write Read-write Read-write Read-only Write-only – – Read-only Read-write Read-write Read-write Read-only Write-only Write-only Read-only – – Reset – 0x0 – – 0x0 0x0 0x0 0x0 0x0 – – – 0x0 0x0 0x0 0x0 0x000000CC – – 0x0 – – Table 37-6. Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100- 0x124 642 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.1 Name: SSC Control Register SSC_CR Addresses: 0xFFF98000 (0), 0xFFF9C000 (1) Access: 31 – 23 – 15 SWRST 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 TXDIS 1 RXDIS 24 – 16 – 8 TXEN 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive. If a character is currently being received, disables at end of current character reception. • TXEN: Transmit Enable 0 = No effect. 1 = Enables Transmit if TXDIS is not set. • TXDIS: Transmit Disable 0 = No effect. 1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. • SWRST: Software Reset 0 = No effect. 1 = Performs a software reset. Has priority on any other bit in SSC_CR. 643 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.2 Name: SSC Clock Mode Register SSC_CMR Addresses: 0xFFF98004 (0), 0xFFF9C004 (1) Access: 31 – 23 – 15 – 7 Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DIV 27 – 19 – 11 26 – 18 – 10 DIV 3 2 1 0 25 – 17 – 9 24 – 16 – 8 • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 644 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.3 Name: SSC Receive Clock Mode Register SSC_RCMR Addresses: 0xFFF98010 (0), 0xFFF9C010 (1) Access: 31 Read-write 30 29 28 PERIOD 27 26 25 24 23 22 21 20 STTDLY 19 18 17 16 15 – 7 CKG 14 – 6 13 – 5 CKI 12 STOP 4 11 10 START 9 8 3 CKO 2 1 CKS 0 • CKS: Receive Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock signal RK pin Reserved • CKO: Receive Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Receive Clock Output Mode None Continuous Receive Clock Receive Clock only during data transfers Reserved RK pin Input-only Output Output • CKI: Receive Clock Inversion 0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. 645 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • CKG: Receive Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Receive Clock Gating None, continuous clock Receive Clock enabled only if RF Low Receive Clock enabled only if RF High Reserved • START: Receive Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RF signal Detection of a high level on RF signal Detection of a falling edge on RF signal Detection of a rising edge on RF signal Detection of any level change on RF signal Detection of any edge on RF signal Compare 0 Reserved • STOP: Receive Stop Selection 0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. • STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. 646 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.4 Name: SSC Receive Frame Mode Register SSC_RFMR Addresses: 0xFFF98014 (0), 0xFFF9C014 (1) Access: 31 FSLEN_EXT 23 – 15 – 7 MSBF Read-write 30 FSLEN_EXT 22 29 FSLEN_EXT 21 FSOS 13 – 5 LOOP 28 FSLEN_EXT 27 – 19 26 – 18 FSLEN 25 – 17 24 FSEDGE 16 20 14 – 6 – 12 – 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • LOOP: Loop Mode 0 = Normal operating mode. 1 = RD is driven by TD, RF is driven by TF and TK drives RK. • MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is sampled first in the bit stream. 1 = The most significant bit of the data register is sampled first in the bit stream. • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). • FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods. 647 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • FSOS: Receive Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF Pin Input-only Output Output Output Output Output Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection • FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description on page 647. 648 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.5 Name: SSC Transmit Clock Mode Register SSC_TCMR Addresses: 0xFFF98018 (0), 0xFFF9C018 (1) Access: 31 Read-write 30 29 28 PERIOD 27 26 25 24 23 22 21 20 STTDLY 19 18 17 16 15 – 7 CKG 14 – 6 13 – 5 CKI 12 – 4 11 10 START 9 8 3 CKO 2 1 CKS 0 • CKS: Transmit Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved • CKO: Transmit Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Transmit Clock only during data transfers Reserved TK pin Input-only Output Output • CKI: Transmit Clock Inversion 0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. 649 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • CKG: Transmit Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TF Low Transmit Clock enabled only if TF High Reserved • START: Transmit Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 - 0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. Receive start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved • STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. 650 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.6 Name: SSC Transmit Frame Mode Register SSC_TFMR Addresses: 0xFFF9801C (0), 0xFFF9C01C (1) Access: 31 FSLEN_EXT 23 FSDEN 15 – 7 MSBF Read-write 30 FSLEN_EXT 22 29 FSLEN_EXT 21 FSOS 13 – 5 DATDEF 28 FSLEN_EXT 27 – 19 26 – 18 FSLEN 25 – 17 24 FSEDGE 16 20 14 – 6 – 12 – 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. • MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is shifted out first in the bit stream. 1 = The most significant bit of the data register is shifted out first in the bit stream. • DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1). • FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock period. 651 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • FSOS: Transmit Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF Pin Input-only Output Output Output Output Output Undefined • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection • FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description on page 651. 652 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.7 Name: SSC Receive Holding Register SSC_RHR Addresses: 0xFFF98020 (0), 0xFFF9C020 (1) Access: 31 Read-only 30 29 28 RDAT 27 26 25 24 23 22 21 20 RDAT 19 18 17 16 15 14 13 12 RDAT 11 10 9 8 7 6 5 4 RDAT 3 2 1 0 • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 37.8.8 Name: SSC Transmit Holding Register SSC_THR Addresses: 0xFFF98024 (0), 0xFFF9C024 (1) Access: 31 Write-only 30 29 28 TDAT 27 26 25 24 23 22 21 20 TDAT 19 18 17 16 15 14 13 12 TDAT 11 10 9 8 7 6 5 4 TDAT 3 2 1 0 • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 653 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.9 Name: SSC Receive Synchronization Holding Register SSC_RSHR Addresses: 0xFFF98030 (0), 0xFFF9C030 (1) Access: 31 – 23 – 15 Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RSDAT 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RSDAT 3 2 1 0 • RSDAT: Receive Synchronization Data 37.8.10 Name: SSC Transmit Synchronization Holding Register SSC_TSHR Addresses: 0xFFF98034 (0), 0xFFF9C034 (1) Access: 31 – 23 – 15 Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 TSDAT 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 TSDAT 3 2 1 0 • TSDAT: Transmit Synchronization Data 654 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.11 Name: SSC Receive Compare 0 Register SSC_RC0R Addresses: 0xFFF98038 (0), 0xFFF9C038 (1) Access: 31 – 23 – 15 Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CP0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 CP0 3 2 1 0 • CP0: Receive Compare Data 0 655 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.12 Name: SSC Receive Compare 1 Register SSC_RC1R Addresses: 0xFFF9803C (0), 0xFFF9C03C (1) Access: 31 – 23 – 15 Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CP1 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 CP1 3 2 1 0 • CP1: Receive Compare Data 1 656 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.13 Name: SSC Status Register SSC_SR Addresses: 0xFFF98040 (0), 0xFFF9C040 (1) Access: 31 – 23 – 15 – 7 RXBUFF Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 RXEN 9 CP1 1 TXEMPTY 24 – 16 TXEN 8 CP0 0 TXRDY • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty. • TXEMPTY: Transmit Empty 0 = Data remains in SSC_THR or is currently transmitted from TSR. 1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. • ENDTX: End of Transmission 0 = The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1 = The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. • TXBUFE: Transmit Buffer Empty 0 = SSC_TCR or SSC_TNCR have a value other than 0. 1 = Both SSC_TCR and SSC_TNCR have a value of 0. • RXRDY: Receive Ready 0 = SSC_RHR is empty. 1 = Data has been received and loaded in SSC_RHR. • OVRUN: Receive Overrun 0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. • ENDRX: End of Reception 0 = Data is written on the Receive Counter Register or Receive Next Counter Register. 1 = End of PDC transfer when Receive Counter Register has arrived at zero. 657 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register. • TXSYN: Transmit Sync 0 = A Tx Sync has not occurred since the last read of the Status Register. 1 = A Tx Sync has occurred since the last read of the Status Register. • RXSYN: Receive Sync 0 = An Rx Sync has not occurred since the last read of the Status Register. 1 = An Rx Sync has occurred since the last read of the Status Register. • TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled. • RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled. 658 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.14 Name: SSC Interrupt Enable Register SSC_IER Addresses: 0xFFF98044 (0), 0xFFF9C044 (1) Access: 31 – 23 – 15 – 7 RXBUFF Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0 = 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Enable 0 = No effect. 1 = Enables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Buffer Empty Interrupt • RXRDY: Receive Ready Interrupt Enable 0 = No effect. 1 = Enables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Enable 0 = No effect. 1 = Enables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Enable 0 = No effect. 1 = Enables the End of Reception Interrupt. 659 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt. 660 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.15 Name: SSC Interrupt Disable Register SSC_IDR Addresses: 0xFFF98048 (0), 0xFFF9C048 (1) Access: 31 – 23 – 15 – 7 RXBUFF Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Disable 0 = No effect. 1 = Disables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Buffer Empty Interrupt. • RXRDY: Receive Ready Interrupt Disable 0 = No effect. 1 = Disables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Disable 0 = No effect. 1 = Disables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Disable 0 = No effect. 1 = Disables the End of Reception Interrupt. 661 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt. 662 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 37.8.16 Name: SSC Interrupt Mask Register SSC_IMR Addresses: 0xFFF9804C (0), 0xFFF9C04C (1) Access: 31 – 23 – 15 – 7 RXBUFF Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled. • TXEMPTY: Transmit Empty Interrupt Mask 0 = The Transmit Empty Interrupt is disabled. 1 = The Transmit Empty Interrupt is enabled. • ENDTX: End of Transmission Interrupt Mask 0 = The End of Transmission Interrupt is disabled. 1 = The End of Transmission Interrupt is enabled. • TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The Transmit Buffer Empty Interrupt is disabled. 1 = The Transmit Buffer Empty Interrupt is enabled. • RXRDY: Receive Ready Interrupt Mask 0 = The Receive Ready Interrupt is disabled. 1 = The Receive Ready Interrupt is enabled. • OVRUN: Receive Overrun Interrupt Mask 0 = The Receive Overrun Interrupt is disabled. 1 = The Receive Overrun Interrupt is enabled. • ENDRX: End of Reception Interrupt Mask 0 = The End of Reception Interrupt is disabled. 1 = The End of Reception Interrupt is enabled. 663 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • RXBUFF: Receive Buffer Full Interrupt Mask 0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled. 1 = The Rx Sync Interrupt is enabled. 664 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 38. AC97 Controller (AC97C) 38.1 Overview The AC97 Controller is the hardware implementation of the AC97 digital controller (DC’97) compliant with AC97 Component Specification 2.2. The AC97 Controller communicates with an audio codec (AC97) or a modem codec (MC’97) via the AC-link digital serial interface. All digital audio, modem and handset data streams, as well as control (command/status) informations are transferred in accordance to the AC-link protocol. The AC97 Controller features a Peripheral DMA Controller (PDC) for audio streaming transfers. It also supports variable sampling rate and four Pulse Code Modulation (PCM) sample resolutions of 10, 16, 18 and 20 bits. 38.2 Block Diagram Figure 38-1. Functional Block Diagram MCK Clock Domain Slot Number AC97 Slot Controller SYNC Slot Number 16/20 bits Slot #0 AC97 Tag Controller Receive Shift Register Slot #0,1 AC97 CODEC Channel Transmit Shift Register SDATA_IN Slot #2 Receive Shift Register Transmit Shift Register M SDATA_OUT U X AC97C_COTHR AC97C_CORHR AC97C Interrupt AC97 Channel A AC97C_CATHR MCK AC97C_CARHR Slot #1,2 D E Transmit Shift Register Slot #3...12 Receive Shift Register M U X BITCLK User Interface Bit Clock Domain APB Interface 665 6264C–CAP–24-Mar-09 38.3 Pin Name List I/O Lines Description Pin Description 12.288-MHz bit-rate clock Receiver Data (Referred as SDATA_IN in AC-link spec) 48-KHz frame indicator and synchronizer Transmitter Data (Referred as SDATA_OUT in AC-link spec) Type Input Input Output Output Table 38-1. Pin Name AC97CK AC97RX AC97FS AC97TX The AC97 reset signal provided to the primary codec can be generated by a PIO. 38.4 Application Block Diagram Figure 38-2. Application Block diagram AC 97 Controller AC-link PIOx AC97_RESET AC'97 Primary Codec AC97_SYNC AC97FS AC97_BITCLK AC97CK AC97_SDATA_OUT AC97_SDATA_IN AC97RX AC97TX 666 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.5 38.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the AC97 Controller receiver, the PIO controller must be configured in order for the AC97C receiver I/O lines to be in AC97 Controller peripheral mode. Before using the AC97 Controller transmitter, the PIO controller must be configured in order for the AC97C transmitter I/O lines to be in AC97 Controller peripheral mode. Table 38-2. Instance AC97C AC97C AC97C AC97C I/O Lines Signal AC97CK AC97FS AC97RX AC97TX I/O Line PA7 PA6 PA9 PA8 Peripheral A A A A 38.5.2 Power Management The AC97 Controller is not continuously clocked. Its interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the AC97 Controller clock. The AC97 Controller has two clock domains. The first one is supplied by PMC and is equal to MCK. The second one is AC97CK which is sent by the AC97 Codec (Bit clock). Signals that cross the two clock domains are re-synchronized. MCK clock frequency must be higher than the AC97CK (Bit Clock) clock frequency. 38.5.3 Interrupt The AC97 Controller interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the AC97C. All AC97 Controller interrupts can be enabled/disabled by writing to the AC97 Controller Interrupt Enable/Disable Registers. Each pending and unmasked AC97 Controller interrupt will assert the interrupt line. The AC97 Controller interrupt service routine can get the interrupt source in two steps: • Reading and ANDing AC97 Controller Interrupt Mask Register (AC97C_IMR) and AC97 Controller Status Register (AC97C_SR). • Reading AC97 Controller Channel x Status Register (AC97C_CxSR). Table 38-3. Instance AC97C Peripheral IDs ID 19 667 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.6 38.6.1 Functional Description Protocol overview AC-link protocol is a bidirectional, fixed clock rate, serial digital stream. AC-link handles multiple input and output Pulse Code Modulation PCM audio streams, as well as control register accesses employing a Time Division Multiplexed (TDM) scheme that divides each audio frame in 12 outgoing and 12 incoming 20-bit wide data slots. Figure 38-3. Bidirectional AC-link Frame with Slot Assignment Slot # AC97FS CMD ADDR CMD DATA PCM L Front PCM R Front LINE 1 DAC PCM Center PCM L SURR PCM R SURR PCM LFE LINE 2 DAC HSET DAC IO CTRL 0 1 2 3 4 5 6 7 8 9 10 11 12 AC97TX (Controller Output) TAG AC97RX (Codec output) TAG STATUS ADDR STATUS DATA PCM LEFT PCM RIGHT LINE 1 DAC PCM MIC RSVED RSVED RSVED LINE 2 ADC HSET ADC IO STATUS Table 38-4. Slot # 0 1 2 3,4 5 6, 7, 8 9 10 11 12 AC-link Output Slots Transmitted from the AC97C Controller Pin Description TAG Command Address Port Command Data Port PCM playback Left/Right Channel Modem Line 1 Output Channel PCM Center/Left Surround/Right Surround PCM LFE DAC Modem Line 2 Output Channel Modem Handset Output Channel Modem GPIO Control Channel Table 38-5. Slot # 0 1 2 3,4 5 6 7, 8, 9 10 11 12 AC-link Input Slots Transmitted from the AC97C Controller Pin Description TAG Status Address Port Status Data Port PCM playback Left/Right Channel Modem Line 1 ADC Dedicated Microphone ADC Vendor Reserved Modem Line 2 ADC Modem Handset Input ADC Modem IO Status 668 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.6.1.1 38.6.1.2 Slot Description Tag Slot The tag slot, or slot 0, is a 16-bit wide slot that always goes at the beginning of an outgoing or incoming frame. Within tag slot, the first bit is a global bit that flags the entire frame validity. The next 12 bit positions sampled by the AC97 Controller indicate which of the corresponding 12 time slots contain valid data. The slot’s last two bits (combined) called Codec ID, are used to distinguish primary and secondary codec. The 16-bit wide tag slot of the output frame is automatically generated by the AC97 Controller according to the transmit request of each channel and to the SLOTREQ from the previous input frame, sent by the AC97 Codec, in Variable Sample Rate mode. 38.6.1.3 Codec Slot 1 The command/status slot is a 20-bit wide slot used to control features, and monitors status for AC97 Codec functions. The control interface architecture supports up to sixty-four 16-bit wide read-write registers. Only the even registers are currently defined and addressed. Slot 1’s bitmap is the following: • Bit 19 is for read-write command, 1= read, 0 = write. • Bits [18:12] are for control register index. • Bits [11:0] are reserved. 38.6.1.4 Codec Slot 2 Slot 2 is a 20-bit wide slot used to carry 16-bit wide AC97 Codec control register data. If the current command port operation is a read, the entire slot time is stuffed with zeros. Its bitmap is the following: • Bits [19:4] are the control register data • Bits [3:0] are reserved and stuffed with zeros. 38.6.1.5 Data Slots [3:12] Slots [3:12] are 20-bit wide data slots, they usually carry audio PCM or/and modem I/O data. 669 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.6.2 AC97 Controller Channel Organization The AC97 Controller features a Codec channel and 2 logical channels: Channel A. The Codec channel controls AC97 Codec registers, it enables write and read configuration values in order to bring the AC97 Codec to an operating state. The Codec channel always runs slot 1 and slot 2 exclusively, in both input and output directions. Channel A transfer data to/from AC97 codec. All audio samples and modem data must transit by these 2 channels. However, Channel A is connected to PDC channels thus making it suitable for audio streaming applications. Each slot of the input or the output frame that belongs to this range [3 to 12] can be operated by Channel A. The slot to channel assignment is configured by two registers: • AC97 Controller Input Channel Assignment Register (AC97C_ICA) • AC97 Controller Output Channel Assignment Register (AC97C_OCA) The AC97 Controller Input Channel Assignment Register (AC97C_ICA) configures the input slot to channel assignment. The AC97 Controller Output Channel Assignment Register (AC97C_OCA) configures the output slot to channel assignment. A slot can be left unassigned to a channel by the AC97 Controller. Slots 0, 1,and 2 cannot be assigned to Channel A through the AC97C_OCA and AC97C_ICA Registers. The width of sample data, that transit via the Channel varies and can take one of these values; 10, 16, 18 or 20 bits. Figure 38-4. Logical Channel Assignment Slot # AC97FS 0 1 2 3 4 5 6 7 8 9 10 11 12 AC97TX (Controller Output) TAG CMD ADDR CMD DATA PCM L Front PCM R Front LINE 1 DAC PCM Center PCM L SURR PCM R SURR PCM LFE LINE 2 DAC HSET DAC IO CTRL Codec Channel Channel A AC97C_OCA = 0x0000_0209 AC97RX (Codec output) TAG STATUS ADDR STATUS DATA PCM LEFT PCM RIGHT LINE 1 DAC PCM MIC RSVED RSVED RSVED LINE 2 ADC HSET ADC IO STATUS Codec Channel AC97C_ICA = 0x0000_0009 Channel A 670 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.6.2.1 AC97 Controller Setup The following operations must be performed in order to bring the AC97 Controller into an operating state: 1. Enable the AC97 Controller clock in the PMC controller. 2. Turn on AC97 function by enabling the ENA bit in AC97 Controller Mode Register (AC97C_MR). 3. Configure the input channel assignment by controlling the AC97 Controller Input Assignment Register (AC97C_ICA). 4. Configure the output channel assignment by controlling the AC97 Controller Input Assignment Register (AC97C_OCA). 5. Configure sample width for Channel A by writing the SIZE bit field in AC97C Channel x Mode Register (AC97C_CAMR). The application can write 10, 16, 18,or 20-bit wide PCM samples through the AC97 interface and they will be transferred into 20-bit wide slots. 6. Configure data Endianness for Channel A by writing CEM bit field in (AC97C_CAMR) register. Data on the AC-link are shifted MSB first. The application can write little- or big-endian data to the AC97 Controller interface. 7. Configure the PIO controller to drive the RESET signal of the external Codec. The RESET signal must fulfill external AC97 Codec timing requirements. 8. Enable Channel A by writing CEN bit field in AC97C_CxMR register. 38.6.2.2 Transmit Operation The application must perform the following steps in order to send data via a channel to the AC97 Codec: • Check if previous data has been sent by polling TXRDY flag in the AC97C Channel x Status Register (AC97_CxSR). x being one of the 2 channels. • Write data to the AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR). Once data has been transferred to the Channel x Shift Register, the TXRDY flag is automatically set by the AC97 Controller which allows the application to start a new write action. The application can also wait for an interrupt notice associated with TXRDY in order to send data. The interrupt remains active until TXRDY flag is cleared. 671 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 38-5. Audio Transfer (PCM L Front, PCM R Front) on Channel x Slot # AC97FS AC97TX (Controller Output) TAG CMD ADDR CMD DATA PCM L Front PCM R Front LINE 1 DAC PCM Center PCM L SURR PCM R SURR PCM LFE LINE 2 DAC HSET DAC IO CTRL 0 1 2 3 4 5 6 7 8 9 10 11 12 TXRDYCx (AC97C_SR) TXEMPTY (AC97C_SR) Write access to AC97C_THRx PCM L Front transfered to the shift register PCM R Front transfered to the shift register The TXEMPTY flag in the AC97 Controller Channel x Status Register (AC97C_CxSR) is set when all requested transmissions for a channel have been shifted on the AC-link. The application can either poll TXEMPTY flag in AC97C_CxSR or wait for an interrupt notice associated with the same flag. In most cases, the AC97 Controller is embedded in chips that target audio player devices. In such cases, the AC97 Controller is exposed to heavy audio transfers. Using the polling technique increases processor overhead and may fail to keep the required pace under an operating system. In order to avoid these polling drawbacks, the application can perform audio streams by using PDC connected to channel A, which reduces processor overhead and increases performance especially under an operating system. The PDC transmit counter values must be equal to the number of PCM samples to be transmitted, each sample goes in one slot. 38.6.2.3 AC97 Output Frame The AC97 Controller outputs a thirteen-slot frame on the AC-Link. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application performs control and status monitoring actions on AC97 Codec control/status registers. Slots [3:12] are used according to the content of the AC97 Controller Output Channel Assignment Register (AC97C_OCA). If the application performs many transmit requests on a channel, some of the slots associated to this channel or all of them will carry valid data. Receive Operation The AC97 Controller can also receive data from AC97 Codec. Data is received in the channel’s shift register and then transferred to the AC97 Controller Channel x Read Holding Register. To read the newly received data, the application must perform the following steps: • Poll RXRDY flag in AC97 Controller Channel x Status Register (AC97C_CxSR). x being one of the 2 channels. • Read data from AC97 Controller Channel x Read Holding Register. 38.6.2.4 672 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 The application can also wait for an interrupt notice in order to read data from AC97C_CxRHR. The interrupt remains active until RXRDY is cleared by reading AC97C_CxSR. The RXRDY flag in AC97C_CxSR is set automatically when data is received in the Channel x shift register. Data is then shifted to AC97C_CxRHR. Figure 38-6. Audio Transfer (PCM L Front, PCM R Front) on Channel x Slot # AC97FS STATUS ADDR STATUS DATA PCM LEFT PCM RIGHT LINE 1 DAC PCM MIC LINE 2 ADC HSET ADC IO STATUS 0 1 2 3 4 5 6 7 8 9 10 11 12 AC97RX (Codec output) RXRDYCx (AC97C_SR) Read access to AC97C_RHRx TAG RSVED RSVED RSVED If the previously received data has not been read by the application, the new data overwrites the data already waiting in AC97C_CxRHR, therefore the OVRUN flag in AC97C_CxSR is raised. The application can either poll the OVRUN flag in AC97C_CxSR or wait for an interrupt notice. The interrupt remains active until the OVRUN flag in AC97C_CxSR is set. The AC97 Controller can also be used in sound recording devices in association with an AC97 Codec. The AC97 Controller may also be exposed to heavy PCM transfers. The application can use the PDC connected to channel A in order to reduce processor overhead and increase performance especially under an operating system. The PDC receive counter values must be equal to the number of PCM samples to be received, each sample goes in one slot. 38.6.2.5 AC97 Input Frame The AC97 Controller receives a thirteen slot frame on the AC-Link sent by the AC97 Codec. The first slot (tag slot or slot 0) flags the validity of the entire frame and the validity of each slot; whether a slot carries valid data or not. Slots 1 and 2 are used if the application requires status informations from AC97 Codec. Slots [3:12] are used according to AC97 Controller Output Channel Assignment Register (AC97C_ICA) content. The AC97 Controller will not receive any data from any slot if AC97C_ICA is not assigned to a channel in input. Configuring and Using Interrupts Instead of polling flags in AC97 Controller Global Status Register (AC97C_SR) and in AC97 Controller Channel x Status Register (AC97C_CxSR), the application can wait for an interrupt notice. The following steps show how to configure and use interrupts correctly: • Set the interruptible flag in AC97 Controller Channel x Mode Register (AC97C_CxMR). • Set the interruptible event and channel event in AC97 Controller Interrupt Enable Register (AC97C_IER). The interrupt handler must read both AC97 Controller Global Status Register (AC97C_SR) and AC97 Controller Interrupt Mask Register (AC97C_IMR) and AND them to get the real interrupt source. Furthermore, to get which event was activated, the interrupt handler has to read AC97 Controller Channel x Status Register (AC97C_CxSR), x being the channel whose event triggers the interrupt. 673 38.6.2.6 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 The application can disable event interrupts by writing in AC97 Controller Interrupt Disable Register (AC97C_IDR). The AC97 Controller Interrupt Mask Register (AC97C_IMR) shows which event can trigger an interrupt and which one cannot. 38.6.2.7 Endianness Endianness can be managed automatically for each channel, except for the Codec channel, by writing to Channel Endianness Mode (CEM) in AC97C_CxMR. This enables transferring data on AC-link in Big Endian format without any additional operation. 38.6.2.8 To Transmit a Word Stored in Big Endian Format on AC-link Word to be written in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (as it is stored in memory or microprocessor register). 24 Byte0[7:0] 23 Byte1[7:0] 16 15 Byte2[7:0] 8 7 Byte3[7:0] 0 31 Word stored in Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit). 31 – 24 23 – 20 19 16 Byte2[3:0] 15 Byte1[7:0] 8 7 Byte0[7:0] 0 Data transmitted on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}. 38.6.2.9 To Transmit A Halfword Stored in Big Indian Format on AC-link Halfw ord to be written in AC97 Controlle r Channel x Transmit Holding Register (AC97C_CxTHR). 24 – 23 – 16 15 Byte0[7:0] 8 7 Byte1[7:0] 0 31 Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit). 31 – 24 23 – 16 15 Byte1[7:0] 8 7 Byte0[7:0] 0 Data emitted on related slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}. 38.6.2.10 To Transmit a10-bit Sample Stored in Big Endian Format on AC-link Halfw ord to be written in AC97 Controlle r Channel x Transmit Holding Register (AC97C_CxTHR). 24 – 23 – 16 15 Byte0[7:0] 8 7 {0x00, Byte1[1:0]} 0 31 Halfword stored in AC97 Controller Channel x Transmit Holding Register (AC97C_CxTHR) (data to transmit). 31 – 24 23 – 16 15 – 10 9 8 Byte1 [1:0] 7 Byte0[7:0] 0 Data emitted on related slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}. 674 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.6.2.11 To Receive Word transfers Data received on appropriate slot: data[19:0] = {Byte2[3:0], Byte1[7:0], Byte0[7:0]}. Word stored in AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data). 31 – 24 23 – 20 19 16 Byte2[3:0] 15 Byte1[7:0] 8 7 Byte0[7:0] 0 Data is read from AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when Channel x data size is greater than 16 bits and when big-endian mode is enabled (data written to memory). 31 Byte0[7:0] 24 23 Byte1[7:0] 16 15 {0x0, Byte2[3:0]} 8 7 0x00 0 38.6.2.12 To Receive Halfword Transfers Data received on appropriate slot: data[19:0] = {0x0, Byte1[7:0], Byte0[7:0]}. Halfword stored in AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data). 31 – 24 23 – 16 15 Byte1[7:0] 8 7 Byte0[7:0] 0 Data is read from AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when data size is equal to 16 bits and when big-endian mode is enabled. 31 – 24 23 – 16 15 Byte0[7:0] 8 7 Byte1[7:0] 0 38.6.2.13 To Receive 10-bit Samples Data received on appropriate slot: data[19:0] = {0x000, Byte1[1:0], Byte0[7:0]}.Halfword stored in AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) (Received Data) 24 – 23 – 16 15 – 10 9 8 Byte1 [1:0] 7 Byte0[7:0] 0 31 Data read from AC97 Controller Channel x Receive Holding Register (AC97C_CxRHR) when data size is equal to 10 bits and when big-endian mode is enabled. 31 – 24 23 – 16 15 Byte0[7:0] 8 7 0x00 3 1 0 Byte1 [1:0] 38.6.3 Variable Sample Rate The problem of variable sample rate can be summarized by a simple example. When passing a 44.1 kHz stream across the AC-link, for every 480 audio output frames that are sent across, 441 of them must contain valid sample data. The new AC97 standard approach calls for the addition of “on-demand” slot request flags. The AC97 Codec examines its sample rate control register, the state of its FIFOs, and the incoming SDATA_OUT tag bits (slot 0) of each output frame and then determines which SLOTREQ bits to set active (low). These bits are passed from the AC97 Codec to the AC97 Controller in slot 1/SLOTREQ in every audio input frame. Each time the 675 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AC97 controller sees one or more of the newly defined slot request flags set active (low) in a given audio input frame, it must pass along the next PCM sample for the corresponding slot(s) in the AC-link output frame that immediately follows. The variable Sample Rate mode is enabled by performing the following steps: • Setting the VRA bit in the AC97 Controller Mode Register (AC97C_MR). • Enable Variable Rate mode in the AC97 Codec by performing a transfer on the Codec channel. Slot 1 of the input frame is automatically interpreted as SLOTREQ signaling bits. The AC97 Controller will automatically fill the active slots according to both SLOTREQ and AC97C_OCA register in the next transmitted frame. 38.6.4 38.6.4.1 Power Management Powering Down the AC-Link The AC97 Codecs can be placed in low power mode. The application can bring AC97 Codec to a power down state by performing sequential writes to AC97 Codec powerdown register. Both the bit clock (clock delivered by AC97 Codec, AC97CK) and the input line (AC97RX) are held at a logic low voltage level. This puts AC97 Codec in power down state while all its registers are still holding current values. Without the bit clock, the AC-link is completely in a power down state. The AC97 Controller should not attempt to play or capture audio data until it has awakened AC97 Codec. To set the AC97 Codec in low power mode, the PR4 bit in the AC97 Codec powerdown register (Codec address 0x26) must be set to 1. Then the primary Codec drives both AC97CK and AC97RX to a low logic voltage level. The following operations must be done to put AC97 Codec in low power mode: • Disable Channel A clearing CEN field in the AC97C_CAMR register. • Write 0x2680 value in the AC97C_COTHR register. • Poll the TXEMPTY flag in AC97C_CxSR registers for the 2 channels. At this point AC97 Codec is in low power mode. 38.6.4.2 Waking up the AC-link There are two methods to bring the AC-link out of low power mode. Regardless of the method, it is always the AC97 Controller that performs the wake-up. Wake-up Triggered by the AC97 Controller The AC97 Controller can wake up the AC97 Codec by issuing either a cold or a warm reset. The AC97 Controller can also wake up the AC97 Codec by asserting AC97FS signal, however this action should not be performed for a minimum period of four audio frames following the frame in which the powerdown was issued. 38.6.4.4 Wake-up Triggered by the AC97 Codec This feature is implemented in AC97 modem codecs that need to report events such as CallerID and wake-up on ring. 38.6.4.3 676 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 The AC97 Codec can drive AC97RX signal from low to high level and holding it high until the controller issues either a cold or a worm reset. The AC97RX rising edge is asynchronously (regarding AC97FS) detected by the AC97 Controller. If WKUP bit is enabled in AC97C_IMR register, an interrupt is triggered that wakes up the AC97 Controller which should then immediately issue a cold or a warm reset. If the processor needs to be awakened by an external event, the AC97RX signal must be externally connected to the WAKEUP entry of the system controller. Figure 38-7. AC97 Power-Down/Up Sequence Wake Event Power Down Frame AC97CK Sleep State Warm Reset New Audio Frame AC97FS AC97TX TAG Write to 0x26 Data PR4 TAG Slot1 Slot2 AC97RX TAG Write to 0x26 Data PR4 TAG Slot1 Slot2 38.6.4.5 AC97 Codec Reset There are three ways to reset an AC97 Codec. Cold AC97 Reset A cold reset is generated by asserting the RESET signal low for the minimum specified time (depending on the AC97 Codec) and then by de-asserting RESET high. AC97CK and AC97FS is reactivated and all AC97 Codec registers are set to their default power-on values. Transfers on AC-link can resume. The RESET signal will be controlled via a PIO line. This is how an application should perform a cold reset: • Clear and set ENA flag in the AC97C_MR register to reset the AC97 Controller • Clear PIO line output controlling the AC97 RESET signal • Wait for the minimum specified time • Set PIO line output controlling the AC97 RESET signal AC97CK, the clock provided by AC97 Codec, is detected by the controller. 38.6.4.6 38.6.4.7 Warm AC97 Reset A warm reset reactivates the AC-link without altering AC97 Codec registers. A warm reset is signaled by driving AC97FX signal high for a minimum of 1us in the absence of AC97CK. In the absence of AC97CK, AC97FX is treated as an asynchronous (regarding AC97FX) input used to signal a warm reset to AC97 Codec. This is the right way to perform a warm reset: • Set WRST in the AC97C_MR register. • Wait for at least 1us • Clear WRST in the AC97C_MR register. 677 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 The application can check that operations have resumed by checking SOF flag in the AC97C_SR register or wait for an interrupt notice if SOF is enabled in AC97C_IMR. 678 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7 AC97 Controller (AC97C) User Interface Register Mapping Register Reserved Mode Register Reserved Input Channel Assignment Register Output Channel Assignment Register Reserved Channel A Receive Holding Register Channel A Transmit Holding Register Channel A Status Register Channel A Mode Register Codec Channel Receive Holding Register Codec Channel Transmit Holding Register Codec Status Register Codec Mode Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral DMA Controller (PDC) registers related to channel transfers Name – AC97C_MR – AC97C_ICA AC97C_OCA – AC97C_CARHR AC97C_CATHR AC97C_CASR AC97C_CAMR AC97C_CORHR AC97C_COTHR AC97C_COSR AC97C_COMR AC97C_SR AC97C_IER AC97C_IDR AC97C_IMR – – Access – Read-write – Read-write Read-write – Read Write Read Read-write Read Write Read Read-write Read Write Write Read – – Reset – 0x0 – 0x0 0x0 – 0x0 – 0x0 0x0 0x0 – 0x0 0x0 0x0 – – 0x0 – – Table 38-6. Offset 0x0-0x4 0x8 0xC 0x10 0x14 0x18-0x1C 0x20 0x24 0x28 0x2C 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60-0xFB 0x100-0x124 679 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.1 Name: Address: Access: 31 – 23 – 15 – 7 – AC97 Controller Mode Register AC97C_MR 0xFFFA0008 Read-Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 VRA 25 – 17 – 9 – 1 WRST 24 – 16 – 8 – 0 ENA • VRA: Variable Rate (for Data Slots 3-12) 0: Variable Rate is inactive. (48 KHz only) 1: Variable Rate is active. • WRST: Warm Reset 0: Warm Reset is inactive. 1: Warm Reset is active. • ENA: AC97 Controller Global Enable 0: No effect. AC97 function as well as access to other AC97 Controller registers are disabled. 1: Activates the AC97 function. 680 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.2 Name: Address: Access: 31 – 23 AC97 Controller Input Channel Assignment Register AC97C_ICA 0xFFFA0010 Read-write 30 – 22 CHID10 14 6 CHID5 29 21 13 CHID7 5 28 CHID12 20 12 4 CHID4 27 19 CHID9 11 3 26 18 10 CHID6 2 25 CHID11 17 CHID8 9 1 CHID3 8 CHID5 0 24 16 15 CHID8 7 • CHIDx: Channel ID CHIDx 0x0 0x1 for the input slot x Selected Receive Channel None. No data will be received during this slot time Channel A data will be received during this slot time. 681 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.3 Name: Address: Access: 31 – 23 AC97 Controller Output Channel Assignment Register AC97C_OCA 0xFFFA0014 Read-write 30 – 22 CHID10 14 6 CHID5 29 21 13 CHID7 5 28 CHID12 20 12 4 CHID4 27 19 CHID9 11 3 26 18 10 CHID6 2 25 CHID11 17 CHID8 9 1 CHID3 8 CHID5 0 24 16 15 CHID8 7 • CHIDx: Channel ID CHIDx 0x0 0x1 for the output slot x Selected Transmit Channel None. No data will be transmitted during this slot time Channel A data will be transferred during this slot time. 682 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.4 Name: Address: Access: 31 – 23 – 15 7 AC97 Controller Codec Channel Receive Holding Register AC97C_CORHR 0xFFFA0040 Read-only 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 SDATA 4 SDATA 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 • SDATA: Status Data Data sent by the CODEC in the third AC97 input frame slot (Slot 2). 683 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.5 Name: Address: Access: 31 – 23 READ 15 7 AC97 Controller Codec Channel Transmit Holding Register AC97C_COTHR 0xFFFA0044 Write-only 30 – 22 14 6 29 – 21 13 5 28 – 20 12 CDATA 4 CDATA 3 2 1 0 27 – 19 CADDR 11 26 – 18 10 25 – 17 9 24 – 16 8 • READ: Read-write command 0: Write operation to the CODEC register indexed by the CADDR address. 1: Read operation to the CODEC register indexed by the CADDR address. This flag is sent during the second AC97 frame slot • CADDR: CODEC control register index Data sent to the CODEC in the second AC97 frame slot. • CDATA: Command Data Data sent to the CODEC in the third AC97 frame slot (Slot 2). 684 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.6 Name: Address: Access: 31 – 23 – 15 7 AC97 Controller Channel A, Receive Holding Register AC97C_CARHR 0xFFFA0020 Read-only 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 RDATA 4 RDATA 3 2 1 0 27 – 19 11 26 – 18 RDATA 10 9 8 25 – 17 24 – 16 • RDATA: Receive Data Received Data on channel x. 685 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.7 Name: Address: Access: 31 – 23 – 15 7 AC97 Controller Channel A, Transmit Holding Register AC97C_CATHR 0xFFFA0024 Write-only 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 TDATA 4 TDATA 3 2 1 0 27 – 19 11 26 – 18 TDATA 10 9 8 25 – 17 24 – 16 • TDATA: Transmit Data Data to be sent on channel x. 686 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.8 Name: Address: Access: AC97 Controller Channel A Status Register AC97C_CASR 0xFFFA0028 Read-only 30 – 22 – 14 ENDRX 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 TXBUFE 3 – 26 – 18 – 10 ENDTX 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY 31 – 23 – 15 RXBUFF 7 – • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty. • TXEMPTY: Channel Transmit Empty 0: Data remains in the Channel Transmit Register or is currently transmitted from the Channel Transmit Shift Register. 1: Data in the Channel Transmit Register have been loaded in the Channel Transmit Shift Register and sent to the codec. • UNRUN: Transmit Underrun Active only when Variable Rate Mode is enabled (VRA bit set in the AC97C_MR register). Automatically cleared by a processor read operation. 0: No data has been requested from the channel since the last read of the Status Register, or data has been available each time the CODEC requested new data from the channel since the last read of the Status Register. 1: Data has been emitted while no valid data to send has been previously loaded into the Channel Transmit Shift Register since the last read of the Status Register. • RXRDY: Channel Receive Ready 0: Channel Receive Holding Register is empty. 1: Data has been received and loaded in Channel Receive Holding Register. • OVRUN: Receive Overrun Automatically cleared by a processor read operation. 0: No data has been loaded in the Channel Receive Holding Register while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in the Channel Receive Holding Register while previous data has not yet been read since the last read of the Status Register. • ENDTX: End of Transmission for Channel A 0: The register AC97C_CATCR has not reached 0 since the last write in AC97C_CATCR or AC97C_CANCR. 1: The register AC97C_CATCR has reached 0 since the last write in AC97C_CATCR or AC97C_CATNCR. 687 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 • TXBUFE: Transmit Buffer Empty for Channel A 0: AC97C_CATCR or AC97C_CATNCR have a value other than 0. 1: Both AC97C_CATCR and AC97C_CATNCR have a value of 0. • ENDRX: End of Reception for Channel A 0: The register AC97C_CARCR has not reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR. 1: The register AC97C_CARCR has reached 0 since the last write in AC97C_CARCR or AC97C_CARNCR. • RXBUFF: Receive Buffer Full for Channel A 0: AC97C_CARCR or AC97C_CARNCR have a value other than 0. 1: Both AC97C_CARCR and AC97C_CARNCR have a value of 0. 688 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.9 Name: Address: Access: 31 – 23 – 15 – 7 – AC97 Controller Codec Status Register AC97C_COSR 0xFFFA0048 Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready 0: Data has been loaded in Channel Transmit Register and is waiting to be loaded in the Channel Transmit Shift Register. 1: Channel Transmit Register is empty. • TXEMPTY: Channel Transmit Empty 0: Data remains in the Channel Transmit Register or is currently transmitted from the Channel Transmit Shift Register. 1: Data in the Channel Transmit Register have been loaded in the Channel Transmit Shift Register and sent to the codec. • UNRUN: Transmit Underrun Active only when Variable Rate Mode is enabled (VRA bit set in the AC97C_MR register). Automatically cleared by a processor read operation. 0: No data has been requested from the channel since the last read of the Status Register, or data has been available each time the CODEC requested new data from the channel since the last read of the Status Register. 1: Data has been emitted while no valid data to send has been previously loaded into the Channel Transmit Shift Register since the last read of the Status Register. • RXRDY: Channel Receive Ready 0: Channel Receive Holding Register is empty. 1: Data has been received and loaded in Channel Receive Holding Register. • OVRUN: Receive Overrun Automatically cleared by a processor read operation. 0: No data has been loaded in the Channel Receive Holding Register while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in the Channel Receive Holding Register while previous data has not yet been read since the last read of the Status Register. 689 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.10 Name: Address: Access: AC97 Controller Channel A Mode Register AC97C_CAMR 0xFFFA002C Read-write 30 – 22 PDCEN 14 ENDRX 6 – 29 – 21 CEN 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 TXBUFE 3 – 26 – 18 CEM 10 ENDTX 2 UNRUN 25 – 17 SIZE 9 – 1 TXEMPTY 8 – 0 TXRDY 24 – 16 31 – 23 – 15 RXBUFF 7 – • TXRDY: Channel Transmit Ready Interrupt Enable • TXEMPTY: Channel Transmit Empty Interrupt Enable • UNRUN: Transmit Underrun Interrupt Enable • RXRDY: Channel Receive Ready Interrupt Enable • OVRUN: Receive Overrun Interrupt Enable • ENDTX: End of Transmission for Channel A Interrupt Enable • TXBUFE: Transmit Buffer Empty for Channel A Interrupt Enable 0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt. 1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt. • ENDRX: End of Reception for Channel A Interrupt Enable 0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt. 1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt. • RXBUFF: Receive Buffer Full for Channel A Interrupt Enable 0: Read: the corresponding interrupt is disabled. Write: disables the corresponding interrupt. 1: Read: the corresponding interrupt is enabled. Write: enables the corresponding interrupt. • SIZE: Channel A Data Size SIZE Encoding SIZE 0x0 0x1 0x2 0x3 Note: Selected Data Size 20 bits 18 bits 16 bits 10 bits Each time slot in the data phase is 20 bit long. For example, if a 16-bit sample stream is being played to an AC 97 DAC, the first 16 bit positions are presented to the DAC MSB-justified. They are followed by the next four bit positions that the AC97 Controller 690 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 fills with zeroes. This process ensures that the least significant bits do not introduce any DC biasing, regardless of the implemented DAC’s resolution (16-, 18-, or 20-bit) • CEM: Channel A Endian Mode 0: Transferring Data through Channel A is straight forward (Little-Endian). 1: Transferring Data through Channel A from/to a memory is performed with from/to Big-Endian format translation. • CEN: Channel A Enable 0: Data transfer is disabled on Channel A. 1: Data transfer is enabled on Channel A. • PDCEN: Peripheral Data Controller Channel Enable 0: Channel A is not transferred through a Peripheral Data Controller Channel. Related PDC flags are ignored or not generated. 1: Channel A is transferred through a Peripheral Data Controller Channel. Related PDC flags are taken into account or generated. 691 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.11 Name: Address: Access: 31 – 23 – 15 – 7 – AC97 Controller Codec Mode Register AC97C_COMR 0xFFFA004C Read-write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 UNRUN 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY • TXRDY: Channel Transmit Ready Interrupt Enable • TXEMPTY: Channel Transmit Empty Interrupt Enable • UNRUN: Transmit Underrun Interrupt Enable • RXRDY: Channel Receive Ready Interrupt Enable • OVRUN: Receive Overrun Interrupt Enable 692 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.12 Name: Address: Access: 31 – 23 – 15 – 7 – AC97 Controller Status Register AC97C_SR 0xFFFA0050 Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF WKUP and SOF flags in AC97C_SR register are automatically cleared by a processor read operation. • SOF: Start Of Frame 0: No Start of Frame has been detected since the last read of the Status Register. 1: At least one Start of frame has been detected since the last read of the Status Register. • WKUP: Wake Up detection 0: No Wake-up has been detected. 1: At least one rising edge on SDATA_IN has been asynchronously detected. That means AC97 Codec has notified a wake-up. • COEVT: CODEC Channel Event A Codec channel event occurs when AC97C_COSR AND AC97C_COMR is not 0. COEVT flag is automatically cleared when the channel event condition is cleared. 0: No event on the CODEC channel has been detected since the last read of the Status Register. 1: At least one event on the CODEC channel is active. • CAEVT: Channel A Event A channel A event occurs when AC97C_CASR AND AC97C_CAMR is not 0. CAEVT flag is automatically cleared when the channel event condition is cleared. 0: No event on the channel A has been detected since the last read of the Status Register. 1: At least one event on the channel A is active. 693 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.13 Name: Address: Access: 31 – 23 – 15 – 7 – AC97 Codec Controller Interrupt Enable Register AC97C_IER 0xFFFA0054 Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event 0: No Effect. 1: Enables the corresponding interrupt. 694 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.14 Name: Address: Access: 31 – 23 – 15 – 7 – AC97 Controller Interrupt Disable Register AC97C_IDR 0xFFFA0058 Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event 0: No Effect. 1: Disables the corresponding interrupt. 695 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 38.7.15 Name: Address: Access: 31 – 23 – 15 – 7 – AC97 Controller Interrupt Mask Register AC97C_IMR 0xFFFA005C Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CAEVT 26 – 18 – 10 – 2 COEVT 25 – 17 – 9 – 1 WKUP 24 – 16 – 8 – 0 SOF • SOF: Start Of Frame • WKUP: Wake Up • COEVT: Codec Event • CAEVT: Channel A Event 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. 696 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 39. Timer Counter (TC) 39.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 39-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2. Table 39-1. Name Timer Counter Clock Assignment Definition MCK/2 MCK/8 MCK/32 MCK/128 SLCK TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5(1) Note: 1. When Slow Clock is selected for Master Clock (CSS = 0 in PMC Master CLock Register), TIMER_CLOCK5 input is Master Clock, i.e., Slow CLock modified by PRES and MDIV fields. 697 6264C–CAP–24-Mar-09 39.2 Block Diagram Figure 39-1. Timer Counter Block Diagram Parallel I/O Controller TCLK0 TIMER_CLOCK2 TIMER_CLOCK1 TIOA1 TIMER_CLOCK3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA2 TCLK1 XC0 XC1 XC2 TC0XC0S Timer/Counter Channel 0 TIOA TIOA0 TIOB TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOB0 SYNC INT0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC Timer/Counter Channel 1 TIOA TIOA1 TIOB TIOB1 INT1 TIOA1 TIOB1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB TIOB2 SYNC TIOA2 TIOB2 INT2 Timer Counter Advanced Interrupt Controller Table 39-2. Signal Name Description Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal Block/Channel Channel Signal TIOB INT SYNC 698 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.3 Pin Name List Table 39-3. Pin Name TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2 TC pin list Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O 39.4 39.4.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 39-4. I/O Lines Signal TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 I/O Line PB28 PC28 PA14 PA29 PB6 PB21 PA30 PB7 PB22 Peripheral B B A A B B A B B Instance TC0 TC0 TC0 TC0 TC0 TC0 TC0 TC0 TC0 39.4.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. 39.4.3 699 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.5 39.5.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 39-5 on page 713. 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 39.5.2 39.5.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 39-2 on page 701. Each channel can independently select an internal or external clock source for its counter: • • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 39-3 on page 701 Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock 700 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 39-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TIOA1 TIOA2 XC0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 TIOA0 TCLK0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 TIOA0 TIOA2 XC0 = TCLK2 XC1 XC2 = TCLK2 TIOB1 TIOA1 SYNC TC2XC2S Timer/Counter Channel 2 XC0 = TCLK0 TIOA2 TCLK2 TIOA0 TIOA1 XC1 = TCLK1 XC2 TIOB2 SYNC Figure 39-3. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 701 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.5.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 39-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. • Figure 39-4. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 39.5.5 TC Operating Modes Each channel can independently operate in two different modes: • • Capture Mode provides measurement on signals. Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 39.5.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. 702 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. The following triggers are common to both modes: • • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. • The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. 39.5.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 39-5 shows the configuration of the TC channel when programmed in Capture Mode. 39.5.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 39.5.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. 703 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 704 TCCLKS CLKI CLKSTA CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 Q Q R S R S Figure 39-5. Capture Mode TIMER_CLOCK5 XC0 XC1 LDBSTOP BURST LDBDIS XC2 Register C 1 16-bit Counter CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LDRA LDRB CPCTRG Capture Register A SWTRG Capture Register B Compare RC = AT91CAP9S500A/AT91CAP9S250A CPCS LOVRS LDRAS LDRBS ETRGS COVFS TC1_SR SYNC MTIOB TIOB MTIOA If RA is not loaded or RB is Loaded Edge Detector If RA is Loaded Edge Detector TC1_IMR TIOA Timer/Counter Channel 6264C–CAP–24-Mar-09 INT 39.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 39-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 39.5.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 705 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 BURST Register A WAVSEL Register B Register C ASWTRG Compare RA = Compare RB = Compare RC = 1 16-bit Counter CLK RESET OVF SWTRG BCPC Trig BCPB WAVSEL EEVT BEEVT EEVTEDG ENETRG Edge Detector CPCS CPAS CPBS ETRGS COVFS TC1_SR MTIOB SYNC Output Controller TIOB TC1_IMR BSWTRG Timer/Counter Channel INT Output Controller 706 TCCLKS CLKSTA ACPC CLKI CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 Figure 39-6. Waveform Mode TIMER_CLOCK3 TIMER_CLOCK4 CPCDIS Q Q R CPCSTOP AEEVT S R ACPA MTIOA TIMER_CLOCK5 S XC0 XC1 XC2 TIOA AT91CAP9S500A/AT91CAP9S250A TIOB 6264C–CAP–24-Mar-09 39.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 39-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 39-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 39-7. WAVSEL= 00 without trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 707 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 39-8. WAVSEL= 00 with trigger Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 39.5.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 39-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 39-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 39-9. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 708 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 39-10. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 39.5.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 39-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 39-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 709 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 39-11. WAVSEL = 01 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 39-12. WAVSEL = 01 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 39.5.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 39-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 39-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 710 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 Figure 39-13. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 39-14. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 711 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.5.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 39.5.13 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 712 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6 Timer Counter (TC) User Interface Register Mapping Offset(1) Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Block Control Register Block Mode Register Reserved TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR TC_BCR TC_BMR – Read-only Read-write Read-write (2) (2) Table 39-5. Name TC_CCR TC_CMR Access Write-only Read-write Reset – 0 0x00 + channel * 0x40 + 0x00 0x00 + channel * 0x40 + 0x04 0x00 + channel * 0x40 + 0x08 0x00 + channel * 0x40 + 0x0C 0x00 + channel * 0x40 + 0x10 0x00 + channel * 0x40 + 0x14 0x00 + channel * 0x40 + 0x18 0x00 + channel * 0x40 + 0x1C 0x00 + channel * 0x40 + 0x20 0x00 + channel * 0x40 + 0x24 0x00 + channel * 0x40 + 0x28 0x00 + channel * 0x40 + 0x2C 0xC0 0xC4 0xFC Notes: 2. Read-only if WAVE = 0 0 0 0 0 0 – – 0 – 0 – Read-write Read-only Write-only Write-only Read-only Write-only Read-write – 1. Channel index ranges from 0 to 2. 713 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.1 Name: Address: Access: 31 – 23 – 15 – 7 – TC Block Control Register TC_BCR 0xFFF7C0C0 Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 714 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.2 Name: Address: Access: 31 – 23 – 15 – 7 – TC Block Mode Register TC_BMR 0xFFF7C0C4 Read-write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 TC2XC2S 28 – 20 – 12 – 4 27 – 19 – 11 – 3 TC1XC1S 26 – 18 – 10 – 2 25 – 17 – 9 – 1 TC0XC0S 24 – 16 – 8 – 0 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 715 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.3 Name: TC Channel Control Register TC_CCRx [x=0..2] Addresses: 0xFFF7C000 (0)[0], 0xFFF7C040 (0)[1], 0xFFF7C080 (0)[2] Access: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SWTRG 25 – 17 – 9 – 1 CLKDIS 24 – 16 – 8 – 0 CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. • SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started. 716 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.4 Name: TC Channel Mode Register: Capture Mode TC_CMRx [x=0..2] (WAVE = 0) Addresses: 0xFFF7C004 (0)[0], 0xFFF7C044 (0)[1], 0xFFF7C084 (0)[2] Access: 31 – 23 – 15 WAVE 7 LDBDIS Read-write 30 – 22 – 14 CPCTRG 6 LDBSTOP 29 – 21 – 13 – 5 BURST 28 – 20 – 12 – 4 11 – 3 CLKI 27 – 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 – 18 25 – 17 LDRA 8 24 – 16 • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. 717 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 • LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • LDRB: RB Loading Selection LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA 718 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.5 Name: TC Channel Mode Register: Waveform Mode TC_CMRx [x=0..2] (WAVE = 1) Addresses: 0xFFF7C004 (0)[0], 0xFFF7C044 (0)[1], 0xFFF7C084 (0)[2] Access: 31 BSWTRG 23 ASWTRG 15 WAVE 7 CPCDIS 6 CPCSTOP 14 WAVSEL 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS Read-write 30 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24 • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. 719 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 • CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • EEVT: External Event Selection EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input (1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. • WAVSEL: Waveform Selection WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare • WAVE 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. 720 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 • ACPA: RA Compare Effect on TIOA ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle • ACPC: RC Compare Effect on TIOA ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle • AEEVT: External Event Effect on TIOA AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle • BCPB: RB Compare Effect on TIOB BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle 721 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 • BCPC: RC Compare Effect on TIOB BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle • BEEVT: External Event Effect on TIOB BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle 722 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.6 Name: TC Counter Value Register TC_CVx [x=0..2] Addresses: 0xFFF7C010 (0)[0], 0xFFF7C050 (0)[1], 0xFFF7C090 (0)[2] Access: 31 – 23 – 15 Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CV 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 CV 3 2 1 0 • CV: Counter Value CV contains the counter value in real time. 723 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.7 Name: TC Register A TC_RAx [x=0..2] Addresses: 0xFFF7C014 (0)[0], 0xFFF7C054 (0)[1], 0xFFF7C094 (0)[2] Access: 31 – 23 – 15 Read-only if WAVE = 0, Read-write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RA 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RA 3 2 1 0 • RA: Register A RA contains the Register A value in real time. 39.6.8 Name: TC Register B TC_RBx [x=0..2] Addresses: 0xFFF7C018 (0)[0], 0xFFF7C058 (0)[1], 0xFFF7C098 (0)[2] Access: 31 – 23 – 15 Read-only if WAVE = 0, Read-write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RB 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RB 3 2 1 0 • RB: Register B RB contains the Register B value in real time. 724 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.9 Name: TC Register C TC_RCx [x=0..2] Addresses: 0xFFF7C01C (0)[0], 0xFFF7C05C (0)[1], 0xFFF7C09C (0)[2] Access: 31 – 23 – 15 Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RC 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RC 3 2 1 0 • RC: Register C RC contains the Register C value in real time. 725 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.10 Name: TC Status Register TC_SRx [x=0..2] Addresses: 0xFFF7C020 (0)[0], 0xFFF7C060 (0)[1], 0xFFF7C0A0 (0)[2] Access: 31 – 23 – 15 – 7 ETRGS Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 MTIOB 10 – 2 CPAS 25 – 17 MTIOA 9 – 1 LOVRS 24 – 16 CLKSTA 8 – 0 COVFS • COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. • CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. • LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. 726 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 • CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 727 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.11 Name: TC Interrupt Enable Register TC_IERx [x=0..2] Addresses: 0xFFF7C024 (0)[0], 0xFFF7C064 (0)[1], 0xFFF7C0A4 (0)[2] Access: 31 – 23 – 15 – 7 ETRGS Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. • CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. • CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. • CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. • LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. • ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 728 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.12 Name: TC Interrupt Disable Register TC_IDRx [x=0..2] Addresses: 0xFFF7C028 (0)[0], 0xFFF7C068 (0)[1], 0xFFF7C0A8 (0)[2] Access: 31 – 23 – 15 – 7 ETRGS Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). • CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). • CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). • CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). • ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. 729 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 39.6.13 Name: TC Interrupt Mask Register TC_IMRx [x=0..2] Addresses: 0xFFF7C02C (0)[0], 0xFFF7C06C (0)[1], 0xFFF7C0AC (0)[2] Access: 31 – 23 – 15 – 7 ETRGS Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. • CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. • CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. • CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. • LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. • LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. • ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 730 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40. Controller Area Network (CAN) 40.1 Overview The CAN controller provides all the features required to implement the serial communication protocol CAN defined by Robert Bosch GmbH, the CAN specification as referred to by ISO/11898A (2.0 Part A and 2.0 Part B) for high speeds and ISO/11519-2 for low speeds. The CAN Controller is able to handle all types of frames (Data, Remote, Error and Overload) and achieves a bitrate of 1 Mbit/sec. CAN controller accesses are made through configuration registers. 16 independent message objects (mailboxes) are implemented. Any mailbox can be programmed as a reception buffer block (even non-consecutive buffers). For the reception of defined messages, one or several message objects can be masked without participating in the buffer feature. An interrupt is generated when the buffer is full. According to the mailbox configuration, the first message received can be locked in the CAN controller registers until the application acknowledges it, or this message can be discarded by new received messages. Any mailbox can be programmed for transmission. Several transmission mailboxes can be enabled in the same time. A priority can be defined for each mailbox independently. An internal 16-bit timer is used to stamp each received and sent message. This timer starts counting as soon as the CAN controller is enabled. This counter can be reset by the application or automatically after a reception in the last mailbox in Time Triggered Mode. The CAN controller offers optimized features to support the Time Triggered Communication (TTC) protocol. 731 6264C–CAP–24-Mar-09 40.2 Block Diagram Figure 40-1. CAN Block Diagram Controller Area Network CANRX CAN Protocol Controller PIO CANTX Error Counter Mailbox Priority Encoder Control & Status MB0 MB1 MCK PMC MBx (x = number of mailboxes - 1) CAN Interrupt User Interface Internal Bus 40.3 Application Block Diagram Figure 40-2. Application Block Diagram Layers CAN-based Profiles CAN-based Application Layer CAN Data Link Layer CAN Physical Layer Implementation Software Software CAN Controller Transceiver 732 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.4 I/O Lines Description I/O Lines Description Description CAN Receive Serial Data CAN Transmit Serial Data Type Input Output Table 40-1. Name CANRX CANTX 40.5 40.5.1 Product Dependencies I/O Lines The pins used for interfacing the CAN may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired CAN pins to their peripheral function. If I/O lines of the CAN are not used by the application, they can be used for other purposes by the PIO Controller. Table 40-2. I/O Lines Signal CANRX CANTX I/O Line PA13 PA12 Peripheral A A Instance CAN CAN 40.5.2 Power Management The programmer must first enable the CAN clock in the Power Management Controller (PMC) before using the CAN. A Low-power Mode is defined for the CAN controller: If the application does not require CAN operations, the CAN clock can be stopped when not needed and be restarted later. Before stopping the clock, the CAN Controller must be in Low-power Mode to complete the current transfer. After restarting the clock, the application must disable the Low-power Mode of the CAN controller. 40.5.3 Interrupt The CAN interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the CAN interrupt requires the AIC to be programmed first. Note that it is not recommended to use the CAN interrupt line in edge-sensitive mode. Table 40-3. Instance CAN Peripheral IDs ID 13 733 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.6 40.6.1 CAN Controller Features CAN Protocol Overview The Controller Area Network (CAN) is a multi-master serial communication protocol that efficiently supports real-time control with a very high level of security with bit rates up to 1 Mbit/s. The CAN protocol supports four different frame types: • Data frames: They carry data from a transmitter node to the receiver nodes. The overall maximum data frame length is 108 bits for a standard frame and 128 bits for an extended frame. • Remote frames: A destination node can request data from the source by sending a remote frame with an identifier that matches the identifier of the required data frame. The appropriate data source node then sends a data frame as a response to this node request. • Error frames: An error frame is generated by any node that detects a bus error. • Overload frames: They provide an extra delay between the preceding and the successive data frames or remote frames. The Atmel CAN controller provides the CPU with full functionality of the CAN protocol V2.0 Part A and V2.0 Part B. It minimizes the CPU load in communication overhead. The Data Link Layer and part of the physical layer are automatically handled by the CAN controller itself. The CPU reads or writes data or messages via the CAN controller mailboxes. An identifier is assigned to each mailbox. The CAN controller encapsulates or decodes data messages to build or to decode bus data frames. Remote frames, error frames and overload frames are automatically handled by the CAN controller under supervision of the software application. 40.6.2 Mailbox Organization The CAN module has 16 buffers, also called channels or mailboxes. An identifier that corresponds to the CAN identifier is defined for each active mailbox. Message identifiers can match the standard frame identifier or the extended frame identifier. This identifier is defined for the first time during the CAN initialization, but can be dynamically reconfigured later so that the mailbox can handle a new message family. Several mailboxes can be configured with the same ID. Each mailbox can be configured in receive or in transmit mode independently. The mailbox object type is defined in the MOT field of the CAN_MMRx register. 40.6.2.1 Message Acceptance Procedure If the MIDE field in the CAN_MIDx register is set, the mailbox can handle the extended format identifier; otherwise, the mailbox handles the standard format identifier. Once a new message is received, its ID is masked with the CAN_MAMx value and compared with the CAN_MIDx value. If accepted, the message ID is copied to the CAN_MIDx register. 734 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 40-3. Message Acceptance Procedure CAN_MIDx CAN_MAMx Message Received & & == Yes Message Accepted No Message Refused CAN_MFIDx If a mailbox is dedicated to receiving several messages (a family of messages) with different IDs, the acceptance mask defined in the CAN_MAMx register must mask the variable part of the ID family. Once a message is received, the application must decode the masked bits in the CAN_MIDx. To speed up the decoding, masked bits are grouped in the family ID register (CAN_MFIDx). For example, if the following message IDs are handled by the same mailbox: ID0 101000100100010010000100 0 11 00b ID1 101000100100010010000100 0 11 01b ID2 101000100100010010000100 0 11 10b ID3 101000100100010010000100 0 11 11b ID4 101000100100010010000100 1 11 00b ID5 101000100100010010000100 1 11 01b ID6 101000100100010010000100 1 11 10b ID7 101000100100010010000100 1 11 11b The CAN_MIDx and CAN_MAMx of Mailbox x must be initialized to the corresponding values: CAN_MIDx = 001 101000100100010010000100 x 11 xxb CAN_MAMx = 001 111111111111111111111111 0 11 00b If Mailbox x receives a message with ID6, then CAN_MIDx and CAN_MFIDx are set: CAN_MIDx = 001 101000100100010010000100 1 11 10b CAN_MFIDx = 00000000000000000000000000000110b If the application associates a handler for each message ID, it may define an array of pointers to functions: void (*pHandler[8])(void); When a message is received, the corresponding handler can be invoked using CAN_MFIDx register and there is no need to check masked bits: unsigned int MFID0_register; MFID0_register = Get_CAN_MFID0_Register(); // Get_CAN_MFID0_Register() returns the value of the CAN_MFID0 register pHandler[MFID0_register](); 735 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.6.2.2 Receive Mailbox When the CAN module receives a message, it looks for the first available mailbox with the lowest number and compares the received message ID with the mailbox ID. If such a mailbox is found, then the message is stored in its data registers. Depending on the configuration, the mailbox is disabled as long as the message has not been acknowledged by the application (Receive only), or, if new messages with the same ID are received, then they overwrite the previous ones (Receive with overwrite). It is also possible to configure a mailbox in Consumer Mode. In this mode, after each transfer request, a remote frame is automatically sent. The first answer received is stored in the corresponding mailbox data registers. Several mailboxes can be chained to receive a buffer. They must be configured with the same ID in Receive Mode, except for the last one, which can be configured in Receive with Overwrite Mode. The last mailbox can be used to detect a buffer overflow. Mailbox Object Type Receive Description The first message received is stored in mailbox data registers. Data remain available until the next transfer request. The last message received is stored in mailbox data register. The next message always overwrites the previous one. The application has to check whether a new message has not overwritten the current one while reading the data registers. A remote frame is sent by the mailbox. The answer received is stored in mailbox data register. This extends Receive mailbox features. Data remain available until the next transfer request. Receive with overwrite Consumer 40.6.2.3 Transmit Mailbox When transmitting a message, the message length and data are written to the transmit mailbox with the correct identifier. For each transmit mailbox, a priority is assigned. The controller automatically sends the message with the highest priority first (set with the field PRIOR in CAN_MMRx register). It is also possible to configure a mailbox in Producer Mode. In this mode, when a remote frame is received, the mailbox data are sent automatically. By enabling this mode, a producer can be done using only one mailbox instead of two: one to detect the remote frame and one to send the answer. Mailbox Object Type Transmit Description The message stored in the mailbox data registers will try to win the bus arbitration immediately or later according to or not the Time Management Unit configuration (see Section 40.6.3). The application is notified that the message has been sent or aborted. The message prepared in the mailbox data registers will be sent after receiving the next remote frame. This extends transmit mailbox features. Producer 736 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.6.3 Time Management Unit The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR register). It is automatically cleared in the following cases: • after a reset • when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and SLEEP bit set in the CAN_SR) • after a reset of the CAN controller (CANEN bit in the CAN_MR register) • in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the MRDY signal in the CAN_MSRlast_mailbox_number register). The application can also reset the internal timer by setting TIMRST in the CAN_TCR register. The current value of the internal timer is always accessible by reading the CAN_TIM register. When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR register is set. TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated while TOVF is set. In a CAN network, some CAN devices may have a larger counter. In this case, the application can also decide to freeze the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device. This feature is enabled by setting TIMFRZ in the CAN_MR register. The CAN_TIM register is frozen to the FFFFh value. A clear condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered. To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register after each start of frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR register is set, the value is captured at each End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the CAN_SR register. The time management unit can operate in one of the two following modes: • Timestamping mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame • Time Triggered mode: A mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. Timestamping Mode is enabled by clearing TTM field in the CAN_MR register. Time Triggered Mode is enabled by setting TTM field in the CAN_MR register. 737 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.6.4 40.6.4.1 CAN 2.0 Standard Features CAN Bit Timing Configuration All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the individual controllers, the bit rate has to be adjusted by the time segments. The CAN protocol specification partitions the nominal bit time into four different segments: Figure 40-4. Partition of the CAN Bit Time NOMINAL BIT TIME SYNC_SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample Point • TIME QUANTUM The TIME QUANTUM (TQ) is a fixed unit of time derived from the MCK period. The total number of TIME QUANTA in a bit time is programmable from 8 to 25. SYNC SEG: SYNChronization Segment. This part of the bit time is used to synchronize the various nodes on the bus. An edge is expected to lie within this segment. It is 1 TQ long. • PROP SEG: PROPagation Segment. This part of the bit time is used to compensate for the physical delay times within the network. It is twice the sum of the signal’s propagation time on the bus line, the input comparator delay, and the output driver delay. It is programmable to be 1,2,..., 8 TQ long. This parameter is defined in the PROPAG field of the ”CAN Baudrate Register”. • PHASE SEG1, PHASE SEG2: PHASE Segment 1 and 2. The Phase-Buffer-Segments are used to compensate for edge phase errors. These segments can be lengthened (PHASE SEG1) or shortened (PHASE SEG2) by resynchronization. Phase Segment 1 is programmable to be 1,2,..., 8 TQ long. Phase Segment 2 length has to be at least as long as the Information Processing Time (IPT) and may not be more than the length of Phase Segment 1. These parameters are defined in the PHASE1 and PHASE2 fields of the ”CAN Baudrate Register”. • INFORMATION PROCESSING TIME: The Information Processing Time (IPT) is the time required for the logic to determine the bit level of a sampled bit. The IPT begins at the sample point, is measured in TQ and is fixed at 2 TQ for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, PHASE SEG2 shall not be less than the IPT. • SAMPLE POINT: 738 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A The SAMPLE POINT is the point in time at which the bus level is read and interpreted as the value of that respective bit. Its location is at the end of PHASE_SEG1. • SJW: ReSynchronization Jump Width. The ReSynchronization Jump Width defines the limit to the amount of lengthening or shortening of the Phase Segments. SJW is programmable to be the minimum of PHASE SEG1 and 4 TQ. If the SMP field in the CAN_BR register is set, then the incoming bit stream is sampled three times with a period of half a CAN clock period, centered on sample point. In the CAN controller, the length of a bit on the CAN bus is determined by the parameters (BRP, PROPAG, PHASE1 and PHASE2). t BIT = t CSC + t PRS + t PHS1 + t PHS2 The time quantum is calculated as follows: t CSC = ( BRP + 1 ) ⁄ MCK Note: The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized. t PRS = t CSC × ( PROPAG + 1 ) t PHS1 = t CSC × ( PHASE1 + 1 ) t PHS2 = t CSC × ( PHASE2 + 1 ) To compensate for phase shifts between clock oscillators of different controllers on the bus, the CAN controller must resynchronize on any relevant signal edge of the current transmission. The resynchronization shortens or lengthens the bit time so that the position of the sample point is shifted with regard to the detected edge. The resynchronization jump width (SJW) defines the maximum of time by which a bit period may be shortened or lengthened by resynchronization. t SJW = t CSC × ( SJW + 1 ) Figure 40-5. CAN Bit Timing MCK CAN Clock tCSC tPRS tPHS1 tPHS2 NOMINAL BIT TIME SYNC_ SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 Sample Point Transmission Point 739 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Example of bit timing determination for CAN baudrate of 500 Kbit/s: MCK = 48MHz CAN baudrate= 500kbit/s => bit time= 2us Delay of the bus driver: 50 ns Delay of the receiver: 30ns Delay of the bus line (20m): 110ns The total number of time quanta in a bit time must be comprised between 8 and 25. If we fix the bit time to 16 time quanta: Tcsc = 1 time quanta = bit time / 16 = 125 ns => BRP = (Tcsc x MCK) - 1 = 5 The propagation segment time is equal to twice the sum of the signal’s propagation time on the bus line, the receiver delay and the output driver delay: Tprs = 2 * (50+30+110) ns = 380 ns = 3 Tcsc => PROPAG = Tprs/Tcsc - 1 = 2 The remaining time for the two phase segments is: Tphs1 + Tphs2 = bit time - Tcsc - Tprs = (16 - 1 - 3)Tcsc Tphs1 + Tphs2 = 12 Tcsc Because this number is even, we choose Tphs2 = Tphs1 (else we would choose Tphs2 = Tphs1 + Tcsc) Tphs1 = Tphs2 = (12/2) Tcsc = 6 Tcsc => PHASE1 = PHASE2 = Tphs1/Tcsc - 1 = 5 The resynchronization jump width must be comprised between 1 Tcsc and the minimum of 4 Tcsc and Tphs1. We choose its maximum value: Tsjw = Min(4 Tcsc,Tphs1) = 4 Tcsc => SJW = Tsjw/Tcsc - 1 = 3 Finally: CAN_BR = 0x00053255 40.6.4.2 CAN Bus Synchronization Two types of synchronization are distinguished: “hard synchronization” at the start of a frame and “resynchronization” inside a frame. After a hard synchronization, the bit time is restarted with the end of the SYNC_SEG segment, regardless of the phase error. Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge. The effect of resynchronization is the same as that of hard synchronization when the magnitude of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width (tSJW). When the magnitude of the phase error is larger than the resynchronization jump width and • the phase error is positive, then PHASE_SEG1 is lengthened by an amount equal to the resynchronization jump width. • the phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the resynchronization jump width. 740 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 40-6. CAN Resynchronization THE PHASE ERROR IS POSITIVE (the transmitter is slower than the receiver) Received data bit Nominal Sample point Sample point after resynchronization Nominal bit time (before resynchronization) SYNC_ SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 SYNC_ SEG Phase error Bit time with resynchronization Phase error (max Tsjw) SYNC_ SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 SYNC_ SEG THE PHASE ERROR IS NEGATIVE (the transmitter is faster than the receiver) Received data bit Sample point after resynchronization Nominal Sample point Nominal bit time (before resynchronization) PHASE_SEG2 SYNC_ SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 SYNC_ SEG Phase error Bit time with resynchronization PHASE_ SYNC_ SEG2 SEG PROP_SEG PHASE_SEG1 PHASE_SEG2 SYNC_ SEG Phase error (max Tsjw) 40.6.4.3 Autobaud Mode The autobaud feature is enabled by setting the ABM field in the CAN_MR register. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It can not send any message. The errors flags are updated. The bit timing can be adjusted until no error occurs (good configuration found). In this mode, the error counters are frozen. To go back to the standard mode, the ABM bit must be cleared in the CAN_MR register. Error Detection There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their correspondence): • CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame. • Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting with the next bit-time. • Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. An error frame is generated and starts with the next bit time. • Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in one of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error has occurred and an error frame is generated. 741 40.6.4.4 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. If this is the case, at least one other node has received the frame correctly. If not, an Acknowledge Error has occurred and the transmitter will start in the next bit-time an Error Frame transmission. 40.6.4.5 Fault Confinement To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The two counters are incremented upon detected errors and are decremented upon correct transmissions or receptions, respectively. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags. The controller changes to the Error Passive state if there is an accumulation of errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state transition to Bus Off. Figure 40-7. Line Error Mode Init TEC < 127 and REC < 127 ERROR ACTIVE TEC > 127 or REC > 127 128 occurences of 11 consecutive recessive bits or CAN controller reset ERROR PASSIVE BUS OFF TEC > 255 An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinement, two errors counters (TEC and REC) are implemented. These counters are accessible via the CAN_ECR register. The state of the CAN controller is automatically updated according to these counter values. If the CAN controller is in Error Active state, then the ERRA bit is set in the CAN_SR register. The corresponding interrupt is pending while the interrupt is not masked in the CAN_IMR register. If the CAN controller is in Error Passive Mode, then the ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is set in the CAN_IMR register. If the CAN is in Bus Off Mode, then the BOFF bit is set in the CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in the CAN_IMR register. 742 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the interrupt is set in the CAN_IMR register. Refer to the Bosch CAN specification v2.0 for details on fault confinement. 40.6.4.6 Error Interrupt Handler WARN, BOFF, ERRA and ERRP (CAN_SR) represent the current status of the CAN bus and are not latched. They reflect the current TEC and REC (CAN_ECR) values as described in Section 40.6.4.5 “Fault Confinement” on page 742. Based on that, if these bits are used as an interrupt, the user can enter into an interrupt and not see the corresponding status register if the TEC and REC counter have changed their state. When entering Bus Off Mode, the only way to exit from this state is 128 occurrences of 11 consecutive recessive bits or a CAN controller reset. In Error Active Mode, the user reads: • ERRA =1 • ERRP = 0 • BOFF = 0 In Error Passive Mode, the user reads: • ERRA = 0 • ERRP =1 • BOFF = 0 In Bus Off Mode, the user reads: • ERRA = 0 • ERRP =1 • BOFF =1 The CAN interrupt handler should do the following: • Only enable one error mode interrupt at a time. • Look at and check the REC and TEC values in the interrupt handler to determine the current state. 40.6.4.7 Overload The overload frame is provided to request a delay of the next data or remote frame by the receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field respectively. Reactive overload frames are transmitted after detection of the following error conditions: • Detection of a dominant bit during the first two bits of the intermission field • Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR register. 743 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR register is not set. An overload flag is generated in the same way as an error flag, but error counters do not increment. 40.6.5 Low-power Mode In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive. In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP signal in the CAN_SR register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Lowpower Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detection of 11 consecutive recessive bits on the bus. 40.6.5.1 Enabling Low-power Mode A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent. When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The WAKEUP signal is automatically cleared once SLEEP is set. Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those messages with higher priority than the last message transmitted can be received between the LPM command and entry in Low-power Mode. Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip’s Power Management Controller (PMC). The CAN controller drains only the static current. Error counters are disabled while the SLEEP signal is set to one. Thus, to enter Low-power Mode, the software application must: – Set LPM field in the CAN_MR register – Wait for SLEEP signal rising Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC). 744 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 40-8. Enabling Low-power Mode Arbitration lost CAN BUS LPEN= 1 LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSR1) MRDY (CAN_MSR3) CAN_TIM Mailbox 1 Mailbox 3 0x0 40.6.5.2 Disabling Low-power Mode The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power Mode by programming the CAN controller. To disable Low-power Mode, the software application must: – Enable the CAN Controller clock. This is done by programming the Power Management Controller (PMC). – Clear the LPM field in the CAN_MR register The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive “recessive” bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while WAKEUP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set. If no message is being sent on the bus, then the CAN controller is able to send a message eleven bit times after disabling Low-power Mode. If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized with the bus activity in the next interframe. The previous message is lost (see Figure 40-9). 745 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 40-9. Disabling Low-power Mode Bus Activity Detected Message x Interframe synchronization CAN BUS LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR) Message lost MRDY (CAN_MSRx) 746 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.7 40.7.1 Functional Description CAN Controller Initialization After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC). The CAN controller must be initialized with the CAN network parameters. The CAN_BR register defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller is enabled by setting the CANEN field in the CAN_MR register. The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage, the internal CAN controller state machine is reset, error counters are reset to 0, error flags are reset to 0. Once the CAN controller is enabled, bus synchronization is done automatically by scanning eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset). The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a mailbox may be configured in Receive Mode. By scanning error flags, the CAN_BR register values synchronized with the network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register. Figure 40-10. Possible Initialization Procedure Enable CAN Controller Clock (PMC) Enable CAN Controller Interrupt Line (AIC) Configure a Mailbox in Reception Mode Change CAN_BR value (ABM == 1 and CANEN == 1) Errors ? (CAN_SR or CAN_MSRx) Yes No ABM = 0 and CANEN = 0 CANEN = 1 (ABM == 0) End of Initialization 747 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.7.2 CAN Controller Interrupt Handling There are two different types of interrupts. One type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources. All interrupt sources can be masked by writing the corresponding field in the CAN_IDR register. They can be unmasked by writing to the CAN_IER register. After a power-up reset, all interrupt sources are disabled (masked). The current mask status can be checked by reading the CAN_IMR register. The CAN_SR register gives all interrupt source states. The following events may initiate one of the two interrupts: • Message object interrupt – Data registers in the mailbox object are available to the application. In Receive Mode, a new message was received. In Transmit Mode, a message was transmitted successfully. – A sent transmission was aborted. • System interrupts – Bus off interrupt: The CAN module enters the bus off state. – Error passive interrupt: The CAN module enters Error Passive Mode. – Error Active Mode: The CAN module is neither in Error Passive Mode nor in Bus Off mode. – Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter value exceeds 96. – Wake-up interrupt: This interrupt is generated after a wake-up and a bus synchronization. – Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all pending messages in transmission have been sent. – Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over. – Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register. All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the CAN_SR register. 748 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.7.3 40.7.3.1 CAN Controller Message Handling Receive Handling Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In Receive with Overwrite Mode, the last message received is stored in the mailbox. Simple Receive Mailbox A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance Mask must be set before the Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. Message data are stored in the mailbox data register until the software application notifies that data processing has ended. This is done by asking for a new transfer command, setting the MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal. The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx register. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while MRDY flag is set in the CAN_MSRx register. See Figure 40-11. Figure 40-11. Receive Mailbox Message ID = CAN_MIDx 40.7.3.2 CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) Message 1 Message 2 lost Message 3 (CAN_MDLx CAN_MDHx) MTCR (CAN_MCRx) Message 1 Message 3 Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx Note: In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler instruction. 749 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.7.3.3 Receive with Overwrite Mailbox A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register. If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx register notifies the software that a message has been dropped by the mailbox. This flag is cleared when reading the CAN_MSRx register. The CAN controller may store a new message in the CAN data registers while the application reads them. To check that CAN_MDHx and CAN_MDLx do not belong to different messages, the application must check the MMI field in the CAN_MSRx register before and after reading CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data registers have been read, the software application has to re-read CAN_MDHx and CAN_MDLx (see Figure 40-12). Figure 40-12. Receive with Overwrite Mailbox Message ID = CAN_MIDx CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) (CAN_MDLx CAN_MDHx) MTCR (CAN_MCRx) Message 1 Message 2 Message 3 Message 4 Message 1 Message 2 Message 3 Message 4 Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx 750 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.7.3.4 Chaining Mailboxes Several mailboxes may be used to receive a buffer split into several messages with the same ID. In this case, the mailbox with the lowest number is serviced first. In the receive and receive with overwrite modes, the field PRIOR in the CAN_MMRx register has no effect. If Mailbox 0 and Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0 and the second message is received by Mailbox 5. Mailbox 0 must be configured in Receive Mode (i.e., the first message received is considered) and Mailbox 5 must be configured in Receive with Overwrite Mode. Mailbox 0 cannot be configured in Receive with Overwrite Mode; otherwise, all messages are accepted by this mailbox and Mailbox 5 is never serviced. If several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in Receive Mode. The first message received is handled by the first mailbox, the second one is refused by the first mailbox and accepted by the second mailbox, the last message is accepted by the last mailbox and refused by previous ones (see Figure 40-13). Figure 40-13. Chaining Three Mailboxes to Receive a Buffer Split into Three Messages Buffer split in 3 messages CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz) Message s1 Message s2 Message s3 Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR If the number of mailboxes is not sufficient (the MMI flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see Figure 40-14). 751 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 40-14. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages Buffer split in 4 messages CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz) Message s1 Message s2 Message s3 Message s4 Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR 40.7.3.5 Transmission Handling A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers. The message is sent once the software asks for a transfer command setting the MTCR bit and the message data length in the CAN_MCRx register. The MRDY flag remains at zero as long as the message has not been sent or aborted. It is important to note that no access to the mailbox data register is allowed while the MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field. The answer to the remote frame is handled by another reception mailbox. In this case, the device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote frame emission and the answer reception using only one mailbox configured in Consumer Mode. Refer to the section “Remote Frame Handling” on page 753. Several messages can try to win the bus arbitration in the same time. The message with the highest priority is sent first. Several transfer request commands can be generated at the same time by setting MBx bits in the CAN_TCR register. The priority is set in the PRIOR field of the CAN_MMRx register. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox 0 and 752 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first. Setting the MACR bit in the CAN_MCRx register aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR register. If the message is being sent when the abort command is set, then the application is notified by the MRDY bit set and not the MABT in the CAN_MSRx register. Otherwise, if the message has not been sent, then the MRDY and the MABT are set in the CAN_MSR register. When the bus arbitration is lost by a mailbox message, the CAN controller tries to win the next bus arbitration with the same message if this one still has the highest priority. Messages to be sent are re-tried automatically until they win the bus arbitration. This feature can be disabled by setting the bit DRPT in the CAN_MR register. In this case if the message was not sent the first time it was transmitted to the CAN transceiver, it is automatically aborted. The MABT flag is set in the CAN_MSRx register until the next transfer command. Figure 40-15 shows three MBx message attempts being made (MRDY of MBx set to 0). The first MBx message is sent, the second is aborted and the last one is trying to be aborted but too late because it has already been transmitted to the CAN transceiver. Figure 40-15. Transmitting Messages CAN BUS MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Reading CAN_MSRx Writing CAN_MDHx & CAN_MDLx Abort MBx message Try to Abort MBx message MBx message MBx message 40.7.3.6 Remote Frame Handling Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. 753 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 40-16. Producer / Consumer Model Producer Request PUSH MODEL CAN Data Frame Consumer Indication(s) PULL MODEL Producer Indications CAN Remote Frame Consumer Request(s) Response CAN Data Frame Confirmation(s) In Pull Mode, a consumer transmits a remote frame to the producer. When the producer receives a remote frame, it sends the answer accepted by one or many consumers. Using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in Transmit Mode to send remote frames, and at least one in Receive Mode to capture the producer’s answer. The same structure is applicable to a producer: one reception mailbox is required to get the remote frame and one transmit mailbox to answer. Mailboxes can be configured in Producer or Consumer Mode. A lonely mailbox can handle the remote frame and the answer. With 16 mailboxes, the CAN controller can handle 16 independent producers/consumers. 40.7.3.7 Producer Configuration A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx registers, then by setting the MTCR bit in the CAN_MCRx register. Data is sent after the reception of a remote frame as soon as it wins the bus arbitration. The MRDY flag remains at zero as long as the message has not been sent or aborted. No access to the mailbox data register can be done while MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. If a remote frame is received while no data are ready to be sent (signal MRDY set in the CAN_MSRx register), then the MMI signal is set in the CAN_MSRx register. This bit is cleared by reading the CAN_MSRx register. The MRTR field in the CAN_MSRx register has no meaning. This field is used only when using Receive and Receive with Overwrite modes. 754 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message may be aborted by setting the MACR bit in the CAN_MCR register. Please refer to the section “Transmission Handling” on page 752. Figure 40-17. Producer Handling CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) Reading CAN_MSRx Remote Frame Message 1 Remote Frame Remote Frame Message 2 (CAN_MDLx CAN_MDHx) Message 1 Message 2 40.7.3.8 Consumer Configuration A mailbox is in Consumer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Consumer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first transfer request command. The software application sends a remote frame by setting the MTCR bit in the CAN_MCRx register or the MBx bit in the global CAN_TCR register. The application is notified of the answer by the MRDY flag set in the CAN_MSRx register. The application can read the data contents in the CAN_MDHx and CAN_MDLx registers. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. The MRTR bit in the CAN_MCRx register has no effect. This field is used only when using Transmit Mode. After a remote frame has been sent, the consumer mailbox functions as a reception mailbox. The first message received is stored in the mailbox data registers. If other messages intended for this mailbox have been sent while the MRDY flag is set in the CAN_MSRx register, they will be lost. The application is notified by reading the MMI field in the CAN_MSRx register. The read operation automatically clears the MMI flag. If several messages are answered by the Producer, the CAN controller may have one mailbox in consumer configuration, zero or several mailboxes in Receive Mode and one mailbox in Receive with Overwrite Mode. In this case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox. The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR register. 755 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 40-18. Consumer Handling CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) Remote Frame Message x Remote Frame Message y (CAN_MDLx CAN_MDHx) Message x Message y 40.7.4 CAN Controller Timing Modes Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes: • Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame. • Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger. Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR register. Time Triggered Mode is enabled by setting the TTM bit in the CAN_MR register. 40.7.4.1 Timestamping Mode Each mailbox has its own timestamp value. Each time a message is sent or received by a mailbox, the 16-bit value MTIMESTAMP of the CAN_TIMESTP register is transferred to the LSB bits of the CAN_MSRx register. The value read in the CAN_MSRx register corresponds to the internal timer value at the Start Of Frame or the End Of Frame of the message handled by the mailbox. Figure 40-19. Mailbox Timestamp Start of Frame End of Frame CAN BUS CAN_TIM Message 1 Message 2 TEOF (CAN_MR) TIMESTAMP (CAN_TSTP) MTIMESTAMP (CAN_MSRx) MTIMESTAMP (CAN_MSRy) Timestamp 1 Timestamp 2 Timestamp 1 Timestamp 2 756 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.7.4.2 Time Triggered Mode In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window. Figure 40-20. Time Triggered Principle Time Cycle Reference Message Reference Message Time Windows for Messages Global Time Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Triggered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at 0. 40.7.4.3 Synchronization by a Reference Message In Time Triggered Mode, the internal timer counter is automatically reset when a new message is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the rising edge of the MRDY signal in the CAN_MSRx register. This allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window. Transmitting within a Time Window A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared with each mailbox time mark. When the internal timer counter reaches the MTIMEMARK value, an internal timer event for the mailbox is generated for the mailbox. In Time Triggered Mode, transmit operations are delayed until the internal timer event for the mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx register. The message is not sent until the CAN_TIM value is less than the MTIMEMARK value defined in the CAN_MMRx register. If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until the next internal time trigger event. This prevents overlapping the next time window, but the message is still pending and is retried in the next time window when CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting the DRPT field in the CAN_MR register. 40.7.4.5 Freezing the Internal Timer Counter The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter is 40.7.4.4 757 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set. Figure 40-21. Time Triggered Operations End of Frame Message x Arbitration Lost Message y Arbitration Win CAN BUS Reference Message Message y Internal Counter Reset CAN_TIM Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MRDY (CAN_MSRx) MTIMEMARKy == CAN_TIM MTIMEMARKx == CAN_TIM Timer Event y MRDY (CAN_MSRy) Time Window Basic Cycle End of Frame Message x Arbitration Win Message x CAN BUS CAN_TIM Reference Message Internal Counter Reset Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MRDY (CAN_MSRx) Time Window Basic Cycle MTIMEMARKx == CAN_TIM 758 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8 Controller Area Network (CAN) User Interface Register Mapping Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x0100 - 0x01FC 0x0200 + mb_num * 0x20 + 0x00 0x0200 + mb_num * 0x20 + 0x04 0x0200 + mb_num * 0x20 + 0x08 0x0200 + mb_num * 0x20 + 0x0C 0x0200 + mb_num * 0x20 + 0x10 0x0200 + mb_num * 0x20 + 0x14 0x0200 + mb_num * 0x20 + 0x18 0x0200 + mb_num * 0x20 + 0x1C Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Baudrate Register Timer Register Timestamp Register Error Counter Register Transfer Command Register Abort Command Register Reserved Mailbox Mode Register (2) Table 40-4. Name CAN_MR CAN_IER CAN_IDR CAN_IMR CAN_SR CAN_BR CAN_TIM CAN_TIMESTP CAN_ECR CAN_TCR CAN_ACR – CAN_MMR CAN_MAM CAN_MID CAN_MFID CAN_MSR CAN_MDL CAN_MDH CAN_MCR Access Read-write Write-only Write-only Read-only Read-only Read-write Read-only Read-only Read-only Write-only Write-only – Read-write Read-write Read-write Read-only Read-only Read-write Read-write Write-only Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 – 0x0 0x0 0x0 0x0 0x0 0x0 0x0 - Mailbox Acceptance Mask Register Mailbox ID Register Mailbox Family ID Register Mailbox Status Register Mailbox Data Low Register Mailbox Data High Register Mailbox Control Register 2. Mailbox number ranges from 0 to 15. 759 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.1 Name: Address: Access: 31 – 23 – 15 – 7 DRPT CAN Mode Register CAN_MR 0xFFFAC000 Read-write 30 – 22 – 14 – 6 TIMFRZ 29 – 21 – 13 – 5 TTM 28 – 20 – 12 – 4 TEOF 27 – 19 – 11 – 3 OVL 26 25 24 18 – 10 – 2 ABM 17 – 9 – 1 LPM 16 – 8 – 0 CANEN • CANEN: CAN Controller Enable 0 = The CAN Controller is disabled. 1 = The CAN Controller is enabled. • LPM: Disable/Enable Low Power Mode w Power Mode. 1 = Enable Low Power M CAN controller enters Low Power Mode once all pending messages have been transmitted. • ABM: Disable/Enable Autobaud/Listen mode 0 = Disable Autobaud/listen mode. 1 = Enable Autobaud/listen mode. • OVL: Disable/Enable Overload Frame 0 = No overload frame is generated. 1 = An overload frame is generated after each successful reception for mailboxes configured in Receive with/without overwrite Mode, Producer and Consumer. • TEOF: Timestamp messages at each end of Frame 0 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame. 1 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame. • TTM: Disable/Enable Time Triggered Mode 0 = Time Triggered Mode is disabled. 1 = Time Triggered Mode is enabled. 760 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • TIMFRZ: Enable Timer Freeze 0 = The internal timer continues to be incremented after it reached 0xFFFF. 1 = The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See “Freezing the Internal Timer Counter” on page 757. • DRPT: Disable Repeat 0 = When a transmit mailbox loses the bus arbitration, the transfer request remains pending. 1 = When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx. 761 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.2 Name: Address: Access: 31 – 23 TSTP 15 MB15 7 MB7 CAN Interrupt Enable Register CAN_IER 0xFFFAC004 Write-only 30 – 22 TOVF 14 MB14 6 MB6 29 – 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0 • MBx: Mailbox x Interrupt Enable 0 = No effect. 1 = Enable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Enable 0 = No effect. 1 = Enable ERRA interrupt. • WARN: Warning Limit Interrupt Enable 0 = No effect. 1 = Enable WARN interrupt. • ERRP: Error Passive Mode Interrupt Enable 0 = No effect. 1 = Enable ERRP interrupt. • BOFF: Bus Off Mode Interrupt Enable 0 = No effect. 1 = Enable BOFF interrupt. • SLEEP: Sleep Interrupt Enable 0 = No effect. 1 = Enable SLEEP interrupt. • WAKEUP: Wakeup Interrupt Enable 0 = No effect. 1 = Enable SLEEP interrupt. 762 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • TOVF: Timer Overflow Interrupt Enable 0 = No effect. 1 = Enable TOVF interrupt. • TSTP: TimeStamp Interrupt Enable 0 = No effect. 1 = Enable TSTP interrupt. • CERR: CRC Error Interrupt Enable 0 = No effect. 1 = Enable CRC Error interrupt. • SERR: Stuffing Error Interrupt Enable 0 = No effect. 1 = Enable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Enable 0 = No effect. 1 = Enable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Enable 0 = No effect. 1 = Enable Form Error interrupt. • BERR: Bit Error Interrupt Enable 0 = No effect. 1 = Enable Bit Error interrupt. 763 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.3 Name: Address: Access: 31 – 23 TSTP 15 MB15 7 MB7 CAN Interrupt Disable Register CAN_IDR 0xFFFAC008 Write-only 30 – 22 TOVF 14 MB14 6 MB6 29 – 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0 • MBx: Mailbox x Interrupt Disable 0 = No effect. 1 = Disable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Disable 0 = No effect. 1 = Disable ERRA interrupt. • WARN: Warning Limit Interrupt Disable 0 = No effect. 1 = Disable WARN interrupt. • ERRP: Error Passive Mode Interrupt Disable 0 = No effect. 1 = Disable ERRP interrupt. • BOFF: Bus Off Mode Interrupt Disable 0 = No effect. 1 = Disable BOFF interrupt. • SLEEP: Sleep Interrupt Disable 0 = No effect. 1 = Disable SLEEP interrupt. • WAKEUP: Wakeup Interrupt Disable 0 = No effect. 1 = Disable WAKEUP interrupt. 764 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • TOVF: Timer Overflow Interrupt 0 = No effect. 1 = Disable TOVF interrupt. • TSTP: TimeStamp Interrupt Disable 0 = No effect. 1 = Disable TSTP interrupt. • CERR: CRC Error Interrupt Disable 0 = No effect. 1 = Disable CRC Error interrupt. • SERR: Stuffing Error Interrupt Disable 0 = No effect. 1 = Disable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Disable 0 = No effect. 1 = Disable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Disable 0 = No effect. 1 = Disable Form Error interrupt. • BERR: Bit Error Interrupt Disable 0 = No effect. 1 = Disable Bit Error interrupt. 765 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.4 Name: Address: Access: 31 – 23 TSTP 15 MB15 7 MB7 CAN Interrupt Mask Register CAN_IMR 0xFFFAC00C Read-only 30 – 22 TOVF 14 MB14 6 MB6 29 – 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0 • MBx: Mailbox x Interrupt Mask 0 = Mailbox x interrupt is disabled. 1 = Mailbox x interrupt is enabled. • ERRA: Error Active Mode Interrupt Mask 0 = ERRA interrupt is disabled. 1 = ERRA interrupt is enabled. • WARN: Warning Limit Interrupt Mask 0 = Warning Limit interrupt is disabled. 1 = Warning Limit interrupt is enabled. • ERRP: Error Passive Mode Interrupt Mask 0 = ERRP interrupt is disabled. 1 = ERRP interrupt is enabled. • BOFF: Bus Off Mode Interrupt Mask 0 = BOFF interrupt is disabled. 1 = BOFF interrupt is enabled. • SLEEP: Sleep Interrupt Mask 0 = SLEEP interrupt is disabled. 1 = SLEEP interrupt is enabled. • WAKEUP: Wakeup Interrupt Mask 0 = WAKEUP interrupt is disabled. 1 = WAKEUP interrupt is enabled. 766 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • TOVF: Timer Overflow Interrupt Mask 0 = TOVF interrupt is disabled. 1 = TOVF interrupt is enabled. • TSTP: Timestamp Interrupt Mask 0 = TSTP interrupt is disabled. 1 = TSTP interrupt is enabled. • CERR: CRC Error Interrupt Mask 0 = CRC Error interrupt is disabled. 1 = CRC Error interrupt is enabled. • SERR: Stuffing Error Interrupt Mask 0 = Bit Stuffing Error interrupt is disabled. 1 = Bit Stuffing Error interrupt is enabled. • AERR: Acknowledgment Error Interrupt Mask 0 = Acknowledgment Error interrupt is disabled. 1 = Acknowledgment Error interrupt is enabled. • FERR: Form Error Interrupt Mask 0 = Form Error interrupt is disabled. 1 = Form Error interrupt is enabled. • BERR: Bit Error Interrupt Mask 0 = Bit Error interrupt is disabled. 1 = Bit Error interrupt is enabled. 767 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.5 Name: Address: Access: 31 OVLSY 23 TSTP 15 MB15 7 MB7 CAN Status Register CAN_SR 0xFFFAC010 Read-only 30 TBSY 22 TOVF 14 MB14 6 MB6 29 RBSY 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0 • MBx: Mailbox x Event 0 = No event occurred on Mailbox x. 1 = An event occurred on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx register. • ERRA: Error Active Mode 0 = CAN controller is not in Error Active Mode. 1 = CAN controller is in Error Active Mode. This flag is set depending on TEC and REC counter values. It is set when node is neither in Error Passive Mode nor in Bus Off Mode. This flag is automatically reset when above condition is not satisfied. Refer to Section 40.6.4.6 “Error Interrupt Handler” on page 743 for more information. • WARN: Warning Limit 0 = CAN controller Warning Limit is not reached. 1 = CAN controller Warning Limit is reached. This flag is set depending on TEC and REC counter values. It is set when at least one of the counter values exceeds 96. This flag is automatically reset when above condition is not satisfied. Refer to Section 40.6.4.6 “Error Interrupt Handler” on page 743 for more information. • ERRP: Error Passive Mode 0 = CAN controller is not in Error Passive Mode. 1 = CAN controller is in Error Passive Mode. This flag is set depending on TEC and REC counters values. A node is error passive when TEC counter is greater or equal to 128 (decimal) or when the REC counter is greater or equal to 128 (decimal). 768 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A This flag is automatically reset when above condition is not satisfied. Refer to Section 40.6.4.6 “Error Interrupt Handler” on page 743 for more information. • BOFF: Bus Off Mode 0 = CAN controller is not in Bus Off Mode. 1 = CAN controller is in Bus Off Mode. This flag is set depending on TEC counter value. A node is bus off when TEC counter is greater or equal to 256 (decimal). This flag is automatically reset when above condition is not satisfied. Refer to Section 40.6.4.6 “Error Interrupt Handler” on page 743 for more information. • SLEEP: CAN controller in Low power Mode 0 = CAN controller is not in low power mode. 1 = CAN controller is in low power mode. This flag is automatically reset when Low power mode is disabled • WAKEUP: CAN controller is not in Low power Mode 0 = CAN controller is in low power mode. 1 = CAN controller is not in low power mode. When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the CAN Controller enters Low Power mode. • TOVF: Timer Overflow 0 = The timer has not rolled-over FFFFh to 0000h. 1 = The timer rolls-over FFFFh to 0000h. This flag is automatically cleared by reading CAN_SR register. • TSTP Timestamp 0 = No bus activity has been detected. 1 = A start of frame or an end of frame has been detected (according to the TEOF field in the CAN_MR register). This flag is automatically cleared by reading the CAN_SR register. • CERR: Mailbox CRC Error 0 = No CRC error occurred during a previous transfer. 1 = A CRC error occurred during a previous transfer. A CRC error has been detected during last reception. This flag is automatically cleared by reading CAN_SR register. • SERR: Mailbox Stuffing Error 0 = No stuffing error occurred during a previous transfer. 1 = A stuffing error occurred during a previous transfer. A form error results from the detection of more than five consecutive bits with the same polarity. 769 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A This flag is automatically cleared by reading CAN_SR register. • AERR: Acknowledgment Error 0 = No acknowledgment error occurred during a previous transfer. 1 = An acknowledgment error occurred during a previous transfer. An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. This flag is automatically cleared by reading CAN_SR register. • FERR: Form Error 0 = No form error occurred during a previous transfer 1 = A form error occurred during a previous transfer A form error results from violations on one or more of the fixed form of the following bit fields: – CRC delimiter – ACK delimiter – End of frame – Error delimiter – Overload delimiter This flag is automatically cleared by reading CAN_SR register. • BERR: Bit Error 0 = No bit error occurred during a previous transfer. 1 = A bit error occurred during a previous transfer. A bit error is set when the bit value monitored on the line is different from the bit value sent. This flag is automatically cleared by reading CAN_SR register. • RBSY: Receiver busy 0 = CAN receiver is not receiving a frame. 1 = CAN receiver is receiving a frame. Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving. • TBSY: Transmitter busy 0 = CAN transmitter is not transmitting a frame. 1 = CAN transmitter is transmitting a frame. Transmitter busy. This status bit is set by hardware while CAN transmitter is generating a frame (remote, data, overload or error frame). It is automatically reset when CAN is not transmitting. • OVLSY: Overload busy 0 = CAN transmitter is not transmitting an overload frame. 1 = CAN transmitter is transmitting a overload frame. It is automatically reset when the bus is not transmitting an overload frame. 770 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.6 Name: Address: Access: 31 – 23 – 15 – 7 – CAN Baudrate Register CAN_BR 0xFFFAC014 Read-write 30 – 22 29 – 21 28 – 20 27 – 19 BRP 11 – 3 – 26 – 18 25 – 17 24 SMP 16 14 – 6 13 SJW 5 PHASE1 12 10 9 PROPAG 1 PHASE2 8 4 2 0 Any modification on one of the fields of the CANBR register must be done while CAN module is disabled. To compute the different Bit Timings, please refer to the Section 40.6.4.1 “CAN Bit Timing Configuration” on page 738. • PHASE2: Phase 2 segment This phase is used to compensate the edge phase error. t PHS2 = t CSC × ( PHASE2 + 1 ) Warning: PHASE2 value must be different from 0. • PHASE1: Phase 1 segment This phase is used to compensate for edge phase error. t PHS1 = t CSC × ( PHASE1 + 1 ) • PROPAG: Programming time segment This part of the bit time is used to compensate for the physical delay times within the network. t PRS = t CSC × ( PROPAG + 1 ) • SJW: Re-synchronization jump width To compensate for phase shifts between clock oscillators of different controllers on bus. The controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lengthened by re-synchronization. t SJW = t CSC × ( SJW + 1 ) • BRP: Baudrate Prescaler. This field allows user to program the period of the CAN system clock to determine the individual bit timing. t CSC = ( BRP + 1 ) ⁄ MCK The BRP field must be within the range [1, 0x7F], i.e., BRP = 0 is not authorized. 771 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • SMP: Sampling Mode 0 = The incoming bit stream is sampled once at sample point. 1 = The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. SMP Sampling Mode is automatically disabled if BRP = 0. 772 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.7 Name: Address: Access: 31 – 23 – 15 TIMER15 7 TIMER7 CAN Timer Register CAN_TIM 0xFFFAC018 Read-only 30 – 22 – 14 TIMER14 6 TIMER6 29 – 21 – 13 TIMER13 5 TIMER5 28 – 20 – 12 TIMER12 4 TIMER4 27 – 19 – 11 TIMER11 3 TIMER3 26 – 18 – 10 TIMER10 2 TIMER2 25 – 17 – 9 TIMER9 1 TIMER1 24 – 16 – 8 TIMER8 0 TIMER0 • TIMERx: Timer This field represents the internal CAN controller 16-bit timer value. 773 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.8 Name: Address: Access: 31 – 23 – 15 MTIMESTAM P15 7 MTIMESTAM P7 CAN Timestamp Register CAN_TIMESTP 0xFFFAC01C Read-only 30 – 22 – 14 MTIMESTAM P14 6 MTIMESTAM P6 29 – 21 – 13 MTIMESTAM P13 5 MTIMESTAM P5 28 – 20 – 12 MTIMESTAM P12 4 MTIMESTAM P4 27 – 19 – 11 MTIMESTAM P11 3 MTIMESTAM P3 26 – 18 – 10 MTIMESTAM P10 2 MTIMESTAM P2 25 – 17 – 9 MTIMESTAM P9 1 MTIMESTAM P1 24 – 16 – 8 MTIMESTAM P8 0 MTIMESTAM P0 • MTIMESTAMPx: Timestamp This field represents the internal CAN controller 16-bit timer value. If the TEOF bit is cleared in the CAN_MR register, the internal Timer Counter value is captured in the MTIMESTAMP field at each start of frame. Else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in the CAN_SR register. If the TSTP mask in the CAN_IMR register is set, an interrupt is generated while TSTP flag is set in the CAN_SR register. This flag is cleared by reading the CAN_SR register. Note: The CAN_TIMESTP register is reset when the CAN is disabled then enabled thanks to the CANEN bit in the CAN_MR. 774 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.9 Name: Address: Access: 31 – 23 CAN Error Counter Register CAN_ECR 0xFFFAC020 Read-only 30 – 22 29 – 21 28 – 20 TEC 27 – 19 26 – 18 25 – 17 24 – 16 15 – 7 14 – 6 13 – 5 12 – 4 REC 11 – 3 10 – 2 9 – 1 8 – 0 • REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG. When a receiver detects a dominant bit as the first bit after sending an ERROR FLAG, REC is increased by 8. When a receiver detects a BIT ERROR while sending an ACTIVE ERROR FLAG, REC is increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits, each receiver increases its REC by 8. After successful reception of a message, REC is decreased by 1 if it was between 1 and 127. If REC was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127. • TEC: Transmit Error Counter When a transmitter sends an ERROR FLAG, TEC is increased by 8 except when – the transmitter is error passive and detects an ACKNOWLEDGMENT ERROR because of not detecting a dominant ACK and does not detect a dominant bit while sending its PASSIVE ERROR FLAG. – the transmitter sends an ERROR FLAG because a STUFF ERROR occurred during arbitration and should have been recessive and has been sent as recessive but monitored as dominant. When a transmitter detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG, the TEC will be increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits every transmitter increases its TEC by 8. After a successful transmission the TEC is decreased by 1 unless it was already 0. 775 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.10 Name: Address: Access: 31 TIMRST 23 – 15 MB15 7 MB7 CAN Transfer Command Register CAN_TCR 0xFFFAC024 Write-only 30 – 22 – 14 MB14 6 MB6 29 – 21 – 13 MB13 5 MB5 28 – 20 – 12 MB12 4 MB4 27 – 19 – 11 MB11 3 MB3 26 – 18 – 10 MB10 2 MB2 25 – 17 – 9 MB9 1 MB1 24 – 16 – 8 MB8 0 MB0 This register initializes several transfer requests at the same time. • MBx: Transfer Request for Mailbox x Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description It receives the next message. This triggers a new reception. Sends data prepared in the mailbox as soon as possible. Sends a remote frame. Sends data prepared in the mailbox after receiving a remote frame from a consumer. This flag clears the MRDY and MABT flags in the corresponding CAN_MSRx register. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mailbox with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., MB0 will be transferred before MB1). • TIMRST: Timer Reset Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This command is useful in Time Triggered mode. 776 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.11 Name: Address: Access: 31 – 23 – 15 MB15 7 MB7 CAN Abort Command Register CAN_ACR 0xFFFAC028 Write-only 30 – 22 – 14 MB14 6 MB6 29 – 21 – 13 MB13 5 MB5 28 – 20 – 12 MB12 4 MB4 27 – 19 – 11 MB11 3 MB3 26 – 18 – 10 MB10 2 MB2 25 – 17 – 9 MB9 1 MB1 24 – 16 – 8 MB8 0 MB0 This register initializes several abort requests at the same time. • MBx: Abort Request for Mailbox x Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Cancels transfer request if the message has not been transmitted to the CAN transceiver. Cancels the current transfer before the remote frame has been sent. Cancels the current transfer. The next remote frame is not serviced. It is possible to set MACR field (in the CAN_MCRx register) for each mailbox. 777 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.12 Name: CAN Message Mode Register CAN_MMRx [x=0..15] Addresses: 0xFFFAC200 [0], 0xFFFAC220 [1], 0xFFFAC240 [2], 0xFFFAC260 [3], 0xFFFAC280 [4], 0xFFFAC2A0 [5], 0xFFFAC2C0 [6], 0xFFFAC2E0 [7], 0xFFFAC300 [8], 0xFFFAC320 [9], 0xFFFAC340 [10], 0xFFFAC360 [11], 0xFFFAC380 [12], 0xFFFAC3A0 [13], 0xFFFAC3C0 [14], 0xFFFAC3E0 [15] Access: 31 – 23 – 15 MTIMEMARK 15 7 MTIMEMARK 7 Read-write 30 – 22 – 14 MTIMEMARK 14 6 MTIMEMARK 6 29 – 21 – 13 MTIMEMARK 13 5 MTIMEMARK 5 28 – 20 – 12 MTIMEMARK 12 4 MTIMEMARK 4 27 – 19 26 25 MOT 18 PRIOR 11 MTIMEMARK 11 3 MTIMEMARK 3 10 MTIMEMARK 10 2 MTIMEMARK 2 9 MTIMEMARK 9 1 MTIMEMARK 1 8 MTIMEMARK 8 0 MTIMEMARK 0 17 16 24 • MTIMEMARKx: Mailbox Timemark This field is active in Time Triggered Mode. Transmit operations are allowed when the internal timer counter reaches the Mailbox Timemark. See “Transmitting within a Time Window” on page 757. In Timestamp Mode, MTIMEMARK is set to 0. • PRIOR: Mailbox Priority This field has no effect in receive and receive with overwrite modes. In these modes, the mailbox with the lowest number is serviced first. When several mailboxes try to transmit a message at the same time, the mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 is serviced before MBx 15 if they have the same priority). • MOT: Mailbox Object Type This field allows the user to define the type of the mailbox. All mailboxes are independently configurable. Five different types are possible for each mailbox: MOT 0 0 0 0 0 1 Mailbox Object Type Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. Transmit mailbox. Mailbox is configured for transmission. 0 0 1 1 0 1 778 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 1 0 0 Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. Reserved 1 1 0 1 1 X 779 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.13 Name: CAN Message Acceptance Mask Register CAN_MAMx [x=0..15] Addresses: 0xFFFAC204 [0], 0xFFFAC224 [1], 0xFFFAC244 [2], 0xFFFAC264 [3], 0xFFFAC284 [4], 0xFFFAC2A4 [5], 0xFFFAC2C4 [6], 0xFFFAC2E4 [7], 0xFFFAC304 [8], 0xFFFAC324 [9], 0xFFFAC344 [10], 0xFFFAC364 [11], 0xFFFAC384 [12], 0xFFFAC3A4 [13], 0xFFFAC3C4 [14], 0xFFFAC3E4 [15] Access: 31 – 23 Read-write 30 – 22 29 MIDE 21 MIDvA 28 27 26 MIDvA 18 25 24 20 19 17 MIDvB 16 15 14 13 12 MIDvB 11 10 9 8 7 6 5 4 MIDvB 3 2 1 0 To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MAMx registers. • MIDvB: Complementary bits for identifier in extended frame mode Acceptance mask for corresponding field of the message IDvB register of the mailbox. • MIDvA: Identifier for standard frame mode Acceptance mask for corresponding field of the message IDvA register of the mailbox. • MIDE: Identifier Version 0= Compares IDvA from the received frame with the CAN_MIDx register masked with CAN_MAMx register. 1= Compares IDvA and IDvB from the received frame with the CAN_MIDx register masked with CAN_MAMx register. 780 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.14 Name: CAN Message ID Register CAN_MIDx [x=0..15] Addresses: 0xFFFAC208 [0], 0xFFFAC228 [1], 0xFFFAC248 [2], 0xFFFAC268 [3], 0xFFFAC288 [4], 0xFFFAC2A8 [5], 0xFFFAC2C8 [6], 0xFFFAC2E8 [7], 0xFFFAC308 [8], 0xFFFAC328 [9], 0xFFFAC348 [10], 0xFFFAC368 [11], 0xFFFAC388 [12], 0xFFFAC3A8 [13], 0xFFFAC3C8 [14], 0xFFFAC3E8 [15] Access: 31 – 23 Read-write 30 – 22 29 MIDE 21 MIDvA 28 27 26 MIDvA 18 25 24 20 19 17 MIDvB 16 15 14 13 12 MIDvB 11 10 9 8 7 6 5 4 MIDvB 3 2 1 0 To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers. • MIDvB: Complementary bits for identifier in extended frame mode If MIDE is cleared, MIDvB value is 0. • MIDE: Identifier Version This bit allows the user to define the version of messages processed by the mailbox. If set, mailbox is dealing with version 2.0 Part B messages; otherwise, mailbox is dealing with version 2.0 Part A messages. • MIDvA: Identifier for standard frame mode 781 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.15 Name: CAN Message Family ID Register CAN_MFIDx [x=0..15] Addresses: 0xFFFAC20C [0], 0xFFFAC22C [1], 0xFFFAC24C [2], 0xFFFAC26C [3], 0xFFFAC28C [4], 0xFFFAC2AC [5], 0xFFFAC2CC [6], 0xFFFAC2EC [7], 0xFFFAC30C [8], 0xFFFAC32C [9], 0xFFFAC34C [10], 0xFFFAC36C [11], 0xFFFAC38C [12], 0xFFFAC3AC [13], 0xFFFAC3CC [14], 0xFFFAC3EC [15] Access: 31 – 23 Read-only 30 – 22 29 – 21 28 27 26 MFID 18 25 24 20 MFID 19 17 16 15 14 13 12 MFID 11 10 9 8 7 6 5 4 MFID 3 2 1 0 • MFID: Family ID This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below. As an example: CAN_MIDx = 0x305A4321 CAN_MAMx = 0x3FF0F0FF CAN_MFIDx = 0x000000A3 782 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.16 Name: CAN Message Status Register CAN_MSRx [x=0..15] Addresses: 0xFFFAC210 [0], 0xFFFAC230 [1], 0xFFFAC250 [2], 0xFFFAC270 [3], 0xFFFAC290 [4], 0xFFFAC2B0 [5], 0xFFFAC2D0 [6], 0xFFFAC2F0 [7], 0xFFFAC310 [8], 0xFFFAC330 [9], 0xFFFAC350 [10], 0xFFFAC370 [11], 0xFFFAC390 [12], 0xFFFAC3B0 [13], 0xFFFAC3D0 [14], 0xFFFAC3F0 [15] Access: 31 – 23 MRDY 15 MTIMESTAM P15 7 MTIMESTAM P7 Read-only 30 – 22 MABT 14 MTIMESTAM P14 6 MTIMESTAM P6 29 – 21 – 13 MTIMESTAM P13 5 MTIMESTAM P5 28 – 20 MRTR 12 MTIMESTAM P12 4 MTIMESTAM P4 27 – 19 26 – 18 MDLC 11 MTIMESTAM P11 3 MTIMESTAM P3 10 MTIMESTAM P10 2 MTIMESTAM P2 9 MTIMESTAM P9 1 MTIMESTAM P1 8 MTIMESTAM P8 0 MTIMESTAM P0 25 – 17 24 MMI 16 These register fields are updated each time a message transfer is received or aborted. MMI is cleared by reading the CAN_MSRx register. MRDY, MABT are cleared by writing MTCR or MACR in the CAN_MCRx register. Warning: MRTR and MDLC state depends partly on the mailbox object type. • MTIMESTAMPx: Timer value This field is updated only when time-triggered operations are disabled (TTM cleared in CAN_MR register). If the TEOF field in the CAN_MR register is cleared, TIMESTAMP is the internal timer value at the start of frame of the last message received or sent by the mailbox. If the TEOF field in the CAN_MR register is set, TIMESTAMP is the internal timer value at the end of frame of the last message received or sent by the mailbox. In Time Triggered Mode, MTIMESTAMP is set to 0. • MDLC: Mailbox Data Length Code Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Length of the first mailbox message received Length of the last mailbox message received No action Length of the mailbox message received Length of the mailbox message to be sent after the remote frame reception 783 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • MRTR: Mailbox Remote Transmission Request Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description The first frame received has the RTR bit set. The last frame received has the RTR bit set. Reserved Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 1. Reserved. After setting the MOT field in the CAN_MMR, MRTR is reset to 0. • MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0 = Previous transfer is not aborted. 1 = Previous transfer has been aborted. This flag is cleared by writing to CAN_MCRx register Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Reserved Reserved Previous transfer has been aborted The remote frame transfer request has been aborted. The response to the remote frame transfer has been aborted. • MRDY: Mailbox Ready An interrupt is triggered when MRDY is set. 0 = Mailbox data registers can not be read/written by the software application. CAN_MDx are locked by the CAN_MDx. 1 = Mailbox data registers can be read/written by the software application. This flag is cleared by writing to CAN_MCRx register. Mailbox Object Type Receive Description At least one message has been received since the last mailbox transfer order. Data from the first frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. At least one frame has been received since the last mailbox transfer order. Data from the last frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. Mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1. At least one message has been received since the last mailbox transfer order. Data from the first message received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. A remote frame has been received, mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1. Receive with overwrite Transmit Consumer Producer 784 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • MMI: Mailbox Message Ignored 0 = No message has been ignored during the previous transfer 1 = At least one message has been ignored during the previous transfer Cleared by reading the CAN_MSRx register. Mailbox Object Type Receive Description Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message. Set when at least two messages intended for the mailbox have been sent. The last one is available in the mailbox data register. Previous ones have been lost. Reserved A remote frame has been sent by the mailbox but several messages have been received. The first one is available in the mailbox data register. Others have been ignored. Another mailbox with a lower priority may have accepted the message. A remote frame has been received, but no data are available to be sent. Receive with overwrite Transmit Consumer Producer 785 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.17 Name: CAN Message Data Low Register CAN_MDLx [x=0..15] Addresses: 0xFFFAC214 [0], 0xFFFAC234 [1], 0xFFFAC254 [2], 0xFFFAC274 [3], 0xFFFAC294 [4], 0xFFFAC2B4 [5], 0xFFFAC2D4 [6], 0xFFFAC2F4 [7], 0xFFFAC314 [8], 0xFFFAC334 [9], 0xFFFAC354 [10], 0xFFFAC374 [11], 0xFFFAC394 [12], 0xFFFAC3B4 [13], 0xFFFAC3D4 [14], 0xFFFAC3F4 [15] Access: 31 Read-write 30 29 28 MDL 27 26 25 24 23 22 21 20 MDL 19 18 17 16 15 14 13 12 MDL 11 10 9 8 7 6 5 4 MDL 3 2 1 0 • MDL: Message Data Low Value When MRDY field is set in the CAN_MSRx register, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDL value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDL value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set. Bytes are received/sent on the bus in the following order: 1. CAN_MDL[7:0] 2. CAN_MDL[15:8] 3. CAN_MDL[23:16] 4. CAN_MDL[31:24] 5. CAN_MDH[7:0] 6. CAN_MDH[15:8] 7. CAN_MDH[23:16] 8. CAN_MDH[31:24] 786 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.18 Name: CAN Message Data High Register CAN_MDHx [x=0..15] Addresses: 0xFFFAC218 [0], 0xFFFAC238 [1], 0xFFFAC258 [2], 0xFFFAC278 [3], 0xFFFAC298 [4], 0xFFFAC2B8 [5], 0xFFFAC2D8 [6], 0xFFFAC2F8 [7], 0xFFFAC318 [8], 0xFFFAC338 [9], 0xFFFAC358 [10], 0xFFFAC378 [11], 0xFFFAC398 [12], 0xFFFAC3B8 [13], 0xFFFAC3D8 [14], 0xFFFAC3F8 [15] Access: 31 Read-write 30 29 28 MDH 27 26 25 24 23 22 21 20 MDH 19 18 17 16 15 14 13 12 MDH 11 10 9 8 7 6 5 4 MDH 3 2 1 0 • MDH: Message Data High Value When MRDY field is set in the CAN_MSRx register, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDH value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set. Bytes are received/sent on the bus in the following order: 1. CAN_MDL[7:0] 2. CAN_MDL[15:8] 3. CAN_MDL[23:16] 4. CAN_MDL[31:24] 5. CAN_MDH[7:0] 6. CAN_MDH[15:8] 7. CAN_MDH[23:16] 8. CAN_MDH[31:24] 787 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 40.8.19 Name: CAN Message Control Register CAN_MCRx [x=0..15] Addresses: 0xFFFAC21C [0], 0xFFFAC23C [1], 0xFFFAC25C [2], 0xFFFAC27C [3], 0xFFFAC29C [4], 0xFFFAC2BC [5], 0xFFFAC2DC [6], 0xFFFAC2FC [7], 0xFFFAC31C [8], 0xFFFAC33C [9], 0xFFFAC35C [10], 0xFFFAC37C [11], 0xFFFAC39C [12], 0xFFFAC3BC [13], 0xFFFAC3DC [14], 0xFFFAC3FC [15] Access: 31 – 23 MTCR 15 – 7 – Write-only 30 – 22 MACR 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 MRTR 12 – 4 – 27 – 19 26 – 18 MDLC 11 – 3 – 10 – 2 – 9 – 1 – 8 – 0 – 25 – 17 24 – 16 • MDLC: Mailbox Data Length Code Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action. No action. Length of the mailbox message. No action. Length of the mailbox message to be sent after the remote frame reception. • MRTR: Mailbox Remote Transmission Request Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Set the RTR bit in the sent frame No action, the RTR bit in the sent frame is set automatically No action Consumer situations can be handled automatically by setting the mailbox object type in Consumer. This requires only one mailbox. It can also be handled using two mailboxes, one in reception, the other in transmission. The MRTR and the MTCR bits must be set in the same time. 788 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A • MACR: Abort Request for Mailbox x Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Cancels transfer request if the message has not been transmitted to the CAN transceiver. Cancels the current transfer before the remote frame has been sent. Cancels the current transfer. The next remote frame will not be serviced. It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR register. • MTCR: Mailbox Transfer Command Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Allows the reception of the next message. Triggers a new reception. Sends data prepared in the mailbox as soon as possible. Sends a remote transmission frame. Sends data prepared in the mailbox after receiving a remote frame from a Consumer. This flag clears the MRDY and MABT flags in the CAN_MSRx register. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn. The mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 will be serviced before MBx 15 if they have the same priority). It is possible to set MTCR for several mailboxes at the same time by writing to the CAN_TCR register. 789 6264C–CAP–24-Mar-09 790 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41. Pulse Width Modulation Controller (PWM) 41.1 Description The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock. All PWM macrocell accesses are made through APB mapped registers. Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. 41.2 Block Diagram Figure 41-1. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Channel Period Update Duty Cycle Comparator PWMx PWMx Clock Selector Counter PIO PWM0 Channel Period Update Duty Cycle Comparator PWM0 PWM0 Clock Selector MCK Counter PMC Clock Generator APB Interface Interrupt Generator AIC APB 791 6264C–CAP–24-Mar-09 41.3 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 41-1. Name PWMx I/O Line Description Description PWM Waveform Output for channel x Type Output 41.4 41.4.1 Product Dependencies I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. Table 41-2. I/O Lines Signal PWM0 PWM0 PWM1 PWM1 PWM1 PWM2 PWM2 PWM3 PWM3 I/O Line PB19 PC28 PA10 PB20 PC3 PB8 PC29 PA11 PB29 Peripheral A A B A B B B B B Instance PWM PWM PWM PWM PWM PWM PWM PWM PWM 41.4.2 Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. Configuring the PWM does not require the PWM clock to be enabled. 41.4.3 Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the PWM interrupt requires the AIC to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode. Table 41-3. Instance PWM Peripheral IDs ID 21 792 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41.5 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. – Clocked by the system clock, MCK, the clock generator module provides 13 clocks. – Each channel can independently choose one of the clock generator outputs. – Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 41.5.1 PWM Clock Generator Figure 41-2. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A clkA PREA DIVA PWM_MR Divider B clkB PREB DIVB PWM_MR Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks: 793 6264C–CAP–24-Mar-09 – a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024 – two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR). After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. 41.5.2 41.5.2.1 PWM Channel Block Diagram Figure 41-3. Functional View of the Channel Block Diagram inputs from clock generator Channel Clock Selector Internal Counter PWMx output waveform Comparator inputs from APB bus Each of the 4 channels is composed of three blocks: • A clock selector which selects one of the clocks provided by the clock generator described in Section 41.5.1 “PWM Clock Generator” on page 793. • An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is 20 bits. • A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration. 41.5.2.2 Waveform Properties The different properties of output waveforms are: • the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0. • the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. - If the waveform is left aligned, then the output waveform period depends on the counter 794 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: ( X × CPRD ) ------------------------------MCK By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( CRPD × DIVA ) ------------------------------------------ or ( CRPD × DIVAB ) ---------------------------------------------MCK MCK If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( 2 × X × CPRD ) -----------------------------------------MCK By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2 × CPRD × DIVA ) ----------------------------------------------------- or ( 2 × CPRD × DIVB ) ----------------------------------------------------MCK MCK • the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left aligned then: duty cycle = ( period – 1 ⁄ fchannel_x_clock × CDTY ) ----------------------------------------------------------------------------------------------------------period If the waveform is center aligned, then: ( ( period ⁄ 2 ) – 1 ⁄ fchannel_x_clock × CDTY ) ) duty cycle = ----------------------------------------------------------------------------------------------------------------------------( period ⁄ 2 ) • the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level. • the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned. 795 6264C–CAP–24-Mar-09 Figure 41-4. Non Overlapped Center Aligned Waveforms No overlap PWM0 PWM1 Period Note: 1. See Figure 41-5 on page 797 for a detailed description of center aligned waveforms. When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel. Waveforms are fixed at 0 when: • CDTY = CPRD and CPOL = 0 • CDTY = 0 and CPOL = 1 Waveforms are fixed at 1 (once the channel is enabled) when: • CDTY = 0 and CPOL = 0 • CDTY = CPRD and CPOL = 1 The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled. 796 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 41-5. Waveform Properties PWM_MCKx CHIDx(PWM_SR) CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Left Aligned CALG(PWM_CMRx) = 0 Period Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) 797 6264C–CAP–24-Mar-09 41.5.3 41.5.3.1 PWM Controller Operations Initialization Before enabling the output channel, this channel must have been configured by the software application: • Configuration of the clock generator if DIVA and DIVB are required • Selection of the clock for each channel (CPRE field in the PWM_CMRx register) • Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) • Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained below. • Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as explained below. • Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register) • Enable Interrupts (Writing CHIDx in the PWM_IER register) • Enable the PWM channel (Writing CHIDx in the PWM_ENA register) It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register. • In such a situation, all channels may have the same clock selector configuration and the same period specified. 41.5.3.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period. 41.5.3.3 Changing the Duty Cycle or the Period It is possible to modulate the output waveform duty cycle or period. To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value in the update register (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. Depending on the CPD field in the PWM_CMRx register, PWM_CUPDx either updates PWM_CPRDx or PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than the duty cycle. 798 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 41-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 1 0 PWM_CMRx. CPD PWM_CPRDx PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level. The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the enabled channel(s). See Figure 41-7. The second method uses an Interrupt Service Routine associated with the PWM channel. Note: Reading the PWM_ISR register automatically clears CHIDx flags. Figure 41-7. Polling Method PWM_ISR Read Acknowledgement and clear previous register state Writing in CPD field Update of the Period or Duty Cycle CHIDx = 1 YES Writing in PWM_CUPDx The last write has been taken into account Note: Polarity and alignment can be modified only when the channel is disabled. 799 6264C–CAP–24-Mar-09 41.5.3.4 Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register. 800 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41.6 Pulse Width Modulation Controller (PWM) User Interface Register Mapping(2) Register PWM Mode Register PWM Enable Register PWM Disable Register PWM Status Register PWM Interrupt Enable Register PWM Interrupt Disable Register PWM Interrupt Mask Register PWM Interrupt Status Register Reserved PWM Channel Mode Register PWM Channel Duty Cycle Register PWM Channel Period Register PWM Channel Counter Register PWM Channel Update Register PWM_CMR PWM_CDTY PWM_CPRD PWM_CCNT PWM_CUPD Read-write Read-write Read-write Read-only Write-only 0x0 0x0 0x0 0x0 Name PWM_MR PWM_ENA PWM_DIS PWM_SR PWM_IER PWM_IDR PWM_IMR PWM_ISR Access Read-write Write-only Write-only Read-only Write-only Write-only Read-only Read-only Reset 0 0 0 0 Table 41-4. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x100 - 0x1FC 0x200 + ch_num * 0x20 + 0x00 0x200 + ch_num * 0x20 + 0x04 0x200 + ch_num * 0x20 + 0x08 0x200 + ch_num * 0x20 + 0x0C 0x200 + ch_num * 0x20 + 0x10 2. Some registers are indexed with “ch_num” index ranging from 0 to 3. 801 6264C–CAP–24-Mar-09 41.6.1 Name: Address: Access: 31 – 23 PWM Mode Register PWM_MR 0xFFFB8000 Read-write 30 – 22 29 – 21 28 – 20 DIVB 27 26 PREB 19 18 17 16 25 24 15 – 7 14 – 6 13 – 5 12 – 4 DIVA 11 10 PREA 9 8 3 2 1 0 • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB 0 1 2-255 CLKA, CLKB CLKA, CLKB clock is turned off CLKA, CLKB clock is clock selected by PREA, PREB CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor. • PREA, PREB PREA, PREB 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Other 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK. MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Reserved Divider Input Clock 802 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41.6.2 Name: Address: Access: 31 – 23 – 15 – 7 – PWM Enable Register PWM_ENA 0xFFFB8004 Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. 803 6264C–CAP–24-Mar-09 41.6.3 Name: Address: Access: 31 – 23 – 15 – 7 – PWM Disable Register PWM_DIS 0xFFFB8008 Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x. 804 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41.6.4 Name: Address: Access: 31 – 23 – 15 – 7 – PWM Status Register PWM_SR 0xFFFB800C Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled. 805 6264C–CAP–24-Mar-09 41.6.5 Name: Address: Access: 31 – 23 – 15 – 7 – PWM Interrupt Enable Register PWM_IER 0xFFFB8010 Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x. 806 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41.6.6 Name: Address: Access: 31 – 23 – 15 – 7 – PWM Interrupt Disable Register PWM_IDR 0xFFFB8014 Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x. 807 6264C–CAP–24-Mar-09 41.6.7 Name: Address: Access: 31 – 23 – 15 – 7 – PWM Interrupt Mask Register PWM_IMR 0xFFFB8018 Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled. 808 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41.6.8 Name: Address: Access: 31 – 23 – 15 – 7 – PWM Interrupt Status Register PWM_ISR 0xFFFB801C Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register. Note: Reading PWM_ISR automatically clears CHIDx flags. 809 6264C–CAP–24-Mar-09 41.6.9 Name: PWM Channel Mode Register PWM_CMR[0..3] 0xFFFB8200 [0], 0xFFFB8220 [1], 0xFFFB8240 [2], 0xFFFB8260 [3] Read-write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 26 – 18 – 10 CPD 2 CPRE 25 – 17 – 9 CPOL 1 24 – 16 – 8 CALG 0 Addresses: Access: 31 – 23 – 15 – 7 – • CPRE: Channel Pre-scaler CPRE 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Other 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 CLKA CLKB Reserved Channel Pre-scaler • CALG: Channel Alignment 0 = The period is left aligned. 1 = The period is center aligned. • CPOL: Channel Polarity 0 = The output waveform starts at a low level. 1 = The output waveform starts at a high level. • CPD: Channel Update Period 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1 = Writing to the PWM_CUPDx will modify the period at the next period start event. 810 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41.6.10 Name: PWM Channel Duty Cycle Register PWM_CDTY[0..3] Addresses: 0xFFFB8204 [0], 0xFFFB8224 [1], 0xFFFB8244 [2], 0xFFFB8264 [3] Access: 31 Read-write 30 29 28 CDTY 27 26 25 24 23 22 21 20 CDTY 19 18 17 16 15 14 13 12 CDTY 11 10 9 8 7 6 5 4 CDTY 3 2 1 0 Only the first 20 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx). 811 6264C–CAP–24-Mar-09 41.6.11 Name: PWM Channel Period Register PWM_CPRD[0..3] Addresses: 0xFFFB8208 [0], 0xFFFB8228 [1], 0xFFFB8248 [2], 0xFFFB8268 [3] Access: 31 Read-write 30 29 28 CPRD 27 26 25 24 23 22 21 20 CPRD 19 18 17 16 15 14 13 12 CPRD 11 10 9 8 7 6 5 4 CPRD 3 2 1 0 Only the first 20 bits (internal channel counter size) are significant. • CPRD: Channel Period I f the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: – By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( X × CPRD ) ------------------------------MCK – By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( CRPD × DIVA ) ------------------------------------------ or ( CRPD × DIVAB ) ---------------------------------------------MCK MCK If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: – By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( 2 × X × CPRD ) -----------------------------------------MCK – By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2 × CPRD × DIVA ) ----------------------------------------------------- or ( 2 × CPRD × DIVB ) ----------------------------------------------------MCK MCK 812 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 41.6.12 Name: PWM Channel Counter Register PWM_CCNT[0..3] Addresses: 0xFFFB820C [0], 0xFFFB822C [1], 0xFFFB824C [2], 0xFFFB826C [3] Access: 31 Read-only 30 29 28 CNT 27 26 25 24 23 22 21 20 CNT 19 18 17 16 15 14 13 12 CNT 11 10 9 8 7 6 5 4 CNT 3 2 1 0 • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register). • the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. 813 6264C–CAP–24-Mar-09 41.6.13 Name: PWM Channel Update Register PWM_CUPD[0..3] Addresses: 0xFFFB8210 [0], 0xFFFB8230 [1], 0xFFFB8250 [2], 0xFFFB8270 [3] Access: 31 Write-only 30 29 28 CUPD 27 26 25 24 23 22 21 20 CUPD 19 18 17 16 15 14 13 12 CUPD 11 10 9 8 7 6 5 4 CUPD 3 2 1 0 This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle. Only the first 20 bits (internal channel counter size) are significant. CPD (PWM_CMRx Register) 0 1 The duty-cycle (CDTY in the PWM_CDTYx register) is updated with the CUPD value at the beginning of the next period. The period (CPRD in the PWM_CPRDx register) is updated with the CUPD value at the beginning of the next period. 814 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 42. MultiMedia Card Interface (MCI) 42.1 Description The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. 815 6264C–CAP–24-Mar-09 42.2 Block Diagram Figure 42-1. Block Diagram APB Bridge PDC APB MCCK (1) (1) MCCDA MCI Interface PMC MCK PIO MCDA0 MCDA1 MCDA2 Interrupt Control MCDA3 (1) (1) (1) (1) MCI Interrupt Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. 42.3 Application Block Diagram Figure 42-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 MMC 9 SDCard 816 AT91CAP9S500A/AT91CAP9S250A 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 42.4 Pin Name List I/O Lines Description Pin Description Command/response Clock Data 0..3 of Slot A Type(1) I/O/PP/OD I/O I/O/PP Comments CMD of an MMC or SDCard/SDIO CLK of an MMC or SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO Table 42-1. Pin Name(2)) MCCDA MCCK MCDA0 - MCDA3 Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. 42.5 42.5.1 Product Dependencies I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. Table 42-2. MCI0 MCI0 MCI0 MCI0 MCI0 MCI0 MCI1 MCI1 MCI1 MCI1 MCI1 MCI1 I/O Lines Signal MCI0_CD MCI0_CK MCI0_D0 MCI0_D1 MCI0_D2 MCI0_D3 MCI1_CD MCI1_CK MCI1_D0 MCI1_D1 MCI1_D2 MCI1_D3 I/O Line PA1 PA2 PA0 PA3 PA4 PA5 PA17 PA16 PA18 PA19 PA20 PA21 Peripheral A A A A A A A A A A A A Instance 42.5.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock. Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. Table 42-3. Instance MCI0 MCI1 42.5.3 Peripheral IDs ID 11 12 817 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A 42.6 Bus Topology Figure 42-3. Multimedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 42-4. Pin Number 1 2 3 4 5 6 7 Notes: Bus Topology Name RSV CMD VSS1 VDD CLK VSS2 DAT[0] Type NC I/O/PP/OD S S I/O S I/O/PP (1) Description Not connected Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 MCI Pin Name(2) (Slot z) MCCDz VSS VDD MCCK VSS MCDz0 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. Figure 42-4. MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK 1234567 MMC1 1234567 MMC2 1234567 MMC3 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. Figure 42-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD 818 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A The SD Memory Card bus includes the signals listed in Table 42-5. Table 42-5. Pin Number 1 2 3 4 5 6 7 8 9 Notes: SD Memory Card Bus Signals Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type (1) Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 or Interrupt Data line Bit 2 MCI Pin Name(2) (Slot z) MCDz3 MCCDz VSS VDD MCCK VSS MCDz0 MCDz1 MCDz2 I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. Figure 42-6. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 SD CARD Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 42.7 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. • Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. • Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. 9 819 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 42-6 on page 821. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined: • Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See “Data Transfer Operation” on page 822.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 42.7.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping the MCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC E Z NID Cycles ****** Z S T CID Content Z Z Z 820 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 42-6 and Table 42-7. Table 42-6. CMD Index CMD2 ALL_SEND_CID Command Description Type bcr Argument [31:0] stuff bits Resp R2 Abbreviation ALL_SEND_CID Command Description Asks all cards to send their CID numbers on the CMD line Note: bcr means broadcast command with response. Table 42-7. Field Fields and Values for MCI_CMDR Command Register Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) 0 (not a special command) CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) IOSPCMD (SDIO special command) The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • Fill the argument register (MCI_ARGR) with the command argument. • Set the command register (MCI_CMDR) (see Table 42-7). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. 821 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 42-7. Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? Read response if required RETURN ERROR(1) RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). 42.7.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the mode register MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block. Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes. 822 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (MCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 42.7.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 42-8), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. 823 6264C–CAP–24-Mar-09 AT91CAP9S500A/AT91CAP9S250A Figure 42-8. Read Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card (1) Send SET_BLOCKLEN command No Read with PDC Yes Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght