AT91FR4042

Features • Incorporates the ARM7TDMI™ ARM® Thumb® Processor Core – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-circuit Emulation) 256K Bytes of On-chip SRAM (2 Mbits) – 32-bit Data Bus, Single-clock Cycle Access 256K Words 16-bit Flash Memory (4 Mbits) – Single Voltage Read/Write, 90 ns Access Time – Sector Erase Architecture – Fast Word Program Time of 30 µs (Typical); Fast Sector Erase Time of 10 sec. (Max) – Low-power Operation: 25 mA Active (Read Current, f = 5 MHz, IOUT = 0 mA Typical), 50 µA Standby (Standby Current CMOS: NCSF = VDDIO - 0.3V to VDDIO Maximum) – Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection – Reset Input for Device Initialization – Factory-programmed AT91 Flash Uploader Software Fully Programmable External Bus Interface (EBI) – Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes – Software Programmable 8/16-bit External Data Bus 8-level Priority, Individually Maskable, Vectored Interrupt Controller – 4 External Interrupts, Including a High-priority Low-latency Interrupt Request 32 Programmable I/O Lines 3-channel 16-bit Timer/Counter – 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel 2 USARTs – 2 Dedicated Peripheral Data Controller (PDC) Channels per USART Programmable Watchdog Timer Advanced Power-saving Features – CPU and Peripherals Can be De-activated Individually Fully Static Operation: – 0 Hz to 70 MHz Internal Frequency Range at VDDCORE = 1.65V, 85°C 2.7V to 3.6V I/O and Flash Operating Range, 1.65V to 1.95V Core Operating Range -40°C to 85°C Temperature Range Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch • • AT91 ARM® Thumb® Microcontrollers AT91FR4042 Preliminary • • • • • • • • • • • Description The AT91FR4042 is a member of the Atmel AT91 16/32-bit Microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. The AT91FR4042 ARM microcontroller features 2 Mbits of on-chip SRAM and 4 Mbits of Flash memory in a single compact 121-ball BGA package. Its high level of integration and very small footprint make the device ideal for space-constrained applications. The high-speed on-chip SRAM enables a performance of up to 63 MIPs and significant power reduction over an external SRAM inplementation. The Flash memory may be programmed via the JTAG/ICE interface or the factory-programmed Flash Uploader using a single device supply, making the AT91FR4042 suitable for in-system programmable applications. Rev. 2648B–ATARM–12/02 Preliminary 1 Preliminary Pin Configuration Figure 1. AT91FR4042 Pinout for 121-ball BGA Package (Top View) A1 Corner 1 2 3 4 5 6 7 8 9 10 11 A P21/TXD1 NTRI P22 RXD1 P19 P16 P15 RXD0 GND P11 P8 VDDCORE IRQ2 TIOB2 P10 IRQ1 P9 IRQ0 P7 TIOA2 P3 TCLK1 P6 TCLK2 P4 TIOA1 GND P2 TIOB0 B P20 SCK1 P18 P17 P12 FIQ VDDIO GND P1 TIOA0 C VDDIO GND NUB NWR1 P14 TXD0 P13 SCK0 NBUSY P5 TIOB1 A16 D15 P0 TCLK0 D P23 MCKI NRST VPP NRSTF A14 A15 D12 D14 VDDIO E P24 BMS P25 NWDOVF MCK0 A3 A8 D11 D10 D13 NC NC D3 F GND TMS GND TCK NOE NRD D9 A11 D7 D8 NC NC G TDO NWE NWR0 A2 TDI NCS0 D2 D5 D4 D6 GND NC H P26 VDDCORE VDDIO NCS2 NC NCSF NC D0 D1 P31/A23 CS4 NC NC J NWAIT GND P27 NCS3 A5 NC VDDIO GND GND A19 VDDIO P30/A22 CS5 K NCS1 NLB A0 GND A7 VDDIO A10 A13 GND A17 P29/A21 VDDCORE CS6 L GND A1 A4 A6 VDDIO A9 A12 GND VDDIO A18 P28/A20 CS7 2 AT91FR4042 2648B–ATARM–12/02 AT91FR4042 Pin Description Table 1. AT91FR4042 Pin Description Module Name A0 - A23 D0 - D15 NCS0 - NCS3 CS4 - CS7 NWR0 NWR1 NRD EBI NWE NOE NUB NLB NWAIT BMS FIQ AIC IRQ0 - IRQ2 TCLK0 - TCLK2 Timer TIOA0 - TIOA2 TIOB0 - TIOB2 SCK0 - SCK1 USART TXD0 - TXD1 RXD0 - RXD1 PIO WD Clock MCKO NRST Reset NTRI TMS TDI ICE TDO TCK Test Data Output Test Clock Output Input – – Schmidt trigger, internal pull-up Tri-state Mode Select Test Mode Select Test Data Input Input Input Input Low – – Sampled during reset Schmidt trigger, internal pull-up Schmidt trigger, internal pull-up Master Clock Output Hardware Reset Input Output Input – Low Schmidt trigger P0 - P31 NWDOVF MCKI External Interrupt Request Timer External Clock Multi-purpose Timer I/O Pin A Multi-purpose Timer I/O Pin B External Serial Clock Transmit Data Output Receive Data Input Parallel IO Line Watchdog Overflow Master Clock Input Input Input I/O I/O I/O Output Input I/O Output Input – – – – – – – – Low – Open drain Schmidt trigger PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Function Address Bus Data Bus External Chip Select External Chip Select Lower Byte 0 Write Signal Upper Byte 1 Write Signal Read Signal Write Enable Output Enable Upper Byte Select Lower Byte Select Wait Input Boot Mode Select Fast Interrupt Request Type Output I/O Output Output Output Output Output Output Output Output Output Input Input Input Active Level All – Low High Low Low Low Low Low Low Low Low – – Sampled during reset; must be driven low during reset for Flash to be used as boot memory PIO-controlled after reset Used to select external devices A23 - A20 after reset Used in Byte Write option Used in Byte Write option Used in Byte Write option Used in Byte Select option Used in Byte Select option Used in Byte Select option Used in Byte Select option Comments Valid after reset Preliminary 2648B–ATARM–12/02 3 Preliminary Table 1. AT91FR4042 Pin Description (Continued) Module Flash Memory Name NCSF NBUSY NRSTF VDDIO VDDCORE Power GND VPP Function Flash Memory Select Flash Memory Busy Output Flash Memory Reset Input Power Power Ground Power Type Input Output Input Power Power Ground Power Active Level Low Low Low – – – – Comments Enables Flash Memory when pulled low Flash RDY/BUSY signal; open-drain Resets Flash to standard operating mode All VDDIO, VDDCORE and all GND pins MUST be connected to their respective supplies by the shortest route See AT49BV/LV4096A 4-megabit (256K x 16/512K x 8) Single 2.7 Volt Flash Memory Datasheet 4 AT91FR4042 2648B–ATARM–12/02 EBI: External Bus Interface 2648B–ATARM–12/02 TMS TDO TDI TCK Figure 2. AT91FR4042 Block Diagram Embedded ICE ARM7TDMI Core D0 - D15 A1 - A18 A0/NLB ASB VDDCORE VDDIO GND SRAM 256K Bytes D0-D15 A19 A1- A18 A0/NLB NWR1/NUB NWAIT NCS0 NCS1 NRD/NOE NWR0/NWE P26/NCS2 P27/NCS3 P28/A20/CS7 P29/A21/CS6 P30/A22/CS5 P31/A23/CS4 D0 - D15 A0 - A17 OE WE GND VPP VCC VCCQ GND VPP VDDIO VDDIO VDDIO NRSTF NBUSY NCSF P0/TCLK0 P3/TCLK1 P6/TCLK2 P1/TIOA0 P2/TIOB0 P4/TIOA1 P5/TIOB1 P7/TIOA2 P8/TIOB2 NRST Reset MCKI P25/MCKO Clock ASB Controller AMBA Bridge P12/FIQ P9/IRQ0 P10/IRQ1 P11/IRQ2 P13/SCK0 P14/TXD0 P15/RXD0 P20/SCK1 P21/TXD1/NTRI P22/RXD1 P16 P17 P18 P19 P23 P24/BMS P I O AIC: Advanced Interrupt Controller APB USART0 2 PDC Channels EBI User Interface MCU AT91R40008 P I O FLASH MEMORY AT49BV4096A USART1 2 PDC Channels BYTE RESET RDY/BUSY CE Preliminary 5 PS: Power Saving TC: Timer Counter TC0 TC1 Chip ID NWDOVF WD: Watchdog Timer PIO: Parallel I/O Controller TC2 AT91FR4042 Preliminary Architectural Overview The AT91FR4042 integrates Atmel’s AT91R40008 ARM Thumb processor and an AT49BV4096A 4-Mbit Flash memory die in a single compact 121-ball BGA package. The address, data and control signals, except the Flash memory enable, are internally interconnected. The AT91R40008 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-chip 32-bit SRAM memory, the External Bus Interface (EBI) connected to the encapsulated Flash and the AMBA™ Bridge. The AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized for low power consumption. The AT91FR4042 implements the ICE port of the ARM7TDMI processor on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target debugging. Memories The AT91FR4042 embeds 256K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 63 MIPS at 70 MHz by using the ARM instruction set of the processor, minimizing system power consumption and improving on the performance of separate memory solutions. The AT91FR4042 features an External Bus Interface (EBI), which enables connection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the early read protocol, enabling faster memory accesses than standard memory interfaces. The AT91FR4042 encapsulates a Flash memory organized as 256K 16-bit words, accessed via the EBI. A 16-bit Thumb instruction can be loaded from Flash memory in a single access. Separate MCU and Flash memory reset inputs (NRST and NRSTF) are provided for maximum flexibility. The user is thus free to tailor the reset operation to the application. The AT91FR4042 integrates resident boot software called AT91 Flash Uploader software in the encapsulated Flash. The AT91 Flash Uploader software is able to upload program application software into its Flash memory. Peripherals The AT91FR4042 integrates several peripherals, which are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can be programmed with a minimum number of instructions. The peripheral register set is composed of control, mode, data, status and enable/disable/status registers. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and on- and off-chip memory address space without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead, making it possible to transfer up to 64K contiguous bytes without reprogramming the start address, thus increasing the performance of the microcontroller, and reducing the power consumption. System Peripherals The External Bus Interface (EBI) controls the external memory or peripheral devices via an 8- or 16-bit databus and is programmed through the APB. Each chip select line has its own programming register. 6 AT91FR4042 2648B–ATARM–12/02 AT91FR4042 The Power-saving (PS) module implements the Idle Mode (ARM7TDMI core clock stopped until the next interrupt) and enables the user to adapt the power consumption of the microcontroller to application requirements (independent peripheral clock control). The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal peripherals and the four external interrupt lines (including the FIQ) to provide an interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller, and, using the Auto-vectoring feature, reduces the interrupt latency time. The Parallel Input/Output Controller (PIO) controls up to 32 I/O lines. It enables the user to select specific pins for on-chip peripheral input/output functions, and general-purpose input/output signal pins. The PIO controller can be programmed to detect an interrupt on a signal change from each line. The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in a deadlock. The Special Function (SF) module integrates the Chip ID, the Reset Status and the Protect registers. User Peripherals Two USARTs, independently configurable, enable communication at a high baud rate in synchronous or asynchronous mode. The format includes start, stop and parity bits and up to 8 data bits. Each USART also features a Timeout and a Time Guard register, facilitating the use of the two dedicated Peripheral Data Controller (PDC) channels. The 3-channel, 16-bit Timer Counter (TC) is highly programmable and supports capture or waveform modes. Each TC channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. The TC has also 3 external clock signals. Preliminary 2648B–ATARM–12/02 7 Preliminary Associated Documentation Table 2. Associated Documentation Product Information Internal architecture of processor ARM/Thumb instruction sets Embedded in-circuit emulator External memory interface mapping Peripheral operations Peripheral user interfaces DC characteristics Power consumption Thermal and reliability considerations AC characteristics Product overview Ordering information Packaging information Soldering profile Detailed description of Flash memory MCU Flash Memory Document Title ARM7TDMI (Thumb) Datasheet AT91x40 Series Datasheet AT91R40008 Electrical Characteristics Datasheet AT49BV/LV4096A 4 megabit (256K x 16/512K x 8) Single 2.7 Volt Flash Memory Datasheet AT91FR4042 AT91FR4042 Datasheet (this document) AT49BV/LV4096A 4 megabit (256K x 16/512K x 8) Single 2.7 Volt Flash Memory Datasheet 8 AT91FR4042 2648B–ATARM–12/02 AT91FR4042 Product Overview Power Supply The AT91FR4042 device has two types of power supply pins: • • VDDCORE pins that power the chip core (i.e., the AT91R40008 with its embedded SRAM and peripherals) VDDIO pins that power the AT91R40008 I/O lines and the Flash memory An independent I/O supply allows a flexible adaptation to external component signal levels. Input/Output Considerations The AT91FR4042 I/O pads accept voltage levels up to the VDDIO power supply limit. After the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption. The AT91FR4042 has a fully static design and works on the Master Clock (MCK), provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multiplexed with a general purpose I/O line. While NRST is active, and after the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use this pin as standard I/O line. Master Clock Reset Reset restores the default states of the user interface registers (defined in the user interface of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter the ARM7TDMI registers do not have defined reset states. NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST. The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority. NRST Pin Watchdog Reset Emulation Functions Tri-state Mode The AT91FR4042 microcontroller provides a tri-state mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In tri-state mode, all the output pin drivers of the AT91R40008 microcontroller are disabled. In tri-state mode, direct access to the Flash via external pins is provided. This enables production Flash programming using classical Flash programmers prior to board mounting. Preliminary 2648B–ATARM–12/02 9 Preliminary To enter tri-state mode, the NTRI pin must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation, the NTRI pin must be held high during reset by a resistor of up to 400 kΩ. NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1. JTAG/ICE Debug ARM-standard embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host computer via the external ICE interface. In ICE Debug Mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant. The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces: • • • Internal memories in the four lowest megabytes Middle space reserved for the external devices (memory or peripherals) controlled by the EBI Internal peripherals in the four highest megabytes Memory Controller In any of these address spaces, the ARM7TDMI operates in little-endian mode only. Internal Memories The AT91FR4042 microcontroller integrates 256K bytes of internal SRAM. It is 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) and word (32-bit) accesses are supported and are executed within one cycle. Fetching either Thumb or ARM instructions is supported, and internal memory can store two times as many Thumb instructions as ARM instructions. The SRAM is mapped at address 0x0 (after the Remap command), allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontroller performance and minimizes system power consumption. The 32-bit bus increases the effectiveness of the use of the ARM instruction set and the processing of data that is wider than 16 bits, thus making optimal use of the ARM7TDMI advanced performance. Being able to dynamically update application software in the 256-Kbyte SRAM adds an extra dimension to the AT91FR4042. The AT91FR4042 also integrates a 4-Mbit Flash memory that is accessed via the External Bus Interface. All data, address and control lines, except for the Chip Select signal, are connected within the device. Boot Mode Select The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory (see Table 1). If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled down externally and NCS0 must be connected to NCSF externally. 10 AT91FR4042 2648B–ATARM–12/02 AT91FR4042 The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any standard PIO line. Table 3. Boot Mode Select BMS 1 0 Boot Memory External 8-bit memory on NCS0 External 16-bit memory on NCS0 Remap Command The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91FR4042 uses a remap command that enables switching between the boot memory and the internal primary SRAM bank addresses. The remap command is accessible through the EBI User Interface by writing one in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to the other external devices (connected to chip selects 1 to 7) is required. The remap operation can only be changed back by an internal reset or an NRST assertion. The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is asserted when accessing an undefined address in the EBI address space. No abort is generated when reading the internal memory or by accessing the internal peripherals, whether the address is defined or not. Abort Control External Bus Interface The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0 0000. It generates the signals that control access to the external devices, and can be configured from eight 1-Mbyte banks up to four 16-Mbyte banks. It supports byte, half-word and word aligned accesses. For each of these banks, the user can program: • • • • Number of wait states Number of data float times (wait time after the access is finished to prevent any bus contention in case the device is too long in releasing the bus) Data bus width (8-bit or 16-bit) With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16bit memory (Byte Write Access Mode). The External Bus Interface features also the Early Read Protocol, configurable for all the devices, that significantly reduces access time requirements on an external device in the case of single-clock cycle access. In the AT91FR4042, the External Bus Interface connects internally to the Flash memory. Flash Memory The 4-Mbit Flash memory is organized as 262144 words of 16 bits each. The Flash memory is addressed as 16-bit words via the EBI. It uses address lines A1 - A18. The address, data and control signals, except the Flash memory enable, are internally interconnected. The user should connect the Flash memory enable (NCSF) to one of the active-low chip selects on the EBI; NCS0 must be used if the Flash memory is to be the boot memory. In addition, if the Flash memory is to be used as boot memory, the BMS input must be pulled down externally in order for the processor to perform correct 16-bit fetches after reset. Preliminary 2648B–ATARM–12/02 11 Preliminary During boot, the EBI must be configured with correct number of standard wait states. As an example, five standard wait states are required when the microcontroller is running at 66 MHz. The user must ensure that all VDDIO, VDDCORE and all GND pins are connected to their respective supplies by the shortest route. The Flash memory powers-on in read mode. Command sequences are used to place the device in other operating modes, such as program and erase. A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility, enabling the reset operation to adapt to the application. When this input is at a logic high level, the memory is in its standard operating mode; a low level on this input halts the current memory operation and puts its outputs in a high impedance state. The Flash memory features data polling to detect the end of a program cycle. While a program cycle is in progress, an attempted read of the last word written will return the complement of the written data on I/O7. An open-drain NBUSY output pin provides another method of detecting the end of a program or erase cycle. This pin is pulled low while program and erase cycles are in progress and is released at the completion of the cycle. A toggle bit feature provides a third means of detecting the end of a program or erase cycle. The Flash memory is divided into 4 sectors for erase operations. The device has the capability to protect data stored in the 8K words boot block sector. Once the data protection for this sector is enabled, the data in the sector cannot be changed while input levels lie between ground and VDDIO. The address range of the boot block is 00000h to 01FFFh The user can override the boot block programing lockout by applying a 12V input signal to the RESET pin while performing a chip erase, sector erase or word programing operation. A 4-byte command sequence (Enter Single Pulse Program Mode) allows the device to be written to directly, using single pulses on the write control lines. This mode (Singlepulse Programming) is exited by powering down the device or by pulsing the NRSTF pin low for a minimum of 50 ns and then bringing it back to VDDIO. The following hardware features protect against inadvertent programming of the Flash memory: • • • • VDDIO Sense – if VDDIO is below 1.8V (typical), the program function is inhibited. VDDIO Power-on Delay – once VDDIO has reached the VDDIO sense level, the device will automatically time out 10 ms (typically) before programming. Program Inhibit – holding any one of OE low, CE high or WE high inhibits program cycles. Noise Filter – pulses of less than 15 ns (typical) on the WE or CE inputs will not initiate a program cycle. See the AT49BV4096A 4-megabit (256K x 16/512K x 8) Single 2.7 volt Flash Memory Datasheet for further details on Flash operation and electrical characteristics. 12 AT91FR4042 2648B–ATARM–12/02 AT91FR4042 AT91 Flash Uploader Software All Flash-based AT91 devices are delivered with a pre-programmed software called the AT91 Flash Uploader, which resides in the first sector of the embedded Flash. The Flash Uploader allows programming to the embedded flash through a serial port. Either of the on-chip USARTs can be used by the Flash Uploader. Figure 3. Flash Uploader Target System AT91FR4042 AT49BV4096A Flash Memory NCSF AT91R40008 RXD0 NCS0 Programming System USART0 RS232 Driver USART1 RXD1 Serial Port Flash Uploader Operations The Flash Uploader requires the encapsulated Flash to be used as the AT91FR4042 boot memory and a valid clock to be applied to MCKI. After reset, the Flash Uploader immediately recopies itself into the internal SRAM and jumps to it. The following operation requires this memory resource only. External accesses are performed only to program the encapsulated Flash. When starting, PIO input change interrupts are initialized on the RXD lines of both USARTs. When an interrupt occurs, a Timer Counter channel is started. When the next input change is detected on the RXD line, the Timer Counter channel is stopped. This is how the first character length is measured and the USART can be initiated by taking into account the ratio between the device master clock speed and the actual communication baud rate speed. The Programming System, then, can send commands and data following a proprietary protocol for the Flash device to be programmed. It is up to the Programming System to erase and program the first sector of the Flash as the last step of the operation, in order to reduce, to a minimum, the risk that the Flash Uploader is erased and the power supply shuts down. Note that in the event that the Flash Uploader is erased from the first sector while the new final application is not yet programmed, and while the target system power supply is switched off, it leads to a non-recoverable error and the AT91FR4042 cannot be reprogrammed by using the Flash Uploader. Preliminary 2648B–ATARM–12/02 13 Preliminary Programming System Atmel provides a free Host Loader that runs on an IBM® c ompatible PC under Windows®95 or Windows®98 operating system. It can be downloaded from the Atmel Web site and requires only a serial cable to connect the Host to the Target. Communications can be selected on either COM1 or COM2 and the serial link speed is limited to 115200 bauds. Because the serial link is the bottleneck in this configuration, the Flash programming lasts 110 seconds per Mbyte. Reduced programming time can be achieved by using a faster programming system. An AT91 Evaluation Board is capable of running a serial link at up to 500 Kbits/sec and can match the fastest programming allowed by the Flash, for example, about 40 seconds per Mbyte when the word programming becomes the bottleneck. Peripherals The AT91FR4042 peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible. Byte and half-word accesses are not supported. If a byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access. Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address space). Peripheral Registers The following registers are common to all peripherals: • Control Register – write only register that triggers a command when a one is written to the corresponding position at the appropriate address. Writing a zero has no effect. Mode Register – read/write register that defines the configuration of the peripheral. Usually has a value of 0x0 after a reset. Data Registers – read and/or write register that enables the exchange of data between the processor and the peripheral. Status Register – read only register that returns the status of the peripheral. Enable/Disable/Status Registers are shadow command registers. Writing a one in the Enable Register sets the corresponding bit in the Status Register. Writing a one in the Disable Register resets the corresponding bit and the result can be read in the Status Register. Writing a bit to zero has no effect. This register access method maximizes the efficiency of bit manipulation, and enables modification of a register with a single non-interruptible instruction, replacing the costly read-modify-write operation. • • • • Unused bits in the peripheral registers must be written at 0 for upward compatibility. These bits read 0. Peripheral Interrupt Control The Interrupt Control of each peripheral is controlled from the status register using the interrupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller. The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask) makes it possible to enable or disable peripheral interrupt sources with a noninterruptible single instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-time and multi-tasking systems. 14 AT91FR4042 2648B–ATARM–12/02 AT91FR4042 Peripheral Data Controller The AT91FR4042 has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC channel is dedicated to the receiver and one to the transmitter of each USART. The user interface of a PDC channel is integrated in the memory space of each USART. It contains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer Counter Register (RCR or TCR). When the programmed number of transfers are performed, a status bit indicating the end of transfer is set in the USART Status Register and an interrupt can be generated. Preliminary 2648B–ATARM–12/02 15 Preliminary System Peripherals PS: Power-saving The power-saving feature optimizes power consumption, enabling the software to stop the ARM7TDMI clock (idle mode), restarting it when the module receives an interrupt (or reset). It also enables on-chip peripheral clocks to be enabled and disabled individually, matching power consumption and application needs. The Advanced Interrupt Controller has an 8-level priority, individually maskable, vectored interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from: • • • The external fast interrupt line (FIQ) The three external interrupt request lines (IRQ0 - IRQ2) The interrupt signals from the on-chip peripherals AIC: Advanced Interrupt Controller The AIC is extensively programmable offering maximum flexibility, and its vectoring features reduce the real-time overhead in handling interrupts. The AIC also features a spurious vector detection feature, which reduces spurious interrupt handling to a minimum, and a protect mode that facilitates the debug capabilities. PIO: Parallel I/O Controller The AT91FR4042 has 32 programmable I/O lines. Six pins are dedicated as generalpurpose I/O pins. Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO controller enables generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins. The Watchdog is built around a 16-bit counter and is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt, or assert an active level on the dedicated pin NWDOVF. All programming registers are password-protected to prevent unintentional programming. The AT91FR4042 provides registers that implement the following special functions. • • • Chip Identification RESET Status Protect Mode WD: Watchdog SF: Special Function 16 AT91FR4042 2648B–ATARM–12/02 AT91FR4042 User Peripherals USART: Universal Synchronous/ Asynchronous Receiver Transmitter The AT91FR4042 provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters. Each USART has its own baud rate generator, and two dedicated Peripheral Data Controller channels. The data format includes a start bit, up to 8 data bits, an optional programmable parity bit and up to 2 stop bits. The USART also features a Receiver Timeout register, facilitating variable length frame support when it is working with the PDC, and a Time-guard register, used when interfacing with slow remote equipment. TC: Timer Counter The AT91FR4042 features a Timer Counter block that includes three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. The Timer Counter can be used in Capture or Waveform mode, and all three counter channels can be started simultaneously and chained together. Preliminary 2648B–ATARM–12/02 17 Preliminary Ordering Information Table 4. Ordering Information Ordering Code AT91FR4042-CI Package BGA 121 Temperature Operating Range Industrial (-40°C to 85°C) 18 AT91FR4042 2648B–ATARM–12/02 AT91FR4042 Packaging Information Figure 4. AT91FR4042 Package Table 5. Thermal Resistance Data Symbol θJA θJC Parameter Junction-toambient thermal resistance Junction-to-case thermal resistance Condition Still Air °C/W 121-BGA TBD Package 121-BGA Typ TBD Units Table 6. Device and 121-ball BGA Package Maximum Weight TBD mg Preliminary 2648B–ATARM–12/02 19 Preliminary Soldering Profile Table 7 gives the recommended soldering profile from J-STD-20. Table 7. Soldering Profile Convection or IR/Convection Average Ramp-up Rate (183°C to Peak) Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature 3°C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max 60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec. VPR 10°C/sec. Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 8. Table 8. Recommended Package Reflow Conditions (1, 2, 3) Parameter Convection VPR IR/Convection Notes: Temperature 220 +5/-0°C 215 to 219°C 220 +5/-0°C 1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220°C (unless 235°C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. A maximum of three reflow passes is allowed per component. 20 AT91FR4042 2648B–ATARM–12/02 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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