AT91M42800A-33CJ

Features • Utilizes the ARM7TDMI® ARM® Thumb® Processor Core – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-circuit Emulation) 8K Bytes Internal SRAM Fully Programmable External Bus Interface (EBI) – Maximum External Address Space of 64M Bytes – Up to 8 Chip Selects – Software Programmable 8/16-bit External Data Bus 8-channel Peripheral Data Controller 8-level Priority, Individually Maskable, Vectored Interrupt Controller – 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request 54 Programmable I/O Lines 6-channel 16-bit Timer/Counter – 6 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel 2 USARTs – 2 Dedicated Peripheral Data Controller (PDC) Channels per USART – Support for up to 9-bit Data Transfers 2 Master/Slave SPI Interfaces – 2 Dedicated Peripheral Data Controller (PDC) Channels per SPI – 8- to 16-bit Programmable Data Length – 4 External Slave Chip Selects per SPI 3 System Timers: – Period Interval Timer (PIT); Real-time Timer (RTT); Watchdog Timer (WDT) Power Management Controller (PMC) – CPU and Peripherals Can be Deactivated Individually Clock Generator with 32.768 kHz Low-power Oscillator and PLL – Support for 38.4 kHz Crystals – Software Programmable System Clock (up to 33 MHz) IEEE® 1149.1 JTAG Boundary Scan on All Active Pins Fully Static Operation: 0 Hz to 33 MHz Internal Frequency Range at VDDCORE = 3.0V, 85° C 2.7V to 3.6V Core and PLL Operating Voltage Range; 2.7V to 5.5V I/O Operating Voltage Range -40° C to +85° C Temperature Range Available in a 144-lead LQFP Package (Green) and a 144-ball BGA Package (RoHScompliant) • • • • • • • AT91 ARM Thumb Microcontrollers AT91M42800A Summary • • • • • • • • • 1. Description The AT91M42800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91 ARM-based MCU family also features Atmel’s high-density, insystem programmable, nonvolatile memory technology. The AT91M42800A has a direct connection to off-chip memory, including Flash, through the External Bus Interface. Rev. 1779ES–ATARM–14-Apr-06 Note: This is a summary document. A complete document is available on our web site at www.atmel.com. The Power Management Controller allows the user to adjust device activity according to system requirements, and, with the 32.768 kHz low-power oscillator, enables the AT91M42800A to reduce power requirements to an absolute minimum. The AT91M42800A is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with onchip SRAM and a wide range of peripheral functions including timers, serial communication controllers and a versatile clock generator on a monolithic chip, the AT91M42800A provides a highly-flexible and cost-effective solution to many compute-intensive applications. 2. Pin Configuration Figure 2-1. Pin Configuration in LQFP144 Package (Top View) 108 109 73 72 AT91M42800 33AI 144 37 1 36 2 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A Figure 2-2. Pin Configuration in BGA144 Package (Top View) 1 2 3 4 5 6 7 8 9 10 11 12 A B C D E F G H J K L M 3 1779ES–ATARM–14-Apr-06 Table 2-1. Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 AT91M42800A Pinout in LQFP 144 Package Name GND GND NLB/A0 A1 A2 A3 A4 A5 A6 A7 A8 VDDIO GND A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 VDDIO GND A19 PB2/A20/CS7 PB3/A21/CS6 PB4/A22/CS5 PB5/A23/CS4 D0 D1 D2 D3 VDDCORE VDDIO Pin# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name GND GND D4 D5 D6 D7 D8 D9 D10 D11 D12 VDDIO GND D13 D14 D15 PB6/TCLK0 PB7/TIOA0 PB8/TIOB0 PB9/TCLK1 PB10/TIOA1 PB11/TIOB1 PB12/TCLK2 VDDIO GND PB13/TIOA2 PB14/TIOB2 PB15/TCLK3 PB16/TIOA3 PB17/TIOB3 PB18/TCLK4 PB19/TIOA4 PB20/TIOB4 PB21/TCLK5 VDDCORE VDDIO Pin# 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name GND GND PB22/TIOA5 PB23/TIOB5 PA0/IRQ0 PA1/IRQ1 PA2/IRQ2 PA3/IRQ3 PA4/FIQ PA5/SCK0 PA6/TXD0 VDDIO GND PA7/RXD0 PA8/SCK1 PA9/TXD1/NTRI PA10/RXD1 PA11/SPCKA PA12/MISOA PA13/MOSIA PA14/NPCSA0/NSSA PA15/NPCSA1 PA16/NPCSA2 VDDIO GND PA17/NPCSA3 PA18/SPCKB PA19/MISOB PA20/MOSIB PA21/NPCSB0/NSSB PA22/NPCSB1 PA23/NPCSB2 PA24/NPCSB3 PA25/MCKO VDDCORE VDDIO Pin# 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name GND GND PA26 MODE0 XIN XOUT GND PLLRCA VDDPLL PLLRCB VDDPLL VDDIO GND NWDOVF PA27/BMS MODE1 TMS TDI TDO TCK NTRST NRST PA28 VDDIO GND PA29/PME NWAIT NOE/NRD NWE/NWR0 NUB/NWR1 NCS0 NCS1 PB0/NCS2 PB1/NCS3 VDDCORE VDDIO 4 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A Table 2-2. Pin# A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 AT91M42800A Pinout in BGA 144 Package Name PB1/NCS3 NCS0 NCS1 GND PLLRCB GND PLLRCA GND XOUT XIN MODE0 PA22/NPCSB1 NUB/NWR1 PB0/NCS2 VDDCORE NWE/NWR0 VDDPLL TDO VDDPLL NWDOVF PA26 PA19/MISOB PA24/NPCSB3 PA23/NPCSB2 NLB/A0 A1 VDDIO NOE/NRD VDDIO NRST TDI VDDIO PA27/BMS VDDIO VDDCORE PA20/MOSIB Pin# D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 Name A2 A3 A4 NWAIT PA29/PME PA28 TCK TMS MODE1 PA25/MCKO PA21/NPCSB0 PA18/SPCKB A7 VDDIO A6 A5 GND GND GND NTRST PA13/MOSIA PA16/NPCSA2 VDDIO PA17/NPCSA3 A8 A12 A9 A10 GND GND GND GND PA12/MISOA PA15/NPCSA1 PA11/SPCKA PA14/NPCSA0 Pin# G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 Name A17 A16 A11 A13 GND GND GND GND PA9/TXD1/NTRI PA10/RXD1 PA8/SCK1 PA7/RXD0 A18 VDDIO A15 A14 A19 GND GND GND PA6/TXD0 PA4/FIQ VDDIO PA5/SCK0 PB5/A23/CS4 D0 PB4/A22/CS5 PB3/A21/CS6 PB2/A20/CS7 D15 PB6/TCLK0 PB10/TIOA1 PA3/IRQ3 PA2/IRQ2 PA0/IRQ0 PA1/IRQ1 Pin# K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Name D1 VDDCORE VDDIO D9 D10 D14 PB9/TCLK1 PB13/TIOA2 PB11/TIOB1 VDDIO PB16/TIOA3 PB23/TIOB5 D3 D2 D5 D8 VDDIO D13 PB8/TIOB0 VDDIO PB17/TIOB3 VDDCORE PB20/TIOB4 PB22/TIOA5 D4 D6 D7 D11 D12 PB7/TIOA0 PB12/TCLK2 PB15/TCLK3 PB14/TIOB2 PB18/TCLK4 PB19/TIOA4 PB21/TCLK5 5 1779ES–ATARM–14-Apr-06 3. Pin Description Table 3-1. Module AT91M42800A Pin Description Name A0 - A23 D0 - D15 CS4 - CS7 NCS0 - NCS3 NWR0 NWR1 NRD Function Address Bus Data Bus Chip Select Chip Select Lower Byte 0 Write Signal Lower Byte 1 Write Signal Read Signal Write Enable Output Enable Upper Byte Select (16-bit SRAM) Lower Byte Select (16-bit SRAM) Wait Input Boot Mode Select Protect Mode Enable External Interrupt Request Fast External Interrupt Request Timer External Clock Multi-purpose Timer I/O Pin A Multi-purpose Timer I/O Pin B External Serial Clock Transmit Data Output Receive Data Input Clock Master In Slave Out Master Out Slave In Slave Select Peripheral Chip Selects Programmable I/O Port A Programmable I/O Port B Watchdog Timer Overflow Type Output I/O Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input I/O I/O I/O Output Input I/O I/O I/O Input Output I/O I/O Output Active Level – – High Low Low Low Low Low Low Low Low Low – High – – – – – – – – – – – Low Low – – Low Sampled during reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset PIO-controlled after reset Input after reset Input after reset Open drain Used in Byte Write option Used in Byte Write option Used in Byte Write option Used in Byte Select option Used in Byte Select option Used in Byte Select option Used in Byte Select option A23 - A20 after reset Comments All valid after reset EBI NWE NOE NUB NLB NWAIT BMS PME IRQ0 - IRQ3 AIC FIQ TCLK0 - TCLK5 TC TIOA0 - TIOA5 TIOB0 - TIOB5 SCK0 - SCK1 USART TXD0 - TXD1 RXD0 - RXD1 SPCKA/SPCKB MISOA/MISOB SPIA SPIB MOSIA/MOSIB NSSA/NSSB NPCSA0 - NPCSA3 NPCSB0 - NPCSB3 PA0 - PA29 PIO PB0 - PB23 ST NWDOVF 6 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A Table 3-1. Module AT91M42800A Pin Description (Continued) Name XIN XOUT Function Oscillator Input or External Clock Oscillator Output RC Filter for PLL A RC Filter for PLL B Clock Output Hardware Reset Input Mode Selection Test Mode Select Test Data In Test Data Out Test Clock Test Reset Input Tri-state Mode Enable I/O Power Core Power PLL Power Ground Type Input Output Input Input Output Input Input Input Input Output Input Input Input Power Power Power Ground Active Level – – – – – Low – – – – – Low Low – – – – Schmitt trigger, internal pull-up Schmitt trigger, internal pull-up Sampled during reset 3V or 5V nominal supply 3V nominal supply 3V nominal supply Schmitt trigger, internal pull-up Schmitt trigger, internal pull-up Schmitt trigger Comments CLOCK PLLRCA PLLRCB MCKO Test and Reset NRST MODE0 - MODE1 TMS TDI JTAG/ICE TDO TCK NTRST Emulation NTRI VDDIO VDDCORE Power VDDPLL GND 7 1779ES–ATARM–14-Apr-06 4. Block Diagram Figure 4-1. AT91M42800A NTRST TMS TDO TDI TCK JTAGSEL Embedded ICE Reset NRST JTAG MODE0 MODE1 ARM7TDMI Core ASB D0-D15 A0/NLB A1-A19 NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0 NCS1 PA27/BMS PA29/PME PB0/NCS2 PB1/NCS3 PB2/A20/CS7 PB3/A21/CS6 PB4/A22/CS5 PB5/A23/CS4 PLLRCA PLLRCB Clock Generator Internal RAM 8K Bytes PA25/MCKO PA26 PA28 PA0/IRQ0 PA1/IRQ1 PA2/IRQ2 PA3/IRQ3 PA4/FIQ PA5/SCK0 PA6/TXD0 PA7/RXD0 PA8/SCK1 PA9/TXD1/NTRI PA10/RXD1 PA11/SPCKA PA12/MISOA PA13/MOSIA PA14/NPCSA0/NSSA PA15/NPCSA1 PA16/NPCSA2 PA17/NPCSA3 PA18/SPCKB PA19/MISOB PA20/MOSIB PA21/NPCSB0/NSSB PA22/NPCSB1 PA23/NPCSB2 PA24/NPCSB3 ASB Controller AMBA™ Bridge AIC: Advanced Interrupt Controller EBI User Interface TC: Timer/ Counter Block 0 APB USART1 P I O SPIA: Serial Peripheral Interface 2 PDC Channels TC0 TC1 TC2 2 PDC Channels TC: Timer/ Counter Block 1 TC3 SPIB: Serial Peripheral Interface TC4 TC5 System Timers PMC: Power Management Controller Watchdog Real-time Chip ID Period Interval P I O EBI: External Bus Interface XIN XOUT USART0 2 PDC Channels PB6/TCLK0 PB9/TCLK1 PB12/TCLK2 PB7/TIOA0 PB8/TIOB0 PB10/TIOA1 PB11/TIOB1 PB13/TIOA2 PB14/TIOB2 PB15/TCLK3 PB18/TCLK4 PB21/TCLK5 PB16/TIOA3 PB17/TIOB3 PB19/TIOA4 PB20/TIOB4 PB22/TIOA5 PB23/TIOB5 2 PDC Channels NWDOVF PIO: Parallel I/O Controller 8 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A 5. Architectural Overview The AT91M42800A microcontroller integrates an ARM7TDMI with its embedded ICE interface, memories and peripherals. Its architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the onchip 32-bit memories, the External Bus Interface (EBI) and the AMBA™ Bridge. The AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized for low power consumption. The AT91M42800A microcontroller implements the ICE port of the ARM7TDMI processor on dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target debugging. 5.1 Memories The AT91M42800A microcontroller embeds up to 8K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 30 MIPS at 33 MHz by using the ARM instruction set of the processor. The on-chip memory significantly reduces the system power consumption and improves its performance over external memory solutions. The AT91M42800A microcontroller features an External Bus Interface (EBI), which enables connection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the early read protocol, enabling faster single clock cycle accesses two times faster than standard memory interfaces. 5.2 Peripherals The AT91M42800A microcontroller integrates several peripherals, which are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can be programmed with a minimum number of instructions. The peripheral register set is composed of control, mode, data, status and enable/disable/status registers. An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPIs and the on- and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K continuous bytes without reprogramming the start address. As a result, the performance of the microcontroller is increased and the power consumption reduced. 5.2.1 System Peripherals The External Bus Interface (EBI) controls the external memory and peripheral devices via an 8or 16-bit data bus and is programmed through the APB. Each chip select line has its own programming register. The Power Management Controller (PMC) optimizes power consumption of the product by controlling the clocking elements such as the oscillator and the two PLLs, system and user peripheral clocks. The Advanced Interrupt Controller (AIC) controls the internal sources from the internal peripherals and the five external interrupt lines (including the FIQ) to provide an interrupt and/or fast 9 1779ES–ATARM–14-Apr-06 interrupt request to the ARM7TDMI. It integrates an 8-level priority controller, and, using the Auto-vectoring feature, reduces the interrupt latency time. The Parallel Input/Output Controllers (PIOA, PIOB) controls up to 54 I/O lines. It enables the user to select specific pins for on-chip peripheral input/output functions, and general-purpose input/output signal pins. The PIO controllers can be programmed to detect an interrupt on a signal change from each line. There are three embedded system timers. The Real-time Timer (RTT) counts elapsed seconds and can generate periodic or programmed interrupts. The Period Interval Timer (PIT) can be used as a user-programmable time-base, and can generate periodic ticks. The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in a deadlock. The Special Function (SF) module integrates the Chip ID and the Reset Status registers. 5.2.2 User Peripherals Two USARTs, independently configurable, enable communication at a high baud rate in synchronous or asynchronous mode. The format includes start, stop and parity bits and up to 9 data bits. Each USART also features a Time-out and a Time-guard register, facilitating the use of the two dedicated Peripheral Data Controller (PDC) channels. The two 3-channel, 16-bit Timer/Counters (TC) are highly-programmable and support capture or waveform modes. Each TC channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. Each TC also has three external clock signals. Two independently configurable SPIs provide communication with external devices in master or slave mode. Each has four external chip selects which can be connected to up to 15 devices. The data length is programmable, from 8- to 16-bit. 6. Associated Documentation Table 6-1. Product Associated Documentation Information Internal architecture of processor ARM/Thumb instruction sets Embedded in-circuit-emulator External memory interface mapping Peripheral operations Peripheral user interfaces Document Title ARM7TDMI (Thumb) Datasheet AT91M42800A Datasheet AT91M42800A DC characteristics Power consumption Thermal and reliability considerations AC characteristics Product overview Ordering information Packaging information Soldering profile AT91M42800A Electrical Characteristics AT91M42800A Summary Datasheet (this document) 10 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A 7. Product Overview 7.1 Power Supply The AT91M42800A has three kinds of power supply pins: • VDDCORE pins, which power the chip core • VDDIO pins, which power the I/O lines • VDDPLL pins, which power the oscillator and PLL cells VDDCORE and VDDIO pins allow core power consumption to be reduced by supplying it with a lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage greater than the supply voltage applied to the VDDIO. The VDDPLL pin is used to supply the oscillator and both PLLs. The voltage applied on these pins is typically 3.3V, and it must not be lower than VDDCORE. Typical supported voltage combinations are shown in the following table: Pins VDDCORE VDDIO VDDPLL 3.3V 5.0V 3.3V Nominal Supply Voltages 3.0V or 3.3V 3.0V or 3.3V 3.0V or 3.3V 7.2 Input/Output Considerations After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the AT91M42800A microcontroller be held at valid logic levels to minimize the power consumption. 7.3 Operating Modes The AT91M42800A has two pins dedicated to defining MODE0 and MODE1 operating modes. These pins allow the user to enter the device in Boundary Scan mode. They also allow the user to run the processor from the on-chip oscillator and from an external clock by bypassing the onchip oscillator. The last mode is reserved for test purposes. A chip reset must be performed (NRST and NTRST) after MODE0 and/or MODE1 have been changed. MODE0 0 0 1 1 MODE1 0 1 0 1 Operating Mode Normal operating mode by using the on-chip oscillator Boundary Scan Mode Normal operating mode by using an external clock on XIN Reserved for test 7.4 Clock Generator The AT91M42800A microcontroller embeds a 32.768 kHz oscillator that generates the Slow Clock (SLCK). This on-chip oscillator can be bypassed by setting the correct logical level on MODE0 and MODE1 pins, as shown above. In this case, SLCK equals XIN. 11 1779ES–ATARM–14-Apr-06 The AT91M42800A microcontroller has a fully static design and works either on the Master Clock (MCK), generated from the Slow Clock by means of the two integrated PLLs, or on the Slow Clock (SLCK). These clocks are also provided as an output of the device on the pin MCKO, which is multiplexed with a general-purpose I/O line. While NRST is active, and after the reset, the MCKO is valid and outputs an image of the SLCK signal. The PIO Controller must be programmed to use this pin as standard I/O line. 7.5 Reset Reset initializes the user interface registers to their default states as defined in the peripheral sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter, the ARM core registers do not have defined reset states. When reset is active, the inputs of the AT91M42800A must be held at valid logic levels. The EBI address lines drive low during reset. All the peripheral clocks are disabled during reset to save power. 7.5.1 NRST Pin NRST is the active low reset input. It is asserted asynchronously, but exit from reset is synchronized internally to the slow clock (SLCK). At power-up, NRST must be active until the on-chip oscillator is stable. During normal operation, NRST must be active for a minimum of 10 SLCK clock cycles to ensure correct initialization. The pins BMS and NTRI are sampled during the 10 SLCK clock cycles just prior to the rising edge of NRST. The NRST pin has no effect on the on-chip Embedded ICE logic. Test Access Port (TAP) reset functionality is provided through the NTRST signal. 7.5.2 NTRST Pin The NTRST control pin initializes the selected TAP controller. The TAP controller involved in this reset is determined according to the initial logical state applied on the JTAGSEL pin after the last valid NRST. In either Boundary Scan or ICE Mode, a reset can be performed from the same or different circuitry, as shown in Figure 7-1 on page 13 below. But in all cases, the NTRST like the NRST signal, must be asserted after each power-up. (See the AT91M42800A Electrical Datasheet, Atmel Lit. No. 1776, for the necessary minimum pulse assertion time.) 12 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A Figure 7-1. Seperate or Common Reset Management NTRST NTRST Reset Controller NRST Reset Controller Reset Controller NRST AT91M42800A (1) AT91M42800A (2) Notes: 1. NRST and NTRST handling in Debug Mode during development. 2. NRST and NTRST handling during production. In order to benefit from the separation of NRST and NTRST during the debug phase of development, the user must independently manage both signals as shown in example (1) of Figure 7-1 above. However, once debug is completed, both signals are easily managed together during production as shown in example (2) of Figure 7-1 above. 7.5.3 Watchdog Reset The internally generated watchdog reset has the same effect as the NRST pin, except that the pins BMS and NTRI are not sampled. Boot mode and Tri-state mode are not updated. The NRST pin has priority if both types of reset coincide. 7.6 7.6.1 Emulation Functions Tri-state Mode The AT91M42800A provides a Tri-state mode, which is used for debug purposes in order to connect an emulator probe to an application board. In Tri-state mode the AT91M42800A continues to function, but all the output pin drivers are tri-stated. To enter Tri-state mode, the pin NTRI must be held low during the last 10 SLCK clock cycles before the rising edge of NRST. For normal operation, the pin NTRI must be held high during reset, by a resistor of up to 400 kΩ. NTRI must be driven to a valid logic value during reset. NTRI is multiplexed with Parallel I/O PA9 and USART 1 serial data transmit line TXD1. Standard RS232 drivers generally contain internal 400 kΩ pull-up resistors. If TXD1 is connected to one of these drivers, this pull-up will ensure normal operation, without the need for an additional external resistor. 7.6.2 Embedded ICE ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. It is connected to a host computer via an embedded ICE Interface. Embedded ICE mode is selected when MODE1 is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed (NRST and NTRST) after MODE0 and/or MODE1 have/has been changed. The reset input to the Embedded ICE (NTRST) is provided separately to facilitate debug of boot programs. 13 1779ES–ATARM–14-Apr-06 7.6.3 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan is enabled when MODE0 is low and MODE1 is high. The functions SAMPLE, EXTEST and BYPASS are implemented. In ICE Debug mode, the ARM core responds with a non-JTAG chip ID that identifies the core to the ICE system. This is not IEEE 1149.1 JTAG compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed (NRST and NTRST) after MODE0 and MODE1 are changed. 7.7 Memory Controller The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces: • Internal Memories in the four lowest megabytes • Middle Space reserved for the external devices (memory or peripherals) controlled by the EBI • Internal Peripherals in the four highest megabytes In any of these address spaces, the ARM7TDMI operates in little-endian mode only. 7.7.1 Protection Mode The embedded peripherals can be protected against unwanted access. The PME (Protect Mode Enable) pin must be tied high and validated in its peripheral operation (PIO Disable) to enable the protection mode. When enabled, any peripheral access must be done while the ARM7TDMI is running in Privileged mode (i.e., the accesses in user mode result in an abort). Only the valid peripheral address space is protected and requests to the undefined addresses will lead to a normal operation without abort. Internal Memories The AT91M42800A microcontroller integrates an 8-Kbyte primary internal SRAM. All internal memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones. The SRAM bank is mapped at address 0x0 (after the remap command), and ARM7TDMI exception vectors between 0x0 and 0x20 that can be modified by the software. The rest of the bank can be used for stack allocation (to speed up context saving and restoring), or as data and program storage for critical algorithms. 7.7.2 7.7.3 Boot Mode Select The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset. The input level on the BMS pin during the last 10 SLCK clock cycles before the rising edge of the NRST selects the type of boot memory. The Boot mode depends on BMS (see Table 7-1). 14 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A The pin BMS is multiplexed with the I/O line PA27 that can be programmed after reset like any standard PIO line. Table 7-1. BMS 1 0 Boot Mode Select Boot Memory External 8-bit memory NCS0 External 16-bit memory on NCS0 7.7.4 Remap Command The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91M42800A microcontroller uses a remap command that enables switching between the boot memory and the internal SRAM bank addresses. The remap command is accessible through the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to the other external devices (connected to chip selects 1 to 7) is required. The remap operation can only be changed back by an internal reset or an NRST assertion. Abort Control The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is asserted in the following cases: • When accessing an undefined address in the EBI address space • When the ARM7TDMI performs a misaligned access No abort is generated when reading the internal memory or by accessing the internal peripherals, whether the address is defined or not. When the processor performs a forbidden write access in a mode-protected peripheral register, the write is cancelled but no abort is generated. The processor can perform word or half-word data access with a misaligned address when a register relative load/store instruction is executed and the register contains a misaligned address. In this case, whether the access is in write or in read, an abort is generated but the access is not cancelled. The Abort Status Register traces the source that caused the last abort. The address and the type of abort are stored in registers of the External Bus Interface. 7.7.5 7.7.6 External Bus Interface The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0 0000. It generates the signals that control access to the external devices, and can be configured from eight 1-Mbyte banks up to four 16-Mbyte banks. In all cases it supports byte, half-word and word aligned accesses. For each of these banks, the user can program: • Number of wait states • Number of data float times (wait time after the access is finished to prevent any bus contention in case the device takes too long in releasing the bus) • Data bus width (8-bit or 16-bit) 15 1779ES–ATARM–14-Apr-06 • With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte Access Select mode) or two 8-bit devices in parallel that emulate a 16-bit memory (Byte Write Access mode). The External Bus Interface also features the Early Read Protocol, configurable for all the devices, which significantly reduces access time requirements on an external device. 8. Peripherals The AT91M42800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible. Byte and half-word accesses are not supported. If a byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access. Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address space). 8.1 Peripheral Registers The following registers are common to all peripherals: • Control Register – Write-only register that triggers a command when a one is written to the corresponding position at the appropriate address. Writing a zero has no effect. • Mode Register – read/write register that defines the configuration of the peripheral. Usually has a value of 0x0 after a reset. • Data Registers – read and/or write register that enables the exchange of data between the processor and the peripheral. • Status Register – Read-only register that returns the status of the peripheral. • Enable/Disable/Status Registers – shadow command registers. Writing a one in the Enable Register sets the corresponding bit in the Status Register. Writing a one in the Disable Register resets the corresponding bit and the result can be read in the Status Register. Writing a bit to zero has no effect. This register access method maximizes the efficiency of bit manipulation, and enables modification of a register with a single non-interruptible instruction, replacing the costly read-modify-write operation. Unused bits in the peripheral registers are shown as “–” and must be written at 0 for upward compatibility. These bits read 0. 8.2 Peripheral Interrupt Control The Interrupt Control of each peripheral is controlled from the status register using the interrupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller. The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask) makes it possible to enable or disable peripheral interrupt sources with a non-interruptible single instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-time and multi-tasking systems. 16 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A 8.3 Peripheral Data Controller The AT91M42800A has an 8-channel PDC dedicated to the two on-chip USARTs and to the two on-chip SPIs. One PDC channel is connected to the receiving channel and one to the transmitting channel of each peripheral. The user interface of a PDC channel is integrated in the memory space of each USART channel and in the memory space of each SPI. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed data is transferred, an end-of-transfer interrupt is generated by the corresponding peripheral. See the USART section and the SPI sections for more details on PDC operation and programming. 8.4 8.4.1 System Peripherals PMC: Power Management Controller The AT91M42800A’s Power Management Controller optimizes the power consumption of the device. The PMC controls the clocking elements such as the oscillator and the PLLs, and the System and the Peripheral Clocks. It also controls the MCKO pin and permits to the user to select four different signals to be driven on this pin. The AT91M42800A has the following clock elements: • The oscillator providing a clock that depends on the crystal fundamental frequency connected between the XIN and XOUT pins • PLL A providing a low-to-middle frequency clock range • PLL B providing a middle-to-high frequency range • The Clock prescaler • The ARM Processor Clock controller • The Peripheral Clock controller • The Master Clock Output controller The on-chip low-power oscillator together with the PLL-based frequency multiplier and the prescaler results in a programmable clock between 500 Hz and 66 MHz. It is the responsibility of the user to make sure that the PMC programming does not result in a clock over the acceptable limits. 8.4.2 ST: System Timer The System Timer module integrates three different free-running timers: • A Period Interval Timer setting the base time for an Operating System. • A Watchdog Timer that is built around a 16-bit counter, and is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt, or assert an active level on the dedicated pin NWDOVF. • A Real-time Timer counting elapsed seconds. These timers count using the Slow Clock provided by the MCU. Typically, this clock has a frequency of 32768 Hz. 8.4.3 AIC: Advanced Interrupt Controller The AT91M42800A has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real-time overhead in handling internal and external interrupts. 17 1779ES–ATARM–14-Apr-06 The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request lines: IRQ0 to IRQ3. The 8-level priority encoder allows the customer to define the priority between the different NIRQ interrupt sources. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high- or low-level sensitive. 8.4.4 PIO: Parallel I/O Controller The AT91M42800A has 54 programmable I/O lines. I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. These lines are controlled by two separate and identical PIO Controllers called PIOA and PIOB. Each PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller and insertion of a simple input glitch filter on any of the PIO pins. SF: Special Function The AT91M42800A provides registers that implement the following special functions. • Chip Identification • RESET Status 8.4.5 8.5 8.5.1 User Peripherals USART: Universal Synchronous/Asynchronous Receiver Transmitter The AT91M42800A provides two identical, full-duplex, universal synchronous/asynchronous receiver/transmitters that interface to the APB and are connected to the Peripheral Data Controller. The main features are: • Programmable Baud Rate Generator with External or Internal Clock, as well as Slow Clock • Parity, Framing and Overrun Error Detection • Line Break Generation and Detection • Automatic Echo, Local Loopback and Remote Loopback channel modes • Multi-drop mode: Address Detection and Generation • Interrupt Generation • Two Dedicated Peripheral Data Controller channels • 5-, 6-, 7-, 8- and 9-bit character length 8.5.2 TC: Timer/Counter The AT91M42800A features two Timer/Counter blocks, each containing three identical 16-bit Timer/Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation. Each Timer/Counter (TC) channel has 3 external clock inputs, 5 internal clock inputs, and 2 multi-purpose input/output signals that can be configured by the user. Each channel drives an 18 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A internal interrupt signal that can be programmed to generate processor interrupts via the AIC (Advanced Interrupt Controller). The Timer/Counter block has two global registers that act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each Timer/Counter channel, allowing them to be chained. Each Timer/Counter block operates independently and has a complete set of block and channel registers. 8.5.3 SPI: Serial Peripheral Interface The AT91M42800A includes two SPIs that provide communication with external devices in Master or Slave mode. They are independent, and are referred to by the letters A and B. Each SPI has four external chip selects that can be connected to up to 15 devices. The data length is programmable from 8- to 16-bit. 19 1779ES–ATARM–14-Apr-06 9. Packaging Information Figure 9-1. 144-lead LQFP Package Drawing


  θ2   θ3  θ1     θ    20 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A Table 9-1. Symbol Common Dimensions (mm) Min c c1 L L1 R2 R1 S q q1 q2 q3 A A1 A2 0.05 1.35 1.4 0.08 0.08 0.2 0° 0° 11° 11° 12° 12° 13° 13° 1.6 0.15 1.45 3.5° 7° 0.09 0.09 0.45 0.6 1.00 REF 0.2 Nom Max 0.2 0.16 0.75 Tolerances and form of position aaa bbb 0.2 0.2 Table 9-2. Pin Count 144 Lead Count Dimensions (mm) D/E BSC 22.0 D1/E1 BSC 20.0 b Min 0.17 Nom 0.22 Max 0.27 Min 0.17 b1 Nom 0.2 Max 0.23 e BSC 0.50 ccc 0.10 ddd 0.08 Table 9-3. 1708 Device and 144-lead LQFP Package Maximum Weight mg 21 1779ES–ATARM–14-Apr-06 Figure 9-2. 144-ball Ball Grid Array Package Drawing TOP VIEW BOTTOM VIEW Symbol Max. SIDE VIEW Table 9-4. 584 Device and 144-ball BGA Package Maximum Weight mg 22 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A 10. Soldering Profile 10.1 LQFP Soldering Profile (Green) Table 10-1 gives the recommended soldering profile from J-STD-020C. Table 10-1. Soldering Profile Green Compliant Package Green Package 3° C/sec. max. 180 sec. max. 60 sec. to 150 sec. 20 sec. to 40 sec. 260° C 6° C/sec. max. 8 min. max. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5° C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° C to Peak Temperature Note: The package is certified to be backward compatible with Pb/Sn soldering profile. A maximum of three reflow passes is allowed per component. 10.2 BGA Soldering Profile (RoHS-compliant) Table 10-2 gives the recommended soldering profile from J-STD-20C. Table 10-2. Soldering Profile RoHS Compliant Package Convection or IR/Convection 3° C/sec. max. 180 sec. max 60 sec. to 150 sec. 20 sec. to 40 sec. 260° C 6° C/sec. 8 min. max Profile Feature Average Ramp-up Rate (183° C to Peak) Preheat Temperature 125° C ±25° C Temperature Maintained Above 183° C Time within 5° C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° C to Peak Temperature Note: It is recomended to apply a soldering temperature higher than 250°C. A maximum of three reflow passes is allowed per component. 23 1779ES–ATARM–14-Apr-06 11. Ordering Information Table 11-1. Ordering Information Ordering Code AT91M42800A-33CJ AT91M42800A-33AU Package BGA 144 LQFP 144 Package Type RoHS-compliant Green Operating Temperature Range Industrial (-40° C to 85° C) 24 AT91M42800A 1779ES–ATARM–14-Apr-06 AT91M42800A 12. Revision History Table 12-1. Revision History Change Request Ref. Version 1779AS Comments First issue Oct-01 Added information to section Internal Memories on page 13. Change in Table 6 on page 19. 1779BS Added Table 9 on page 21. Added Table 10 on page 22. Added section Soldering Profile on page 23. Updated package name to LQFP throughout. 1779CS Updated “Ordering Information” on page 24 and “Soldering Profile” on page 23 with new data on Green/RoHS-compliant packages. Added Section 7.5.2 ”NTRST Pin” on page 12. Updated Section 10. ”Soldering Profile” on page 23 and Section 11. ”Ordering Information” on page 24 to remove leaded package references. 05-329 05-474 1779DS 1779ES 25 1779ES–ATARM–14-Apr-06 26 AT91M42800A 1779ES–ATARM–14-Apr-06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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