AT91RM9200-QU-002

Features • Incorporates the ARM920T™ ARM® Thumb® Processor 200 MIPS at 180 MHz, Memory Management Unit 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer In-circuit Emulator including Debug Communication Channel Mid-level Implementation Embedded Trace Macrocell™ (256-ball BGA Package only) Low Power: On VDDCORE 24.4 mA in Normal Mode, 520 µA in Standby Mode Additional Embedded Memories – 16K Bytes of SRAM and 128K Bytes of ROM External Bus Interface (EBI) – Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to CompactFlash® and NAND Flash/SmartMedia® System Peripherals for Enhanced Performance: – Enhanced Clock Generator and Power Management Controller – Two On-chip Oscillators with Two PLLs – Very Slow Clock Operating Mode and Software Power Optimization Capabilities – Four Programmable External Clock Signals – System Timer Including Periodic Interrupt, Watchdog and Second Counter – Real-time Clock with Alarm Interrupt – Debug Unit, Two-wire UART and Support for Debug Communication Channel – Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored Interrupt Sources, Spurious Interrupt Protected – Seven External Interrupt Sources and One Fast Interrupt Source – Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change Interrupt and Open-drain Capability on Each Line – 20-channel Peripheral DMA Controller (PDC) Ethernet MAC 10/100 Base-T – Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – Integrated 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit USB 2.0 Full Speed (12 Mbits per second) Host Double Port – Dual On-chip Transceivers (Single Port Only on 208-lead PQFP Package) – Integrated FIFOs and Dedicated DMA Channels USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs Multimedia Card Interface (MCI) – Automatic Protocol Control and Fast Automatic Data Transfers – MMC and SD Memory Card-compliant, Supports Up to Two SD Memory Cards Three Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I2S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Support for ISO7816 T0/T1 Smart Card – Hardware Handshaking – RS485 Support, IrDA® Up To 115 Kbps – Full Modem Control Lines on USART1 Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, 4 External Peripheral Chip Selects Two 3-channel, 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two-wire Interface (TWI) – Master Mode Support, All 2-wire Atmel EEPROMs Supported IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins Power Supplies – 1.65V to 1.95V for VDDCORE, VDDOSC and VDDPLL – 3.0V to 3.6V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os) Available in a 208-pin Green PQFP or 256-ball RoHS-compliant BGA Package – – – – • • • • ARM920T-based Microcontroller AT91RM9200 • • • • • • • • • • • • Rev. 1768G-ATARM–29-Sep-06 1. Description The AT91RM9200 is a complete system-on-chip built around the ARM920T ARM Thumb processor. It incorporates a rich set of system and application peripherals and standard interfaces in order to provide a single-chip solution for a wide range of compute-intensive applications that require maximum functionality at minimum power consumption at lowest cost. The AT91RM9200 incorporates a high-speed on-chip SRAM workspace, and a low-latency External Bus Interface (EBI) for seamless connection to whatever configuration of off-chip memories and memory-mapped peripherals is required by the application. The EBI incorporates controllers for synchronous DRAM (SDRAM), Burst Flash and Static memories and features specific circuitry facilitating the interface for NAND Flash/SmartMedia and Compact Flash. The Advanced Interrupt Controller (AIC) enhances the interrupt handling performance of the ARM920T processor by providing multiple vectored, prioritized interrupt sources and reducing the time taken to transfer to an interrupt handler. The Peripheral DMA Controller (PDC) provides DMA channels for all the serial peripherals, enabling them to transfer data to or from on- and off-chip memories without processor intervention. This reduces the processor overhead when dealing with transfers of continuous data streams.The AT91RM9200 benefits from a new generation of PDC which includes dual pointers that simplify significantly buffer chaining. The set of Parallel I/O (PIO) controllers multiplex the peripheral input/output lines with generalpurpose data I/Os for maximum flexibility in device configuration. An input change interrupt, open drain capability and programmable pull-up resistor is included on each line. The Power Management Controller (PMC) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals under software control. It uses an enhanced clock generator to provide a selection of clock signals including a slow clock (32 kHz) to optimize power consumption and performance at all times. The AT91RM9200 integrates a wide range of standard interfaces including USB 2.0 Full Speed Host and Device and Ethernet 10/100 Base-T Media Access Controller (MAC), which provides connection to a extensive range of external peripheral devices and a widely used networking layer. In addition, it provides an extensive set of peripherals that operate in accordance with several industry standards, such as those used in audio, telecom, Flash Card, infrared and Smart Card applications. To complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints. 2 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 2. Block Diagram Bold arrows ( Figure 2-1. AT91RM9200 Block Diagram NRST JTAGSEL TDI TDO TMS TCK NTRST Reset and Test ICE JTAG Scan Instruction Cache 16K bytes Data Cache 16K bytes ) indicate master-to-slave dependency. TST0-TST1 ARM920T Core ETM MMU TSYNC PIO TCLK TPS0 - TPS2 TPK0 - TPK15 BMS PIO FIQ IRQ0-IRQ6 PCK0-PCK3 PLLRCB PLLRCA XIN XOUT AIC Fast SRAM 16K bytes Address Decoder Abort Status EBI CompactFlash NAND Flash SmartMedia PLLB PLLA PMC OSC Peripheral Bridge System Timer Peripheral DMA Controller Fast ROM 128K bytes Misalignment Detector Bus Arbiter SDRAM Controller XIN32 XOUT32 DRXD PIO DTXD OSC RTC Memory Controller DBGU PDC Static Memory Controller PIOA/PIOB/PIOC/PIOD Controller DMA FIFO USB Host FIFO Transceiver PIO Burst Flash Controller D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A22 A16/BA0 A17/BA1 NCS0/BFCS NCS1/SDCS NCS2 NCS3/SMCS NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 BFRDY/SMOE BFCK BFAVD BFBAA/SMWE BFOE BFWE A23-A24 A25/CFRNW NWAIT NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NCS7 D16-D31 HDMA HDPA HDMB HDPB DDM DDP Transceiver USB Device DMA FIFO ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO EF100 TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TF2 TK2 TD2 RD2 RK2 RF2 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TCLK3 TCLK4 TCLK5 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 MCCK MCCDA MCDA0-MCDA3 MCCDB MCDB0-MCDB3 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DSR1 DTR1 DCD1 RI1 RXD2 TXD2 SCK2 RTS2 CTS2 RXD3 TXD3 SCK3 RTS3 CTS3 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK TWD MCI PDC Ethernet MAC 10/100 APB USART0 PDC PDC USART1 PIO PIO PIO SSC1 PDC PDC SSC0 USART2 PDC PDC SSC2 USART3 PDC Timer Counter TC0 TC1 TC2 SPI Timer Counter PDC TC3 TWI TC4 TC5 TWCK 3 1768G–ATARM–29-Sep-06 3. Signal Description Table 3-1. Pin Name Signal Description by Peripheral Function Power Type Active Level Comments VDDIOM VDDIOP VDDPLL VDDCORE VDDOSC GND GNDPLL GNDOSC Memory I/O Lines Power Supply Peripheral I/O Lines Power Supply Oscillator and PLL Power Supply Core Chip Power Supply Oscillator Power Supply Ground PLL Ground Oscillator Ground Power Power Power Power Power Ground Ground Ground 3.0V to 3.6V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V 1.65V to 1.95V Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Crystal Input Main Crystal Output 32KHz Crystal Input 32KHz Crystal Output PLL A Filter PLL B Filter Programmable Clock Output ICE and JTAG TCK TDI TDO TMS NTRST JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal JTAG Selection ETM™ TSYNC TCLK TPS0 - TPS2 TPK0 - TPK15 Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Trace Packet Port Reset/Test NRST TST0 - TST1 Microcontroller Reset Test Mode Select Input Input Low No on-chip pull-up, Schmitt trigger Must be tied low for normal operation, Schmitt trigger Output Output Output Output Input Input Output Input Input Input Low Schmitt trigger Internal Pull-up, Schmitt trigger Tri-state Internal Pull-up, Schmitt trigger Internal Pull-up, Schmitt trigger Schmitt trigger Input Output Input Output Input Input Output 4 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 3-1. Pin Name Signal Description by Peripheral Function Memory Controller Type Active Level Comments BMS Boot Mode Select Debug Unit Input DRXD DTXD Debug Receive Data Debug Transmit Data AIC Input Output Debug Receive Data Debug Transmit Data IRQ0 - IRQ6 FIQ External Interrupt Inputs Fast Interrupt Input PIO Input Input PA0 - PA31 PB0 - PB29 PC0 - PC31 PD0 - PD27 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D EBI I/O I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset D0 - D31 A0 - A25 Data Bus Address Bus SMC I/O Output Pulled-up input at reset 0 at reset NCS0 - NCS7 NWR0 - NWR3 NOE NRD NUB NLB NWE NWAIT NBS0 - NBS3 Chip Select Lines Write Signal Output Enable Read Signal Upper Byte Select Lower Byte Select Write Enable Wait Signal Byte Mask Signal Output Output Output Output Output Output Output Input Output EBI for CompactFlash Support Low Low Low Low Low Low Low Low Low 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Output Output Output Output Output Output Output Low Low Low Low Low Low 5 1768G–ATARM–29-Sep-06 Table 3-1. Pin Name Signal Description by Peripheral Function Type EBI for NAND Flash/SmartMedia Support Active Level Comments SMCS SMOE SMWE NAND Flash/SmartMedia Chip Select NAND Flash/SmartMedia Output Enable NAND Flash/SmartMedia Write Enable SDRAM Controller Output Output Output Low Low Low SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Burst Flash Controller Low Low High Low BFCK BFCS BFAVD BFBAA BFOE BFRDY BFWE Burst Flash Clock Burst Flash Chip Select Burst Flash Address Valid Burst Flash Address Advance Burst Flash Output Enable Burst Flash Ready Burst Flash Write Enable Output Output Output Output Output Input Output Multimedia Card Interface Low Low Low Low High Low MCCK MCCDA MCDA0 - MCDA3 MCCDB MCDB0 - MCDB3 Multimedia Card Clock Multimedia Card A Command Multimedia Card A Data Multimedia Card B Command Multimedia Card B Data USART Output I/O I/O I/O I/O SCK0 - SCK3 TXD0 - TXD3 RXD0 - RXD3 RTS0 - RTS3 CTS0 - CTS3 DSR1 DTR1 DCD1 RI1 Serial Clock Transmit Data Receive Data Ready To Send Clear To Send Data Set Ready Data Terminal Ready Data Carrier Detect Ring Indicator I/O Output Input Output Input Input Output Input Input 6 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 3-1. Pin Name Signal Description by Peripheral Function USB Device Port Type Active Level Comments DDM DDP USB Device Port Data USB Device Port Data + USB Host Port Analog Analog HDMA HDPA HDMB HDPB USB Host Port A Data USB Host Port A Data + USB Host Port B Data USB Host Port B Data + Ethernet MAC Analog Analog Analog Analog EREFCK ETXCK ERXCK ETXEN ETX0 - ETX3 ETXER ERXDV ECRSDV ERX0 - ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Reference Clock Transmit Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Carrier Sense and Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force 100 Mbits/sec. Input Input Input Output Output Output Input Input Input Input Input Input Output I/O Output Synchronous Serial Controller High RMII only MII only MII only ETX0 - ETX1 only in RMII MII only MII only RMII only ERX0 - ERX1 only in RMII MII only MII only RMII only TD0 - TD2 RD0 - RD2 TK0 - TK2 RK0 - RK2 TF0 - TF2 RF0 - RF2 Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Timer/Counter Output Input I/O I/O I/O I/O TCLK0 - TCLK5 TIOA0 - TIOA5 TIOB0 - TIOB5 External Clock Input I/O Line A I/O Line B Input I/O I/O 7 1768G–ATARM–29-Sep-06 Table 3-1. Pin Name Signal Description by Peripheral Function SPI Type Active Level Comments MISO MOSI SPCK NPCS0 NPCS1 - NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select Two-Wire Interface I/O I/O I/O I/O Output Low Low TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O 4. Package and Pinout The AT91RM9200 is available in two packages: • 208-pin PQFP, 31.2 x 31.2 mm, 0.5 mm pitch • 256-ball BGA, 15 x 15 mm, 0.8 mm ball pitch The product features of the 256-ball BGA package are extended compared to the 208-lead PQFP package. The features that are available only with the 256-ball BGA package are: • Parallel I/O Controller D • ETM™ port with outputs multiplexed on the PIO Controller D • a second USB Host transceiver, opening the Hub capabilities of the embedded USB Host. 4.1 208-pin PQFP Package Outline Figure 4-1 shows the orientation of the 208-pin PQFP package. A detailed mechanical description is given in the section “AT91RM9200 Mechanical Characteristics” of the product datasheet. Figure 4-1. 208-pin PQFP Package (Top View) 156 157 105 104 208 1 52 53 8 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 4.2 208-pin PQFP Package Pinout AT91RM9200 Pinout for 208-pin PQFP Package Signal Name PC24 PC25 PC26 PC27 PC28 PC29 VDDIOM GND PC30 PC31 PC10 PC11 PC12 PC13 PC14 PC15 PC0 PC1 VDDCORE GND PC2 PC3 PC4 PC5 PC6 VDDIOM GND VDDPLL PLLRCA GNDPLL XOUT XIN VDDOSC GNDOSC XOUT32 XIN32 Table 4-1. Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Signal Name VDDPLL PLLRCB GNDPLL VDDIOP GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 VDDIOP GND PA14 PA15 PA16 PA17 VDDCORE GND PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Signal Name PA27 PA28 VDDIOP GND PA29 PA30 PA31/BMS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 VDDIOP GND PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 JTAGSEL TDI TDO TCK Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Signal Name TMS NTRST VDDIOP GND TST0 TST1 NRST VDDCORE GND PB23 PB24 PB25 PB26 PB27 PB28 PB29 HDMA HDPA DDM DDP VDDIOP GND VDDIOM GND A0/NBS0 A1/NBS2/NWR2 A2 A3 A4 A5 A6 A7 A8 A9 A10 SDA10 9 1768G–ATARM–29-Sep-06 Table 4-1. Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 AT91RM9200 Pinout for 208-pin PQFP Package (Continued) Signal Name A11 VDDIOM GND A12 A13 A14 A15 VDDCORE GND A16/BA0 A17/BA1 A18 A19 A20 A21 A22 Pin Number 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Signal Name PC7 PC8 PC9 VDDIOM GND NCS0/BFCS NCS1/SDCS NCS2 NCS3/SMCS NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS Pin Number 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 Signal Name CAS SDWE D0 D1 D2 D3 VDDIOM GND D4 D5 D6 VDDCORE GND D7 D8 D9 Pin Number 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal Name D10 D11 D12 D13 D14 D15 VDDIOM GND PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 Note: 1. Shaded cells define the pins powered by VDDIOM. 4.3 256-ball BGA Package Outline Figure 4-2 shows the orientation of the 256-ball LFBGA package. A detailed mechanical description is given in the section “AT91RM9200 Mechanical Characteristics” of the product datasheet. Figure 4-2. 256-ball LFBGA Package (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGHJKLMNPRTU BALL A1 10 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 4.4 256-ball BGA Package Pinout AT91RM9200 Pinout for 256-ball BGA Package Signal Name TDI JTAGSEL PB20 PB17 PD11 PD8 VDDIOP PB9 PB4 PA31/BMS VDDIOP PA23 PA19 GND PA14 VDDIOP PA13 TDO PD13 PB18 PB21 PD12 PD9 GND PB10 PB5 PB0 VDDIOP PA24 PA17 PA15 PA11 PA12 PA7 TMS PD15 Pin C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 Signal Name PD14 PB22 PB19 PD10 PB13 PB12 PB6 PB1 GND PA20 PA18 VDDCORE GND PA8 PD5 TST1 VDDIOP VDDIOP GND VDDIOP PD7 PB14 VDDIOP PB8 PB2 GND PA22 PA21 PA16 PA10 PD6 PD4 NRST NTRST GND TST0 Pin E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F9 F11 F12 F13 F14 F15 F16 F17 G1 G2 G3 G4 G5 G6 G12 G13 Signal Name TCK GND PB15 GND PB7 PB3 PA29 PA26 PA25 PA9 PA6 PD3 PD0 PD16 GND PB23 PB25 PB24 VDDCORE PB16 PB11 PA30 PA28 PA4 PD2 PD1 PA5 PLLRCB PD19 PD17 GND PB26 PD18 PB27 PA27 PA0 Pin G14 G15 G16 G17 H1 H2 H3 H4 H5 H13 H14 H15 H16 H17 J1 J2 J3 J4 J5 J6 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K13 K14 K15 K16 K17 Signal Name PA1 PA2 PA3 XIN32 PD23 PD20 PD22 PD21 VDDIOP VDDPLL VDDIOP GNDPLL GND XOUT32 PD25 PD27 PD24 PD26 PB28 PB29 GND GNDOSC VDDOSC VDDPLL GNDPLL XIN HDPA DDM HDMA VDDIOP DDP PC5 PC4 PC6 VDDIOM XOUT Table 4-2. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 11 1768G–ATARM–29-Sep-06 Table 4-2. Pin L1 L2 L3 L4 L5 L6 L12 L13 L14 L15 L16 L17 M1 M2 M3 M4 M5 M6 M7 M9 M11 M12 M13 M14 M15 M16 M17 N1 AT91RM9200 Pinout for 256-ball BGA Package (Continued) Signal Name GND HDPB HDMB A6 GND VDDIOP PC10 PC15 PC2 PC3 VDDCORE PLLRCA VDDIOM GND A3 A1/NBS2/NWR2 A10 A2 GND NCS1/SDCS D4 GND PC13 PC1 PC0 GND PC14 A0/NBS0 Pin N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 Signal Name A5 A9 A4 A14 SDA10 A8 A21 NRD/NOE/CFOE RAS D2 GND PC28 PC31 PC30 PC11 PC12 A7 A13 A12 VDDIOM A11 A22 PC9 NWR0/NWE/CFWE SDCKE D1 D5 D10 Pin P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 Signal Name D15 PC26 PC27 VDDIOM GND GND GND A18 A20 PC8 VDDIOM NCS3/SMCS NWR3/NBS3/ CFIOW D0 VDDIOM D8 D13 PC17 VDDIOM PC24 PC29 VDDIOM A15 VDDCORE A17/BA1 PC7 VDDIOM NCS2 Pin T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name NWR1/NBS1/ CFIOR SDWE GND VDDCORE D9 D12 GND PC19 PC21 PC23 PC25 VDDCORE GND A16/BA0 A19 GND NCS0/BFCS SDCK CAS D3 D6 D7 D11 D14 PC16 PC18 PC20 PC22 Note: 1. Shaded cells define the balls powered by VDDIOM. 12 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 5. Power Considerations 5.1 Power Supplies The AT91RM9200 has five types of power supply pins: • VDDCORE pins. They power the core, including processor, memories and peripherals; voltage ranges from 1.65V to 1.95V, 1.8V nominal. • VDDIOM pins. They power the External Bus Interface I/O lines; voltage ranges from 3.0V to 3.6V, 3V or 3.3V nominal. • VDDIOP pins. They power the Peripheral I/O lines and the USB transceivers; voltage ranges from 3.0V to 3.6V, 3V or 3.3V nominal. • VDDPLL pins. They power the PLL cells; voltage ranges from 1.65V to 1.95V, 1.8V nominal. • VDDOSC pin. They power both oscillators; voltage ranges from 1.65V to 1.95V, 1.8V nominal. The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 9 and Table 4-2 on page 11. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins are common to all power supplies, except VDDPLL and VDDOSC pins. For these pins, GNDPLL and GNDOSC are provided, respectively. 5.2 Power Consumption The AT91RM9200 consumes about 500 uA of static current on VDDCORE at 25 ° C. For dynamic power consumption, the AT91RM9200 consumes a maximum of 25 mA on VDDCORE at maximum speed in typical conditions (1.8V, 25 ° C), processor running full-performance algorithm. 6. I/O Considerations 6.1 JTAG Port Pins TMS and TDI are Schmitt trigger inputs and integrate internal pull-up resistors of 15 kOhm typical. TCK is a Schmitt trigger input without internal pull-up resistor. TDO is a tri-state output. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The NTRST pin is used to initialize the EmbeddedICE™ TAP Controller. 6.2 Test Pin The TST0 and TST1 pins are used for manufacturing test purposes when asserted high. As they do not integrate a pull-down resistor, they must be tied low during normal operations. Driving this line at a high level leads to unpredictable results. 6.3 Reset Pin NRST is a Schmitt trigger without pull-up resistor. The NRST signal is inserted in the Boundary Scan. 13 1768G–ATARM–29-Sep-06 6.4 PIO Controller A, B, C and D Lines All the I/O lines PA0 to PA31, PB0 to PB29, PC0 to PC31 and PD0 to PD27 integrate a programmable pull-up resistor of 15 kOhm typical. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that must be enabled as peripherals at reset. This is explicitly indicated in the column "Reset State" of the PIO Controller multiplexing tables. 7. Processor and Architecture 7.1 ARM920T Processor • ARM9TDMI™-based on ARM Architecture v4T • Two instruction sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 16-Kbyte Data Cache, 16-Kbyte Instruction Cache – Virtually-addressed 64-way Associative Cache – 8 words per line – Write-though and write-back operation – Pseudo-random or Round-robin replacement – Low-power CAM RAM implementation • Write Buffer – 16-word Data Buffer – 4-address Address Buffer – Software Control Drain • Standard ARMv4 Memory Management Unit (MMU) – Access permission for sections – Access permission for large pages and small pages can be specified separately for each quarter of the pages – 16 embedded domains – 64 Entry Instruction TLB and 64 Entry Data TLB 8-, 16-, 32-bit Data Bus for Instructions and Data 14 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 7.2 Debug and Test • Integrated EmbeddedICE • Debug Unit – Two-pin UART – Debug Communication Channel – Chip ID Register • Embedded Trace Macrocell: ETM9™ Rev2a – Medium Level Implementation – Half-rate Clock Mode – Four Pairs of Address Comparators – Two Data Comparators – Eight Memory Map Decoder Inputs – Two Counters – One Sequencer – One 18-byte FIFO • IEEE1149.1 JTAG Boundary Scan on all Digital Pins 7.3 Boot Program • Default Boot Program stored in ROM-based products • Downloads and runs an application from external storage media into internal SRAM • Downloaded code size depends on embedded SRAM size • Automatic detection of valid application • Bootloader supporting a wide range of non-volatile memories – SPI DataFlash® connected on SPI NPCS0 – Two-wire EEPROM – 8-bit parallel memories on NCS0 • Boot Uploader in case no valid program is detected in external NVM and supporting several communication media • Serial communication on a DBGU (XModem protocol) • USB Device Port (DFU Protocol) 7.4 Embedded Software Services • Compliant with ATPCS • Compliant with AINSI/ISO Standard C • Compiled in ARM/Thumb Interworking • ROM Entry Service • Tempo, Xmodem and DataFlash services • CRC and Sine tables 7.5 Memory Controller • Programmable Bus Arbiter handling four Masters 15 1768G–ATARM–29-Sep-06 – Internal Bus is shared by ARM920T, PDC, USB Host Port and Ethernet MAC Masters – Each Master can be assigned a priority between 0 and 7 • Address Decoder provides selection for – Eight external 256-Mbyte memory areas – Four internal 1-Mbyte memory areas – One 256-Mbyte embedded peripheral area • Boot Mode Select Option – Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset • Abort Status Registers – Source, Type and all parameters of the access leading to an abort are saved • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap command – Provides remapping of an internal SRAM in place of the boot NVM 16 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 8. Memories Figure 8-1. AT91RM9200 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF Internal Memory Mapping 0x0000 0000 Boot Memory (1) 1 MBytes 1 MBytes 256M Bytes 0x0010 0000 ROM 0x0020 0000 0x1000 0000 EBI Chip Select 0 / BFC EBI Chip Select 1 / SDRAMC 256M Bytes SRAM 0x0030 0000 USB Host User Interface 0x0040 0000 1 MBytes 0x1FFF FFFF 0x2000 0000 256M Bytes 1 MBytes 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF Undefined (Abort) 256M Bytes 0x0FFF FFFF Notes : 248 MBytes (1) Can be SRAM, ROM or Flash depending on BMS and the REMAP Command 0x4000 0000 EBI Chip Select 3 / NANDFlash Logic EBI Chip Select 4 / CF Logic EBI Chip Select 5 / CF Logic EBI Chip Select 6 / CF Logic EBI Chip Select 7 0x8FFF FFFF 256M Bytes 0x4FFF FFFF 0x5000 0000 256M Bytes User Peripheral Mapping 0x5FFF FFFF 0x6000 0000 256M Bytes 0xF000 0000 Reserved 0xFFFA 0000 0x6FFF FFFF TCO, TC1, TC2 0xFFFA 4000 16K Bytes 0x7000 0000 256M Bytes 0xFFFA 8000 TC3, TC4, TC5 Reserved 16K Bytes 0x7FFF FFFF 0x8000 0000 256M Bytes 0xFFFB 0000 16K Bytes UDP 0xFFFB 4000 16K Bytes 0x9000 0000 MCI 0xFFFB 8000 16K Bytes System Peripheral Mapping 0xFFFE 4000 TWI 0xFFFB C000 16K Bytes EMAC 0xFFFC 0000 16K Bytes Reserved USART0 0xFFFC 4000 16K Bytes 0xFFFF F000 AIC USART1 16K Bytes 0xFFFF F200 512 Bytes 0xFFFC 8000 DBGU USART2 16K Bytes 0xFFFF F400 512 Bytes Undefined (Abort) 1,518M Bytes 0xFFEC C000 PIOA USART3 16K Bytes 0xFFFF F600 512 Bytes 0xFFFD 0000 PIOB SSC0 16K Bytes 0xFFFF F800 512 Bytes 0xFFFD 4000 PIOC SSC1 16K Bytes 0xFFFF FA00 512 bytes 0xFFFD 8000 PIOD SSC2 16K Bytes 0xFFFF FC00 512 bytes 0xFFED C000 PMC Reserved 0xFFFF FD00 256 Bytes 0xFFFE 0000 ST SPI 16K Bytes 0xFFFF FE00 256 Bytes 0xEFFF FFFF 0xF000 0000 Internal Peripherals 0xFFFF FFFF 0xFFFE 4000 RTC Reserved 0xFFFF FF00 256 Bytes 256M Bytes 0xFFFF FFFF MC 0xFFFF FFFF 256 Bytes 17 1768G–ATARM–29-Sep-06 A first level of address decoding is performed by the Memory Controller, i.e., by the implementation of the Advanced System Bus (ASB) with additional features. Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The area 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M bytes of internal memory area. The area 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. 8.1 8.1.1 8.1.1.1 Embedded Memories Internal Memory Mapping Internal RAM The AT91RM9200 integrates a high-speed, 16-Kbyte internal SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x20 0000. After Remap, the SRAM is also available at address 0x0. 8.1.1.2 Internal ROM The AT91RM9200 integrates a 128-Kbyte Internal ROM. At any time, the ROM is mapped at address 0x10 0000. It is also accessible at address 0x0 after reset and before the Remap Command if the BMS is tied high during reset. 8.1.1.3 USB Host Port The AT91RM9200 integrates a USB Host Port Open Host Controller Interface (OHCI). The registers of this interface are directly accessible on the ASB Bus and are mapped like a standard internal memory at address 0x30 0000. 18 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 9. System Peripherals A complete memory map is shown in Figure 8-1 on page 17. 9.1 Reset Controller • Two reset input lines (NRST and NTRST) providing, respectively: • Initialization of the User Interface registers (defined in the user interface of each peripheral) and: – Sample the signals needed at bootup – Compel the processor to fetch the next instruction at address zero • Initialization of the embedded ICE TAP controller 9.2 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU…) – Source 2 to Source 31 control thirty embedded peripheral interrupts or external interrupts – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources • 8-level Priority Controller – Drives the Normal Interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode – Easy debugging by preventing automatic operations • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt 9.3 Power Management Controller • Optimizes the power consumption of the whole system • Embeds and controls: – One Main Oscillator and One Slow Clock Oscillator (32.768Hz) – Two Phase Locked Loops (PLLs) and Dividers – Clock Prescalers • Provides: – the Processor Clock PCK – the Master Clock MCK 19 1768G–ATARM–29-Sep-06 – the USB Clocks, UHPCK and UDPCK, respectively for the USB Host Port and the USB Device Port – Programmable automatic PLL switch-off in USB Device suspend conditions – up to thirty peripheral clocks – four programmable clock outputs PCK0 to PCK3 • Four operating modes: – Normal Mode, Idle Mode, Slow Clock Mode, Standby Mode 9.4 Debug Unit • System peripheral to facilitate debug of Atmel’s ARM-based systems • Composed of the following functions – Two-pin UART – Debug Communication Channel (DCC) support – Chip ID Registers • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Interrupt generation – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of COMMRX and COMMTX signals from the ARM Processor – Interrupt generation • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of peripherals 9.5 PIO Controller • Up to 32 programmable I/O Lines • Fully programmable through Set/Clear Registers • Multiplexing of two peripheral functions per I/O Line • For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 20 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 10. User Peripherals 10.1 User Interface The User Peripherals are mapped in the upper 256M bytes of the address space, between the addresses 0xFFFA 0000 and 0xFFFE 3FFF. Each peripheral has a 16-Kbyte address space. A complete memory map is presented in Figure 8-1 on page 17. 10.2 Peripheral Identifiers The AT91RM9200 embeds a wide range of peripherals. Table 10-1 defines the peripheral identifiers of the AT91RM9200. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Peripheral Identifiers Peripheral Mnemonic AIC SYSIRQ PIOA PIOB PIOC PIOD US0 US1 US2 US3 MCI UDP TWI SPI SSC0 SSC1 SSC2 TC0 TC1 TC2 TC3 TC4 TC5 UHP EMAC AIC Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D USART 0 USART 1 USART 2 USART 3 Multimedia Card Interface USB Device Port Two-wire Interface Serial Peripheral Interface Synchronous Serial Controller 0 Synchronous Serial Controller 1 Synchronous Serial Controller 2 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 Timer/Counter 4 Timer/Counter 5 USB Host Port Ethernet MAC Advanced Interrupt Controller IRQ0 Peripheral Name Advanced Interrupt Controller External Interrupt FIQ 21 1768G–ATARM–29-Sep-06 Table 10-1. Peripheral ID 26 27 28 29 30 31 Peripheral Identifiers (Continued) Peripheral Mnemonic AIC AIC AIC AIC AIC AIC Peripheral Name Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller External Interrupt IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 10.3 Peripheral Multiplexing on PIO Lines The AT91RM9200 features four PIO controllers: • PIOA and PIOB, multiplexing I/O lines of the peripheral set • PIOC, multiplexing the data bus bits 16 to 31 and several External Bus Interface control signals. Using PIOC pins increases the number of general-purpose I/O lines available but prevents 32-bit memory access • PIOD, available in the 256-ball BGA package option only, multiplexing outputs of the peripheral set and the ETM port Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers A, B, C and D. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application. The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral mode. If equal to “I/O”, the PIO line resets in input with the pull-up enabled so that the device is maintained in a static state as soon as the NRST pin is asserted. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is in the “Reset State” column, the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case for pins controlling memories, either address lines or chip selects, and that require the pin to be driven as soon as NRST raises. Note that the pull-up resistor is also enabled in this case. See Table 10-2 on page 23, Table 10-3 on page 24, Table 10-4 on page 25 and Table 10-5 on page 26. 22 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 10.3.1 PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A MISO MOSI SPCK NPCS0 NPCS1 NPCS2 NPCS3 ETXCK/EREFCK ETXEN ETX0 ETX1 ECRS/ECRSDV ERX0 ERX1 ERXER EMDC EMDIO TXD0 RXD0 SCK0 CTS0 RTS0 RXD2 TXD2 SCK2 TWD TWCK MCCK MCCDA MCDA0 DRXD DTXD Peripheral B PCK3 PCK0 IRQ4 IRQ5 PCK1 TXD3 RXD3 PCK2 MCCDB MCDB0 MCDB1 MCDB2 MCDB3 TCLK0 TCLK1 TCLK2 IRQ6 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 IRQ3 PCK1 IRQ2 IRQ1 TCLK3 TCLK4 TCLK5 CTS2 RTS2 Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Application Usage Comments Table 10-2. 23 1768G–ATARM–29-Sep-06 10.3.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B PIO Controller B Application Usage Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O EF100 I/O I/O I/O I/O I/O Function Comments Table 10-3. I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 Peripheral A TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TF2 TK2 TD2 RD2 RK2 RF2 RI1 DTR1 TXD1 RXD1 SCK1 DCD1 CTS1 DSR1 RTS1 PCK0 FIQ IRQ0 Peripheral B RTS3 CTS3 SCK3 MCDA1 MCDA2 MCDA3 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 ETX2 ETX3 ETXER ERX2 ERX3 ERXDV ECOL ERXCK 24 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 10.3.3 PIO Controller C Multiplexing The PIO Controller C has no multiplexing and only peripheral A lines are used. Selecting Peripheral B on the PIO Controller C has no effect. Table 10-4. Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Peripheral A BFCK BFRDY/SMOE BFAVD BFBAA/SMWE BFOE BFWE NWAIT A23 A24 A25/CFRNW NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NCS7 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O A23 A24 A25 NCS4 NCS5 NCS6 NCS7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Application Usage Comments 25 1768G–ATARM–29-Sep-06 10.3.4 PIO Controller D Multiplexing The PIO Controller D multiplexes pure output signals on peripheral A connections, in particular from the EMAC MII interface and the ETM Port on the peripheral B connections. The PIO Controller D is available only in the 256-ball BGA package option of the AT91RM9200. Table 10-5. Multiplexing on PIO Controller D PIO Controller D I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 TD0 TD1 TD2 NPCS1 NPCS2 NPCS3 RTS0 RTS1 RTS2 RTS3 DTR1 Peripheral A ETX0 ETX1 ETX2 ETX3 ETXEN ETXER DTXD PCK0 PCK1 PCK2 PCK3 TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Application Usage Comments 26 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 10.3.5 System Interrupt The System Interrupt is the wired-OR of the interrupt signals coming from: • the Memory Controller • the Debug Unit • the System Timer • the Real-Time Clock • the Power Management Controller The clock of these peripherals cannot be controlled and the Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.3.6 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ6, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.4 External Bus Interface • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – Burst Flash Controller • Additional logic for NAND Flash/SmartMedia and CompactFlash support • Optimized External Bus: – 16- or 32-bit Data Bus – Up to 26-bit Address Bus, up to 64-Mbytes addressable – Up to 8 Chip Selects, each reserved to one of the eight Memory Areas – Optimized pin multiplexing to reduce latencies on External Memories • Configurable Chip Select Assignment: – Burst Flash Controller or Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia Support – Static Memory Controller on NCS4 - NCS6, Optional CompactFlash Support – Static Memory Controller on NCS7 10.5 Static Memory Controller • External memory mapping, 512-Mbyte address space • Up to 8 Chip Select Lines • 8- or 16-bit Data Bus • Remap of Boot Memory • Multiple Access Modes supported – Byte Write or Byte Select Lines – Two different Read Protocols for each Memory Bank 27 1768G–ATARM–29-Sep-06 • Multiple device adaptability – Compliant with LCD Module – Programmable Setup Time Read/Write – Programmable Hold Time Read/Write • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time 10.6 SDRAM Controller • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh and Low-power Modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • Latency is set to two clocks (CAS Latency of 1, 3 Not Supported) • Auto Precharge Command not used 10.7 Burst Flash Controller • Multiple Access Modes supported – Asynchronous or Burst Mode Byte, Half-word or Word Read Accesses – Asynchronous Mode Half-word Write Accesses • Adaptability to different device speed grades – Programmable Burst Flash Clock Rate – Programmable Data Access Time – Programmable Latency after Output Enable • Adaptability to different device access protocols and bus interfaces – Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled Address Advance – Multiplexed or separate address and data buses – Continuous Burst and Page Mode Accesses supported 28 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 10.8 Peripheral DMA Controller (PDC) • Generates transfers to/from peripherals such as DBGU, USART, SSC, SPI and MCI • Twenty channels • One Master Clock cycle needed for a transfer from memory to peripheral • Two Master Clock cycles needed for a transfer from peripheral to memory 10.9 System Timer • One Period Interval Timer, 16-bit programmable counter • One Watchdog Timer, 16-bit programmable counter • One Real-time Timer, 20-bit free-running counter • Interrupt Generation on event 10.10 Real-time Clock • Low power consumption • Full asynchronous design • Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 10.11 USB Host Port • Compliance with Open HCI Rev 1.0 specification • Compliance with USB V2.0 Full-speed and Low-speed Specification • Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices • Root hub integrated with two downstream USB ports • Two embedded USB transceivers • Supports power management • Operates as a master on the Memory Controller 10.12 USB Device Port • USB V2.0 full-speed compliant, 12 Mbits per second • Embedded USB V2.0 full-speed transceiver • Embedded dual-port RAM for endpoints • Suspend/Resume logic • Ping-pong mode (two memory banks) for isochronous and bulk endpoints • Six general-purpose endpoints – Endpoint 0, Endpoint 3: 8 bytes, no ping-pong mode – Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode – Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode 10.13 Ethernet MAC • Compatibility with IEEE Standard 802.3 29 1768G–ATARM–29-Sep-06 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operation • MII or RMII interface to the physical layer • Register interface to address, status and control registers • DMA interface, operating as a master on the Memory Controller • Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Supports promiscuous mode where all valid frames are copied to memory • Supports physical layer management through MDIO interface 10.14 Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Connection to PDC channel optimizes data transfers – One channel for the receiver, one channel for the transmitter – Next buffer support 10.15 Two-wire Interface • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential Read/Write operations 10.16 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection 30 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 – MSB- or LSB-first – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Optional hardware handshaking RTS-CTS – Optional modem signal management DTR-DSR-DCD-RI – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Connection of two Peripheral DMA Controller (PDC) channels – Offers buffer transfer without processor intervention The USART describes features allowing management of the Modem Signals DTR, DSR, DCD and RI. For details, see ”Modem Mode” on page 435. In the AT91RM9200, only the USART1 implements these signals, named DTR1, DSR1, DCD1 and RI1. The USART0, USART2 and USART3 do not implement all the modem signals. Only RTS and CTS (RTS0 and CTS0, RTS2 and CTS2, RTS3 and CTS3, respectively) are implemented in these USARTs for other features. Thus, programming the USART0, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated. 10.17 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider • Interfaced with two PDC channels to reduce processor overhead • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.18 Timer Counter • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting 31 1768G–ATARM–29-Sep-06 – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Internal interrupt signal • Two global registers that act on all three TC Channels • The Timer Counter 0 to 5 are described with five generic clock inputs, TIMER_CLOCK1 to TIMER_CLOCK5. In the AT91RM9200, these clock inputs are connected to the Master Clock (MCK), to the Slow Clock (SLCK) and to divisions of the Master Clock. For details, see ”Clock Control” on page 488. Table 10-6 gives the correspondence between the Timer Counter clock inputs and clocks in the AT91RM9200. Each Timer Counter 0 to 5 displays the same configuration. Table 10-6. Timer Counter Clocks Assignment TC Clock Input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Clock MCK/2 MCK/8 MCK/32 MCK/128 SLCK 10.19 MultiMedia Card Interface • Compatibility with MultiMedia Card Specification Version 2.2 • Compatibility with SD Memory Card Specification Version 1.0 • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used • Supports two slots – One slot for one MultiMedia Card bus (up to 30 cards) or one SD Memory Card • Support for stream, block and multi-block data read and write • Connection to a Peripheral DMA Controller (PDC) channel – Minimizes processor intervention for large buffer transfers 32 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 11. ARM920T Processor Overview 11.1 Overview The ARM920T cached processor is a member of the ARM9™ Thumb family of high-performance 32-bit system-on-a-chip processors. It provides a complete high performance CPU subsystem including: • ARM9TDMI RISC integer CPU • 16-Kbyte instruction and 16-Kbyte data caches • Instruction and data memory management units (MMUs) • Write buffer • AMBA™ (Advanced Microprocessor Bus Architecture) bus interface • Embedded Trace Macrocell (ETM) interface The ARM9TDMI core within the ARM920T executes both the 32-bit ARM and 16-bit Thumb instruction sets. The ARM9TDMI processor is a Harvard architecture device, implementing a five-stage pipeline consisting of Fetch, Decode, Execute, Memory and Write stages. The ARM920T processor incorporates two coprocessors: • CP14 - Controls software access to the debug communication channel • CP15 - System Control Processor, providing 16 additional registers that are used to configure and control the caches, the MMU, protection system, clocking mode and other system options The main features of the ARM920T processor are: • ARM9TDMI-based, ARM Architecture v4T • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • 5-Stage Pipeline Architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory Access (M) – Register Write (W) • 16-Kbyte Data Cache, 16-Kbyte Instruction Cache – Virtually-addressed 64-way Associative Cache – 8 Words per Line – Write-though and Write-back Operation – Pseudo-random or Round-robin Replacement – Low-power CAM RAM Implementation • Write Buffer – 16-word Data Buffer – 4-address Address Buffer – Software Control Drain 33 1768G–ATARM–29-Sep-06 • Standard ARMv4 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for Large Pages and Small Pages Can be Specified Separately for Each Quarter of the Pages – 16 Embedded Domains – 64-entry Instruction TLB and 64-entry Data TLB • 8-, 16-, 32-bit Data Bus for Instructions and Data 34 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 11.2 Block Diagram Figure 11-1. ARM920T Internal Functional Block Diagram ARM920T Instruction Cache Instruction MMU Instruction Physical Address Bus R13 Instruction Modified Virtual Address Bus Instruction Virtual Address Bus ICE Interface Instruction Bus ICE ARM9TDMI CP15 Bus Interface Memory Controller Data Virtual Address Bus Data Bus Write Buffer R13 Data Modified Virtual Address Bus Data Physical Address Bus Data Cache Data MMU Data Index Bus Write Back PA TAG RAM Write Back Physical Address Bus 35 1768G–ATARM–29-Sep-06 11.3 11.3.1 ARM9TDMI Processor Instruction Type Instructions are either 32 bits (in ARM state) or 16 bits (in Thumb state). 11.3.2 Data Types ARM9TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half-words to two-byte boundaries. Unaligned data access behavior depends on which instruction is used in a particular location. 11.3.3 ARM9TDMI Operating Modes The ARM9TDMI, based on ARM architecture v4T, supports seven processor modes: • User: Standard ARM program execution state • FIQ: Designed to support high-speed data transfer or channel processes • IRQ: Used for general-purpose interrupt handling • Supervisor: Protected mode for the operating system • Abort mode: Implements virtual memory and/or memory protection • System: A privileged user mode for the operating system • Undefined: Supports software emulation of hardware coprocessors Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs will execute in User Mode. The nonuser modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 11.3.4 ARM9TDMI Registers The ARM9TDMI processor core consists of a 32-bit datapath and associated control logic. That datapath contains 31 general-purpose registers, coupled to a full shifter, Arithmetic Logic Unit and multiplier. At any one time, 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer. Table 11-1. User and System Mode R0 R1 R2 R3 ARM9TDMI Modes and Register Layout Supervisor Mode R0 R1 R2 R3 Undefined Mode R0 R1 R2 R3 Interrupt Mode R0 R1 R2 R3 Fast Interrupt Mode R0 R1 R2 R3 Abort Mode R0 R1 R2 R3 36 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 11-1. User and System Mode R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC ARM9TDMI Modes and Register Layout (Continued) Supervisor Mode R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC Undefined Mode R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC Abort Mode R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC CPSR CPSR SPSR_SVC CPSR SPSR_ABO RT CPSR SPSR_UND EF CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers Registers R0 to R7 are unbanked registers, thus each of them refers to the same 32-bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a general-purpose register to be specified. Registers R8 to R14 are banked registers. This means that each of them depends of the current processor mode. For further details, see the ARM Architecture Reference Manual, Rev. DDI0100E. 11.3.4.1 Modes and Exception Handling All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used both to return after the exception is processed and to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without the need to save these registers. 37 1768G–ATARM–29-Sep-06 A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 11.3.4.2 Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: • four ALU flags (Negative, Zero, Carry, and Overflow), • two interrupt disable bits (one for each type of interrupt), • one bit to indicate ARM or Thumb execution • five bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) which holds the CPSR of the task immediately before the exception occurred. 11.3.4.3 Exception Types The ARM9TDMI supports five types of exceptions and a privileged processing mode for each type. The types of exceptions are: • fast interrupt (FIQ) • normal interrupt (IRQ) • memory aborts (used to implement memory protection or virtual memory) • attempted execution of an undefined instruction • software interrupt (SWIs) Exceptions are generated by internal and external sources. More than one exception can occur at the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. To return after handling the exception, the SPSR is moved to the CPSR and R14 is moved to the PC. This can be done in two ways: • use of a data-processing instruction with the S-bit set, and the PC as the destination • use of the Load Multiple with Restore CPSR instruction (LDM) 11.3.5 ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions • Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C. 38 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 11-2 gives the ARM instruction mnemonic list. Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Mnemonic CDP MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR STRH STRB STRBT STRT STM SWPB MRC STC Operation Coprocessor Data Processing Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor 11.3.6 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store multiple instructions • Exception-generating instruction In Thumb mode, eight general-purpose registers are available, R0 to R7, that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the 39 1768G–ATARM–29-Sep-06 Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM register 8 to 15. For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C. Table 11-3 gives the Thumb instruction mnemonic list. Table 11-3. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack BL SWI STR STRH STRB LDRSB STMIA POP Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Mnemonic MVN ADC SBC CMN NEG BIC ORR LSR ROR Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right 40 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 11.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used when special features are used with the ARM9TDMI such as: • On-chip Memory Management Unit (MMU) • Instruction and/or Data Cache • Write buffer To control these features, CP15 provides 16 additional registers. See Table 11-4. Table 11-4. Register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Notes: CP15 Registers Name ID Register Control Translation Table Base Domain Access Control Reserved Fault Status Fault Address Cache Operations TLB (1) Access Read-only Read/Write Read/Write Read/Write None Read/Write Read/Write Write-only Write-only Read/Write Read/Write None None Read/Write None None Operations cache lockdown TLB lockdown Reserved Reserved FCSE PID(2) Reserved Test configuration 1. TLB: Translation Lookaside Buffer 2. FCSE PID: Fast Context Switch Extension Process Identifier 11.4.1 CP15 Register Access • MCR (Move to Coprocessor from ARM Register) instruction • MRC (Move to ARM Register from Coprocessor) instruction CP15 registers can only be accessed in privileged mode by: Other instructions (CDP, LDC, STC) cause an undefined instruction exception. The MCR instruction is used to write an ARM register to CP15. The MRC instruction is used to read the value of CP15 to an ARM register. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. 41 1768G–ATARM–29-Sep-06 The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 27 26 25 24 Cond 23 22 21 20 1 19 1 18 1 17 0 16 opcode_1 15 14 13 L 12 11 10 CRn 9 8 Rd 7 6 5 4 1 3 1 2 1 1 1 0 opcode_2 1 CRm • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. • opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. • Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • Cond [31:28]: Condition 42 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 11.5 Memory Management Unit (MMU) The ARM920T processor implements an enhanced ARM architecture v4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI core. The MMU is controlled from a single set of two-level page tables stored in the main memory, providing a single address and translation protection scheme. Independently, instruction and data TLBs in the MMU can be locked and flushed. Table 11-5. Mapping Details Mapping Size 1M byte 64K bytes 4K bytes 1K byte Access Permission By Section 4 separated subpages 4 separated subpages Tiny Page Subpage Size 16K bytes 1K byte - Mapping Name Section Large Page Small Page Tiny Page 11.5.1 Domain A domain is a collection of sections and pages. The ARM920T supports 16 domains. Access to the domains is controlled by the Domain Access Control register. For details, refer to ”CP15 Register 3, Domain Access Control Register” on page 50. 11.5.2 MMU Faults The MMU generates alignment faults, translation faults, domain faults and permission faults. Alignment fault checking is not affected by whether the MMU is enabled or not. The access controls of the MMU detect the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU stores the status and address fault in the FSR and FAR registers (only for faults generated by data access). The MMU does not store fault information about faults generated by an instruction fetch. The memory system can abort during line fetches, memory accesses and translation table access. 43 1768G–ATARM–29-Sep-06 11.6 Caches, Write Buffers and Physical Address The ARM920T includes an Instruction Cache (ICache), a Data Cache (DCache), a write buffer and a Physical Address (PA) TAG RAM to reduce the effect on main memory bandwidth and latency performance. The ARM920T implements separate 16-Kbyte Instruction and 16-Kbyte Data Caches. The caches and the write buffer are controlled by the CP15 Register 1 (Control), CP15 Register 7 (Cache Operations) and CP15 Register 9 (Cache Lockdown). 11.6.1 Instruction Cache (ICache) The ARM920T includes a 16-Kbyte Instruction Cache (ICache). The ICache has 512 lines of 32 bytes, arranged as a 64-way set associative cache. Instruction access is subject to MMU permission and translation checks. If the ICache is enabled with the MMU disabled, all instructions fetched as threats are cachable. No protection checks are made and the physical address is flat-mapped to the modified virtual address. When the ICache is disabled, the cache contents are ignored and all instruction fetches appear on the AMBA bus. On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. The ICache is enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this bit. For more details, see ”CP15 Register 1, Control” on page 48. The ICache is organized as eight segments, each containing 64 lines with each line made up of 8 words.The position of the line within the segment is called the index and is numbered from 0 to 63. A line in the cache is identified by the index and segment. The index is independent of the MVA (Modified Virtual Address), and the segment is the bit[7:5] of the MVA. 11.6.2 Data Cache (DCache) and Write Buffer The ARM920T includes a 16-Kbyte data cache (DCache). The DCache has 512 lines of 32 bytes, arranged as a 64-way set associative cache, and uses MVAs translated by CP15 Register 13 from the ARM9DTMI core. 11.6.2.1 DCache The DCache is organized as eight segments, each containing 64 lines with each line made up of eight words.The position of the line within the segment is called the index and is a number from 0 to 63. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. All data accesses are subject to MMU permission and translation checks. Data accesses aborted by the MMU cannot cause linefill or data access via the AMBA ASB interface. 44 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Write-though Operation When a cache hit occurs for a data access, the cache line that contains the data is updated to contains its value. The new data is also immediately written to the main memory. When a cache hit occurs for a data access, the cache line is marked as dirty, meaning that its contents are not up-to-date with those in the main memory. Write-back Operation 11.6.2.2 Write Buffer The ARM920T incorporates a 16-entry write buffer to avoid stalling the processor when writes to external memory are performed. When a store occurs, its data, address and other details are written to the write buffer at high speed. The write buffer then completes the store at the main memory speed (typically slower than the ARM speed). In parallel, the ARM9TDMI processor can execute further instructions at full speed. 11.6.2.3 Physical Address Tag RAM (PA TAG RAM) The ARM920T implements Physical Address Tag RAM (PA TAG RAM) to perform write-backs from the data cache. The physical address of all the lines held in the data cache is stored in the PA TAG memory, removing the need for address translation when evicting a line from the cache. When a line is written into the data cache, the physical address TAG is written into the PA TAG RAM. If this line has to be written back to the main memory, the PA TAG RAM is read and the physical address is used by the AMBA ASB interface to perform the write-back. For a 16-Kbyte DCache, the PA TAG RAM is organized by eight segments with: • 64 rows per segments • 26 bits per rows • be 45 1768G–ATARM–29-Sep-06 11.7 11.7.1 ARM920T User Interface CP15 Register 0, ID Code and Cache Type Access: Read-only The CP Register 0 contains specific hardware information. The contents of the read accesses are determined by the opcode_2 field value. Writing to Register 0 is unpredictable. 11.7.1.1 ID Code The ID code register is accessed by reading the register 0 with the opcode_2 field set to 0. The contents of the ID code is shown below: 31 30 29 28 27 26 25 24 imp 23 22 21 20 19 18 17 16 SRev 15 14 13 12 11 10 archi 9 8 PNumber 7 6 5 4 3 2 1 0 Layout Rev • LayoutRev[3:0]: Revision Contains the processor revision number • PNumber[15:4]: Processor Part Number 0x920 value for ARM920T processor. • archi[19:16]: Architecture Details the implementor architecture code. 0x2 value means ARMv4T architecture. • SRev[23:20]: Specification Revision Number 0x1 value; specification revision number used to distinguished two variants of the same primary part. • imp[31:24]: Implementor Code 0x41 (= A); means ARM Ltd. 46 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 11.7.1.2 Cache Type The Cache Type register is accessed by reading the register 0 with the opcode_2 field set to 1. The Cache Type register contains information about the size and architecture of the caches. 31 30 29 28 27 26 25 24 0 23 0 22 0 21 20 19 ctype 18 17 S 16 DSize 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISize • ISize[11:0]: Instruction Cache Size Indicates the size, line length and associativity of the instruction cache. • DSize[23:12]: Data Cache Size Indicates the size, line length and associativity of the data cache. • S[24]: Cache Indicates if the cache is unified or has separate instruction and data caches. Set to 1, this field indicates separate Instruction and Data caches. • ctype[28:25]: Cache Type Defines the cache type. For details on bits DSize and ISize, refer to the ARM920T Technical Reference Manual, Rev. DDI0151C. 47 1768G–ATARM–29-Sep-06 11.7.2 CP15 Register 1, Control Access: Read/Write The CP15 Register 1, or Control Register, contains the control bits of the ARM920T. 31 30 29 28 27 26 25 24 iA 23 nF 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 RR 6 V 5 I 4 0 3 0 2 R 1 S 0 B 1 1 1 1 C A M • M[0]: MMU Enable 0 = MMU disabled. 1 = MMU enabled. • A[1]: Alignment Fault Enable 0 = Fault checking disabled. 1 = Fault checking enabled. • C[2]: DCache Enable 0 = DCache disabled. 1 = DCache enabled. • B[7]: Endianness 0 = Little endian mode. 1 = Big endian mode. • S[8]: System Protection Modifies the MMU protection system. For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C. • R[9]: ROM Protection Modifies the MMU protection system. For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C. • I[12]: ICache Control 0 = ICache disabled. 1 = ICache enabled. 48 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • V[13]: Base Location of Exception Register 0 = Low address means 0x00000000. 1 = High address means 0xFFFF0000. • RR[14]: Round Robin Replacement 0 = Random replacement. 1 = Round robin replacement. • Clocking Mode[31:30] (iA and nF bits) iA 0 0 1 1 nF 0 1 0 1 Clocking mode Fast Bus Synchronous Reserved Asynchronous 11.7.3 CP15 Register 2, TTB Access: Read/Write The CP15 Register 2, or Translation Table Base (TTB) Register, defines the first-level translation table. 31 30 29 28 27 26 25 24 Pointer 23 22 21 20 19 18 17 16 Pointer 15 14 13 12 11 10 9 8 Pointer 7 6 5 4 3 2 1 0 - - - - - - - - • Pointer[31:14] Points to the first-level translation table base. Read returns the currently active first-level translation table. Write sets the pointer to the first-level table to the written value. The non-defined bits should be zero when written and are unpredictable when read. 49 1768G–ATARM–29-Sep-06 11.7.4 CP15 Register 3, Domain Access Control Register Access: Read/Write The CP 15 Register 3, or Domain Access Control Register, defines the domain’s access permission. MMU accesses are priory controlled through the use of 16 domains. Each field of Register 3 is associated with one domain. 31 30 29 28 27 26 25 24 D15 23 22 21 D14 20 19 D13 18 17 D12 16 D11 15 14 13 D10 12 11 D9 10 9 D8 D 8 D7 7 6 5 D6 4 3 D5 2 1 D4 0 D3 D2 D1 D0 • D15 to D0: Named Domain Access The 2-bit field value allows domain access as described in the table below. Value 0 0 1 1 0 1 0 1 Access No access Client Reserved Manager Description Any access generates a domain fault The Users of domain (execute programs, access data), the domain access permission controlled the domain access. Reserved Controls the behavior of the domain, no checking of the domain access permission is done 11.7.5 CP15 Register 4, Reserved Any access (Read or Write) to this register causes unpredictable behavior. 50 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 11.7.6 CP15 Register 5, Fault Status Register Access: Read/Write Reading the CP 15 Register 5, or Fault Status Register (FSR), returns the source of the last data fault, indicating the domain and type of access being attempted when the data abort occurred. In addition, the virtual address which caused the data abort is written into the Fault Address Register (CP15 Register 6). Writing the CP 15 Register 5, or Fault Status Register (FSR), sets the FSR to the value of the data written. This is useful for a debugger to restore the value of the FSR. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 D 8 7 6 5 4 3 2 1 0 Domain Status • Status[3:0]: Fault Type Indicates the fault type. The status field is encoded by the MMU when a data abort occurs. The interpretation of the Status field is dependant on the domain field and the MVA associated with the data abort (stored in the FAR). • Domain[7:4]: Domain Indicates the domain (D15 - D0) being accessed when the fault occurred. The non-defined bits should be zero when written and are unpredictable when read. 51 1768G–ATARM–29-Sep-06 11.7.7 CP15 Register 6, Fault Address Register Access: Read/Write The CP 15 Register 6, or Fault Address Register (FAR), contains the MVA (Modified Virtual Address) of the access being attempted when the last fault occurred. The FAR is only updated for data faults, not for prefetch faults. The ability to write to the FAR is provided to allow a debugger to restore a previous state. 31 30 29 28 27 26 25 24 FAR 23 22 21 20 19 18 17 16 D FAR 15 14 13 12 11 10 9 8 FAR 7 6 5 4 3 2 1 0 FAR • FAR[31:0]: Fault Address On reading: returns the value of the FAR. The FAR holds the virtual address of the access which was attempted when fault occurred. On writing: sets the FAR to the value of the written data. This is useful for a debugger to restore the value of the FAR. 11.7.8 CP15 Register 7, Cache Operation Register Access: Write-only The CP15 Register 7, or Cache Operation Register, is used to manage the Instruction Cache (ICache) and the Data Cache (DCache). The function of each cache operation is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 Register 7. Table 11-6. Function Wait for Interrupt Invalidate ICache Invalidate ICache single entry (using MVA) Invalidate DCache Invalidate DCache single entry (using MVA) Invalidate ICache and DCache Clean DCache singe entry (using MVA) Clean DCache single entry (using index) Drain write buffer Prefetch ICache line (using MVA) Clean and Invalidate DCache entry (using MVA) Clean and Invalidate DCache entry (using index) Cache Functions Data SBZ SBZ MVA format SBZ MVA format SBZ MVA format Index format SBZ MVA format MVA format Index format CRm c0 c5 c5 c6 c6 c7 c10 c10 c10 c13 c14 c14 opcode_2 4 0 1 0 1 0 1 2 4 1 1 2 52 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Function Details • Wait for interrupt Stops execution in low-power state until an interrupt occurs. • Invalidate The cache line (or lines) is marked as invalid, so no cache hits occur in that line until it is re-allocated to an address. • Clean Applies to write-back data caches. If the cache line contains stored data that has not yet been written out to the main memory, it is written to main memory immediately. • Drain write buffer Stops the execution until all data in the write buffer has been stored in the main memory. • Prefetch The memory cache line at the specified virtual address is loaded into the cache. The operation carried out on a single cache line identifies the line using the data transferred in the MCR instruction. The data is interpreted as using one of the two formats: – MVA format – index format Below are the details of CP15 Register 7, or Cache Function Register, in MVA format. 31 30 29 28 27 26 25 24 mva 23 22 21 20 19 18 17 16 mva 15 14 13 12 11 10 9 8 mva 7 6 5 4 3 2 1 0 mva - - - - - • mva[31:5]: Modified Virtual Address The non-defined bits should be zero when written and are unpredictable when read. 53 1768G–ATARM–29-Sep-06 Below the details of CP15 Register 7, or Cache Function Register, in Index format: 31 30 29 28 27 26 25 24 index 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 set - - - - - • index[31:26]: Line Determines the cache line. • set[7:5]: Segment Determines the cache segment. The non-defined bits should be zero when written and are unpredictable when read. Writing other opcode_2 values or CRm values is unpredictable. Reading from CP15 Register 7 is unpredictable. 54 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 11.7.9 CP15 Register 8, TLB Operations Register Access: Write-only The CP15 Register 8, or Translation Lookaside Buffer (TLB) Operations Register, is used to manage instruction TLBs and data TLBs. The TLB operation is selected by opcode_2 and CRm fields in the MCR instruction used to write CP15 Register 8. Table 11-7. Function Invalidate I TLB Invalidate I TLB single entry (using MVA) Invalidate D TLB Invalidate D TLB single entry (using MVA) Invalidate both Instruction and Data TLB TLB Operations Data SBZ MVA format SBZ MVA format SBZ CRm 5 5 6 6 7 opcode_2 0 1 0 1 Below are details of the CP15 Register 8 for TLB operation on MVA format and one single entry. 31 30 29 28 27 26 25 24 mva 23 22 21 20 19 18 17 16 mva 15 14 13 12 11 10 9 8 mva 7 6 5 4 3 2 1 0 - - - - - - - - • mva[31:10]: Modified Virtual Address The non-defined bits should be zero when written and are unpredictable when read. Writing other opcode_2 values or CRm values is unpredictable. Reading from CP15 Register 8 is unpredictable. 55 1768G–ATARM–29-Sep-06 11.7.10 CP15 Register 9, Cache Lockdown Register Access: Read/Write The CP15 Register 9, or Cache Lockdown Register, is 0x0 on reset. The Cache Lockdown Register allows software to control which cache line in the ICache or DCache is loaded for a linefill. It prevents lines in the ICache or DCache from being evicted during a linefill, locking them into the cache. Reading from the CP15 Register 9 returns the value of the Cache Lockdown Register that is the base pointer for all cache segments. Only the bits[31:26] are returned; others are unpredictable. Writing to the CP15 Register 9 updates the Cache Lockdown Register with both the base and the current victim pointers for all cache segments. Table 11-8. Function Cache Lockdown Functions Data Base Victim = Base Base Victim = Base CRm 0 0 0 0 opcode_2 0 0 1 1 Read DCache lockdown base Write DCache victim and lockdown base Read ICache lockdown base Write ICache victim and lockdown base 31 30 29 28 27 26 25 24 index 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - - - - - - • index[31:26]: Victim Pointer Current victim pointer that specifies the cache line to be used as victim for the next linefill. The non-defined bits should be zero when written and are unpredictable when read. 56 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 11.7.11 CP15 Register 10, TLB Lockdown Register Access: Read/Write The CP15 Register 10, or TLB Lockdown Register, is 0x0 on reset. There is a TLSB Lockdown Register for each of the TLBs; the value of opcode_2 determines which TLB register to access: • opcode_2 = 0x0 for D TLB register • opcode_2 = 0x1 for I TLB register Table 11-9. Function TLB Lockdown Functions Data TLB lockdown TLB lockdown TLB lockdown TLB lockdown CRm 0 0 0 0 Opcode_2 0 0 1 1 Read D TLB lockdown Write D TLB lockdown Read I TLB lockdown Write I TLB lockdown 31 30 29 28 27 26 25 24 Base 23 22 21 20 19 18 17 16 Victim 15 14 13 12 11 10 9 D 8 7 6 5 4 3 2 1 0 - - - - - - - P • Base[31:26]: Base The TLB replacement strategy only uses the TLB entries numbered from base to 63. The Victim field provided is in that range. • Victim[25:20]: Victim Counter Specifies the TLB entry (line) being overwritten. • P[0]: Preserved If 0, the TLB entry can be invalidated. If 1, the TLB entry is protected. It cannot be invalidated during the Invalidate All instruction. Refer to ”CP15 Register 8, TLB Operations Register” on page 55. The non-defined bits should be zero when written and are unpredictable when read. 11.7.12 CP15 Registers 11, 12, Reserved Any access (Read or Write) to these registers causes unpredictable behavior. 57 1768G–ATARM–29-Sep-06 11.7.13 CP15 Register 13, FCSE PID Register Access: Read/Write The CP15 Register 13, or Fast Context Switch Extension (FCSE) Process Identifier (PID) Register, is set to 0x0 on reset. Reading from CP15 Register 13 returns the FCSE PID value. Writing to CP15 Register 13 sets the FCSE PID. The FCSE PID sets the mapping between the ARM9TDMI and the MMU of the cache memories. The addresses issued by the ARM9TDMI are in the range of 0 to 32 Mbytes and are translated via the FCSE PID. 31 30 29 28 27 26 25 24 FCSEPID 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 D 8 7 6 5 4 3 2 1 0 - - - - - - - - • FCSEPID[31:25]: FCSE PID The FCSE PID modifies the behavior of the of the ARM920T memory system. This modification allows multiple programs to run on the ARM. The 4-GB virtual address is divided into 128 process blocks of 32 Mbytes each. Each process block can contain a program that has been compiled to use the address range 0x00000000 to 0x01FFFFFF. For each i = 0 to 127 process blocks, i runs from address i*0x20000000 to address i*0x20000000 + 0x01FFFFFF. For further details, see the ARM920T Technical Reference Manual, Rev. DDI0151C. The non-defined bits should be zero when written and are unpredictable when read. 11.7.14 CP15 Register 14, Reserved Any access (Read or Write) of these registers causes unpredictable behavior. 11.7.15 CP15 Register 15, Test Configuration Register CP15 Register 15, or Test Configuration Register, is used for test purposed. Any access (write or read) to this register causes unpredictable behavior. 58 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 12. Debug and Test Features (DBG Test) 12.1 Overview The AT91RM9200 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions such as downloading code and single-stepping through programs. An ETM (Embedded Trace Macrocell) provides more sophisticated debug features such as address and data comparators, half-rate clock mode, counters, sequencer and FIFO. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins give direct access to these capabilities from a PC-based test environment. Features of Debug and Test Features are: • Integrated Embedded In-Circuit-Emulator • Debug Unit – Two-pin UART – Debug Communication Channel – Chip ID Register • Embedded Trace Macrocell: ETM9 Rev2a – Medium Level Implementation – Half-rate Clock Mode – Four Pairs of Address Comparators – Two Data Comparators – Eight Memory Map Decoder Inputs – Two Counters – One Sequencer – One 18-byte FIFO • IEEE1149.1 JTAG Boundary Scan on all Digital Pins 59 1768G–ATARM–29-Sep-06 12.2 Block Diagram Figure 12-1. AT91RM9200 Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP JTAGSEL TDO Boundary Port TPK0-TPK15 PIO TPS0-TPS2 TSYNC 2 ARM920T TCLK ARM9TDMI ICE ETM DTXD PDC DBGU DRXD Reset and Test TST0-TST1 NRST TAP: Test Access Port 60 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 12.3 12.3.1 Application Examples Debug Environment Figure 12-2 on page 61 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. AT91RM9200-based Application Debug and Trace Environment Example Host Debugger ICE/JTAG Interface Trace Port Interface ICE/JTAG Connector Trace Connector RS232 Connector AT91RM9200 Terminal AT91RM9200-based Application Board 12.4 Test Environment Figure 12-3 below shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board under test” is designed using many JTAG compliant devices. These devices can be connected together to form a single scan chain. 61 1768G–ATARM–29-Sep-06 Figure 12-3. AT91RM9200-based Application IEEE1149.1 Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91RM920 Chip 1 AT91RM9200-based Application Board Under Test 12.5 Debug and Test Pin Description Debug and Test Pin List Function Reset/Test Type Active Level Table 12-1. Pin Name NRST TST0 TST1 Microcontroller Reset Test Mode Select Test Mode Select ICE and JTAG Input Input Input Low TCK TDI TDO TMS NTRST JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal JTAG Selection ETM (available only in BGA package) Input Input Output Input Input Input Low TSYNC TCLK TPS0- TPS2 TPK0 - TPK15 Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Trace Packet Port Debug Unit Output Output Output Output DRXD DTXD Debug Receive Data Debug Transmit Data Input Output DRXD DTXD 62 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 12.6 12.6.1 Functional Description Test Mode Pins Two dedicated pins (TST1, TST0) are used to define the test mode of the device. The user must make sure that these pins are both tied at low level to ensure normal operating conditions. Other values associated to these pins are manufacturing test reserved. 12.6.2 Embedded In-Circuit Emulator The ARM9TDMI Embedded In-Circuit Emulator is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9TDMI core embedded within the ARM920T. The internal state of the ARM920T is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9TDMI registers. This data can be serially shifted out without affecting the rest of the system. There are six scan chains inside the ARM920T processor which support testing, debugging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed (NRST and NTRST) after JTAGSEL is changed. The test reset input to the embedded ICE (NTRST) is provided separately to facilitate debug of the boot program. For further details on the Embedded In-Circuit-Emulator, see the ARM920T Technical Reference Manual, ARM Ltd, - DDI 0151C. 12.6.3 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) UART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the link with two Peripheral DMA Controller channels provides packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and trace the activity of the Debug Communication Channel. The Debug Unit can be used to upload an application into internal SRAM. It is activated by the boot program when no valid application is detected. A specific register, the Debug Unit Chip ID Register, informs about the product version and its internal configuration. The AT91RM9200 Debug Unit Chip ID value is: 0x09290781, on 32-bit width. For further details on the Debug Unit, see ”Debug Unit (DBGU)” on page 321. For further details on the Debug Unit and the Boot program, see ”Boot Program” on page 83. 12.6.4 Embedded Trace Macrocell The AT91RM9200 features an Embedded Trace Macrocell (ETM), which is closely connected to the ARM9TDMI Processor. The Embedded Trace is a standard mid-level implementation and contains the following resources: • Four pairs of address comparators 63 1768G–ATARM–29-Sep-06 • Two data comparators • Eight memory map decoder inputs • Two counters • One sequencer • Four external inputs • One external output • One 18-byte FIFO The Embedded Trace Macrocell of the AT91RM9200 works in half-rate clock mode and thus integrates a clock divider. This assures that the maximum frequency of all the trace port signals do not exceed one half of the ARM920T clock speed. The Embedded Trace Macrocell input and output resources are not used in the AT91RM9200. The Embedded Trace is a real-time trace module with the capability of tracing the ARM9TDMI instruction and data. The Embedded Trace debug features are only accessible in the AT91RM9200 BGA package. For further details on Embedded Trace Macrocell, see the ETM9 (Rev2a) Technical Reference Manual, ARM Ltd. -DDI 0157E. 12.6.4.1 Trace Port The Trace Port is made up of the following pins: • TSYNC - the synchronization signal (Indicates the start of a branch sequence on the trace packet port.) • TCLK - the Trace Port clock, half-rate of the ARM920T processor clock. • TPS0 to TPS2 - indicate the processor state at each trace clock edge. • TPK0 to TPK15 - the Trace Packet data value. The trace packet information (address, data) is associated with the processor state indicated by TPS. Some processor states have no additional data associated with the Trace Packet Port (i.e. failed condition code of an instruction). The packet is 8-bits wide, and up to two packets can be output per cycle. 64 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 12-4. ETM9 Block TPS-TPS0 ARM920T Bus Tracker Trace Control FIFO TPK15-TPK0 TSYNC Trace Enable, View Data TAP Controller Trigger, Sequencer, Counters Scan Chain 6 ETM9 TMS TCK TDO TDI 12.6.4.2 Implementation Details This section gives an overview of the Embedded Trace resources. For further details, see the Embedded Trace Macrocell Specification, ARM Ltd. -IHI 0014H. Three-state Sequencer The sequencer has three possible next states (one dedicated to itself and two others) and can change on every clock cycle. The sate transition is controlled with internal events. If the user needs multiple-stage trigger schemes, the trigger event is based on a sequencer state. Address Comparator In single mode, address comparators compare either the instruction address or the data address against the user-programmed address. In range mode, the address comparators are arranged in pairs to form a virtual address range resource. Details of the address comparator programming are: • The first comparator is programmed with the range start address. • The second comparator is programmed with the range end address. • The resource matches if the address is within the following range: – (address > = range start address) AND (address < range end address) • Unpredictable behavior occurs if the two address comparators are not configured in the same way. Data Comparator Each full address comparator is associated with a specific data comparator. A data comparator is used to observe the data bus only when load and store operations occur. A data comparator has both a value register and a mask register, therefore it is possible to compare only certain bits of a preprogrammed value against the data bus. 65 1768G–ATARM–29-Sep-06 Memory Decoder Inputs The eight memory map decoder inputs are connected to custom address decoders. The address decoders divide the memory into regions of on-chip SRAM, on-chip ROM, and peripherals. The address decoders also optimize the ETM9 trace trigger. Table 12-2. Description SRAM SRAM ROM ROM NCS0-NCS7 NCS0-NCS7 User Peripheral System Peripheral ETM Memory Map Inputs Layout Region Internal Internal Internal Internal External External Internal Internal Access type Data Fetch Data Fetch Data Fetch Data Data start_address 0x00000000 0x00000000 0x00100000 0x00100000 0x10000000 0x10000000 0xF0000000 0xFFFFF000 end_address 0x000FFFFF 0x000FFFFF 0x001FFFFF 0x001FFFFF 0x8FFFFFFF 0x8FFFFFFF 0xFFFFEFFF 0xFFFFFFFF FIFO An 18-byte FIFO is used to store data tracing. The FIFO is used to separate the pipeline status from the trace packet. So, the FIFO can be used to buffer trace packets. A FIFO overflow is detected by the embedded trace macrocell when the FIFO is full or when the FIFO has less bytes than the user-programmed number. For further details, see the ETM9 (Rev2a) Technical Reference Manual, ARM Ltd. DDI 0157E. Half-rate Clocking Mode The ETM9 is implemented in half-rate mode that allows both rising and falling edge data tracing of the trace clock. The half-rate mode is implemented to maintain the signal clock integrity of high speed systems (up to 100 Mhz). Figure 12-5. Half-rate Clocking Mode ARM920T Clock Trace Clock TraceData Half-rate Clocking Mode Care must be taken on the choice of the trace capture system as it needs to support half-rate clock functionality. 66 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 12.6.4.3 Application Board Restriction The TCLK signal needs to be set with care, some timing parameters are required. Refer to AT91RM9200 ”JTAG/ICE Timings” on page 649 and ”ETM Timings” on page 652. The specified target system connector is the AMP Mictor connector. The connector must be oriented on the application board as described below in Figure 12-6. The view of the PCB is shown from above with the trace connector mounted near the edge of the board. This allows the Trace Port Analyzer to minimize the physical intrusiveness of the interconnected target. Figure 12-6. AMP Mictor Connector Orientation AT91RM9200-based Application Board 38 37 2 1 Pin 1Chamfer 12.6.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed (NRST and NTRST) after JTAGSEL is changed. Two Boundary Scan Descriptor Language (BSDL) files are provided to set up testing. Each BSDL file is dedicated to a specific packaging. 12.6.5.1 JTAG Boundary Scan Register The Boundary Scan Register (BSR) contains 449 bits which correspond to active pins and associated control signals. Each AT91RM9200 input pin has a corresponding bit in the Boundary Scan Register for observability. Each AT91RM9200 output pin has a corresponding 2-bit register in the BSR. The OUTPUT bit contains data which can be forced on the pad. The CTRL bit can put the pad into high impedance. 67 1768G–ATARM–29-Sep-06 Each AT91RM9200 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CTRL bit selects the direction of the pad. Table 12-3. Bit Number 449 448 447 446 445 444 443 442 441 440 439 438 437 436 435 434 433 432 431 430 429 428 427 NWE/NWR0 426 425 NUB/NWR1/NBS1 424 423 422 421 420 419 418 NBS3 SDCKE SDCKE/RAS/CAS/WE/SDA10 RAS CAS WE Output Output Output Output Output Output Output OUTPUT OUTPUT OUTPUT CTRL OUTPUT OUTPUT OUTPUT Output OUTPUT INPUT NCS0/BFCS NCS[1:0]/NOE/NRD/NUB/ NWR1/NBS1/BFCS/SDCS NCS1/SDCS NCS2 NCS[2:3]/NBS3 NCS3 NOE/NRD Output Output Output Output Output Output Output PC9/A25/CFRNW I/O PC8/A24 I/O PC7/A23 I/O JTAG Boundary Scan Register Pin Name A19 A[19:16]/BA0/BA1 A20 A[22:20]/NWE/NWR0 A21 A22 Pin Type Output Output Output Output Output Output Associated BSR Cells OUTPUT CTRL OUTPUT CTRL OUTPUT OUTPUT INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL OUTPUT CTRL OUTPUT OUTPUT CTRL OUTPUT OUTPUT INPUT 68 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 12-3. Bit Number 417 D0 416 415 414 D1 413 412 D2 411 410 D3 409 408 D4 407 406 405 D5 404 403 D6 402 401 D7 400 399 D8 398 397 396 D9 395 394 D10 393 392 D11 391 390 D12 389 388 387 D13 386 385 D14 384 I/O OUTPUT I/O OUTPUT INPUT D[15:12] I/O I/O OUTPUT CTRL INPUT I/O OUTPUT INPUT I/O OUTPUT INPUT I/O OUTPUT INPUT D[11:8] I/O I/O OUTPUT CTRL INPUT I/O OUTPUT INPUT I/O OUTPUT INPUT I/O OUTPUT INPUT D[7:4] I/O I/O OUTPUT CTRL INPUT I/O OUTPUT INPUT I/O OUTPUT INPUT I/O OUTPUT INPUT D[3:0] I/O I/O OUTPUT CTRL INPUT JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT 69 1768G–ATARM–29-Sep-06 Table 12-3. Bit Number 383 JTAG Boundary Scan Register (Continued) Pin Name D15 Pin Type I/O OUTPUT INPUT PC16/D16 I/O OUTPUT CTRL INPUT PC17D17 I/O OUTPUT CTRL INPUT PC18/D18 I/O OUTPUT CTRL INPUT PC19/D19 I/O OUTPUT CTRL INPUT PC20/D20 I/O OUTPUT CTRL INPUT PC21/D21 I/O OUTPUT CTRL INPUT PC22/D22 I/O OUTPUT CTRL INPUT PC23/D23 I/O OUTPUT CTRL INPUT PC24/D24 I/O OUTPUT CTRL INPUT PC25/D25 I/O OUTPUT CTRL INPUT PC26/D26 I/O OUTPUT CTRL Associated BSR Cells INPUT 382 381 380 379 378 377 376 375 374 373 372 371 370 369 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 353 352 351 350 349 70 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 12-3. Bit Number 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 PC15 I/O PC14 I/O PC13/NCS7 I/O PC12/NCS6/CFCE2 I/O PC11/NCS5/CFCE1 I/O PC10/NCS4/CFCS I/O PC31/D31 I/O PC30/D30 I/O PC29/D29 I/O PC28/D28 I/O PC27/D27 I/O JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL 71 1768G–ATARM–29-Sep-06 Table 12-3. Bit Number 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PC0/BCFK I/O OUTPUT CTRL INPUT PC1/BFRDY/SMOE I/O OUTPUT CTRL INPUT PC2/BFAVD I/O OUTPUT CTRL INPUT PC3/BFBAA/SMWE I/O OUTPUT CTRL INPUT PC4/BFOE I/O OUTPUT CTRL INPUT PC5/BFWE I/O OUTPUT CTRL INPUT PC6/NWAIT I/O OUTPUT CTRL INPUT PA0/MISO/PCK3 I/O OUTPUT CTRL INPUT PA1/MOSI/PCK0 I/O OUTPUT CTRL INPUT PA2/SPCK/IRQ4 I/O OUTPUT CTRL INPUT PA3/NPCS0/IRQ5 I/O OUTPUT CTRL 72 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 12-3. Bit Number 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 PA7/ETXCK/EREFCK/PCK2 I/O PA6/NPCS3/RXD3 I/O PD6/DTXD I/O PD5/ETXER I/O PD4/ETXEN I/O PD3/ETX3 I/O PD2/ETX2 I/O PD1/ETX1 I/O PD0/ETX0 I/O PA5/NPCS2/TXD3 I/O PA4/NPCS1/PCK1 I/O JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL 73 1768G–ATARM–29-Sep-06 Table 12-3. Bit Number 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PA8/ETXEN/MCCDB I/O OUTPUT CTRL INPUT PA9/ETX0/MCDB0 I/O OUTPUT CTRL INPUT PA10/ETX1/MCDB1 I/O OUTPUT CTRL INPUT PA11/ECRS/ECRSDV/MCDB2 I/O OUTPUT CTRL INPUT PA12/ERX0/MCDB3 I/O OUTPUT CTRL INPUT PA13/ERX1/TCLK0 I/O OUTPUT CTRL INPUT PA14/ERXER/TCLK1 I/O OUTPUT CTRL INPUT PA15/EMDC/TCLK2 I/O OUTPUT CTRL INPUT PA16/EMDIO/IRQ6 I/O OUTPUT CTRL INPUT PA17/TXD0/TIOA0 I/O OUTPUT CTRL INPUT PA18/RXD0/TIOB0 I/O OUTPUT CTRL 74 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 12-3. Bit Number 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 PA29/MCDA0/TCLK5 I/O PA28/MCCDA/TCLK4 I/O PA27/MCCK/TCLK3 I/O PA26/TWCK/IRQ1 I/O PA25/TWD/IRQ2 I/O PA24/SCK2/PCK1 I/O PA23/TXD2/IRQ3 I/O PA22/RXD2/TIOB2 I/O PA21/RTS0/TIOA2 I/O PA20/CTS0/TIOB1 I/O PA19/SCK0/TIOA1 I/O JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL 75 1768G–ATARM–29-Sep-06 Table 12-3. Bit Number 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PA30/DRXD/CTS2 I/O OUTPUT CTRL INPUT PA31/DTXD/RTS2 I/O OUTPUT CTRL INPUT PB0/TF0/RTS3 I/O OUTPUT CTRL INPUT PB1/TK0/CTS3 I/O OUTPUT CTRL INPUT PB2/TD0/SCK3 I/O OUTPUT CTRL INPUT PB3/RD0/MCDA1 I/O OUTPUT CTRL INPUT PB4/RK0/MCDA2 I/O OUTPUT CTRL INPUT PB5/RF0/MCDA3 I/O OUTPUT CTRL INPUT PB6/TF1/TIOA3 I/O OUTPUT CTRL INPUT PB7/TK1/TIOB3 I/O OUTPUT CTRL INPUT PB8/TD1/TIOA4 I/O OUTPUT CTRL 76 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 12-3. Bit Number 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 PD9/PCK2/TPS0 I/O PD8/PCK1/TCLK I/O PD7/PCK0/TSYNC I/O PB16/RK2/ERX3 I/O PB15/RD2/ERX2 I/O PB14/TD2/ETXER I/O PB13/TK2/ETX3 I/O PB12/TF2/ETX2 I/O PB11/RF1/TIOB5 I/O PB10/RK1/TIOA5 I/O PB9/RD1/TIOB4 I/O JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL 77 1768G–ATARM–29-Sep-06 Table 12-3. Bit Number 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PD10/PCK3/TPS1 I/O OUTPUT CTRL INPUT PD11/TPS2 I/O OUTPUT CTRL INPUT PD12/TPK0 I/O OUTPUT CTRL INPUT PB17/RF2/ERXDV I/O OUTPUT CTRL INPUT PB18/RI1/ECOL I/O OUTPUT CTRL INPUT PB19/DTR1/ERXCK I/O OUTPUT CTRL INPUT PB20/TXD1 I/O OUTPUT CTRL INPUT PB21/RXD1 I/O OUTPUT CTRL INPUT PB22/SCK1 I/O OUTPUT CTRL INPUT PD13/TPK1 I/O OUTPUT CTRL INPUT PD14/TPK2 I/O OUTPUT CTRL 78 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 12-3. Bit Number 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 PD20/NPCS3/TPK8 I/O PD19/NPCS2/TPK7 I/O PD18/NPCS1/TPK6 I/O PD17/TD2/TPK5 I/O PD16/TD1/TPK4 I/O PB27/PCK0 I/O PB26/RTS1 I/O PB25/DSR1/EF100 I/O PB24/CTS1 I/O PB23/DCD1 I/O PD15/TD0/TPK3 I/O JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL INPUT OUTPUT CTRL 79 1768G–ATARM–29-Sep-06 Table 12-3. Bit Number 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PD21/RTS0/TPK9 I/O OUTPUT CTRL INPUT PD22/RTS1/TPK10 I/O OUTPUT CTRL INPUT PD23/RTS2/TPK11 I/O OUTPUT CTRL INPUT PD24/RTS3/TPK12 I/O OUTPUT CTRL INPUT PD25/DTR1/TPK13 I/O OUTPUT CTRL INPUT PD26/TPK14 I/O OUTPUT CTRL INPUT PD27/TPK15 I/O OUTPUT CTRL INPUT PB28/FIQ I/O OUTPUT CTRL INPUT PB29/IRQ0 I/O OUTPUT CTRL A0/NLB/NBS0 A[3:0]/NLB/NWR2/NBS0 /NBS2 A1/NWR2/NBS2 A2 A3 A4 A[7:4] A5 Output Output Output Output Output Output Output Output OUPUT CTRL OUTPUT OUTPUT OUTPUT OUTPUT CTRL OUTPUT 80 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 12-3. Bit Number 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 JTAG Boundary Scan Register (Continued) Pin Name A6 A7 A8 A[11:8] A9 A10 SDA10 A11 A12 A[15:12] A13 A14 A15 A16/BA0 A17/BA1 A18 Pin Type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Associated BSR Cells OUTPUT OUTPUT OUTPUT CTRL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CTRL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT 81 1768G–ATARM–29-Sep-06 12.6.6 AT91RM9200 ID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 • VERSION[31:28]: Product Version Number Set to 0x0 = JTAGSEL is low. Set to 0x1 = JTAGSEL is high. • PART NUMBER[27:14]: Product Part Number Set to 0x5b02. • MANUFACTURER IDENTITY[11:1] Set to 0x01f. • Bit [0]: Required by IEEE Std. 1149.1 Set to 1. The AT91RM9200 ID Code value is 0x15b0203f (JTAGSEL is High). The AT91RM9200 ID Code value is 0x05b0203f (JTAGSEL is Low). 82 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 13. Boot Program 13.1 Overview The Boot Program is capable of downloading an application in an AT91RM9200-based system. It integrates a Bootloader and a boot Uploader to assure correct information download. The Bootloader is activated first. It looks for a sequence of eight valid ARM exception vectors in a DataFlash connected to the SPI, an EEPROM connected to the Two-wire Interface (TWI) or an 8-bit memory device connected to the external bus interface (EBI). All these vectors must be Bbranch or LDR load register instructions except for the sixth instruction. This vector is used to store information, such as the size of the image to download and the type of DataFlash device. If a valid sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, the boot Uploader is started. It initializes the Debug Unit serial port (DBGU) and the USB Device Port. It then waits for any transaction and downloads a piece of code into the internal SRAM via a Device Firmware Upgrade (DFU) protocol for USB and XMODEM protocol for the DBGU. After the end of the download, it branches to the application entry point at the first address of the SRAM. The main features of the Boot Program are: • Default Boot Program stored in ROM-based products • Downloads and runs an application from external storage media into internal SRAM • Downloaded code size depends on embedded SRAM size • Automatic detection of valid application • Bootloader supporting a wide range of non-volatile memories – SPI DataFlash connected on SPI NPCS0 – Two-wire EEPROM – 8-bit parallel memories on NCS0 • Boot Uploader in case no valid program is detected in external NVM and supporting several communication media • Serial communication on a DBGU (XModem protocol) • USB Device Port (DFU Protocol) 83 1768G–ATARM–29-Sep-06 13.2 Flow Diagram The Boot Program implements the algorithm presented in Figure 13-1. Figure 13-1. Boot Program Algorithm Flow Diagram Device Setup SPI DataFlash Boot Yes Download from DataFlash Run Bootloader Timeout 10 ms TWI EEPROM Boot Yes Download from EEPROM Run Timeout 40 ms Parallel Boot Yes Download from 8-bit Device Run DBGU Serial Download OR USB Download DFU* protocol *DFU = Device Firmware Upgrade Run Boot Uploader Run 84 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 13.3 Bootloader The Boot Program is started from address 0x0000_0000 (ARM reset vector) when the on-chip boot mode is selected (BMS high during the reset, only on devices with EBI integrated). The first operation is the search for a valid program in the off-chip non-volatile memories. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a secondlevel Bootloader. To optimize the downloaded application code size, the Boot Program embeds several functions that can be reused by the application. The Boot Program is linked at address 0x0010_0000 but the internal ROM is mapped at both 0x0000_0000 and 0x0010_0000 after reset. All the call to functions is PC relative and does not use absolute addresses. The ARM vectors are present at both addresses, 0x0000_0000 and 0x0010_0000. To access the functions in ROM, a structure containing chip descriptor and function entry points is defined at a fixed address in ROM. If no valid application is detected, the debug serial port or the USB device port must be connected to allow the upload. A specific application provided by Atmel (DFU uploader) loads the application into internal SRAM through the USB. To load the application through the debug serial port, a terminal application (HyperTerminal) running the Xmodem protocol is required. Figure 13-2. Remap Action after Download Completion Internal SRAM 0x0020_0000 REMAP Internal ROM 0x0010_0000 Internal ROM 0x0000_0000 Internal SRAM 0x0000_0000 After reset, the code in internal ROM is mapped at both addresses 0x0000_0000 and 0x0010_0000: 100000 100004 100008 10000c 100010 100014 100018 10001c ea00000b e59ff014 e59ff014 e59ff014 e59ff014 00001234 e51fff20 e51fff20 B LDR LDR LDR LDR LDR LDR LDR 0x2c00ea00000bB0x2c PC,[PC,20]04e59ff014LDRPC,[PC,20] PC,[PC,20]08e59ff014LDRPC,[PC,20] PC,[PC,20]0ce59ff014LDRPC,[PC,20] PC,[PC,20]10e59ff014LDRPC,[PC,20] PC,[PC,20]1400001234LDRPC,[PC,20] PC,[PC,-0xf20]18e51fff20LDRPC,[PC,-0xf20] PC,[PC,-0xf20]1ce51fff20LDRPC,[PC,-0xf20] 85 1768G–ATARM–29-Sep-06 13.3.1 Valid Image Detection The Bootloader software looks for a valid application by analyzing the first 32 bytes corresponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download and the DataFlash parameters. The user must replace this vector with his own vector. Figure 13-3. LDR Opcode 31 1 1 1 28 27 0 1 1 I 24 23 P U 1 W 20 19 0 Rn 16 15 Rd 12 11 0 Figure 13-4. B Opcode 31 1 1 1 28 27 0 1 0 1 24 23 0 Offset (24 bits) 0 Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: – Rn = Rd = PC = 0xF – I==1 – P==1 – U offset added (U==1) or subtracted (U==0) – W==1 13.3.1.1 Example An example of valid vectors: 00 004 08 0c 10 14 18 1c ea00000b e59ff014 e59ff014 e59ff014 e59ff014 00001234 e51fff20 e51fff20 LDR LDR PC, [PC,-0xf20] PC, [PC,-0xf20] B LDR LDR LDR LDR 0x2c PC, [PC,20] PC, [PC,20] PC, [PC,20] PC, [PC,20] Number of DataFlash pages = 213 = 8192 DataFlash page size(000010000100000b) = 1056 For download in the EEPROM or 8-bit external memory, only the size to be downloaded is decoded. 87 1768G–ATARM–29-Sep-06 13.3.3 Bootloader Sequence The Boot Program performs device initialization followed by the download procedure. If unsuccessful, the upload is done via the USB or debug serial port. 13.3.3.1 Device Initialization Initialization follows the steps described below: 1. PLL setup – PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. Table 13-2 defines the crystals supported by the Boot Program. Table 13-2. 3.0 4.433619 6.144 7.864320 12.0 16.0 Crystals Supported by Software Auto-detection (MHz) 3.2768 4.9152 6.4 8.0 12.288 17.734470 3.6864 5.0 6.5536 9.8304 13.56 18.432 3.84 5.24288 7.159090 10.0 14.31818 20.0 4.0 6.0 7.3728 11.05920 14.7456 2. Stacks setup for each ARM mode 3. Main oscillator frequency detection 4. Interrupt controller setup 5. C variables initialization 6. Branch main function 13.3.3.2 Download Procedure The download procedure checks for a valid boot on several devices. The first device checked is a serial DataFlash connected to the NPCS0 of the SPI, followed by the serial EEPROM connected to the TWI and by an 8-bit parallel memory connected on NCS0 of the External Bus Interface. 88 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 13.3.3.3 Serial DataFlash Download The Boot Program supports all Atmel DataFlash devices. Table 13-1 summarizes the parameters to include in the ARM vector 6 for all devices. The DataFlash has a Status Register that determines all the parameters required to access the device. Thus, to be compatible with the future design of the DataFlash, parameters are coded in the ARM vector 6. Figure 13-6. Serial DataFlash Download Start Send status command Is status ok ? No Serial DataFlash Download Read the first 8 instructions (32 bytes). Decode the sixth ARM vector Yes 8 vectors (except vector 6) are LDR or Branch instruction ? No Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End 89 1768G–ATARM–29-Sep-06 13.3.3.4 Serial Two-wire EEPROM Download Generally, serial EEPROMs have no identification code. The bootloader checks for an acknowledgment on the first read. The device address on the two-wire bus must be 0x0. The bootloader supports the devices listed in Table 13-3. Table 13-3. Supported EEPROM Devices Device AT24C16A AT24C164 AT24C32 AT24C64 AT24C128 AT24C256 AT24C512 Size 16 Kbits 16 Kbits 32 Kbits 64 Kbits 128 Kbits 256 Kbits 528 Kbits Organization 16 bytes page write 16 bytes page write 32 bytes page write 32 bytes page write 64 bytes page write 64 bytes page write 128 bytes page write Figure 13-7. Serial Two-Wire EEPROM Download Start Send Read command 8-bits parallel memory Download Device ACK ? No Only for Device with EBI integrated Memory Uploader Only for Device without EBI integrated Read the first 8 instructions (32 bytes). Decode the sixth ARM vector Yes 8 vectors (except vector 6) are LDR or Branch instruction ? No Yes Read the Two-Wire EEPROM into the internal SRAM (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End 90 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 13.3.3.5 8-bit Parallel Flash Download (Applicable to Devices with EBI) Eight-bit parallel Flash download is supported if the product integrates an External Bus Interface (EBI). All 8-bit memory devices supported by the EBI when NCS0 is configured in 8-bit data bus width are supported by the bootloader. Figure 13-8. 8-bit Parallel Flash Download Start Setup memory controller Read the first 8 instructions (32 bytes). Read the size in sixth ARM vector 8 vectors (except vector 6) are LDR or Branch instruction ? No Memory uploader Yes Read the external memory into the internal SRAM (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End 91 1768G–ATARM–29-Sep-06 13.4 Boot Uploader If no valid boot device has been found during the Bootloader sequence, initialization of serial communication devices (DBGU and USB device ports) is performed. – Initialization of the DBGU serial port (115200 bauds, 8, N, 1) and Xmodem protocol start – Initialization of the USB Device Port and DFU protocol start – Download of the application The boot Uploader performs the DFU and Xmodem protocols to upload the application into internal SRAM at address 0x0020_0000. The Boot Program uses a piece of internal SRAM for variables and stacks. To prevent any upload error, the size of the application to upload must be less than the SRAM size minus 3K bytes. After the download, the peripheral registers are reset, the interrupts are disabled and the remap is performed. After the remap, the internal SRAM is at address 0x0000_0000 and the internal ROM at address 0x0010_0000. The instruction setting the PC to 0 is the one just after the remap command. This instruction is fetched in the pipe before doing the remap and executed just after. This fetch cycle executes the downloaded image. 13.4.1 13.4.1.1 External Communication Channels DBGU Serial Port The upload is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The DBGU sends the character ‘C’ (0x43) to start an Xmodem protocol. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product (Refer to the microcontroller datasheet to determine SRAM size embedded in the microcontroller). In all cases, the size of the binary file must be lower than SRAM size because the Xmodem protocol requires some SRAM memory to work. 13.4.1.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: – = 01 hex – = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – = 1’s complement of the blk#. – = 2 bytes CRC16 Figure 13-9 shows a transmission using this protocol. 92 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 13-9. Xmodem Transfer Example Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device 13.4.1.3 USB Device Port A 48 MHz USB clock is necessary to use USB Device port. It has been programmed earlier in the device initialization with PLLB configuration. 13.4.1.4 DFU Protocol The DFU allows upgrade of the firmware of USB devices. The DFU algorithm is a part of the USB specification. For more details, refer to “USB Device Firmware Upgrade Specification, Rev. 1.0”. There are four distinct steps when carrying out a firmware upgrade: 1. Enumeration: The device informs the host of its capabilities. 2. Reconfiguration: The host and the device agree to initiate a firmware upgrade. 3. Transfer: The host transfers the firmware image to the device. Status requests are employed to maintain synchronization between the host and the device. 4. Manifestation: Once the device reports to the host that it has completed the reprogramming operations, the host issues a reset and the device executes the upgraded firmware. Figure 13-10. DFU Protocol Host Prepare for an upgrade Device USB reset DFU mode activated Download this firmware Prepare to exit DFU mode USB reset 93 1768G–ATARM–29-Sep-06 13.5 Hardware and Software Constraints The software limitations of the Boot Program are: • The downloaded code size is less than the SRAM size -4K embedded in the product. • The device address of the EEPROM must be 0 on the TWI bus. • The code is always downloaded from the device address 0x0000_0000 (DataFlash, EEPROM) to the address 0x0000_0000 of the internal SRAM (after remap). • The downloaded code must be position-independent or linked at address 0x0000_0000. The hardware limitations of the Boot Program are: • The DataFlash must be connected to NPCS0 of the SPI. • The 8-bit parallel Flash must be connected to NCS0 of the EBI. • The Boot Program initializes the DBGU pins multiplexed on the PIO common to both the 208lead PQFP and 256-ball BGA packages, in this case meaning PIOA. • Using an external clock source on the XIN pin is not possible as the main oscillator is enabled by the Boot ROM. The SPI and TWI drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between SPI or TWI output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins or to boot on an external 16-bit parallel memory by setting bit BMS. Table 13-4 contains a list of pins that are driven during the Boot Program execution. These pins are driven during the boot sequence for a period of about 6 ms if no correct boot program is found. The download through the TWI takes about 5 sec for 64K bytes due to the TWI bit rate (100 Kbits/s). For the DataFlash driven by SPCK signal at 12 MHz, the time to download 64K bytes is reduced to 66 ms. Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the Boot Program are set to their reset state. Table 13-4. Pin Used MOSI(1) SPCK (1) (1) Pins Driven during Boot Program Execution SPI (DataFlash) O O O X X TWI (EEPROM) X X X I/O O NPCS0 TWD(1) TWCK Note: (1) 1. See Section 10.3 ”Peripheral Multiplexing on PIO Lines” on page 22. 94 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 14. Embedded Software Services 14.1 Overview An embedded software service is an independent software object that drives device resources for frequently implemented tasks. The object-oriented approach of the software provides an easy way to access services to build applications. An AT91 service has several purposes: • It gives software examples dedicated to the AT91 devices. • It can be used on several AT91 device families. • It offers an interface to the software stored in the ROM. The main features of the software services are: • Compliant with ATPCS • Compliant with ANSI/ISO Standard C • Compiled in ARM/Thumb Interworking • ROM Entry Service • Tempo, Xmodem and DataFlash services • CRC and Sine tables 14.2 14.2.1 Service Definition Service Structure Structure Definition A service structure is defined in C header files. This structure is composed of data members and pointers to functions (methods) and is similar to a class definition. There is no protection of data access or methods access. However, some functions can be used by the customer application or other services and so be considered as public methods. Similarly, other functions are not invoked by them. They can be considered as private methods. This is also valid for data. 14.2.1.1 14.2.1.2 Methods In the service structure, pointers to functions are supposed to be initialized by default to the standard functions. Only the default standard functions reside in ROM. Default methods can be overloaded by custom application methods. Methods do not declare any static variables nor invoke global variables. All methods are invoked with a pointer to the service structure. A method can access and update service data without restrictions. Similarly, there is no polling in the methods. In fact, there is a method to start the functionality (a read to give an example), a method to get the status (is the read achieved?), and a callback, initialized by the start method. Thus, using service, the client application carries out a synchronous read by starting the read and polling the status, or an asynchronous read specifying a callback when starting the read operation. 95 1768G–ATARM–29-Sep-06 14.2.1.3 Service Entry Point Each AT91 service, except for the ROM Entry Service (see 14.3.2 ”ROM Entry Service” on page 99), defines a function named AT91F_Open_. It is the only entry point defined for a service. Even if the functions AT91F_Open_ may be compared with object constructors, they do not act as constructors in that they initiate the service structure but they do not allocate it. Thus the customer application must allocate it. Example // Allocation of the service structure AT91S_Pipe pipe; // Opening of the service AT91PS_Pipe pPipe = AT91F_OpenPipe(&pipe, …); Method pointers in the service structure are initialized to the default methods defined in the AT91 service. Other fields in the service structure are initialized to default values or with the arguments of the function AT91F_Open_. In summary, an application must know what the service structure is and where the function AT91F_Open_ is. The default function AT91F_Open_ may be redefined by the application or comprised in an application-defined function. 14.2.2 14.2.2.1 Using a Service Opening a Service The entry point to a service is established by initializing the service structure. An open function is associated with each service structure, except for the ROM Entry Service (see 14.3.2 ”ROM Entry Service” on page 99). Thus, only the functions AT91F_Open_ are visible from the user side. Access to the service methods is made via function pointers in the service structure. The function AT91F_Open_ has at least one argument: a pointer to the service structure that must be allocated elsewhere. It returns a pointer to the base service structure or a pointer to this service structure. The function AT91F_Open_ initializes all data members and method pointers. All function pointers in the service structure are set to the service’s functions. The advantage of this method is to offer a single entry point for a service. The methods of a service are initialized by the open function and each member can be overloaded. 14.2.2.2 Overloaqding a Method Default methods are defined for all services provided in ROM. These methods may not be adapted to a project requirement. It is possible to overload default methods by methods defined in the project. A method is a pointer to a function. This pointer is initialized by the function AT91F_Open_ . To overload one or several methods in a service, the function pointer must be updated to the new method. 96 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 It is possible to overload just one method of a service or all the methods of a service. In this latter case, the functionality of the service is user-defined, but still works on the same data structure. Note: Calling the default function AT91F_Open_ ensures that all methods and data are initialized. This can be done by writing a new function My_OpenService(). This new Open function must call the library-defined function AT91F_Open_, and then update one or several function pointers: Table 14-1. Overloading a Method with the Overloading of the Open Service Function Overloading AT91F_ChildMethod by My_ChildMethod // My_ChildMethod will replace AT91F_ChildMethod char My_ChildMethod () { } // Overloading Open Service Method // Defined in obj_service.c (in ROM) char AT91F_MainMethod () { } char AT91F_ChildMethod () { } } // Init the service with default methods AT91PS_Service AT91F_OpenService( AT91PS_Service pService) { pService->data = 0; pService->MainMethod =AT91F_MainMethod; pService->ChildMethod=AT91F_ChildMethod; return pService; } // Opening of the service AT91PS_Service pService = My_OpenService(&service); // Allocation of the service structure AT91S_Service service; AT91PS_Service My_OpenService( AT91PS_Service pService) { AT91F_OpenService(pService); // Overloading ChildMethod default value pService->ChildMethod= My_ChildMethod; return pService; Default service behavior in ROM // Defined in embedded_services.h typedef struct _AT91S_Service { char data; char (*MainMethod) (); char (*ChildMethod) (); } AT91S_Service, * AT91PS_Service; 97 1768G–ATARM–29-Sep-06 This also can be done directly by overloading the method after the use of AT91F_Open_ method: Table 14-2. Overloading a Method without the Overloading of the Open Service Function. Overloading AT91F_ChildMethod by My_ChildMethod // My_ChildMethod will replace AT91F_ChildMethod char My_ChildMethod () { } // Allocation of the service structure // Defined in obj_service.c (in ROM) char AT91F_MainMethod () { } char AT91F_ChildMethod () { } // Init the service with default methods AT91PS_Service AT91F_OpenService( AT91PS_Service pService) { pService->data = 0; pService->MainMethod =AT91F_MainMethod; pService->ChildMethod=AT91F_ChildMethod; return pService; } // Overloading ChildMethod default value pService->ChildMethod= My_ChildMethod; // Opening of the service AT91PS_Service pService = AT91F_OpenService(&service); AT91S_Service service; Default service behavior in ROM // Defined in embedded_services.h typedef struct _AT91S_Service { char data; char (*MainMethod) (); char (*ChildMethod) (); } AT91S_Service, * AT91PS_Service; 98 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 14.3 14.3.1 Embedded Software Services Definition Several AT91 products embed ROM. In most cases, the ROM integrates a bootloader and several services that may speed up the application and reduce the application code size. When software is fixed in the ROM, the address of each object (function, constant, table, etc.) must be related to a customer application. This is done by providing an address table to the linker. For each version of ROM, a new address table must be provided and all client applications must be recompiled. The Embedded Software Services offer another solution to access objects stored in ROM. For each embedded service, the customer application requires only the address of the Service Entry Point (see 14.2.1.3 ”Service Entry Point” on page 96). Even if these services have only one entry point (AT91F_Open_ function), they must be specified to the linker. The Embedded Software Services solve this problem by providing a dedicated service: the ROM Entry Service. The goal of this product-dedicated service is to provide just one address to access all ROM functionalities. 14.3.2 ROM Entry Service The ROM Entry Service of a product is a structure named AT91S_RomBoot. Some members of this structure point to the open functions of all services stored in ROM (function AT91F_Open_) but also the CRC and Sine Arrays. Thus, only the address of the AT91S_RomBoot has to be published. Table 14-3. Initialization of the ROM Entry Service and Use with an Open Service Method ROM Memory Space AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtlTempo, void const *pTempoTimer ) { ... } AT91S_TempoStatus AT91F_CtlTempoCreate ( AT91PS_CtlTempo pCtrl, AT91PS_SvcTempo pTempo) { ... } Application Memory Space // Init the ROM Entry Service AT91S_RomBoot const *pAT91; pAT91 = AT91C_ROM_BOOT_ADDRESS; // Allocation of the service structure AT91S_CtlTempo tempo; // Call the Service Open method pAT91->OpenCtlTempo(&tempo, ...); // Use of tempo methods tempo.CtlTempoCreate(&tempo, ...); The application obtains the address of the ROM Entry Service and initializes an instance of the AT91S_RomBoot structure. To obtain the Open Service Method of another service stored in ROM, the application uses the appropriate member of the AT91S_RomBoot structure. The address of the AT91S_RomBoot can be found at the beginning of the ROM, after the exception vectors. 99 1768G–ATARM–29-Sep-06 14.3.3 14.3.3.1 Tempo Service Presentation The Tempo Service allows a single hardware system timer to support several software timers running concurrently. This works as an object notifier. There are two objects defined to control the Tempo Service : A T91S_CtlTempo a nd AT91S_SvcTempo. The application declares one instance of AT91S_CtlTempo associated with the hardware system timer. Additionally, it controls a list of instances of AT91S_SvcTempo. Each time the application requires another timer, it asks the AT91S_CtlTempo to create a new instance of A T91S_SvcTempo , then the application initializes all the settings of AT91S_SvcTempo. 14.3.3.2 Tempo Service Description Table 14-4. Tempo Service Methods Description Member of AT91S_RomBoot structure. Corresponds to the Open Service Method for the Tempo Service. Input Parameters: Pointer on a Control Tempo Object. Pointer on a System Timer Descriptor Structure. Output Parameters: Returns 0 if OpenCtrlTempo successful. Returns 1 if not. Associated Function Pointers & Methods Used by Default // Typical Use: pAT91->OpenCtlTempo(...); // Default Method: AT91S_TempoStatus AT91F_OpenCtlTempo( AT91PS_CtlTempo pCtlTempo, void const *pTempoTimer) // Typical Use: AT91S_CtlTempo ctlTempo; ctlTempo.CtlTempoStart(...); // Default Method: AT91S_TempoStatus AT91F_STStart(void * pTimer) Member of AT91S_CtlTempo structure. Start of the Hardware System Timer associated. Input Parameters: Pointer on a Void Parameter corresponding to a System Timer Descriptor Structure. Output Parameters: Returns 2. // Typical Use: AT91S_CtlTempo ctlTempo; ctlTempo.CtlTempoIsStart(...); // Default Method: AT91S_TempoStatus AT91F_STIsStart( AT91PS_CtlTempo pCtrl) Member of AT91S_CtlTempo structure. Input Parameters: Pointer on a Control Tempo Object. Output Parameters: Returns the Status Register of the System Timer. 100 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 14-4. Tempo Service Methods (Continued) Description Member of AT91S_CtlTempo structure. Insert a software timer in the AT91S_SvcTempo’s list. Input Parameters: Pointer on a Control Tempo Object. Pointer on a Service Tempo Object to insert. Output Parameters: Returns 0 if the software tempo was created. Returns 1 if not. Member of AT91S_CtlTempo structure. Remove a software timer in the list. Input Parameters: Pointer on a Control Tempo Object. Pointer on a Service Tempo Object to remove. Output Parameters: Returns 0 if the tempo was created. Returns 1 if not. Member of AT91S_CtlTempo structure. Refresh all the software timers in the list. Update their timeout and check if callbacks have to be launched. So, for example, this function has to be used when the hardware timer starts a new periodic interrupt if period interval timer is used. Input Parameters: Pointer on a Control Tempo Object. Output Parameters: Returns 1. Member of AT91S_SvcTempo structure. Start a software timer. Input Parameters: Pointer on a Service Tempo Object. Timeout to apply. Number of times to reload the tempo after timeout completed for periodic execution. Callback on a method to launch once the timeout completed. Allows to have a hook on the current service. Output Parameters: Returns 1. Member of AT91S_SvcTempo structure. Force to stop a software timer. Input Parameters: Pointer on a Service Tempo Object. Output Parameters: Returns 1. Associated Function Pointers & Methods Used by Default // Typical Use: AT91S_CtlTempo ctlTempo; ctlTempo.CtlTempoCreate(...); // Default Method: AT91S_TempoStatus AT91F_CtlTempoCreate ( AT91PS_CtlTempo pCtrl, AT91PS_SvcTempo pTempo) // Typical Use: AT91S_CtlTempo ctlTempo; ctlTempo.CtlTempoRemove(...); // Default Method: AT91S_TempoStatus AT91F_CtlTempoRemove (AT91PS_CtlTempo pCtrl, AT91PS_SvcTempo pTempo) // Typical Use: AT91S_CtlTempo ctlTempo; ctlTempo.CtlTempoTick(...); // Default Method: AT91S_TempoStatus AT91F_CtlTempoTick (AT91PS_CtlTempo pCtrl) // Typical Use: AT91S_SvcTempo svcTempo; svcTempo.Start(...); // Default Method: AT91S_TempoStatus AT91F_SvcTempoStart ( AT91PS_SvcTempo pSvc, unsigned int timeout, unsigned int reload, void (*callback) (AT91S_TempoStatus, void *), void *pData) // Typical Use: AT91S_SvcTempo svcTempo; svcTempo.Stop(...); // Default Method: AT91S_TempoStatus AT91F_SvcTempoStop ( Note: AT91PS_SvcTempo pSvc) AT91S_TempoStatus corresponds to an unsigned int. 101 1768G–ATARM–29-Sep-06 14.3.3.3 Using the Service The first step is to find the address of the open service method AT91F_OpenCtlTempo using the ROM Entry Service. Allocate one instance of AT91S_CtlTempo and AT91S_SvcTempo in the application memory space: // Allocate the service and the control tempo AT91S_CtlTempo ctlTempo; AT91S_SvcTempo svcTempo1; Initialize the AT91S_CtlTempo instance by calling the AT91F_OpenCtlTempo function: // Initialize service pAT91->OpenCtlTempo(&ctlTempo, (void *) &(pAT91->SYSTIMER_DESC)); At this stage, the application can use the AT91S_CtlTempo service members. If the application wants to overload an object member, it can be done now. For example, if AT91F_CtlTempoCreate(&ctlTempo, &svcTempo1) method is to be replaced by the application defined as my_CtlTempoCreate(...), the procedure is as follows: // Overload AT91F_CtlTempoCreate ctlTempo.CtlTempoCreate = my_CtlTempoCreate; In most cases, initialize the AT91S_SvcTempo object by calling the AT91F_CtlTempoCreate method of the AT91S_CtlTempo service: // Init the svcTempo1, link it to the AT91S_CtlTempo object ctlTempo.CtlTempoCreate(&ctlTempo, &svcTempo1); Start the timeout by calling Start method of the svcTempo1 object. Depending on the function parameters, either a callback is started at the end of the countdown or the status of the timeout is checked by reading the TickTempo member of the svcTempo1 object. // Start the timeout svcTempo1.Start(&svcTempo1,100,0,NULL,NULL); // Wait for the timeout of 100 (unity depends on the timer programmation) // No repetition and no callback. while (svcTempo1.TickTempo); When the application needs another software timer to control a timeout, it: • Allocates one instance of AT91S_SvcTempo in the application memory space // Allocate the service AT91S_SvcTempo svcTempo2; • Initializes the AT91S_SvcTempo object calling the AT91F_CtlTempoCreate method of the AT91S_CtlTempo service: // Init the svcTempo2, link it to the AT91S_CtlTempo object ctlTempo.CtlTempoCreate(&ctlTempo, &svcTempo2); 102 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 14.3.4 14.3.4.1 Xmodem Service Presentation The Xmodem service is an application of the communication pipe abstract layer. This layer is media-independent (USART, USB, etc.) and gives entry points to carry out reads and writes on an abstract media, the pipe. Communication Pipe Service The pipe communication structure is a virtual structure that contains all the functions required to read and write a buffer, regardless of the communication media and the memory management. The pipe structure defines: • a pointer to a communication service structure AT91PS_SvcComm • a pointer to a buffer manager structure AT91PS_Buffer • pointers on read and write functions • pointers to callback functions associated to the read and write functions The following structure defines the pipe object: typedef struct _AT91S_Pipe { // A pipe is linked with a peripheral and a buffer AT91PS_SvcComm pSvcComm; AT91PS_Buffer pBuffer; // Callback functions with their arguments void (*WriteCallback) (AT91S_PipeStatus, void *); void (*ReadCallback) (AT91S_PipeStatus, void *); void *pPrivateReadData; void *pPrivateWriteData; // Pipe methods AT91S_PipeStatus (*Write) ( struct _AT91S_Pipe char const * unsigned int void void struct _AT91S_Pipe char unsigned int void void *pPipe, pData, size, (*callback) (AT91S_PipeStatus, void *), *privateData); *pPipe, *pData, size, (*callback) (AT91S_PipeStatus, void *), *privateData); *pPipe); AT91S_PipeStatus (*Read) ( AT91S_PipeStatus (*AbortWrite) (struct _AT91S_Pipe AT91S_PipeStatus (*AbortRead) (struct _AT91S_Pipe *pPipe); AT91S_PipeStatus (*Reset) (struct _AT91S_Pipe *pPipe); char (*IsWritten) (struct _AT91S_Pipe *pPipe,char const *pVoid); 103 1768G–ATARM–29-Sep-06 char (*IsReceived) (struct _AT91S_Pipe *pPipe,char const *pVoid); } AT91S_Pipe, *AT91PS_Pipe; The Xmodem protocol implementation demonstrates how to use the communication pipe. Description of the Buffer Structure The AT91PS_Buffer is a pointer to the AT91S_Buffer structure manages the buffers. This structure embeds the following functions: • pointers to functions that manage the read buffer • pointers to functions that manage the write buffer All the functions can be overloaded by the application to adapt buffer management. A simple implementation of buffer management for the Xmodem Service is provided in the boot ROM source code. typedef struct _AT91S_Buffer { struct _AT91S_Pipe *pPipe; void *pChild; // Functions invoked by the pipe AT91S_BufferStatus (*SetRdBuffer) char *pBuffer, unsigned int Size); (struct _AT91S_Buffer *pSBuffer, AT91S_BufferStatus (*SetWrBuffer) (struct _AT91S_Buffer *pSBuffer, char const *pBuffer, unsigned int Size); AT91S_BufferStatus (*RstRdBuffer) AT91S_BufferStatus (*RstWrBuffer) char (*MsgWritten) *pBuffer); char (*MsgRead) *pBuffer); (struct _AT91S_Buffer *pSBuffer); (struct _AT91S_Buffer *pSBuffer); (struct _AT91S_Buffer *pSBuffer, char const (struct _AT91S_Buffer *pSBuffer, char const // Functions invoked by the peripheral AT91S_BufferStatus (*GetWrBuffer) (struct _AT91S_Buffer *pSBuffer, char const **pData, unsigned int *pSize); AT91S_BufferStatus (*GetRdBuffer) char **pData, unsigned int *pSize); AT91S_BufferStatus (*EmptyWrBuffer) unsigned int size); AT91S_BufferStatus (*FillRdBuffer) unsigned int size); char (*IsWrEmpty) char (*IsRdFull) (struct _AT91S_Buffer *pSBuffer, (struct _AT91S_Buffer *pSBuffer, (struct _AT91S_Buffer *pSBuffer, (struct _AT91S_Buffer *pSBuffer); (struct _AT91S_Buffer *pSBuffer); } AT91S_Buffer, *AT91PS_Buffer; Description of the SvcComm Structure The SvcComm structure provides the interface between low-level functions and the pipe object. It contains pointers of functions initialized to the lower level functions (e.g. SvcXmodem). The Xmodem Service implementation gives an example of SvcComm use. 104 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 typedef struct _AT91S_Service { // Methods: AT91S_SvcCommStatus (*Reset) (struct _AT91S_Service *pService); AT91S_SvcCommStatus (*StartTx)(struct _AT91S_Service *pService); AT91S_SvcCommStatus (*StartRx)(struct _AT91S_Service *pService); AT91S_SvcCommStatus (*StopTx) (struct _AT91S_Service *pService); AT91S_SvcCommStatus (*StopRx) (struct _AT91S_Service *pService); char char // Data: struct _AT91S_Buffer *pBuffer; // Link to a buffer object void *pChild; } AT91S_SvcComm, *AT91PS_SvcComm; (*TxReady)(struct _AT91S_Service *pService); (*RxReady)(struct _AT91S_Service *pService); Description of the SvcXmodem Structure The SvcXmodem service is a reusable implementation of the Xmodem protocol. It supports only the 128-byte packet format and provides read and write functions. The SvcXmodem structure defines: • a pointer to a handler initialized to readHandler or writeHandler • a pointer to a function that processes the xmodem packet crc • a pointer to a function that checks the packet header • a pointer to a function that checks data With this structure, the Xmodem protocol can be used with all media (USART, USB, etc.). Only private methods may be overloaded to adapt the Xmodem protocol to a new media. The default implementation of the Xmodem uses a USART to send and receive packets. Read and write functions implement Peripheral DMA Controller facilities to reduce interrupt overhead. It assumes the USART is initialized, the memory buffer allocated and the interrupts programmed. A periodic timer is required by the service to manage timeouts and the periodic transmission of the character “C” (Refer to Xmodem protocol). This feature is provided by the Tempo Service. The following structure defines the Xmodem Service: typedef struct _AT91PS_SvcXmodem { // Public Methods: AT91S_SvcCommStatus (*Handler) (struct _AT91PS_SvcXmodem *, unsigned int); AT91S_SvcCommStatus (*StartTx) (struct _AT91PS_SvcXmodem *, unsigned int); AT91S_SvcCommStatus (*StopTx) // Private Methods: AT91S_SvcCommStatus (*ReadHandler) int csr); (struct _AT91PS_SvcXmodem *, unsigned (struct _AT91PS_SvcXmodem *, unsigned int); AT91S_SvcCommStatus (*WriteHandler) (struct _AT91PS_SvcXmodem *, unsigned int csr); unsigned short (*GetCrc) (char *ptr, unsigned int count); 105 1768G–ATARM–29-Sep-06 char *packet); char AT91S_SvcComm (*CheckHeader) (*CheckData) parent; (unsigned char currentPacket, char (struct _AT91PS_SvcXmodem *); // Base class AT91PS_USART pUsart; AT91S_SvcTempo tempo; // Link to a AT91S_Tempo object char unsigned int char char char char *pData; dataSize; // = XMODEM_DATA_STX or XMODEM_DATA_SOH // Current packet packetDesc[AT91C_XMODEM_PACKET_SIZE]; packetStatus; isPacketDesc; eot; // end of transmition unsigned char packetId; } AT91S_SvcXmodem, *AT91PS_SvcXmodem 14.3.4.2 Table 14-5. Xmodem Service Description Xmodem Service Methods Description Member of AT91S_RomBoot structure. Corresponds to the Open Service Method for the Xmodem Service. Input Parameters: Pointer on SvcXmodem structure. Pointer on a USART structure. Pointer on a CtlTempo structure. Output Parameters: Returns the Xmodem Service Pointer Structure. Associated Function Pointers & Methods Used by Default // Typical Use: pAT91->OpenSvcXmodem(...); // Default Method: AT91PS_SvcComm AT91F_OpenSvcXmodem( AT91PS_SvcXmodem pSvcXmodem, AT91PS_USART pUsart, AT91PS_CtlTempo pCtlTempo) // Typical Use: AT91S_SvcXmodem svcXmodem; svcXmodem.Handler(...); // Default read handler: AT91S_SvcCommStatus AT91F_SvcXmodemReadHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr) // Default write handler: AT91S_SvcCommStatus AT91F_SvcXmodemWriteHandler(AT91PS_SvcXmodem pSvcXmodem, unsigned int csr) Member of AT91S_SvcXmodem structure. interrupt handler for xmodem read or write functionnalities Input Parameters: Pointer on a Xmodem Service Structure. csr: usart channel status register . Output Parameters: Status for xmodem read or write. 106 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 14.3.4.3 Using the Service The following steps show how to initialize and use the Xmodem Service in an application: Variables definitions: AT91S_RomBoot const *pAT91; // struct containing Openservice functions AT91S_SBuffer AT91S_Pipe AT91S_CtlTempo sXmBuffer; // Xmodem Buffer allocation xmodemPipe;// xmodem pipe communication struct ctlTempo; // Tempo struct AT91S_SvcXmodem svcXmodem; // Xmodem service structure allocation AT91PS_Buffer pXmBuffer; // Pointer on a buffer structure AT91PS_SvcComm pSvcXmodem; // Pointer on a Media Structure Initialisations // Call Open methods: pAT91 = AT91C_ROM_BOOT_ADDRESS; // OpenCtlTempo on the system timer pAT91->OpenCtlTempo(&ctlTempo, (void *) &(pAT91->SYSTIMER_DESC)); ctlTempo.CtlTempoStart((void *) &(pAT91->SYSTIMER_DESC)); // Xmodem buffer initialisation pXmBuffer = pAT91->OpenSBuffer(&sXmBuffer); pSvcXmodem = pAT91->OpenSvcXmodem(&svcXmodem, AT91C_BASE_DBGU, &ctlTempo); // Open communication pipe on the xmodem service pAT91->OpenPipe(&xmodemPipe, pSvcXmodem, pXmBuffer); // Init the DBGU peripheral // Open PIO for DBGU AT91F_DBGU_CfgPIO(); // Configure DBGU AT91F_US_Configure ( (AT91PS_USART) AT91C_BASE_DBGU, MCK, BAUDRATE , 0); // Enable Transmitter AT91F_US_EnableTx((AT91PS_USART) AT91C_BASE_DBGU); // Enable Receiver AT91F_US_EnableRx((AT91PS_USART) AT91C_BASE_DBGU); // Initialize the Interrupt for System Timer and DBGU (shared interrupt) // Initialize the Interrupt Source 1 for SysTimer and DBGU AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, AT91F_ASM_ST_DBGU_Handler); // Enable SysTimer and DBGU interrupt AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS); // Master Clock // mode Register to be programmed // baudrate to be programmed // timeguard to be programmed AT91C_US_ASYNC_MODE, // DBGU base address 107 1768G–ATARM–29-Sep-06 xmodemPipe.Read(&xmodemPipe, (char *) BASE_LOAD_ADDRESS, MEMORY_SIZE, XmodemProtocol, (void *) BASE_LOAD_ADDRESS); 14.3.5 14.3.5.1 DataFlash Service Presentation The DataFlash Service allows the Serial Peripheral Interface (SPI) to support several Serial DataFlash and DataFlash Cards for reading, programming and erasing operations. This service is based on SPI interrupts that are managed by a specific handler. It also uses the corresponding PDC registers. For more information on the commands available in the DataFlash Service, refer to the relevant DataFlash documentation. 14.3.5.2 DataFlash Service Description Table 14-6. DataFlash Service Methods Description Member of AT91S_RomBoot structure. Corresponds to the Open Service Method for the DataFlash Service. Input Parameters: Pointer on a PMC Register Description Structure. Pointer on a DataFlash Service Structure. Output Parameters: Returns the DataFlash Service Pointer Structure. Member of AT91S_SvcDataFlash structure. SPI Fixed Peripheral C interrupt handler. Input Parameters: Pointer on a DataFlash Service Structure. Status: corresponds to the interruptions detected and validated on SPI (SPI Status Register masked by SPI Mask Register). Has to be put in the Interrupt handler for SPI. Output Parameters: None. Member of AT91S_SvcDataFlash structure. Read the status register of the DataFlash. Input Parameters: Pointer on a DataFlash Descriptor Structure (member of the service structure). Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Associated Function Pointers & Methods Used by Default // Typical Use: pAT91->OpenSvcDataFlash(...); // Default Method: AT91PS_SvcDataFlash AT91F_OpenSvcDataFlash ( const AT91PS_PMC pApmc, AT91PS_SvcDataFlash pSvcDataFlash) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.Handler(...); // Default Method: void AT91F_DataFlashHandler( AT91PS_SvcDataFlash pSvcDataFlash, unsigned int status) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.Status(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_DataFlashGetStatus(AT91PS_DataflashDes c pDesc) 108 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 14-6. DataFlash Service Methods (Continued) Description Member of AT91S_SvcDataFlash structure Allows to reset PDC & Interrupts. Input Parameters: Pointer on a DataFlash Descriptor Structure (member of the service structure). Output Parameters: None. Associated Function Pointers & Methods Used by Default // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.AbortCommand(...); // Default Method: void AT91F_DataFlashAbortCommand(AT91PS_Dataflash Desc pDesc) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.PageRead(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_DataFlashPageRead ( AT91PS_SvcDataFlash pSvcDataFlash, unsigned int src, unsigned char *dataBuffer, int sizeToRead ) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.ContinuousRead(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_DataFlashContinuousRead ( AT91PS_SvcDataFlash pSvcDataFlash, int src, unsigned char *dataBuffer, int sizeToRead ) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.ReadBuffer(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_DataFlashReadBuffer ( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned int bufferAddress, unsigned char *dataBuffer, int sizeToRead ) Member of AT91S_SvcDataFlash structure. Continuous Stream Read. Input Parameters: Pointer on DataFlash Service Structure. DataFlash address. Data buffer destination pointer. Number of bytes to read. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Member of AT91S_SvcDataFlash structure. Read the Internal DataFlash SRAM Buffer 1 or 2. Input Parameters: Pointer on DataFlash Service Structure. Choose Internal DataFlash Buffer 1 or 2 command. DataFlash address. Data buffer destination pointer. Number of bytes to read. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Returns 4 if DataFlash Bad Command. Returns 5 if DataFlash Bad Address. Member of AT91S_SvcDataFlash structure Read a Page in DataFlash. Input Parameters: Pointer on DataFlash Service Structure. DataFlash address. Data buffer destination pointer. Number of bytes to read. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash Ready. 109 1768G–ATARM–29-Sep-06 Table 14-6. DataFlash Service Methods (Continued) Description Member of AT91S_SvcDataFlash structure Read a Page in the Internal SRAM Buffer 1 or 2. Input Parameters: Pointer on DataFlash Service Structure. Choose Internal DataFlash Buffer 1 or 2 command. Page to read. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Returns 4 if DataFlash Bad Command. Member of AT91S_SvcDataFlash structure Page Program through Internal SRAM Buffer 1 or 2. Input Parameters: Pointer on DataFlash Service Structure. Choose Internal DataFlash Buffer 1 or 2 command. Source buffer. DataFlash destination address. Number of bytes to write. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Returns 4 if DataFlash Bad Command. Member of AT91S_SvcDataFlash structure. Write data to the Internal SRAM buffer 1 or 2. Input Parameters: Pointer on DataFlash Service Structure. Choose Internal DataFlash Buffer 1 or 2 command. Pointer on data buffer to write. Address in the internal buffer. Number of bytes to write. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Returns 4 if DataFlash Bad Command. Returns 5 if DataFlash Bad Address. Associated Function Pointers & Methods Used by Default // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.MainMemoryToBufferTransfert(... ); // Default Method: AT91S_SvcDataFlashStatus AT91F_MainMemoryToBufferTransfert( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned int page) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.PagePgmBuf(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_DataFlashPagePgmBuf( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned char *src, unsigned int dest, unsigned int SizeToWrite) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.WriteBuffer(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_DataFlashWriteBuffer ( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned char *dataBuffer, unsigned int bufferAddress, int SizeToWrite ) 110 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 14-6. DataFlash Service Methods (Continued) Description Member of AT91S_SvcDataFlash structure. Write Internal Buffer to the DataFlash Main Memory. Input Parameters: Pointer on DataFlash Service Structure. Choose Internal DataFlash Buffer 1 or 2 command. Main memory address on DataFlash. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash is Ready. Member of AT91S_SvcDataFlash structure. Erase a page in DataFlash. Input Parameters: Pointer on a Service DataFlash Object. Page to erase. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash Ready. Member of AT91S_SvcDataFlash structure. Erase a block of 8 pages. Input Parameters: Pointer on a Service DataFlash Object. Block to erase. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash Ready. Member of AT91S_SvcDataFlash structure. Compare the contents of a Page and one of the Internal SRAM buffer. Input Parameters: Pointer on a Service DataFlash Object. Internal SRAM DataFlash Buffer to compare command. Page to compare. Output Parameters: Returns 0 if DataFlash is Busy. Returns 1 if DataFlash Ready. Returns 4 if DataFlash Bad Command. Associated Function Pointers & Methods Used by Default // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.WriteBufferToMain(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_WriteBufferToMain ( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned int dest ) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.PageErase(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_PageErase ( AT91PS_SvcDataFlash pSvcDataFlash, unsigned int PageNumber) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.BlockErase(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_BlockErase ( AT91PS_SvcDataFlash pSvcDataFlash, unsigned int BlockNumber ) // Typical Use: AT91S_SvcDataFlash svcDataFlash; svcDataFlash.MainMemoryToBufferCompare(...); // Default Method: AT91S_SvcDataFlashStatus AT91F_MainMemoryToBufferCompare( AT91PS_SvcDataFlash pSvcDataFlash, unsigned char BufferCommand, unsigned int page) Note: AT91S_SvcDataFlashStatus corresponds to an unsigned int. 111 1768G–ATARM–29-Sep-06 14.3.5.3 Using the Service The first step is to find the address of the open service method AT91F_OpenSvcDataFlash using the ROM Entry Service. 1. Allocate one instance of AT91S_SvcDataFlash and AT91S_Dataflash in the application memory space: // Allocate the service and a device structure. AT91S_SvcDataFlash svcDataFlash; AT91S_Dataflash Device; // member of AT91S_SvcDataFlash service Then initialize the A T91S_SvcDataFlash i nstance by calling the A T91F_OpenSvcDataFlash function: // Initialize service pAT91->OpenSvcDataFlash (AT91C_BASE_PMC, &svcDataFlash); 2. Initialize the SPI Interrupt: // Initialize the SPI Interrupt at91_irq_open ( AT91C_BASE_AIC,AT91C_ID_SPI,3, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ,AT91F_spi_asm_handler); 3. Configure the DataFlash structure with its correct features and link it to the device structure in the AT91S_SvcDataFlash service structure: // Example with an ATMEL AT45DB321B DataFlash Device.pages_number = 8192; Device.pages_size = 528; Device.page_offset = 10; Device.byte_mask = 0x300; // Link to the service structure svcDataFlash.pDevice = &Device; 4. Now the different methods can be used. Following is an example of a Page Read of 528 bytes on page 50: // Result of the read operation in RxBufferDataFlash unsigned char RxBufferDataFlash[528]; svcDataFlash.PageRead(&svcDataFlash, (50*528),RxBufferDataFlash,528); 112 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 14.3.6 14.3.6.1 CRC Service Presentation This “service” differs from the preceding ones in that it is structured differently: it is composed of an array and some methods directly accessible via the AT91S_RomBoot structure. 14.3.6.2 CRC Service Description Table 14-7. CRC Service Description Description This function provides a table driven 32bit CRC generation for byte data. This CRC is known as the CCITT CRC32. Input Parameters: Pointer on the data buffer. The size of this buffer. A pointer on the result of the CRC. Output Parameters: None. This function provides a table driven 16bit CRC generation for byte data. This CRC is calculated with the POLYNOME 0x8005 Input Parameters: Pointer on the data buffer. The size of this buffer. A pointer on the result of the CRC. Output Parameters: None. This function provides a table driven 16bit CRC generation for byte data. This CRC is known as the HDLC CRC. Input Parameters: Pointer on the data buffer. The size of this buffer. A pointer on the result of the CRC. Output Parameters: None. This function provides a table driven 16bit CRC generation for byte data. This CRC is known as the CCITT CRC16 (POLYNOME = 0x1021). Input Parameters: Pointer on the data buffer. The size of this buffer. A pointer on the result of the CRC. Output Parameters: None. Methods and Array Available // Typical Use: pAT91->CRC32(...); // Default Method: void CalculateCrc32( const unsigned char *address, unsigned int size, unsigned int *crc) // Typical Use: pAT91->CRC16(...); // Default Method: void CalculateCrc16( const unsigned char *address, unsigned int size, unsigned short *crc) // Typical Use: pAT91->CRCHDLC(...); // Default Method: void CalculateCrcHdlc( const unsigned char *address, unsigned int size, unsigned short *crc) // Typical Use: pAT91->CRCCCITT(...); // Default Method: void CalculateCrc16ccitt( const unsigned char *address, unsigned int size, unsigned short *crc) 113 1768G–ATARM–29-Sep-06 Table 14-7. CRC Service Description (Continued) Description Methods and Array Available // Typical Use: char reverse_byte; reverse_byte = pAT91>Bit_Reverse_Array[...]; // Array Embedded: const unsigned char bit_rev[256] Bit Reverse Array: array which allows to reverse one octet. Frequently used in mathematical algorithms. Used for example in the CRC16 calculation. 14.3.6.3 Using the Service Compute the CRC16 CCITT of a 256-byte buffer and save it in the crc16 variable: // Compute CRC16 CCITT unsigned char BufferToCompute[256]; short crc16; ... (BufferToCompute Treatment) pAT91->CRCCCITT(&BufferToCompute,256,&crc16); 14.3.7 14.3.7.1 Sine Service Presentation This “service” differs from the preceding one in that it is structured differently: it is composed of an array and a method directly accessible through the AT91S_RomBoot structure. 14.3.7.2 Sine Service Description Table 14-8. Sine Service Description Description This function returns the amplitude coded on 16 bits, of a sine waveform for a given step. Input Parameters: Step of the sine. Corresponds to the precision of the amplitude calculation. Depends on the Sine Array used. Here, the array has 256 values (thus 256 steps) of amplitude for 180 degrees. Output Parameters: Amplitude of the sine waveform. Method and Array Available // Typical Use: pAT91->Sine(...); // Default Method: short AT91F_Sinus(int step) // Typical Use: short sinus; sinus = pAT91->SineTab[...]; // Array Embedded: const short AT91C_SINUS180_TAB[256] Sine Array with a resolution of 256 values for 180 degrees. 114 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 15. AT91RM9200 Reset Controller 15.1 Overview This chapter describes the AT91RM9200 reset signals and how to use them in order to assure correct operation of the device. The AT91RM9200 has two reset input lines called NRST and NTRST. Each line provides, respectively: • Initialization of the User Interface registers (defined in the user interface of each peripheral) and: – Sample the signals needed at bootup – Compel the processor to fetch the next instruction at address zero. • Initialization of the embedded ICE TAP controller. The NRST signal must be considered as the System Reset signal and the reader must take care when designing the logic to drive this reset signal. NTRST is typically used by the hardware debug interface which uses the In-Circuit Emulator unit and Initializes it without affecting the normal operation of the ARM® processor. This line shall also be driven by an on board logic. Both NRST and NTRST are active low signals that asynchronously reset the logic in the AT91RM92000. 15.1.1 15.1.1.1 Reset Conditions NRST Conditions NRST is the active low reset input. When power is first applied to the system, a power-on reset (also denominated as “cold” reset) must be applied to the AT91RM9200. During this transient state, it is mandatory to hold the reset signal low long enough for the power supply to reach a working nominal level and for the oscillator to reach a stable operating frequency. Typically, these features are provided by every power supply supervisor which, under a threshold voltage limit, the electrical environment is considered as not nominal. Power-up is not the only event to be considered as power-down or a brownout are also occurrences that assert the NRST signal. The threshold voltage must be selected according to the minimum operating voltage of the AT91RM9200 power supply lines marked as VDD in Figure 15-1. (See Section 37.2 ”DC Characteristics” on page 624.) The choice of the reset holding delay depends on the start-up time of the low frequency oscillator as shown below in Figure 15-1. (See Section 37.5.1 ”32 kHz Oscillator Characteristics” on page 627.) 115 1768G–ATARM–29-Sep-06 Figure 15-1. Cold Reset and Oscillator Start-up relationship VDD (1) VDD(min) XIN32 Oscillator Stabilization after Power-Up NRST Note: 1. VDD is applicable to VDDIOM, VDDIOP, VDDPLL, VDDOSC and VDDCORE NRST can also be asserted in circumstances other than the power-up sequence, such as a manual command. This assertion can be performed asynchronously, but exit from reset is synchronized internally to the default active clock. During normal operation, NRST must be active for a minimum delay time to ensure correct behavior. See Figure 15-2 and Table 15-1. Table 15-1. Symbol RST1 Reset Minimum Pulse Width Parameter NRST Minimum Pulse Width Min. Pulse Width 92 Unit µs Figure 15-2. NRST assertion RST1 NRST 15.1.1.2 NTRST Assertion As with the NRST signal, at power-up, the NTRST signal must be valid while the power supply has not obtained the minimum recommended working level. A clock on TCK is not required to validate this reset request. As with the NRST signal, NTRST can also be asserted in circumstances other than the powerup sequence, such as a manual command or an ICE Interface action. This assertion and deassertion can be performed asynchronously but must be active for a minimum delay time. (See Section 38.3 ”JTAG/ICE Timings” on page 649.) 15.1.2 15.1.2.1 Reset Management System Reset The system reset functionality is provided through the NRST signal. This Reset signal is used to compel the microcontroller unit to assume a set of initial conditions: • Sample the Boot Mode Select (BMS) logical state. • Restore the default states (default values) of the user interface. • Require the processor to perform the next instruction fetch from address zero. With the exception of the program counter and the Current Program Status Register, the processor’s registers do not have defined reset states. When the microcontroller’s NRST input is 116 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 asserted, the processor immediately stops execution of the current instruction independently of the clock. The system reset circuitry must take two types of reset requests into account: • The cold reset needed for the power-up sequence. • The user reset request. Both have the same effect but can have different assertion time requirements regarding the NRST pin. In fact, the cold reset assertion has to overlap the start-up time of the system. The user reset request requires a shorter assertion delay time than does cold reset. 15.1.2.2 Test Access Port (TAP) Reset Test Access Port (TAP) reset functionality is provided through the NTRST signal. The NTRST control pin initializes the selected TAP controller. The TAP controller involved in this reset is determined according to the initial logical state applied on the JTAGSEL pin after the last valid NRST. In Boundary Scan Mode, after a NTRST assertion, the IDCODE instruction is set onto the output of the instruction register in the Test-Logic-Reset controller state. Otherwise, in ICE Mode, the reset action is as follows: • • The core exits from Debug Mode. The IDCORE instruction is requested. In either Boundary Scan or ICE Mode a reset can be performed from the same or different circuitry, as shown in Figure 15-3 below, upon system reset at power-up or upon user request. Figure 15-3. Separate or Common Reset Management Reset Controller NTRST Reset Controller NRST AT91RM9200 (1) NTRST NRST Reset Controller AT91RM9200 (2) Notes: 1. NRST and NTRST handling in Debug Mode during development. 2. NRST and NTRST handling during production. In order to benefit the most regarding the separation of NRST and NTRST during the Debug phase of development, the user must independently manage both signals as shown in example (1) of Figure 15-3 above. However, once Debug is completed, both signals are easily managed together during production as shown in example (2) of Figure 15-3 above. 117 1768G–ATARM–29-Sep-06 15.1.3 Required Features for the Reset Controller The following table presents the features required of a reset controller in order to obtain an optimal system with the AT91RM9200 processor. Table 15-2. Feature Reset Controller Functions Synthesis Description Overlaps the transient state of the system during power-up/down and brownout. Overlaps the start-up time of the boot-up oscillator by holding the reset signal during this delay. Asserts the reset signal from a logic command and holds the reset signal with a shorter delay than that of the “Reset Active Timeout Period”. Power Supply Monitoring Reset Active Timeout Period Manual Reset Command 118 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 16. Memory Controller(MC) 16.1 Overview The Memory Controller (MC) manages the ASB bus and controls access by up to four masters. It features a bus arbiter and an address decoder that splits the 4G bytes of address space into areas to access the embedded SRAM and ROM, the embedded peripherals and the external memories through the External Bus Interface (EBI). It also features an abort status and a misalignment detector to assist in application debug. The Memory Controller allows booting from the embedded ROM or from an external non-volatile memory connected to the Chip Select 0 of the EBI. The Remap command switches addressing of the ARM vectors (0x0 - 0x20) on the embedded SRAM. Key Features of the AT91RM9200 Memory Controller are: • Programmable Bus Arbiter Handling Four Masters – Internal Bus is Shared by ARM920T, PDC, USB Host Port and Ethernet MAC Masters – Each Master Can Be Assigned a Priority Between 0 and 7 • Address Decoder Provides Selection For – Eight External 256-Mbyte Memory Areas – Four Internal 1-Mbyte Memory Areas – One 256-Mbyte Embedded Peripheral Area • Boot Mode Select Option – Non-volatile Boot Memory Can Be Internal or External – Selection is Made By BMS Pin Sampled at Reset • Abort Status Registers – Source, Type and All Parameters of the Access Leading to an Abort are Saved • Misalignment Detector – Alignment Checking of All Data Accesses – Abort Generation in Case of Misalignment • Remap Command – Provides Remapping of an Internal SRAM in Place of the Boot NVM 119 1768G–ATARM–29-Sep-06 16.2 Block Diagram Figure 16-1. Memory Controller Block Diagram Memory Controller ASB ARM920T Processor Abort Abort Status Address Decoder Internal Memories EMAC DMA Bus Arbiter UHP DMA Misalignment Detector External Bus Interface BMS User Interface Peripheral Data Controller APB Bridge Peripheral 0 Peripheral 1 APB Memory Controller Interrupt AIC From Master to Slave Peripheral N 120 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 16.3 Functional Description The Memory Controller (MC) handles the internal ASB bus and arbitrates the accesses of up to four masters. It is made up of: • A bus arbiter • An address decoder • An abort status • A misalignment detector The Memory Controller handles only little-endian mode accesses. All masters must work in littleendian mode only. 16.3.1 Bus Arbiter The Memory Controller has a user-programmable bus arbiter. Each master can be assigned a priority between 0 and 7, where 7 is the highest level. The bus arbiter is programmed in the register MC_MPR (Master Priority Register). The same priority level can be assigned to more than one master. If requests occur from two masters having the same priority level, the following default priority is used by the bus arbiter to determine the first to serve: Master 0, Master 1, Master 2, Master 3. The masters are: • the ARM920T as the Master 0 • the Peripheral DMA Controller as the Master 1 • the USB Host Port as the Master 2 • the Ethernet MAC as the Master 3 16.3.2 Address Decoder The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address bus and defines 11 separate areas: • One 256-Mbyte address space for the internal memories • Eight 256-Mbyte address spaces, each assigned to one of the eight chip select lines of the External Bus Interface • One 256-Mbyte address space reserved for the embedded peripherals • An undefined address space of 1536M bytes that returns an Abort if accessed 121 1768G–ATARM–29-Sep-06 16.3.2.1 External Memory Areas Figure 16-2 shows the assignment of the 256-Mbyte memory areas. Figure 16-2. External Memory Areas 256M Bytes 256M Bytes 256M Bytes 256M Bytes 0x0000 0000 0x0FFF FFFF Internal Memories Chip Select 0 Chip Select 1 Chip Select 2 Chip Select 3 Chip Select 4 Chip Select 5 Chip Select 6 Chip Select 7 EBI External Bus Interface 0x1000 0000 0x1FFF FFFF 0x2000 0000 0x2FFF FFFF 0x3000 0000 0x3FFF FFFF 0x4000 0000 256M Bytes 256M Bytes 256M Bytes 256M Bytes 256M Bytes 0x4FFF FFFF 0x5000 0000 0x5FFF FFFF 0x6000 0000 0x6FFF FFFF 0x7000 0000 0x7FFF FFFF 0x8000 0000 0x8FFF FFFF 0x9000 0000 6 x 256M Bytes 1,536M Bytes 0xEFFF FFFF Undefined (Abort) 256M Bytes 0xF000 0000 0xFFFF FFFF Peripherals 16.3.2.2 Internal Memory Mapping Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories. The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this address space, n equaling 1M byte divided by the size of the memory. When the address of the access is undefined within the internal memory area, i.e. over the address 0x0040 0000, the Address Decoder returns an Abort to the master. 122 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 16-3. Internal Memory Mapping After Remap 0x0000 0000 Internal Memory Area 0 0x000F FFFF 1M Byte 0x0010 0000 0x001F FFFF Internal Memory Area 1 Internal ROM Internal Memory Area 2 Internal SRAM Internal Memory Area 3 USB Host Port 1M Byte 0x0020 0000 256M bytes 0x002F FFFF 1M Byte 0x0030 0000 0x003F FFFF 0x0040 0000 1M Byte Undefined Area (Abort) 0x0FFF FFFF 252M bytes 16.3.2.3 Internal Memory Area 0 Depending on the BMS pin state at reset and as a function of the remap command, the memory mapped at address 0x0 is different. Before execution of the remap command the on-chip ROM (BMS = 1) or the 16-bit non-volatile memory connected to external chip select zero (BMS = 0) is mapped into Internal Memory Area 0. After the remap command, the internal SRAM at address 0x0020 0000 is mapped into Internal Memory Area 0. The memory mapped into Internal Memory Area 0 is accessible in both its original location and at address 0x0. The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors. Table 16-1. Internal Memory Area Depending on BMS and the Remap Command Before Remap BMS State Internal Memory Area 0 1 Internal ROM 0 External Memory Area 0 After Remap X Internal SRAM 16.3.2.4 Boot Mode Select The BMS pin state allows the device to boot out of an internal ROM or out of an external 16-bit memory connected on the signal NCS0. The input level on the BMS pin during the last 2 clock cycles before the reset selects the type of boot memory according to the following conditions: • If high, the Internal ROM, which is generally mapped within the Internal Memory Area 1, is also accessible through the Internal Memory Area 0 • If low, the External Memory Area 0, which is generally accessible from address 0x10000000, is also accessible through the Internal Memory Area 0. The BMS pin is multiplexed with an I/O line. After reset, this pin can be used as any standard PIO line. 16.3.3 Remap Command After execution, the Remap Command causes the Internal SRAM to be accessed through the Internal Memory Area 0. 123 1768G–ATARM–29-Sep-06 As the ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, and Fast Interrupt) are mapped from address 0x0 to address 0x20, the Remap Command allows the user to redefine dynamically these vectors under software control. The Remap Command is accessible through the Memory Controller User Interface by writing the MC_RCR (Remap Control Register) RCB field to one. The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as just after a reset. Table 16-1 on page 123 is provided to summarize the effect of these two key features on the nature of the memory mapped to the address 0x0. 16.3.4 Abort Status There are two reasons for an abort to occur: • an access to an undefined address • an access to a misaligned address. When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. However, only the master having generated the access leading to the abort takes this signal into account. The abort signal generates directly an abort on the ARM9TDMI. Note that, from the processor perspective, an abort can also be generated by the Memory Management Unit of the ARM920T, but this is obviously not managed by the Memory Controller and not discussed in this section. The Peripheral DMA Controller does not handle the abort input signal (and that’s why the connection is not represented in Figure 16-1). The UHP reports an unrecoverable error in the HcInterruptStatus register and resets its operations. The EMAC reports the Abort to the user through the ABT bit in its Status Register, which might generate an interrupt. To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status register set. The full 32-bit wide abort address is saved in the Abort Address Status Register (MC_AASR). Parameters of the access are saved in the Abort Status Register (MC_ASR) and include: • the size of the request (ABTSZ field) • the type of the access, whether it is a data read or write or a code fetch (ABTTYP field) • whether the access is due to accessing an undefined address (UNDADD bit) or a misaligned address (MISADD bit) • the source of the access leading to the last abort (MST0, MST1, MST2 and MST3 bits) • whether or not an abort occurred for each master since the last read of the register (SVMST0, SVMST1, SVMST2 and SVMST3 bits) except if it is traced in the MST bits. In case of Data Abort from the processor, the address of the data access is stored. This is probably the most useful, as finding which address has generated the abort would require disassembling the instruction and full knowledge of the processor context. However, in case of prefetch abort, the address might have changed, as the prefetch abort is pipelined in the ARM processor. The ARM processor takes the prefetch abort into account only if the read instruction is actually executed and it is probable that several aborts have occurred dur- 124 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 ing this time. So, in this case, it is preferable to use the content of the Abort Link register of the ARM processor. 16.3.5 Misalignment Detector The Memory Controller features a Misalignment Detector that checks the consistency of the accesses. For each access, regardless of the master, the size of access and the 0 and 1 bits of the address bus are checked. If the type of access is a word (32-bit) and the 0 and 1 bits are not 0, or if the type of the access is a half-word (16-bit) and the 0 bit is not 0, an abort is returned to the master and the access is cancelled. Note that the accesses of the ARM processor when it is fetching instructions are not checked. The misalignments are generally due to software errors leading to wrong pointer handling. These errors are particularly difficult to detect in the debug phase. As the requested address is saved in the Abort Status and the address of the instruction generating the misalignment is saved in the Abort Link Register of the processor, detection and correction of this kind of software error is simplified. 16.3.6 Memory Controller Interrupt The Memory Controller itself does not generate any interrupt. However, as indicated in Figure 16-1, the Memory Controller receives an interrupt signal from the External Bus Interface, which might be activated in case of Refresh Error detected by the SDRAM Controller. This interrupt signal just transits through the Memory Controller, which can neither enable/disable it nor return its activity. This Memory Controller interrupt signal is ORed with the other System Peripheral interrupt lines (RTC, ST, DBGU, PMC) to provide the System Interrupt on Source 1 of the Advanced Interrupt Controller. 125 1768G–ATARM–29-Sep-06 16.4 User Interface Base Address: 0xFFFFFF00 AT91RM9200 Memory Controller Memory Map Offset 0x00 0x04 0x08 0x0C 0x10 - 0x5C 0x60 Register MC Remap Control Register MC Abort Status Register MC Abort Address Status Register MC Master Priority Register Reserved EBI Configuration Registers See ”External Bus Interface (EBI)” on page 131 Name MC_RCR MC_ASR MC_AASR MC_MPR Access Write-only Read-only Read-only Read/Write 0x0 0x0 0x3210 Reset State 126 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 16.4.1 MC Remap Control Register MC_RCR Write-only 0xFFFF FF00 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RCB Register Name: Access Type: Absolute Address: 31 – 23 – 15 – 7 – • RCB: Remap Command Bit 0: No effect. 1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices. 127 1768G–ATARM–29-Sep-06 16.4.2 MC Abort Status Register MC_ASR Read-only 0x0 0xFFFF FF04 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 3 – 27 SVMST3 19 MST3 11 ABTTYP 2 – 1 MISADD 26 SVMST2 18 MST2 10 25 SVMST1 17 MST1 9 ABTSZ 0 UNDADD 24 SVMST0 16 MST0 8 Register Name: Access Type: Reset Value: Absolute Address: 31 – 23 – 15 – 7 – • UNDADD: Undefined Address Abort Status 0: The last abort was not due to the access of an undefined address in the address space. 1: The last abort was due to the access of an undefined address in the address space. • MISADD: Misaligned Address Abort Status 0: The last aborted access was not due to an address misalignment. 1: The last aborted access was due to an address misalignment. • ABTSZ: Abort Size Status ABTSZ 0 0 1 1 0 1 0 1 Abort Size Byte Half-word Word Reserved • ABTTYP: Abort Type Status ABTTYP 0 0 1 1 0 1 0 1 Abort Type Data Read Data Write Code Fetch Reserved • MST0: ARM920T Abort Source 0: The last aborted access was not due to the ARM920T. 1: The last aborted access was due to the ARM920T. 128 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • MST1: PDC Abort Source 0: The last aborted access was not due to the PDC. 1: The last aborted access was due to the PDC. • MST2: UHP Abort Source 0: The last aborted access was not due to the UHP. 1: The last aborted access was due to the UHP. • MST3: EMAC Abort Source 0: The last aborted access was not due to the EMAC. 1: The last aborted access was due to the EMAC. • SVMST0: Saved ARM920T Abort Source 0: No abort due to the ARM920T occurred since the last read of MC_ASR or it is notified in the bit MST0. 1: At least one abort due to the ARM920T occurred since the last read of MC_ASR. • SVMST1: Saved PDC Abort Source 0: No abort due to the PDC occurred since the last read of MC_ASR or it is notified in the bit MST1. 1: At least one abort due to the PDC occurred since the last read of MC_ASR. • SVMST2: Saved UHP Abort Source 0: No abort due to the UHP occurred since the last read of MC_ASR or it is notified in the bit MST2. 1: At least one abort due to the UHP occurred since the last read of MC_ASR. • SVMST3: Saved EMAC Abort Source 0: No abort due to the EMAC occurred since the last read of MC_ASR or it is notified in the bit MST3. 1: At least one abort due to the EMAC occurred since the last read of MC_ASR. 129 1768G–ATARM–29-Sep-06 16.4.3 MC Abort Address Status Register MC_AASR Read-only 0x0 0xFFFF FF08 30 29 28 ABTADD 23 22 21 20 ABTADD 15 14 13 12 ABTADD 7 6 5 4 ABTADD 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: Reset Value: Absolute Address: 31 • ABTADD: Abort Address This field contains the address of the last aborted access. 16.4.4 MC Master Priority Register MC_MPR Read/Write 0x3210 0xFFFF FF0C 30 – 22 – 14 29 – 21 – 13 MSTP3 6 5 MSTP1 4 28 – 20 – 12 27 – 19 – 11 – 3 – 2 26 – 18 – 10 25 – 17 – 9 MSTP2 1 MSTP0 0 24 – 16 – 8 Register Name: Access Type: Reset Value: Absolute Address: 31 – 23 – 15 – 7 – • MSTP0: ARM920T Priority • MSTP1: PDC Priority • MSTP2: UHP Priority • MSTP3: EMAC Priority 000: Lowest priority 111: Highest priority In the case of equal priorities, Master 0 has highest and Master 3 has lowest priority. 130 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17. External Bus Interface (EBI) 17.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an ARM-based device. The Static Memory, SDRAM and Burst Flash Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, SDRAM and Burst Flash. The EBI also supports the CompactFlash and the NAND Flash/SmartMedia protocols via integrated circuitry that greatly reduces the requirements for external components. Furthermore, the EBI handles data transfers with up to eight external devices, each assigned to eight address spaces defined by the embedded Memory Controller. Data transfers are performed through a 16-bit or 32-bit data bus, an address bus of up to 26 bits, up to eight chip select lines (NCS[7:0]) and several control pins that are generally multiplexed between the different external Memory Controllers. Features of the EBI are: • Integrates Three External Memory Controllers: – Static Memory Controller – SDRAM Controller – Burst Flash Controller • Additional Logic for NAND Flash/SmartMedia and CompactFlash Support • Optimized External Bus: – 16- or 32-bit Data Bus(1) – Up to 26-bit Address Bus, Up to 64 Mbytes Addressable – Up to 8 Chip Selects, Each Reserved for one of the Eight Memory Areas – Optimized Pin Multiplexing to Reduce Latencies on External Memories • Configurable Chip Select Assignment: – Burst Flash Controller or Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia Support – Static Memory Controller on NCS4 - NCS6, Optional NAND Flash/SmartMedia and CompactFlash Support – Static Memory Controller on NCS7 Note: 1. The 32-bit Data Bus is for SDRAM only. 131 1768G–ATARM–29-Sep-06 17.2 Block Diagram Figure 17-1 below shows the organization of the External Bus Interface. Figure 17-1. Organization of the External Bus Interface Memory Controller ASB External Bus Interface D[15:0] SDRAM Controller A0/NBS0 A1/NWR2/NBS2 A[15:2], A[22:18] MUX Logic A16/BA0 A17/BA1 NCS0/BFCS NCS1/SDCS NCS2 NCS3/SMCS Static Memory Controller NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS CAS SDWE NAND Flash/ SmartMedia Logic PIO CompactFlash Logic SDA10 D[31:16] A[24:23] A25/CFRNW NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NCS7 Address Decoder Chip Select Assignor BFCK BFAVD BFBAA/SMWE BFOE BFRDY/SMOE User Interface BFWE NWAIT Burst Flash Controller APB 132 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17.3 I/O Lines Description I/O Lines Description Function EBI D[31:0] A[25:0] Data Bus Address Bus SMC NCS[7:0] NWR[1:0] NOE NRD NBS1 NBS0 NWE NWAIT Chip Select Lines Write Signals Output Enable Read Signal NUB: Upper Byte Select NLB: Lower Byte Select Write Enable Wait Signal EBI for CompactFlash Support CFCE[2:1] CFOE CFWE CFIOR CFIOW CFRNW CFCS CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash I/O Read Signal CompactFlash I/O Write Signal CompactFlash Read Not Write Signal CompactFlash Chip Select Line EBI for NAND Flash/SmartMedia Support SMCS SMOE SMWE NAND Flash/Smart Media Chip Select Line NAND Flash/SmartMedia Output Enable NAND Flash/SmartMedia Write Enable SDRAM Controller SDCK SDCKE SDCS BA[1:0] SDWE RAS - CAS NWR[3:0] NBS[3:0] SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Line Bank Select SDRAM Write Enable Row and Column Signal Write Signals Byte Mask Signals SDRAM Address 10 Line Output Output Output Output Output Output Output Output Output Low Low Low Low High Low Output Output Output Low Low Low Output Output Output Output Output Output Output Low Low Low Low Low Low Output Output Output Output Output Output Output Input Low Low Low Low Low Low Low Low I/O Output Type Active Level Table 17-1. Name 133 1768G–ATARM–29-Sep-06 Table 17-1. Name I/O Lines Description (Continued) Function Burst Flash Controller Type Active Level BFCK BFCS BFAVD BFBAA BFOE BFRDY BFWE Burst Flash Clock Burst Flash Chip Select Line Burst Flash Address Valid Signal Burst Flash Address Advance Signal Burst Flash Output Enable Burst Flash Ready Signal Burst Flash Write Enable Output Output Output Output Output Input Output Low Low Low Low High Low The connection of some signals through the MUX logic is not direct and depends on the Memory Controller in use at the moment. Table 17-2 below details the connections between the three Memory Controllers and the EBI pins. Table 17-2. EBI Pins NWR1/NBS1/CFIOR A0/NBS0 A1 A[11:2] SDA10 A12 A[14:13] A[25:15] D[31:16] D[15:0] EBI Pins and Memory Controllers I/O Line Connections SDRAMC I/O Lines NBS1 Not Supported Not Supported A[9:0] A10 Not Supported A[12:11] Not Supported D[31:16] D[15:0] BFC I/O Lines Not Supported Not Supported A0 A[10:1] Not Supported A11 A[13:12] A[24:14] Not Supported D[15:0] SMC I/O Lines NWR1/NUB A0/NLB A1 A[11:2] Not Supported A12 A[14:13] A[25:15] Not Supported D[15:0] 134 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17.4 17.4.1 Application Example Hardware Interface Table 17-3 below details the connections to be applied between the EBI pins and the external devices for each Memory Controller. Table 17-3. EBI Pins and External Device Connections Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices SMC D0 - D7 – – A0 A1 A2 - A9 A10 A11 – A12 A13 - A14 A15 A16 A17 A18 - A20 A21 A22 A23 - A24 A25 CS CS CS CS CS CS CS OE WE D0 - D7 D8 - D15 – – A0 A1 - A8 A9 A10 – A11 A12 - A13 A14 A15 A16 A17 - A19 A20 A21 A22 - A23 A24 CS CS CS CS CS CS CS OE WE (5) Pin Controller D0 - D7 D8 - D15 D16 - D31 A0/NBS0 A1/NWR2/NBS2 A2 - A9 A10 A11 SDA10 A12 A13 - A14 A15 A16/BA0 A17/BA1 A18 - A20 A21 A22 A23 - A24 A25 NCS0/BFCS NCS1/SDCS NCS2 NCS3/SMCS NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NRD/NOE/CFOE NWR0/NWE/CFWE 16-bit Static Device Burst Flash Device BFC SDRAM SDRAMC D0 - D7 D8 - D15 D16 - D31 DQM0 DQM2 A0 - A7 A8 A9 A10 – A11 - A12 – BA0 BA1 – – – – – – CS – – – – – – – CompactFlash SMC D0 - D7 D8 - 15 – A0 A1 A2 - A9 A10 – – – – – – – – – REG(3) – CFRNW – – – – CFCS (1) (1) NANDFlash/ SmartMedia D0 - D7 D8 - D15 – NLB A0 A1 - A8 A9 A10 – A11 A12 - A13 A14 A15 A16 A17 - A19 A20 A21 A22 - A23 A24 CS CS CS CS CS CS CS OE WE D0 - D7 D8 - D15 – – A0 A1 - A8 A9 A10 – A11 A12 - A13 A14 A15 A16 A17 - A19 A20 A21 A22 - A23 A24 CS – – – – – – – – AD0 - AD7 – – – – – – – – – – – – – – CLE ALE – – – – – – – – – CE1 CE2 OE WE 135 1768G–ATARM–29-Sep-06 Table 17-3. EBI Pins and External Device Connections (Continued) Pins of the Interfaced Device 8-bit Static Device 2 x 8-bit Static Devices SMC – – – – – – – – – – – – – – – – – WE(5) – – – – – – – – – – – – – – – – NUB – – – – – – – – – – – – – – – – 16-bit Static Device Burst Flash Device BFC – – CK AVD BAA OE RDY WE – – – – – – – – – NANDFlash/ SmartMedia Pin Controller NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW BFCK BFAVD BFBAA/SMWE BFOE BFRDY/SMOE BFWE SDCK SDCKE RAS CAS SDWE NWAIT Pxx (2) SDRAM SDRAMC DQM1 DQM3 – – – – – – CLK CKE RAS CAS WE – – – – CompactFlash SMC IOR IOW – – – – – – – – – – – WAIT CD1 or CD2 – – – – – – WE – OE – – – – – – – – CE RDY Pxx(2) Pxx (2) Notes: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer between the EBI data bus and the CompactFlash slot. 2. Any PIO line. 3. The REG signal of the CompactFlash can be driven by any of the following address bits: A24, A22 to A11. For details, see Section 17.6.6 ”CompactFlash Support” on page 139. 4. NWR1 enables upper byte writes. NWR0 enables lower byte writes. 136 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17.4.2 Connection Examples Figure 17-2 below shows an example of connections between the EBI and external devices. Figure 17-2. EBI Connections to Memory Devices EBI D0-D31 RAS CAS SDCK SDCKE SDWE A0/NBS0 NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 NRD/NOE NWR0/NWE D0-D7 2M x 8 SDRAM D0-D7 D8-D15 2M x 8 SDRAM D0-D7 CS CLK CKE SDWE WE RAS CAS DQM NBS0 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 CS CLK CKE SDWE WE RAS CAS DQM NBS1 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 SDA10 A2-A15 A16/BA0 A17/BA1 A18-A25 D16-D23 NCS0/BFCS NCS1/SDCS NCS2 NCS3 NCS4 NCS5 NCS6 NCS7 2M x 8 SDRAM D0-D7 D24-D31 2M x 8 SDRAM D0-D7 CS CLK CKE SDWE WE RAS CAS DQM NBS2 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 CS CLK CKE SDWE WE RAS CAS DQM NBS3 A0-A9, A11 A10 BA0 BA1 A2-A11, A13 SDA10 A16/BA0 A17/BA1 BFCLK BFOE BFWE BFAVD BFRDY 2M x 16 Burst Flash D0-D15 D0-D15 CE A0-A20 A1-A21 CLK OE WE AVD RDY 128K x 8 SRAM D0-D7 D0-D7 A0-A16 A1-A17 D8-D15 128K x 8 SRAM D0-D7 A0-A16 A1-A17 CS NRD/NOE A0/NWR0/NBS0 OE WE NRD/NOE NWR1/NBS1 CS OE WE 137 1768G–ATARM–29-Sep-06 17.5 17.5.1 Product Dependencies I/O Lines The pins used for interfacing the External Bus Interface may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the External Bus Interface pins to their peripheral function. If I/O lines of the External Bus Interface are not used by the application, they can be used for other purposes by the PIO Controller. 17.6 Functional Description The EBI transfers data between the internal ASB Bus (handled by the Memory Controller) and the external memories or peripheral devices. It controls the waveforms and the parameters of the external address, data and control busses and is composed of the following elements: • The Static Memory Controller (SMC) • The SDRAM Controller (SDRAMC) • The Burst Flash Controller (BFC) • A chip select assignment feature that assigns an ASB address space to the external devices. • A multiplex controller circuit that shares the pins between the different Memory Controllers. • Programmable CompactFlash support logic • Programmable NAND Flash /SmartMedia and support logic 17.6.1 Bus Multiplexing The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed. Multiplexing is also designed to respect the data float times defined in the Memory Controllers. Furthermore, refresh cycles of the SDRAM are executed independently by the SDRAM Controller without delaying the other external Memory Controller accesses. Lastly, it prevents burst accesses on the same page of a burst Flash from being interrupted which avoids the need to restart a highlatency first access. 17.6.2 Pull-up Control The EBI permits enabling of on-chip pull-up resistors on the data bus lines not multiplexed with the PIO Controller lines. The pull-up resistors are enabled after reset. Setting the DBPUC bit disables the pull-up resistors on the D0 to D15 lines. Enabling the pull-up resistor on the D16 - D31 lines can be performed by programming the appropriate PIO controller. 17.6.3 Static Memory Controller For information on the Static Memory Controller, refer to the SMC Section 18.1 ”Overview” on page 153. 17.6.4 SDRAM Controller For information on the SDRAM Controller, refer to the SDRAMC description on Section 19.1 ”Overview” on page 193. 138 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17.6.5 Burst Flash Controller For information on the Burst Flash Controller, refer to the BFC Section 20.1 ”Overview” on page 215. 17.6.6 CompactFlash Support The External Bus Interface integrates circuitry that interfaces to CompactFlash devices. The CompactFlash logic is driven by the Static Memory Controller (SMC) on the NCS4 address space. Programming the CS4A field of the Chip Select Assignment Register (See Section 17.8.1 ”EBI Chip Select Assignment Register” on page 150.) to the appropriate value enables this logic. Access to an external CompactFlash device is then made by accessing the address space reserved to NCS4 (i.e., between 0x5000 0000 and 0x5FFF FFFF). When multiplexed with CFCE1 and CFCE2 signals, the NCS5 and NCS6 signals become unavailable. Performing an access within the address space reserved to NCS5 and NCS6 (i.e., between 0x6000 0000 and 0x7FFF FFFF) may lead to an unpredictable outcome. The True IDE Mode is not supported and in I/O Mode, the signal _IOIS16 is not managed. 17.6.6.1 I/O Mode, Common Memory Mode and Attribute Memory Mode Within the NCS4 address space, the current transfer address is used to distinguish I/O mode, common memory mode and attribute memory mode. More precisely, the A23 bit of the transfer address is used to select I/O Mode. Any EBI address bit not required by the CompactFlash device (i.e., bit A24 or bits A22 to A11) can be used to separate common memory mode and attribute memory mode. Using the A22 bit, for example, leads to the address map in Figure 17-3 below. In this figure, “i” stands for any hexadecimal digit. Figure 17-3. Address Map Example 0x5iBF FFFF 0x5i80 0000 0x5i7F FFFF 0x5i40 0000 0x5i3F FFFF 0x5i00 0000 A23 = 1 A22 = 0 A23 = 0 A22 = 1 A23 = 0 A22 = 0 I/O Mode Common Memory Mode Attribute Memory Mode Note: In the above example, the A22 pin of the EBI can be used to drive the REG signal of the CompactFlash Device. 17.6.6.2 Read/Write Signals In I/O mode, the CompactFlash logic drives the read and write command signals of the SMC on CFIOR and CFIOW signals, while the CFOE and CFWE signals are deactivated. Likewise, in common memory mode and attribute memory mode, the SMC signals are driven on the CFOE and CFWE signals, while the CFIOR and CFIOW are deactivated. Figure 17-4 on page 140 demonstrates a schematic representation of this logic. Attribute memory mode, common memory mode and I/O mode are supported by setting the address setup and hold time on the NCS4 chip select to the appropriate values. For details on 139 1768G–ATARM–29-Sep-06 these signal waveforms, please refer to: Section 18.5.5 ”Setup and Hold Cycles” on page 167 of the Static Memory Controller documentation. Figure 17-4. CompactFlash Read/Write Control Signals External Bus Interface SMC CompactFlash Logic A23 1 1 CFIOR CFIOW NRD_NOE NWR0_NWE 1 1 CFOE CFWE 17.6.6.3 Access Type The CFCE1 and CFCE2 signals enable upper- and lower-byte access on the data bus of the CompactFlash device in accordance with Table 17-4 below. The odd byte access on the D[7:0] bus is only possible when the SMC is configured to drive 8-bit memory devices on the NCS4 pin. The Chip Select Register (DBW field in Section 18.6.1 ”SMC Chip Select Registers” on page 189) of the NCS4 address space must be set as shown in Table 17-4 to enable the required access type. The CFCE1 and CFCE2 waveforms are identical to the NCS4 waveform. For details on these waveforms and timings, refer to the Static Memory Controller Section 18.1 ”Overview” on page 153. Table 17-4. Access Upper- and Lower-byte Access CFCE2 1 CFCE1 0 0 1 0 A0 0 1 X X D[15:8] Don’t Care/High Z Don’t Care/High Z Odd Byte Odd Byte D[7:0] Even Byte Odd Byte Don’t Care/High Z Even Byte SMC_CSR4 (DBW) 8-bit or 16-bit 8-bit 16-bit 16-bit Byte R/W Access 1 Odd Byte R/W Access Half-word R/W Access 0 0 17.6.6.4 Multiplexing of CompactFlash Signals on EBI Pins Table 17-5 below and Table 17-6 on page 141 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 17-5 are strictly dedicated to the CompactFlash interface as soon as the CS4A field of the Chip Select Assignment Register is set (See Section 17.8.1 ”EBI Chip Select Assignment Register” on page 150.) These pins must not be used to drive any other memory devices. 140 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 The EBI pins in Table 17-6 on page 141 remain shared between all memory areas when the CompactFlash interface is enabled (CS4A = 1). Table 17-5. Dedicated CompactFlash Interface Multiplexing CS4A = 1 Pins NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 CompactFlash Signals CFCS CFCE1 CFCE2 CS4A = 0 EBI Signals NCS4 NCS5 NCS6 Table 17-6. Shared CompactFlash Interface Multiplexing Access to CompactFlash Device Access to Other EBI Devices EBI Signals NRD/NOE NWR0/NWE NWR1/NBS1 NWR3/NBS3 A25 Pins NOE/NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW A25/CFRNW CompactFlash Signals CFOE CFWE CFIOR CFIOW CFRNW 17.6.6.5 CompactFlash Application Example Figure 17-5 below illustrates an example of a CompactFlash application. CFCS and CFRNW signals are not directly connected to the CompactFlash slot, but do control the direction and the output enable of the buffers between the EBI and the CompactFlash Device. The timing of the CFCS signal is identical to the NCS4 signal. Moreover, the CFRNW signal remains valid throughout the transfer, as does the address bus. The CompactFlash _WAIT signal is connected to the NWAIT input of the Static Memory Controller. For details on these waveforms and timings, refer to the Static Memory Controller Section 18.1 ”Overview” on page 153. 141 1768G–ATARM–29-Sep-06 Figure 17-5. CompactFlash Application Example EBI CompactFlash Connector D[15:0] DIR /OE A25/CFRNW NCS4/CFCS D[15:0] _CD1 CD (PIO) _CD2 /OE A[10:0] A22/REG A[10:0] _REG NOE/CFOE NWE/CFWE NWR1/CFIOR NWR3/CFIOW _OE _WE _IORD _IOWR NCS5/CFE1 NCS6/CFE2 _CE1 _CE2 NWAIT _WAIT 17.6.7 NAND Flash/ SmartMedia Support The EBI integrates circuitry that interfaces to NAND Flash/SmartMedia devices. The NAND Flash/SmartMedia logic is driven by the Static Memory Controller on the NCS3 address space. Programming the CS3A field in the Chip Select Assignment Register to the appropriate value enables the NAND Flash/SmartMedia logic (See Section 17.8.1 ”EBI Chip Select Assignment Register” on page 150.) Access to an external NAND Flash/SmartMedia device is then made by accessing the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF). The NAND Flash/SmartMedia Logic drives the read and write command signals of the SMC on the SMOE and SMWE signals when the NCS3 signal is active. SMOE and SMWE are invalidated as soon as the transfer address fails to lie in the NCS3 address space. For details on these waveforms, refer to the Static Memory Controller Section 18.1 ”Overview” on page 153. The SMWE and SMOE signals are multiplexed with BFRDY and BFBAA signals of the Burst Flash Controller. This multiplexing is controlled in the MUX logic part of the EBI by the CS3A field of the Chip Select Assignment Register (See Section 17.8.1 ”EBI Chip Select Assignment Register” on page 150.) This logic also controls the direction of the BFRDY/SMOE pad. 142 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 17-6. BFC NAND Flash/SmartMedia Signal Multiplexing on EBI Pins MUX Logic BFRDY BFRDY_SMOE BFBAA BFBAA_SMWE SMC NAND Flash/Smart Media Logic NCS3 NRD_NOE SMOE SMWE NWR0_NWE EBI User Interface CS3A The address latch enable and command latch enable signals on the NAND Flash/SmartMedia device are driven by address bits A22 and A21 of the EBI address bus. The user should note that any bit on the EBI address bus can also be used for this purpose. The command, address or data words on the data bus of the NAND Flash/SmartMedia device are distinguished by using their address within the NCS3 address space. The chip enable (CE) signal of the device and the ready/busy (R/B) signals are connected to PIO lines. The CE signal then remains asserted even when NCS3 is not selected, preventing the device from returning to standby mode. Some functional limitation with the supported burst Flash device will occur when the NAND Flash/SmartMedia device is activated due to the fact that the SMOE and SMWE signals are multiplexed with BFRDY and BFBAA signals respectively. 143 1768G–ATARM–29-Sep-06 Figure 17-7. NAND Flash/SmartMedia Application Example D[7:0] A[22:21] AD[7:0] ALE CLE NCS3/SMCS Not Connected EBI NAND Flash/SmartMedia BFBAA/SMWE BFRDY/SMOE NWE NOE PIO PIO CE R/B 144 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17.7 17.7.1 17.7.1.1 Implementation Examples 16-bit SDRAM Hardware Configuration 17.7.1.2 Software Configuration The following configuration has to be performed: • Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space • Initialize the SDRAM Controller accordingly to SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 16 bits. The SDRAM initialization sequence is described in the “SDRAM Device Initialization” part of the SDRAM controller. 145 1768G–ATARM–29-Sep-06 17.7.2 17.7.2.1 32-bit SDRAM Hardware Configuration 17.7.2.2 Software Configuration The following configuration has to be performed: • Assign the EBI CS1 to the SDRAM controller by setting the bit EBI_CS1A in the EBI Chip Select Assignment Register located in the bus matrix memory space • Initialize the SDRAM Controller accordingly to SDRAM device and system bus frequency. The Data Bus Width is to be programmed to 32 bits. The data lines D[16..31] are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller. The SDRAM initialization sequence is described in the “SDRAM Device Initialization” part of the SDRAM controller. 146 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17.7.3 17.7.3.1 NOR Flash on NCS0 Hardware Configuration 17.7.3.2 Software Configuration The default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on a 16-bit non-volatile memory at slow clock. For other configurations, configure Static Memory Controller CS0 Setup, Pulse, Cycle and Mode accordingly to Flash timings and system bus frequency. 147 1768G–ATARM–29-Sep-06 17.7.4 17.7.4.1 Compact Flash Hardware Configuration 17.7.4.2 Software Configuration The following configuration has to be performed: • Assign the EBI CS4 to the CompactFlash slot by setting the bit EBI_CS4A in the EBI Chip Select Assignment Register located in the Bus Matrix memory space. • The address line A23 is to select I/O (A23=1) or Memory mode (A23=0) and the address line A22 for REG function. • A23, CFRNW, CFCS0, CFCE1 and CFCE2 signals are multiplexed with PIO lines and thus the dedicated PIOs must be programmed in peripheral mode in the PIO controller • Configure a PIO line as an output for CFRST and two others as an input for CFIRQ and CARD DETECT functions respectively. • Configure SMC CS4 Setup, Pulse, Cycle and Mode accordingly to Compact Flash timings and system bus frequency. 148 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17.8 External Bus Interface (EBI) User Interface AT91RM9200 EBI User Interface Base Address: 0xFFFF FF60 Table 17-7. Offset 0x00 0x04 0x08 0x0C 0x10 - 0x2C 0x30 - 0x5C 0x60 0x64 - 0x9C External Bus Interface Memory Map Register Chip Select Assignment Register Configuration Register Reserved Reserved SMC User Interface SDRAMC User Interface BFC User Interface Reserved Name EBI_CSA EBI_CFGR Access Read/Write Read/Write – – (See Section 18.6 ”Static Memory Controller (SMC) User Interface” on page 188.) (See Section 19.7 ”SDRAM Controller (SDRAMC) User Interface” on page 205.) (See Section 20.7 ”Burst Flash Controller (BFC) User Interface” on page 227.) Reset State 0x0 0x0 149 1768G–ATARM–29-Sep-06 17.8.1 EBI Chip Select Assignment Register EBI_CSA Read/Write 0x0 0x0 0xFFFF FF60 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 CS4A 27 – 19 – 11 – 3 CS3A 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 CS1A 24 – 16 – 8 – 0 CS0A Register Name: Access Type: Reset Value: Offset: Absolute Address: 31 – 23 – 15 – 7 – • CS0A: Chip Select 0 Assignment 0 = Chip Select 0 is assigned to the Static Memory Controller. 1 = Chip Select 0 is assigned to the Burst Flash Controller. • CS1A: Chip Select 1 Assignment 0 = Chip Select 1 is assigned to the Static Memory Controller. 1 = Chip Select 1 is assigned to the SDRAM Controller. • CS3A: Chip Select 3 Assignment 0 = Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC. 1 = Chip Select 3 is assigned to the Static Memory Controller and the NAND Flash/SmartMedia Logic is activated. • CS4A: Chip Select 4 Assignment 0 = Chip Select 4 is assigned to the Static Memory Controller and NCS4, NCS5 and NCS6 behave as defined by the SMC. 1 = Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic is activated. Accessing the address space reserved to NCS5 and NCS6 may lead to an unpredictable outcome. 150 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 17.8.2 EBI Configuration Register EBI_CFGR Read/Write 0x0 0x04 0xFFFF FF64 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 24 – 16 – 8 – 0 DBPUC Register Name: Access Type: Reset Value: Offset: Absolute Address: 31 – 23 – 15 – 7 – • DBPUC: Data Bus Pull-Up Configuration 0 = [D15:0] Data Bus bits are internally pulled-up to the VDDIOM power supply. 1 = [D15:0] Data Bus bits are not internally pulled-up. 151 1768G–ATARM–29-Sep-06 152 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 18. Static Memory Controller (SMC) 18.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to external static memory or peripheral devices. The SMC is fully programmable and can address up to 512M bytes. It has eight chip selects and a 26-bit address bus. The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. The SMC supports different access protocols allowing single clock cycle memory accesses. It also provides an external wait request capability. The main features of the SMC are: • External memory mapping, 512-Mbyte address space • Up to 8 Chip Select Lines • 8- or 16-bit Data Bus • Remap of Boot Memory • Multiple Access Modes Supported – Byte Write or Byte Select Lines – Two different Read Protocols for each Memory Bank • Multiple Device Adaptability – Compliant with LCD Module – Programmable Setup Time Read/Write – Programmable Hold Time Read/Write • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time 153 1768G–ATARM–29-Sep-06 18.2 Block Diagram Figure 18-1. Static Memory Controller Block Diagram SMC Memory Controller SMC Chip Select PIO Controller NCS[7:0] NRD/NOE NWR0/NWE NWR1/NUB A0/NLB PMC MCK A[25:1] D[15:0] NWAIT User Interface APB 154 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 18.3 I/O Lines Descriptiion Table 18-1. Name NCS[7:0] NRD/NOE NWR0/NWE NWR1/NUB A0/NLB A[25:1] D[15:0] NWAIT I/O Lines Description Description Static Memory Controller Chip Select Lines Read/Output Enable Signal Write 0/Write Enable Signal Write1/Upper Byte Select Signal Address Bit 0/Lower Byte Select Signal Address Bus Data Bus External Wait Signal Type Output Output Output Output Output Output I/O Input Low Active Level Low Low Low Low Low Multiplexed signals are listed in Table 18-2 with their functions. Table 18-2. Static Memory Controller Multiplexed Signals Related Function 8-bit or 16-bit data bus, see 18.5.1.3 ”Data Bus Width” on page 157. Byte-write or byte-select access, see 18.5.2.1 ”Write Access Type” on page 158. Byte-write or byte-select access, see 18.5.2.1 ”Write Access Type” on page 158. Byte-write or byte-select access, see 18.5.2.1 ”Write Access Type” on page 158. Multiplexed Signals A0 NRD NWR0 NWR1 NLB NOE NWE NUB 155 1768G–ATARM–29-Sep-06 18.4 18.4.1 Product Dependencies I/O Lines The pins used for interfacing the Static Memory Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Static Memory Controller pins to their peripheral function. If I/O lines of the Static Memory Controller are not used by the application, they can be used for other purposes by the PIO Controller. 18.5 18.5.1 Functional Description External Memory Interface External Memory Mapping The memory map is defined by hardware and associates the internal 32-bit address space with the external 26-bit address bus. Note that A[25:0] is only significant for 8-bit memory. A[25:1] is used for 16-bit memory. If the physical memory device is smaller than the page size, it wraps around and appears to be repeated within the page. The SMC correctly handles any valid access to the memory device within the page. See Figure 18-2. Figure 18-2. Case of an External Memory Smaller than Page Size Base + 4M Bytes 1M Byte Device Hi Low Base + 3M Bytes 1M Byte Device Memory Map 1M Byte Device Hi Low Base + 2M Bytes Hi Low Base + 1M Byte 1M Byte Device Hi Low Base Repeat 1 Repeat 2 Repeat 3 18.5.1.1 18.5.1.2 Chip Select Lines The Static Memory Controller provides up to eight chip select lines: NCS0 to NCS7. 156 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-3. Memory Connections for Eight External Devices(1) NCS[7:0] NRD SMC NWR[1:0] A[25:0] D[15:0] NCS7 NCS6 NCS5 NCS4 NCS3 NCS2 NCS1 NCS0 Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Memory Enable Output Enable Write Enable A[25:0] 8 or 16 D[15:0] or D[7:0] Note: 1. The maximum address space per device is 64M bytes 18.5.1.3 Data Bus Width A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the DBW field in the SMC_CSR for the corresponding chip select. See ”SMC Chip Select Registers” on page 189. Figure 18-4 shows how to connect a 512K x 8-bit memory on NCS2 (DBW = 10). Figure 18-4. Memory Connection for an 8-bit Data Path Device D[7:0] D[15:8] A[25:1] SMC A0 NWR1 NWR0 NRD NCS2 Write Enable Output Enable Memory Enable A[25:1] A0 D[7:0] Figure 18-5 shows how to connect a 512K x 16-bit memory on NCS2 (DBW = 01). 157 1768G–ATARM–29-Sep-06 Figure 18-5. Memory Connection for a 16-bit Data Path Device D[7:0] D[15:8] A[25:1] SMC NLB NUB NWE NOE NCS2 D[7:0] D[15:8] A[24:0] Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable 18.5.2 18.5.2.1 Write Access Write Access Type Each chip select with a 16-bit data bus can operate with one of two different types of write access: • Byte Write Access supports two byte write and a single read signal. • Byte Select Access selects upper and/or lower byte with two byte select lines, and separate read and write signals. This option is controlled by the BAT field in the SMC_CSR for the corresponding chip select. See ”SMC Chip Select Registers” on page 189. Byte Write Access Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory page. • The signal A0/NLB is not used. • The signal NWR1/NUB is used as NWR1 and enables upper byte writes. • The signal NWR0/NWE is used as NWR0 and enables lower byte writes. • The signal NRD/NOE is used as NRD and enables half-word and byte reads. Figure 18-6 shows how to connect two 512K x 8-bit devices in parallel on NCS2 (BAT = 0) 158 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-6. Memory Connection for 2 x 8-bit Data Path Devices D[7:0] D[15:8] A[24:1] SMC A0 NWR1 NWR0 NRD NCS2 Write Enable Read Enable Memory Enable A[18:0] D[7:0] D[15:8] A[18:0] Write Enable Read Enable Memory Enable Byte Select Access Byte Select Access is used to connect 16-bit devices in a memory page. • The signal A0/NLB is used as NLB and enables the lower byte for both read and write operations. • The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write operations. • The signal NWR0/NWE is used as NWE and enables writing for byte or half-word. • The signal NRD/NOE is used as NOE and enables reading for byte or half-word. Figure 18-7 shows how to connect a 16-bit device with byte and half-word access (e.g., SRAM device type) on NCS2 (BAT = 1). Figure 18-7. Connection to a 16-bit Data Path Device with Byte and Half-word Access D[7:0] D[15:8] A[19:1] SMC NLB NUB NWE NOE NCS2 D[7:0] D[15:8] A[18:0] Low Byte Enable High Byte Enable Write Enable Output Enable Memory Enable Figure 18-8 shows how to connect a 16-bit device without byte access (e.g., Flash device type) on NCS2 (BAT = 1). 159 1768G–ATARM–29-Sep-06 Figure 18-8. Connection to a 16-bit Data Path Device without Byte Write Capability D[7:0] D[15:8] A[19:1] SMC NLB NUB NWE NOE NCS2 Write Enable Output Enable Memory Enable D[7:0] D[15:8] A[18:0] 18.5.2.2 Write Data Hold Time During write cycles, data output becomes valid after the rising edge of MCK and remains valid after the rising edge of NWE. During a write access, the data remain on the bus 1/2 period of MCK after the rising edge of NWE. See Figure 18-9 and Figure 18-10. Figure 18-9. Write Access with 0 Wait State MCK A[25:0] NCS2 NWE D[15:0] Figure 18-10. Write Access with 1 Wait State MCK A[25:0] NCS2 NWE D[15:0] 160 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 18.5.3 18.5.3.1 Read Access Read Protocols The SMC provides two alternative protocols for external memory read accesses: standard and early read. The difference between the two protocols lies in the behavior of the NRD signal. For write accesses, in both protocols, NWE has the same behavior. In the second half of the master clock cycle, NWE always goes low (see Figure 18-18 on page 166). The protocol is selected by the DRP field in SMC_CSR (See “SMC Chip Select Registers” on page 189.). Standard read protocol is the default protocol after reset. Note: In the following waveforms and descriptions, NRD represents NRD as well as NOE since the two signals have the same waveform. Likewise, NWE represents NWE, NWR0 and NWR1 unless NWR0 and NWR1 are otherwise represented. In addition, NCS represents NCS[7:0] (see ”I/O Lines” on page 156, Table 18-1 and Table 18-2). Standard Read Protocol Standard read protocol implements a read cycle during which NRD and NWE are similar. Both are active during the second half of the clock cycle. The first half of the clock cycle allows time to ensure completion of the previous access as well as the output of address lines and NCS before the read cycle begins. During a standard read protocol, NCS is set low and address lines are valid at the beginning of the external memory access, while NRD goes low only in the second half of the master clock cycle to avoid bus conflict. See Figure 18-11. Figure 18-11. Standard Read Protocol MCK A[25:0] NCS NRD D[15:0] Early Read Protocol Early read protocol provides more time for a read access from the memory by asserting NRD at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NRD remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol can allow a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contentions on the external bus. 161 1768G–ATARM–29-Sep-06 Figure 18-12. Early Read Protocol MCK A[25:0] NCS NRD D[15:0] 18.5.4 Wait State Management The SMC can automatically insert wait states. The different types of wait states managed are listed below: • Standard wait states • External wait states • Data float wait states • Chip select change wait states • Early Read wait states 18.5.4.1 Standard Wait States Each chip select can be programmed to insert one or more wait states during an access on the corresponding memory area. This is done by setting the WSEN field in the corresponding SMC_CSR ( 18.6.1 ”SMC Chip Select Registers” on page 189). The number of cycles to insert is programmed in the NWS field in the same register. Below is the correspondence between the number of standard wait states programmed and the number of clock cycles during which the NWE pulse is held low: 0 wait states 1 wait state 1/2 clock cycle 1 clock cycle For each additional wait state programmed, an additional cycle is added. 162 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-13. One Standard Wait State Access 1 Wait State Access MCK A[25:0] NCS NWE NRD (1) (2) Notes: 1. Early Read Protocol 2. Standard Read Protocol 18.5.4.2 External Wait States The NWAIT input pin is used to insert wait states beyond the maximum standard wait states programmable or in addition to. If NWAIT is asserted low, then the SMC adds a wait state and no changes are made to the output signals, the internal counters or the state. When NWAIT is deasserted, the SMC completes the access sequence. WARNING: Asserting NWAIT low stops the core’s clock and thus stops program execution. The input of the NWAIT signal is an asynchronous input. To avoid any metastability problems, NWAIT is synchronized before using it. This operation results in a two-cycle delay. NWS must be programmed as a function of synchronization time and delay between NWAIT falling and control signals falling (NRD/NWE), otherwise SMC will not function correctly. NWS ≥ Wait Delay from nrd/nwe + external_nwait Synchronization Delay + 1 where external NWAIT synchronization is equal to 2 cycles. The minimum value for NWS is 3 if NWAIT is used. WARNING: If NWAIT is asserted during a setup or hold timing, the SMC does not function correctly. 163 1768G–ATARM–29-Sep-06 Figure 18-14. NWAIT behavior in Read Access MCK A[25:0] NWAIT NWAIT internally synchronized NRD NCS (2) (1) Wait Delay from NRD NWAIT Synchronization Delay Notes: 1. Early Read Protocol 2. Standard Read Protocol Figure 18-15. NWAIT behavior in Write Access MCK A[25:0] NWAIT NWAIT internally synchronized NWE D[15:0] Wait Delay from NWE NWAIT Synchronization Delay 18.5.4.3 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access before starting a write access or a read access to a different external memory. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF field of the SMC_CSR register for the corresponding chip select ( 18.6.1 ”SMC Chip Select Registers” on page 189). The value of TDF indicates the number of data float wait cycles (between 0 and 15) to be inserted and represents the time allowed for the data output to go to high impedance after the memory is disabled. 164 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Data float wait states do not delay internal memory accesses. Hence, a single access to an external memory with long t DF w ill not slow down the execution of a program from internal memory. To ensure that the external memory system is not accessed while it is still busy, the SMC keeps track of the programmed external data float time during internal accesses. Internal memory accesses and consecutive read accesses to the same external memory do not add data float wait states. Figure 18-16. Data Float Output Delay MCK A[25:0] NCS NRD (1) (2) tDF D[15:0] Notes: 1. Early Read Protocol 2. Standard Read Protocol 18.5.4.4 Chip Select Change Wait State A chip select wait state is automatically inserted when consecutive accesses are made to two different external memories (if no other type of wait state has already been inserted). If a wait state has already been inserted (e.g., data float wait state), then no more wait states are added. 165 1768G–ATARM–29-Sep-06 Figure 18-17. Chip Select Wait State Mem 1 MCK Chip Select Wait Mem 2 A[25:0] addr Mem 1 addr Mem 2 NCS1 NCS2 NRD (1) (2) NWE Notes: 1. Early Read Protocol 2. Standard Read Protocol 18.5.4.5 Early Read Wait State In early read protocol, an early read wait state is automatically inserted when an external write cycle is followed by a read cycle to allow time for the write cycle to end before the subsequent read cycle begins (see Figure 18-18). This wait state is generated in addition to any other programmed wait states (i.e., data float wait state). No wait state is added when a read cycle is followed by a write cycle, between consecutive accesses of the same type, or between external and internal memory accesses. Figure 18-18. Early Read Wait States Write Cycle MCK Early Read Wait Read Cycle A[25:0] NCS NRD NWE D[15:0] 166 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 18.5.5 Setup and Hold Cycles The SMC allows some memory devices to be interfaced with different setup, hold and pulse delays. These parameters are programmable and define the timing of each portion of the read and write cycles. However, it is not possible to use this feature in early read protocol. If an attempt is made to program the setup parameter as not equal to zero and the hold parameter as equal to zero with WSEN = 0 (0 standard wait state), the SMC does not operate correctly. If consecutive accesses are made to two different external memories and the second memory is programmed with setup cycles, then no chip select change wait state is inserted (see Figure 1823 on page 169). When a data float wait state (tDF) is programmed on the first memory bank and when the second memory bank is programmed with setup cycles, the SMC behaves as follows: • If the number of tDF is higher or equal to the number of setup cycles, the number of setup cycles inserted is equal to 0 (see Figure 18-24 on page 169). • If the number of the setup cycle is higher than the number of tDF, the number of tDF inserted is 0 (see Figure 18-25 on page 170). 18.5.5.1 Read Access The read cycle can be divided into a setup, a pulse length and a hold. The setup parameter can have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0 and 7 clock cycles and the pulse length between 1.5 and 128.5 clock cycles, by increments of one. Figure 18-19. Read Access with Setup and Hold MCK A[25:0] NRD NRD Setup Pulse Length NRD Hold Figure 18-20. Read Access with Setup MCK A[25:0] NRD NRD Setup Pulse Length 167 1768G–ATARM–29-Sep-06 18.5.5.2 Write Access The write cycle can be divided into a setup, a pulse length and a hold. The setup parameter can have a value between 1.5 and 7.5 clock cycles, the hold parameter between 0.5 and 7 clock cycles and the pulse length between 1 and 128 clock cycles by increments of one. Figure 18-21. Write Access with Setup and Hold MCK A[25:0] NWE D[15:0] NWR Setup Pulse Length NWR Hold Figure 18-22. Write Access with Setup MCK A[25:0] NWE D[15:0] NWR Setup Pulse Length NWR Hold 168 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 18.5.5.3 Data Float Wait States with Setup Cycles Figure 18-23. Consecutive Accesses with Setup Programmed on the Second Access Setup MCK A[25:0] NCS1 NCS2 NWE NRD Figure 18-24. First Access with Data Float Wait States (TDF = 2) and Second Access with Setup (NRDSETUP = 1) Setup MCK A[25:0] NCS1 NCS2 NRD D[15:0] Data Float Time 169 1768G–ATARM–29-Sep-06 Figure 18-25. First Access with Data Float Wait States (TDF = 2) and Second Access with Setup (NRDSETUP = 3) Setup MCK A[25:0] NCS1 NCS2 NRD D[15:0] Data Float Time 18.5.6 LCD Interface Mode The SMC can be configured to work with an external liquid crystal display (LCD) controller by setting the ACSS (Address to Chip Select Setup) bit in the SMC_CSR registers ( 18.6.1 ”SMC Chip Select Registers” on page 189). In LCD mode, NCS is shortened by one/two/three clock cycles at the leading and trailing edges, providing positive address setup and hold. For read accesses, the data is latched in the SMC when NCS is raised at the end of the access. Additionally, WSEN must be set and NWS programmed with a value of two or more superior to ACSS. In LCD mode, it is not recommended to use RWHOLD or RWSETUP. If the above conditions are not satisfied, SMC does not operate correctly. 170 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-26. Read Access in LCD Interface Mode MCK A[25:0] NRD NCS ACSS ACSS Data from LCD Controller ACSS = 3, NWEN = 1, NWS = 10 Figure 18-27. Write Access in LCD Interface Mode MCK A[25:0] NWE NCS ACCS D[15:0] ACCS = 2, NWEN = 1, NWS = 10 ACCS 18.5.7 18.5.7.1 Memory Access Waveforms Read Accesses in Standard and Early Protocols Figure 18-28 on page 172 through Figure 18-31 on page 175 show examples of the alternatives for external memory read protocol. 171 1768G–ATARM–29-Sep-06 Figure 18-28. Standard Read Protocol without tDF Read Mem 1 Write Mem 1 Read Mem 1 Read Mem 2 Write Mem 2 Read Mem 2 MCK A[25:0] NRD NWE NCS1 Chip Select Change Wait NCS2 D[15:0] (Mem 1) D[15:0] (to write) tWHDX D[15:0] (Mem 2) tWHDX 172 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-29. Early Read Protocol without tDF Read Mem 1 MCK Write Mem 1 Early Read Wait Cycle Read Mem 1 Read Mem 2 Write Mem 2 Early Read Wait Cycle Read Mem 2 A[25:0] NRD NWE NCS1 Chip Select Change Wait NCS2 D[15:0] (Mem 1) D[15:0] (to write) tWHDX D[15:0] (Mem 2) Long tWHDX 173 1768G–ATARM–29-Sep-06 Figure 18-30. Standard Read Protocol with tDF Read Mem 1 Data Float Wait MCK Write Mem 1 Read Mem 1 Data Float Wait Read Mem 2 Read Mem 2 Data Float Wait Write Mem 2 Write Mem 2 A[25:0] NRD NWE NCS1 NCS2 tDF D[15:0] (Mem 1) D[15:0] (to write) tWHDX D[15:0] (Mem 2) tDF (tDF = 2) (tDF = 1) tDF (tDF = 1) 174 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-31. Early Read Protocol with tDF Read Mem 1 Data Float Wait Write Mem 1 Early Read Wait Read Mem 1 Data Float Wait Read Mem 2 Read Mem 2 Data Float Wait Write Mem 2 Write Mem 2 MCK A[25:0] NRD NWE NCS1 NCS2 tDF D[15:0] (Mem 1) D[15:0] (to write) tDF (tDF = 2) D[15:0] (Mem 2) tDF 18.5.7.2 Accesses with Setup and Hold Figure 18-32 and Figure 18-33 show an example of read and write accesses with Setup and Hold Cycles. 175 1768G–ATARM–29-Sep-06 Figure 18-32. Read Accesses in Standard Read Protocol with Setup and Hold(1) MCK A[25:1] 00d2b 00028 00d2c A0/NLB NRD/NOE NWR0/NWE NWR1/NUB Setup NCS Hold Setup Hold D[15:0] e59f ZZ01 ZZ02 Note: 1. Read access memory data bus width = 8, RWSETUP = 1, RWHOLD = 1,WSEN= 1, NWS = 0 Figure 18-33. Write Accesses with Setup and Hold(1) MCK A[25:1] 008cb 00082 008cc A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NCS D[15:0] 3000 e3a0 0605 0606 Setup Hold Setup Hold Note: 1. Write access, memory data bus width = 8, RWSETUP = 1, RWHOLD = 1, WSEN = 1, NWS = 0 176 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 18.5.7.3 Accesses Using NWAIT Input Signal Figure 18-34 on page 177 through Figure 18-37 on page 180 show examples of accesses using NWAIT. Figure 18-34. Write Access using NWAIT in Byte Select Type Access(1) Chip Select Wait MCK NWAIT NWAIT internally synchronized A[25:1] NRD/NOE NWR0/NWE A0/NLB NWR1/NUB NCS 000008A D[15:0] 1312 Wait Delay Falling from NWR0/NWE Note: 1. Write access memory, data bus width = 16 bits, WSEN = 1, NWS = 6 177 1768G–ATARM–29-Sep-06 Figure 18-35. Write Access using NWAIT in Byte Write Type Access(1) Chip Select Wait MCK NWAIT NWAIT internally synchronized A[25:1] 000008C A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NCS D[15:0] 1716 Wait Delay Falling from NWR0/NWE/NWR1/NUB Note: 1. Write access memory, data bus width = 16 bits, WSEN = 1, NWS = 5 178 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-36. Write Access using NWAIT(1) Chip Select Wait MCK NWAIT NWAIT internally synchronized A[25:1] 0000033 A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NCS D[15:0] 0403 Wait Delay Falling from NWR0/NWE Note: 1. Write access memory, data bus width = 8 bits, WSEN = 1, NWS = 4 179 1768G–ATARM–29-Sep-06 Figure 18-37. Read Access in Standard Protocol using NWAIT(1) MCK NWAIT NWAIT internally synchronized A[25:1] 0002C44 A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NCS D[15:0] 0003 Wait Delay Falling from NRD/NOE Note: 1. Read access, memory data bus width = 16, NWS = 5, WSEN = 1 18.5.7.4 Memory Access Example Waveforms Figure 18-38 on page 181 through Figure 18-44 on page 187 show the waveforms for read and write accesses to the various associated external memory devices. The configurations described are shown in Table 18-3. Table 18-3. Memory Access Waveforms Number of Wait States 0 1 1 0 1 1 0 Bus Width 16 16 16 8 8 8 16 Size of Data Transfer Word Word Half-word Word Half-word Byte Byte Figure Number Figure 18-38 Figure 18-39 Figure 18-40 Figure 18-41 Figure 18-42 Figure 18-43 Figure 18-44 180 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-38. 0 Wait State, 16-bit Bus Width, Word Transfer MCK A[25:1] addr addr+1 NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] B2B1 B 4 B3 · Early Read Protocol NRD D[15:0] B2 B1 B4 B3 Write Access · Byte Write/ Byte Select Option NWE D[15:0] B 2 B1 B 4 B3 181 1768G–ATARM–29-Sep-06 Figure 18-39. 1 Wait State, 16-bit Bus Width, Word Transfer 1 Wait State MCK 1 Wait State A[25:1] addr addr+1 NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] B2 B1 B4 B3 · Early Read Protocol NRD D[15:0] B2B1 B4B3 Write Access · Byte Write/ Byte Select Option NWE D[15:0] B2B1 B4B3 182 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-40. 1 Wait State, 16-bit Bus Width, Half-Word Transfer 1 Wait State MCK A[25:1] NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] B2 B1 · Early Read Protocol NRD D[15:0] Write Access B2 B1 · Byte Write/ Byte Select Option NWE D[15:0] B2 B1 183 1768G–ATARM–29-Sep-06 Figure 18-41. 0 Wait State, 8-bit Bus Width, Word Transfer MCK A[25:0] addr addr+1 addr+2 addr+3 NCS Read Access · Standard Read Protocol NRD D[15:0] X B1 X B2 X B3 X B4 · Early Read Protocol NRD D[15:0] X B1 X B2 X B3 X B4 Write Access NWR0 NWR1 D[15:0] X B1 X B2 X B3 X B4 184 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-42. 1 Wait State, 8-bit Bus Width, Half-Word Transfer 1 Wait State MCK 1 Wait State A[25:0] Addr Addr+1 NCS Read Access · Standard Read, Protocol NRD D[15:0] X B1 X B2 · Early Read Protocol NRD D[15:0] Write Access X B1 X B2 NWR0 NWR1 D[15:0] X B1 X B2 185 1768G–ATARM–29-Sep-06 Figure 18-43. 1 Wait State, 8-bit Bus Width, Byte Transfer 1 Wait State MCK A[25:0] NCS Read Access · Standard Read Protocol NRD D[15:0] XB1 · Early Read Protocol NRD D[15:0] Write Access X B1 NWR0 NWR1 D[15:0] X B1 186 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-44. 0 Wait State, 16-bit Bus Width, Byte Transfer MCK A[25:1] addr X X X 0 addr X X X 0 Internal Address Bus addr X X X 0 addr X X X 1 NCS NLB NUB Read Access · Standard Read Protocol NRD D[15:0] X B1 B2X · Early Read Protocol NRD D[15:0] Write Access XB1 B2X · Byte Write Option NWR0 NWR1 D[15:0] B1B1 B2B2 · Byte Select Option NWE 187 1768G–ATARM–29-Sep-06 18.6 Static Memory Controller (SMC) User Interface The Static Memory Controller is programmed using the registers listed in Table 18-4. Eight Chip Select Registers (SMC_CSR0 to SMC_CSR7) are used to program the parameters for the individual external memories. Table 18-4. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Static Memory Controller Register Mapping Register SMC Chip Select Register 0 SMC Chip Select Register 1 SMC Chip Select Register 2 SMC Chip Select Register 3 SMC Chip Select Register 4 SMC Chip Select Register 5 SMC Chip Select Register 6 SMC Chip Select Register 7 Name SMC_CSR0 SMC_CSR1 SMC_CSR2 SMC_CSR3 SMC_CSR4 SMC_CSR5 SMC_CSR6 SMC_CSR7 Access Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Reset State 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 0x00002000 188 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 18.6.1 SMC Chip Select Registers SMC_CSR0..SMC_CSR7 Read/Write See Table 18-4 on page 188 30 29 RWHOLD 21 – 13 DBW 6 5 28 27 – 19 – 11 26 25 RWSETUP 17 ACSS 9 TDF 3 NWS 2 1 0 8 24 Register Name: Access Type: Reset Value: 31 – 23 – 15 DRP 7 WSEN 22 – 14 20 – 12 BAT 4 18 – 10 16 • NWS: Number of Wait States This field defines the Read and Write signal pulse length from 1 cycle up to 128 cycles. Note: When WSEN is 0, NWS will be read to 0 whichever the previous programmed value should be. • WSEN: Wait State Enable 0: Wait states are disabled. 1: Wait states are enabled. • TDF: Data Float Time The external bus is marked occupied and cannot be used by another chip select during TDF cycles. Up to 15 cycles can be defined. • BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. 0: Chip select line is connected to two 8-bit wide devices or four 8-bit wide devices. 1: Chip select line is connected to a 16-bit wide device. • DBW: Data Bus Width DBW 0 0 1 1 0 1 0 1 Data Bus Width Reserved 16-bit 8-bit Reserved • DRP: Data Read Protocol 0: Standard Read Protocol is used. 1: Early Read Protocol is used. 189 1768G–ATARM–29-Sep-06 • ACSS: Address to Chip Select Setup ACSS 0 0 1 1 0 1 0 1 Chip Select Waveform Standard, asserted at the beginning of the access and deasserted at the end. One cycle less at the beginning and the end of the access. Two cycles less at the beginning and the end of the access. Three cycles less at the beginning and the end of the access. • RWSETUP: Read and Write Signal Setup Time See definition and description below. • RWHOLD: Read and Write Signal Hold Time See definition and description below RWSETUP 0 0 0 0 1 1 1 1 Notes: 0 0 1 1 0 0 1 0 1 0 1 0 1 0 NRD Setup ½ cycle(1)or 0 cycles(2) 1 + ½ cycles 2 + ½ cycles 3 + ½ cycles 4 + ½ cycles 5 + ½ cycles 6 + ½ cycles NWR Setup ½ cycle 1 + ½ cycles 2 + ½ cycles 3 + ½ cycles 4 + ½ cycles 5 + ½ cycles 6 + ½ cycles 0 0 0 0 1 1 1 RWHOLD 0 0 1 1 0 0 1 0 1 0 1 0 1 0 NRD Hold 0 1 cycles 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles NWR Hold ½ cycle 1 cycle 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 1 1 7 + ½ cycles 7 + ½ cycles 1 1 1 7 cycles 1. In Standard Read Protocol. 2. In Early Read Protocol. (It is not possible to use the parameters RWSETUP or RWHOLD in this mode.) NWS(2) 0 1 NRD Pulse Length 1 + ½ cycles 2 + ½ cycles NWR Pulse Length 1 cycles 2 cycles Notes: Up to X = 127 X + 1+ ½ cycles X + 1 cycle 1. For a visual description, please refer to ”Setup and Hold Cycles” on page 167 and the diagrams in Figure 18-45 , Figure 1846 and Figure 18-47 on page 191. 2. WSEN is considered to be 1. 190 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 18-45. Read/Write Setup MCK A[25:0] NRD/NOE NWE RWSETUP Figure 18-46. Read Hold MCK A[25:0] NRD/NOE RWHOLD Figure 18-47. Write Hold MCK A[25:0] NWE D[15:0] RWHOLD 191 1768G–ATARM–29-Sep-06 192 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19. SDRAM Controller (SDRAMC) 19.1 Overview The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAM Controller supports a read or write burst length of one location. It does not support byte Read/Write bursts or half-word write bursts. It keeps track of the active row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in one bank and data in the other banks. So as to optimize performance, it is advisable to avoid accessing different rows in the same bank. Features of the SDRAMC are: • Numerous Configurations Supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with Two or Four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming Facilities – Word, Half-word, Byte Access – Automatic Page Break When Memory Boundary Has Been Reached – Multibank Ping-pong Access – Timing Parameters Specified by Software – Automatic Refresh Operation, Refresh Rate is Programmable • Energy-saving Capabilities – Self-refresh and Low-power Modes Supported • Error Detection – Refresh Error Interrupt • SDRAM Power-up Initialization by Software • Latency is Set to Two Clocks (CAS Latency of 1, 3 Not Supported) • Auto Precharge Command Not Used 193 1768G–ATARM–29-Sep-06 19.2 Block Diagram Figure 19-1. SDRAM Controller Block Diagram SDRAMC SDRAMC Chip Select Memory Controller SDRAMC Interrupt PIO Controller SDCK SDCKE SDCS BA[1:0] RAS PMC MCK CAS SDWE NBS[3:0] A[12:0] D[31:0] User Interface APB 19.3 Name SDCK I/O Lines Description I/O Line Description Description SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select Signals Row Signal Column Signal SDRAM Write Enable Data Mask Enable Signals Address Bus Data Bus Type Output Output Output Output Output Output Output Output Output I/O Low Low Low Low High Low Active Level Table 19-1. SDCKE SDCS BA[1:0] RAS CAS SDWE NBS[3:0] A[12:0] D[31:0] 194 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.4 Software Interface The SDRAM Controller’s function is to make the SDRAM device access protocol transparent to the user. Table 19-2 to Table 19-7 illustrate the SDRAM device memory mapping therefore seen by the user in correlation with the device structure. Various configurations are illustrated. 19.4.1 32-bit Memory Data Bus Width SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 19-2. Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[10:0] Row[10:0] Row[10:0] Row[10:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M[1:0] M[1:0] M[1:0] M[1:0] Table 19-3. 27 26 25 SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[11:0] Row[11:0] Row[11:0] Row[11:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M[1:0] M[1:0] M[1:0] M[1:0] Table 19-4. 27 26 25 SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Bk[1:0] Bk[1:0] Bk[1:0] Row[12:0] Row[12:0] Row[12:0] Row[12:0] Column[7:0] Column[8:0] Column[9:0] Column[10:0] M[1:0] M[1:0] M[1:0] M[1:0] Notes: 1. M[1:0] is the byte address inside a 32-bit word. 2. Bk[1] = BA1, Bk[0] = BA0. 195 1768G–ATARM–29-Sep-06 19.4.2 16-bit Memory Data Bus Width SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns CPU Address Line 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 19-5. 27 26 25 Bk[1:0] Row[10:0] Column[7:0] M 0 M 0 M 0 M 0 Bk[1:0] Row[10:0] Column[8:0] Bk[1:0] Row[10:0] Column[9:0] Bk[1:0] Row[10:0] Column[10:0] Table 19-6. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[11:0] Column[7:0] M 0 M 0 M 0 M 0 Bk[1:0] Row[11:0] Column[8:0] Bk[1:0] Row[11:0] Column[9:0] Bk[1:0] Row[11:0] Column[10:0] Table 19-7. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns CPU Address Line 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bk[1:0] Row[12:0] Column[7:0] M 0 M 0 M 0 M 0 Bk[1:0] Row[12:0] Column[8:0] Bk[1:0] Row[12:0] Column[9:0] Bk[1:0] Row[12:0] Column[10:0] Notes: 1. M0 is the byte address inside a 16-bit half-word. 2. Bk[1] = BA1, Bk[0] = BA0. 196 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.5 19.5.1 Product Dependencies SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. A minimum pause of 200 µs is provided to precede any signal toggle. 2. An All Banks Precharge command is issued to the SDRAM devices. 3. Eight auto-refresh (CBR) cycles are provided. 4. A mode register set (MRS) cycle is issued to program the parameters of the SDRAM devices, in particular CAS latency and burst length. 5. A Normal Mode command is provided, 3 clocks after tMRD is met. 6. Write refresh rate into the count field in the SDRAMC Refresh Timer register. (Refresh rate = delay between refresh cycles). After these six steps, the SDRAM devices are fully functional. The commands (NOP, MRS, CBR, normal mode) are generated by programming the command field in the SDRAMC Mode register Figure 19-2. SDRAM Device Initialization Sequence SDCKE SDCK tRP tRC tMRD A[9:0] A10 A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 µsec Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command 19.5.2 I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their 197 1768G–ATARM–29-Sep-06 peripheral function. If I/O lines of the SDRAM Controller are not used by the application, they can be used for other purposes by the PIO Controller. 19.5.3 Interrupt The SDRAM Controller interrupt (Refresh Error notification) is connected to the Memory Controller. This interrupt may be ORed with other System Peripheral interrupt lines and is finally provided as the System Interrupt Source (Source 1) to the AIC (Advanced Interrupt Controller). Using the SDRAM Controller interrupt requires the AIC to be programmed first. 198 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.6 19.6.1 Functional Description SDRAM Controller Write Cycle The SDRAM Controller allows burst access or single access. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential write access, writing to the SDRAM device is carried out. If the next access is a write-sequential access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a write command. To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (t RP ) commands and active/write (tRCD) commands. For definition of these timing parameters, refer to the Section 19.7.3 ”SDRAMC Configuration Register” on page 208. This is described in Figure 19-3 below. Figure 19-3. Write Burst, 32-bit SDRAM Access tRCD = 3 SDCS SDCK A[12:0] Row n col a col b col c col d col e col f col g col h col i col j col k col l RAS CAS SDWE D[31:0] D na Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl 199 1768G–ATARM–29-Sep-06 19.6.2 SDRAM Controller Read Cycle The SDRAM Controller allows burst access or single access. To initiate a burst access, the SDRAM Controller uses the transfer type signal provided by the master requesting the access. If the next access is a sequential read access, reading to the SDRAM device is carried out. If the next access is a sequential read access, but the current access is to a boundary page, or if the next access is in another row, then the SDRAM Controller generates a precharge command, activates the new row and initiates a read command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (t RP ) command and the active/read (tRCD) command, After a read command, additional wait states are generated to comply with cas latency. The SDRAM Controller supports a cas latency of two. For definition of these timing parameters, refer to 19.7.3 ”SDRAMC Configuration Register” on page 208. This is described in Figure 19-4 below. Figure 19-4. Read Burst, 32-bit SDRAM access tRCD = 3 SDCS CAS = 2 SDCK A[12:0] Row n col a col b col c col d col e col f RAS CAS SDWE D[31:0] (Input) D na Dnb Dnc Dnd Dne Dnf 200 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.6.3 Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command. To comply with SDRAM timing parameters, an additional clock cycle is inserted between the precharge/active (tRP) command and the active/read (tRCD) command. This is described in Figure 19-5 below. Figure 19-5. Read Burst with Boundary Row Access TRP = 3 SDCS TRCD = 3 CAS = 3 SDCK Row n A[12:0] col a c ol b col c col d Row m col a col b col c col d col e RAS CAS SDWE D[31:0] Dna Dnb Dnc Dnd Dma Dmb Dmc Dmd Dme 201 1768G–ATARM–29-Sep-06 19.6.4 SDRAM Controller Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. A timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles. A refresh error interrupt is generated when the previous auto-refresh command did not perform. It will be acknowledged by reading the Interrupt Status Register (SDRAMC_ISR). When the SDRAM Controller initiates a refresh of the SDRAM device, internal memory accesses are not delayed. However, if the CPU tries to access the SDRAM, the slave will indicate that the device is busy and the ARM BWAIT signal will be asserted. See Figure 19-6 below. Figure 19-6. Refresh Cycle Followed by a Read Access tRP = 3 SDCS tRC = 8 tRCD = 3 CAS = 2 SDCK Row n A[12:0] col c col d R ow m col a RAS CAS SDWE D[31:0] (input) Dnb Dnc Dnd D ma 202 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.6.5 19.6.5.1 Power Management Self-refresh Mode Self-refresh mode is used in power-down mode, i.e., when no access to the SDRAM device is possible. In this case, power consumption is very low. The mode is activated by programming the self-refresh command bit (SRCB) in SDRAMC_SRR. In self-refresh mode, the SDRAM device retains data without external clocking and provides its own internal clocking, thus performing its own auto-refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE, which remains low. As soon as the SDRAM device is selected, the SDRAM Controller provides a sequence of commands and exits self-refresh mode, so the self-refresh command bit is disabled. To re-activate this mode, the self-refresh command bit must be re-programmed. The SDRAM device must remain in self-refresh mode for a minimum period of tRAS and may remain in self-refresh mode for an indefinite period. This is described in Figure 19-7 below. Figure 19-7. Self-refresh Mode Behavior Self Refresh Mode SRCB = 1 Write SDRAMC_SRR A[12:0] Row TXSR = 3 SDCK SDCKE SDCS RAS CAS SDWE Access Request to the SDRAM Controller 203 1768G–ATARM–29-Sep-06 19.6.5.2 Low-power Mode Low-power mode is used in power-down mode, i.e., when no access to the SDRAM device is possible. In this mode, power consumption is greater than in self-refresh mode. This state is similar to normal mode (No low-power mode/No self-refresh mode), but the SDCKE pin is low and the input and output buffers are deactivated as soon as the SDRAM device is no longer accessible. In contrast to self-refresh mode, the SDRAM device cannot remain in low-power mode longer than the refresh period (64 ms for a whole device refresh operation). As no auto-refresh operations are performed in this mode, the SDRAM Controller carries out the refresh operation. In order to exit low-power mode, a NOP command is required. The exit procedure is faster than in self-refresh mode. When self-refresh mode is enabled, it is recommended to avoid enabling low-power mode. When low-power mode is enabled, it is recommended to avoid enabling self-refresh mode. This is described in Figure 19-8 below. Figure 19-8. Low-power Mode Behavior TRCD = 3 SDCS CAS = 2 Low Power Mode SDCK A[12:0] Row n col a col b col c col d col e col f RAS CAS SDCKE D[31:0] (input) D na Dnb Dnc Dnd Dne Dnf 204 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.7 SDRAM Controller (SDRAMC) User Interface SDRAM Controller Memory Map Register SDRAMC Mode Register SDRAMC Refresh Timer Register SDRAMC Configuration Register SDRAMC Self Refresh Register SDRAMC Low Power Register SDRAMC Interrupt Enable Register SDRAMC Interrupt Disable Register SDRAMC Interrupt Mask Register SDRAMC Interrupt Status Register Name SDRAMC_MR SDRAMC_TR SDRAMC_CR SDRAMC_SRR SDRAMC_LPR SDRAMC_IER SDRAMC_IDR SDRAMC_IMR SDRAMC_ISR Access Read/Write Read/Write Read/Write Write-only Read/Write Write-only Write-only Read-only Read-only Reset State 0x00000010 0x00000800 0x2A99C140 – 0x0 – – 0x0 0x0 Table 19-8. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 205 1768G–ATARM–29-Sep-06 19.7.1 SDRAMC Mode Register SDRAMC_MR Read/Write 0x00000010 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 DBW 27 – 19 – 11 – 3 26 – 18 – 10 – 2 MODE 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Register Name: Access Type: Reset Value: 31 – 23 – 15 – 7 – • MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. MODE 0 0 0 0 0 0 0 0 1 0 1 0 Description Normal mode. Any access to the SDRAM is decoded normally. The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. The SDRAM Controller issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of the cycle. The SDRAM Controller issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the cycle. The address offset with respect to the SDRAM device base address is used to program the Mode Register. For instance, when this mode is activated, an access to the “SDRAM_Base + offset” address generates a “Load Mode Register” command with the value “offset” written to the SDRAM device Mode Register. The SDRAM Controller issues a “Refresh” Command when the SDRAM device is accessed regardless of the cycle. Previously, an “All Banks Precharge” command must be issued. 0 0 1 1 0 1 0 0 • DBW: Data Bus Width 0: Data bus width is 32 bits. 1: Data bus width is 16 bits. 206 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.7.2 SDRAMC Refresh Timer Register SDRAMC_TR Read/Write 0x00000800 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 COUNT 27 – 19 – 11 26 – 18 – 10 COUNT 3 2 1 0 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: Reset Value: 31 – 23 – 15 – 7 • COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated. The value to be loaded depends on the SDRAMC clock frequency (MCK: Master Clock), the refresh rate of the SDRAM device and the refresh burst length where 15.6 µs per row is a typical value for a burst of length one. To refresh the SDRAM device even if the reset value is not equal to 0, this 12-bit field must be written. If this condition is not satisfied, no refresh command is issued and no refresh of the SDRAM device is carried out. 207 1768G–ATARM–29-Sep-06 19.7.3 SDRAMC Configuration Register SDRAMC_CR Read/Write 0x2A99C140 30 29 TXSR 22 21 TRCD 14 13 TRC 6 CAS 5 4 NB 3 NR 2 12 11 10 20 19 18 28 27 26 25 TRAS 17 TRP 9 TWR 1 NC 24 Register Name: Access Type: Reset Value: 31 – 23 TRAS 15 TRP 7 TWR 16 8 0 • NC: Number of Column Bits Reset value is 8 column bits. NC 0 0 1 1 0 1 0 1 Column Bits 8 9 10 11 • NR: Number of Row Bits Reset value is 11 row bits. NR 0 0 1 1 0 1 0 1 Row Bits 11 12 13 Reserved • NB: Number of Banks Reset value is two banks. NB 0 1 Number of Banks 2 4 • CAS: CAS Latency Reset value is two cycles. 208 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 In the SDRAMC, only a CAS latency of two cycles is managed. In any case, another value must be programmed. CAS 0 0 1 1 0 1 0 1 CAS Latency (Cycles) Reserved Reserved 2 Reserved • TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 2 and 15. If TWR is less than or equal to 2, two clock periods are inserted by default. • TRC: Row Cycle Delay Reset value is eight cycles. This field defines the delay between a Refresh and an Activate Command in number of cycles. Number of cycles is between 2 and 15. If TRC is less than or equal to 2, two clock periods are inserted by default. • TRP: Row Precharge Delay Reset value is three cycles. This field defines the delay between a Precharge Command and another Command in number of cycles. Number of cycles is between 2 and 15. If TRP is less than or equal to 2, two clock periods are inserted by default. • TRCD: Row to Column Delay Reset value is three cycles. This field defines the delay between an Activate Command and a Read/Write Command in number of cycles. Number of cycles is between 2 and 15. If TRCD is less than or equal to 2, two clock periods are inserted by default. • TRAS: Active to Precharge Delay Reset value is five cycles. This field defines the delay between an Activate Command and a Precharge Command in number of cycles. Number of cycles is between 2 and 15. If TRAS is less than or equal to 2, two clock periods are inserted by default. • TXSR: Exit Self Refresh to Active Delay Reset value is five cycles. This field defines the delay between SCKE set high and an Activate Command in number of cycles. Number of cycles is between 1/2 and 15.5. If TXSR is equal to 0, 1/2 clock period is inserted by default. 209 1768G–ATARM–29-Sep-06 19.7.4 SDRAMC Self-refresh Register SDRAMC_SRR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 SRCB Register Name: Access Type: 31 – 23 – 15 – 7 – • SRCB: Self-refresh Command Bit 0: No effect. 1: The SDRAM Controller issues a self-refresh command to the SDRAM device, the SDCK clock is inactivated and the SDCKE signal is set low. The SDRAM device leaves self-refresh mode when accessed again. 19.7.5 SDRAMC Low-power Register SDRAMC_LPR Read/Write 0x0 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 LPCB Register Name: Access Type: Reset Value: 31 – 23 – 15 – 7 – • LPCB: Low-power Command Bit 0: The SDRAM Controller low-power feature is inhibited: no low-power command is issued to the SDRAM device. 1: The SDRAM Controller issues a low-power command to the SDRAM device after each burst access, the SDCKE signal is set low. The SDRAM device will leave low-power mode when accessed and enter it after the access. 210 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.7.6 SDRAMC Interrupt Enable Register SDRAMC_IER Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RES Register Name: Access Type: 31 – 23 – 15 – 7 – • RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt. 19.7.7 SDRAMC Interrupt Disable Register SDRAMC_IDR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RES Register Name: Access Type: 31 – 23 – 15 – 7 – • RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt. 211 1768G–ATARM–29-Sep-06 19.7.8 SDRAMC Interrupt Mask Register SDRAMC_IMR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RES Register Name: Access Type: 31 – 23 – 15 – 7 – • RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled. 212 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 19.7.9 SDRAMC Interrupt Status Register SDRAMC_ISR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RES Register Name: Access Type: 31 – 23 – 15 – 7 – • RES: Refresh Error Status 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read. 213 1768G–ATARM–29-Sep-06 214 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 20. Burst Flash Controller (BFC) 20.1 Overview The Burst Flash Controller (BFC) provides an interface for external 16-bit Burst Flash devices and handles an address space of 256M bytes. It supports byte, half-word and word aligned accesses and can access up to 32M bytes of Burst Flash devices. The BFC also supports data bus and address bus multiplexing. The Burst Flash interface supports only continuous burst reads. Programmable burst lengths of four or eight words are not possible. The BFC never generates an abort signal, regardless of the requested address within the 256M bytes of address space. The BFC can operate with two burst read protocols depending on whether or not the address increment of the Burst Flash device is signal controlled. The Burst Flash Controller Mode Register (BFC_MR) located in the BFC user interface is used in programming Asynchronous or Burst Operating Modes. In Burst Mode, the read protocol, Clock Controlled Address Advance, automatically increments the address at each clock cycle. Whereas in Signal Controlled Address Advance protocol the address is incremented only when the Burst Address Advance signal is active. When Address and Data Bus Multiplexing Mode is chosen, the sixteen lowest address bits are multiplexed with the data bus. The BFC clock speed is programmable to be either master clock or master clock divided by 2 or 4. Page size handling (16 bytes to 1024 bytes) is required by some Burst Flash devices unable to handle continuous burst read. The number of latency cycles after address valid goes up to sixteen cycles. The number of latency cycles after output enable runs between one and three cycles. The Burst Flash Controller can also be programmed to suspend and maintain the current burst. This attribute gives other devices the possibility to share the BFC busses without any loss of efficiency. In Burst Mode, the BFC can restart a sequential access without any additional latency. Features of the Burst Flash Controller are: • Multiple Access Modes Supported – Asynchronous or Burst Mode Byte, Half-word or Word Read Accesses – Asynchronous Mode Half-word Write Accesses • Adaptability to Different Device Speed Grades – Programmable Burst Flash Clock Rate – Programmable Data Access Time – Programmable Latency after Output Enable • Adaptability to Different Device Access Protocols and Bus Interfaces – Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled Address Advance – Multiplexed or Separate Address and Data Busses – Continuous Burst and Page Mode Accesses Supported 215 1768G–ATARM–29-Sep-06 20.2 Block Diagram Figure 20-1. Burst Flash Controller Block Diagram BFC Memory Controller BFC Chip Select PIO Controller BFCK BFCS BFAVD BFBAA BFOE PMC MCK BFWE BFRDY A[24:0] D[15:0] User Interface APB 20.3 I/O Lines Description I/O Lines Description Description Burst Flash Clock Burst Flash Chip Select Burst Flash Address Valid Burst Flash Address Advance Burst Flash Output Enable Burst Flash Write Enable Burst Flash Ready Address Bus Data Bus Type Output Output Output Output Output Output Input Output I/O Low Low Low Low Low High Active Level Table 20-1. Name BFCK BFCS BFAVD BFBAA BFOE BFWE BFRDY A[24:0] D[15:0] 216 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 20.4 20.4.1 Application Example Burst Flash Interface The Burst Flash Interface provides control, address and data signals to the Burst Flash Memory. These signals are detailed in Section 20.6 ”Functional Description” on page 218 which describes the BFC functionality and operating modes. Figure 20-2 below presents an illustration of the possible connections of the BFC to some popular Burst Flash Memories. Figure 20-2. Burst Flash Controller Connection Example Burst Flash Burst Flash BFC [D0:D15] [A0:A22] BFCK BFAVD BFCS BFOE BFWE BFRDY [D0:D15] [A0:A22] clk avd/adv ce oe we rdy/wait BFC [D0:D15] [A16:A21] BFCK BFAVD BFCS BFOE BFWE BFRDY [AD0:AD15] [A16:A21] clk avd ce oe we rdy Clock Controlled Address Advance Multiplexed Bus Disabled Clock Controlled Address Advance Multiplexed Bus Enabled Burst Flash BFC [D0:D15] [A0:A19] BFCK BFCS BFAVD BFBAA BFOE BFWE BFRDY [D0:D15] [A0:A19] clk ce avd/lba baa oe we rdy/ind BFC [D0:D15] [A16:A19] BFCK BFCS BFAVD BFBAA BFOE BFWE BFRDY Burst Flash [AD0:AD15] [A16:A19] clk ce avd baa oe we rdy Signal Controlled Address Advance Multiplexed Bus Disabled Signal Controlled Address Advance Multiplexed Bus Enabled 217 1768G–ATARM–29-Sep-06 20.5 20.5.1 Product Dependencies I/O Lines The pins used for interfacing the Burst Flash Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the Burst Flash Controller pins to their peripheral function. If I/O lines of the Burst Flash Controller are not used by the application, they can be used for other purposes by the PIO Controller. 20.6 Functional Description The Burst Flash Controller drives the following signals: • Address Valid (BFAVD), to latch the addresses • Clock (BFCK), to supply the burst clock • Burst Advance Address (BFBAA), to control the Burst Flash memory address advance when programmed to operate in signal controlled burst advance • Write Enable (BFWE), to write to the Burst Flash device • Output Enable (BFOE), to enable the external device data drive on the data bus When enabled, the BFC also drives the address bus, the data bus and the Chip Select (BFCS) line. The Ready Signal (BFRDY) is taken as an input and used as an indicator for the next data availability. 20.6.1 Burst Flash Controller Reset State After reset, the BFC is disabled and, therefore, must be enabled by programming the field BFCOM. (See “Burst Flash Controller Mode Register” on page 227) At this time, the Burst Flash Controller operates in Asynchronous Mode. The Burst Flash memory can be programmed by writing and reading in Asynchronous Mode. 20.6.2 Burst Flash Controller Clock Selection The BFC clock rate is programmable to be either Master Clock, Master Clock divided by 2 or Master Clock divided by 4. The clock selection is necessary in Burst Mode as well as in Asynchronous Mode. The latency fields in the mode register and all burst Flash control signal waveforms are related to the Burst Flash Clock (BFCK) period. The BFC clock rate is selected by the BFCC field. ”Burst Flash Controller Mode Register” on page 227 Figure 20-3. Burst Flash Clock Rates MCK BFC Clock BFCC = 1 MCK BFC Clock BFCC = 2 MCK BFC Clock BFCC = 3 20.6.3 Burst Flash Controller Asynchronous Mode In Asynchronous Mode, the Burst Flash Controller clock is off. The BFCK signal is driven low. 218 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 The BFC performs read access to bytes (8-bits), half-words (16-bits), and words (32-bits). In the last case, the BFC autonomously transforms the word read request into two separate half-word reads. This is fully transparent to the user. The BFC performs only half-word write requests. Write requests for bytes or words are ignored by the BFC. For any access in the address space, the address is driven on the address bus while a pulse is driven on the BFAVD signal (see Figure 20-4 on page 220, and Figure 20-5 on page 221). The Burst Flash address is also driven on the data bus if the multiplexed data and address bus options are enabled. (Figure 20-4 on page 220). • For write access, the signal BFWE is asserted in the following BFCK clock cycle. • For read access, the signal BFOE is asserted one cycle later. This additional cycle in read accesses has been inserted to switch the I/O pad direction so as to avoid conflict on the Burst Flash data bus when address and data busses are multiplexed. The Address Valid Latency (AVL) determines the length of the pulses as a number of Master Clock cycles. The AVL field (See “Burst Flash Controller Mode Register” on page 227) is coded as the Address Valid Latency minus 1. Waveforms in Figure 20-4 on page 220 and Figure 20-5 on page 221 show the AVL field definition in read and write accesses. • In read access, the access finishes with the rising edge of BFOE. • In write access, data and address lines are released one half cycle after the rising edge of BFWE. After a read access to the Burst Flash, it takes Output Enable Latency (OEL) cycles for the Burst Flash device to release the data bus. The OEL field (See “Burst Flash Controller Mode Register” on page 227) gives the OEL expressed in BFCK Clock cycles. This prevents other memory controllers from using the Data Bus until it is released by the Burst Flash device. In Figure 20-4 on page 220 (multiplexed address and data busses), one idle cycle (OEL = 1) is inserted between the read and write accesses. The Burst Flash device must release the data bus before the BFC can drive the address. As shown in Figure 20-5 on page 221, where busses are not multiplexed, the write access can start as soon as the read access ends. In the same way, the OEL has no impact when a read follows a write access. Waveforms in Figure 20-4 on page 220 below and Figure 20-5 on page 221 are related to the Burst Flash Controller Clock even though the BFCK pin is driven low in Asynchronous Mode. The BFCC field (See “Burst Flash Controller Mode Register” on page 227)is used as a measure of the burst Flash speed and must also be programmed in Asynchronous Mode. 219 1768G–ATARM–29-Sep-06 Figure 20-4. Asynchronous Read and Write Accesses with Multiplexed Address and Data Buses BFCS BFCK A[24:0] Read Address Write Address BFAVD AVL BFOE AVL BFWE D[15:0] Output D[15:0] Input Read Address Write Address Data Data OEL = 1 Asynchronous Read Access Asynchronous Write Access Address Valid Latency = 4 BFCK cycles (AVL field = 3) Output Enable Latency (OEL) = 1 BFCK cycle 220 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 20-5. Asynchronous Read and Write Accesses with Non-multiplexed Address and Data BFCS BFCK A[24:0] Read Address Write Address BFAVD AVL BFOE AVL BFWE D[15:0] Output D[15:0] Input Data Data OEL = 1 Asynchronous Read Access Asynchronous Write Access Address Valid Latency = 4 BFCK cycles (AVL field = 3) Output Enable Latency (OEL) = 1 BFCK cycle 20.6.4 Burst Flash Controller Synchronous Mode Writing the Burst Flash Controller Operating Mode field (BFCOM) to 2 (See “Burst Flash Controller Mode Register” on page 227) puts the BFC in Burst Mode. The BFC Clock is driven on the BFCK pin. Only read accesses are treated and write accesses are ignored. The BFC supports read access of bytes, half-words or words. 20.6.4.1 Burst Read Protocols The BFC supports two burst read protocols: • Clock Controlled Address Advance, the internal address of the burst Flash is automatically incremented at each BFCK cycle. • Signal Controlled Address Advance, the internal address of the burst Flash is incremented only when the BFBAA signal is active. 20.6.4.2 Read Access in Burst Mode When a read access is requested in Burst Mode, the requested address is registered in the BFC. For subsequent read accesses, the address is compared to the previous one. Then the two following cases are considered: 1. In case of a non-sequential access, the current burst is broken and the BFC launches a new burst by performing an address latch cycle. The address is presented on the address bus in any case and on the data bus if the multiplexed bus option is enabled. 221 1768G–ATARM–29-Sep-06 This new address is registered in the BFC and is then used as reference for further accesses. 2. In case of sequential access, and provided that the BFOEH mode is selected in the mode register (See “Burst Flash Controller Mode Register” on page 227), the internal burst address is incremented: – Through the BFBAA pin, if the Signal Controlled Address Advance is enabled. – By enabling the clock during one clock cycle in Clock Controlled Address Advance Mode. These protocols are illustrated in Figure 20-6 below and Figure 20-7 on page 223. The Address Valid Latency AVL+1 (See “Burst Flash Controller Mode Register” on page 227) gives the number of cycles from the first rising clock edge when BFAVD is asserted to the rising edge that causes the read of data D1. Note: This rising edge is also used to latch D0 in the BFC. Figure 20-6. Burst Suspend and Resume with Signal Control Address Advance BFCS Internal BFC Selection Signal BFCK A[24:0] Address (D0) BFAVD AVL BFOE BFWE Burst Suspend BFBAA Burst Resume OEL = 2 D[15:0] Output D[15:0] Input Address (1) D0 D1 D2 D3 D4 D4 D5 D6 D0 Sampling D2 Sampling D3 Sampling D5 Sampling D4 Sampling D1 Sampling Burst Suspend and Resume (BFOEH = 1) Signal Control Address Advance (BAAEN = 1) (1) Only if Multiplexed Address & Data Buses Address Valid Latency = 4 BFCK cycles (AVL field = 3) Output Enable Latency (OEL) = 2 BFCK cycles 222 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 20-7. Burst Suspend and Resume with Clock Control Address Advance BFCS Burst Suspend Burst Resume Internal BFC Selection Signal BFCK A[24:0] Address (D0) BFAVD AVL BFOE OEL = 2 BFWE D[15:0] Output D[15:0] Input Address (1) D0 D1 D2 D3 D4 D4 D5 D6 D0 Sampling D2 Sampling D3 Sampling D5 Sampling D4 Sampling Address Valid Latency = 4 BFCK cycles (AVL = 3) Output Enable Latency (OEL) = 2 BFCK cycles D1 Sampling Burst Suspend and Resume (BFOEH = 1) Clock Control Address Advance (BAAEN = 0) (1) Only if Multiplexed Address & Data Buses 20.6.4.3 Burst Suspension for Transfer Enabling The BFC can suspend a burst to enable other internal transfers, or other memory controllers to use the memory address and data busses if they are shared. Two modes are provided on the BFOEH bit (Burst Flash Output Enable Handling, (See “Burst Flash Controller Mode Register” on page 227)): • BFOEH = 1: the BFC suspends the burst when it is no longer selected and the BFOE pin is deasserted. When a new sequential access on the Burst Flash device is requested, the burst is resumed and the BFOE pin is asserted again. The data is available on the data bus after OEL cycles. This mode provides a minimal access latency. (Refer to Figure 20-6 on page 222 and Figure 20-7 above). • BFOEH = 0: the BFC suspends the burst when it is no longer selected and the BFOE pin is deasserted. When a new access to the Burst Flash device is requested, either sequential or not, a new burst is initialized and the next data is available as defined by the AVL latency field in the Mode Register. This mode is provided for Burst Flash devices for which the deassertion of the BFOE signal causes an irreversible break of the burst. Figure 20-8 on page 224 shows the access request to the BFC and the deassertion of the BFOE signal due to a deselection 223 1768G–ATARM–29-Sep-06 of the BFC (Suspend). When the BFC is requested again, a new burst is started even though the requested address is sequential to the previously requested address. Figure 20-8. Burst Flash Controller with No Burst Enable Handling Internal Clock (2) Internal Address Bus A0 A1 Burst Suspend Internal BFC Selection Signal A2 Begin New Burst A3 BFCS BFCK A[24:0] Address (D0) Address (D2) BFAVD AVL BFOE BFWE D[15:0] Output D[15:0] Input OEL = 1 AVL Address (1) Address (1) D0 D1 D2 D2 D3 D4 BFBAA D0 Sampling D1 Sampling (1) Only if Multiplexed Address & Data Busses (2) Master Clock Mode (BFCC =1) Address Valid Latency = 4 BFCK cycles Output Enable Latency (OEL) = 1 BFCK cycle D3 Sampling D2 Sampling No Burst Output Enable Handling (BFOEH = 0) Signal Control Advance Address (BAAEN = 1) 20.6.4.4 Continuous Burst Reads The BFC performs continuous burst reads. It is also possible to program page sizes from 16 bytes up to 1024 bytes. This is done by setting the appropriate value in the PAGES field of the ”Burst Flash Controller Mode Register” on page 227. Page Mode 224 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 In Page Mode, the BFC stops the current burst and starts a new burst each time the requested address matches a page boundary. Figure 20-9 on page 225 illustrates a 16-byte page size. Data D0 to D10 belong to two separate pages and are accessed through two burst accesses. This mode is provided for Burst Flash devices that cannot handle continuous burst read (in which case, a continuous burst access to address D0 would cause the Burst Flash internal address to wrap around address D0). Page Mode can be disabled by programming a null value in the PAGES field of the ”Burst Flash Controller Mode Register” on page 227. Figure 20-9. Burst Read in Page Mode 16-byte Page Boundary BFCS (1) BFCK A[24:0] ….. Address (D0) Address (D8) BFAVD AVL BFOE AVL (1) BFWE D[15:0] Output D[15:0] Input D0 D1 ….. D6 D7 D0 D8 D9 D10 BFBAA D0 Sampling 16-byte Page D7 Sampling D8 (1) Sampling 16-byte Page (8 Accesses of 2 Bytes Each) Address Valid Latency = 3 BFCK cycles (AVL field = 2) Output Enable Latency (OEL) = 1 BFCK cycle Page Size = 16 Bytes (8 Accesses of 2 Bytes Each) Burst Read in Page Mode (16 Bytes) Signal Control Advance Address (BAAEN = 1) (1) A New Page Begins at D8 Ready Enable Mode In Ready Enable Mode (bit RDYEN in the ”Burst Flash Controller Mode Register” on page 227), the BFC uses the Ready Signal (BFRDY) from the burst Flash device as an indicator of the next data availability. The BFRDY signal must be asserted one BFCK cycle before data is valid. In Figure 20-10 on page 226 below, the BFRDY signal indicates on edge (A) that the expected D4 data will not be available on the next rising BFCK edge. The BFRDY signal remains low until rising at edge (B). D4 is then sampled on edge (C). 225 1768G–ATARM–29-Sep-06 When the RDYEN mode is disabled (RDYEN = 0), the BFRDY signal at the BFC input interface is ignored. This mode is provided for Burst Flash devices that do not handle the BFRDY signal. Figure 20-10. Burst Read Using BFRDY Signal (A) BFCS (B) (C) BFCK A[24:0] Address (D0) BFAVD AVL BFOE D[15:0] Input BFBAA D0 D1 D2 D3 D4 D5 D6 D7 BFRDY Sampling D0 D1 D2 D3 D4 D5 D6 D7 Burst Read Signal Control Advance Address (BAAEN = 1) Address Valid Latency = 4 BFCK cycles (AVL field = 3) Output Enable Latency (OEL) = 1 BFCK cycle 226 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 20.7 20.7.1 Burst Flash Controller (BFC) User Interface Burst Flash Controller Mode Register BFC_MR Read/Write : 30 – 22 – 14 – 6 AVL 29 – 21 – 13 OEL 5 4 3 BFCC 2 Register Name: Access Type: Reset Value 31 – 23 – 15 – 7 0x0 28 – 20 – 12 27 – 19 RDYEN 11 26 – 18 MUXEN 10 25 – 17 BFOEH 9 PAGES 1 BFCOM 24 – 16 BAAEN 8 0 • BFCOM: Burst Flash Controller Operating Mode BFCOM 0 0 1 1 0 1 0 1 BFC Operating Mode Disabled. Asynchronous Burst Read Reserved • BFCC: Burst Flash Controller Clock BFCC 0 0 1 1 0 1 0 1 BFC Clock Reserved Master Clock Master Clock divided by 2 Master Clock divided by 4 • AVL: Address Valid Latency The Address Valid Latency is defined as the number of BFC Clock Cycles from the first BFCK rising edge when BFAVD is asserted to the BFCK rising edge that samples read data. The Latency is equal to AVL + 1. 227 1768G–ATARM–29-Sep-06 • PAGES: Page Size This field defines the page size handling and the page size. Pages 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Page Size No page handling. The Ready Signal (BFRDY) is sampled to check if the next data is available. 16 bytes page size 32 bytes page size 64 bytes page size 128 bytes page size 256 bytes page size 512 bytes page size 1024 bytes page size • OEL: Output Enable Latency This field defines the number of idle cycles inserted after each level change on the BFOE output enable signal. OEL range is 1 to 3. • BAAEN: Burst Address Advance Enable 0: The burst clock is enabled to increment the burst address or, disabled to remain at the same address. 1: The burst clock is continuous and the burst address advance is controlled with the BFBAA pin. • BFOEH: Burst Flash Output Enable Handling 0: No burst resume in Burst Mode. When the BFC is deselected, this causes an irreversible break of the burst. A new burst will be initiated for the next access. 1: Burst resume. When the BFC is deselected, the burst is suspended. It will be resumed if the next access is sequential to the last one. • MUXEN: Multiplexed Bus Enable 0: The address and data busses operate independently. 1: The address and data busses are multiplexed. Actually, the address is presented on both the data bus and the address bus when the BFAVD signal is asserted. • RDYEN: Ready Enable Mode 0: The BFRDY input signal at the BFC input interface is ignored. 1: The BFRDY input signal is used as an indicator of data availability in the next cycle. 228 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 21. Peripheral DMA Controller (PDC) 21.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals such as the UART, USART, SSC, SPI, MCI and the on- and off-chip memories. Using the Peripheral DMA Controller avoids processor intervention and removes the processor interrupt-handling overhead.This significantly reduces the number of clock cycles required for a data transfer and, as a result, improves the performance of the microcontroller and makes it more power efficient. The PDC channels are implemented in pairs, each pair being dedicated to a particular peripheral. One channel in the pair is dedicated to the receiving channel and one to the transmitting channel of each UART, USART, SSC and SPI. The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains: • A 32-bit memory pointer register • A 16-bit transfer count register • A 32-bit register for next memory pointer • A 16-bit register for next transfer count The peripheral triggers PDC transfers using transmit and receive signals. When the programmed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral. Important features of the PDC are: • Generates Transfers to/from Peripherals Such as DBGU, USART, SSC, SPI and MCI • Supports Up to Twenty Channels (Product Dependent) • One Master Clock Cycle Needed for a Transfer from Memory to Peripheral • Two Master Clock Cycles Needed for a Transfer from Peripheral to Memory 21.2 Block Diagram Figure 21-1. Block Diagram Peripheral Peripheral DMA Controller THR PDC Channel 0 RHR PDC Channel 1 Control Memory Controller Control Status & Control 229 1768G–ATARM–29-Sep-06 21.3 21.3.1 Functional Description Configuration The PDC channels user interface enables the user to configure and control the data transfers for each channel. The user interface of a PDC channel is integrated into the user interface of the peripheral (offset 0x100), which it is related to. Per peripheral, it contains four 32-bit Pointer Registers (RPR, RNPR, TPR, and TNPR) and four 16-bit Counter Registers (RCR, RNCR, TCR, and TNCR). The size of the buffer (number of transfers) is configured in an internal 16-bit transfer counter register, and it is possible, at any moment, to read the number of transfers left for each channel. The memory base address is configured in a 32-bit memory pointer by defining the location of the first address to access in the memory. It is possible, at any moment, to read the location in memory of the next transfer and the number of remaining transfers. The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/RXTDIS in PDC Transfer Control Register. These control bits enable reading the pointer and counter registers safely without any risk of their changing between both reads. The PDC sends status flags to the peripheral visible in its status-register (ENDRX, ENDTX, RXBUFF, and TXBUFE). ENDRX flag is set when the PERIPH_RCR register reaches zero. RXBUFF flag is set when both PERIPH_RCR and PERIPH_RNCR reach zero. ENDTX flag is set when the PERIPH_TCR register reaches zero. TXBUFE flag is set when both PERIPH_TCR and PERIPH_TNCR reach zero. These status flags are described in the peripheral status register. 21.3.2 Memory Pointers Each peripheral is connected to the PDC by a receiver data channel and a transmitter data channel. Each channel has an internal 32-bit memory pointer. Each memory pointer points to a location anywhere in the memory space (on-chip memory or external bus interface memory). Depending on the type of transfer (byte, half-word or word), the memory pointer is incremented by 1, 2 or 4, respectively for peripheral transfers. If a memory pointer is reprogrammed while the PDC is in operation, the transfer address is changed, and the PDC performs transfers using the new address. 21.3.3 Transfer Counters There is one internal 16-bit transfer counter for each channel used to count the size of the block already transferred by its associated channel. These counters are decremented after each data transfer. When the counter reaches zero, the transfer is complete and the PDC stops transferring data. If the Next Counter Register is equal to zero, the PDC disables the trigger while activating the related peripheral end flag. 230 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 If the counter is reprogrammed while the PDC is operating, the number of transfers is updated and the PDC counts transfers from the new value. Programming the Next Counter/Pointer registers chains the buffers. The counters are decremented after each data transfer as stated above, but when the transfer counter reaches zero, the values of the Next Counter/Pointer are loaded into the Counter/Pointer registers in order to re-enable the triggers. For each channel, two status bits indicate the end of the current buffer (ENDRX, ENTX) and the end of both current and next buffer (RXBUFF, TXBUFE). These bits are directly mapped to the peripheral status register and can trigger an interrupt request to the AIC. The peripheral end flag is automatically cleared when one of the counter-registers (Counter or Next Counter Register) is written. Note: When the Next Counter Register is loaded into the Counter Register, it is set to zero. 21.3.4 Data Transfers The peripheral triggers PDC transfers using transmit (TXRDY) and receive (RXRDY) signals. When the peripheral receives an external character, it sends a Receive Ready signal to the PDC which then requests access to the system bus. When access is granted, the PDC starts a read of the peripheral Receive Holding Register (RHR) and then triggers a write in the memory. After each transfer, the relevant PDC memory pointer is incremented and the number of transfers left is decremented. When the memory block size is reached, a signal is sent to the peripheral and the transfer stops. The same procedure is followed, in reverse, for transmit transfers. 21.3.5 Priority of PDC Transfer Requests The Peripheral DMA Controller handles prioritized transfer requests from the channel. If simultaneous requests of the same type (receiver or transmitter) occur on identical peripherals, the priority is determined by the numbering of the peripherals. If transfer requests are not simultaneous, they are treated in the order they occurred. Requests from the receivers are handled first and then followed by transmitter requests. 231 1768G–ATARM–29-Sep-06 21.4 Peripheral DMA Controller (PDC) User Interface Peripheral DMA Controller (PDC) Register Mapping Register PDC Receive Pointer Register PDC Receive Counter Register PDC Transmit Pointer Register PDC Transmit Counter Register PDC Receive Next Pointer Register PDC Receive Next Counter Register PDC Transmit Next Pointer Register PDC Transmit Next Counter Register PDC Transfer Control Register PDC Transfer Status Register Register Name PERIPH _RPR PERIPH_RCR PERIPH_TPR PERIPH_TCR PERIPH_RNPR PERIPH_RNCR PERIPH_TNPR PERIPH_TNCR PERIPH_PTCR PERIPH_PTSR (1) Table 21-1. Offset 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 Note: Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Write-only Read-only Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 1. PERIPH: Ten registers are mapped in the peripheral memory space at the same offset. These can be defined by the user according to the function and the peripheral desired (DBGU, USART, SSC, SPI, MCI etc). 232 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 21.4.1 PDC Receive Pointer Register PERIPH_RPR Register Name: Access Type: 31 Read/Write 30 29 28 27 26 25 24 RXPTR 23 22 21 20 19 18 17 16 RXPTR 15 14 13 12 11 10 9 8 RXPTR 7 6 5 4 3 2 1 0 RXPTR • RXPTR: Receive Pointer Address Address of the next receive transfer. 21.4.2 PDC Receive Counter Register PERIPH_RCR Register Name: Access Type: 31 Read/Write 30 29 28 27 26 25 24 -23 22 21 20 19 18 17 16 -15 14 13 12 11 10 9 8 RXCTR 7 6 5 4 3 2 1 0 RXCTR • RXCTR: Receive Counter Value Number of receive transfers to be performed. 233 1768G–ATARM–29-Sep-06 21.4.3 PDC Transmit Pointer Register PERIPH_TPR Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 TXPTR 23 22 21 20 19 18 17 16 TXPTR 15 14 13 12 11 10 9 8 TXPTR 7 6 5 4 3 2 1 0 TXPTR • TXPTR: Transmit Pointer Address Address of the transmit buffer. 21.4.4 PDC Transmit Counter Register PERIPH_TCR Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 -23 22 21 20 19 18 17 16 -15 14 13 12 11 10 9 8 TXCTR 7 6 5 4 3 2 1 0 TXCTR • TXCTR: Transmit Counter Value ·TXCTR is the size of the transmit transfer to be performed. At zero, the peripheral DMA transfer is stopped. 234 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 21.4.5 PDC Receive Next Pointer Register PERIPH_RNPR Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 RXNPTR 23 22 21 20 19 18 17 16 RXNPTR 15 14 13 12 11 10 9 8 RXNPTR 7 6 5 4 3 2 1 0 RXNPTR • RXNPTR: Receive Next Pointer Address RXNPTR is the address of the next buffer to fill with received data when the current buffer is full. 21.4.6 PDC Receive Next Counter Register PERIPH_RNCR Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 -23 22 21 20 19 18 17 16 -15 14 13 12 11 10 9 8 RXNCR 7 6 5 4 3 2 1 0 RXNCR • RXNCR: Receive Next Counter Value ·RXNCR is the size of the next buffer to receive. 235 1768G–ATARM–29-Sep-06 21.4.7 PDC Transmit Next Pointer Register PERIPH_TNPR Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 TXNPTR 23 22 21 20 19 18 17 16 TXNPTR 15 14 13 12 11 10 9 8 TXNPTR 7 6 5 4 3 2 1 0 TXNPTR • TXNPTR: Transmit Next Pointer Address TXNPTR is the address of the next buffer to transmit when the current buffer is empty. 21.4.8 PDC Transmit Next Counter Register PERIPH_TNCR Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 -23 22 21 20 19 18 17 16 -15 14 13 12 11 10 9 8 TXNCR 7 6 5 4 3 2 1 0 TXNCR • TXNCR: Transmit Next Counter Value TXNCR is the size of the next buffer to transmit. 236 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 21.4.9 PDC Transfer Control Register PERIPH_PTCR Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXTDIS 1 TXTEN 0 – – – – – – RXTDIS RXTEN • RXTEN: Receiver Transfer Enable 0 = No effect. 1 = Enables the receiver PDC transfer requests if RXTDIS is not set. • RXTDIS: Receiver Transfer Disable 0 = No effect. 1 = Disables the receiver PDC transfer requests. • TXTEN: Transmitter Transfer Enable 0 = No effect. 1 = Enables the transmitter PDC transfer requests. • TXTDIS: Transmitter Transfer Disable 0 = No effect. 1 = Disables the transmitter PDC transfer requests 237 1768G–ATARM–29-Sep-06 21.4.10 PDC Transfer Status Register PERIPH_PTSR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 TXTEN 0 – – – – – – – RXTEN • RXTEN: Receiver Transfer Enable 0 = Receiver PDC transfer requests are disabled. 1 = Receiver PDC transfer requests are enabled. • TXTEN: Transmitter Transfer Enable 0 = Transmitter PDC transfer requests are disabled. 1 = Transmitter PDC transfer requests are enabled. 238 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22. Advanced Interrupt Controller (AIC) 22.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an ARM processor. Inputs of the AIC are either internal peripheral interrupts or external interrupts coming from the product's pins. The 8-level Priority Controller allows the user to define the priority for each interrupt source, thus permitting higher priority interrupts to be serviced even if a lower priority interrupt is being treated. Internal interrupt sources can be programmed to be level sensitive or edge triggered. External interrupt sources can be programmed to be positive-edge or negative-edge triggered or highlevel or low-level sensitive. Important Features of the AIC are: • Controls the Interrupt Lines (nIRQ and nFIQ) of an ARM Processor • Thirty-two Individually Maskable and Vectored Interrupt Sources – Source 0 is Reserved for the Fast Interrupt Input (FIQ) – Source 1 is Reserved for System Peripherals (ST, RTC, PMC, DBGU…) – Source 2 to Source 31 Control up to Thirty Embedded Peripheral Interrupts or External Interrupts – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources • 8-level Priority Controller – Drives the Normal Interrupt of the Processor – Handles Priority of the Interrupt Sources 1 to 31 – Higher Priority Interrupts Can Be Served During Service of Lower Priority Interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per Interrupt Source – Interrupt Vector Register Reads the Corresponding Current Interrupt Vector • Protect Mode – Easy Debugging by Preventing Automatic Operations when Protect ModeIs Are Enabled • General Interrupt Mask – Provides Processor Synchronization on Events Without Triggering an Interrupt 239 1768G–ATARM–29-Sep-06 22.2 Block Diagram Figure 22-1. Block Diagram FIQ IRQ0-IRQn AIC ARM Processor Up to Thirty-two Sources nFIQ nIRQ Embedded PeripheralEE Embedded Peripheral Embedded Peripheral APB 22.3 Application Block Diagram Figure 22-2. Description of the Application Block OS-based Applications Standalone Applications OS Drivers RTOS Drivers Hard Real Time Tasks General OS Interrupt Handler Advanced Interrupt Controller Embedded Peripherals External Peripherals (External Interrupts) 22.4 AIC Detailed Block Diagram Figure 22-3. AIC Detailed Block Diagram Advanced Interrupt Controller FIQ PIO Controller External Source Input Stage Fast Interrupt Controller ARM Processor nFIQ nIRQ IRQ0-IRQn PIOIRQ Internal Source Input Stage Embedded Peripherals User Interface Interrupt Priority Controller Processor Clock Power Management Controller Wake Up APB 240 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22.5 I/O Line Description Table 22-1. Pin Name FIQ IRQ0 - IRQn I/O Line Description Pin Description Fast Interrupt Interrupt 0 - Interrupt n Type Input Input 22.6 22.6.1 Product Dependencies I/O Lines The interrupt signals FIQ and IRQ0 to IRQn are normally multiplexed through the PIO controllers. Depending on the features of the PIO controller used in the product, the pins must be programmed in accordance with their assigned interrupt function. This is not applicable when the PIO controller used in the product is transparent on the input path. 22.6.2 Power Management The Advanced Interrupt Controller is continuously clocked. The Power Management Controller has no effect on the Advanced Interrupt Controller behavior. The assertion of the Advanced Interrupt Controller outputs, either nIRQ or nFIQ, wakes up the ARM processor while it is in Idle Mode. The General Interrupt Mask feature enables the AIC to wake up the processor without asserting the interrupt line of the processor, thus providing synchronization of the processor on an event. 22.6.3 Interrupt Sources The Interrupt Source 0 is always located at FIQ. If the product does not feature an FIQ pin, the Interrupt Source 0 cannot be used. The Interrupt Source 1 is always located at System Interrupt. This is the result of the OR-wiring of the system peripheral interrupt lines, such as the System Timer, the Real Time Clock, the Power Management Controller and the Memory Controller. When a system interrupt occurs, the service routine must first distinguish the cause of the interrupt. This is performed by reading successively the status registers of the above mentioned system peripherals. The interrupt sources 2 to 31 can either be connected to the interrupt outputs of an embedded user peripheral or to external interrupt lines. The external interrupt lines can be connected directly, or through the PIO Controller. The PIO Controllers are considered as user peripherals in the scope of interrupt handling. Accordingly, the PIO Controller interrupt lines are connected to the Interrupt Sources 2 to 31. The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 241 1768G–ATARM–29-Sep-06 22.7 22.7.1 Functional Description Interrupt Source Control Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source. The SRCTYPE field of the corresponding AIC_SMR (Source Mode Register) selects the interrupt condition of each source. The internal interrupt sources wired on the interrupt outputs of the embedded peripherals can be programmed either in level-sensitive mode or in edge-triggered mode. The active level of the internal interrupts is not important for the user. The external interrupt sources can be programmed either in high level-sensitive or low level-sensitive modes, or in positive edge-triggered or negative edge-triggered modes. 22.7.1.1 22.7.1.2 Interrupt Source Enabling Each interrupt source, including the FIQ in source 0, can be enabled or disabled by using the command registers; AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register). This set of registers conducts enabling or disabling in one instruction. The interrupt mask can be read in the AIC_IMR register. A disabled interrupt does not affect servicing of other interrupts. 22.7.1.3 Interrupt Clearing and Setting All interrupt sources programmed to be edge-triggered (including the FIQ in source 0) can be individually set or cleared by writing respectively the AIC_ISCR and AIC_ICCR registers. Clearing or setting interrupt sources programmed in level-sensitive mode has no effect. The clear operation is perfunctory, as the software must perform an action to reinitialize the “memorization” circuitry activated when the source is programmed in edge-triggered mode. However, the set operation is available for auto-test or software debug purposes. It can also be used to execute an AIC-implementation of a software interrupt. The AIC features an automatic clear of the current interrupt when the AIC_IVR (Interrupt Vector Register) is read. Only the interrupt source being detected by the AIC as the current interrupt is affected by this operation. (See Section 22.7.3.1 ”Priority Controller” on page 245.) The automatic clear reduces the operations required by the interrupt service routine entry code to reading the AIC_IVR.) The automatic clear of the interrupt source 0 is performed when AIC_FVR is read. 22.7.1.4 Interrupt Status For each interrupt, the AIC operation originates in AIC_IPR (Interrupt Pending Register) and its mask in AIC_IMR (Interrupt Mask Register). AIC_IPR enables the actual activity of the sources, whether masked or not. The AIC_ISR register reads the number of the current interrupt (See Section 22.7.3.1 ”Priority Controller” on page 245.) and the register AIC_CISR gives an image of the signals nIRQ and nFIQ driven on the processor. Each status referred to above can be used to optimize the interrupt handling of the systems. 242 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22.7.1.5 Internal Interrupt Source Input Stage Figure 22-4. Internal Interrupt Source Input Stage MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 22.7.1.6 External Interrupt Source Input Stage Figure 22-5. External Interrupt Source Input Stage AIC_SMRi SRCTYPE Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Pos./Neg. Edge Detector Set AIC_ISCR AIC_ICCR Clear AIC_IDCR AIC_IECR High/Lo w FF 243 1768G–ATARM–29-Sep-06 22.7.2 Interrupt Latencies Global interrupt latencies depend on several parameters, including: • The time the software masks the interrupts. • Occurrence, either at the processor level or at the AIC level. • The execution time of the instruction in progress when the interrupt occurs. • The treatment of higher priority interrupts and the resynchronization of the hardware signals. This section addresses only the hardware resynchronizations. It gives details of the latency times between the event on an external interrupt leading in a valid interrupt (edge or level) or the assertion of an internal interrupt source and the assertion of the nIRQ or nFIQ line on the processor. The resynchronization time depends on the programming of the interrupt source and on its type (internal or external). For the standard interrupt, resynchronization times are given assuming there is no higher priority in progress. The PIO Controller multiplexing has no effect on the interrupt latencies of the external interrupt sources. 22.7.2.1 External Interrupt Edge Triggered Source Figure 22-6. External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles 22.7.2.2 External Interrupt Level Sensitive Source Figure 22-7. External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles 244 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22.7.2.3 Internal Interrupt Edge Triggered Source Figure 22-8. Internal Interrupt Edge Triggered Source MCK nIRQ Maximum IRQ Latency = 4.5 Cycles Peripheral Interrupt Becomes Active 22.7.2.4 Internal Interrupt Level Sensitive Source Figure 22-9. Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 22.7.3 22.7.3.1 Normal Interrupt Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31. Each interrupt source has a programmable priority level of 7 to 0, which is user-definable by writing the PRIOR field of the corresponding AIC_SMR (Source Mode Register). Level 7 is the highest priority and level 0 the lowest. As soon as an interrupt condition occurs, as defined by the SRCTYPE field of the AIC_SVR (Source Vector Register), the nIRQ line is asserted. As a new interrupt condition might have happened on other interrupt sources since the nIRQ has been asserted, the priority controller determines the current interrupt at the time the AIC_IVR (Interrupt Vector Register) is read. The read of AIC_IVR is the entry point of the interrupt handling which allows the AIC to consider that the interrupt has been taken into account by the software. The current priority level is defined as the priority level of the current interrupt. If several interrupt sources of equal priority are pending and enabled when the AIC_IVR is read, the interrupt with the lowest interrupt source number is serviced first. 245 1768G–ATARM–29-Sep-06 The nIRQ line can be asserted only if an interrupt condition occurs on an interrupt source with a higher priority. If an interrupt condition happens (or is pending) during the interrupt treatment in progress, it is delayed until the software indicates to the AIC the end of the current service by writing the AIC_EOICR (End of Interrupt Command Register). The write of AIC_EOICR is the exit point of the interrupt handling. 22.7.3.2 Interrupt Nesting The priority controller utilizes interrupt nesting in order for the highest priority interrupt to be handled during the service of lower priority interrupts. This requires the interrupt service routines of the lower interrupts to re-enable the interrupt at the processor level. When an interrupt of a higher priority happens during an already occurring interrupt service routine, the nIRQ line is re-asserted. If the interrupt is enabled at the core level, the current execution is interrupted and the new interrupt service routine should read the AIC_IVR. At this time, the current interrupt number and its priority level are pushed into an embedded hardware stack, so that they are saved and restored when the higher priority interrupt servicing is finished and the AIC_EOICR is written. The AIC is equipped with an 8-level wide hardware stack in order to support up to eight interrupt nestings pursuant to having eight priority levels. 22.7.3.3 Interrupt Vectoring The interrupt handler addresses corresponding to each interrupt source can be stored in the registers AIC_SVR1 to AIC_SVR31 (Source Vector Register 1 to 31). When the processor reads AIC_IVR (Interrupt Vector Register), the value written into AIC_SVR corresponding to the current interrupt is returned. This feature offers a way to branch in one single instruction to the handler corresponding to the current interrupt, as AIC_IVR is mapped at the absolute address 0xFFFF F100 and thus accessible from the ARM interrupt vector at address 0x0000 0018 through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction, it loads the read value in AIC_IVR in its program counter, thus branching the execution on the correct interrupt handler. This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring. This can be performed by defining all the AIC_SVR of the interrupt source to be handled by the operating system at the address of its interrupt handler. When doing so, the interrupt vectoring permits a critical interrupt to transfer the execution on a specific very fast handler and not onto the operating system’s general interrupt handler. This facilitates the support of hard real-time tasks (input/outputs of voice/audio buffers and software peripheral handling) to be handled efficiently and independently of the application running under an operating system. 22.7.3.4 Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and the associated status bits. 246 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 It is assumed that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR registers are loaded with corresponding interrupt service routine addresses and interrupts are enabled. 2. The instruction at the ARM interrupt exception vector address is required to work with the vectoring LDR PC, [PC, # -&F20] When nIRQ is asserted, if the bit “I” of CPSR is 0, the sequence is as follows: 1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in the Interrupt link register (R14_irq) and the Program Counter (R15) is loaded with 0x18. In the following cycle during fetch at address 0x1C, the ARM core adjusts R14_irq, decrementing it by four. 2. The ARM core enters Interrupt mode, if it has not already done so. 3. When the instruction loaded at address 0x18 is executed, the program counter is loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects: a. Sets the current interrupt to be the pending and enabled interrupt with the highest priority. The current level is the priority level of the current interrupt. b. c. De-asserts the nIRQ line on the processor. Even if vectoring is not used, AIC_IVR must be read in order to de-assert nIRQ. Automatically clears the interrupt, if it has been programmed to be edge-triggered. d. Pushes the current level and the current interrupt number on to the stack. e. Returns the value written in the AIC_SVR corresponding to the current interrupt. 4. The previous step has the effect of branching to the corresponding interrupt service routine. This should start by saving the link register (R14_irq) and SPSR_IRQ. The link register must be decremented by four when it is saved if it is to be restored directly into the program counter at the end of the interrupt. For example, the instruction SUB PC, LR, #4 may be used. 5. Further interrupts can then be unmasked by clearing the “I” bit in CPSR, allowing reassertion of the nIRQ to be taken into account by the core. This can happen if an interrupt with a higher priority than the current interrupt occurs. 6. The interrupt handler can then proceed as required, saving the registers that will be used and restoring them at the end. During this phase, an interrupt of higher priority than the current level will restart the sequence from step 1. Note: If the interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase. 7. The “I” bit in CPSR must be set in order to mask interrupts before exiting to ensure that the interrupt is completed in an orderly manner. 8. The End of Interrupt Command Register (AIC_EOICR) must be written in order to indicate to the AIC that the current interrupt is finished. This causes the current level to be popped from the stack, restoring the previous current level if one exists on the stack. If another interrupt is pending, with lower or equal priority than the old current level but with higher priority than the new current level, the nIRQ line is re-asserted, but the interrupt sequence does not immediately start because the “I” bit is set in the core. SPSR_irq is restored. Finally, the saved value of the link register is restored directly into the PC. This has effect of returning from the interrupt to whatever was being executed 247 1768G–ATARM–29-Sep-06 before, and of loading the CPSR with the stored SPSR, masking or unmasking the interrupts depending on the state saved in SPSR_irq. Note: The “I” bit in SPSR is significant. If it is set, it indicates that the ARM core was on the verge of masking an interrupt when the mask instruction was interrupted. Hence, when SPSR is restored, the mask instruction is completed (interrupt is masked). 22.7.4 22.7.4.1 Fast Interrupt Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor. The interrupt source 0 is generally connected to an FIQ pin of the product, either directly or through a PIO Controller. 22.7.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller. The mode of interrupt source 0 is programmed with the AIC_SMR0 and the field PRIOR of this register is not used even if it reads what has been written. The field SRCTYPE of AIC_SMR0 enables programming the fast interrupt source to be positive-edge triggered or negative-edge triggered or high-level sensitive or low-level sensitive Writing 0x1 in the AIC_IECR (Interrupt Enable Command Register) and AIC_IDCR (Interrupt Disable Command Register) respectively enables and disables the fast interrupt. The bit 0 of AIC_IMR (Interrupt Mask Register) indicates whether the fast interrupt is enabled or disabled. 22.7.4.3 Fast Interrupt Vectoring The fast interrupt handler address can be stored in AIC_SVR0 (Source Vector Register 0). The value written into this register is returned when the processor reads AIC_FVR (Fast Vector Register). This offers a way to branch in one single instruction to the interrupt handler, as AIC_FVR is mapped at the absolute address 0xFFFF F104 and thus accessible from the ARM fast interrupt vector at address 0x0000 001C through the following instruction: LDR PC,[PC,# -&F20] When the processor executes this instruction it loads the value read in AIC_FVR in its program counter, thus branching the execution on the fast interrupt handler. It also automatically performs the clear of the fast interrupt source if it is programmed in edge-triggered mode. 22.7.4.4 Fast Interrupt Handlers This section gives an overview of the fast interrupt handling sequence when using the AIC. It is assumed that the programmer understands the architecture of the ARM processor, and especially the processor interrupt modes and associated status bits. Assuming that: 1. The Advanced Interrupt Controller has been programmed, AIC_SVR0 is loaded with the fast interrupt service routine address, and the interrupt source 0 is enabled. 2. The Instruction at address 0x1C (FIQ exception vector address) is required to vector the fast interrupt: LDR PC, [PC, # -&F20] 3. The user does not need nested fast interrupts. When nFIQ is asserted if the bit “F” of CPSR is 0, the sequence is: 248 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 1. The CPSR is stored in SPSR_fiq, the current value of the program counter is loaded in the FIQ link register (R14_FIQ) and the program counter (R15) is loaded with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core adjusts R14_fiq, decrementing it by four. 2. The ARM core enters FIQ mode. 3. When the instruction loaded at address 0x1C is executed, the program counter is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of automatically clearing the fast interrupt, if it has been programmed to be edge triggered. In this case only, it de-asserts the nFIQ line on the processor. 4. The previous step enables branching to the corresponding interrupt service routine. It is not necessary to save the link register R14_fiq and SPSR_fiq if nested fast interrupts are not needed. 5. The Interrupt Handler can then proceed as required. It is not necessary to save registers R8 to R13 because FIQ mode has its own dedicated registers and the user R8 to R13 are banked. The other registers, R0 to R7, must be saved before being used, and restored at the end (before the next step). Note that if the fast interrupt is programmed to be level sensitive, the source of the interrupt must be cleared during this phase in order to de-assert the interrupt source 0. 6. Finally, the Link Register R14_fiq is restored into the PC after decrementing it by four (with instruction SUB PC, LR, #4 for example). This has the effect of returning from the interrupt to whatever was being executed before, loading the CPSR with the SPSR and masking or unmasking the fast interrupt depending on the state saved in the SPSR. Note: The “F” bit in SPSR is significant. If it is set, it indicates that the ARM core was just about to mask FIQ interrupts when the mask instruction was interrupted. Hence when the SPSR is restored, the interrupted instruction is completed (FIQ is masked). Another way to handle the fast interrupt is to map the interrupt service routine at the address of the ARM vector 0x1C. This method does not use the vectoring, so that reading AIC_FVR must be performed at the very beginning of the handler operation. However, this method saves the execution of a branch instruction. 22.7.5 Protect Mode The Protect Mode permits reading the Interrupt Vector Register without performing the associated automatic operations. This is necessary when working with a debug system. When a debugger, working either with a Debug Monitor or the ARM processor's ICE, stops the applications and updates the opened windows, it might read the AIC User Interface and thus the IVR. This has undesirable consequences: • If an enabled interrupt with a higher priority than the current one is pending, it is stacked. • If there is no enabled pending interrupt, the spurious vector is returned. In either case, an End of Interrupt command is necessary to acknowledge and to restore the context of the AIC. This operation is generally not performed by the debug system as the debug system would become strongly intrusive and cause the application to enter an undesired state. This is avoided by using the Protect Mode. Writing DBGM in AIC_DCR (Debug Control Register) at 0x1 enables the Protect Mode. When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the 249 1768G–ATARM–29-Sep-06 Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR. Extra AIC_IVR reads perform the same operations. However, it is recommended to not stop the processor between the read and the write of AIC_IVR of the interrupt service routine to make sure the debugger does not modify the AIC context. To summarize, in normal operating mode, the read of AIC_IVR performs the following operations within the AIC: 1. Calculates active interrupt (higher than current or spurious). 2. 2. Determines and returns the vector of the active interrupt. 3. Memorizes the interrupt. 4. Pushes the current priority level onto the internal stack. 5. Acknowledges the interrupt. However, while the Protect Mode is activated, only operations 1 to 3 are performed when AIC_IVR is read. Operations 4 and 5 are only performed by the AIC when AIC_IVR is written. Software that has been written and debugged using the Protect Mode runs correctly in Normal Mode without modification. However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code. 22.7.6 Spurious Interrupt The Advanced Interrupt Controller features protection against spurious interrupts. A spurious interrupt is defined as being the assertion of an interrupt source long enough for the AIC to assert the nIRQ, but no longer present when AIC_IVR is read. This is most prone to occur when: • An external interrupt source is programmed in level-sensitive mode and an active level occurs for only a short time. • An internal interrupt source is programmed in level sensitive and the output signal of the corresponding embedded peripheral is activated for a short time. (As in the case for the Watchdog.) • An interrupt occurs just a few cycles before the software begins to mask it, thus resulting in a pulse on the interrupt source. The AIC detects a spurious interrupt at the time the AIC_IVR is read while no enabled interrupt source is pending. When this happens, the AIC returns the value stored by the programmer in AIC_SPU (Spurious Vector Register). The programmer must store the address of a spurious interrupt handler in AIC_SPU as part of the application, to enable an as fast as possible return to the normal execution flow. This handler writes in AIC_EOICR and performs a return from interrupt. 22.7.7 General Interrupt Mask The AIC features a General Interrupt Mask bit to prevent interrupts from reaching the processor. Both the nIRQ and the nFIQ lines are driven to their inactive state if the bit GMSK in AIC_DCR (Debug Control Register) is set. However, this mask does not prevent waking up the processor if it has entered Idle Mode. This function facilitates synchronizing the processor on a next event and, as soon as the event occurs, performs subsequent operations without having to handle an interrupt. It is strongly recommended to use this mask with caution. 250 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22.8 22.8.1 Advanced Interrupt Controller (AIC) User Interface Base Address The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PC-relative load/store instructions of the ARM processor supports only an ± 4-Kbyte offset. Table 22-2. Offset 0000 0x04 – 0x7C 0x80 0x84 – 0xFC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 Register Mapping Register Source Mode Register 0 Source Mode Register 1 – Source Mode Register 31 Source Vector Register 0 Source Vector Register 1 – Source Vector Register 31 Interrupt Vector Register Fast Interrupt Vector Register Interrupt Status Register Interrupt Pending Register Interrupt Mask Register Core Interrupt Status Register Reserved Reserved Interrupt Enable Command Register Interrupt Disable Command Register Interrupt Clear Command Register Interrupt Set Command Register End of Interrupt Command Register Spurious Interrupt Vector Register Debug Control Register Name AIC_SMR0 AIC_SMR1 – AIC_SMR31 AIC_SVR0 AIC_SVR1 – AIC_SVR31 AIC_IVR AIC_FVR AIC_ISR AIC_IPR AIC_IMR AIC_CISR – – AIC_IECR AIC_IDCR AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU AIC_DCR Access Read/Write Read/Write – Read/Write Read/Write Read/Write – Read/Write Read-only Read-only Read-only Read-only Read-only Read-only – – Write-only Write-only Write-only Write-only Write-only Read/Write Read/Write Reset Value 0x0 0x0 – 0x0 0x0 0x0 – 0x0 0x0 0x0 0x0 0x0(1) 0x0 0x0 – – – – – – – 0x0 0x0 0x13C Reserved – – – Note: 1. The reset value of the Interrupt Pending Register depends on the level of the external interrupt source. All other sources are cleared at reset, thus not pending. 251 1768G–ATARM–29-Sep-06 22.8.2 AIC Source Mode Register AIC_SMR0..AIC_SMR31 Read/Write 0x0 30 – 22 – 14 – 6 SRCTYPE 29 – 21 – 13 – 5 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 25 – 17 – 9 – 1 PRIOR 24 – 16 – 8 – 0 Register Name: Access Type: Reset Value: 31 – 23 – 15 – 7 – • PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest). The priority level is not used for the FIQ in the related SMR register AIC_SMRx. • SRCTYPE: Interrupt Source Type The active level or edge is not programmable for the internal interrupt sources. SRCTYPE 0 0 1 1 0 1 0 1 Internal Interrupt Sources High-level Sensitive Positive-edge Triggered High-level Sensitive Positive-edge Triggered External Interrupt Sources Low-level Sensitive Negative-edge Triggered High-level Sensitive Positive-edge Triggered 252 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22.8.3 AIC Source Vector Register AIC_SVR0..AIC_SVR31 Read/Write 0x0 30 29 28 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: Reset Value: 31 • VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. 22.8.4 AIC Interrupt Vector Register AIC_IVR Read-only 0 30 29 28 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: Reset Value: 31 • IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read. When there is no current interrupt, the Interrupt Vector Register reads the value stored in AIC_SPU. 253 1768G–ATARM–29-Sep-06 22.8.5 AIC FIQ Vector Register AIC_FVR Read-only 0 30 29 28 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: Reset Value: 31 • FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the Fast Interrupt Vector Register reads the value stored in AIC_SPU. 22.8.6 AIC Interrupt Status Register AIC_ISR Read-only 0 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 IRQID 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Register Name: Access Type: Reset Value: 31 – 23 – 15 – 7 – • IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. 254 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22.8.7 AIC Interrupt Pending Register AIC_IPR Read-only 0 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ Register Name: Access Type: Reset Value: 31 PID31 23 PID23 15 PID15 7 PID7 • FIQ, SYS, PID2-PID31: Interrupt Pending 0 = Corresponding interrupt is no pending. 1 = Corresponding interrupt is pending. 22.8.8 AIC Interrupt Mask Register AIC_IMR Read-only 0 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ Register Name: Access Type: Reset Value: 31 PID31 23 PID23 15 PID15 7 PID7 • FIQ, SYS, PID2-PID31: Interrupt Mask 0 = Corresponding interrupt is disabled. 1 = Corresponding interrupt is enabled. 255 1768G–ATARM–29-Sep-06 22.8.9 AIC Core Interrupt Status Register AIC_CISR Read-only 0 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 NIRQ 24 – 16 – 8 – 0 NIFQ Register Name: Access Type: Reset Value: 31 – 23 – 15 – 7 – • NFIQ: NFIQ Status 0 = nFIQ line is deactivated. 1 = nFIQ line is active. • NIRQ: NIRQ Status 0 = nIRQ line is deactivated. 1 = nIRQ line is active. 22.8.10 AIC Interrupt Enable Command Register AIC_IECR Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ Register Name: Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 • FIQ, SYS, PID2-PID3: Interrupt Enable 0 = No effect. 1 = Enables corresponding interrupt. 256 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22.8.11 AIC Interrupt Disable Command Register AIC_IDCR Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ Register Name: Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 • FIQ, SYS, PID2-PID31: Interrupt Disable 0 = No effect. 1 = Disables corresponding interrupt. 22.8.12 AIC Interrupt Clear Command Register AIC_ICCR Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ Register Name: Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 • FIQ, SYS, PID2-PID31: Interrupt Clear 0 = No effect. 1 = Clears corresponding interrupt. 257 1768G–ATARM–29-Sep-06 22.8.13 AIC Interrupt Set Command Register AIC_ISCR Write-only 30 PID30 22 PID22 14 PID14 6 PID6 29 PID29 21 PID21 13 PID13 5 PID5 28 PID28 20 PID20 12 PID12 4 PID4 27 PID27 19 PID19 11 PID11 3 PID3 26 PID26 18 PID18 10 PID10 2 PID2 25 PID25 17 PID17 9 PID9 1 SYS 24 PID24 16 PID16 8 PID8 0 FIQ Register Name: Access Type: 31 PID31 23 PID23 15 PID15 7 PID7 • FIQ, SYS, PID2-PID31: Interrupt Set 0 = No effect. 1 = Sets corresponding interrupt. 22.8.14 AIC End of Interrupt Command Register AIC_EOICR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 – Register Name: Access Type: 31 – 23 – 15 – 7 – The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete. Any value can be written because it is only necessary to make a write to this register location to signal the end of interrupt treatment. 258 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 22.8.15 AIC Spurious Interrupt Vector Register AIC_SPU Read/Write 0 30 29 28 SIQV 23 22 21 20 SIQV 15 14 13 12 SIQV 7 6 5 4 SIQV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: Reset Value: 31 • SIQV: Spurious Interrupt Vector Register The use may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 259 1768G–ATARM–29-Sep-06 22.8.16 AIC Debug Control Register AIC_DEBUG Read/Write 0 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 GMSK 24 – 16 – 8 – 0 PROT Register Name: Access Type: Reset Value: 31 – 23 – 15 – 7 – • PROT: Protection Mode 0 = The Protection Mode is disabled. 1 = The Protection Mode is enabled. • GMSK: General Mask 0 = The nIRQ and nFIQ lines are normally controlled by the AIC. 1 = The nIRQ and nFIQ lines are tied to their inactive state. 260 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23. Power Management Controller (PMC) 23.1 Overview The Power Management Controller (PMC) generates all the clocks of a system thanks to the integration of two oscillators and two PLLs. The PMC provides clocks to the embedded processor and enables the idle mode by stopping the processor clock until the next interrupt. The PMC independently provides and controls up to thirty peripheral clocks and four programmable clocks that can be used as outputs on pins to feed external devices. The integration of the PLLs supplies the USB devices and host ports with a 48 MHz clock, as required by the bus speed, and the rest of the system with a clock at another frequency. Thus, the fully-featured Power Management Controller optimizes power consumption of the whole system and supports the Normal, Idle, Slow Clock and Standby operating modes. The main features of the PMC are: • Optimize the Power Consumption of the Whole System • Embeds and Controls: – One Main Oscillator and One Slow Clock Oscillator (32.768 kHz) – Two Phase Locked Loops (PLLs) and Dividers – Clock Prescalers • Provides: – the Processor Clock PCK – the Master Clock MCK – the USB Clocks, UHPCK and UDPCK, Respectively for the USB Host Port and the USB Device Port – Programmable Automatic PLL Switch-off in USB Device Suspend Conditions – up to Thirty Peripheral Clocks – up to Four Programmable Clock Outputs • Four Operating Modes: – Normal Mode, Idle Mode, Slow Clock Mode, Standby Mode 261 1768G–ATARM–29-Sep-06 23.2 23.2.1 Product Dependencies I/O Lines The Power Management Controller is capable of handling up to four Programmable Clocks, PCK0 to PCK3. A Programmable Clock is generally multiplexed on a PIO Controller. The user must first program the PIO controllers to assign the pins of the Programmable Clock to its peripheral function. 23.2.2 Interrupt The Power Management Controller has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the PMC interrupt requires programming the AIC before configuring the PMC. 23.2.3 Oscillator and PLL Characteristics The electrical characteristics of the embedded oscillators and PLLs are product-dependent, even if the way to control them is similar. All of the parameters for both oscillators and the PLLs are given in the DC Characteristics section of the product datasheet. These figures are used not only for the hardware design, as they affect the external components to be connected to the pins, but also the software configuration, as they determine the waiting time for the startup and lock times to be programmed. 23.2.4 Peripheral Clocks The Power Management Controller provides and controls up to thirty peripheral clocks. The bit number permitting the control of a peripheral clock is the Peripheral ID of the embedded peripheral. When the Peripheral ID does not correspond to a peripheral, either because this is an external interrupt or because there are less than thirty peripherals, the control bits of the Peripheral ID are not implemented in the PMC and programming them has no effect on the behavior of the PMC. 23.2.5 USB Clocks The Power Management Controller provides and controls two USB Clocks, the UHPCK for the USB Host Port, and the UDPCK for the USB Device. If the product does not embed either the USB Host Port or the USB Device Port, the associated control bits and registers are not implemented in the PMC and programming them has no effect on the behavior of the PMC. 262 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.3 Block Diagram Figure 23-1. Power Management Controller Block Diagram Power Management Controller Processor Clock Controller Processor Clock ARM7 Processor Clock Generator XIN32 XOUT32 XIN XOUT PLL and Divider A PLLA Clock SLCK Main Clock PLLA Clock PLLB Clock Slow Clock SLCK Idle Mode Processor Clock ARM920T Processor Slow Clock Oscillator IRQ or FIQ Master Clock Controller Prescaler /2,/4,...,/64 PMCIRQ Divider /1,/2,/3,/4 ARM9-systems only AIC Main Oscillator Main Clock MCK (Continuous) Memory Controller PLLRCA Peripherals Clock Controller PLLRCB PLL and Divider B PLLB Clock ON/OFF 30 MCK (Individually Switchable) Embedded Peripherals UDPCK PLLB Clock USB Clock Controller ON/OFF UDP Suspend UHPCK UHP Programmable Clock Controller SLCK Main Clock PLLA Clock PLLB Clock PCK0-PCK3 Prescaler /2,/4,...,/64 4 Programmable Clocks PIO ST User Interface Slow Clock SLCK SLCK RTC APB 263 1768G–ATARM–29-Sep-06 23.4 23.4.1 Functional Description Operating Modes Definition The following operating modes are supported by the PMC and offer different power consumption levels and event response latency times: • Normal Mode: The ARM processor clock is enabled and peripheral clocks are enabled depending on application requirements. • Idle Mode: The ARM processor clock is disabled and waiting for the next interrupt (or a main reset). The peripheral clocks are enabled depending on application requirements. PDC transfers are still possible. • Slow Clock Mode: Slow clock mode is similar to normal mode, but the main oscillator and the PLL are switched off to save power and the processor and the peripherals run in Slow Clock mode. Note that slow clock mode is the mode selected after the reset. • Standby Mode: Standby mode is a combination of Slow Clock mode and Idle Mode. It enables the processor to respond quickly to a wake-up event by keeping power consumption very low. 23.4.2 Clock Definitions The Power Management Controller provides the following clocks: • Slow Clock (SLCK), typically at 32.768 kHz, is the only permanent clock within the system. • Master Clock (MCK), programmable from a few hundred Hz to the maximum operating frequency of the device. It is available to the modules running permanently, such as the AIC and the Memory Controller. • Processor Clock (PCK), typically the Master Clock for ARM7-based systems and a faster clock on ARM9-based systems, switched off when entering idle mode. • Peripheral Clocks, typically MCK, provided to the embedded peripherals (USART, SSC, SPI, TWI, TC, MCI, etc.) and independently controllable. In order to reduce the number of clock names in a product, the Peripheral Clocks are named MCK in the product datasheet. • UDP Clock (UDPCK), typically at 48 MHz, required by the USB Device Port operations. • UHP Clock (UHPCK), typically at 48 MHz, required by the USB Host Port operations. • Programmable Clock Outputs (PCK0 to PCK3) can be selected from the clocks provided by the clock generator and driven on the PCK0 to PCK3 pins. 23.4.3 Clock Generator The Clock Generator embeds: • the Slow Clock Oscillator • the Main Oscillator • two PLL and divider blocks, A and B The Clock Generator may optionally integrate a divider by 2. The ARM7-based systems generally embed PLLs able to output between 20 MHz and 100 MHz and do not embed the divider by 2. The ARM9-based systems generally embed PLLs able to output between 80 MHz and 240 MHz. As the 48 MHz required by the USB cannot be reached by such a PLL, the optional divider by 2 is implemented. The block diagram of the Clock Generator is shown in Figure 23-2. 264 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 23-2. Clock Generator Block Diagram Clock Generator XIN32 XOUT32 XIN XOUT Main Clock Frequency Counter PLLRCA /2 (optional) Slow Clock Oscillator Slow Clock SLCK Main Oscillator Main Clock Divider A PLL A PLLA Clock Divider B PLL B PLLB Clock PLLRCB 23.4.4 23.4.4.1 Slow Clock Oscillator Slow Clock Oscillator Connection The Clock Generator integrates a low-power 32.768 kHz oscillator. The XIN32 and XOUT32 pins must be connected to a 32.768 kHz crystal. Two external capacitors must be wired as shown in Figure 23-3. Figure 23-3. Typical Slow Clock Oscillator Connection XIN32 32.768 kHz Crystal XOUT32 GNDOSC CL1 CL2 23.4.4.2 Slow Clock Oscillator Startup Time The startup time of the Slow Clock Oscillator is given in the DC Characteristics section of the product datasheet. As it is often higher than 500 ms and the processor requires an assertion of the reset until it has stabilized, the user must implement an external reset supervisor covering this startup time. However, this startup is only required in case of cold reset, i.e., in case of system power-up. When a warm reset occurs, the length of the reset pulse may be much lower. For further details, see Section 15. ”AT91RM9200 Reset Controller” on page 115. 265 1768G–ATARM–29-Sep-06 23.4.5 Main Oscillator Figure 23-4 shows the Main Oscillator block diagram. Figure 23-4. Main Oscillator Block Diagram MOSCEN XIN Main Oscillator XOUT Main Clock OSCOUNT Slow Clock Main Oscillator Counter Main Clock Frequency Counter MOSCS MAINF MAINRDY 23.4.5.1 Main Oscillator Connections The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 23-5. The 1 kΩ resistor is only required for crystals with frequencies lower than 8 MHz. The oscillator contains internal capacitors on each XIN and XOUT pin. For further details on the electrical characteristics of the Main Oscillator, see the section “AT91RM9200 Electrical Characteristics”. Figure 23-5. Typical Crystal Connection XIN XOUT GNDOSC 1K CL1 CL2 23.4.5.2 Main Oscillator Startup Time The startup time of the Main Oscillator is given in the DC Characteristics section of the product datasheet. The startup time depends on the crystal frequency and increases when the frequency rises. 23.4.5.3 Main Oscillator Control To minimize the power required to start up the system, the Main Oscillator is disabled after reset and the Slow Clock mode is selected. 266 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 The software enables or disables the Main Oscillator so as to reduce power consumption by clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR). When disabling the Main Oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit in PMC_SR is automatically cleared indicating the Main Clock is off. When enabling the Main Oscillator, the user must initiate the Main Oscillator counter with a value corresponding to the startup time of the oscillator. This startup time depends on the crystal frequency connected to the main oscillator. When the MOSCEN bit and the OSCOUNT are written in CKGR_MOR to enable the Main Oscillator, the MOSCS bit is cleared and the counter starts counting down on Slow Clock from the OSCOUNT value. Since the OSCOUNT value is coded with 8 bits, the maximum startup time is about 62 ms. When the counter reaches 0, the MOSCS bit is set, indicating that the Main Clock is valid. Setting the MOSCS bit in PMC_IMR can trigger an interrupt to the processor on this event. 23.4.5.4 Main Clock Frequency Counter The Main Oscillator features a Main Clock frequency counter that provides the quartz frequency connected to the Main Oscillator. Generally, this value is known by the system designer; however, it is useful for the boot program to configure the device with the correct clock speed, independently of the application. The Main Clock frequency counter starts incrementing at the Main Clock speed after the next rising edge of the Slow Clock as soon as the Main Oscillator is stable, i.e., as soon as the MOSCS bit is set. Then, at the 16th falling edge of Slow Clock, the bit MAINRDY in CKGR_MCFR (Main Clock Frequency Register) is set and the counter stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can be determined. 23.4.5.5 Main Oscillator Bypass The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the external clock signal on the pin XIN. The input characteristics of the XIN pin under these conditions are given in the product Electrical Characteristics section. The programmer has to be sure not to modify the MOSCEN bit in the Main Oscillator Register (CKGR_MOR). This bit must remain at 0, its reset value, for the external clock to operate properly. While this bit is at 0, the pin XIN is pulled down by a 500 kΩ resistor in parallel with a 40 pF capacitor. The external clock signal must meet the requirements relating to the power supply VDDPLL (i.e., between 1.65V and 1.95V) and cannot exceed 50 MHz. 267 1768G–ATARM–29-Sep-06 23.4.6 Divider and PLL Blocks The Clock Generator features two Divider/PLL Blocks that generates a wide range of frequencies. Additionally, they provide a 48 MHz signal to the embedded USB device and/or host ports, regardless of the frequency of the Main Clock. Figure 23-6 shows the block diagram of the divider and PLL blocks. Figure 23-6. Divider and PLL Blocks Block Diagram DIVB Main Clock MULB OUTB PLL B Output Divider B PLL B PLLRCB DIVA MULA OUTA Divider A PLL A PLL A Output PLLRCA PLLBCOUNT PLL B Counter LOCKB PLLACOUNT Slow Clock PLL A Counter LOCKA 23.4.6.1 PLL Filters The two PLLs require connection to an external second-order filter through the pins PLLRC. Figure 23-7 shows a schematic of these filters. Figure 23-7. PLL Capacitors and Resistors PLLRC PLL R C2 C1 GND 268 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Values of R, C1 and C2 to be connected to the PLLRC pins must be calculated as a function of the PLL input frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal overshoot and startup time. 23.4.6.2 PLL Source Clock The source of PLLs A and B is respectively the output of Divider A, i.e. the Main Clock divided by DIVA, and the output of Divider B, i.e. the Main Clock divided by DIVB. As the input frequency of the PLLs is limited, the user has to make sure that the programming of DIVA and DIVB are compliant with the input frequency range of the PLLs, which is given in the DC Characteristics section of the product datasheet. 23.4.6.3 Divider and Phase Lock Loop Programming The two dividers increase the accuracy of the PLLA and the PLLB clocks independently of the input frequency. The Main Clock can be divided by programming the DIVB field in CKGR_PLLBR and the DIVA field in CKGR_PLLAR. Each divider can be set between 1 and 255 in steps of 1. When the DIVA and DIVB fields are set to 0, the output of the divider and the PLL outputs A and B are a continuous signal at level 0. On reset, the DIVA and DIVB fields are set to 0, thus both PLL input clocks are set to 0. The two PLLs of the clock generator allow multiplication of the divider’s outputs. The PLLA and the PLLB clock signals have a frequency that depends on the respective source signal frequency and on the parameters DIV (DIVA, DIVB) and MUL (MULA, MULB). The factor applied to the source signal frequency is (MUL + 1)/DIV. When MULA or MULB is written to 0, the corresponding PLL is disabled and its power consumption is saved. Re-enabling the PLLA or the PLLB can be performed by writing a value higher than 0 in the MULA or MULB field, respectively. Whenever a PLL is re-enabled or one of its parameters is changed, the LOCKA or LOCKB bit in PMC_SR is automatically cleared. The values written in the PLLACOUNT or PLLBCOUNT fields in CKGR_PPLAR and CKGR_PLLBR, respectively, are loaded in the corresponding PLL counter. The PLL counter then decrements at the speed of the Slow Clock until it reaches 0. At this time, the corresponding LOCK bit is set in PMC_SR and can trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the PLL transient time into the PLLACOUNT and PLLBCOUNT field. The transient time depends on the PLL filters. The initial state of the PLL and its target frequency can be calculated using a specific tool provided by Atmel. 23.4.6.4 PLLB Divider by 2 In ARM9-based systems, the PLLB clock may be divided by two. This divider can be enabled by setting the bit USB_96M of CKGR_PLLBR. In this case, the divider by 2 is enabled and the PLLB must be programmed to output 96 MHz and not 48 MHz, thus ensuring correct operation of the USB bus. 269 1768G–ATARM–29-Sep-06 23.4.7 Clock Controllers The Power Management Controller provides the clocks to the different peripherals of the system, either internal or external. It embeds the following elements: • the Master Clock Controller, which selects the Master Clock. • the Processor Clock Controller, which implements the Idle Mode. • the Peripheral Clock Controller, which provides power saving by controlling clocks of the embedded peripherals. • the USB Clock Controller, which distributes the 48 MHz clock to the USB controllers. • the Programmable Clock Controller, which allows generation of up to four programmable clock signals on external pins. 23.4.7.1 Master Clock Controller The Master Clock Controller provides selection and division of the Master Clock (MCK). MCK is the clock provided to all the peripherals and the memory controller. The Master Clock is selected from one of the clocks provided by the Clock Generator. Selecting the Slow Clock enables Slow Clock Mode by providing a 32.768 kHz signal to the whole device. Selecting the Main Clock saves power consumption of both PLLs, but prevents using the USB ports. Selecting the PLLB Clock saves the power consumption of the PLLA by running the processor and the peripheral at 48 MHz required by the USB ports. Selecting the PLLA Clock runs the processor and the peripherals at their maximum speed while running the USB ports at 48 MHz. The Master Clock Controller is made up of a clock selector and a prescaler, as shown in Figure 23-8. It also contains an optional Master Clock divider in products integrating an ARM9 processor. This allows the processor clock to be faster than the Master Clock. The Master Clock selection is made by writing the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register). The prescaler supports the division by a power of 2 of the selected clock between 1 and 64. The PRES field in PMC_MCKR programs the prescaler. When the Master Clock divider is implemented, it can be programmed between 1 and 4 through the MDIV field in PMC_MCKR. Each time PMC_MCKR is written to define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is established. Then, the MCKRDY bit is set and can trigger an interrupt to the processor. This feature is useful when switching from a high-speed clock to a lower one to inform the software when the change is actually done. Note: A new value to be written in PMC_MCKR must not be the same as the current value in PMC_MCKR. 270 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 23-8. Master Clock Controller MDIV CD SLCK Main Clock PLLA Clock PLLB Clock PRES Master Clock Divider MCK To the Processor Clock Controller Master Clock Prescaler MCK To the Processor Clock Controller ARM9 Products ARM7 Products 23.4.7.2 Processor Clock Controller The PMC features a Processor Clock Controller that implements the Idle Mode. The Processor Clock can be enabled and disabled by writing the System Clock Enable (PMC_SCER) and System Clock Disable Registers (PMC_SCDR). The status of this clock (at least for debug purpose) can be read in the System Clock Status Register (PMC_SCSR). Processor Clock Source The clock provided to the processor is determined by the Master Clock controller. On ARM7based systems, the Processor Clock source is directly the Master Clock. On ARM9-based systems, the Processor Clock source might be 2, 3 or 4 times the Master Clock. This ratio value is determined by programming the field MDIV of the Master Clock Register (PMC_MCKR). Idle Mode The Processor Clock is enabled after a reset and is automatically re-enabled by any enabled interrupt. The Idle Mode is achieved by disabling the Processor Clock, which is automatically reenabled by any enabled fast or normal interrupt, or by the reset of the product. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 23.4.7.3 Peripheral Clock Controller The PMC controls the clocks of each embedded peripheral. The user can individually enable and disable the Master Clock on the peripherals by writing into the Peripheral Clock Enable (PMC_PCER) and Peripheral Clock Disable (PMC_PCDR) registers. The status of the peripheral clock activity can be read in the Peripheral Clock Status Register (PMC_PCSR). When a peripheral clock is disabled, the clock is immediately stopped. When the clock is reenabled, the peripheral resumes action where it left off. The peripheral clocks are automatically disabled after a reset. In order to stop a peripheral, it is recommended that the system software wait until the peripheral has executed its last programmed operation before disabling the clock. This is to avoid data corruption or erroneous behavior of the system. The bit number within the Peripheral Clock Control registers (PMC_PCER, PMC_PCDR, and PMC_PCSR) is the Peripheral Identifier defined at the product level. Generally, the bit number corresponds to the interrupt source number assigned to the peripheral. 271 1768G–ATARM–29-Sep-06 23.4.7.4 USB Clock Controller If using one of the USB ports, the user has to program the Divider and PLL B block to output a 48 MHz signal with an accuracy of ± 0.25%. When the clock for the USB is stable, the USB device and host clocks, UDPCK and UHPCK, can be enabled. They can be disabled when the USB transactions are finished, so that the power consumption generated by the 48 MHz signal on these peripherals is saved. The USB ports require both the 48 MHz signal and the Master Clock. The Master Clock may be controlled via the Peripheral Clock Controller. USB Device Clock Control The USB Device Port clock UDPCK can be enabled by writing 1 at the UDP bit in PMC_SCER (System Clock Enable Register) and disabled by writing 1 at the bit UDP in PMC_SCDR (System Clock Disable Register). The activity of UDPCK is shown in the bit UDP of PMC_SCSR (System Clock Status Register). USB Device Port Suspend When the USB Device Port detects a suspend condition, the 48 MHz clock is automatically disabled, i.e., the UDP bit in PMC_SCSR is cleared. It is also possible to automatically disable the Master Clock provided to the USB Device Port on a suspend condition. The MCKUDP bit in PMC_SCSR configures this feature and can be set or cleared by writing one in the same bit of PMC_SCER and PMC_SCDR. USB Host Clock Control The USB Host Port clock UHPCK can be enabled by writing 1 at the UHP bit in PMC_SCER (System Clock Enable Register) and disabled by writing 1 at the UHP bit in PMC_SCDR (System Clock Disable Register). The activity of UDPCK is shown in the bit UHP of PMC_SCSR (System Clock Status Register). 23.4.7.5 Programmable Clock Output Controller The PMC controls up to four signals to be output on external pins PCK0 to PCK3. Each signal can be independently programmed via the registers PMC_PCK0 to PMC_PCK3. PCK0 to PCK3 can be independently selected between the four clocks provided by the Clock Generator by writing the CSS field in PMC_PCK0 to PMC_PCK3. Each output signal can also be divided by a power of 2 between 1 and 64 by writing the field PRES (Prescaler) in PMC_PCK0 to PMC_PCK3. Each output signal can be enabled and disabled by writing 1 in the corresponding bit PCK0 to PCK3 of PMC_SCER and PMC_SCDR, respectively. Status of the active programmable output clocks are given in the bits PCK0 to PCK3 of PMC_SCSR (System Clock Status Register). Moreover, like the MCK, a status bit in PMC_SR indicates that the Programmable Clock is actually what has been programmed in the Programmable Clock registers. As the Programmable Clock Controller does not manage with glitch prevention when switching clocks, it is strongly recommended to disable the Programmable Clock before any configuration change and to re-enable it after the change is actually performed. Note also that it is required to assign the pin to the Programmable Clock operation in the PIO Controller to enable the signal to be driven on the pin. 272 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.5 23.5.1 Clock Switching Details Master Clock Switching Timings Table 23-1 gives the worst case timing required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 23-1. Clock Switching Timings (Worst Case) From Main Clock SLCK PLLA Clock PLLB Clock To Main Clock – 0.5 x Main Clock + 4.5 x SLCK 0.5 x Main Clock + 4 x SLCK + PLLACOUNT x SLCK + 2.5 x PLLA Clock 0.5 x Main Clock + 4 x SLCK + PLLBCOUNT x SLCK + 2.5 x PLLB Clock 4 x SLCK + 2.5 x Main Clock – 2.5 x PLLA Clock + 5 x SLCK + PLLACOUNT x SLCK 2.5 x PLLB Clock + 5 x SLCK + PLLBCOUNT x SLCK 3 x PLLA Clock + 4 x SLCK + 1 x Main Clock 3 x PLLA Clock + 5 x SLCK 2.5 x PLLA Clock + 4 x SLCK + PLLB COUNT x SLCK 3 x PLLB Clock + 4 x SLCK + 1.5 x PLLB Clock 3 x PLLB Clock + 4 x SLCK + 1 x Main Clock 3 x PLLB Clock + 5 x SLCK 3 x PLLA Clock + 4 x SLCK + 1.5 x PLLA Clock 2.5 x PLLB Clock + 4 x SLCK + PLLACOUNT x SLCK SLCK PLLA Clock PLLB Clock 273 1768G–ATARM–29-Sep-06 23.5.2 Clock Switching Waveforms Figure 23-9. Switch Master Clock from Slow Clock to PLLA Clock Slow Clock PLLA Clock LOCK A MCKRDY Master Clock Write PMC_MCKR Figure 23-10. Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR 274 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 23-11. Change PLLA Programming Slow Clock PLLA Clock LOCKA MCKRDY Master Clock Slow Clock Write CKGR_PLLAR Figure 23-12. Programmable Clock Output Programming PLLA Clock PCKRDY PCKx Output Write PMC_PCKX PLLA Clock is selected Write PMC_SCER PCKx is enabled Write PMC_SCDR PCKx is disabled 275 1768G–ATARM–29-Sep-06 23.6 Power Management Controller (PMC) User Interface Register Mapping Register System Clock Enable Register System Clock Disable Register System Clock Status Register Reserved Peripheral Clock Enable Register Peripheral Clock Disable Register Peripheral Clock Status Register Reserved Main Oscillator Register Main Clock Frequency Register PLL A Register PLL B Register Master Clock Register Reserved Reserved Reserved Programmable Clock 0 Register Programmable Clock 1 Register Programmable Clock 2 Register Programmable Clock 3 Register Reserved Reserved Reserved Reserved Interrupt Enable Register Interrupt Disable Register Status Register Interrupt Mask Register Name PMC_SCER PMC_SCDR PMC _SCSR – PMC _PCER PMC_PCDR PMC_PCSR – CKGR_MOR CKGR_MCFR CKGR_PLLAR CKGR_PLLBR PMC_MCKR – – – PMC_PCK0 PMC_PCK1 PMC_PCK2 PMC_PCK3 – – – – PMC_IER PMC_IDR PMC_SR PMC_IMR Access Write-only Write-only Read-only – Write-only Write-only Read-only – ReadWrite Read-only ReadWrite ReadWrite Read/Write – – – Read/Write Read/Write Read/Write Read/Write – – – – Write-only Write-only Read-only Read-only Reset Value – – 0x01 – – – 0x0 – 0x0 0x3F00 0x3F00 0x00 – – – 0x0 0x0 0x0 0x0 – – – – ---0x0 Table 23-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 276 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.6.1 PMC System Clock Enable Register PMC_SCER Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 PCK3 3 PCK2 2 PCK1 1 PCK0 0 – – – UHP – MCKUDP UDP PCK • PCK: Processor Clock Enable 0 = No effect. 1 = Enables the Processor Clock. • UDP: USB Device Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Device Port. • MCKUDP: USB Device Port Master Clock Automatic Disable on Suspend Enable 0 = No effect. 1 = Enables the automatic disable of the Master Clock of the USB Device Port when a suspend condition occurs. • UHP: USB Host Port Clock Enable 0 = No effect. 1 = Enables the 48 MHz clock of the USB Host Port. • PCK0...PCK3: Programmable Clock Output Enable 0 = No effect. 1 = Enables the corresponding Programmable Clock output. 277 1768G–ATARM–29-Sep-06 23.6.2 PMC System Clock Disable Register PMC_SCDR Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 PCK3 3 PCK2 2 PCK1 1 PCK0 0 – – – UHP – MCKUDP UDP PCK • PCK: Processor Clock Disable 0 = No effect. 1 = Disables the Processor Clock. • UDP: USB Device Port Clock Disable 0 = No effect. 1 = Disables the 48 MHz clock of the USB Device Port. • MCKUDP: USB Device Port Master Clock Automatic Disable on Suspend Disable 0 = No effect. 1 = Disables the automatic disable of the Master Clock of the USB Device Port when a suspend condition occurs. • UHP: USB Host Port Clock Disable 0 = No effect. 1 = Disables the 48 MHz clock of the USB Host Port. • PCK0...PCK3: Programmable Clock Output Disable 0 = No effect. 1 = Disables the corresponding Programmable Clock output. 278 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.6.3 PMC System Clock Status Register PMC_SCSR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 PCK3 3 PCK2 2 PCK1 1 PCK0 0 – – – UHP – MCKUDP UDP PCK • PCK: Processor Clock Status 0 = The Processor Clock is disabled. 1 = The Processor Clock is enabled. • UDP: USB Device Port Clock Status 0 = The 48 MHz clock of the USB Device Port is disabled. 1 = The 48 MHz clock of the USB Device Port is enabled. • MCKUDP: USB Device Port Master Clock Automatic Disable on Suspend Status 0 = The automatic disable of the Master clock of the USB Device Port when suspend condition occurs is disabled. 1 = The automatic disable of the Master clock of the USB Device Port when suspend condition occurs is enabled. • UHP: USB Host Port Clock Status 0 = The 48 MHz clock of the USB Host Port is disabled. 1 = The 48 MHz clock of the USB Host Port is enabled. • PCK0...PCK3: Programmable Clock Output Status 0 = The corresponding Programmable Clock output is disabled. 1 = The corresponding Programmable Clock output is enabled. 279 1768G–ATARM–29-Sep-06 23.6.4 PMC Peripheral Clock Enable Register PMC_PCER Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 – – • PID2...PID31: Peripheral Clock Enable 0 = No effect. 1 = Enables the corresponding peripheral clock. 280 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.6.5 PMC Peripheral Clock Disable Register PMC_PCDR Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 – – • PID2...PID31: Peripheral Clock Disable 0 = No effect. 1 = Disables the corresponding peripheral clock. 281 1768G–ATARM–29-Sep-06 23.6.6 PMC Peripheral Clock Status Register PMC_PCSR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 PID31 23 PID30 22 PID29 21 PID28 20 PID27 19 PID26 18 PID25 17 PID24 16 PID23 15 PID22 14 PID21 13 PID20 12 PID19 11 PID18 10 PID17 9 PID16 8 PID15 7 PID14 6 PID13 5 PID12 4 PID11 3 PID10 2 PID9 1 PID8 0 PID7 PID6 PID5 PID4 PID3 PID2 – – • PID2...PID31: Peripheral Clock Status 0 = The corresponding peripheral clock is disabled. 1 = The corresponding peripheral clock is enabled. 282 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.6.7 PMC Clock Generator Main Oscillator Register CKGR_MOR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 OSCOUNT 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 MOSCEN 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: 31 – 23 – 15 • MOSCEN: Main Oscillator Enable 0 = The Main Oscillator is disabled. Main Clock is the signal connected on XIN. 1 = The Main Oscillator is enabled. A crystal must be connected between XIN and XOUT. • OSCOUNT: Main Oscillator Start-up Time Specifies the number of Slow Clock cycles for the Main Oscillator start-up time. 283 1768G–ATARM–29-Sep-06 23.6.8 PMC Clock Generator Main Clock Frequency Register CKGR_MCFR Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 MAINF 7 6 5 4 MAINF 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 MAINRDY 8 Register Name: Access Type: 31 – 23 – 15 • MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. • MAINRDY: Main Clock Ready 0 = MAINF value is not valid or the Main Oscillator is disabled. 1 = The Main Oscillator has been enabled previously and MAINF value is available. 284 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.6.9 PMC Clock Generator PLL A Register CKGR_PLLAR Read/Write 30 – 22 29 1 21 28 – 20 MULA 15 OUTA 7 6 5 4 DIVA 3 14 13 12 11 PLLACOUNT 2 1 0 10 9 8 27 – 19 26 25 MULA 17 24 Register Name: Access Type: 31 – 23 18 16 Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the Clock Generator. Value to be written in CKGR_PLLAR must not be the same as current value in CKGR_PLLAR. • DIVA: Divider A DIVA 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the Main Clock divided by DIVA. • PLLACOUNT: PLL A Counter Specifies the number of Slow Clock cycles before the LOCKA bit is set in PMC_SR after CKGR_PLLAR is written. • OUTA: PLL A Clock Frequency Range OUTA 0 0 1 1 0 1 0 1 PLL A Frequency Output Range 80 MHz to 160 MHz Reserved 150 MHz to 240 MHz Reserved • MULA: PLL A Multiplier 0 = The PLL A is deactivated. 1 up to 2047 = The PLL A Clock frequency is the PLL A input frequency multiplied by MULA + 1. 285 1768G–ATARM–29-Sep-06 23.6.10 PMC Clock Generator PLL B Register CKGR_PLLBR Read/Write 30 – 22 29 – 21 28 USB_96M 20 MULB 27 – 19 26 25 MULB 17 24 Register Name: Access Type: 31 – 23 18 16 15 OUTB 7 14 13 12 11 PLLBCOUNT 10 9 8 6 5 4 DIVB 3 2 1 0 Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the Clock Generator. Value to be written in CKGR_PLLBR must not be the same as current value in CKGR_PLLBR. • DIVB: Divider B DIVB 0 1 2 - 255 Divider Selected Divider output is 0 Divider is bypassed Divider output is the selected clock divided by DIVB. • PLLBCOUNT: PLL B Counter Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written. • OUTB: PLL B Clock Frequency Range OUTB 0 0 1 1 0 1 0 1 PLL B Clock Frequency Range 80 MHz to 160 MHz Reserved 150 MHz to 240 MHz Reserved • MULB: PLL B Multiplier 0 = The PLL B is deactivated. 1 up to 2047 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1. • USB_96M: Divider by 2 Enable (only on ARM9-based Systems) 0 = USB ports clocks are PLL B Clock, therefore the PMC Clock Generator must be programmed for the PLL B Clock to be 48 MHz. 1 = USB ports clocks are PLL B Clock divided by 2, therefore the PMC Clock Generator must be programmed for the PLL B Clock to be 96 MHz. 286 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.6.11 PMC Master Clock Register PMC_MCKR Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 MDIV 0 – – PRES CSS Note: Value to be written in PMC_MCKR must not be the same as current value in PMC_MCKR. • CSS: Master Clock Selection CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected PLL A Clock is selected PLL B Clock is selected • PRES: Master Clock Prescaler PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved • MDIV: Master Clock Division (on ARM9-based systems only) 0 = The Master Clock and the Processor Clock are the same. 1 = The Processor Clock is twice as fast as the Master Clock. 2 = The Processor Clock is three times faster than the Master Clock. 3 = The Processor Clock is four times faster than the Master Clock. 287 1768G–ATARM–29-Sep-06 23.6.12 PMC Programmable Clock Register 0 to 3 PMC_PCK0..PMC_PCK3 Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – PRES CSS • CSS: Master Clock Selection CSS 0 0 1 1 0 1 0 1 Clock Source Selection Slow Clock is selected Main Clock is selected PLL A Clock is selected PLL B Clock is selected • PRES: Programmable Clock Prescaler PRES 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Master Clock Selected clock Selected clock divided by 2 Selected clock divided by 4 Selected clock divided by 8 Selected clock divided by 16 Selected clock divided by 32 Selected clock divided by 64 Reserved 288 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.6.13 PMC Interrupt Enable Register PMC_IER Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 PCK3RDY 3 PCK2RDY 2 PCK1RDY 1 PCK0RDY 0 – – – – MCKRDY LOCKB LOCKA MOSCS • MOSCS: Main Oscillator Status • LOCKA: PLL A Lock • LOCKB: PLL B Lock • MCKRDY: Master Clock Ready • PCK0RDY - PCK3RDY: Programmable Clock Ready 0 = No effect. 1 = Enables the corresponding interrupt. 289 1768G–ATARM–29-Sep-06 23.6.14 PMC Interrupt Disable Register PMC_IDR Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 PCK3RDY 3 PCK2RDY 2 PCK1RDY 1 PCK0RDY 0 – – – – MCKRDY LOCKB LOCKA MOSCS • MOSCS: Main Oscillator Status • LOCKA: PLL A Lock • LOCKB: PLL B Lock • MCKRDY: Master Clock Ready • PCK0RDY - PCK3RDY: Programmable Clock Ready 0 = No effect. 1 = Disables the corresponding interrupt. 290 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 23.6.15 PMC Status Register PMC_SR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 PCK3RDY 3 PCK2RDY 2 PCK1RDY 1 PCK0RDY 0 – – – – MCKRDY LOCKB LOCKA MOSCS • MOSCS: MOSCS Flag Status 0 = Main oscillator is not stabilized. 1 = Main oscillator is stabilized. • LOCKA: PLLA Lock Status 0 = PLLL A is not locked 1 = PLL A is locked. • LOCKB: PLLB Lock Status 0 = PLL B is not locked. 1 = PLL B is locked. • MCKRDY: Master Clock Status 0 = MCK is not ready. 1 = MCK is ready. • PCK0RDY - PCK3RDY: Programmable Clock Ready Status 0 = Programmable Clock 0 to 3 is not ready. 1 = Programmable Clock 0 to 3 is ready. 291 1768G–ATARM–29-Sep-06 23.6.16 PMC Interrupt Mask Register PMC_IMR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 PCK3RDY 3 PCK2RDY 2 PCK1RDY 1 PCK0RDY 0 – – – – MCKRDY LOCKB LOCKA MOSCS • MOSCS: Main Oscillator Status • LOCKA: PLL A Lock • LOCKB: PLL B Lock • MCKRDY: Master Clock Ready • PCK0RDY - PCK3RDY: Programmable Clock Ready • MOSCS: MOSCS Interrupt Mask 0 = The corresponding interrupt is enabled. 1 = The corresponding interrupt is disabled. 292 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 24. System Timer (ST) 24.1 Overview The System Timer (ST) module integrates three different free-running timers: • A Period Interval Timer (PIT) that sets the time base for an operating system. • A Watchdog Timer (WDT) with system reset capabilities in case of software deadlock. • A Real-Time Timer (RTT) counting elapsed seconds. These timers count using the Slow Clock provided by the Power Management Controller. Typically, this clock has a frequency of 32.768 kHz, but the System Timer might be configured to support another frequency. The System Timer provides an interrupt line connected to one of the sources of the Advanced Interrupt Controller (AIC). Interrupt handling requires programming the AIC before configuring the System Timer. Usually, the System Timer interrupt line is connected to the first interrupt source line and shares this entry with the Debug Unit (DBGU) and the Real Time Clock (RTC). This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. Important features of the System Timer include: • One Period Interval Timer, 16-bit Programmable Counter • One Watchdog Timer, 16-bit Programmable Counter • One Real-time Timer, 20-bit Free-running Counter • Interrupt Generation on Event 24.2 Block Diagram Figure 24-1. System Timer Block Diagram APB System Timer Periodic Interval Timer Real-Time Timer Power Management Controller SLCK NWDOVF Watchdog Timer STIRQ Advanced Interrupt Controller 293 1768G–ATARM–29-Sep-06 24.3 Application Block Diagram Figure 24-2. Application Block Diagram OS or RTOS Scheduler Date, Time and Alarm Manager System Survey Manager PIT RTT WDT 24.4 24.4.1 Product Dependencies Power Management The System Timer is continuously clocked at 32768 Hz. The power management controller has no effect on the system timer behavior. 24.4.2 Interrupt Sources The System Timer interrupt is generally connected to the source 1 of the Advanced Interrupt Controller. This interrupt line is the result of the OR-wiring of the system peripheral interrupt lines (System Timer, Real Time Clock, Power Management Controller, Memory Controller). When a system interrupt happens, the service routine must first determine the cause of the interrupt. This is accomplished by reading successively the status registers of the above mentioned system peripherals. 24.4.3 Watchdog Overflow The System Timer is capable of driving the NWDOVF pin. This pin might be implemented or not in a product. When it is implemented, this pin might or not be multiplexed on the PIO Controllers even though it is recommended to dedicate a pin to the watchdog function. If the NWDOVF is multiplexed on a PIO Controller, this last should be first programmed to assign the pin to the watchdog function before using the pin as NWDOVF. When it is not implemented, programming the associated bits and registers has no effect on the behavior of the System Timer. 24.5 24.5.1 Functional Description System Timer Clock The System Timer uses only the SLCK clock so that it is capable to provide periodic, watchdog, second change or alarm interrupt even if the Power Management Controller is programmed to put the product in Slow Clock Mode. If the product has the capability to back up the Slow Clock oscillator and the System Timer, the System Timer can continue to operate. 24.5.2 Period Interval Timer (PIT) The Period Interval Timer can be used to provide periodic interrupts for use by operating systems. The reset value of the PIT is 0 corresponding to the maximum value. It is built around a 16-bit down counter, which is preloaded by a value programmed in ST_PIMR (Period Interval Mode Register). When the PIT counter reaches 0, the bit PITS is set in ST_SR (Status Register), and an interrupt is generated if it is enabled. 294 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 The counter is then automatically reloaded and restarted. Writing to the ST_PIMR at any time immediately reloads and restarts the down counter with the new programmed value. Warning: If ST_PIMR is programmed with a period less or equal to the current MCK period, the update of the PITS status bit and its associated interrupt generation are unpredictable. Figure 24-3. Period Interval Timer PIV SLCK Slow Clock 16-bit Down Counter PITS 24.5.3 Watchdog Timer (WDT) The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is built around a 16-bit down counter loaded with the value defined in ST_WDMR (Watchdog Mode Register). At reset, the value of the ST_WDMR is 0x00020000, corresponding to the maximum value of the counter. The watchdog overflow signal is tied low during 8 slow clock cycles when a watchdog overflow occurs (EXTEN bit set in ST_WDMR). It uses the Slow Clock divided by 128 to establish the maximum watchdog period to be 256 seconds (with a typical slow clock of 32.768 kHz). In normal operation, the user reloads the Watchdog at regular intervals before the timer overflow occurs, by setting the bit WDRST in the ST_CR (Control Register). If an overflow does occur, the watchdog timer: • Sets the WDOVF bit in ST_SR (Status Register), from which an interrupt can be generated. • Generates a pulse for 8 slow clock cycles on the external signal watchdog overflow if the bit EXTEN in ST_WDMR is set. • Generates an internal reset if the parameter RSTEN in ST_WDMR is set. • Reloads and restarts the down counter. Writing the ST_WDMR does not reload or restart the down counter. When the ST_CR is written the watchdog counter is immediately reloaded from ST_WDMR and restarted and the Slow Clock 128 divider is also immediately reset and restarted. 295 1768G–ATARM–29-Sep-06 Figure 24-4. Watchdog Timer WV SLCK 1/128 16-bit Down Counter RSTEN WDRST EXTEN WDOVF Status Internal Reset NWDOVF 24.5.4 Real-time Timer (RTT) The Real-Time Timer is used to count elapsed seconds. It is built around a 20-bit counter fed by Slow Clock divided by a programmable value. At reset, this value is set to 0x8000, corresponding to feeding the real-time counter with a 1 Hz signal when the Slow Clock is 32.768 Hz. The 20-bit counter can count up to 1048576 seconds, corresponding to more than 12 days, then roll over to 0. The Real-Time Timer value can be read at any time in the register ST_CRTR (Current Real-time Register). As this value can be updated asynchronously to the master clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. This current value of the counter is compared with the value written in the alarm register ST_RTAR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in TC_SR is set. The alarm register is set to its maximum value, corresponding to 0, after a reset. The bit RTTINC in ST_SR is set each time the 20-bit counter is incremented. This bit can be used to start an interrupt, or generate a one-second signal. Writing the ST_RTMR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 20-bit counter. Warning: If RTPRES is programmed with a period less or equal to the current MCK period, the update of the RTTINC and ALMS status bits and their associated interrupt generation are unpredictable. Figure 24-5. Real Time Timer RTPRES SLCK 16-bit Divider 20-bit Counter RTTINC = ALMV ALMS 296 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 24.6 System Timer (ST) User Interface Table 24-1. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 Register Mapping Register Control Register Period Interval Mode Register Watchdog Mode Register Real-time Mode Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Real-time Alarm Register Current Real-time Register Name ST_CR ST_PIMR ST_WDMR ST_RTMR ST_SR ST_IER ST_IDR ST_IMR ST_RTAR ST_CRTR Access Write-only Read/Write Read/Write Read/Write Read-only Write-only Write-only Read-only Read/Write Read-only Reset Value – 0x00000000 0x00020000 0x00008000 – – – 0x0 0x0 0x0 297 1768G–ATARM–29-Sep-06 24.6.1 ST Control Register ST_CR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 WDRST Register Name: Access Type: 31 – 23 – 15 – 7 – • WDRST: Watchdog Timer Restart 0 = No effect. 1 = Reload the start-up value in the watchdog timer. 24.6.2 ST Period Interval Mode Register ST_PIMR Read/Write – – – – – – – Register Name: Access Type: – – – – – – – – – PIV PIV • PIV: Period Interval Value Defines the value loaded in the 16-bit counter of the period interval timer. The maximum period is obtained by programming PIV at 0x0 corresponding to 65536 slow clock cycles. 298 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 24.6.3 ST Watchdog Mode Register ST_WDMR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 WDV 7 6 5 4 WDV 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 EXTEN 9 24 – 16 RSTEN 8 Register Name: Access Type: 31 – 23 – 15 • WDV: Watchdog Counter Value Defines the value loaded in the 16-bit counter. The maximum period is obtained by programming WDV to 0x0 corresponding to 65536 x 128 slow clock cycles. • RSTEN: Reset Enable 0 = No reset is generated when a watchdog overflow occurs. 1 = An internal reset is generated when a watchdog overflow occurs. • EXTEN: External Signal Assertion Enable 0 = The watchdog_overflow is not tied low when a watchdog overflow occurs. 1 = The watchdog_overflow is tied low during 8 slow clock cycles when a watchdog overflow occurs. 24.6.4 ST Real-Time Mode Register ST_RTMR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RTPRES 7 6 5 4 RTPRES 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: 31 – 23 – 15 • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer. The maximum period is obtained by programming RTPRES to 0x0 corresponding to 65536 slow clock cycles. 299 1768G–ATARM–29-Sep-06 24.6.5 ST Status Register ST_SR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 ALMS 26 – 18 – 10 – 2 RTTINC 25 – 17 – 9 – 1 WDOVF 24 – 16 – 8 – 0 PITS Register Name: Access Type: 31 – 23 – 15 – 7 – • PITS: Period Interval Timer Status 0 = The period interval timer has not reached 0 since the last read of the Status Register. 1 = The period interval timer has reached 0 since the last read of the Status Register. • WDOVF: Watchdog Overflow 0 = The watchdog timer has not reached 0 since the last read of the Status Register. 1 = The watchdog timer has reached 0 since the last read of the Status Register. • RTTINC: Real-time Timer Increment 0 = The real-time timer has not been incremented since the last read of the Status Register. 1 = The real-time timer has been incremented since the last read of the Status Register. • ALMS: Alarm Status 0 = No alarm compare has been detected since the last read of the Status Register. 1 = Alarm compare has been detected since the last read of the Status Register. 300 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 24.6.6 ST Interrupt Enable Register ST_IER Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 ALMS 26 – 18 – 10 – 2 RTTINC 25 – 17 – 9 – 1 WDOVF 24 – 16 – 8 – 0 PITS Register Name: Access Type: 31 – 23 – 15 – 7 – • PITS: Period Interval Timer Status Interrupt Enable • WDOVF: Watchdog Overflow Interrupt Enable • RTTINC: Real-time Timer Increment Interrupt Enable • ALMS: Alarm Status Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 301 1768G–ATARM–29-Sep-06 24.6.7 ST Interrupt Disable Register ST_IDR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 ALMS 26 – 18 – 10 – 2 RTTINC 25 – 17 – 9 – 1 WDOVF 24 – 16 – 8 – 0 PITS Register Name: Access Type: 31 – 23 – 15 – 7 – • PITS: Period Interval Timer Status Interrupt Disable • WDOVF: Watchdog Overflow Interrupt Disable • RTTINC: Real-time Timer Increment Interrupt Disable • ALMS: Alarm Status Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 302 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 24.6.8 ST Interrupt Mask Register ST_IMR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 ALMS 26 – 18 – 10 – 2 RTTINC 25 – 17 – 9 – 1 WDOVF 24 – 16 – 8 – 0 PITS Register Name: Access Type: 31 – 23 – 15 – 7 – • PITS: Period Interval Timer Status Interrupt Mask • WDOVF: Watchdog Overflow Interrupt Mask • RTTINC: Real-time Timer Increment Interrupt Mask • ALMS: Alarm Status Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 24.6.9 ST Real-time Alarm Register ST_RTAR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 ALMV 7 6 5 4 ALMV 3 2 1 0 27 – 19 26 – 18 ALMV 11 10 9 8 25 – 17 24 – 16 Register Name: Access Type: 31 – 23 – 15 • ALMV: Alarm Value Defines the alarm value compared with the real-time timer. The maximum delay before ALMS status bit activation is obtained by programming ALMV to 0x0 corresponding to 1048576 seconds. 303 1768G–ATARM–29-Sep-06 24.6.10 ST Current Real-Time Register ST_CRTR Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CRTV 27 – 19 26 – 18 CRTV 11 10 9 8 25 – 17 24 – 16 Register Name: Access Type: 31 – 23 – 15 7 6 5 4 CRTV 3 2 1 0 • CRTV: Current Real-time Value Returns the current value of the real-time timer. 304 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 25. Real Time Clock (RTC) 25.1 Overview The Real-time Clock (RTC) peripheral is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred-year Gregorian calendar, complemented by a programmable periodic interrupt. The alarm and calendar registers are accessed by a 32-bit data bus. The time and calendar values are coded in binary-coded decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator. Updating time and calendar fields and configuring the alarm fields are performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/year/century. Important features of the RTC include: • Low Power Consumption • Full Asynchronous Design • Two Hundred Year Calendar • Programmable Periodic Interrupt • Alarm and Update Parallel Load • Control of Alarm and Update Time/Calendar Data In 25.2 Block Diagram Figure 25-1. RTC Block Diagram Crystal Oscillator: SLCK 32768 Divider Time Date Bus Interface Bus Interface Entry Control Interrupt Control RTC Interrupt 25.3 25.3.1 Product Dependencies Power Management The Real-time Clock is continuously clocked at 32768 Hz. The Power Management Controller has no effect on RTC behavior. 25.3.2 Interrupt The RTC Interrupt is connected to interrupt source 1 (IRQ1) of the advanced interrupt controller. This interrupt line is due to the OR-wiring of the system peripheral interrupt lines (System Timer, 305 1768G–ATARM–29-Sep-06 Real Time Clock, Power Management Controller, Memory Controller, etc.). When a system interrupt occurs, the service routine must first determine the cause of the interrupt. This is done by reading the status registers of the above system peripherals successively. 25.4 Functional Description The RTC provides a full binary-coded decimal (BCD) clock that includes century (19/20), year (with leap years), month, date, day, hours, minutes and seconds. The valid year range is 1900 to 2099, a two-hundred-year Gregorian calendar achieving full Y2K compliance. The RTC can operate in 24-hour mode or in 12-hour mode with an AM/PM indicator. Corrections for leap years are included (all years divisible by 4 being leap years, including year 2000). This is correct up to the year 2099. After hardware reset, the calendar is initialized to Thursday, January 1, 1998. 25.4.1 Reference Clock The reference clock is Slow Clock (SLCK). It can be driven by the Atmel cell OSC55 or OSC56 (or an equivalent cell) and an external 32.768 kHz crystal. During low power modes of the processor (idle mode), the oscillator runs and power consumption is critical. The crystal selection has to take into account the current consumption for power saving and the frequency drift due to temperature effect on the circuit for time accuracy. 25.4.2 Timing The RTC is updated in real time at one-second intervals in normal mode for the counters of seconds, at one-minute intervals for the counter of minutes and so on. Due to the asynchronous operation of the RTC with respect to the rest of the chip, to be certain that the value read in the RTC registers (century, year, month, date, day, hours, minutes, seconds) are valid and stable, it is necessary to read these registers twice. If the data is the same both times, then it is valid. Therefore, a minimum of two and a maximum of three accesses are required. 25.4.3 Alarm The RTC has five programmable fields: month, date, hours, minutes and seconds. Each of these fields can be enabled or disabled to match the alarm condition: • If all the fields are enabled, an alarm flag is generated (the corresponding flag is asserted and an interrupt generated if enabled) at a given month, date, hour/minute/second. • If only the “seconds” field is enabled, then an alarm is generated every minute. Depending on the combination of fields enabled, a large number of possibilities are available to the user ranging from minutes to 365/366 days. 25.4.4 Error Checking Verification on user interface data is performed when accessing the century, year, month, date, day, hours, minutes, seconds and alarms. A check is performed on illegal BCD entries such as illegal date of the month with regard to the year and century configured. 306 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 If one of the time fields is not correct, the data is not loaded into the register/counter and a flag is set in the validity register. The user can not reset this flag. It is reset as soon as an acceptable value is programmed. This avoids any further side effects in the hardware. The same procedure is done for the alarm. The following checks are performed: 1. Century (check if it is in range 19 - 20) 2. Year (BCD entry check) 3. Date (check range 01 - 31) 4. Month (check if it is in BCD range 01 - 12, check validity regarding “date”) 5. Day (check range 1 - 7) 6. Hour (BCD checks: in 24-hour mode, check range 00 - 23 and check that AM/PM flag is not set if RTC is set in 24-hour mode; in 12-hour mode check range 01 - 12) 7. Minute (check BCD and range 00 - 59) 8. Second (check BCD and range 00 - 59) Note: If the 12-hour mode is selected by means of the RTC_MODE register, a 12-hour value can be programmed and the returned value on RTC_TIME will be the corresponding 24-hour value. The entry control checks the value of the AM/PM indicator (bit 22 of RTC_TIME register) to determine the range to be checked. 25.4.5 Updating Time/Calendar To update any of the time/calendar fields, the user must first stop the RTC by setting the corresponding field in the Control Register. Bit UPDTIM must be set to update time fields (hour, minute, second) and bit UPDCAL must be set to update calendar fields (century, year, month, date, day). Then the user must poll or wait for the interrupt (if enabled) of bit ACKUPD in the Status Register. Once the bit reads 1, the user can write to the appropriate register. Once the update is finished, the user must reset (0) UPDTIM and/or UPDCAL in the Control Register. When programming the calendar fields, the time fields remain enabled. This avoids a time slip in case the user stays in the calendar update phase for several tens of seconds or more. In successive update operations, the user must wait at least one second after resetting the UPDTIM/UPDCAL bit in the RTC_CR (Control Register) before setting these bits again. This is done by waiting for the SEC flag in the Status Register before setting UPDTIM/UPDCAL bit. After resetting UPDTIM/UPDCAL, the SEC flag must also be cleared. 307 1768G–ATARM–29-Sep-06 25.5 Real Time Clock (RTC) User Interface RTC Register Mapping Register RTC Control Register RTC Mode Register RTC Time Register RTC Calendar Register RTC Time Alarm Register RTC Calendar Alarm Register RTC Status Register RTC Status Clear Command Register RTC Interrupt Enable Register RTC Interrupt Disable Register RTC Interrupt Mask Register RTC Valid Entry Register Register Name RTC_CR RTC_MR RTC_TIMR RTC_CALR RTC_TIMALR RTC_CALALR RTC_SR RTC_SCCR RTC_IER RTC_IDR RTC_IMR RTC_VER Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read only Write only Write only Write only Read only Read only Reset 0x0 0x0 0x0 0x01819819 0x0 0x01010000 0x0 ------0x0 0x0 Table 25-1. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 308 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 25.5.1 Name: Access Type: 31 RTC Control Register RTC_CR Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 CALEVSEL 8 – 7 – 6 – 5 – 4 – 3 – 2 1 TIMEVSEL 0 – – – – – – UPDCAL UPDTIM • UPDTIM: Update Request Time Register 0 = No effect. 1 = Stops the RTC time counting. Time counting consists of second, minute and hour counters. Time counters can be programmed once this bit is set and acknowledged by the bit ACKUPD of the Status Register. • UPDCAL: Update Request Calendar Register 0 = No effect. 1 = Stops the RTC calendar counting. Calendar counting consists of day, date, month, year and century counters. Calendar counters can be programmed once this bit is set. • TIMEVSEL: Time Event Selection The event that generates the flag TIMEV in RTC_SR (Status Register) depends on the value of TIMEVSEL. 0 = Minute change. 1 = Hour change. 2 = Every day at midnight. 3 = Every day at noon. • CALEVSEL: Calendar Event Selection The event that generates the flag CALEV in RTC_SR depends on the value of CALEVSEL. 0 = Week change (every Monday at time 00:00:00). 1 = Month change (every 01 of each month at time 00:00:00). 2, 3 = Year change (every January 1 at time 00:00:00). 309 1768G–ATARM–29-Sep-06 25.5.2 Name: RTC Mode Register RTC_MR Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – – – HRMOD • HRMOD: 12-/24-hour Mode 0 = 24-hour mode is selected. 1 = 12-hour mode is selected. All non-significant bits read zero. 310 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 25.5.3 Name: Access Type: 31 RTC Time Register RTC_TIMR Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 AMPM 14 13 12 11 HOUR 10 9 8 – 7 6 5 4 MIN 3 2 1 0 – SEC • SEC: Current Second The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MIN: Current Minute The range that can be set is 0 - 59 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • HOUR: Current Hour The range that can be set is 1 - 12 (BCD) in 12-hour mode or 0 - 23 (BCD) in 24-hour mode. • AMPM: Ante Meridiem Post Meridiem Indicator This bit is the AM/PM indicator in 12-hour mode. 0 = AM. 1 = PM. All non-significant bits read zero. 311 1768G–ATARM–29-Sep-06 25.5.4 Name: RTC Calendar Register RTC_CALR Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 21 20 19 DATE 18 17 16 DAY 15 14 13 12 11 MONTH 10 9 8 YEAR 7 6 5 4 3 2 1 0 – CENT • CENT: Current Century The range that can be set is 19 - 20 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • YEAR: Current Year The range that can be set is 00 - 99 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • MONTH: Current Month The range that can be set is 01 - 12 (BCD). The lowest four bits encode the units. The higher bits encode the tens. • DAY: Current Day The range that can be set is 1 - 7 (BCD). The coding of the number (which number represents which day) is user-defined as it has no effect on the date counter. • DATE: Current Date The range that can be set is 01 - 31 (BCD). The lowest four bits encode the units. The higher bits encode the tens. All non-significant bits read zero. 312 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 25.5.5 Name: Access Type: 31 RTC Time Alarm Register RTC_TIMALR Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 HOUREN 15 AMPM 14 13 12 11 HOUR 10 9 8 MINEN 7 6 5 4 MIN 3 2 1 0 SECEN SEC • SEC: Second Alarm This field is the alarm field corresponding to the BCD-coded second counter. • SECEN: Second Alarm Enable 0 = The second-matching alarm is disabled. 1 = The second-matching alarm is enabled. • MIN: Minute Alarm This field is the alarm field corresponding to the BCD-coded minute counter. • MINEN: Minute Alarm Enable 0 = The minute-matching alarm is disabled. 1 = The minute-matching alarm is enabled. • HOUR: Hour Alarm This field is the alarm field corresponding to the BCD-coded hour counter. • AMPM: AM/PM Indicator This field is the alarm field corresponding to the BCD-coded hour counter. • HOUREN: Hour Alarm Enable 0 = The hour-matching alarm is disabled. 1 = The hour-matching alarm is enabled. 313 1768G–ATARM–29-Sep-06 25.5.6 Name: RTC Calendar Alarm Register RTC_CALALR Read/Write 30 29 28 27 26 25 24 Access Type: 31 DATEEN 23 – 22 21 20 19 DATE 18 17 16 MTHEN 15 – 14 – 13 12 11 MONTH 10 9 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – – – – • MONTH: Month Alarm This field is the alarm field corresponding to the BCD-coded month counter. • MTHEN: Month Alarm Enable 0 = The month-matching alarm is disabled. 1 = The month-matching alarm is enabled. • DATE: Date Alarm This field is the alarm field corresponding to the BCD-coded date counter. • DATEEN: Date Alarm Enable 0 = The date-matching alarm is disabled. 1 = The date-matching alarm is enabled. 314 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 25.5.7 Name: Access Type: 31 RTC Status Register RTC_SR Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CALEV TIMEV SEC ALARM ACKUPD • ACKUPD: Acknowledge for Update 0 = Time and calendar registers cannot be updated. 1 = Time and calendar registers can be updated. • ALARM: Alarm Flag 0 = No alarm matching condition occurred. 1 = An alarm matching condition has occurred. • SEC: Second Event 0 = No second event has occurred since the last clear. 1 = At least one second event has occurred since the last clear. • TIMEV: Time Event 0 = No time event has occurred since the last clear. 1 = At least one time event has occurred since the last clear. The time event is selected in the TIMEVSEL field in RTC_CTRL (Control Register) and can be any one of the following events: minute change, hour change, noon, midnight (day change). • CALEV: Calendar Event 0 = No calendar event has occurred since the last clear. 1 = At least one calendar event has occurred since the last clear. The calendar event is selected in the CALEVSEL field in RTC_CR and can be any one of the following events: week change, month change and year change. 315 1768G–ATARM–29-Sep-06 25.5.8 Name: RTC Status Clear Command Register RTC_SCCR Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CALCLR TIMCLR SECCLR ALRCLR ACKCLR • Status Flag Clear 0 = No effect. 1 = Clears corresponding status flag in the Status Register (RTC_SR). 316 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 25.5.9 Name: Access Type: 31 RTC Interrupt Enable Register RTC_IER Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CALEN TIMEN SECEN ALREN ACKEN • ACKEN: Acknowledge Update Interrupt Enable 0 = No effect. 1 = The acknowledge for update interrupt is enabled. • ALREN: Alarm Interrupt Enable 0 = No effect. 1 = The alarm interrupt is enabled. • SECEN: Second Event Interrupt Enable 0 = No effect. 1 = The second periodic interrupt is enabled. • TIMEN: Time Event Interrupt Enable 0 = No effect. 1 = The selected time event interrupt is enabled. • CALEN: Calendar Event Interrupt Enable 0 = No effect. • 1 = The selected calendar event interrupt is enabled. 317 1768G–ATARM–29-Sep-06 25.5.10 Name: RTC Interrupt Disable Register RTC_IDR Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CALDIS TIMDIS SECDIS ALRDIS ACKDIS • ACKDIS: Acknowledge Update Interrupt Disable 0 = No effect. 1 = The acknowledge for update interrupt is disabled. • ALRDIS: Alarm Interrupt Disable 0 = No effect. 1 = The alarm interrupt is disabled. • SECDIS: Second Event Interrupt Disable 0 = No effect. 1 = The second periodic interrupt is disabled. • TIMDIS: Time Event Interrupt Disable 0 = No effect. 1 = The selected time event interrupt is disabled. • CALDIS: Calendar Event Interrupt Disable 0 = No effect. 1 = The selected calendar event interrupt is disabled. 318 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 25.5.11 Name: Access Type: 31 RTC Interrupt Mask Register RTC_IMR Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – CAL TIM SEC ALR ACK • ACK: Acknowledge Update Interrupt Mask 0 = The acknowledge for update interrupt is disabled. 1 = The acknowledge for update interrupt is enabled. • ALR: Alarm Interrupt Mask 0 = The alarm interrupt is disabled. 1 = The alarm interrupt is enabled. • SEC: Second Event Interrupt Mask 0 = The second periodic interrupt is disabled. 1 = The second periodic interrupt is enabled. • TIM: Time Event Interrupt Mask 0 = The selected time event interrupt is disabled. 1 = The selected time event interrupt is enabled. • CAL: Calendar Event Interrupt Mask 0 = The selected calendar event interrupt is disabled. 1 = The selected calendar event interrupt is enabled. 319 1768G–ATARM–29-Sep-06 25.5.12 Name: RTC Valid Entry Register RTC_VER Read-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – NVCALAR NVTIMALR NVCAL NVTIM • NVTIM: Non valid Time 0 = No invalid data has been detected in RTC_TIMR (Time Register). 1 = RTC_TIMR has contained invalid data since it was last programmed. • NVCAL: Non valid Calendar 0 = No invalid data has been detected in RTC_CALR (Calendar Register). 1 = RTC_CALR has contained invalid data since it was last programmed. • NVTIMALR: Non valid Time Alarm 0 = No invalid data has been detected in RTC_TIMALR (Time Alarm Register). 1 = RTC_TIMALR has contained invalid data since it was last programmed. • NVCALALR: Non valid Calendar Alarm 0 = No invalid data has been detected in RTC_CALALR (Calendar Alarm Register). 1 = RTC_CALALR has contained invalid data since it was last programmed. 320 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26. Debug Unit (DBGU) 26.1 Overview The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Atmel’s ARM-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. Moreover, the association with two Peripheral DMA Controller channels permits packet handling for these tasks with processor time reduced to a minimum. The Debug Unit also makes the Debug Communication Channel (DCC) signals provided by the In-circuit Emulator of the ARM processor visible to the software. These signals indicate the status of the DCC read and write registers and generate an interrupt to the ARM processor, making possible the handling of the DCC under interrupt control. Chip Identifier registers permit recognition of the device and its revision. These registers inform as to the sizes and types of the on-chip memories, as well as the set of embedded peripherals. Finally, the Debug Unit features a Force NTRST capability that enables the software to decide whether to prevent access to the system via the In-circuit Emulator. This permits protection of the code, stored in ROM. Important features of the Debug Unit are: • System Peripheral to Facilitate Debug of Atmel’s ARM-based Systems • Composed of Three Functions – Two-pin UART – Debug Communication Channel (DCC) Support – Chip ID Registers • Two-pin UART – Implemented Features are 100% Compatible with the Standard Atmel USART – Independent Receiver and Transmitter with a Common Programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Interrupt Generation – Support for Two Peripheral DMA Controller (PDC) Channels with Connection to Receiver and Transmitter • Debug Communication Channel Support – Offers Visibility of COMMRX and COMMTX Signals from the ARM Processor – Interrupt Generation • Chip ID Registers – Identification of the Device Revision, Sizes of the Embedded Memories, Set of Peripherals 321 1768G–ATARM–29-Sep-06 26.2 Block Diagram Figure 26-1. Debug Unit Functional Block Diagram Peripheral Bridge Peripheral Data Controller APB Debug Unit DTXD Power Management Controller Transmit MCK Baud Rate Generator Receive Parallel Input/ Output DRXD COMMRX ARM Processor nTRST COMMTX DCC Handler Chip ID ICE Access Handler Interrupt Control NTRST(1) Force NTRST Other System Interrupt Sources DBGU Interupt Source 1 Advanced Interrupt Controller Note: 1. If NTRST pad is not bonded out, it is connected to NRST. Table 26-1. Pin Name DRXD DTXD Debug Unit Pin Description Description Debug Receive Data Debug Transmit Data Type Input Output Figure 26-2. Debug Unit Application Example Boot Program Debug Monitor Trace Manager Debug Unit RS232 Drivers Programming Tool Debug Console Trace Console 322 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26.3 26.3.1 Product Dependencies I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines. In this case, the programmer must first configure the corresponding PIO Controller to enable I/O lines operations of the Debug Unit. 26.3.2 Power Management Depending on product integration, the Debug Unit clock may be controllable through the Power Management Controller. In this case, the programmer must first configure the PMC to enable the Debug Unit clock. Usually, the peripheral identifier used for this purpose is 1. 26.3.3 Interrupt Source Depending on product integration, the Debug Unit interrupt line is connected to one of the interrupt sources of the Advanced Interrupt Controller. Interrupt handling requires programming of the AIC before configuring the Debug Unit. Usually, the Debug Unit interrupt line connects to the interrupt source 1 of the AIC, which may be shared with the real-time clock, the system timer interrupt lines and other system peripheral interrupts, as shown in Figure 26-1. This sharing requires the programmer to determine the source of the interrupt when the source 1 is triggered. 26.4 UART Operations The Debug Unit operates as a UART, (asynchronous mode only) and supports only 8-bit character handling (with parity). It has no clock pin. The Debug Unit's UART is made up of a receiver and a transmitter that operate independently, and a common baud rate generator. Receiver timeout and transmitter time guard are not implemented. However, all the implemented features are compatible with those of a standard USART. 26.4.1 Baud Rate Generator The baud rate generator provides the bit period clock named baud rate clock to both the receiver and the transmitter. The baud rate clock is the master clock divided by 16 times the value (CD) written in DBGU_BRGR (Baud Rate Generator Register). If DBGU_BRGR is set to 0, the baud rate clock is disabled and the Debug Unit's UART remains inactive. The maximum allowable baud rate is Master Clock divided by 16. The minimum allowable baud rate is Master Clock divided by (16 x 65536). MCK Baud Rate = --------------------16 × CD 323 1768G–ATARM–29-Sep-06 Figure 26-3. Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock 26.4.2 26.4.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 26.4.2.2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. 324 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 26-4. Start Bit Detection Sampling Clock DRXD True Start Detection Baud Rate Clock D0 Figure 26-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 26.4.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 26-6. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 26.4.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral DMA Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 26-7. Receiver Overrun DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 325 1768G–ATARM–29-Sep-06 26.4.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 26-8. Parity Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 26.4.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 26-9. Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 RSTSTA 26.4.3 26.4.3.1 Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. 326 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26.4.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 26-10. Character Transmission Example: Parity enabled Baud Rate Clock DTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 26.4.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 26-11. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register Data 0 Data 1 DTXD S Data 0 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 327 1768G–ATARM–29-Sep-06 26.4.4 Peripheral DMA Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral DMA Controller (PDC) channel. The Peripheral DMA controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR. 26.4.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. 328 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 26-12. Test Modes Automatic Echo Receiver RXD Transmitter Disabled TXD Local Loopback Receiver Disabled RXD VDD Transmitter Disabled TXD Remote Loopback Receiver VDD Disabled RXD Transmitter Disabled TXD 26.4.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 329 1768G–ATARM–29-Sep-06 26.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: • EXT - shows the use of the extension identifier register • NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size • ARCH - identifies the set of embedded peripheral • SRAMSIZ - indicates the size of the embedded SRAM • EPROC - indicates the embedded ARM processor • VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 330 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26.5 Debug Unit User Interface Debug Unit Memory Map Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Reserved 0x004C - 0x00FC 0x0100 - 0x0124 Reserved PDC Area – – – – – – Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR – DBGU_CIDR DBGU_EXID Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write – Read-only Read-only Reset Value – 0x0 – – 0x0 – 0x0 – 0x0 – – – Table 26-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 - 0x003C 0X0040 0X0044 331 1768G–ATARM–29-Sep-06 26.5.1 Name: Debug Unit Control Register DBGU_CR Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 0 – 7 TXDIS – 6 TXEN – 5 RXDIS – 4 RXEN – 3 RSTTX – 2 RSTRX – 1 – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. • RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. • RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. • RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. • TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. • TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. • RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 332 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26.5.2 Name: Access Type: 31 Debug Unit Mode Register DBGU_MR Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CHMODE 7 – 14 – 13 – 12 – 11 – 10 PAR – 9 – 8 – 6 5 – 4 3 – 1 0 2 – – – – – – – – • PAR: Parity Type PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback 333 1768G–ATARM–29-Sep-06 26.5.3 Name: Debug Unit Interrupt Enable Register DBGU_IER Write-only 30 COMMTX 22 29 28 27 26 25 24 Access Type: 31 COMMRX 23 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Enable RXRDY Interrupt • TXRDY: Enable TXRDY Interrupt • ENDRX: Enable End of Receive Transfer Interrupt • ENDTX: Enable End of Transmit Interrupt • OVRE: Enable Overrun Error Interrupt • FRAME: Enable Framing Error Interrupt • PARE: Enable Parity Error Interrupt • TXEMPTY: Enable TXEMPTY Interrupt • TXBUFE: Enable Buffer Empty Interrupt • RXBUFF: Enable Buffer Full Interrupt • COMMTX: Enable COMMTX (from ARM) Interrupt • COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 334 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26.5.4 Name: Access Type: 31 COMMRX 23 Debug Unit Interrupt Disable Register DBGU_IDR Write-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Disable RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Disable End of Receive Transfer Interrupt • ENDTX: Disable End of Transmit Interrupt • OVRE: Disable Overrun Error Interrupt • FRAME: Disable Framing Error Interrupt • PARE: Disable Parity Error Interrupt • TXEMPTY: Disable TXEMPTY Interrupt • TXBUFE: Disable Buffer Empty Interrupt • RXBUFF: Disable Buffer Full Interrupt • COMMTX: Disable COMMTX (from ARM) Interrupt • COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 335 1768G–ATARM–29-Sep-06 26.5.5 Name: Debug Unit Interrupt Mask Register DBGU_IMR Read-only 30 COMMTX 22 29 28 27 26 25 24 Access Type: 31 COMMRX 23 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Mask RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Mask End of Receive Transfer Interrupt • ENDTX: Mask End of Transmit Interrupt • OVRE: Mask Overrun Error Interrupt • FRAME: Mask Framing Error Interrupt • PARE: Mask Parity Error Interrupt • TXEMPTY: Mask TXEMPTY Interrupt • TXBUFE: Mask TXBUFE Interrupt • RXBUFF: Mask RXBUFF Interrupt • COMMTX: Mask COMMTX Interrupt • COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 336 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26.5.6 Name: Access Type: 31 COMMRX 23 Debug Unit Status Register DBGU_SR Read-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. • TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. • ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral DMA Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral DMA Controller channel is active. • ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral DMA Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral DMA Controller channel is active. • OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. • PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. • TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. 337 1768G–ATARM–29-Sep-06 • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active. 338 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26.5.7 Name: Access Type: 31 Debug Unit Receiver Holding Register DBGU_RHR Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 RXCHR – 3 – 2 – 1 – 0 • RXCHR: Received Character Last received character if RXRDY is set. 339 1768G–ATARM–29-Sep-06 Debug Unit Transmit Holding Register Name: Access Type: 31 DBGU_THR Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 TXCHR – 3 – 2 – 1 – 0 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 340 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 26.5.8 Name: Access Type: 31 Debug Unit Baud Rate Generator Register DBGU_BRGR Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 CD – 11 – 10 – 9 – 8 7 6 5 4 CD 3 2 1 0 • CD: Clock Divisor CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16) 341 1768G–ATARM–29-Sep-06 26.5.9 Name: Debug Unit Chip ID Register DBGU_CIDR Read-only 30 29 NVPTYP 22 ARCH 15 0 7 14 0 6 EPROC 13 0 5 12 0 4 3 2 VERSION 11 10 NVPSIZ 1 0 21 20 19 18 SRAMSIZ 9 8 28 27 26 ARCH 17 16 25 24 Access Type: 31 EXT 23 • VERSION: Version of the device • EPROC: Embedded Processor EPROC 0 0 1 0 1 0 1 0 0 Processor ARM946ES™ ARM7TDMI® ARM920T • NVPSIZ: Nonvolatile Program Memory Size NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes Reserved Reserved Reserved Reserved Reserved Reserved 342 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • SRAMSIZ: Internal SRAM Size SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes Reserved 112K bytes 4K bytes 80K bytes 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 128K bytes 256K bytes 96K bytes 512K bytes • ARCH: Architecture Identifier ARCH Hex 0x40 0x63 0x55 0x42 0x92 0x34 Dec 0100 0000 0110 0011 0101 0101 0100 0010 1001 0010 0011 0100 Architecture AT91x40 Series AT91x63 Series AT91x55 Series AT91x42 Series AT91x92 Series AT91x34 Series • NVPTYP: Nonvolatile Program Memory Type NVPTYP 0 0 1 0 0 0 0 1 0 Memory ROM ROMless or on-chip Flash SRAM emulating ROM • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists. 343 1768G–ATARM–29-Sep-06 26.5.10 Name: Debug Unit Chip ID Extension Register DBGU_EXID Read-only 30 29 28 EXID 27 26 25 24 Access Type: 31 23 22 21 20 EXID 19 18 17 16 15 14 13 12 EXID 11 10 9 8 7 6 5 4 EXID 3 2 1 0 • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 344 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27. Parallel Input/Output Controller (PIO) 27.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: • An input change interrupt enabling level change on any I/O line. • A glitch filter providing rejection of pulses lower than one-half of clock cycle. • Multi-drive capability similar to an open drain I/O line. • Control of the pull-up of the I/O line. • Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. Important features of the PIO also include: • Up to 32 Programmable I/O Lines • Fully Programmable through Set/Clear Registers • Multiplexing of Two Peripheral Functions per I/O Line • For each I/O Line (Whether Assigned to a Peripheral or Used as General Purpose I/O) – Input Change Interrupt – Glitch Filter – Multi-drive Option Enables Driving in Open Drain – Programmable Pull Up on Each I/O Line – Pin Data Status Register, Supplies Visibility of the Level on the Pin at Any Time • Synchronous Output, Provides Set and Clear of Several I/O lines in a Single Write 345 1768G–ATARM–29-Sep-06 27.2 Block Diagram Figure 27-1. Block Diagram PIO Controller AIC PIO Interrupt PMC PIO Clock Embedded Peripheral Embedded Peripheral Embedded Peripheral Up to 32 peripheral IOs PIN Embedded Peripheral Embedded Peripheral Embedded Peripheral Up to 32 pins Up to 32 peripheral IOs PIN PIN APB Figure 27-2. Application Block Diagram On-chip Peripheral Drivers Keyboard Driver Control & Command Driver On-chip Peripherals PIO Controller Keyboard Driver General Purpose I/Os External Devices 346 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27.3 27.3.1 Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. 27.3.2 External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. 27.3.3 Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default (see Power Management Controller). The user must configure the Power Management Controller before any access to the input line information. 27.3.4 Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled. 27.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 27-3. 347 1768G–ATARM–29-Sep-06 Figure 27-3. I/O Line Control Logic PIO_OER PIO_OSR PIO_ODR PIO_PUER PIO_PUSR 1 Peripheral A Output Enable Peripheral B Output Enable PIO_ASR PIO_ABSR PIO_BSR Peripheral A Output Peripheral B Output 0 0 1 PIO_SODR PIO_ODSR PIO_CODR 1 0 0 0 1 PIO_PER PIO_PSR PIO_PDR PIO_MDER PIO_MDSR PIO_MDDR 1 Pad 1 0 PIO_PUDR Peripheral A Input Peripheral B Input PIO_PDSR 0 Edge Detector Glitch Filter PIO_IFER PIO_IFSR PIO_IFDR PIO_IER 1 PIO_ISR 1 0 PIO Interrupt PIO_IMR PIO_IDR 27.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The internal pull-ups have a typical value of 200 kOhm(see the product electrical characteristics for more details about this value). The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. 348 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. 27.4.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. 27.4.3 Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. 27.4.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_PDR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O 349 1768G–ATARM–29-Sep-06 lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 27.4.5 Synchronous Data Output Using the write operations in PIO_SODR and PIO_CODR can require that several instructions be executed in order to define values on several bits. Both clearing and setting I/O lines on an 8bit port, for example, cannot be done at the same time, and thus might limit the application covered by the PIO Controller. To avoid these inconveniences, the PIO Controller features a Synchronous Data Output to clear and set a number of I/O lines in a single write. This is performed by authorizing the writing of PIO_ODSR (Output Data Status Register) from the register set PIO_OWER (Output Write Enable Register), PIO_OWDR (Output Write Disable Register) and PIO_OWSR (Output Write Status Register). The value of PIO_OWSR register is user-definable by writing in PIO_OWER and PIO_OWDR. It is used by the PIO Controller as a PIO_ODSR write authorization mask. Authorizing the write of PIO_ODSR on a user-definable number of bits is especially useful, as it guarantees that the unauthorized bit will not be changed when writing it and thus avoids the need of a time consuming read-modify-write operation. After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 27.4.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 27.4.7 Output Line Timings Figure 27-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 27-4 also shows when the feedback in PIO_PDSR is available. 350 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 27-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0 APB Access APB Access PIO_ODSR 2 Cycles PIO_PDSR 2 Cycles 27.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 27.4.9 Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 27-5. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled. 351 1768G–ATARM–29-Sep-06 Figure 27-5. Input Glitch Filter Timing MCK Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 1 cycle 1 cycle 1 cycle 1 cycle 27.4.10 Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. Figure 27-6. Input Change Interrupt Timings MCK PIO_PDSR PIO_ISR Read PIO_ISR APB Access APB Access 27.5 I/O Lines Programming Example The programing example shown in Table 27-1 below is used to define the following configuration. • 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor • Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor • Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts 352 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter • I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor • I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor • I/O lines 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 27-1. Programming Example Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0 353 1768G–ATARM–29-Sep-06 27.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 27-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C 0x0070 0x0074 0x0078 PIO Register Mapping Register PIO Enable Register PIO Disable Register PIO Status Register Reserved PIO Output Enable Register PIO Output Disable Register PIO Output Status Register Reserved PIO Glitch Input Filter Enable Register PIO Glitch Input Filter Disable Register PIO Glitch Input Filter Status Register Reserved PIO Set Output Data Register PIO Clear Output Data Register PIO Output Data Status Register PIO Pin Data Status Register (3) (2) (1) Name PIO_PER PIO_PDR PIO_PSR Access Write-only Write-only Read-only Reset Value – – 0x0000 0000 PIO_OER PIO_ODR PIO_OSR Write-only Write-only Read-only – – 0x0000 0000 PIO_IFER PIO_IFDR PIO_IFSR Write-only Write-only Read-only – – 0x0000 0000 PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR Write-only Write-only Read-only Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only – – 0x0000 0000 PIO Interrupt Enable Register PIO Interrupt Disable Register PIO Interrupt Mask Register PIO Interrupt Status Register (4) – – 0x0000 0000 0x0000 0000 – – 0x0000 0000 PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR PIO Multi-driver Enable Register PIO Multi-driver Disable Register PIO Multi-driver Status Register Reserved PIO Pull-up Disable Register PIO Pull-up Enable Register PIO Pad Pull-up Status Register Reserved PIO Peripheral A Select Register(5) PIO Peripheral B Select Register(5) PIO AB Status Register(5) PIO_PUDR PIO_PUER PIO_PUSR Write-only Write-only Read-only – – 0x0000 0000 PIO_ASR PIO_BSR PIO_ABSR Write-only Write-only Read-only – – 0x0000 0000 354 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 27-2. Offset 0x007C to 0x009C 0x00A0 0x00A4 0x00A8 0x00AC Notes: 1. 2. 3. 4. PIO Register Mapping (Continued) Register Reserved PIO Output Write Enable PIO Output Write Disable PIO Output Write Status Register PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only – – 0x0000 0000 Name Access Reset Value Reserved Reset value of PIO_PSR depends on the product implementation. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. Reset value of PIO_PDSR depends on the level of the I/O lines. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register. 355 1768G–ATARM–29-Sep-06 27.6.1 Name: PIO Enable Register PIO_PER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 27.6.2 Name: Access Type: 31 PIO Disable Register PIO_PDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 356 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27.6.3 Name: Access Type: 31 PIO Status Register PIO_PSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive). 27.6.4 Name: Access Type: 31 PIO Output Enable Register PIO_OER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line. 357 1768G–ATARM–29-Sep-06 27.6.5 Name: PIO Output Disable Register PIO_ODR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. 27.6.6 Name: Access Type: 31 PIO Output Status Register PIO_OSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output. 358 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27.6.7 Name: Access Type: 31 PIO Input Filter Enable Register PIO_IFER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 27.6.8 Name: Access Type: 31 PIO Input Filter Disable Register PIO_IFDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line. 359 1768G–ATARM–29-Sep-06 27.6.9 Name: PIO Input Filter Status Register PIO_IFSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 27.6.10 Name: Access Type: 31 PIO Set Output Data Register PIO_SODR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line. 360 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27.6.11 Name: Access Type: 31 PIO Clear Output Data Register PIO_CODR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 27.6.12 Name: Access Type: 31 PIO Output Data Status Register PIO_ODSR Read-only or Read/Write 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1. 361 1768G–ATARM–29-Sep-06 27.6.13 Name: PIO Pin Data Status Register PIO_PDSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 27.6.14 Name: Access Type: 31 PIO Interrupt Enable Register PIO_IER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line. 362 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27.6.15 Name: Access Type: 31 PIO Interrupt Disable Register PIO_IDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 27.6.16 Name: Access Type: 31 PIO Interrupt Mask Register PIO_IMR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line. 363 1768G–ATARM–29-Sep-06 27.6.17 Name: PIO Interrupt Status Register PIO_IMR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Input Change Interrupt Mask 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 27.6.18 Name: Access Type: 31 PIO Multi-driver Enable Register PIO_MDER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Multi Drive Enable 0 = No effect. 1 = Enables Multi Drive on the I/O line. 364 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27.6.19 Name: Access Type: 31 PIO Multi-driver Disable Register PIO_MDDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Multi Drive Disable 0 = No effect. 1 = Disables Multi Drive on the I/O line. 27.6.20 Name: Access Type: 31 PIO Multi-driver Status Register PIO_MDSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Multi Drive Status 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 365 1768G–ATARM–29-Sep-06 27.6.21 Name: PIO Pull Up Disable Register PIO_PUDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Pull Up Disable 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 27.6.22 Name: Access Type: 31 PIO Pull Up Enable Register PIO_PUER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Pull Up Enable 0 = No effect. 1 = Enables the pull up resistor on the I/O line. 366 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27.6.23 Name: Access Type: 31 PIO Pad Pull Up Status Register PIO_PUSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Pull Up Status 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 27.6.24 Name: Access Type: 31 PIO Peripheral A Select Register PIO_ASR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Peripheral A Select 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function. 367 1768G–ATARM–29-Sep-06 27.6.25 Name: PIO Peripheral B Select Register PIO_BSR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Peripheral B Select 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. 27.6.26 Name: Access Type: 31 PIO Peripheral AB Status Register PIO_ABSR Read-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Peripheral A B Status 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B. 368 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 27.6.27 Name: Access Type: 31 PIO Output Write Enable Register PIO_OWER Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Output Write Enable 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 27.6.28 Name: Access Type: 31 PIO Output Write Disable Register PIO_OWDR Write-only 30 29 28 27 26 25 24 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Output Write Disable 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line. 369 1768G–ATARM–29-Sep-06 27.6.29 Name: PIO Output Write Status Register PIO_OWSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0 - P31: Output Write Status 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line. 370 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 28. Serial Peripheral Interface (SPI) 28.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also allows communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the master that controls the data flow, while the other system acts as the slave, having data shifted into and out of it by the master. Different CPUs can take turn being masters (Multiple Master Protocol versus Single Master Protocol where one CPU is always the master while all of the others are always slaves), and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. • Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. • Slave Select (NSS): This control line allows slaves to be turned on and off by hardware. The main features of the SPI are: • Supports Communication with Serial External Devices – 4 Chip Selects with External Decoder Support Allow Communication with Up to 15 Peripherals – Serial Memories, such as DataFlash and 3-wire EEPROMs – Serial Peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External Co-processors • Master or Slave Serial Peripheral Bus Interface – 8- to 16-bit Programmable Data Length Per Chip Select – Programmable Phase and Polarity Per Chip Select – Programmable Transfer Delays Between Consecutive Transfers and Between Clock and Data Per Chip Select – Programmable Delay Between Consecutive Transfers – Selectable Mode Fault Detection • Connection to PDC Channel Capabilities Optimizes Data Transfers – One Channel for the Receiver, One Channel for the Transmitter – Next Buffer Support 371 1768G–ATARM–29-Sep-06 28.2 Block Diagram Figure 28-1. Block Diagram ASB APB Bridge PDC APB SPCK MISO MOSI SPI Interface PIO NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 PMC MCK SPI Interrupt 372 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 28.3 Application Block Diagram Figure 28-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS Table 28-1. Signal Description Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input 373 1768G–ATARM–29-Sep-06 28.4 28.4.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. 28.4.2 Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first have to configure the PMC to enable the SPI clock. 28.4.3 Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI. 28.5 28.5.1 Functional Description Master Mode Operations When configured in Master Mode, the Serial Peripheral Interface controls data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select(s) to the slave(s) and the serial clock (SPCK). After enabling the SPI, a data transfer begins when the core writes to the SPI_TDR (Transmit Data Register). Transmit and Receive buffers maintain the data flow at a constant rate with a reduced requirement for high-priority interrupt servicing. When new data is available in the SPI_TDR, the SPI continues to transfer data. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error (OVRES) flag is set. Note: As long as this flag is set, no data is loaded in the SPI_RDR. The user has to read the status register to clear it. The programmable delay between the activation of the chip select and the start of the data transfer (DLYBS), as well as the delay between each data transfer (DLYBCT), can be programmed for each of the four external chip selects. All data transfer characteristics, including the two timing values, are programmed in registers SPI_CSR0 to SPI_CSR3 (Chip Select Registers). In Master Mode, the peripheral selection can be defined in two different ways: • Fixed Peripheral Select: SPI exchanges data with only one peripheral • Variable Peripheral Select: Data can be exchanged with more than one peripheral Figure 28-7 and Figure 28-8 show the operation of the SPI in Master Mode. For details concerning the flag and control bits in these diagrams, see the ”Serial Peripheral Interface (SPI) User Interface” on page 382 and the subsequent register descriptions. 28.5.1.1 Fixed Peripheral Select This mode is used for transferring memory blocks without the extra overhead in the transmit data register to determine the peripheral. Fixed Peripheral Select is activated by setting bit PS to zero in SPI_MR (Mode Register). The peripheral is defined by the PCS field in SPI_MR. 374 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 This option is only available when the SPI is programmed in Master Mode. 28.5.1.2 Variable Peripheral Select Variable Peripheral Select is activated by setting bit PS to one. The PCS field in SPI_TDR is used to select the destination peripheral. The data transfer characteristics are changed when the selected peripheral changes, according to the associated chip select register. The PCS field in the SPI_MR has no effect. This option is only available when the SPI is programmed in Master Mode. 28.5.1.3 Chip Selects The Chip Select lines are driven by the SPI only if it is programmed in Master Mode. These lines are used to select the destination peripheral. The PCSDEC field in SPI_MR (Mode Register) selects one to four peripherals (PCSDEC = 0) or up to 15 peripherals (PCSDEC = 1). If Variable Peripheral Select is active, the chip select signals are defined for each transfer in the PCS field in SPI_TDR. Chip select signals can thus be defined independently for each transfer. If Fixed Peripheral Select is active, Chip Select signals are defined for all transfers by the field PCS in SPI_MR. If a transfer with a new peripheral is necessary, the software must wait until the current transfer is completed, then change the value of PCS in SPI_MR before writing new data in SPI_TDR. The value on the NPCS pins at the end of each transfer can be read in the SPI_RDR (Receive Data Register). By default, all NPCS signals are high (equal to one) before and after each transfer. 28.5.1.4 Clock Generation and Transfer Delays The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock divided by 32 (if DIV32 is set in the Mode Register) by a value between 4 and 510. The divisor is defined in the SCBR field in each Chip Select Register. The transfer speed can thus be defined independently for each chip select signal. Figure 28-3 shows a chip select transfer change and consecutive transfers on the same chip selects. Three delays can be programmed to modify the transfer waveforms: • Delay between chip selects, programmable only once for all the chip selects by writing the field DLYBCS in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. • Delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed until after the chip select has been asserted. • Delay between consecutive transfers, independently programmable for each chip select by writing the field DLYBCT. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. 375 1768G–ATARM–29-Sep-06 Figure 28-3. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 28.5.1.5 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is disabled until re-enabled by bit SPIEN in the SPI_CR (Control Register). By default, Mode Fault Detection is enabled. It is disabled by setting the MODFDIS bit in the SPI Mode Register. 376 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 28.5.1.6 Master Mode Flow Diagram Figure 28-4. Master Mode Flow Diagram SPI Enable 1 TDRE 0 0 PS 1 Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral NPCS = SPI_TDR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT TDRE 0 1 NPCS = 0xF PS 1 0 Fixed peripheral Variable peripheral Same peripheral Delay DLYBCS SPI_TDR(PCS) New peripheral NPCS = 0xF Delay DLYBCS NPCS = SPI_TDR(PCS) 377 1768G–ATARM–29-Sep-06 28.5.1.7 Master Mode Block Diagram Figure 28-5. Master Mode Block Diagram SPI_MR(DIV32) MCK 0 1 SPCK Clock Generator SPI_CSRx[15:0] SPCK MCK/32 SPIDIS SPIEN S Q R SPI_RDR PCS LSB MISO RD MSB MOSI Serializer SPI_TDR PCS TD NPCS3 NPCS2 SPI_MR(PS) NPCS1 NPCS0 1 SPI_MR(PCS) 0 SPI_MR(MSTR) SPI_SR M O D F T D R E R D R F O V R E S P I E N S SPI_IER SPI_IDR SPI_IMR SPI Interrupt 378 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 28.5.2 SPI Slave Mode In Slave Mode, the SPI waits for NSS to go active low before receiving the serial clock from an external master. In Slave Mode, CPOL, NCPHA and BITS fields of SPI_CSR0 are used to define the transfer characteristics. The other Chip Select Registers are not used in Slave Mode. In Slave Mode, the low and high pulse durations of the input clock on SPCK must be longer than two Master Clock periods. Figure 28-6. Slave Mode Block Diagram SPCK NSS SPIDIS SPIEN S Q R SPI_RDR RD LSB MOSI MSB MISO Serializer SPI_TDR TD SPI_SR S P I E N S T D R E R D R F O V R E SPI_IER SPI_IDR SPI_IMR SPI Interrupt 379 1768G–ATARM–29-Sep-06 28.5.3 Data Transfer Four modes are used for data transfers. These modes correspond to combinations of a pair of parameters called clock polarity (CPOL) and clock phase (NCPHA) that determine the edges of the clock signal on which the data are driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 28-2 shows the four modes and corresponding parameter settings. Table 28-2. SPI Bus Protocol Mode SPI Mode 0 1 2 3 CPOL 0 0 1 1 NCPHA 1 0 1 0 Figure 28-7 and Figure 28-8 show examples of data transfers. Figure 28-7. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) (Mode 1) SPCK (CPOL = 1) (Mode 3) MOSI (from master) 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. 380 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 28-8. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) (Mode 0) SPCK (CPOL = 1) (Mode 2) MOSI (from master) 1 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB MISO (from slave) * MSB 6 5 4 3 2 1 LSB NSS (to slave) * Not defined but normally LSB of previous character transmitted. 381 1768G–ATARM–29-Sep-06 28.6 Serial Peripheral Interface (SPI) User Interface SPI Register Mapping Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 Read/Write Read/Write Read/Write Read/Write 0x0 0x0 0x0 0x0 Register Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0 Table 28-3. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x40 - 0xFF 0x100 - 0x124 382 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 28.6.1 Name: Access Type: 31 SPI Control Register SPI_CR Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled • SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. 383 1768G–ATARM–29-Sep-06 28.6.2 Name: SPI Mode Register SPI_MR Read/Write 30 29 28 27 26 25 24 Access Type: 31 DLYBCS 23 22 21 20 19 18 17 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 LLB – – MODFDIS DIV32 PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. • PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 16 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 15*. *Note: The 16th state corresponds to a state in which all chip selects are inactive. This allows a different clock configuration to be defined by each chip select register. • DIV32: Clock Selection 0 = The SPI operates at MCK. 1 = The SPI operates at MCK/32. • MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. 384 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • LLB: Local Loopback Enable 0 = Local loopback path disabled 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods (or 192 MCK periods if DIV32 is set) will be inserted by default. Otherwise, the following equation determines the delay: If DIV32 is 0: Delay Between Chip Selects = DLYBCS ⁄ MCK If DIV32 is 1: Delay Between Chip Selects = DLYBCS × 32 ⁄ MCK NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 385 1768G–ATARM–29-Sep-06 28.6.3 Name: SPI Receive Data Register SPI_RDR Read-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 RD 7 6 5 4 3 2 1 0 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. 386 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 28.6.4 Name: Access Type: 31 SPI Transmit Data Register SPI_TDR Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 TD 7 6 5 4 3 2 1 0 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 387 1768G–ATARM–29-Sep-06 28.6.5 Name: SPI Status Register SPI_SR Read-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 SPIENS 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. • TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. • MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. • OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. • ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR or SPI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR or SPI_RNCR. • ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR or SPI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR or SPI_TNCR. • RXBUFF: RX Buffer Full 0 = SPI_RCR or SPI_RNCR have a value other than 0. 1 = Both SPI_RCR and SPI_RNCR have a value of 0. 388 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • TXBUFE: TX Buffer Empty 0 = SPI_TCR or SPI_TNCR have a value other than 0. 1 = Both SPI_TCR and SPI_TNCR have a value of 0. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. 389 1768G–ATARM–29-Sep-06 28.6.6 Name: SPI Interrupt Enable Register SPI_IER Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full Interrupt Enable • TDRE: SPI Transmit Data Register Empty Interrupt Enable • MODF: Mode Fault Error Interrupt Enable • OVRES: Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 390 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 28.6.7 Name: Access Type: 31 SPI Interrupt Disable Register SPI_IDR Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full Interrupt Disable • TDRE: SPI Transmit Data Register Empty Interrupt Disable • MODF: Mode Fault Error Interrupt Disable • OVRES: Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 391 1768G–ATARM–29-Sep-06 28.6.8 Name: SPI Interrupt Mask Register SPI_IMR Read-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full Interrupt Mask • TDRE: SPI Transmit Data Register Empty Interrupt Mask • MODF: Mode Fault Error Interrupt Mask • OVRES: Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. 392 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 28.6.9 Name: Access Type: 31 SPI Chip Select Register SPI_CSR0... SPI_CSR3 Read/Write 30 29 28 27 26 25 24 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 7 6 5 4 3 2 1 0 BITS – – NCPHA CPOL • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. • NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 8 9 10 11 12 13 14 15 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved 393 1768G–ATARM–29-Sep-06 • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 2 to 255 in the field SCBR. The following equation determines the SPCK baud rate: If DIV32 is 0: SPCK Baudrate = MCK ⁄ ( 2 × SCBR ) If DIV32 is 1: SPCK Baudrate = MCK ⁄ ( 64 × SCBR ) Giving SCBR a value of zero or one disables the baud rate generator. SPCK is disabled and assumes its inactive state value. No serial transfers may occur. At reset, baud rate is disabled. • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: If DIV32 is 0: Delay Before SPCK = DLYBS ⁄ MCK If DIV32 is 1: Delay Before SPCK = 32 × DLYBS ⁄ MCK • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, a minimum delay of four MCK cycles are inserted (or 128 MCK cycles when DIV32 is set) between two consecutive characters. Otherwise, the following equation determines the delay: If DIV32 is 0: Delay Between Consecutive Transfers = 32 × DLYBCT ⁄ MCK If DIV32 is 1: Delay Between Consecutive Transfers = 1024 × DLYBCT ⁄ MCK 394 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 29. Two-wire Interface (TWI) 29.1 Overview The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel two-wire bus serial EEPROM. The TWI is programmable as a master with sequential or single-byte access. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. The main features of the TWI are: • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential Read/Write operations 29.2 Block Diagram Figure 29-1. Block Diagram APB Bridge TWCK PIO Two-wire Interface TWD PMC MCK TWI Interrupt AIC 29.3 Application Block Diagram Figure 29-2. Application Block Diagram VDD R TWD TWCK R Host with TWI Interface AT24LC16 U1 Slave 1 AT24LC16 U2 Slave 2 LCD Controller U3 Slave 3 395 1768G–ATARM–29-Sep-06 Table 29-1. Pin Name TWD TWCK I/O Lines Description Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output 29.4 29.4.1 Product Dependencies I/O Lines Both TWD and TWCK are bi-directional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 29-2 on page 395). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or opencollector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: • Program the PIO controller to: – Dedicate TWD and TWCK as peripheral lines. – Define TWD and TWCK as open-drain. 29.4.2 Power Management • Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 29.4.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. 29.5 29.5.1 Functional Description Transfer Format The data put on the TWD line must be eight bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 29-4 on page 397). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 29-3 on page 397). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. 396 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 29-3. START and STOP Conditions TWD TWCK Start Stop Figure 29-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 29.5.2 Modes of Operation The TWI has two modes of operations: • Master transmitter mode • Master receiver mode The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks. 29.5.3 Transmitting Data After the master initiates a Start condition, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write operation (transmit operation). If the bit is 1, it indicates a request for data read (receive operation). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in the control register starts the transmission. The data is shifted in the internal shifter and when an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Figure 296 on page 398). The master generates a stop condition to end the transfer. The read sequence begins by setting the START bit. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address). The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, the IADRSZ must be set to 0. For 397 1768G–ATARM–29-Sep-06 slave address higher than seven bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). Figure 29-5. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A DATA A P One byte internal address TWD S DADR W A IADR(7:0) A DATA A P Figure 29-6. Master Write with One Byte Internal Address and Multiple Data Bytes TWD S DADR W A IADR(7:0) A DATA A DATA A DATA A P TXCOMP Write THR TXRDY Write THR Write THR Write THR Figure 29-7. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A S DADR R A DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A S DADR R A DATA N P N P One byte internal address TWD S DADR W A IADR(7:0) A S DADR R A DATA N P Figure 29-8. Master Read with One Byte Internal Address and Multiple Data Bytes TWD S DADR W A IADR(7:0) A S DADR R A DATA A DATA N P TXCOMP Write START Bit RXRDY Write STOP Bit Read RHR Read RHR 398 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • S = Start • P = Stop • W = Write • R = Read • A = Acknowledge • N = Not Acknowledge • DADR= Device Address • IADR = Internal Address Figure 29-9 shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 29-9. Internal Address Usage S T A R T W R I T E S T O P Device Address 0 M S B FIRST WORD ADDRESS SECOND WORD ADDRESS DATA LRA S/C BW K M S B A C K LA SC BK A C K 29.5.4 Read/Write Flowcharts The following flowcharts shown in Figure 29-10 on page 400 and in Figure 29-11 on page 401 give examples for read and write operations in Master Mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. 399 1768G–ATARM–29-Sep-06 Figure 29-10. TWI Write in Master Mode START Set TWI clock: TWI_CWGR = clock Set the control register: - Master enable TWI_CR = TWI_MSEN Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Write ==> bit MREAD = 0 Internal address size = 0? Set the internal address TWI_IADR = address Yes Load transmit register TWI_THR = Data to send Start the transfer TWI_CR = TWI_START Read status register TWI_THR = data to send TXRDY = 0? Yes Data to send? Yes Stop the transfer TWI_CR = TWI_STOP Read status register TXCOMP = 0? END 400 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 29-11. TWI Read in Master Mode START Set TWI clock: TWI_CWGR = clock Set the control register: - Master enable TWI_CR = TWI_MSEN Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Read ==> bit MREAD = 0 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = TWI_START Read status register RXRDY = 0? Yes Data to read? Yes Stop the transfer TWI_CR = TWI_STOP Read status register Yes TXCOMP = 0? END 401 1768G–ATARM–29-Sep-06 29.6 Two-wire Interface (TWI) User Interface TWI Register Mapping Register Control Register Master Mode Register Reserved Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR Read/Write Read/Write Read-only Write-only Write-only Read-only Read-only Read/Write 0x0000 0x0000 0x0008 N/A N/A 0x0000 0x0000 0x0000 Name TWI_CR TWI_MMR Access Write-only Read/Write Reset Value N/A 0x0000 Table 29-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 402 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 29.6.1 TWI Control Register TWI_CR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 MSDIS 26 – 18 – 10 – 2 MSEN 25 – 17 – 9 – 1 STOP 24 – 16 – 8 – 0 START Register Name: Access Type: 31 – 23 – 15 – 7 SWRST • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. • STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read or write mode. In single data byte master read or write, the START and STOP must both be set. In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission. In master read mode, if a NACK bit is received, the STOP is automatically performed. In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. • MSEN: TWI Master Transfer Enabled 0 = No effect. 1 = If MSDIS = 0, the master data transfer is enabled. • MSDIS: TWI Master Transfer Disabled 0 = No effect. 1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset. 403 1768G–ATARM–29-Sep-06 29.6.2 TWI Master Mode Register TWI_MMR Read/Write 30 – 22 29 – 21 28 – 20 27 – 19 DADR 11 – 3 – 26 – 18 25 – 17 24 – 16 Register Name: Address Type: 31 – 23 – 15 – 7 – 14 – 6 – 13 – 5 – 12 MREAD 4 – 10 – 2 – 9 IADRSZ 1 – 8 0 – • IADRSZ: Internal Device Address Size IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address (Byte command protocol) One-byte internal device address Two-byte internal device address Three-byte internal device address • MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. • DADR: Device Address The device address is used in Master Mode to access slave devices in read or write mode. 404 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 29.6.3 TWI Internal Address Register TWI_IADR Read/Write 30 – 22 29 – 21 28 – 20 IADR 15 14 13 12 IADR 7 6 5 4 IADR 3 2 1 0 11 10 9 8 27 – 19 26 – 18 25 – 17 24 – 16 Register Name: Access Type: 31 – 23 • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. Low significant byte address in 10-bit mode addresses. 29.6.4 TWI Clock Waveform Generator Register TWI_CWGR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CHDIV 7 6 5 4 CLDIV 3 2 1 0 27 – 19 – 11 26 – 18 25 – 17 CKDIV 9 24 – 16 Register Name: Access Type: 31 – 23 – 15 10 8 • CLDIV: Clock Low Divider The TWCK low period is defined as follows: T low = ( ( CLDIV × 2 CKDIV ) + 3 ) × T MCK • CHDIV: Clock High Divider The TWCK high period is defined as follows: T high = ( ( CHDIV × 2 CKDIV ) + 3 ) × T MCK • CKDIV: Clock Divider The CKDIV is used to increase both TWCK high and low periods. 405 1768G–ATARM–29-Sep-06 29.6.5 TWI Status Register TWI_SR Read-only 30 – 22 – 14 – 6 OVRE 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 TXRDY 25 – 17 – 9 – 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP Register Name: Access Type: 31 – 23 – 15 – 7 UNRE • TXCOMP: Transmission Completed 0 = In master, during the length of the current frame. In slave, from START received to STOP received. 1 = When both holding and shifter registers are empty and STOP condition has been sent (in Master) or when MSEN is set (enable TWI). • RXRDY: Receive Holding Register Ready 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. • TXRDY: Transmit Holding Register Ready 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). • OVRE: Overrun Error 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. • UNRE: Underrun Error 0 = No underrun error 1 = No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in Master Mode. Reset by read in TWI_SR when TXCOMP is set. • NACK: Not Acknowledged 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read. 406 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 29.6.6 TWI Interrupt Enable Register TWI_IER Write-only 30 – 22 – 14 – 6 OVRE 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 TXRDY 25 – 17 – 9 – 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP Register Name: Access Type: 31 – 23 – 15 – 7 UNRE • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • OVRE: Overrun Error • UNRE: Underrun Error • NACK: Not Acknowledge 0 = No effect. 1 = Enables the corresponding interrupt. 407 1768G–ATARM–29-Sep-06 29.6.7 TWI Interrupt Disable Register TWI_IDR Write-only 30 – 22 – 14 – 6 OVRE 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 TXRDY 25 – 17 – 9 – 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP Register Name: Access Type: 31 – 23 – 15 – 7 UNRE • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • OVRE: Overrun Error • UNRE: Underrun Error • NACK: Not Acknowledge 0 = No effect. 1 = Disables the corresponding interrupt. 408 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 29.6.8 TWI Interrupt Mask Register TWI_IMR Read-only 30 – 22 – 14 – 6 OVRE 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 TXRDY 25 – 17 – 9 – 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP Register Name: Access Type: 31 – 23 – 15 – 7 UNRE • TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • OVRE: Overrun Error • UNRE: Underrun Error • NACK: Not Acknowledge 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 29.6.9 TWI Receive Holding Register TWI_RHR Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Register Name: Access Type: 31 – 23 – 15 – 7 • RXDATA: Master or Slave Receive Holding Data 409 1768G–ATARM–29-Sep-06 29.6.10 TWI Transmit Holding Register TWI_THR Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Register Name: Access Type: 31 – 23 – 15 – 7 • TXDATA: Master or Slave Transmit Holding Data 410 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30. Universal Synchronous Asynchronous Receiver Transceiver (USART) 30.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multi-drop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 busses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. Important features of the USART are: • Programmable Baud Rate Generator • 5- to 9-bit Full-duplex Synchronous or Asynchronous Serial Communications – 1, 1.5 or 2 Stop Bits in Asynchronous Mode or 1 or 2 Stop Bits in Synchronous Mode – Parity Generation and Error Detection – Framing Error Detection, Overrun Error Detection – MSB- or LSB-first – Optional Break Generation and Detection – By 8 or by-16 Over-sampling Receiver Frequency – Optional Hardware Handshaking RTS-CTS – Optional Modem Signal Management DTR-DSR-DCD-RI – Receiver Time-out and Transmitter Timeguard – Optional Multi-Drop Mode with Address Generation and Detection • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for Interfacing with Smart Cards – NACK Handling, Error Counter with Repetition and Iteration Limit • IrDA Modulation and Demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Supports Connection of Two Peripheral DMA Controller Channels (PDC) – Offer Buffer Transfer without Processor Intervention 411 1768G–ATARM–29-Sep-06 30.2 Block Diagram Figure 30-1. USART Block Diagram Peripheral Data Controller Channel Channel USART PIO Controller RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS DTR PMC MCK MCK/DIV Modem Signals Control DSR DCD RI SLCK Baud Rate Generator SCK DIV User Interface APB 412 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.3 Application Block Diagram Figure 30-2. Application Block Diagram PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver USART RS232 Drivers Modem PSTN RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers Serial Port Differential Bus 30.4 I/O Lines Description I/O Line Description Description Serial Clock Transmit Serial Data Receive Serial Data Ring Indicator Data Set Ready Data Carrier Detect Data Terminal Ready Clear to Send Request to Send Type I/O I/O Input Input Input Input Output Input Output Low Low Low Low Low Low Active Level Table 30-1. Name SCK TXD RXD RI DSR DCD DTR CTS RTS 30.5 30.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. All the pins of the modems may or may not be implemented on the USART within a product. Frequently, only the USART1 is fully equipped with all the modem signals. For the other USARTs of the product not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART. 413 1768G–ATARM–29-Sep-06 30.5.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. 30.5.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. 30.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes. • 5- to 9-bit full-duplex asynchronous serial communication: – MSB- or LSB-first – 1, 1.5 or 2 stop bits – Parity even, odd, marked, space or none – By-8 or by-16 over-sampling receiver frequency – Optional hardware handshaking – Optional modem signals management – Optional break management – Optional multi-drop serial communication • High-speed 5- to 9-bit full-duplex synchronous serial communication: – MSB- or LSB-first – 1 or 2 stop bits – Parity even, odd, marked, space or none – by 8 or by-16 over-sampling frequency – Optional Hardware handshaking – Optional Modem signals management – Optional Break management – Optional Multi-Drop serial communication • RS485 with driver control signal • ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • InfraRed IrDA Modulation and Demodulation • Test modes – remote loopback, local loopback, automatic echo 414 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: • the Master Clock MCK • A division of the Master Clock, the divider being product dependent, but generally set to 8 • the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 30-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC SCK 30.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over ) CD ) 415 1768G–ATARM–29-Sep-06 This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. Baud Rate Calculation Example Table 30-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 30-2. Baud Rate Example (OVER = 0) Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 97.66 113.93 6 8 8 12 13 20 20 23 24 30 39 40 40 52 53 54 65 81 98 114 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 38 265.31 38 377.19 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% 0.35% 0.06% Error Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 60 000 000 70 000 000 The baud rate is calculated with the following formula: B audRate = MCK ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 – ⎛ --------------------------------------------------⎞ ⎝ ActualBaudRate ⎠ 416 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.6.1.2 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. BaudRate = SelectedClock ------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 30.6.1.3 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- × f Fi where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 30-3. Table 30-3. DI field Di (decimal) Binary and Decimal Values for D 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 30-4. Table 30-4. FI field Fi (decimal Binary and Decimal Values for F 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 30-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 30-5. Fi/Di 1 2 4 8 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 558 558 279 139.5 69.75 774 744 372 186 93 1116 1116 558 279 139.5 1488 1488 744 372 186 1806 1860 930 465 232.5 512 512 256 128 64 768 768 384 192 96 1024 1024 512 256 128 1536 1536 768 384 192 2048 2048 1024 512 256 417 1768G–ATARM–29-Sep-06 Table 30-5. 16 32 12 20 Possible Values for the Fi/Di Ratio (Continued) 23.25 11.62 31 18.6 34.87 17.43 46.5 27.9 46.5 23.25 62 37.2 69.75 34.87 93 55.8 93 46.5 124 74.4 116.2 58.13 155 93 32 16 42.66 25.6 48 24 64 38.4 64 32 85.33 51.2 96 48 128 76.8 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 30-4 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 30-4. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 30.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The reset commands have the same effect as a hardware reset on the corresponding logic. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. 418 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a time guard is programmed, it is handled normally. 30.6.3 30.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. Figure 30-5. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY raises. Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in US_THR while TXRDY is active has no effect and the written character is lost. 419 1768G–ATARM–29-Sep-06 Figure 30-6. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 30.6.3.2 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. The number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 30-7 and Figure 30-8 illustrate start detection and character reception when USART operates in asynchronous mode. 420 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 30-7. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 30-8. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 30.6.3.3 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 30-9 illustrates a character reception in synchronous mode. 421 1768G–ATARM–29-Sep-06 Figure 30-9. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 30.6.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 30-10. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 30.6.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multi-drop Mode, see ”Multi-drop Mode” on page 423. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The 422 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 30-6 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. I Table 30-6. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 30-11 illustrates the parity bit status setting and clearing. Figure 30-11. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 30.6.3.6 Multi-drop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x7, the USART runs in Multi-drop mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multi-drop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. 423 1768G–ATARM–29-Sep-06 The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. 30.6.3.7 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 30-12, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. Figure 30-12. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write US_THR TXRDY TXEMPTY Table 30-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 30-7. Maximum Timeguard Length Depending on Baud Rate Bit time µs 833 104 69.4 52.1 34.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 Baud Rate bit/sec 1 200 9 600 14400 19200 28800 424 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 30-7. Maximum Timeguard Length Depending on Baud Rate (Continued) Bit time 29.9 17.9 17.4 8.7 Timeguard 7.63 4.55 4.43 2.21 Baud Rate 33400 56000 57600 115200 30.6.3.8 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. The user can either: • Obtain an interrupt when a time-out is detected after having received at least one character. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. • Obtain a periodic interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 30-13 shows the block diagram of the Receiver Time out feature. Figure 30-13. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 425 1768G–ATARM–29-Sep-06 Table 30-8 gives the maximum time-out period for some standard baud rates.t Table 30-8. Maximum Time-out Period Bit Time µs 1 667 833 417 208 104 69 52 35 30 18 17 5 Time -out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 1 170 1 138 328 Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 56000 57600 200000 30.6.3.9 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 30-14. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 30.6.3.10 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 426 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 30-15 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STP BRK) commands on the TXD line. Figure 30-15. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write US_CR TXRDY TXEMPTY 30.6.3.11 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. 427 1768G–ATARM–29-Sep-06 When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 30.6.3.12 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 30-16. Figure 30-16. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 30-17 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 30-17. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1 Figure 30-18 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only 428 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 30-18. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 30.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 30.6.4.1 ISO7816 Mode overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see ”Baud Rate Generator” on page 415). The USART connects to a smart card. as shown in Figure 30-19. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 30-19. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this for- 429 1768G–ATARM–29-Sep-06 mat and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 30.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 30-20. If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 30-21. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 30-20. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 30-21. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is reset, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 430 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. 30.6.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). 30.6.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 30-22. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2,4 Kbps to 115,2 Kbps. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. 431 1768G–ATARM–29-Sep-06 Figure 30-22. Connection to IrDA Transceivers USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. 30.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 30-9. Table 30-9. Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s IrDA Pulse Duration Pulse Duration (3/16) 78.13 µs 19.53 µs 9.77 µs 4.88 µs 3.26 µs 1.63 µs Figure 30-23 shows an example of character transmission. Figure 30-23. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Start Bit 1 TXD Bit Period 3 16 Bit Period 432 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.6.5.2 IrDA Baud Rate Table 30-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of +/- 1.87% must be met. Table 30-10. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 38 400 38 400 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 2 11 18 22 4 22 36 43 6 33 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% 0.00% 1.38% 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 4.88 4.88 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 30.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 30-24 illustrates the operations of the IrDA demodulator. 433 1768G–ATARM–29-Sep-06 Figure 30-24. IrDA Demodulator Operations MCK RXD Counter Value 6 5 4 3 2 6 6 5 4 3 2 1 0 Pulse Accepted Receiver Input Pulse Rejected Driven Low During 16 Baud Rate Clock Cycles As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 30.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters are possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to an RS485 bus is shown in Figure 30-25. Figure 30-25. Typical Connection to an RS485 bus. USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse of the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 30-26 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. 434 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 30-26. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 30.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 30-11 gives the correspondence of the USART signals with modem connection standards. Table 30-11. Circuit References USART pin TXD RTS DTR RXD CTS DSR DCD RI V24 2 4 20 3 5 6 8 22 CCITT 103 105 108.2 104 106 107 109 125 Direction From terminal to modem From terminal to modem From terminal to modem From modem to terminal From terminal to modem From terminal to modem From terminal to modem From terminal to modem The control of the RTS and DTR output pins is performed by witting the Control Register (US_CR) with the RTSDIS, RTSEN, DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable commands force the corresponding pin to its active level, i.e. low. 435 1768G–ATARM–29-Sep-06 The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. 30.6.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 30.6.8.1 Normal Mode As a reminder, the normal mode simply connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 30-27. Normal Mode Configuration RXD Receiver TXD Transmitter 30.6.8.2 Automatic Echo Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 30-28. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 30-28. Automatic Echo RXD Receiver TXD Transmitter 30.6.8.3 Local Loopback The local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 30-29. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. 436 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 30-29. Local Loopback RXD Receiver Transmitter 1 TXD 30.6.8.4 Remote Loopback Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 30-30. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 30-30. Remote Loopback Receiver 1 RXD TXD Transmitter 437 1768G–ATARM–29-Sep-06 30.7 USART User Interface USART Memory Map Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Reserved Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR – US_FIDI US_NER – US_IF – Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write Read/Write Read/Write – Read/Write Read-only – Read/Write – Reset State – – – – 0x0 – 0x0 – 0x0 0x0 0x0 – 0x174 – – 0x0 – Table 30-12. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x2C to 0x3C 0x0040 0x0044 0x0048 0x004C 0x5C to 0xFC 0x100 to 0x128 Reserved for PDC Registers – – – 438 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.7.1 Name: Access Type: 31 – 23 – 15 RETTO 7 TXDIS USART Control Register US_CR Write-only 30 – 22 – 14 RSTNACK 6 TXEN 29 – 21 – 13 RSTIT 5 RXDIS 28 – 20 – 12 SENDA 4 RXEN 27 – 19 RTSDIS 11 STTTO 3 RSTTX 26 – 18 RTSEN 10 STPBRK 2 RSTRX 25 – 17 DTRDIS 9 STTBRK 1 – 24 – 16 DTREN 8 RSTSTA 0 – • RSTRX: Reset Receiver 0 = No effect. 1 = Resets the receiver. • RSTTX: Reset Transmitter 0 = No effect. 1 = Resets the transmitter. • RXEN: Receiver Enable 0 = No effect. 1 = Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0 = No effect. 1 = Disables the receiver. • TXEN: Transmitter Enable 0 = No effect. 1 = Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0 = No effect. 1 = Disables the transmitter. • RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR. 439 1768G–ATARM–29-Sep-06 • STTBRK: Start Break 0 = No effect. 1 = Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0 = No effect. 1 = Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0 = No effect 1 = Starts waiting for a character before clocking the time-out counter. • SENDA: Send Address 0 = No effect. 1 = In Multi-drop Mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0 = No effect. 1 = Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0 = No effect 1 = Resets NACK in US_CSR. • RETTO: Rearm Time-out 0 = No effect 1 = Restart Time-out • DTREN: Data Terminal Ready Enable 0 = No effect. 1 = Drives the pin DTR at 0. • DTRDIS: Data Terminal Ready Disable 0 = No effect. 1 = Drives the pin DTR to 1. • RTSEN: Request to Send Enable 0 = No effect. 1 = Drives the pin RTS to 0. 440 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • RTSDIS: Request to Send Disable 0 = No effect. 1 = Drives the pin RTS to 1. 441 1768G–ATARM–29-Sep-06 30.7.2 Name: USART Mode Register US_MR Read/Write 30 – 22 – 14 CHMODE 7 CHRL 6 5 USCLKS 29 – 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 – 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Access Type: 31 – 23 – 15 18 CLKO 10 PAR 2 16 MSBF 8 SYNC 0 1 USART_MODE • USART_MODE USART_MODE 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 x 0 1 0 1 0 1 0 1 0 x Mode of the USART Normal RS485 Hardware Handshaking Modem IS07816 Protocol: T = 0 Reserved IS07816 Protocol: T = 1 Reserved IrDA Reserved • USCLKS: Clock Selection USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK / DIV Reserved SCK 442 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • CHRL: Character Length. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits • SYNC: Synchronous Mode Select 0 = USART operates in Asynchronous Mode. 1 = USART operates in Synchronous Mode • PAR: Parity Type PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multi-drop mode • NBSTOP: Number of Stop Bits NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin. • MSBF: Bit Order 0 = Least Significant Bit is sent/received first. 1 = Most Significant Bit is sent/received first. 443 1768G–ATARM–29-Sep-06 • MODE9: 9-bit Character Length 0 = CHRL defines character length. 1 = 9-bit character length. • CKLO: Clock Output Select 0 = The USART does not drive the SCK pin. 1 = The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0 = 16x Oversampling. 1 = 8x Oversampling. • INACK: Inhibit Non Acknowledge 0 = The NACK is generated. 1 = The NACK is not generated. • DSNACK: Disable Successive NACK 0 = NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1 = Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T = 0. • FILTER: Infrared Receive Line Filter 0 = The USART does not filter the receive line. 1 = The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). 444 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.7.3 Name: Access Type: 31 – 23 – 15 – 7 PARE USART Interrupt Enable Register US_IER Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITERATION 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • ENDRX: End of Receive Transfer Interrupt Enable • ENDTX: End of Transmit Interrupt Enable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITERATION: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Enable • RXBUFF: Buffer Full Interrupt Enable • NACK: Non Acknowledge Interrupt Enable • RIIC: Ring Indicator Input Change Enable • DSRIC: Data Set Ready Input Change Enable • DCDIC: Data Carrier Detect Input Change Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 445 1768G–ATARM–29-Sep-06 30.7.4 Name: USART Interrupt Disable Register US_IDR Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITERATION 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • ENDRX: End of Receive Transfer Interrupt Disable • ENDTX: End of Transmit Interrupt Disable • OVRE: Overrun Error Interrupt Disable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITERATION: Iteration Interrupt Disable • TXBUFE: Buffer Empty Interrupt Disable • RXBUFF: Buffer Full Interrupt Disable • NACK: Non Acknowledge Interrupt Disable • RIIC: Ring Indicator Input Change Disable • DSRIC: Data Set Ready Input Change Disable • DCDIC: Data Carrier Detect Input Change Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 446 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.7.5 Name: Access Type: 31 – 23 – 15 – 7 PARE USART Interrupt Mask Register US_IMR Read-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITERATION 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • ENDRX: End of Receive Transfer Interrupt Mask • ENDTX: End of Transmit Interrupt Mask • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITERATION: Iteration Interrupt Mask • TXBUFE: Buffer Empty Interrupt Mask • RXBUFF: Buffer Full Interrupt Mask • NACK: Non Acknowledge Interrupt Mask • RIIC: Ring Indicator Input Change Mask • DSRIC: Data Set Ready Input Change Mask • DCDIC: Data Carrier Detect Input Change Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 447 1768G–ATARM–29-Sep-06 30.7.6 Name: USART Channel Status Register US_CSR Read-only 30 – 22 DCD 14 – 6 FRAME 29 – 21 DSR 13 NACK 5 OVRE 28 – 20 RI 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITERATION 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 CTS 15 – 7 PARE • RXRDY: Receiver Ready 0 = No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1 = At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0 = A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1 = There is no character in the US_THR. • RXBRK: Break Received/End of Break 0 = No Break received or End of Break detected since the last RSTSTA. 1 = Break Received or End of Break detected since the last RSTSTA. • ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the Receive PDC channel is inactive. 1 = The End of Transfer signal from the Receive PDC channel is active. • ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the Transmit PDC channel is inactive. 1 = The End of Transfer signal from the Transmit PDC channel is active. • OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0 = No stop bit has been detected low since the last RSTSTA. 1 = At least one stop bit has been detected low since the last RSTSTA. 448 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • PARE: Parity Error 0 = No parity error has been detected since the last RSTSTA. 1 = At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0 = There has not been a time-out since the last Start Time-out command or the Time-out Register is 0. 1 = There has been a time-out since the last Start Time-out command. • TXEMPTY: Transmitter Empty 0 = There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1 = There is at least one character in either US_THR or the Transmit Shift Register. • ITERATION: Max number of Repetitions Reached 0 = Maximum number of repetitions has not been reached since the last RSIT. 1 = Maximum number of repetitions has been reached since the last RSIT. • TXBUFE: Transmission Buffer Empty 0 = The signal Buffer Empty from the Transmit PDC channel is inactive. 1 = The signal Buffer Empty from the Transmit PDC channel is active. • RXBUFF: Reception Buffer Full 0 = The signal Buffer Full from the Receive PDC channel is inactive. 1 = The signal Buffer Full from the Receive PDC channel is active. • NACK: Non Acknowledge 0 = No Non Acknowledge has not been detected since the last RSTNACK. 1 = At least one Non Acknowledge has been detected since the last RSTNACK. • RIIC: Ring Indicator Input Change Flag 0 = No input change has been detected on the RI pin since the last read of US_CSR. 1 = At least one input change has been detected on the RI pin since the last read of US_CSR. • DSRIC: Data Set Ready Input Change Flag 0 = No input change has been detected on the DSR pin since the last read of US_CSR. 1 = At least one input change has been detected on the DSR pin since the last read of US_CSR. • DCDIC: Data Carrier Detect Input Change Flag 0 = No input change has been detected on the DCD pin since the last read of US_CSR. 1 = At least one input change has been detected on the DCD pin since the last read of US_CSR. • CTSIC: Clear to Send Input Change Flag 0 = No input change has been detected on the CTS pin since the last read of US_CSR. 1 = At least one input change has been detected on the CTS pin since the last read of US_CSR. 449 1768G–ATARM–29-Sep-06 • RI: Image of RI Input 0 = RI is at 0. 1 = RI is at 1. • DSR: Image of DSR Input 0 = DSR is at 0 1 = DSR is at 1. • DCD: Image of DCD Input 0 = DCD is at 0. 1 = DCD is at 1. • CTS: Image of CTS Input 0 = CTS is at 0. 1 = CTS is at 1. 450 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.7.7 Name: Access Type: 31 – 23 – 15 – 7 USART Receive Holding Register US_RHR Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 RXCHR 0 • RXCHR: Received Character Last character received if RXRDY is set. 30.7.8 Name: Access Type: 31 – 23 – 15 – 7 USART Transmit Holding Register US_THR Write-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 TXCHR 0 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 451 1768G–ATARM–29-Sep-06 30.7.9 Name: USART Baud Rate Generator Register US_BRGR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CD 7 6 5 4 CD 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 • CD: Clock Divider USART_MODE ≠ ISO7816 CD OVER = 0 0 1 to 65535 Baud Rate = Selected Clock/16/CD SYNC = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816 30.7.10 Name: USART Receiver Time-out Register US_RTOR Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 15 – 22 – 14 – 21 – 13 – 20 – 12 TO – 19 – 11 – 18 – 10 – 17 – 9 – 16 – 8 7 6 5 4 TO 3 2 1 0 • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 452 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 30.7.11 Name: Access Type: 31 – 23 – 15 – 7 USART Transmitter Timeguard Register US_TTGR Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TG 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 30.7.12 Name: Access Type: Reset Value : 31 – 23 – 15 – 7 USART FI DI RATIO Register US_FIDI Read/Write 0x174 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FI_DI_RATIO 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 – 9 FI_DI_RATIO 1 24 – 16 – 8 2 0 • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1-2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 453 1768G–ATARM–29-Sep-06 30.7.13 Name: USART Number of Errors Register US_NER Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 NB_ERRORS 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 30.7.14 Name: Access Type: 31 – 23 – 15 – 7 USART IrDA FILTER Register US_IF Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IRDA_FILTER 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 454 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31. Serial Synchronous Controller (SSC) 31.1 Overview The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. Transfers contain up to 16 data of up to 32 bits. they can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: • CODECs in master or slave mode • DAC through dedicated serial interface, particularly I2S • Magnetic card reader Features of the SSC are: • Provides Serial Synchronous Communication Links Used in Audio and Telecom Applications • Contains an Independent Receiver and Transmitter and a Common Clock Divider • Interfaced with Two PDC Channels (DMA Access) to Reduce Processor Overhead • Offers a Configurable Frame Sync and Data Length • Receiver and Transmitter can be Programmed to Start Automatically or on Detection of Different Event on the Frame Sync Signal • Receiver and Transmitter Include a Data Signal, a Clock Signal and a Frame Synchronization Signal 455 1768G–ATARM–29-Sep-06 31.2 Block Diagram Figure 31-1. Block Diagram ASB APB Bridge PDC APB TF TK TD SSC Interface PIO RF RK Interrupt Control RD PMC MCK SSC Interrupt 31.3 Application Block Diagram Figure 31-2. Application Block Diagram OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management Serial AUDIO Codec Line Interface 456 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.4 Pin Name List Table 31-1. Pin Name RF RK RD TF TK TD I/O Lines Description Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output 31.5 31.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. 31.5.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. 31.5.3 Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. 31.6 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. Each level of the clock must be stable for at least two master clock periods. 457 1768G–ATARM–29-Sep-06 Figure 31-3. SSC Functional Block Diagram Transmitter Clock Output Controller TK MCK Clock Divider TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller TX clock Frame Sync Controller TF Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register TD APB User Interface Load Shift Receiver Clock Output Controller RK RK Input TX Clock RF TF Start Selector Receive Clock RX Clock Controller Frame Sync Controller RF Receive Shift Register Receive Holding Register Receive Sync Holding Register RD RX PDC PDC Interrupt Control Load Shift AIC 31.6.1 Clock Management The transmitter clock can be generated by: • an external clock received on the TK I/O pad • the receiver clock • the internal clock divider The receiver clock can be generated by: • an external clock received on the RK I/O pad • the transmitter clock • the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave-mode data transfers. 458 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.6.1.1 Clock Divider Figure 31-4. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal or greater to 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless if the DIV value is even or odd. Figure 31-5. Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 Table 31-2. Maximum MCK / 2 Bit Rate Minimum MCK / 8190 31.6.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. 459 1768G–ATARM–29-Sep-06 Figure 31-6. Transmitter Clock Management SSC_TCMR.CKS SSC_TCMR.CKO TK Receiver Clock Divider Clock 0 1 SSC_TCMR.CKI Transmitter Clock TK 31.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) might lead to unpredictable results. Figure 31-7. Receiver Clock Management SSC_RCMR.CKS SSC_RCMR.CKO RK Transmitter Clock Divider Clock 0 1 SSC_RCMR.CKI Receiver Clock RK 31.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). (See Section 31.6.4 ”Start” on page 462.) The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). (See Section 31.6.5 ”Frame Sync” on page 463.) To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. 460 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 31-8. Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD TF SSC_TFMR.MSBF 0 Start Selector Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR 0 1 SSC_TSHR SSC_TFMR.FSLEN 31.6.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). (See Section 31.6.4 ”Start” on page 462.) The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). (See Section 31.6.5 ”Frame Sync” on page 463.) The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register in function of data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register, if another transfer occurs before read the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. 461 1768G–ATARM–29-Sep-06 Figure 31-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF SSC_RFMR.MSBF SSC_RFMR.DATNB Start Selector Receive Shift Register RD SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN SSC_RHR SSC_RFMR.DATLEN 31.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: • Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. • Synchronously with the transmitter/receiver • On detection of a falling/rising edge on TK/RK • On detection of a low level/high level on TK/RK • On detection of a level change or an edge on TK/RK A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Detection on TF/RF input/output is done through the field FSOS of the Transmit / Receive Frame Mode Register (TFMR/RFMR). Generating a Frame Sync signal is not possible without generating it on its related output. 462 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 31-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF TD (Output) TD (Output) TD (Output) TD (Output) TD (Output) TD (Output) X X BO B1 STTDLY Start = Falling Edge on TF X BO B1 STTDLY BO B1 STTDLY BO B1 Start = High Level on TF X Start = Rising Edge on TF X STTDLY B1 Start = Level Change on TF X BO B1 BO STTDLY Start = Any Edge on TF BO B1 BO B1 STTDLY Figure 31-11. Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF RD (Input) RD (Input) X X BO B1 STTDLY Start = Falling Edge on RF BO B1 STTDLY BO B1 STTDLY Start = High Level on RF RD (Input) Start = Rising Edge on RF RD (Input) RD (Input) RD (Input) X X X BO B1 STTDLY B1 Start = Level Change on RF BO B1 BO STTDLY Start = Any Edge on RF X BO B1 BO B1 STTDLY 31.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported. 463 1768G–ATARM–29-Sep-06 If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1-bit time up to 16-bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 31.6.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Synchro signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register then shifted out. 31.6.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). 31.6.6 Data Format The data framing format of both the transmitter and the receiver are largely programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: • The event that starts the data transfer (START). • The delay in number of bit periods between the start event and the first data bit (STTDLY). • The length of the data (DATLEN) • The number of data to be transferred for each start event (DATNB). • The length of Synchronization transferred for each start event (FSLEN). • The bit sense: most or lowest significant bit first (MSBF). Additionally, the transmitter can be used to transfer Synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. 464 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 31-3. Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR SSC_RCMR SSC_RCMR Data Frame Registers Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN PERIOD STTDLY up to 512 up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number Word transmitter in frame 1 most significant bit in first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay Figure 31-12. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start PERIOD TF/RF(1) FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data Start From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored TD (If FSDEN = 0) RD DATNB Note: 1. Input on falling edge on TF/RF example. Figure 31-13. Transmit Frame Format in Continuous Mode Start TD Data From SSC_THR DATLEN Data From SSC_THR DATLEN Default Start: 1. TXEMPTY set to 1 2. Write to the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. The value of FSDEN has no effect on transmission. SyncData cannot be output in continuous mode. 465 1768G–ATARM–29-Sep-06 Figure 31-14. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Data To SSC_RHR DATLEN Data To SSC_RHR DATLEN Note: 1. STTDLY is set to 0. 31.6.7 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 31.6.8 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC Controller can be programmed to generate an interrupt when it detects an event. The Interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register), which respectively enable and disable the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. Figure 31-15. Interrupt Block Diagram SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear SSC Interrupt 466 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 31-16. Audio Application Block Diagram Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER Clock SCK Word Select WS Data SD MSB Left Channel LSB MSB Right Channel Figure 31-17. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK Frame sync (FSYNC) Serial Data Out Serial Data In CODEC Serial Data Clock (SCLK) First Time Slot Dstart Dend 467 1768G–ATARM–29-Sep-06 Figure 31-18. Time Slot Application Block Diagram SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend Serial Data in 468 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.8 Serial Synchronous Controller (SSC) User Interface SSC Register Mapping Register Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Reserved Reserved Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral DMA Controller (PDC) Register Name SSC_CR SSC_CMR – – SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR – – SSC_RSHR SSC_TSHR – – SSC_SR SSC_IER SSC_IDR SSC_IMR – – Access Write Read/Write – – Read/Write Read/Write Read/Write Read/Write Read Write – – Read Read/Write – – Read Write Write Read – – Reset – 0x0 – – 0x0 0x0 0x0 0x0 0x0 – – – 0x0 0x0 – – 0x000000CC – – 0x0 – – Table 31-4. Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFF 0x100- 0x124 469 1768G–ATARM–29-Sep-06 31.8.1 SSC Control Register SSC_CR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 TXDIS 1 RXDIS 24 – 16 – 8 TXEN 0 RXEN Register Name: Access Type: 31 – 23 – 15 SWRST 7 – • RXEN: Receive Enable 0: No effect. 1: Enables Data Receive if RXDIS is not set(1). • RXDIS: Receive Disable 0: No effect. 1: Disables Data Receive(1). • TXEN: Transmit Enable 0: No effect. 1: Enables Data Transmit if TXDIS is not set(1). • TXDIS: Transmit Disable 0: No effect. 1: Disables Data Transmit(1). • SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR. Note: 1. Only the data management is affected 470 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.8.2 SSC Clock Mode Register SSC_CMR Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DIV 27 – 19 – 11 3 26 – 18 – 10 DIV 2 1 0 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: 31 – 23 – 15 – 7 • DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 31.8.3 SSC Receive Clock Mode Register SSC_RCMR Read/Write 30 22 14 – 6 – 29 21 13 – 5 CKI 28 PERIOD 23 15 – 7 – 20 STTDLY 12 – 4 11 3 CKO 10 START 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: 31 • CKS: Receive Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock Signal RK Pin Reserved • CKO: Receive Clock Output Mode Selection CKO 0x0 0x1 0x2-0x7 Receive Clock Output Mode None Continuous Receive Clock Reserved RK pin Input-only Output 471 1768G–ATARM–29-Sep-06 • CKI: Receive Clock Inversion 0: The data and the Frame Sync signal are sampled on Receive Clock falling edge. 1: The data and the Frame Sync signal are shifted out on Receive Clock rising edge. CKI does not affects the RK output clock signal. • START: Receive Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit Start Detection of a low level on RF input Detection of a high level on RF input Detection of a falling edge on RF input Detection of a rising edge on RF input Detection of any level change on RF input Detection of any edge on RF input Reserved • STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. 472 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.8.4 SSC Receive Frame Mode Register SSC_RFMR Read/Write 30 – 22 14 – 6 – 29 – 21 FSOS 13 – 5 LOOP 28 – 20 12 – 4 27 – 19 11 3 26 – 18 FSLEN 10 DATNB 2 DATLEN 1 0 9 8 25 – 17 24 FSEDGE 16 Register Name: Access Type: 31 – 23 – 15 – 7 MSBF • DATLEN: Data Length 0x0 is not supported. The value of DATLEN can be set between 0x1 and 0x1F. The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the Receiver. If DATLEN is less than or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred. For any other value, 32-bit words are transferred. • LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred. • FSLEN: Receive Frame Sync Length This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. Only when FSOS is set on negative or positive pulse. • FSOS: Receive Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF pin Input-only Output Output Output Output Output Undefined 473 1768G–ATARM–29-Sep-06 • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync sets RXSYN in the SSC Status Register. FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection 474 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.8.5 SSC Transmit Clock Mode Register SSC_TCMR Read/Write 30 22 14 – 6 – 29 21 13 – 5 CKI 28 PERIOD 23 15 – 7 – 20 STTDLY 12 – 4 11 3 CKO 10 START 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: 31 • CKS: Transmit Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved • CKO: Transmit Clock Output Mode Selection CKO 0x0 0x1 0x2-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Reserved TK pin Input-only Output • CKI: Transmit Clock Inversion 0: The data and the Frame Sync signal are shifted out on Transmit Clock falling edge. 1: The data and the Frame Sync signal are shifted out on Transmit Clock rising edge. CKI affects only the Transmit Clock and not the output clock signal. • START: Transmit Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8-0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled) and immediately after the end of transfer of the previous data. Receive Start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved 475 1768G–ATARM–29-Sep-06 • STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Please Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. 476 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.8.6 SSC Transmit Frame Mode Register SSC_TFMR Read/Write 30 – 22 14 – 6 – 29 – 21 FSOS 13 – 5 DATDEF 28 – 20 12 – 4 27 – 19 11 3 26 – 18 FSLEN 10 DATNB 2 DATLEN 1 0 9 8 25 – 17 24 FSEDGE 16 Register Name: Access Type: 31 – 23 FSDEN 15 – 7 MSBF • DATLEN: Data Length 0x0 is not supported. The value of DATLEN can be set between 0x1 and 0x1F. The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the Receiver. If DATLEN is less than or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred. For any other value, 32-bit words are transferred. • DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. • DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start. If 0, only 1 data word is transferred and up to 16 data words can be transferred. • FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible. • FSOS: Transmit Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF pin Input-only Output Output Output Output Output Undefined 477 1768G–ATARM–29-Sep-06 • FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync sets TXSYN (Status Register). FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection 31.8.7 SSC Receive Holding Register SSC_RHR Read-only 30 22 14 6 29 21 13 5 28 RDAT 23 15 7 20 RDAT 12 RDAT 4 RDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: 31 • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 31.8.8 SSC Transmit Holding Register SSC_THR Write only 30 22 14 6 29 21 13 5 28 TDAT 23 15 7 20 TDAT 12 TDAT 4 TDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: 31 TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 478 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.8.9 SSC Receive Synchronization Holding Register SSC_RSHR Read/Write 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 RSDAT 7 4 RSDAT 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: 31 – 23 – 15 • RSDAT: Receive Synchronization Data Right aligned regardless of the number of data bits defined by FSLEN in SSC_RFMR. 31.8.10 Name: Access Type: 31 – 23 – 15 7 SSC Transmit Synchronization Holding Register SSC_TSHR Read/Write 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 TSDAT 4 TSDAT 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 • TSDAT: Transmit Synchronization Data Right aligned regardless of the number of data bits defined by FSLEN in SSC_TFMR. 479 1768G–ATARM–29-Sep-06 31.8.11 SSC Status Register SSC_SR Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 RXEN 9 – 1 TXEMPTY 24 – 16 TXEN 8 – 0 TXRDY Register Name: Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register. 1: SSC_THR is empty. • TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from Transmit Shift Register. 1: Last data written in SSC_THR has been loaded in Transmit Shift Register and transmitted by it. • ENDTX: End of Transmission 0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. • TXBUFE: Transmit Buffer Empty 0: SSC_TCR or SSC_TNCR have a value other than 0. 1: Both SSC_TCR and SSC_TNCR have a value of 0. • RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. • OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. • ENDRX: End of Reception 0: Data is written on the Receive Counter Register or Receive Next Counter Register. 1: End of PDC transfer when Receive Counter Register has arrived at zero. • RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. 480 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. • RXSYN: Receive Sync 0: A Rx Sync has not occurred since the last read of the Status Register. 1: A Rx Sync has occurred since the last read of the Status Register. • TXEN: Transmit Enable 0: Transmit data is disabled. 1: Transmit data is enabled. • RXEN: Receive Enable 0: Receive data is disabled. 1: Receive data is enabled. 481 1768G–ATARM–29-Sep-06 31.8.12 SSC Interrupt Enable Register SSC_IER Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY Register Name: Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready • TXEMPTY: Transmit Empty • ENDTX: End of Transmission • TXBUFE: Transmit Buffer Empty • RXRDY: Receive Ready • OVRUN: Receive Overrun • ENDRX: End of Reception • RXBUFF: Receive Buffer Full • TXSYN: Tx Sync • RXSYN: Rx Sync 0: No effect. 1: Enables the corresponding interrupt. 482 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 31.8.13 SSC Interrupt Disable Register SSC_IDR Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY Register Name: Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready • TXEMPTY: Transmit Empty • ENDTX: End of Transmission • TXBUFE: Transmit Buffer Empty • RXRDY: Receive Ready • OVRUN: Receive Overrun • ENDRX: End of Reception • RXBUFF: Receive Buffer Full • TXSYN: Tx Sync • RXSYN: Rx Sync 0: No effect. 1: Disables the corresponding interrupt. 483 1768G–ATARM–29-Sep-06 31.8.14 SSC Interrupt Mask Register SSC_IMR Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY Register Name: Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready • TXEMPTY: Transmit Empty • ENDTX: End of Transmission • TXBUFE: Transmit Buffer Empty • RXRDY: Receive Ready • OVRUN: Receive Overrun • ENDRX: End of Reception • RXBUFF: Receive Buffer Full • TXSYN: Tx Sync • RXSYN: Rx Sync 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. 484 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 32. Timer Counter (TC) 32.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Key Features of the Timer Counter are: • Three 16-bit Timer Counter Channels • A Wide Range of Functions Including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each Channel is User-configurable and Contains: – Three External Clock Inputs – Five Internal Clock Inputs – Two Multi-purpose Input/Output Signals • Internal Interrupt Signal Two Global Registers that Act on All Three TC Channels 485 1768G–ATARM–29-Sep-06 32.2 Block Diagram Figure 32-1. Timer Counter Block Diagram Parallel I/O Controller TCLK0 TIMER_CLOCK2 TIMER_CLOCK1 TIOA1 TIMER_CLOCK3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA2 TCLK1 XC0 XC1 XC2 TC0XC0S Timer/Counter Channel 0 TIOA TIOA0 TIOB TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOB0 SYNC INT0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC Timer/Counter Channel 1 TIOA TIOA1 TIOB TIOB1 INT1 TIOA1 TIOB1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB TIOB2 SYNC TIOA2 TIOB2 INT2 Timer Counter Advanced Interrupt Controller Table 32-1. Signal Name Description Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture Mode: General-purpose Input Waveform Mode: General-purpose Output Capture Mode: General-purpose Input Waveform Mode: General-purpose Input/output Interrupt Signal Output Synchronization Input Signal External Clock Inputs TIOA Signal for Channel 0 TIOB Signal for Channel 0 TIOA Signal for Channel 1 TIOB Signal for Channel 1 TIOA Signal for Channel 2 TIOB Signal for Channel 2 Block/Channel Channel Signal TIOB INT SYNC TCLK0, TCLK1, TCLK2 TIOA0 TIOB0 Block Signal TIOA1 TIOB1 TIOA2 TIOB2 486 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 32.3 Pin Name List Table 32-2. Pin Name Timer Counter pin list Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2 32.4 Product Dependencies For further details on the Timer Counter hardware implementation, see the specific Product Properties document. 32.4.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 32.4.2 Power Management The TC must be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter. 32.4.3 Interrupt The TC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. 32.5 32.5.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 32-2 on page 487. 32.5.1.1 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 32.5.1.2 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 32-2. Each channel can independently select an internal or external clock source for its counter: 487 1768G–ATARM–29-Sep-06 • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 • External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register (Capture Mode). The selected clock can be inverted with the CLKI bit in TC_CMR (Capture Mode). This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock Figure 32-2. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 32.5.1.3 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 32-3. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. 488 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 32-3. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 32.5.1.4 TC Operating Modes Each channel can independently operate in two different modes: • Capture Mode provides measurement on signals. • Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 32.5.1.5 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. 489 1768G–ATARM–29-Sep-06 If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 32.5.2 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 32-4 shows the configuration of the TC channel when programmed in Capture Mode. 32.5.2.1 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 32.5.2.2 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. 490 AT91RM9200 1768G–ATARM–29-Sep-06 1768G–ATARM–29-Sep-06 Figure 32-4. Capture Mode TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 LDBSTOP BURST Register C Capture Register A SWTRG CLK RESET SYNC Trig ABETRG ETRGEDG MTIOB Edge Detector LDRA Edge Detector If RA is Loaded LDRB Edge Detector TC1_SR CLKI CLKSTA CLKEN CLKDIS Q Q S R S R LDBDIS 1 16-bit Counter OVF Capture Register B Compare RC = CPCTRG TIOB ETRGS COVFS LOVRS LDRAS LDRBS CPCS MTIOA If RA is not loaded or RB is Loaded TC1_IMR TIOA AT91RM9200 Timer/Counter Channel INT 491 32.6 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 32-5 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 32.6.0.3 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 492 AT91RM9200 1768G–ATARM–29-Sep-06 TIMER_CLOCK5 XC0 XC1 XC2 Q S R CPCSTOP Output Controller WAVSEL EEVT BEEVT EEVTEDG Edge Detector TIOB TC1_IMR TC1_SR ENETRG ETRGS COVFS CPCS CPAS CPBS Output Controller 1768G–ATARM–29-Sep-06 Figure 32-5. Waveform Mode TCCLKS CLKSTA TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 CLKI CLKEN CLKDIS ACPC Q S CPCDIS R ACPA MTIOA AEEVT TIOA BURST WAVSEL Register A Register B Register C ASWTRG Compare RA = 16-bit Counter CLK RESET OVF 1 Compare RB = Compare RC = SWTRG BCPC SYNC Trig BCPB MTIOB TIOB AT91RM9200 BSWTRG Timer/Counter Channel INT 493 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 32-6. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 32-7. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 32-6. WAVSEL= 00 without trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 494 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 32-7. WAVSEL= 00 with trigger Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 32-8. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 32-9. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 32-8. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 495 1768G–ATARM–29-Sep-06 Figure 32-9. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 32-10. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 32-11. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 496 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 32-10. WAVSEL = 01 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 32-11. WAVSEL = 01 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF Counter incremented by trigger RA Waveform Examples TIOB Time TIOA WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 32-12. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 32-13. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 497 1768G–ATARM–29-Sep-06 Figure 32-12. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 32-13. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 32.6.0.4 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The parameter EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the TC channel can only generate a waveform on TIOA. 498 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 32.6.0.5 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 499 1768G–ATARM–29-Sep-06 32.7 Timer Counter (TC) User Interface Timer Counter Global Memory Map Channel/Register TC Channel 0 TC Channel 1 TC Channel 2 TC Block Control Register TC Block Mode Register TC_BCR TC_BMR Name Access See Table 32-4 See Table 32-4 See Table 32-4 Write-only Read/Write – 0 Reset Value Table 32-3. Offset 0x00 0x40 0x80 0xC0 0xC4 TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in Table 32-4. The offset of each of the channel registers in Table 32-4 is in relation to the offset of the corresponding channel as mentioned in Table 32-4. Table 32-4. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 Timer Counter Channel Memory Map Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR Read-only Read/Write (1) Name TC_CCR TC_CMR Access Write-only Read/Write Reset Value – 0 – – 0 0 0 0 0 – – 0 Read/Write(1) Read/Write Read-only Write-only Write-only Read-only 0x2C Interrupt Mask Register Notes: 1. Read only if WAVE = 0 500 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 32.7.1 TC Block Control Register TC_BCR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 SYNC Register Name: Access Type: 31 – 23 – 15 – 7 – • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 501 1768G–ATARM–29-Sep-06 32.7.2 TC Block Mode Register TC_BMR Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 TC2XC2S 28 – 20 – 12 – 4 27 – 19 – 11 – 3 TCXC1S 26 – 18 – 10 – 2 25 – 17 – 9 – 1 TC0XC0S 24 – 16 – 8 – 0 Register Name: Access Type: 31 – 23 – 15 – 7 – • TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 502 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 32.7.3 TC Channel Control Register TC_CCR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SWTRG 25 – 17 – 9 – 1 CLKDIS 24 – 16 – 8 – 0 CLKEN Register Name: Access Type: 31 – 23 – 15 – 7 – • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. • SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started. 503 1768G–ATARM–29-Sep-06 32.7.4 TC Channel Mode Register: Capture Mode TC_CMR Read/Write 30 – 22 – 14 CPCTRG 6 LDBSTOP 29 – 21 – 13 – 5 BURST 28 – 20 – 12 – 4 11 – 3 CLKI 27 – 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 – 18 25 – 17 LDRA 8 24 – 16 Register Name: Access Type: 31 – 23 – 15 WAVE = 0 7 LDBDIS • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. • LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. 504 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • ETRGEDG: External Trigger Edge Selection ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • LDRB: RB Loading Selection LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA 505 1768G–ATARM–29-Sep-06 32.7.5 TC Channel Mode Register: Waveform Mode TC_CMR Read/Write 30 BSWTRG 23 ASWTRG 15 14 WAVSEL 6 CPCSTOP 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24 Register Name: Access Type: 31 WAVE = 1 7 CPCDIS • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. • CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. 506 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • EEVTEDG: External Event Edge Selection EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • EEVT: External Event Selection EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input(1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms. • ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. • WAVSEL: Waveform Selection WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare • WAVE = 1 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. • ACPA: RA Compare Effect on TIOA ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle 507 1768G–ATARM–29-Sep-06 • ACPC: RC Compare Effect on TIOA ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle • AEEVT: External Event Effect on TIOA AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle • BCPB: RB Compare Effect on TIOB BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle • BCPC: RC Compare Effect on TIOB BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle 508 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • BEEVT: External Event Effect on TIOB BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle 509 1768G–ATARM–29-Sep-06 32.7.6 TC Counter Value Register TC_CV Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CV 7 6 5 4 CV 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: 31 – 23 – 15 • CV: Counter Value CV contains the counter value in real time. 32.7.7 TC Register A TC_RA Read-only if WAVE = 0, Read/Write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RA 7 6 5 4 RA 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: 31 – 23 – 15 • RA: Register A RA contains the Register A value in real time. 510 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 32.7.8 TC Register B TC_RB Read-only if WAVE = 0, Read/Write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RB 7 6 5 4 RB 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: 31 – 23 – 15 • RB: Register B RB contains the Register B value in real time. 32.7.9 TC Register C TC_RC Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RC 7 6 5 4 RC 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Register Name: Access Type: 31 – 23 – 15 • RC: Register C RC contains the Register C value in real time. 511 1768G–ATARM–29-Sep-06 32.7.10 TC Status Register TC_SR Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 MTIOB 10 – 2 CPAS 25 – 17 MTIOA 9 – 1 LOVRS 24 – 16 CLKSTA 8 – 0 COVFS Register Name: Access Type: 31 – 23 – 15 – 7 ETRGS • COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. • CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. • LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. 512 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 513 1768G–ATARM–29-Sep-06 32.7.11 TC Interrupt Enable Register TC_IER Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS Register Name: Access Type: 31 – 23 – 15 – 7 ETRGS • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. • CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. • CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. • CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. • LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. • ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 514 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 32.7.12 TC Interrupt Disable Register TC_IDR Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS Register Name: Access Type: 31 – 23 – 15 – 7 ETRGS • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). • CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). • CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). • CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). • ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. 515 1768G–ATARM–29-Sep-06 32.7.13 TC Interrupt Mask Register TC_IMR Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS Register Name: Access Type: 31 – 23 – 15 – 7 ETRGS • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. • CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. • CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. • CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. • LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. • LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. • ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 516 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 33. MultiMedia Card Interface (MCI) 33.1 Description The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V2.2 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 1 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. 517 1768G–ATARM–29-Sep-06 33.2 Block Diagram Figure 33-1. Block Diagram APB Bridge PDC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCI Interface PIO MCCDB(1) MCDB0(1) MCDB1(1) MCDB2(1) Interrupt Control MCDB3(1) MCI Interrupt Note: 1. When several MCIs (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 518 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 33.3 Application Block Diagram Figure 33-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 MMC 9 SDCard 33.4 Pin Name List I/O Lines Description Pin Description Command/response Clock Data 0..3 of Slot A Data 0..3 of Slot B Type(1) I/O/PP/OD I/O I/O/PP I/O/PP Comments CMD of an MMC or SDCard CLK of an MMC or SD Card DAT0 of an MMC DAT[0..3] of an SD Card DAT0 of an MMC DAT[0..3] of an SD Card Table 33-1. Pin Name(2) MCCDA/MCCDB MCCK MCDA0 - MCDA3 MCDB0 - MCDB3 Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 519 1768G–ATARM–29-Sep-06 AT91RM9200 33.5 33.5.1 Product Dependencies I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. 33.5.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock. Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. 33.5.3 33.6 Bus Topology Figure 33-3. Multimedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 33-2. Pin Number 1 2 3 4 5 6 7 Notes: Bus Topology Name RSV CMD VSS1 VDD CLK VSS2 DAT[0] Type NC I/O/PP/OD S S I/O S I/O/PP (1) Description Not connected Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 MCI Pin Name(2) (Slot z) MCCDz VSS VDD MCCK VSS MCDz0 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 520 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 33-4. MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK 1234567 MMC1 1234567 MMC2 1234567 MMC3 Note: When several MCIs (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. Figure 33-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 33-3. Table 33-3. Pin Number 1 2 3 4 5 6 7 8 9 Notes: SD Memory Card Bus Signals Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type (1) Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 Data line Bit 2 MCI Pin Name(2) (Slot z) MCDz3 MCCDz VSS VDD MCCK VSS MCDz0 MCDz1 MCDz2 I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several MCIs (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 521 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 33-6. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1234567 MMC1 1 2 3 4 5 6 78 SD CARD Note: When several MCIs (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. Figure 33-7. SD Card Bus Connections with Two Slots MCDA0 - MCDA3 MCCK MCCDA MCDB0 - MCDB3 MCCDB Note: When several MCIs (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. Figure 33-8. Mixing MultiMedia and SD Memory Cards with Two Slots MCDA0 MCCDA MCCK 1234567 MMC2 9 9 SD CARD 2 9 SD CARD 1 1234567 MMC3 MCDB0 - MCDB3 SD CARD MCCDB Note: When several MCIs (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that 9 522 1768G–ATARM–29-Sep-06 AT91RM9200 the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 33.7 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. • Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. • Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 33-4 on page 524. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined: • Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read. The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 33.7.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2 PWSDIV + 1 w hen the bus is inactive. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. 523 1768G–ATARM–29-Sep-06 AT91RM9200 The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC E Z NID Cycles ****** Z S T CID Content Z Z Z The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 33-4 and Table 33-5. Table 33-4. CMD Index ALL_SEND_CID Command Description Type Argument Resp Abbreviation Command Description Asks all cards to send their CID numbers on the CMD line CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Note: bcr means broadcast command with response. Table 33-5. Field Fields and Values for MCI_CMDR Command Register Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • Fill the argument register (MCI_ARGR) with the command argument. • Set the command register (MCI_CMDR) (see Table 33-5). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. 524 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 33-9. Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? Read response if required RETURN ERROR(1) RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). 33.7.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined in the mode register MCI_MR. This field determines the size of the data block. 33.7.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 33-10), a polling method is used to wait for the end of read. Simi- 525 1768G–ATARM–29-Sep-06 AT91RM9200 larly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. Figure 33-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD (1) command to select the card Send SET_BLOCKLEN command(1) No Read with PDC Yes Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght Data OUT transaction • Data IN transaction > Data IN transaction • Data OUT transaction > Data OUT transaction • Data IN transaction > Data IN transaction • Data OUT transaction > Data OUT transaction Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake. 552 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 34.5.2 34.5.2.1 Handling Transactions with USB V2.0 Device Peripheral Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: • The USB device automatically acknowledges the setup packet • RXSETUP is set in the UDP_CSRx register • An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. Figure 34-4. Setup Transaction Followed by a Data OUT Transaction Setup Received Setup Handled by Firmware Data Out Received USB Bus Packets Setup PID Data Setup ACK PID Data OUT PID Data OUT NAK PID Data OUT PID Data OUT ACK PID RXSETUP Flag Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (USB_CSRx) FIFO (DPR) Content XX Data Setup XX Data OUT 34.5.2.2 Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes. Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction, using a non ping-pong endpoint: 553 1768G–ATARM–29-Sep-06 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx register (TXPKTRDY must be cleared). 2. The microcontroller writes data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 3. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register, 4. The microcontroller is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Note: Please refer to Chapter 8 of the Universal Serial Bus Specification, Rev 1.1, for more information on the Data IN protocol layer. Figure 34-5. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus USB Bus Packets Data IN PID Data IN 1 ACK PID Data IN PID NAK PID Data IN PID Data IN 2 ACK PID TXPKTRDY Flag (USB_CSRx) Cleared by USB Device Interrupt Pending TXCOMP Flag (USB_CSRx) Cleared by Firmware Set by the Firmware Data Payload Written in FIFO Start to Write Data Payload in FIFO Interrupt Pending FIFO (DPR) Content Data IN 1 Load In Progress Data IN 2 Load In Progress 554 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. To be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 34-6. Bank Swapping Data IN Transfer for Ping-pong Endpoints Microcontroller 1st Data Payload Write Bank 0 Endpoint 1 USB Device Read USB Bus Read and Write at the Same Time 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Data IN Packet 1st Data Payload Data IN Packet 2nd Data Payload Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent rising TXPKTRDY in the endpoint’s UDP_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. 555 1768G–ATARM–29-Sep-06 Figure 34-7. Data IN Transfer for Ping-pong Endpoint Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 USB Bus Packets Data IN PID Data IN ACK PID Data IN PID Data IN ACK PID TXPKTRDY Flag (USB_MCSRx) Cleared by USB Device, Data Payload Fully Transmitted Set by Firmware, Data Payload Written in FIFO Bank 0 Set by USB Device Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device TXCOMP Flag (USB_CSRx) Interrupt Cleared by Firmware FIFO (DPR) Written by Microcontroller Bank 0 Read by USB Device Written by Microcontroller FIFO (DPR) Bank 1 Written by Microcontroller Read by USB Device Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set is too long, some Data IN packets may be NACKed, reducing the bandwidth. 34.5.2.3 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 556 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the endpoint’s UDP_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 34-8. Data OUT Transfer for Non Ping-pong Endpoints Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT2 Data OUT2 NAK PID PID Data OUT PID Data OUT2 ACK PID RX_DATA_BK0 (USB_CSRx) Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device FIFO (DPR) Content Data OUT 1 Written by USB Device Data OUT 1 Microcontroller Read An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO. Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is necessary. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. 557 1768G–ATARM–29-Sep-06 Figure 34-9. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Data IN Packet nd Data Payload 2 Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_FDRx register. 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. 558 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 34-10. Data OUT Transfer for Ping-pong Endpoint Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT PID Data OUT 2 ACK PID Data OUT PID Data OUT 3 A P RX_DATA_BK0 Flag (USB_CSRx) Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 Cleared by Firmware RX_DATA_BK1 Flag (USB_CSRx) Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 Cleared by Firmware Interrupt Pending FIFO (DPR) Bank 0 Data OUT1 Write by USB Device Data OUT 1 Read By Microcontroller Data OUT 3 Write In Progress FIFO (DPR) Bank 1 Data OUT 2 Write by USB Device Data OUT 2 Read By Microcontroller Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 34.5.2.4 Status Transaction A status transaction is a special type of host to device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. 559 1768G–ATARM–29-Sep-06 Figure 34-11. Control Read and Write Sequences Setup Stage Data Stage Status Stage Control Read Setup TX Data OUT TX Data OUT TX Status IN TX Setup Stage Data Stage Status Stage Control Write Setup TX Data IN TX Data IN TX Status OUT TX Setup Stage Status Stage No Data Control Setup TX Status IN TX Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Please refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 1.1, to get more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 34.5.2.5 Status IN Transfer Once a control request has been processed, the device returns a status to the host. This is a zero length Data IN transaction. 1. The microcontroller waits for TXPKTRDY in the UDP_CSRx endpoint’s register to be cleared. (At this step, TXPKTRDY must be cleared because the previous transaction was a setup transaction or a Data OUT transaction.) 2. Without writing anything to the UDP_FDRx endpoint’s register, the microcontroller sets TXPKTRDY. The USB device generates a Data IN packet using DATA1 PID. 3. This packet is acknowledged by the host and TXPKTRDY is set in the UDP_CSRx endpoint’s register. 560 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 34-12. Data Out Followed by Status IN Transfer. Host Sends the Last Data Payload to the Device USB Bus Packets Device Sends a Status IN to the Host Data OUT PID Data OUT NAK PID Data IN PID ACK PID Interrupt Pending RX_DATA_BKO (USB_CSRx) Cleared by Firmware Set by USB Device Cleared by USB Device TXPKTRDY (USB_CSRx) Set by Firmware 34.5.2.6 Status OUT Transfer Once a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. This is a zero length Data OUT transaction. 1. The USB device receives a zero length packet. It sets RX_DATA_BK0 flag in the UDP_CSRx register and acknowledges the zero length packet. 2. The microcontroller is notified that the USB device has received a zero length packet sent by the host polling RX_DATA_BK0 in the UDP_CSRx register. An interrupt is pending while RX_DATA_BK0 is set. The number of bytes received in the endpoint’s UDP_BCR register is equal to zero. 3. The microcontroller must clear RX_DATA_BK0. Figure 34-13. Data IN Followed by Status OUT Transfer Device Sends the Last Data Payload to Host USB Bus Packets Data IN PID Data IN ACK PID Device Sends a Status OUT to Host Data OUT PID ACK PID Interrupt Pending RX_DATA_BKO (USB_CSRx) Set by USB Device Cleared by Firmware TXCOMP (USB_CSRx) Set by USB Device Cleared by Firmware 34.5.2.7 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 1.1.) 561 1768G–ATARM–29-Sep-06 • A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 1.1, for more information on the halt feature.) • To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register. 2. The host receives the stall packet. 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. Figure 34-14. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 34-15. Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID FORCESTALL Set by Firmware Interrupt Pending STALLSENT Set by USB Device Cleared by Firmware 562 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 34.5.3 Controlling Device States A USB device has several possible states. Please refer to Chapter 9 of the Universal Serial Bus Specification, Rev 1.1. Figure 34-16. USB Device State Diagram Attached Hub Reset or Deconfigured Hub Configured Bus Inactive Powered Bus Activity Power Interruption Suspended Reset Bus Inactive Default Reset Address Assigned Bus Inactive Bus Activity Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Suspended Configured Bus Activity Suspended Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the UDP device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 uA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse. The wake-up feature is not mandatory for all devices and must be negotiated with the host. 563 1768G–ATARM–29-Sep-06 34.5.3.1 From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The USB host stops driving a reset state once it has detected the device’s pull-up on DP. The unmasked flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. The UDP software enables the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. 34.5.3.2 From Default State to Address State After a set address standard device request, the USB host peripheral enters the address state. Before this, it achieves the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STATE, sets its new address, and sets the FEN bit in the UDP_FADDR register. 34.5.3.3 From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. 34.5.3.4 Enabling Suspend When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register. This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks may be switched off. However, the transceiver and the USB peripheral must not be switched off, otherwise the resume is not detected. 34.5.3.5 Receiving a Host Resume In suspend mode, the USB transceiver and the USB peripheral must be powered to detect the RESUME. However, the USB device peripheral may not be clocked as the WAKEUP signal is asynchronous. Once the resume is detected on the bus, the signal WAKEUP in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register. 34.5.3.6 Sending an External Resume The External Resume is negotiated with the host and enabled by setting the ESR bit in the UDP_GLB_STATE. An asynchronous event on the ext_resume_pin of the peripheral generates a WAKEUP interrupt. On early versions of the USP peripheral, the K-state on the USB line is generated immediately. This means that the USB device must be able to answer to the host very 564 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 quickly. On recent versions, the software sets the RMWUPE bit in the UDP_GLB_STATE register once it is ready to communicate with the host. The K-state on the bus is then generated. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register. 565 1768G–ATARM–29-Sep-06 34.6 USB Device Port (UDP) User Interface USB Device Port Memory Map Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint 0 Control and Status Register Endpoint 1 Control and Status Register Endpoint 2 Control and Status Register Endpoint 3 Control and Status Register Endpoint 4 Control and Status Register Endpoint 5 Control and Status Register Reserved Reserved Endpoint 0 FIFO Data Register Endpoint 1 FIFO Data Register Endpoint 2 FIFO Data Register Endpoint 3 FIFO Data Register Endpoint 4 FIFO Data Register Endpoint 5 FIFO Data Register Reserved Reserved Transceiver Control Register Reserved Name UDP_FRM_NUM UDP_GLB_STAT UDP_FADDR – UDP_IER UDP_IDR UDP_IMR UDP_ISR UDP_ICR – UDP_RST_EP – UDP_CSR0 UDP_CSR1 UDP_CSR2 UDP_CSR3 UDP_CSR4 UDP_CSR5 – – UDP_FDR0 UDP_FDR1 UDP_FDR2 UDP_FDR3 UDP_FDR4 UDP_FDR5 – – UDP_TXVC – Access Read Read/Write Read/Write – Write Write Read Read Write – Read/Write – Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write – – Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write – – Read/Write – – 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 – – 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 – – 0x0000_0100 – – 0x0000_1200 0x0000_0000 Reset State 0x0000_0000 0x0000_0010 0x0000_0100 – Table 34-3. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x074 0x070 566 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 34.6.1 UDP Frame Number Register UDP_FRM_NUM Read-only 30 --22 – 14 – 6 29 --21 – 13 – 5 28 --20 – 12 – 4 FRM_NUM 27 --19 – 11 – 3 26 --18 – 10 25 --17 FRM_OK 9 FRM_NUM 1 24 --16 FRM_ERR 8 Register Name: Access Type: 31 --23 – 15 – 7 2 0 • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). • FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. • FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. 567 1768G–ATARM–29-Sep-06 34.6.2 UDPGlobal State Register UDP_GLB_STAT Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 RMWUPE 27 – 19 – 11 – 3 RSMINPR 26 – 18 – 10 – 2 ESR 25 – 17 – 9 – 1 CONFG 24 – 16 – 8 – 0 FADDEN Register Name: Access Type: 31 – 23 – 15 – 7 – This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.1.1. • FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Set device in address state. This occurs after a successful Set Address request. Beforehand, the USB_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Please refer to chapter 9 of the Universal Serial Bus Specification, Rev. 1.1 to get more details. • CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Set device in a nonconfigured state 1 = Set device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Please refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 1.1 to get more details. • ESR: Enable Send Resume 0 = Disable the Remote Wake Up sequence. 1 = Remote Wake Up can be processed and the pin send_resume is enabled. 568 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • RSMINPR: A Resume Has Been Sent to the Host Read: 0 = No effect. 1 = A Resume has been received from the host during Remote Wake Up feature. • RMWUPE: Remote Wake Up Enable 0 = Must be cleared after receiving any HOST packet or SOF interrupt. 1 = Enables the K-state on the USB cable if ESR is enabled. 34.6.3 UDP Function Address Register UDP_FADDR Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 FADD 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 FEN 0 Register Name: Access Type: 31 – 23 – 15 – 7 – • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Please refer to the Universal Serial Bus Specification, Rev. 1.1 to get more information. After power up, or reset, the function address value is set to 0. • FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disable function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. 569 1768G–ATARM–29-Sep-06 34.6.4 UDP Interrupt Enable Register UDP_IER Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT Register Name: Access Type: 31 – 23 – 15 – 7 – • EP0INT: Enable Endpoint 0 Interrupt • EP1INT: Enable Endpoint 1 Interrupt • EP2INT: Enable Endpoint 2Interrupt • EP3INT: Enable Endpoint 3 Interrupt • EP4INT: Enable Endpoint 4 Interrupt • EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enable corresponding Endpoint Interrupt. • RXSUSP: Enable USB Suspend Interrupt 0 = No effect. 1 = Enable USB Suspend Interrupt. • RXRSM: Enable USB Resume Interrupt 0 = No effect. 1 = Enable USB Resume Interrupt. • EXTRSM: Enable External Resume Interrupt 0 = No effect. 1 = Enable External Resume Interrupt. • SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enable Start Of Frame Interrupt. 570 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • WAKEUP: Enable USB bus Wakeup Interrupt 0 = No effect. 1 = Enable USB bus Interrupt. 571 1768G–ATARM–29-Sep-06 34.6.5 UDP Interrupt Disable Register UDP_IDR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT Register Name: Access Type: 31 – 23 – 15 – 7 – • EP0INT: Disable Endpoint 0 Interrupt • EP1INT: Disable Endpoint 1 Interrupt • EP2INT: Disable Endpoint 2 Interrupt • EP3INT: Disable Endpoint 3 Interrupt • EP4INT: Disable Endpoint 4 Interrupt • EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disable corresponding Endpoint Interrupt. • RXSUSP: Disable USB Suspend Interrupt 0 = No effect. 1 = Disable USB Suspend Interrupt. • RXRSM: Disable USB Resume Interrupt 0 = No effect. 1 = Disable USB Resume Interrupt. • EXTRSM: Disable External Resume Interrupt 0 = No effect. 1 = Disable External Resume Interrupt. • SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disable Start Of Frame Interrupt 572 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disable USB Bus Wakeup Interrupt. 573 1768G–ATARM–29-Sep-06 34.6.6 UDP Interrupt Mask Register UDP_IMR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT Register Name: Access Type: 31 – 23 – 15 – 7 – • EP0INT: Mask Endpoint 0 Interrupt • EP1INT: Mask Endpoint 1 Interrupt • EP2INT: Mask Endpoint 2 Interrupt • EP3INT: Mask Endpoint 3 Interrupt • EP4INT: Mask Endpoint 4 Interrupt • EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. • RXSUSP: Mask USB Suspend Interrupt 0 = USB Suspend Interrupt is disabled. 1 = USB Suspend Interrupt is enabled. • RXRSM: Mask USB Resume Interrupt. 0 = USB Resume Interrupt is disabled. 1 = USB Resume Interrupt is enabled. • EXTRSM: Mask External Resume Interrupt 0 = External Resume Interrupt is disabled. 1 = External Resume Interrupt is enabled. • SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. 574 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register USB_IMR is enabled. 575 1768G–ATARM–29-Sep-06 34.6.7 UDP Interrupt Status Register UDP_ISR Read -only 30 – 22 – 14 – 29 – 21 – 13 WAKEUP 28 – 20 – 12 ENDBUSRE S 4 EP4INT 27 – 19 – 11 SOFINT 26 – 18 – 10 EXTRSM 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT Register Name: Access Type: 31 – 23 – 15 – 7 – 6 – 5 EP5INT 3 EP3INT 2 EP2INT • EP0INT: Endpoint 0 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit. • EP1INT: Endpoint 1 Interrupt Status 0 = No Endpoint1 Interrupt pending. 1 = Endpoint1 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR1: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding UDP_CSR1 bit. 576 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 • EP2INT: Endpoint 2 Interrupt Status 0 = No Endpoint2 Interrupt pending. 1 = Endpoint2 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR2: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding UDP_CSR2 bit. • EP3INT: Endpoint 3 Interrupt Status 0 = No Endpoint3 Interrupt pending. 1 = Endpoint3 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR3: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding UDP_CSR3 bit. • EP4INT: Endpoint 4 Interrupt Status 0 = No Endpoint4 Interrupt pending. 1 = Endpoint4 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR4: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding UDP_CSR4 bit. • EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint5 Interrupt pending. 1 = Endpoint5 Interrupt has been raised. 577 1768G–ATARM–29-Sep-06 Several signals can generate this interrupt. The reason can be found by reading UDP_CSR5: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding UDP_CSR5 bit. • RXSUSP: USB Suspend Interrupt Status 0 = No USB Suspend Interrupt pending. 1 = USB Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. • RXRSM: USB Resume Interrupt Status 0 = No USB Resume Interrupt pending. 1 = USB Resume Interrupt has been raised. The USB device sets this bit when a USB resume signal is detected at its port. • EXTRSM: External Resume Interrupt Status 0 = No External Resume Interrupt pending. 1 = External Resume Interrupt has been raised. This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus. • SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a USB reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. • WAKEUP: USB Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. 578 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 34.6.8 UDP Interrupt Clear Register UDP_ICR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 – 28 – 20 – 12 ENDBUSRES Register Name: Access Type: 31 – 23 – 15 – 7 – 27 – 19 – 11 SOFINT 3 – 26 – 18 – 10 EXTRSM 2 – 25 – 17 – 9 RXRSM 1 – 24 – 16 – 8 RXSUSP 0 – 4 – • RXSUSP: Clear USB Suspend Interrupt 0 = No effect. 1 = Clear USB Suspend Interrupt. • RXRSM: Clear USB Resume Interrupt 0 = No effect. 1 = Clear USB Resume Interrupt. • EXTRSM: Clear External Resume Interrupt 0 = No effect. 1 = Clear External Resume Interrupt. • SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clear Start Of Frame Interrupt. • ENDBUSRES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clear End of Bus Reset Interrupt. • WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clear Wakeup Interrupt. 579 1768G–ATARM–29-Sep-06 34.6.9 UDP Reset Endpoint Register UDP_RST_EP Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 EP5 28 – 20 – 12 – 4 EP4 27 – 19 – 11 – 3 EP3 26 – 18 – 10 – 2 EP2 25 – 17 – 9 – 1 EP1 24 – 16 – 8 – 0 EP0 Register Name: Access Type: 31 – 23 – 15 – 7 – • EP0: Reset Endpoint 0 • EP1: Reset Endpoint 1 • EP2: Reset Endpoint 2 • EP3: Reset Endpoint 3 • EP4: Reset Endpoint 4 • EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.1.1. Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register. 580 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 34.6.10 UDP Endpoint Control and Status Register UDP_CSRx [x = 0. 7] Read/Write 30 – 22 29 – 21 28 – 20 RXBYTECNT 15 EPEDS 7 DIR 14 – 6 RX_DATA_ BK1 13 – 5 FORCE STALL 12 – 4 TXPKTRDY 11 DTGLE 3 STALLSENT ISOERROR 10 9 EPTYPE 1 RX_DATA_ BK0 8 27 – 19 26 25 RXBYTECNT 17 24 Register Name: Access Type: 31 – 23 18 16 2 RXSETUP 0 TXCOMP • TXCOMP: Generates an IN packet with data previously written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware) 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral) 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. • RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware) 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = No effect. Read (Set by the USB peripheral) 0 = No data packet has been received in the FIFO's Bank 0 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. • RXSETUP: Sends STALL to the Host (Control endpoints) This flag generates an interrupt while it is set to one. 581 1768G–ATARM–29-Sep-06 Read 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transactions is not accepted while RXSETUP is set. • STALLSENT: Stall sent (Control, Bulk Interrupt endpoints)/ ISOERROR (Isochronous endpoints) This flag generates an interrupt while it is set to one. STALLSENT: this ends a STALL handshake Read 0 = the host has not acknowledged a STALL. 1 = host has acknowledge the stall. Write 0 = reset the STALLSENT flag, clear the interrupt. 1 = No effect. This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Please refer to chapters 8.4.4 and 9.4.5 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on the STALL handshake. ISOERROR: a CRC error has been detected in an isochronous transfer Read 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write 0 = reset the ISOERROR flag, clear the interrupt. 1 = No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read 0 = Data values can be written in the FIFO. 582 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 1 = Data values can not be written in the FIFO. Write 0 = No effect. 1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. • FORCESTALL: Force Stall (used by Control, Bulk and Isochronous endpoints) Write-only 0 = No effect. 1 = Send STALL to the host. Please refer to chapters 8.4.4 and 9.4.5 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on the STALL handshake. Control endpoints: during the data stage and status stage, this indicates that the microcontroller can not complete the request. Bulk and interrupt endpoints: notify the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. • RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware) 0 = Notify USB device that data have been read in the FIFO’s Bank 1. 1 = No effect. Read (Set by the USB peripheral) 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. • DIR: Transfer Direction (only available for control endpoints) Read/Write 0 = Allow Data OUT transactions in the control data stage. 1 = Enable Data IN transactions in the control data stage. Please refer to Chapter 8.5.2 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on the control data stage. This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. 583 1768G–ATARM–29-Sep-06 • EPTYPE[2:0]: Endpoint Type Read/Write 000 001 101 010 110 011 111 Control Isochronous OUT Isochronous IN Bulk OUT Bulk IN Interrupt OUT Interrupt IN • DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Please refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 1.1 to get more information on DATA0, DATA1 packet definitions. • EPEDS: Endpoint Enable Disable Read 0 = Endpoint disabled. 1 = Endpoint enabled. Write 0 = Disable endpoint. 1 = Enable endpoint. • RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only. When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register. 584 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 34.6.11 UDP FIFO Data Register UDP_FDRx [x = 0. 7] Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FIFO_DATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Register Name: Access Type: 31 – 23 – 15 – 7 • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Please refer to the Universal Serial Bus Specification, Rev. 1.1 to get more information. 34.6.12 UDP Transceiver Control Register UDP_TXVC Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 TXVDIS 0 – Register Name: Access Type: 31 – 23 – 15 – 7 – • TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared. 585 1768G–ATARM–29-Sep-06 586 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 35. USB Host Port (UHP) 35.1 Overview The USB Host Port interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. It also provides a simple Read/Write protocol on the ASB. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB “tiered star” topology. The USB Host Port controller is fully compliant with the Open HCI specification. The standard OHCI USB stack driver can be easily ported to ATMEL’s architecture in the same way all existing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses. Key features of the USB Host Port are: • Compliance with Open HCI Rev 1.0 Specification • Compliance with USB V2.0 Full Speed and Low Speed Specification • Supports Both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices • Root Hub Integrated with Two Downstream USB Ports • Embedded USB Transceivers (Number of Transceivers is Product Dependant) • Supports Power Management • Operates as a Master on the ASB Bus 587 1768G–ATARM–29-Sep-06 35.2 Block Diagram Figure 35-1. USB Host Port Block Diagram ASB HCI Slave Block OHCI Registers Control List Processor Block ED & TD Regsisters OHCI Root Hub Registers Embedded USB v2.0 Full-speed Transceiver USB transceiver USB transceiver DP DM DP DM Root Hub and Host SIE PORT S/M PORT S/M HCI Master Block Data FIFO 64 x 8 uhp_int MCK UDPCK Access to the USB host operational registers is achieved through the ASB bus interface. The Open HCI host controller initializes master DMA transfers with the ASB bus as follows: • Fetches endpoint descriptors and transfer descriptors • Access to endpoint data from system memory • Access to the HC communication area • Write status and retire transfer Descriptor Memory access errors (abort, misalignment) lead to an “UnrecoverableError” indicated by the corresponding flag in the host controller operational registers. All of the ASB memory map is accessible to the USB host master DMA. Thus there is no need to define a dedicated physical memory area to the USB host. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic. Warning: a pull-down must be connected to DP on the board. Otherwise The USB host will permanently detect a device connection on this port. USB physical transceivers are integrated in the product and driven by the root hub’s ports. Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not dedicate pads to external over current protection. 588 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 35.3 35.3.1 Product Dependencies I/O Lines DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host controller. 35.3.2 Power Management The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%. Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain). 35.3.3 Interrupt The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling USB host interrupts requires programming the AIC before configuring the UHP. 589 1768G–ATARM–29-Sep-06 35.4 Functional Description Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a. 35.4.1 Host Controller Interface There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The operational registers contain control, status and list pointer registers. They are mapped in the ASB memory mapped area. Within the operational register set there is a pointer to a location in the processor address space named the Host Controller Communication Area (HCCA). The HCCA is the second communication channel. The host controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue and status information associated with start-of-frame processing. The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint. Figure 35-2. USB Host Communication Channels Device Enumeration Open HCI Operational Registers Mode HCCA Status Event Frame Int Ratio Control Bulk Host Controller Communications Area Interrupt 0 Interrupt 1 Interrupt 2 ... Interrupt 31 ... ... Done Device Register in Memory Space Shared RAM = Transfer Descriptor = Endpoint Descriptor 590 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 35.4.2 Host Controller Driver Figure 35-3. USB Host Drivers User Application User Space Kernel Drivers Mini Driver Class Driver Class Driver HUB Driver USBD Driver Host Controller Driver Hardware Host Controller Hardware USB Handling is done through several layers as follows: • Host controller hardware and serial engine: Transmit and receive USB data on the bus. • Host controller driver: Drives the Host controller hardware and handle the USB protocol • USB Bus driver and hub driver: Handles USB commands and enumeration. Offers a hardware independent interface. • Mini driver: Handles device specific commands. Class driver: handles standard devices. This acts as a generic driver for a class of devices, for example the HID driver. 591 1768G–ATARM–29-Sep-06 35.5 Typical Connection Figure 35-4. Board Schematic to Interface UHP Device Controller 5V 0.20A Type A Connector 10µF HDMA or HDMB HDPA or HDPB 100nF 10nF 27Ω 27Ω 15kΩ 15kΩ 47pF 47pF As device connection is automatically detected by the USB host port logic, a pull-down must be connected on DP and DM on the board. Otherwise the USB host will permanently detect a device connection on this port. 592 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36. Ethernet MAC (EMAC) 36.1 Overview The Ethernet MAC is the hardware implementation of the MAC sub-layer OSI reference model between the physical layer (PHY) and the logical link layer (LLC). It controls the data exchange between a host and a PHY layer according to Ethernet IEEE 802.3u data frame format. The Ethernet MAC contains the required logic and transmit and receive FIFOs for DMA management. In addition, it is interfaced through MDIO/MDC pins for PHY layer management. The Ethernet MAC can transfer data in media-independent interface (MII) or reduced mediaindependent interface (RMII) modes depending on the pinout configuration. The aim of the reduced interface is to lower the pin count for a switch product that can be connected to multiple PHY interfaces. The characteristics specific to RMII mode are: • Single clock at 50 MHz frequency • Reduction of required control pins • Reduction of data paths to di-bit (2-bit wide) by doubling clock frequency • 10 Mbits/sec. and 100 Mbits/sec. data capability The major features of the EMAC are: • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operation • MII or RMII interface to the physical layer • Register interface to address, status and control registers • DMA interface • Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Supports promiscuous mode where all valid frames are copied to memory • Supports physical layer management through MDIO interface control of alarm and update time/calendar data in 593 1768G–ATARM–29-Sep-06 36.2 Block Diagram Figure 36-1. Block Diagram ASB DMA ETXCK-ERXCK-EREFCK EXTEN-EXTER APB Bridge ECRS-ECOL ERXER-ERXDV APB Ethernet MAC PIO ERX0-ERX3 ETX0-ETX3 EMDC PMC MCK Interrupt Control EMDIO EF100 EMAC IRQ 36.3 Application Block Diagram Figure 36-2. Ethernet MAC Application Block Diagram MIB Functions SNMP AGENT SNMP WEB Pages WEB Server HTTP TELNET Console TELNET Server TELNET FTP Server FTP TCP/IP Socket API UDP TCP IP ARP/RARP ETHERNET Driver EMAC (802.3 compliant) Physical Medium Independant Layer (MII or RMII) Physical Medium Dependant Layer (10 Base-T Phy) Link Connector (RJ45) NETWORK 594 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.4 36.4.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the EMAC pins to their peripheral functions. In RMII mode, unused pins (see Table 36-1: MII/RMII Signal Mapping) can be used as general I/O lines. 36.4.2 Power Management The EMAC may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the EMAC clock. If not used, about 400 µA current consumption can be saved by switching the EMAC in Local Loopback Mode with the following sequence: • EMAC clock is enabled – write 0x1000000 in PMC_PCER • EMAC Local Loopback is enabled – set bit 1 in EMAC_CTL • EMAC clock is disabled – write 0x1000000 in PMC_PCDR 36.4.3 Interrupt The EMAC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the EMAC interrupt requires programming the AIC before configuring the EMAC. 595 1768G–ATARM–29-Sep-06 36.5 Functional Description The Ethernet Media Access Control (EMAC) engine is fully compatible with the IEEE 802.3 Ethernet standard. It manages frame transmission and reception including collision detection, preamble generation and detection, CRC control and generation and transmitted frame padding. The MAC functions are: • Frame encapsulation and decapsulation • Error detection • Media access management (MII, RMII) Figure 36-3. EMAC Functional Block Diagram EMAC Address Checker APB Register Interface Statistics Registers Control Registers MDIO ASB DMA Interface Ethernet Receive RMII/MII Ethernet Transmit MII/RMII 596 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.5.1 36.5.1.1 Media Independent Interface General The Ethernet MAC is capable of interfacing to both RMII and MII Interfaces. The RMII bit in the ETH_CFG register controls the interface that is selected. When this bit is set, the RMII interface is selected, else the MII interface is selected. The MII and RMII interface are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by the MII and RMII interfaces are described in the Table 36-1. Table 36-1. Pin Name ETXCK_REFCK ECRS_ECRSDV ECOL ERXDV ERX0 - ERX3 ERXER ERXCK ETXEN ETX0-ETX3 ETXER Pin Configurations MII ETXCK: Transmit Clock ECRS: Carrier Sense ECOL: Collision Detect ERXDV: Data Valid ERX0 - ERX3: 4-bit Receive Data ERXER: Receive Error ERXCK: Receive Clock ETXEN: Transmit Enable ETX0 - ETX3: 4-bit Transmit Data ETXER: Transmit Error ETXEN: Transmit Enable ETX0 - ETX1: 2-bit Transmit Data ERX0 - ERX1: 2-bit Receive Data ERXER: Receive Error RMII REFCK: Reference Clock ECRSDV: Carrier Sense/Data Valid The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It uses 2 bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error (ERXER), a Carrier Sense (ECRS_DV), and a 50 MHz Reference Clock (ETXCK_REFCK) for 100Mb/s data rate. 36.5.1.2 RMII Transmit and Receive Operation The same signals are used internally for both the RMII and the MII operations. The RMII maps these signals in a more pin-efficient manner. The transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. The carrier sense and data valid signals are combined into the ECRS_ECRSDV signal. This signal contains information on carrier sense, FIFO status, and validity of the data. Transmit error bit (ETXER) and collision detect (ECOL) are not used in RMII mode. 597 1768G–ATARM–29-Sep-06 36.5.2 Transmit/Receive Operation A standard IEEE 802.3 packet consists of the following fields: preamble, start of frame delimiter (SFD), destination address (DA), source address (SA), length, data (Logical Link Control Data) and frame check sequence CRC32 (FCS). Table 36-2. Packet Format Frame(1) SFD 1 byte DA 6 bytes SA 6 bytes Length/type 2 bytes LLC Data PAD FCS 4 bytes Preamble Alternating 1s/0s Up to 7 bytes Note: Frame Length between 64 bytes and 1518 bytes. The packets are Manchester-encoded and -decoded and transferred serially using NRZ data with a clock. All fields are of fixed length except for the data field. The MAC generates and appends the preamble, SFD and CRC fields during transmission. The preamble and SFD fields are stripped during reception. 36.5.2.1 Preamble and Start of Frame Delimiter (SFD) The preamble field is used to acquire bit synchronization with an incoming packet. When transmitted, each packet contains 62 bits of alternating 1,0 preamble. Some of this preamble is lost as the packet travels through the network. Byte alignment is performed with the Start of Frame Delimiter (SFD) pattern that consists of two consecutive 1's. 36.5.2.2 Destination Address The destination address (DA) indicates the destination of the packet on the network and is used to filter unwanted packets. There are three types of address formats: physical, multicast and broadcast. The physical address is a unique address that corresponds only to a single node. All physical addresses have an MSB of 0. Multicast addresses begin with an MSB of 1. The MAC filters multicast addresses using a standard hashing algorithm that maps all multicast addresses into a 6-bit value. This 6-bit value indexes a 64-bit array that filters the value. If the address consists of all ones, it is a broadcast address, indicating that the packet is intended for all nodes. 36.5.2.3 Source Address The source address (SA) is the physical address of the node that sent the packet. Source addresses cannot be multicast or broadcast addresses. This field is passed to buffer memory. 36.5.2.4 Length/Type If the value of this field is less than or equal to 1500, then the Length/Type field indicates the number of bytes in the subsequent LLC Data field. If the value of this field is greater than or equal to 1536, then the Length/Type field indicates the nature of the MAC client protocol (protocol type). 36.5.2.5 LLC Data The data field consists of anywhere from 46 to 1500 bytes. Messages longer than 1500 bytes need to be broken into multiple packets. Messages shorter than 46 bytes require appending a pad to bring the data field to the minimum length of 46 bytes. If the data field is padded, the number of valid data bytes is indicated in the length field. 598 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.5.2.6 FCS Field The Frame Check Sequence (FCS) is a 32-bit CRC field, calculated and appended to a packet during transmission to allow detection of errors when a packet is received. During reception, error free packets result in a specific pattern in the CRC generator. Packets with improper CRC will be rejected. 36.5.3 Frame Format Extensions The original Ethernet standards defined the minimum frame size as 64 bytes and the maximum as 1518 bytes. These numbers include all bytes from the Destination MAC Address field through the Frame Check Sequence field. The Preamble and Start Frame Delimiter fields are not included when quoting the size of a frame. The IEEE 802.3ac standard extended the maximum allowable frame size to 1522 bytes to allow a VLAN tag to be inserted into the Ethernet frame format. The bit BIG defined in the ETH_CFG register aims to process packet with VLAN tag. The VLAN protocol permits insertion of an identifier, or tag, into the Ethernet frame format to identify the VLAN to which the frame belongs. It allows frames from stations to be assigned to logical groups. This provides various benefits, such as easing network administration, allowing formation of work groups, enhancing network security, and providing a means of limiting broadcast domains (refer to IEEE standard 802.1Q for definition of the VLAN protocol). The 802.3ac standard defines only the implementation details of the VLAN protocol that are specific to Ethernet. If present, the 4-byte VLAN tag is inserted into the Ethernet frame between the Source MAC Address field and the Length field. The first 2-bytes of the VLAN tag consist of the “802.1Q Tag Type” and are always set to a value of 0x8100. The 0x8100 value is a reserved Length/Type field assignment that indicates the presence of the VLAN tag, and signals that the traditional Length/Type field can be found at an offset of four bytes further into the frame. The last two bytes of the VLAN tag contain the following information: • The first three bits are a User Priority Field that may be used to assign a priority level to the Ethernet frame. • The following one bit is a Canonical Format Indicator (CFI) used in Ethernet frames to indicate the presence of a Routing Information Field (RIF). • The last twelve bits are the VLAN Identifier (VID) that uniquely identifies the VLAN to which the Ethernet frame belongs. With the addition of VLAN tagging, the 802.3ac standard permits the maximum length of an Ethernet frame to be extended from 1518 bytes to 1522 bytes. Table 36-3 illustrates the format of an Ethernet frame that has been “tagged” with a VLAN identifier according to the IEEE 802.3ac standard. Table 36-3. Preamble Start Frame Delimiter Dest. MAC Address Source MAC Address Length/Type = 802.1Q Tag Type Tag Control Information Length / Type Ethernet Frame with VLAN Tagging 7 bytes 1 byte 6 bytes 6 bytes 2 byte 2 bytes 2 bytes 599 1768G–ATARM–29-Sep-06 Table 36-3. Ethernet Frame with VLAN Tagging (Continued) 0 - n bytes 0 - p bytes 4 bytes MAC Client Data Pad Frame Check Sequence 36.5.4 DMA Operations Frame data is transferred to and from the Ethernet MAC via the DMA interface. All transfers are 32-bit words and may be single accesses or bursts of two, three or four words. Burst accesses do not cross 16-byte boundaries. The DMA controller performs four types of operations on the ASB bus. In order of priority, these operations are receive buffer manager read, receive buffer manager write, transmit data DMA read and receive data DMA write. 36.5.4.1 Transmitter Mode Transmit frame data needs to be stored in contiguous memory locations. It does not need to be word-aligned. The transmit address register is written with the address of the first byte to be transmitted. Transmit is initiated by writing the number of bytes to transfer (length) to the transmit control register. The transmit channel then reads data from memory 32 bits at a time and places them in the transmit FIFO. The transmit block starts frame transmission when three words have been loaded into the FIFO. The transmit address register must be written before the transmit control register. While a frame is being transmitted, it is possible to set up one other frame for transmission by writing new values to the transmit address and control registers. Reading the transmit address register returns the address of the buffer currently being accessed by the transmit FIFO. Reading the transmit control register returns the total number of bytes to be transmitted. The BNQ bit in the Transmit Status Register indicates whether another buffer can be safely queued. An interrupt is generated whenever this bit is set. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO word-by-word. If necessary, padding is added to make the frame length 60 bytes. The CRC is calculated as a 32-bit polynomial. This is inverted and appended to the end of the frame, making the frame length a minimum of 64 bytes. The CRC is not appended if the NCRC bit is set in the transmit control register. In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at least 96 bit times apart to guarantee the inter-frame gap. In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert and then starts transmission after the inter-frame gap of 96 bit-times. If the collision signal is asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the data register and then retries transmission after the backoff time has elapsed. An error is indicated and any further attempts aborted if 16 attempts cause collisions. 600 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as jam insertion. Underrun also causes TXER to be asserted. 36.5.4.2 Receiver Mode When a packet is received, it is checked for valid preamble, CRC, alignment, length and address. If all these criteria are met, the packet is stored successfully in a receive buffer. If at the end of reception the CRC is bad, then the received buffer is recovered. Each received frame including CRC is written to a single receive buffer. Receive buffers are word-aligned and are capable of containing 1518 or 1522 bytes (BIG = 1 in ETH_CFG) of data (the maximum length of an Ethernet frame). The start location for each received frame is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. Each entry in the list consists of two words. The first word is the address of the received buffer; the second is the receive status. Table 36-4 defines an entry in the received buffer descriptor list. To receive frames, the buffer queue must be initialized by writing an appropriate address to bits [31:2] in the first word of each list entry. Bit zero of word zero must be written with zero. After a frame is received, bit zero becomes set and the second word indicates what caused the frame to be copied to memory. The start location of the received buffer descriptor list should be written to the received buffer queue pointer register before receive is enabled (by setting the receive enable bit in the network control register). As soon as the received block starts writing received frame data to the receive FIFO, the received buffer manager reads the first receive buffer location pointed to by the received buffer queue pointer register. If the filter block is active, the frame should be copied to memory; the receive data DMA operation starts writing data into the receive buffer. If an error occurs, the buffer is recovered. If the frame is received without error, the queue entry is updated. The buffer pointer is rewritten to memory with its low-order bit set to indicate successful frame reception and a used buffer. The next word is written with the length of the frame and how the destination address was recognized. The next receive buffer location is then read from the following word or, if the current buffer pointer had its wrap bit set, the beginning of the table. The maximum number of buffer pointers before a wrap bit is seen is 1024. If a wrap bit is not seen by then, a wrap bit is assumed in that entry. The received buffer queue pointer register must be written with zero in its lower-order bit positions to enable the wrap function to work correctly. If bit zero is set when the receive buffer manager reads the location of the receive buffer, then the buffer has already been used and cannot be used again until software has processed the frame and cleared bit zero. In this case, the DMA block sets the buffer unavailable bit in the received status register and triggers an interrupt. The frame is discarded and the queue entry is reread on reception of the next frame to see if the buffer is now available. Each discarded frame increments a statistics register that is cleared on being read. When there is network congestion, it is possible for the MAC to be programmed to apply back pressure. This is when half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (a default pattern). Reading the received buffer queue register returns the location of the queue entry currently being accessed. The queue wraps around to the start after either 1024 entries (i.e., 2048 words) or when the wrap bit is found to be set in bit 1 of the first word of an entry. 601 1768G–ATARM–29-Sep-06 Table 36-4. Bit Word 0 31:2 1 Received Buffer Descriptor List Function Base address of receive buffer Wrap bit. If this bit is set, the counter that is ORed with the received buffer queue pointer register to give the pointer to entries in this table is cleared after the buffer is used. Ownership bit. 1 indicates software owns the pointer, 0 indicates that the DMA owns the buffer. If this bit is not zero when the entry is read by the receiver, the buffer unavailable bit is set in the received status register and the receiver goes inactive. 0 Word 1 31 30 29 28 27 26 25 24 23 22:11 10:0 Global all ones broadcast address detected Multicast hash match Unicast hash match External address (optional) Unknown source address (reserved for future use) Local address match (Specific address 1 match) Local address match (Specific address 2 match) Local address match (Specific address 3 match) Local address match (Specific address 4 match) Reserved; written to 0 Length of frame including FCS 36.5.5 Address Checking Whether or not a frame is stored depends on what is enabled in the network configuration register, the contents of the specific address and hash registers and the frame destination address. In this implementation of the MAC the frame source address is not checked. A frame is not copied to memory if the MAC is transmitting in half-duplex mode at the time a destination address is received. The hash register is 64 bits long and takes up two locations in the memory map. There are four 48-bit specific address registers, each taking up two memory locations. The first location contains the first four bytes of the address; the second location contains the last two bytes of the address stored in its least significant byte positions. The addresses stored can be specific, group, local or universal. Ethernet frames are transmitted a byte at a time, LSB first. The first bit (i.e., the LSB of the first byte) of the destination address is the group/individual bit and is set one for multicast addresses and zero for unicast. This bit corresponds to bit 24 of the first word of the specific address register. The MSB of the first byte of the destination address corresponds to bit 31 of the specific address register. The specific address registers are compared to the destination address of received frames once they have been activated. Addresses are deactivated at reset or when the first byte [47:40] is written and activated or when the last byte [7:0] is written. If a receive frame address matches an 602 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 active address, the local match signal is set and the store frame pulse signal is sent to the DMA block via the HCLK synchronization block. A frame can also be copied if a unicast or multicast hash match occurs, it has the broadcast address of all ones, or the copy all frames bit in the network configuration register is set. The broadcast address of 0xFFFFFFFF is recognized if the no broadcast bit in the network configuration register is zero. This sets the broadcast match signal and triggers the store frame signal. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. So all multicast frames can be received by setting all bits in the hash register. The CRC algorithm reduces the destination address to a 6-bit index into a 64-bit hash register.If the equivalent bit in the register is set, the frame is matched depending on whether the frame is multicast or unicast and the appropriate match signals are sent to the DMA block. If the copy all frames bit is set in the network configuration register, the store frame pulse is always sent to the DMA block as soon as any destination address is received. 603 1768G–ATARM–29-Sep-06 36.6 Ethernet MAC (EMAC) User Interface EMAC Register Mapping Register EMAC Control Register EMAC Configuration Register EMAC Status Register EMAC Transmit Address Register EMAC Transmit Control Register EMAC Transmit Status Register EMAC Receive Buffer Queue Pointer Reserved EMAC Receive Status Register EMAC Interrupt Status Register EMAC Interrupt Enable Register EMAC Interrupt Disable Register EMAC Interrupt Mask Register EMAC PHY Maintenance Register Register Name ETH_CTL ETH_CFG ETH_SR ETH_TAR ETH_TCR ETH_TSR ETH_RBQP – ETH_RSR ETH_ISR ETH_IER ETH_IDR ETH_IMR ETH_MAN (1) Table 36-5. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 Read/Write Read/Write Read/Write Read-only Read/Write Read/Write Read/Write Read/Write Read-only Read/Write Read/Write Write-only Write-only Read-only Read/Write Reset 0x0 0x800 0x6 0x0 0x0 0x18 0x0 0x0 0x0 0x0 – – 0xFFF 0x0 Statistics Registers 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 Frames Transmitted OK Register Single Collision Frame Register Multiple Collision Frame Register Frames Received OK Register Frame Check Sequence Error Register Alignment Error Register Deferred Transmission Frame Register Late Collision Register Excessive Collision Register Transmit Underrun Error Register Carrier Sense Error Register Discard RX Frame Register Receive Overrun Regsiter Code Error Register Excessive Length Error Register Receive Jabber Register Undersize Frame Register SQE Test Error Register ETH_FRA ETH_SCOL ETH_MCOL ETH_OK ETH_SEQE ETH_ALE ETH_DTE ETH_LCOL ETH_ECOL ETH_TUE ETH_CSE ETH_DRFC ETH_ROV ETH_CDE ETH_ELR ETH_RJB ETH_USF ETH_SQEE Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 604 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 36-5. Offset EMAC Register Mapping (Continued) Register Register Name Address Registers Read/Write Reset 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 Note: EMAC Hash Address Low [31:0] EMAC Hash Address High [63:32] EMAC Specific Address 1 Low, First 4 Bytes EMAC Specific Address 1 High, Last 2 Bytes EMAC Specific Address 2 Low, First 4 Bytes EMAC Specific Address 2 High, Last 2 Bytes EMAC Specific Address 3 Low, First 4 Bytes EMAC Specific Address 3 High, Last 2 Bytes EMAC Specific Address 4 Low, First 4 Bytes ETH_HSL ETH_HSH ETH_SA1L ETH_SA1H ETH_SA2L ETH_SA2H ETH_SA3L ETH_SA3H ETH_SA4L Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 EMAC Specific Address 4 High, Last 2 ETH_SA4H Bytes 1. For further details on the statistics registers, see Table 36-6 on page 621. 605 1768G–ATARM–29-Sep-06 36.6.1 Name: EMAC Control Register ETH_CTL Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 BP 0 WES ISR CSR MPE TE RE LBL LB • LB: Loopback Optional. When set, loopback signal is at high level. • LBL: Loopback Local When set, connects ETX[3:0] to ERX[3:0], ETXEN to ERXDV, forces full duplex and drives ERXCK and ETXCK_REFCK with MCK divided by 4. • RE: Receive Enable When set, enables the Ethernet MAC to receive data. • TE: Transmit Enable When set, enables the Ethernet transmitter to send data. • MPE: Management Port Enable Set to one to enable the management port. When zero, forces MDIO to high impedance state. • CSR: Clear Statistics Registers This bit is write-only. Writing a one clears the statistics registers. • ISR: Increment Statistics Registers This bit is write-only. Writing a one increments all the statistics registers by one for test purposes. • WES: Write Enable for Statistics Registers Setting this bit to one makes the statistics registers writable for functional test purposes. • BP: Back Pressure If this field is set, then in half-duplex mode collisions are forced on all received frames by transmitting 64 bits of data (default pattern). 606 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.6.2 Name: Access Type: 31 EMAC Configuration Register ETH_CFG Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 RMII 5 RTY 4 3 CLK 2 EAE 1 BIG 0 UNI MTI NBC CAF – BR FD SPD • SPD: Speed Set to 1 to indicate 100 Mbit/sec, 0 for 10 Mbit/sec. Has no other functional effect. • FD: Full Duplex If set to 1, the transmit block ignores the state of collision and carrier sense and allows receive while transmitting. • BR: Bit Rate Optional. • CAF: Copy All Frames When set to 1, all valid frames are received. • NBC: No Broadcast When set to 1, frames addressed to the broadcast address of all ones are not received. • MTI: Multicast Hash Enable When set multicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register. • UNI: Unicast Hash Enable When set, unicast frames are received when six bits of the CRC of the destination address point to a bit that is set in the hash register. • BIG: Receive 1522 Bytes When set, the MAC receives up to 1522 bytes. Normally the MAC receives frames up to 1518 bytes in length. This bit allows to receive extended Ethernet frame with “VLAN tag” (IEEE 802.3ac) • EAE: External Address Match Enable Optional. 607 1768G–ATARM–29-Sep-06 • CLK The system clock (MCK) is divided down to generate MDC (the clock for the MDIO). To conform with IEEE standard 802.3 MDC must not exceed 2.5 MHz. At reset this field is set to 10 so that MCK is divided by 32. CLK 00 01 10 11 MDC MCK divided by 8 MCK divided by 16 MCK divided by 32 MCK divided by 64 • RTY: Retry Test When set, the time between frames is always one time slot. For test purposes only. Must be cleared for normal operation. • RMII: Reduce MII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. 608 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.6.3 Name: Access Type: 31 EMAC Status Register ETH_SR Read only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – IDLE MDIO LINK • LINK Reserved. • MDIO 0 = MDIO pin not set. 1 = MDIO pin set. • IDLE 0 = PHY logic is idle. 1 = PHY logic is running. 609 1768G–ATARM–29-Sep-06 36.6.4 Name: EMAC Transmit Address Register ETH_TAR Read/Write 30 29 28 27 26 25 24 Access Type: 31 ADDRESS 23 22 21 20 19 18 17 16 ADDRESS 15 14 13 12 11 10 9 8 ADDRESS 7 6 5 4 3 2 1 0 ADDRESS • ADDRESS: Transmit Address Register Written with the address of the frame to be transmitted, read as the base address of the buffer being accessed by the transmit FIFO. Note that if the two least significant bits are not zero, transmit starts at the byte indicated. 36.6.5 Name: EMAC Transmit Control Register ETH_TCR Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 NCRC 7 – 6 – 5 – 4 – 3 2 LEN 1 0 LEN • LEN: Transmit Frame Length This register is written to the number of bytes to be transmitted excluding the four CRC bytes unless the no CRC bit is asserted. Writing these bits to any non-zero value initiates a transmission. If the value is greater than 1514 (1518 if no CRC is being generated), an oversize frame is transmitted. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Must always be written in address-then-length order. Reads as the total number of bytes to be transmitted (i.e., this value does not change as the frame is transmitted.) Frame transmission does not start until two 32-bit words have been loaded into the transmit FIFO. The length must be great enough to ensure two words are loaded. • NCRC: No CRC If this bit is set, it is assumed that the CRC is included in the length being written in the low-order bits and the MAC does not append CRC to the transmitted frame. If the buffer is not at least 64 bytes long, a short frame is sent. This field is buffered so that a new frame can be queued while the previous frame is still being transmitted. Reads as the value of the frame currently being transmitted. 610 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.6.6 Name: Access Type: 31 EMAC Transmit Status Register ETH_TSR Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – UND COMP BNQ IDLE RLE COL OVR • OVR: Ethernet Transmit Buffer Overrun Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when bit BNQ was not set. Cleared by writing a one to this bit. • COL: Collision Occurred Set by the assertion of collision. Cleared by writing a one to this bit. • RLE: Retry Limit Exceeded Cleared by writing a one to this bit. • IDLE: Transmitter Idle Asserted when the transmitter has no frame to transmit. Cleared when a length is written to transmit frame length portion of the Transmit Control register. This bit is read-only. • BNQ: Ethernet Transmit Buffer not Queued Software may write a new buffer address and length to the transmit DMA controller when set. Cleared by having one frame ready to transmit and another in the process of being transmitted. This bit is read-only. • COMP: Transmit Complete Set when a frame has been transmitted. Cleared by writing a one to this bit. • UND: Transmit Underrun Set when transmit DMA was not able to read data from memory in time. If this happens, the transmitter forces bad CRC. Cleared by writing a one to this bit. 611 1768G–ATARM–29-Sep-06 36.6.7 Name: EMAC Receive Buffer Queue Pointer Register ETH_RBQP Read/Write 30 29 28 27 26 25 24 Access Type: 31 ADDRESS 23 22 21 20 19 18 17 16 ADDRESS 15 14 13 12 11 10 9 8 ADDRESS 7 6 5 4 3 2 1 0 ADDRESS • ADDRESS: Receive Buffer Queue Pointer Written with the address of the start of the receive queue, reads as a pointer to the current buffer being used. The receive buffer is forced to word alignment. 36.6.8 Name: Access Type: 31 EMAC Receive Status Register ETH_RSR Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – OVR REC BNA • BNA: Buffer Not Available An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor. The DMA rereads the pointer each time a new frame starts until a valid pointer is found. This bit is set at each attempt that fails even if it has not had a successful pointer read since it has been cleared. Cleared by writing a one to this bit. • REC: Frame Received One or more frames have been received and placed in memory. Cleared by writing a one to this bit. • OVR: RX Overrun The DMA block was unable to store the receive frame to memory, either because the ASB bus was not granted in time or because a not OK HRESP was returned. The buffer is recovered if this happens. Cleared by writing a one to this bit. 612 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.6.9 Name: Access Type: 31 EMAC Interrupt Status Register ETH_ISR Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ABT 3 ROVR 2 LINK 1 TIDLE 0 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE • DONE: Management Done The PHY maintenance register has completed its operation. Cleared on read. • RCOM: Receive Complete A frame has been stored in memory. Cleared on read. • RBNA: Receive Buffer Not Available Cleared on read. • TOVR: Transmit Buffer Overrun Software has written to the Transmit Address Register (ETH_TAR) or Transmit Control Register (ETH_TCR) when BNQ of the Transmit Status Register (ETH_TSR) was not set. Cleared on read. • TUND: Transmit Buffer Underrun Ethernet transmit buffer underrun. The transmit DMA did not complete fetch frame data in time for it to be transmitted. Cleared on read. • RTRY: Retry Limit Retry limit exceeded. Cleared on read. • TBRE: Transmit Buffer Register Empty Software may write a new buffer address and length to the transmit DMA controller. Cleared by having one frame ready to transmit and another in the process of being transmitted. Cleared on read. • TCOM: Transmit Complete Set when a frame has been transmitted. Cleared on read. • TIDLE: Transmit Idle Set when all frames have been transmitted. Cleared on read. 613 1768G–ATARM–29-Sep-06 • LINK Set when LINK pin changes value. Optional. • ROVR: RX Overrun Set when the RX overrun status bit is set. Cleared on read. • ABT: Abort Set when an abort occurs during a DMA transfer. Cleared on read. 614 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.6.10 Name: Access Type: 31 EMAC Interrupt Enable Register ETH_IER Write only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ABT 3 ROVR 2 LINK 1 TIDLE 0 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE • DONE: Management Done Interrupt Enable • RCOM: Receive Complete Interrupt Enable • RBNA: Receive Buffer Not Available Interrupt Enable • TOVR: Transmit Buffer Overrun Interrupt Enable • TUND: Transmit Buffer Underrun Interrupt Enable • RTRY: Retry Limit Interrupt Enable • TBRE: Transmit Buffer Register Empty Interrupt Enable • TCOM: Transmit Complete Interrupt Enable • TIDLE: Transmit Idle Interrupt Enable • LINK: LINK Interrupt Enable • ROVR: RX Overrun Interrupt Enable • ABT: Abort Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. 615 1768G–ATARM–29-Sep-06 36.6.11 Name: EMAC Interrupt Disable Register ETH_IDR Write only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ABT 3 ROVR 2 LINK 1 TIDLE 0 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE • DONE: Management Done Interrupt Disable • RCOM: Receive Complete Interrupt Disable • RBNA: Receive Buffer Not Available Interrupt Disable • TOVR: Transmit Buffer Overrun Interrupt Disable • TUND: Transmit Buffer Underrun Interrupt Disable • RTRY: Retry Limit Interrupt Disable • TBRE: Transmit Buffer Register Empty Interrupt Disable • TCOM: Transmit Complete Interrupt Disable • TIDLE: Transmit Idle Interrupt Disable • LINK: LINK Interrupt Disable • ROVR: RX Overrun Interrupt Disable • ABT: Abort Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. 616 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.6.12 Name: Access Type: 31 EMAC Interrupt Mask Register ETH_IMR Read only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 ABT 3 ROVR 2 LINK 1 TIDLE 0 TCOM TBRE RTRY TUND TOVR RBNA RCOM DONE • DONE: Management Done Interrupt Mask • RCOM: Receive Complete Interrupt Mask • RBNA: Receive Buffer Not Available Interrupt Mask • TOVR: Transmit Buffer Overrun Interrupt Mask • TUND: Transmit Buffer Underrun Interrupt Mask • RTRY: Retry Limit Interrupt Mask • TBRE: Transmit Buffer Register Empty Interrupt Mask • TCOM: Transmit Complete Interrupt Mask • TIDLE: Transmit Idle Interrupt Mask • LINK: LINK Interrupt Mask • ROVR: RX Overrun Interrupt Mask • ABT: Abort Interrupt Mask 0: The corresponding interrupt is enabled. 1: The corresponding interrupt is not enabled. Important Note: The interrupt is disabled when the corresponding bit is set. This is non-standard for AT91 products as generally a mask bit set enables the interrupt. 617 1768G–ATARM–29-Sep-06 36.6.13 Name: EMAC PHY Maintenance Register ETH_MAN Read/Write 30 29 28 27 26 25 24 Access Type: 31 LOW 23 HIGH 22 21 RW 20 19 18 PHYA 17 16 PHYA 15 14 13 REGA 12 11 10 9 CODE 8 DATA 7 6 5 4 3 2 1 0 DATA Writing to this register starts the shift register that controls the serial connection to the PHY. On each shift cycle the MDIO pin becomes equal to the MSB of the shift register and LSB of the shift register becomes equal to the value of the MDIO pin. When the shifting is complete an interrupt is generated and the IDLE field is set in the Network Status register. When read, gives current shifted value. • DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. • CODE Must be written to 10 in accordance with IEEE standard 802.3. Reads as written. • REGA Register address. Specifies the register in the PHY to access. • PHYA PHY address. Normally is 0. • RW Read/Write Operation. 10 is read. 01 is write. Any other value is an invalid PHY management frame. • HIGH Must be written with 1 to make a valid PHY management frame. Conforms with IEEE standard 802.3. • LOW Must be written with 0 to make a valid PHY management frame. Conforms with IEEE standard 802.3. 618 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.6.14 Name: Access Type: 31 EMAC Hash Address Low Register ETH_HSL Read/Write 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 7 6 5 4 3 2 1 0 ADDR • ADDR Hash address bits 31 to 0. 36.6.15 Name: Access Type: 31 EMAC Hash Address High Register ETH_HSH Read/Write 30 29 28 27 26 25 24 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 7 6 5 4 3 2 1 0 ADDR • ADDR Hash address bits 63 to 32. 619 1768G–ATARM–29-Sep-06 36.6.16 Name: EMAC Specific Address (1, 2, 3 and 4) High Register ETH_SA1H,...ETH_SA4H Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 ADDR 7 6 5 4 3 2 1 0 ADDR • ADDR Unicast addresses (1, 2, 3 and 4), Bits 47:32. 36.6.17 Name: EMAC Specific Address (1, 2, 3 and 4) Low Register ETH_SA1L,...ETH_SA4L Read/Write 30 29 28 27 26 25 24 Access Type: 31 ADDR 23 22 21 20 19 18 17 16 ADDR 15 14 13 12 11 10 9 8 ADDR 7 6 5 4 3 2 1 0 ADDR • ADDR Unicast addresses (1, 2, 3 and 4), Bits 31:0. 620 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 36.6.18 EMAC Statistics Register Block Registers These registers reset to zero on a read and remain at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The statistics register block contains the registers found in Table 36-6. Table 36-6. Register Frames Transmitted OK Register Single Collision Frame Register Multiple Collision Frame Register Frames Received OK Register EMAC Statistic Register Block Register Descriptions Register Name ETH_FRA ETH_SCOL ETH_MCOL Description A 24-bit register counting the number of frames successfully transmitted. A 16-bit register counting the number of frames experiencing a single collision before being transmitted and experiencing no carrier loss nor underrun. A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being transmitted (62 - 1518 bytes, no carrier loss, no underrun). A 24-bit register counting the number of good frames received, i.e., address recognized. A good frame is of length 64 to 1518 bytes and has no FCS, alignment or code errors. An 8-bit register counting address-recognized frames that are an integral number of bytes long, that have bad CRC and that are 64 to 1518 bytes long. An 8-bit register counting frames that: - are address-recognized, - are not an integral number of bytes long, - have bad CRC when their length is truncated to an integral number of bytes, - are between 64 and 1518 bytes long. A 16-bit register counting the number of frames experiencing deferral due to carrier sense active on their first attempt at transmission (no underrun or collision). An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. No carrier loss or underrun. A late collision is counted twice, i.e., both as a collision and a late collision. An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions (64 - 1518 bytes, no carrier loss or underrun). An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other register is incremented. An 8-bit register counting the number of frames for which carrier sense was not detected and that were maintained in half-duplex mode one slot time (512 bits) after the start of transmission (no excessive collision). This 16-bit counter is incremented every time an address-recognized frame is received but cannot be copied to memory because no receive buffer is available. An 8-bit register counting the number of frames that are address-recognized but were not copied to memory due to a receive DMA overrun. An 8-bit register counting the number of frames that are address-recognized, had RXER asserted during reception. If this counter is incremented, then no other counters are incremented. ETH_OK Frame Check Sequence Error Register Alignment Error Register ETH_SEQE ETH_ALE Deferred Transmission Frame Register Late Collision Register ETH_DTE ETH_LCOL Excessive Collision Register ETH_ECOL Transmit Underrun Error Register Carrier Sense Error Register ETH_TUE ETH_CSE Discard RX Frame Register ETH_DRFC Receive Overrun Register Code Error Register ETH_ROV ETH_CDE 621 1768G–ATARM–29-Sep-06 Table 36-6. Register EMAC Statistic Register Block Register Descriptions (Continued) Register Name ETH_ELR Description An 8-bit register counting the number of frames received exceeding 1518 bytes in length but that do not have either a CRC error, an alignment error or a code error. An 8-bit register counting the number of frames received exceeding 1518 bytes in length and having either a CRC error, an alignment error or a code error. An 8-bit register counting the number of frames received less that are than 64 bytes in length but that do not have either a CRC error, an alignment error or a code error. An 8-bit register counting the number of frames where pin ECOL was not asserted within a slot time of pin ETXEN being deasserted. Excessive Length Error Register Receive Jabber Register Undersize Frame Register ETH_RJB ETH_USF SQE Test Error Register ETH_SQEE 622 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 37. AT91RM9200 Electrical Characteristics 37.1 Absolute Maximum Ratings Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 37-1. Operating Temperature (Industrial) ........-40° C to +85° C Storage Temperature ............................ -60°C to +150°C Voltage on Input Pins with Respect to Ground ................ -0.3V to VDDIO+0.3V ........................................................................ (+4V max) Maximum Operating Voltage (VDDCORE, VDDPLL and VDDOSC) .................................... 2V Maximum Operating Voltage (VDDIOM and VDDIOP) .................................................... 4V DC Output Current (SDA10, SDCKE, SDWE, RAS, CAS) .................. 16 mA DC Output Current (Any other pin) ........................................................ 8 mA 623 1768G–ATARM–29-Sep-06 37.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C. Table 37-2. Symbol VDDCORE VDDOSC VDDPLL VDDIOM VDDIOP VIL VIH DC Characteristics Parameter DC Supply Core DC Supply Oscillator DC Supply PLL DC Supply Memory I/Os DC Supply Peripheral I/Os Input Low-level Voltage Input High-level Voltage SDA10, SDCKE, SDWE, RAS, CAS pins: IOL = 16 mA(2) IOL = 0 mA(2) Other pins: IOL = 8 mA(2) IOL = 0 mA(2) SDA10, SDCKE, SDWE, RAS, CAS pins: IOH = 16 mA(2) IOH = 0 mA(2) Other pins: IOH = 8 mA(2) IOH = 0 mA(2) VDD - 0.4(1) VDD - 0.2(1) V VDD - 0.4(1) VDD - 0.2(1) 1 8 µA 30 200 208-PQFP Package 8.8 pF 256-LFBGA Package On VDDCORE = 2V, MCK = 0 Hz TA = 25°C TA = 85°C 350 2800 7.6 2000 µA 14000 kOhm µA Conditions Min 1.65 1.65 1.65 3.0 3.0 -0.3 2 Typ Max 1.95 1.95 1.95 3.6 3.6 0.8 VDD + 0.3(1) 0.4 0.2 V 0.4 0.2 Units V V V V V V V VOL Output Low-level Voltage VOH Output High-level Voltage ILEAK IPULL RPULLUP CIN Input Leakage Current Input Pull-up Current Internal Pull-up Value Input Capacitance Pullup resistors disabled VDD = 3.0V(1), VIN = 0 VDD = 3.6V , VIN = 0 (1) ISC Notes: Static Current All inputs driven TMS, TDI, TCK, NRST = 1 1. VDD is applicable to VDDIOM, VDDIOP, VDDPLL and VDDOSC 2. IO = Output Current. 624 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 37.3 • • Clocks Characteristics VDDCORE = 1.8V Ambient Temperature = 25°C These parameters are given in the following conditions: The Temperature Derating Factor described in the section 38.1.2 ”Temperature Derating Factor” on page 632 and VDDCORE Voltage Derating Factor described in the section 38.1.3 ”VDDCORE Voltage Derating Factor” on page 632 are both applicable to these characteristics. 37.3.1 Processor Clock Characteristics Processor Clock Waveform Parameters Parameter Processor Clock Frequency Processor Clock Period Processor Clock High Half-period Processor Clock Low Half-period 4.8 2.2 2.2 Conditions Min Max 209.0 Units MHz ns ns ns Table 37-3. Symbol 1/(tCPPCK) tCPPCK tCHPCK tCLPCK 37.3.2 Master Clock Characteristics Master Clock Waveform Parameters Parameter Master Clock Frequency Master Clock Period Master Clock High Half-period Master Clock Low Half-period 12.5 6.3 6.3 Conditions Min Max 80.0 Units MHz ns ns ns Table 37-4. Symbol 1/(tCPMCK) tCPMCK tCHMCK tCLMCK 37.3.3 XIN Clock Characteristics (1) XIN Clock Electrical Characteristics Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance Note (1) 20.0 0.4 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN 0.6 x tCPXIN 40 pF Conditions Min Max 50.0 Units MHz ns Table 37-5. Symbol 1/(tCPXIN) tCPXIN tCHXIN tCLXIN CIN RIN Notes: XIN Pulldown Resistor Note (1) 500 kOhm 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 in the CKGR_MOR register. (See Section 23.6.7 ”PMC Clock Generator Main Oscillator Register” on page 283.) 625 1768G–ATARM–29-Sep-06 37.4 Power Consumption The values in Table 37-6 and Table 37-7 are measured values on the AT91RM9200DK Evaluation Board with operating conditions as follows: • VDDIO = 3.3V • VDDCORE = VDDPLL = VDDOSC = 1.8V • TA = 25° C • MCK = 60 MHz • PCK = 180 Mhz • SLCK = 32.768 kHz • EMACK 50 MHz clock not connected These figures represent the power consumption measured on the VDDCORE power supply. Table 37-6. Mode Normal Power Consumption for PMC Modes(1) Conditions ARM Core clock enabled. All peripheral clocks deactivated. ARM Core clock disabled and waiting for the next interrupt. All peripheral clocks deactivated. Main oscillator and PLLs are switched off. Processor and all peripherals run at slow clock. Combination of Idle and Slow Clock Modes. Consumption 24.4 Unit Idle 13.8 mA Slow Clock Standby Note: 1.44 520 µA 1. Code in internal SRAM. Table 37-7. Peripheral PIO Controller USART MCI UDP TWI SPI SSC Power Consumption by Peripheral (1) Consumption 0.5 1.3 1.6 1.2 0.3 1.2 1.5 0.4 2.5 mA Unit Timer Counter Channel UHP EMAC (2) 3.5 3144 858 350 uA nA uA PMC PLL(3) Slow Clock Oscillator (3) Main Oscillator (4) Notes: 1. 2. 3. 4. Code in internal SRAM. Master Clock related power consumption only. Power consumption on the VDDPLL power supply. Power consumption on the VDDOSC power supply. 626 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 37.5 37.5.1 Crystal Oscillators Characteristics 32 kHz Oscillator Characteristics 32 kHz Oscillator Characteristics Parameter Crystal Oscillator Frequency Duty Cycle Measured at the PCK output pin 40 Conditions Min Typ 32.768 50 60 900 Max Unit kHz % ms Table 37-8. Symbol 1/(tCP32KHz) tST Note: VDDOSC = 1.8V , Rs = 50 kΩ CL = 12.5 pF(1) 1. Rs is the equivalent series resistance, CL is the equivalent load capacitance Startup Time 37.5.2 Main Oscillator Characteristics Main Oscillator Characteristics Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Equivalent Load Capacitance Duty Cycle CL1 = CL2 = 40 pF Measured at the PCK output pin VDDPLL = 1.8V 1/(tCPMAIN) = 3 MHz Without any capacitor connected to the main oscillator pins (XIN and XOUT) 40 Conditions Min 3 Typ 16 40 20 50 60 Max 20 Unit MHz pF pF % Table 37-9. Symbol 1/(tCPMAIN) CL1, CL2 CL tST Startup Time 14.5 ms 37.6 PLL Characteristics Table 37-10. Phase Lock Loop Characteristics Symbol Parameter Conditions 00 Field OUTA of CKGR_PLLA 10 FOUT Output Frequency 00 Field OUTB of CKGR_PLLB 10 FIN Input Frequency 150 1 180 32 MHz MHz 80 160 MHz 150 180 MHz Min 80 Typ Max 160 Unit MHz 627 1768G–ATARM–29-Sep-06 37.7 37.7.1 Transceiver Characteristics Electrical Characteristics Table 37-11. Electrical Parameters Symbol Input Levels VIL VIH VDI VCM CIN I REXT Output Levels VOL VOH VCRS Low Level Output High Level Output Output Signal Crossover Voltage Measured with RL of 1.425 kOhm tied to 3.6V Measured with RL of 14.25 kOhm tied to GND Measure conditions described in Figure 37-1 2.8 1.3 2.0 0.3 V V V Low Level High Level Differential Input Sensitivity Differential Input Common Mode Range Transceiver capacitance Hi-Z State Data Line Leakage Recommended External USB Series Resistor Capacitance to ground on each line 0V < VIN < 3.3V In series with each USB pin with ±5% -5 27 |(D+) - (D-)| 2.0 0.2 0.8 2.5 20 +5 0.8 V V V V pF µA Parameter Conditions Min Typ Max Unit 628 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 37.7.2 Switching Characteristics Table 37-12. In Slow Mode Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 400 pF CLOAD = 400 pF CLOAD = 400 pF Min 75 75 80 Typ Max 300 300 120 Unit ns ns % Table 37-13. In Full Speed Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall Time Matching Conditions CLOAD = 50 pF CLOAD = 50 pF Min 4 4 90 Typ Max 20 20 111.11 Unit ns ns % Figure 37-1. USB Data Signal Rise and Fall Times Rise Time VCRS 10% Differential Data Lines tR (a) REXT=27 ohms Fosc = 6MHz/750kHz Buffer (b) Cload tF 90% 10% Fall Time 629 1768G–ATARM–29-Sep-06 630 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 38. AT91RM9200 AC Characteristics 38.1 38.1.1 Applicable Conditions and Derating Data Conditions and Timings Computation The delays are given as typical values in the following conditions: • VDDIOM = 3.3V • VDDCORE = 1.8V • Ambient Temperature = 25°C • Load Capacitance = 0 pF • The output level change detection is (0.5 x VDDIOM). • The input level is (0.3 x VDDIOM) for a low-level detection and is (0.7 x VDDIOM) for a high-level detection. The minimum and maximum values given in the AC characteristics tables of this datasheet take into account process variation and design. In order to obtain the timing for other conditions, the following equation should be used: t = δT ° × ⎛ ( δVDDCORE × t DATASHEET ) + ⎛ δVDDIO M × ⎝ ⎝ where: • δT° is the derating factor in temperature given in Figure 38-1 on page 632. • δVDDCORE is the derating factor for the Core Power Supply given in Figure 38-2 on page 632. • tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. • δVDDIOM is the derating factor for the IOM Power Supply given in Figure 38-3 on page 633. • CSIGNAL is the capacitance load on the considered output pin(1). • δCSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet. The input delays are given as typical values. Note: 1. The user must take into account the package capacitance load contribution (CIN) described in Table 37-2, “DC Characteristics,” on page 624. ( ∑CSIGNAL × δCSIGNAL )⎞ ⎞ ⎠⎠ 631 1768G–ATARM–29-Sep-06 38.1.2 Temperature Derating Factor Figure 38-1. Derating Curve for Different Operating Temperatures 1,2 1,1 Derating Factor 1 0,9 0,8 -40 -20 0 20 40 60 80 Operating Temperature (°C) 38.1.3 VDDCORE Voltage Derating Factor Figure 38-2. Derating Curve for Different Core Supply Voltages 1,15 1,1 Derating Factor 1,05 1 0,95 0,9 1,65 1,7 1,75 1,8 Core Supply Voltage (V) 1,85 1,9 1,95 632 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 38.1.4 VDDIOM Voltage Derating Factor Figure 38-3. Derating Curve for Different IO Supply Voltages 1,1 1,05 Derating Factor 1 0,95 0,9 3 3,1 3,2 3,3 3,4 3,5 3,6 I/O Supply Voltage (V) Note: The derating factor in this example is applicable only to timings related to output pins. 633 1768G–ATARM–29-Sep-06 38.2 38.2.1 EBI Timings SMC Signals Relative to MCK Table 38-1, Table 38-2 and Table 38-3 show timings relative to operating condition limits defined in the section 38.1.1 ”Conditions and Timings Computation” on page 631. Table 38-1. Symbol SMC1 General-purpose SMC Signals Parameter MCK Falling to NUB Valid Conditions CNUB = 0 pF CNUB derating MCK Falling to NLB/A0 Valid CNLB = 0 pF CNLB derating MCK Falling to A1 - A25 Valid MCK Falling to Chip Select Change (No Address to Chip Select Setup) MCK Falling to Chip Select Active (Address to Chip Select Setup) (1) Chip Select Inactive to MCK Falling (Address to Chip Select Setup) (1) NCS Minimum Pulse Width (Address to Chip Select Setup) (1) CADD = 0 pF CADD derating CNCS = 0 pF CNCS derating CNCS = 0 pF CNCS derating CNCS = 0 pF CNCS derating CNCS = 0 pF Min 5.0 0.028 4.9 0.028 4.9 0.028 4.3 0.028 (nacss x tCPMCK) + 4.3 0.028 (nacss x tCPMCK) + 4.4 (2) -0.028 (((n + 2) - (2 x nacss)) (2) (3) x tCPMCK) (2) Max 7.5 0.045 7.5 0.045 7.4 0.045 6.5 0.045 (nacss x tCPMCK) + 6.5 0.045 (nacss x tCPMCK) + 6.5 (2) -0.045 (2) Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns SMC2 SMC3 SMC4 SMC5 SMC6 SMC7 SMC8 NWAIT Minimum Pulse Width (1) tCPMCK Notes: 1. The derating factor is not to be applied to tCPMCK. 2. nacss = Number of Address to Chip Select Setup Cycles inserted. 3. n = Number of standard Wait States inserted. 634 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 38-2. Symbol SMC10 . SMC Write Signals Parameter MCK Rising to NWR Active (No Wait States) (5) MCK Rising to NWR Active (Wait States) MCK Falling to NWR Inactive (No Wait States) (5) MCK Rising to NWR Inactive (Wait States) MCK Rising to D0 - D15 Out Valid Conditions CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CDATA = 0 pF CDATA derating NWR High to NUB Change (5) CNUB = 0 pF CNUB derating NWR High to NLB/A0 Change (5) CNLB = 0 pF CNLB derating NWR High to A1 - A25 Change (5) CADD = 0 pF CADD derating NWR High to Chip Select Inactive (5) CNCS = 0 pF CNCS derating C = 0 pF Data Out Valid before NWR High (No Wait States) (1) (5) Min 4.8 0.028 4.8 0.028 4.8 0.028 4.8 0.028 4.1 0.028 3.4 0.028 3.7 0.028 3.3 0.028 3.3 0.028 tCHMCK - 0.8 - 0.044 0.045 n x tCPMCK - 0.6 - 0.044 0.045 tCLMCK - 1.0 0.044 - 0.045 tCHMCK - 1.2 0.044 - 0.045 h x tCPMCK - 1.1 (4) 0.044 - 0.045 (2) Max 7.2 0.045 7.2 0.045 7.2 0.045 7.2 0.045 7.9 0.044 Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns/pF ns ns/pF ns/pF ns ns/pF ns/pF ns ns/pF ns/pF ns ns/pF ns/pF SMC11 SMC12 SMC13 SMC14 SMC15 SMC16 SMC17 SMC18 SMC19 CDATA derating CNWR derating C = 0 pF SMC20 Data Out Valid before NWR High (Wait States) (1) (5) CDATA derating CNWR derating C = 0 pF SMC21 Data Out Valid after NWR High (No Wait States) (1) (5) CDATA derating CNWR derating C = 0 pF SMC22 Data Out Valid after NWR High (Wait States without Hold Cycles) (1) (5) CDATA derating CNWR derating C = 0 pF SMC23 Data Out Valid after NWR High (Wait States with Hold Cycles) (1) (5) CDATA derating CNWR derating 635 1768G–ATARM–29-Sep-06 Table 38-2. Symbol SMC Write Signals (Continued) Parameter Conditions C = 0 pF Min (((n + 1) - nacss) x tCPMCK) + tCHMCK - 1.4 (2) (3) - 0.044 0.045 nacss x tCPMCK - 0.4 0.044 - 0.045 tCHMCK - 0.1 0.002 n x tCPMCK (2) 0.002 (n + 1) x tCPMCK 0.002 (2) (3) Max Units ns ns/pF ns/pF ns ns/pF ns/pF ns ns/pF ns ns/pF ns ns/pF SMC24 Data Out Valid before NCS High (Address to Chip Select Setup Cycles) (1) CDATA derating CNCS derating C = 0 pF SMC25 Data Out Valid after NCS High (Address to Chip Select Setup Cycles) (1) CDATA derating CNCS derating SMC26 SMC27 NWR Minimum Pulse Width (No Wait States) (1) (5) NWR Minimum Pulse Width (Wait States) (1) (5) NWR Minimum Pulse Width (Address to Chip Select Setup Cycles) (1) 1. 2. 3. 4. 5. CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating CNWR = 0 pF CNWR derating SMC28 Notes: The derating factor is not to be applied to tCLMCK, tCHMCK or tCPMCK. n = Number of standard Wait States inserted. nacss = Number of Address to Chip Select Setup Cycles inserted. h = Number of Hold Cycles inserted. Not applicable when Address to Chip Select Setup Cycles are inserted. 636 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 38-3. Symbol SMC29 SMC Read Signals Parameter MCK Falling to NRD Active (1) (7) Conditions CNRD = 0 pF CNRD derating MCK Rising to NRD Active (2) CNRD = 0 pF CNRD derating MCK Falling to NRD Inactive (1) (7) CNRD = 0 pF CNRD derating MCK Falling to NRD Inactive (2) D0-D15 in Setup before MCK Falling D0-D15 in Hold after MCK Falling (9) (8) Min 4.5 0.028 4.7 0.028 4.5 0.028 4.5 0.028 0.8 1.7 Max 6.8 0.045 7.0 0.045 6.8 0.045 6.8 0.045 Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns SMC30 SMC31 SMC32 SMC33 SMC34 CNRD = 0 pF CNRD derating CNUB = 0 pF SMC35 NRD High to NUB Change (3) (h x tCPMCK) + 0.5 (6) 0.028 -0.028 (h x tCPMCK) + 0.4 (6) 0.028 -0.028 (h x tCPMCK) + 0.3 (6) 0.028 -0.028 (h x tCPMCK) - 0.3 (6) 0.028 -0.028 (nacss x tCPMCK) + 0.2 (5) - 0.028 0.028 7.5 0.045 -3.4 - 0.028 7.3 0.045 (h x tCPMCK) + 0.8 (6) 0.045 -0.045 (h x tCPMCK) + 0.7 (6) 0.045 -0.045 (h x tCPMCK) + 0.6 (6) 0.045 -0.045 (h x tCPMCK) -0.2 (6) 0.045 -0.045 (nacss x tCPMCK) + 0.3 (5) - 0.045 0.045 ns ns/pF ns/pF ns ns/pF ns/pF ns ns/pF ns/pF ns ns/pF ns/pF ns ns/pF ns/pF ns ns/pF ns ns/pF ns ns/pF CNUB derating CNRD derating CNLB = 0 pF SMC36 NRD High to NLB/A0 Change (3) CNLB derating CNRD derating CADD = 0 pF SMC37 NRD High to A1-A25 Change (3) CADD derating CNRD derating CNCS = 0 pF SMC38 NRD High to Chip Select Inactive (3) CNCS derating CNRD derating CNCS = 0 pF SMC39 Chip Select Inactive to NRD High (3) CNCS derating CNRD derating SMC40 Data Setup before NRD High (8) CNRD = 0 pF CNRD derating SMC41 Data Hold after NRD High (9) CNRD = 0 pF CNRD derating SMC42 Data Setup before NCS High CNRD = 0 pF CNRD derating 637 1768G–ATARM–29-Sep-06 Table 38-3. Symbol SMC43 SMC Read Signals (Continued) Parameter Data Hold after NCS High Conditions CNRD = 0 pF CNRD derating NRD Minimum Pulse Width (1) (3) (7) CNRD = 0 pF CNRD derating NRD Minimum Pulse Width (2) (3) (7) CNRD = 0 pF CNRD derating Min -3.2 - 0.028 n x tCPMCK - 0.02 0.002 n x tCHMCK + tCHMCK - 0.2 (4) 0.002 ((n + 1) x tCHMCK) + tCHMCK- 0.2 (4) 0.002 (4) Max Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF SMC44 SMC45 SMC46 Notes: 1. 2. 3. 4. 5. 6. 7. 8. 9. NRD Minimum Pulse Width (2) (3) CNRD = 0 pF CNRD derating Early Read Protocol. Standard Read Protocol. The derating factor is not to be applied to tCHMCK or tCPMCK. n = Number of standard Wait States inserted. nacss = Number of Address to Chip Select Setup Cycles inserted. h = Number of Hold Cycles inserted. Not applicable when Address to Chip Select Setup Cycles are inserted. Only one of these two timings needs to be met. Only one of these two timings needs to be met. 638 AT91RM9200 1768G–ATARM–29-Sep-06 Notes: SMC29 SMC31 SMC29 SMC44 SMC15 SMC16 SMC44 SMC30 SMC32 SMC30 SMC32 SMC30 SMC32 Figure 38-4. SMC Signals Relative to MCK in Memory Interface Mode SMC10 SMC12 SMC11 SMC13 SMC11 SMC26 SMC27 SMC27 SMC14 SMC19 SMC21 SMC14 SMC22 SMC20 SMC14 NWR SMC20 SMC13 1. Early Read Protocol 2. Standard Read Protocol with or without Setup and Hold Cycles. NRD(1) SMC31 1768G–ATARM–29-Sep-06 SMC4 SMC4 SMC4 SMC4 SMC4 SMC4 SMC4 SMC4 SMC4 SMC4 SMC3 SMC38 SMC18 SMC38 SMC3 SMC3 SMC3 SMC38 SMC3 SMC37 SMC17 SMC8 SMC37 SMC37 SMC35 SMC1 SMC36 SMC2 SMC1 SMC2 SMC35 SMC1 SMC36 SMC2 SMC1 SMC2 SMC35 SMC36 SMC1 SMC2 SMC45 SMC45 SMC33 SMC40 SMC41 SMC34 SMC33 SMC40 SMC34 SMC41 SMC23 MCK internal signal SMC4 SMC4 NCS SMC3 A1 - A25 NWAIT SMC1 SMC2 NUB/NLB/A0 SMC45 NRD(2) SMC33 SMC34 SMC40 SMC41 D0 - D15 Read D0 - D15 to Write AT91RM9200 639 Notes: Figure 38-5. SMC Signals Relative to MCK in LCD Interface Mode SMC46 NRD(1) SMC33 SMC42 SMC43 SMC34 D0 - D15 Read SMC11 SMC28 SMC13 NWR(2) SMC14 SMC24 SMC25 D0 - D15 to Write SMC32 640 SMC5 SMC7 SMC6 SMC5 SMC7 SMC6 SMC39 SMC3 SMC37 SMC8 SMC35 SMC1 SMC36 SMC2 1. Standard Read Protocol only. 2. With standard Wait States inserted only. AT91RM9200 MCK internal signal NCS SMC3 A1 - A25 NWAIT SMC1 SMC2 NUB/NLB/A0 SMC30 1768G–ATARM–29-Sep-06 AT91RM9200 38.2.2 SDRAMC Signals Relative to SDCK Table 38-4 and Table 38-5 below show timings relative to operating condition limits defined in the section 38.1.1 ”Conditions and Timings Computation” on page 631. Table 38-4. Symbol 1/(tCPSDCK) tCPSDCK tCHSDCK tCLSDCK SDRAMC Clock Signal Parameter SDRAM Controller Clock Frequency SDRAM Controller Clock Period SDRAM Controller Clock High Half-Period SDRAM Controller Clock Low Half-Period 12.5 5.6 6.9 Conditions Min Max 80.0 Units MHz ns ns ns Table 38-5. Symbol SDRAMC1 SDRAMC Signals Parameter SDCKE High before SDCK Rising Edge (1) Conditions CSDCKE = 0 pF CSDCKE derating SDCKE Low after SDCK Rising Edge (1) CSDCKE = 0 pF CSDCKE derating SDCKE Low before SDCK Rising Edge (1) CSDCKE = 0 pF CSDCKE derating SDCKE High after SDCK Rising Edge (1) CSDCKE = 0 pF CSDCKE derating SDCS Low before SDCK Rising Edge (1) CSDCS = 0 pF CSDCS derating SDCS High after SDCK Rising Edge (1) CSDCS = 0 pF CSDCS derating RAS Low before SDCK Rising Edge (1) CRAS = 0 pF CRAS derating RAS High after SDCK Rising Edge (1) CRAS = 0 pF CRAS derating SDA10 Change before SDCK Rising Edge (1) CSDA10 = 0 pF CSDA10 derating SDA10 Change after SDCK Rising Edge (1) CSDA10 = 0 pF CSDA10 derating Address Change before SDCK Rising Edge (1) CADD = 0 pF CADD derating Address Change after SDCK Rising Edge (1) CADD = 0 pF CADD derating Min tCLMCK + 1.2 - 0.015 tCHMCK - 1.4 0.023 tCLMCK + 1.0 - 0.015 tCHMCK - 1.7 0.023 tCLMCK + 1.2 - 0.028 tCHMCK - 1.9 0.045 tCLMCK + 0.6 - 0.015 tCHMCK - 1.1 0.023 tCLMCK + 0.8 - 0.015 tCHMCK - 1.2 0.023 tCLMCK + 0.6 - 0.028 tCHMCK - 1.5 0.045 Max Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF SDRAMC2 SDRAMC3 SDRAMC4 SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 SDRAMC9 SDRAMC10 SDRAMC11 SDRAMC12 641 1768G–ATARM–29-Sep-06 Table 38-5. Symbol SDRAMC13 SDRAMC Signals (Continued) Parameter Bank Change before SDCK Rising Edge (1) Conditions CBA = 0 pF CBA derating Bank Change after SDCK Rising Edge (1) CBA = 0 pF CBA derating CAS Low before SDCK Rising Edge (1) CCAS = 0 pF CCAS derating CAS High after SDCK Rising Edge (1) CCAS = 0 pF CCAS derating DQM Change before SDCK Rising Edge (1) CDQM = 0 pF CDQM derating DQM Change after SDCK Rising Edge (1) D0-D15 in Setup before SDCK Rising Edge D0-D15 in Hold after SDCK Rising Edge D16-D31 in Setup before SDCK Rising Edge D16-D31 in Hold after SDCK Rising Edge SDWE Low before SDCK Rising Edge CSDWE = 0 pF CSDWE derating SDWE High after SDCK Rising Edge CSDWE = 0 pF CSDWE derating C = 0 pF D0-D15 Out Valid before SDCK Rising Edge CDATA derating C = 0 pF D0-D15 Out Valid after SDCK Rising Edge CDATA derating C = 0 pF D16-D31 Out Valid before SDCK Rising Edge CDATA derating C = 0 pF D16-D31 Out Valid after SDCK Rising Edge CDATA derating CDQM = 0 pF CDQM derating Min tCLMCK + 0.8 - 0.028 tCHMCK - 1.6 0.045 tCLMCK + 0.9 - 0.015 tCHMCK - 1.5 0.023 tCLMCK + 0.7 - 0.028 tCHMCK - 1.4 0.045 1.3 0.03 2.0 -0.2 tCLMCK + 1.0 - 0.015 tCHMCK - 1.8 0.023 tCLMCK - 2.7 -0.044 tCHMCK - 2.4 0.044 tCLMCK - 3.2 -0.044 tCHMCK - 2.4 0.044 Max Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns ns ns ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF SDRAMC14 SDRAMC15 SDRAMC16 SDRAMC17 SDRAMC18 SDRAMC19 SDRAMC20 SDRAMC21 SDRAMC22 SDRAMC23 SDRAMC24 SDRAMC25 SDRAMC26 SDRAMC27 SDRAMC28 Note: 1. The derating factor is not to be applied to tCLMCK or tCHMCK. 642 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 38-6. SDRAMC Signals Relative to SDCK SDCK SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDCKE SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDCS SDRAMC7 SDRAMC8 RAS SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16 CAS SDRAMC23 SDRAMC24 SDWE SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDA10 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 A0 - A9, A11 - A13 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 BA0/BA1 SDRAMC17 SDRAMC18 SDRAMC17 SDRAMC18 DQM0 DQM3 SDRAMC19 SDRAMC20 D0 - D15 Read SDRAMC21 SDRAMC22 D16 - D31 Read SDRAMC25 SDRAMC26 D0 - D15 to Write SDRAMC27 SDRAMC28 D16 - D31 to Write 643 1768G–ATARM–29-Sep-06 38.2.3 BFC Signals Relative to BFCK Table 38-6, Table 38-7 and Table 38-8 show timings relative to operating condition limits defined in the section ”Conditions and Timings Computation” on page 631. Table 38-6. Symbol BFC Clock Signal Parameter Conditions BFCK is MCK (1) Min Max 80.0 40.0 20.0 12.5 25.0 50.0 6.5 12.8 25.3 6.1 12.3 24.8 Units MHz MHz MHz ns ns ns ns ns ns ns ns ns 1/(tCPBFCK) BF Controller Clock Frequency BFCK is MCK/2 BFCK is MCK/4 (2) (3) BFCK is MCK (1) tCPBFCK BF Controller Clock Period BFCK is MCK/2 BFCK is MCK/4 BFCK is MCK tCHBFCK BF Controller Clock High Half-Period (2) (3) (1) BFCK is MCK/2 (2) BFCK is MCK/4 (3) BFCK is MCK (1) (2) tCLBFCK BF Controller Clock Low Half-Period BFCK is MCK/2 BFCK is MCK/4 (3) Notes: 1. Field BFCC = 1 in Register BFC_MR, see Section 20.7.1 ”Burst Flash Controller Mode Register” on page 227. 2. Field BFCC = 2 in Register BFC_MR, see Section 20.7.1 ”Burst Flash Controller Mode Register” on page 227. 3. Field BFCC = 3 in Register BFC_MR, see Section 20.7.1 ”Burst Flash Controller Mode Register” on page 227. Table 38-7. Symbol BFC1 BFC Signals in Asynchronous Mode Parameter BFCK Rising to A1-A25 Valid (1) Conditions CADD = 0 pF CADD derating BFCK Rising to A1-A25 Change (1) CADD = 0 pF CADD derating BFCK Falling to BFAVD Active (1) CBFAVD = 0 pF CBFAVD derating BFCK Falling to BFAVD Inactive (1) CBFAVD = 0 pF CBFAVD derating BFAVD Minimum Pulse Width (1) CBFAVD = 0 pF CBFAVD derating BFCK Rising to BFOE Active CBFOE = 0 pF CBFOE derating BFCK Rising to BFOE Inactive CBFOE = 0 pF CBFOE derating tCLBFCK - 1.0 0.028 tCLBFCK - 1.1 0.028 tCLBFCK - 1.8 0.028 tCPBFCK + 1.0 0.001 - 0.4 0.028 - 1.1 0.028 0.1 0.044 0.7 0.044 tCLBFCK - 0.3 0.044 tCLBFCK + 0.2 0.044 Min Max tCLBFCK - 0.2 0.045 Units ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF BFC2 BFC3 BFC4 BFC5 BFC6 BFC7 644 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Table 38-7. Symbol BFC Signals in Asynchronous Mode (Continued) Parameter BFOE Minimum Pulse Width (1) (5) Conditions CBFOE = 0 pF CBFOE derating Min (a x tCPBFCK) + 0.9 (2)) 0.001 - 0.1 1.0 Max Units ns ns/pF ns ns ns ns/pF ns ns/pF BFC8 BFC9 BFC10 BFC11 D0-D15 in Setup before BFCK Rising Edge D0-D15 in Hold after BFCK Rising Edge Data Setup before BFOE High (5) (6) CBFOE = 0 pF CBFOE derating - 0.9 - 0.044 2.0 0.028 - 0.6 0.028 - 1.3 0.028 - 0.05 0.044 0.5 0.044 tCLBFCK - 0.2 0.044 tCLBFCK - 0.8 0.028 tCLBFCK + 0.5 -0.044 tCHBFCK + 0.7 0.028 tCLBFCK - 0.5 - 0.028 0.044 tCHBFCK + 0.3 0.028 - 0.044 ((a + 1) x tCPBFCK) (2) (o x tCPBFCK) (3) BFC12 Data Hold after BFOE High (6)) CBFOE = 0 pF CBFOE derating BFC13 BFCK Rising to BFWE Active CBFWE = 0 pF CBFWE derating ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns/pF ns ns/pF ns/pF BFC14 BFCK Rising to BFWE Inactive CBFWE = 0 pF CBFWE derating BFC15 BFCK Rising to AD0-AD15 Valid (1) (4) CDATA = 0 pF CDATA derating BFC16 BFCK Rising to AD0-AD15 Not Valid (1) (4) CDATA = 0 pF CDATA derating BFC17 Data Out Valid before BFCK Rising (1) (5) CDATA = 0 pF CDATA derating BFC18 Data Out Valid after BFCK Rising (1) (6) CDATA = 0 pF CDATA derating C = 0 pF BFC19 Data Out Valid before BFWE High (1) (5) CDATA derating CBFWE derating C = 0 pF BFC20 Data Out Valid after BFWE High (1) (6) CDATA derating CBFWE derating BFC21 BFC22 Notes: 1. 2. 3. 4. 5. 6. Number of Address Valid Latency Cycles (1) Number of Output Enable Latency Cycles (1) ((a + 1) x tCPBFCK) (2) (o x tCPBFCK) (3) ns ns The derating factor is not to be applied to tCPBFCK. a = Number of Address Valid Latency Cycles defined in the BFC_MR AVL field. o = Number of Output Enable Latency Cycles defined in the BFC_MR OEL field. Applicable only with multiplexed Address and Data Buses. Only one of these two timings needs to be met. Only one of these two timings needs to be met. 645 1768G–ATARM–29-Sep-06 Note: 1. Figure 38-7. BFC Signals Relative to BFCK in Asynchronous Mode 646 BFC1 BFC3 BFC4 BFC3 BFC4 BFC5 BFC6 BFC7 BFC5 BFC8 BFC9 BFC11 BFC10 BFC12 BFC21 BFC22 BFC21 BFC13 BFC14 BFC16 BFC15 BFC16 BFC17 BFC19 BFC18 BFC20 AT91RM9200 BFCK internal signal BFCS(1) BFC1 A1 - A25 BFAVD BFOE BFCS is asserted as soon as the BFCOM field in BFC_MR is different from 0. D0 - D15 Read BFWE BFC15 D0 - D15 to Write 1768G–ATARM–29-Sep-06 AT91RM9200 Table 38-8. Symbol BFC1 BFC Signals in Burst Mode Parameter BFCK Rising to A1-A25 Valid (1) Conditions CADD = 0 pF CADD derating BFCK Rising to A1-A25 Change (1) CADD = 0 pF CADD derating BFCK Falling to BFAVD Active (1) CBFAVD = 0 pF CBFAVD derating BFCK Falling to BFAVD Inactive (1) CBFAVD = 0 pF CBFAVD derating BFAVD Minimum Pulse Width (1) CBFAVD = 0 pF CBFAVD derating BFCK Rising to BFOE Active CBFOE = 0 pF CBFOE derating BFCK Rising to BFOE Inactive D0-D15 in Setup before BFCK Rising Edge D0-D15 in Hold after BFCK Rising Edge BFCK Rising to AD0-AD15 Valid (1) (4) CDATA = 0 pF CDATA derating BFCK Rising to AD0-AD15 Not Valid (1) (4) Number of Address Valid Latency Cycles (1) Number of Output Enable Latency Cycles (1) BFCK Falling to BFBAA Active (1) CBFBAA = 0 pF CBFBAA derating BFCK Falling to BFBAA Inactive (1) BFRDY Change Hold after BFCK Rising Edge BFRDY Change Setup before BFCK Rising Edge CBFBAA = 0 pF CBFBAA derating CDATA = 0 pF CDATA derating tCLBFCK - 0.8 0.028 ((a + 1) x tCPBFCK) (2) (o x tCPBFCK) (3) Min Max tCLBFCK - 0.2 0.045 Units ns ns/pF ns ns/pF BFC2 tCLBFCK - 1.0 0.028 tCLBFCK - 1.1 0.028 tCLBFCK - 1.8 0.028 tCPBFCK + 1.0 0.001 - 0.4 0.028 - 1.1 0.028 - 0.1 1.0 tCLBFCK - 0.2 0.044 0.1 0.044 0.7 0.044 tCLBFCK - 0.3 0.044 tCLBFCK + 0.2 0.044 ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns/pF ns ns ns ns/pF ns ns/pF BFC3 BFC4 BFC5 BFC6 BFC7 BFC9 BFC10 BFC15 CBFOE = 0 pF CBFOE derating BFC16 BFC21 BFC22 ((a + 1) x tCPBFCK) (2) (o x tCPBFCK) (3) ns ns ns ns/pF ns ns/pF ns ns BFC23 tCLBFCK - 1.0 0.028 tCLBFCK - 1.7 0.028 0.1 0.3 tCLBFCK - 0.1 0.044 tCLBFCK + 0.1 0.044 BFC24 BFC25 BFC26 Notes: 1. 2. 3. 4. The derating factor is not to be applied to tCPBFCK. a = Number of Address Valid Latency Cycles defined in the BFC_MR AVL field. o = Number of Output Enable Latency Cycles defined in the BFC_MR OEL field. Applicable only with multiplexed Address and Data Buses. 647 1768G–ATARM–29-Sep-06 Note: 1. Figure 38-8. BFC Signals Relative to BFCK in Burst Mode BFC10 BFC10 BFC10 BFC10 BFC10 BFC10 BFC10 BFC10 BFC10 D0 - D15 Read D0 - D15 to Write if multiplexed bus only BFC15 BFC21 BFC16 BFC22 BFC10 BFC9 BFC9 BFC9 BFC9 BFC9 BFC9 BFC9 BFC9 BFC9 BFC9 BFC9 648 AT91RM9200 1768G–ATARM–29-Sep-06 BFCS is asserted as soon as the BFCOM field in BFC_MR is different from 0. BFCK if signal controlled address advance BFC23 BFC24 BFC23 BFC24 BFBAA if signal controlled address advance BFCK if clock controlled address advance BFCS(1) BFC1 A1 - A25 BFC3 BFC4 BFAVD BFC5 BFC25 BFC26 BFC25 BFC26 BFRDY BFC6 BFC7 BFC6 BFC7 BFOE AT91RM9200 38.3 38.3.1 JTAG/ICE Timings ICE Interface Signals Table 38-9 shows timings relative to operating condition limits defined in the section Section 38.1.1 ”Conditions and Timings Computation” on page 631 Table 38-9. Symbol ICE0 ICE1 ICE2 ICE3 ICE4 ICE5 ICE6 ICE7 ICE8 ICE Interface Timing Specifications Parameter NTRST Minimum Pulse Width NTRST High Recovery to TCK High NTRST High Removal from TCK High TCK Low Half-period TCK High Half-period TCK Period TDI, TMS, Setup before TCK High TDI, TMS, Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid CTDO = 0 pF CTDO derating Conditions Min 20.00 0.86 0.90 8.00 8.00 20.00 -0.13 0.10 4.17 0 6.49 0.028 Max Units ns ns ns ns ns ns ns ns ns ns/pF ns ns/pF ICE9 Figure 38-9. ICE Interface Signals ICE0 NTRST ICE1 ICE5 TCK ICE3 ICE4 ICE2 TMS/TDI ICE6 ICE7 TDO ICE8 ICE9 649 1768G–ATARM–29-Sep-06 38.3.2 JTAG Interface Signals Table 38-10 shows timings relative to operating condition limits defined in the section 38.1.1 ”Conditions and Timings Computation” on page 631. Table 38-10. JTAG Interface Timing Specifications Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Parameter NTRST Minimum Pulse Width NTRST High Recovery to TCK High NTRST High Recovery to TCK Low NTRST High Removal from TCK High NTRST High Removal from TCK Low TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time COUT = 0 pF COUT derating TCK to Device Outputs Valid COUT = 0 pF COUT derating CTDO = 0 pF CTDO derating -1.23 3.81 7.15 0 7.22 0.028 Conditions Min 20.00 -0.16 -0.16 -0.07 -0.07 8.00 8.00 20.00 0.01 3.21 2.38 0 4.66 0.028 Max Units ns ns ns ns ns ns ns ns ns ns ns ns/pF ns ns/pF ns ns ns ns/pF ns ns/pF JTAG11 JTAG12 JTAG13 JTAG14 JTAG15 650 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 38-10. JTAG Interface Signals JTAG0 NTRST JTAG1 JTAG5 TCK JTAG3 JTAG4 JTAG2 TMS/TDI JTAG6 JTAG7 TDO JTAG8 JTAG9 Device Inputs JTAG10 JTAG11 Device Outputs JTAG12 JTAG13 651 1768G–ATARM–29-Sep-06 38.4 38.4.1 ETM Timings Timings Data Table 38-11 shows timings relative to operating condition limits defined in the section 38.1.1 ”Conditions and Timings Computation” on page 631. Table 38-11. ETM Timing Characteristics Symbol 1/(tCPTCLK) tCPTCLK tCHTCLK tCLTCLK ETM0 ETM1 ETM2 ETM3 Parameter Trace Clock Frequency Trace Clock Period TCLK High Half-period TCLK Low Half-period Data Signals Out Valid before TCLK Rising Edge Data Signals Out Valid after TCLK Rising Edge Data Signals Out Valid before TCLK Falling Edge Data Signals Out Valid after TCLK Falling Edge C = 0 pF CDATA derating C = 0 pF CDATA derating 11.56 tCPTCLK/2 + 0.02 tCPTCLK/2 - 0.02 tCLTCLK - 1.06 tCHTCLK - 0.49 0.044 tCHTCLK - 1.03 tCLTCLK - 0.51 0.044 Conditions Min Typ 1/(2 x tCPPCK) 2 x tCPPCK Max 86.54 Units MHz ns ns ns ns ns ns/pF ns ns ns/pF Figure 38-11. ETM Signals tCHTCLK TCLK tCLTCLK tCPTCLK TSYNC TPS[2:0] TPK[15:0] ETM0 ETM1 ETM2 ETM3 1768G–ATARM–29-Sep-06 38.4.2 Design Considerations When designing a PCB, it is important to keep the differences between trace length of ETM signals as small as possible to minimize skew between them. In addition, crosstalk on the trace port must be kept to a minimum as it can cause erroneous trace results. Stubs on these traces can cause unpredictable responses, thus it is recommended to avoid stubs on the trace lines. The TCLK line should be series-terminated as close as possible to the microcontroller pins. The maximum capacitance presented by the trace connector, cabling and interfacing logic must be less than 15 pF. 652 AT91RM9200 AT91RM9200 39. AT91RM9200 Mechanical Characteristics 39.1 39.1.1 Thermal and Reliability Considerations Thermal Data Table 39-1 summarizes the thermal resistance data depending on the package. Table 39-1. Symbol θJA θJC Thermal Resistance Data Parameter Junction-to-ambient thermal resistance Condition Still Air LFBGA256 PQFP208 Junction-to-case thermal resistance LFBGA256 7.7 35.6 °C/W 15.7 Package PQFP208 Typ 33.9 Unit 39.1.2 Reliability Data The number of gates and the device die size are provided Table 39-2 so that the user can calculate reliability data for another standard and/or in another environmental model. Table 39-2. Parameter Number of Logic Gates Number of Memory Gates Device Die Size Reliability Data Data 4461 2458 33.9 Unit K gates K gates mm2 653 1768G–ATARM–29-Sep-06 39.1.3 Junction Temperature The average chip-junction temperature, TJ, in °C can be obtained from the following: 1. T J = T A + ( P D × θ JA ) 2. T J = T A + ( P D × ( θ HEATSINK + θ JC ) ) where: • θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 39-1 on page 653. • θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 39-1 on page 653. • θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet. • PD = device power consumption (W) estimated from data provided in the section 37.4 ”Power Consumption” on page 626. • TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. 654 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 39.2 Package Drawings Figure 39-1. 208-pin PQFP Package Drawing C C1 Table 39-3. Symbol c c1 L L1 R2 R1 S A A1 A2 b 208-pin PQFP Package Dimensions (in mm) Min 0.11 0.11 0.65 0.15 0.88 1.60 REF 0.13 0.13 0.4 4.10 0.25 3.20 0.17 3.40 0.50 3.60 0.27 D D1 E E1 e 0.3 Nom Max 0.23 0.19 1.03 aaa ccc BSC 31.20 28.00 31.20 28.00 0.50 Symbol b1 ddd Min 0.17 0.10 Tolerances of Form and Position 0.25 0.1 Nom 0.20 Max 0.23 655 1768G–ATARM–29-Sep-06 Table 39-4. Device and 208-pin Package Maximum Weight Weight 5427 Unit mg Package Type Standard and Green Table 39-5. 208-pin PQFP Moisture Sensitivity Level 3 Package Type Standard and Green Table 39-6. Package Reference Standard JEDEC Drawing MS-022 JEDEC Drawing MS-212 Package Type Standard Green JESD97 Classification: e2 The Green package respects the recommendations of the NEMI User Group. 656 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 Figure 39-2. 256-ball BGA Package Drawing Table 39-7. Device and 256-ball BGA Package Maximum Weight Weight 4954 mg 7455 Unit Package Type Standard RoHS-compliant Table 39-8. 256-ball BGA Package Characteristics Moisture Sensitivity Level 3 Package Type Standard and RoHS-compliant Table 39-9. Package Reference Standard JEDEC Drawing MO-205E JEDEC Drawing MO-205E Package Type Standard RoHS-compliant JESD97 Classification: e1 The RoHS-compliant package respects the recommendations of the NEMI User Group. 657 1768G–ATARM–29-Sep-06 39.3 39.3.1 Soldering Profiles Standard Packages Table 39-10 gives the recommended soldering profile from J-STD-20. Table 39-10. Soldering Profile Convection or IR/Convection Average Ramp-up Rate (183° C to Peak) Preheat Temperature 125° C ±25° C Temperature Maintained Above 183° C Time within 5° C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° C to Peak Temperature 3° C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0° C or 235 +5/-0° C 6° C/sec. 6 min. max 60 sec. 215 to 219° C or 235 +5/-0° C 10° C/sec. VPR 10° C/sec. Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235° C, not 220° C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 39-11. Table 39-11. Recommended Package Reflow Conditions (LQFP and BGA)(1) (2)(3) Parameter Convection VPR IR/Convection Notes: Temperature 220 +5/-0° C 215 to 219° C 220 +5/-0° C 1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220° C (unless 235° C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. A maximum of three reflow passes is allowed per component. 658 AT91RM9200 1768G–ATARM–29-Sep-06 AT91RM9200 39.3.2 Green and RoHS-compliant Packages Table 39-12 gives the recommended soldering profile from J-STD-20. Table 39-12. Soldering Profile Profile Feature Average Ramp-up Rate (183° C to Peak) Preheat Temperature 175° C ±25° C Temperature Maintained Above 217° C Time within 5° C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° C to Peak Temperature Notes: PQFP208 Green Package (1)(2) 3° C/sec. max. 180 sec. max 60 sec. to 150 sec. 20sec. to 40 sec. 260° C 6° C/sec. max 8 min. max BGA256 RoHS Compliant Package (3) 3° C/sec. max 180 sec. max 60 sec. to 150 sec. 20 sec. to 40 sec. 260° C 6° C/sec. max 8 min. max 1. The package is certified to be backward compatible with Pb/Sn soldering profile. 2. Atmel Green Definition is: RoHS and