AT91RM9200

Features • Incorporates the ARM920T™ ARM® Thumb® Processor – 200 MIPS at 180 MHz, Memory Management Unit – 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer – In-circuit Emulator including Debug Communication Channel – Mid-level Implementation Embedded Trace Macrocell (256-ball BGA Package Only) Low Power: On VDDCORE 24.4 mA in Normal Mode, 520 µA in Standby Mode Additional Embedded Memories – 16K Bytes of SRAM and 128K Bytes of ROM External Bus Interface (EBI) – Supports SDRAM, Static Memory, Burst Flash, Glueless Connection to CompactFlash® and NAND Flash/SmartMedia™ System Peripherals for Enhanced Performance: – Enhanced Clock Generator and Power Management Controller – Two On-chip Oscillators with Two PLLs – Very Slow Clock Operating Mode and Software Power Optimization Capabilities – Four Programmable External Clock Signals – System Timer Including Periodic Interrupt, Watchdog and Second Counter – Real-time Clock with Alarm Interrupt – Debug Unit, Two-wire UART and Support for Debug Communication Channel – Advanced Interrupt Controller with 8-level Priority, Individually Maskable Vectored Interrupt Sources, Spurious Interrupt Protected – Seven External Interrupt Sources and One Fast Interrupt Source – Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, Input Change Interrupt and Open-drain Capability on Each Line – 20-channel Peripheral DMA Controller (PDC) Ethernet MAC 10/100 Base-T – Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – Integrated 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit USB 2.0 Full Speed (12 Mbits per second) Host Double Port – Dual On-chip Transceivers (Single Port Only on 208-lead PQFP Package) – Integrated FIFOs and Dedicated DMA Channels USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs Multimedia Card Interface (MCI) – Automatic Protocol Control and Fast Automatic Data Transfers – MMC and SD Memory Card-compliant, Supports Up to Two SD Memory Cards Three Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I2S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) – Support for ISO7816 T0/T1 Smart Card – Hardware Handshaking – RS485 Support, IrDA Up To 115 Kbps – Full Modem Control Lines on USART1 Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, 4 External Peripheral Chip Selects Two 3-channel, 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two-wire Interface (TWI) – Master Mode Support, All 2-wire Atmel EEPROMs Supported IEEE 1149.1 JTAG Boundary Scan on All Digital Pins Power Supplies – 1.65V to 1.95V for VDDCORE, VDDOSC and VDDPLL – 3.0V to 3.6V for VDDIOP (Peripheral I/Os) and for VDDIOM (Memory I/Os)Available in a 208-lead PQFP or 256-ball BGA Package • • • • ARM920T™based Microcontroller AT91RM9200 Summary • • • • • • • • • • • • Rev. 1768IS-ATARM–30-Sep-05 1. Description The AT91RM9200 is a complete system-on-chip built around the ARM920T ARM Thumb processor. It incorporates a rich set of system and application peripherals and standard interfaces in order to provide a single-chip solution for a wide range of compute-intensive applications that require maximum functionality at minimum power consumption at lowest cost. The AT91RM9200 incorporates a high-speed on-chip SRAM workspace, and a low-latency External Bus Interface (EBI) for seamless connection to whatever configuration of off-chip memories and memory-mapped peripherals is required by the application. The EBI incorporates controllers for synchronous DRAM (SDRAM), Burst Flash and Static memories and features specific circuitry facilitating the interface for NAND Flash/SmartMedia and Compact Flash. The Advanced Interrupt Controller (AIC) enhances the interrupt handling performance of the ARM920T processor by providing multiple vectored, prioritized interrupt sources and reducing the time taken to transfer to an interrupt handler. The Peripheral DMA Controller (PDC) provides DMA channels for all the serial peripherals, enabling them to transfer data to or from on- and off-chip memories without processor intervention. This reduces the processor overhead when dealing with transfers of continuous data streams.The AT91RM9200 benefits from a new generation of PDC which includes dual pointers that simplify significantly buffer chaining. The set of Parallel I/O (PIO) controllers multiplex the peripheral input/output lines with generalpurpose data I/Os for maximum flexibility in device configuration. An input change interrupt, open drain capability and programmable pull-up resistor is included on each line. The Power Management Controller (PMC) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals under software control. It uses an enhanced clock generator to provide a selection of clock signals including a slow clock (32 kHz) to optimize power consumption and performance at all times. The AT91RM9200 integrates a wide range of standard interfaces including USB 2.0 Full Speed Host and Device and Ethernet 10/100 Base-T Media Access Controller (MAC), which provides connection to a extensive range of external peripheral devices and a widely used networking layer. In addition, it provides an extensive set of peripherals that operate in accordance with several industry standards, such as those used in audio, telecom, Flash Card, infrared and Smart Card applications. To complete the offer, the AT91RM9200 benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU) and an embedded real time trace. This enables the development and debug of all applications, especially those with real-time constraints. 2 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 2. Block Diagram Bold arrows ( Figure 2-1. AT91RM9200 Block Diagram NRST JTAGSEL TDI TDO TMS TCK NTRST Reset and Test ICE JTAG Scan Instruction Cache 16K bytes Data Cache 16K bytes ) indicate master-to-slave dependency. TST0-TST1 ARM920T Core ETM MMU TSYNC PIO TCLK TPS0 - TPS2 TPK0 - TPK15 BMS PIO FIQ IRQ0-IRQ6 PCK0-PCK3 PLLRCB PLLRCA XIN XOUT AIC Fast SRAM 16K bytes Address Decoder Abort Status EBI CompactFlash NAND Flash SmartMedia PLLB PLLA PMC OSC Peripheral Bridge System Timer Peripheral Data Controller Fast ROM 128K bytes Misalignment Detector Bus Arbiter SDRAM Controller XIN32 XOUT32 DRXD PIO DTXD OSC RTC Memory Controller DBGU PDC Static Memory Controller PIOA/PIOB/PIOC/PIOD Controller DMA FIFO USB Host FIFO Transceiver PIO Burst Flash Controller D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A22 A16/BA0 A17/BA1 NCS0/BFCS NCS1/SDCS NCS2 NCS3/SMCS NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 BFRDY/SMOE BFCK BFAVD BFBAA/SMWE BFOE BFWE A23-A24 A25/CFRNW NWAIT NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NCS7 D16-D31 HDMA HDPA HDMB HDPB DDM DDP Transceiver USB Device DMA FIFO ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO EF100 TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TF2 TK2 TD2 RD2 RK2 RF2 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TCLK3 TCLK4 TCLK5 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 MCCK MCCDA MCDA0-MCDA3 MCCDB MCDB0-MCDB3 RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DSR1 DTR1 DCD1 RI1 RXD2 TXD2 SCK2 RTS2 CTS2 RXD3 TXD3 SCK3 RTS3 CTS3 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK TWD MCI PDC Ethernet MAC 10/100 APB USART0 PDC PDC USART1 PIO PIO PIO SSC1 PDC PDC SSC0 USART2 PDC PDC SSC2 USART3 PDC Timer Counter TC0 TC1 TC2 SPI Timer Counter PDC TC3 TWI TC4 TC5 TWCK 3 1768IS–ATARM–30-Sep-05 3. Key Features This section presents the key features of each block. 3.1 ARM920T Processor • ARM9TDMI™-based on ARM® Architecture v4T • Two instruction sets – ARM® High-performance 32-bit Instruction Set – Thumb® High Code Density 16-bit Instruction Set • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 16-Kbyte Data Cache, 16-Kbyte Instruction Cache – Virtually-addressed 64-way Associative Cache – 8 words per line – Write-though and write-back operation – Pseudo-random or Round-robin replacement – Low-power CAM RAM implementation • Write Buffer – 16-word Data Buffer – 4-address Address Buffer – Software Control Drain • Standard ARMv4 Memory Management Unit (MMU) – Access permission for sections – Access permission for large pages and small pages can be specified separately for each quarter of the pages – 16 embedded domains – 64 Entry Instruction TLB and 64 Entry Data TLB • 8-, 16-, 32-bit Data Bus for Instructions and Data 3.2 Debug and Test • Integrated Embedded In-Circuit-Emulator • Debug Unit – Two-pin UART – Debug Communication Channel – Chip ID Register • Embedded Trace Macrocell: ETM9 Rev2a – Medium Level Implementation – Half-rate Clock Mode 4 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary – Four Pairs of Address Comparators – Two Data Comparators – Eight Memory Map Decoder Inputs – Two Counters – One Sequencer – One 18-byte FIFO • IEEE1149.1 JTAG Boundary Scan on all Digital Pins 3.3 Boot Program • Default Boot Program stored in ROM-based products • Downloads and runs an application from external storage media into internal SRAM • Downloaded code size depends on embedded SRAM size • Automatic detection of valid application • Bootloader supporting a wide range of non-volatile memories – SPI DataFlash® connected on SPI NPCS0 – Two-wire EEPROM – 8-bit parallel memories on NCS0 • Boot Uploader in case no valid program is detected in external NVM and supporting several communication media • Serial communication on a DBGU (XModem protocol) • USB Device Port (DFU Protocol) 3.4 Embedded Software Services • Compliant with ATPCS • Compliant with AINSI/ISO Standard C • Compiled in ARM/Thumb Interworking • ROM Entry Service • Tempo, Xmodem and DataFlash services • CRC and Sine tables 3.5 Reset Controller • Two reset input lines (NRST and NTRST) providing, respectively: • Initialization of the User Interface registers (defined in the user interface of each peripheral) and: – Sample the signals needed at bootup – Compel the processor to fetch the next instruction at address zero. • Initialization of the embedded ICE TAP controller. 3.6 Memory Controller • Programmable Bus Arbiter handling four Masters – Internal Bus is shared by ARM920T, PDC, USB Host Port and Ethernet MAC Masters 5 1768IS–ATARM–30-Sep-05 – Each Master can be assigned a priority between 0 and 7 • Address Decoder provides selection for – Eight external 256-Mbyte memory areas – Four internal 1-Mbyte memory areas – One 256-Mbyte embedded peripheral area • Boot Mode Select Option – Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset • Abort Status Registers – Source, Type and all parameters of the access leading to an abort are saved • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap command – Provides remapping of an internal SRAM in place of the boot NVM 3.7 External Bus Interface • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – Burst Flash Controller • Additional logic for NAND Flash/SmartMedia and CompactFlash support • Optimized External Bus: – 16- or 32-bit Data Bus – Up to 26-bit Address Bus, up to 64-Mbytes addressable – Up to 8 Chip Selects, each reserved to one of the eight Memory Areas – Optimized pin multiplexing to reduce latencies on External Memories • Configurable Chip Select Assignment: – Burst Flash Controller or Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS3, Optional NAND Flash/SmartMedia Support – Static Memory Controller on NCS4 - NCS6, Optional CompactFlash Support – Static Memory Controller on NCS7 3.8 Static Memory Controller • External memory mapping, 512-Mbyte address space • Up to 8 Chip Select Lines • 8- or 16-bit Data Bus • Remap of Boot Memory • Multiple Access Modes supported – Byte Write or Byte Select Lines 6 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary – Two different Read Protocols for each Memory Bank • Multiple device adaptability – Compliant with LCD Module – Programmable Setup Time Read/Write – Programmable Hold Time Read/Write • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time 3.9 SDRAM Controller • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh and Low-power Modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • Latency is set to two clocks (CAS Latency of 1, 3 Not Supported) • Auto Precharge Command not used 3.10 Burst Flash Controller • Multiple Access Modes supported – Asynchronous or Burst Mode Byte, Half-word or Word Read Accesses – Asynchronous Mode Half-word Write Accesses • Adaptability to different device speed grades – Programmable Burst Flash Clock Rate – Programmable Data Access Time – Programmable Latency after Output Enable • Adaptability to different device access protocols and bus interfaces – Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled Address Advance – Multiplexed or separate address and data buses 7 1768IS–ATARM–30-Sep-05 – Continuous Burst and Page Mode Accesses supported 3.11 Peripheral DMA Controller (PDC) • Generates transfers to/from peripherals such as DBGU, USART, SSC, SPI and MCI • Twenty channels • One Master Clock cycle needed for a transfer from memory to peripheral • Two Master Clock cycles needed for a transfer from peripheral to memory 3.12 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of an ARM® Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU…) – Source 2 to Source 31 control thirty embedded peripheral interrupts or external interrupts – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive External Sources • 8-level Priority Controller – Drives the Normal Interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode – Easy debugging by preventing automatic operations • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt 3.13 Power Management Controller • Optimizes the power consumption of the whole system • Embeds and controls: – One Main Oscillator and One Slow Clock Oscillator (32.768Hz) – Two Phase Locked Loops (PLLs) and Dividers – Clock Prescalers • Provides: – the Processor Clock PCK – the Master Clock MCK – the USB Clocks, UHPCK and UDPCK, respectively for the USB Host Port and the USB Device Port 8 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary – Programmable automatic PLL switch-off in USB Device suspend conditions – up to thirty peripheral clocks – four programmable clock outputs PCK0 to PCK3 • Four operating modes: – Normal Mode, Idle Mode, Slow Clock Mode, Standby Mode 3.14 System Timer • One Period Interval Timer, 16-bit programmable counter • One Watchdog Timer, 16-bit programmable counter • One Real-time Timer, 20-bit free-running counter • Interrupt Generation on event 3.15 Real Time Clock • Low power consumption • Full asynchronous design • Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 3.16 Debug Unit • System peripheral to facilitate debug of Atmel’s ARM®-based systems • Composed of the following functions – Two-pin UART – Debug Communication Channel (DCC) support – Chip ID Registers • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Interrupt generation – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of COMMRX and COMMTX signals from the ARM Processor – Interrupt generation • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of peripherals 9 1768IS–ATARM–30-Sep-05 3.17 PIO Controller • Up to 32 programmable I/O Lines • Fully programmable through Set/Clear Registers • Multiplexing of two peripheral functions per I/O Line • For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 3.18 USB Host Port • Compliance with Open HCI Rev 1.0 specification • Compliance with USB V2.0 Full-speed and Low-speed Specification • Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices • Root hub integrated with two downstream USB ports • Two embedded USB transceivers • Supports power management • Operates as a master on the Memory Controller 3.19 USB Device Port • USB V2.0 full-speed compliant, 12 Mbits per second • Embedded USB V2.0 full-speed transceiver • Embedded dual-port RAM for endpoints • Suspend/Resume logic • Ping-pong mode (two memory banks) for isochronous and bulk endpoints • Six general-purpose endpoints – Endpoint 0, Endpoint 3: 8 bytes, no ping-pong mode – Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode – Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode 3.20 Ethernet MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operation • MII or RMII interface to the physical layer • Register interface to address, status and control registers • DMA interface, operating as a master on the Memory Controller • Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs 10 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Supports promiscuous mode where all valid frames are copied to memory • Supports physical layer management through MDIO interface 3.21 Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Connection to PDC channel optimizes data transfers – One channel for the receiver, one channel for the transmitter – Next buffer support 3.22 Two-wire Interface • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential Read/Write operations 3.23 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Optional hardware handshaking RTS-CTS – Optional modem signal management DTR-DSR-DCD-RI – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection 11 1768IS–ATARM–30-Sep-05 • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo • Connection of two Peripheral DMA Controller (PDC) channels – Offers buffer transfer without processor intervention 3.24 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider • Interfaced with two PDC channels to reduce processor overhead • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 3.25 Timer Counter • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Internal interrupt signal • Two global registers that act on all three TC Channels 3.26 MultiMedia Card Interface • Compatibility with MultiMedia Card Specification Version 2.2 • Compatibility with SD Memory Card Specification Version 1.0 • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used 12 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary • Supports two slots – One slot for one MultiMedia Card bus (up to 30 cards) or one SD Memory Card • Support for stream, block and multi-block data read and write • Connection to a Peripheral DMA Controller (PDC) channel – Minimizes processor intervention for large buffer transfers 13 1768IS–ATARM–30-Sep-05 4. AT91RM9200 Product Properties 4.1 Power Supplies The AT91RM9200 has five types of power supply pins: • VDDCORE pins. They power the core, including processor, memories and peripherals; voltage ranges from 1.65V to 1.95V, 1.8V nominal. • VDDIOM pins. They power the External Bus Interface I/O lines; voltage ranges from 3.0V to 3.6V, 3V or 3.3V nominal. • VDDIOP pins. They power the Peripheral I/O lines and the USB transceivers; voltage ranges from 3.0V to 3.6V, 3V or 3.3V nominal. • VDDPLL pins. They power the PLL cells; voltage ranges from 1.65V to 1.95V, 1.8V nominal. • VDDOSC pin. They power both oscillators; voltage ranges from 1.65V to 1.95V, 1.8V nominal. The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 15 and Table 4-2 on page 17. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins are common to all power supplies, except VDDPLL and VDDOSC pins. For these pins, GNDPLL and GNDOSC are provided, respectively. 4.2 Pinout The AT91RM9200 is available in two packages: • 208-lead PQFP, 31.2 x 31.2 mm, 0.5 mm lead pitch • 256-ball BGA, 15 x 15 mm, 0.8 mm ball pitch The product features of the 256-ball BGA package are extended compared to the 208-lead PQFP package. The features that are available only with the 256-ball BGA package are: • Parallel I/O Controller D • ETM port with outputs multiplexed on the PIO Controller D • a second USB Host transceiver, opening the Hub capabilities of the embedded USB Host. 14 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 4.2.1 Table 4-1. Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 208-lead PQFP Package Pinout AT91RM9200 Pinout for 208-lead PQFP Package Signal Name PC24 PC25 PC26 PC27 PC28 PC29 VDDIOM GND PC30 PC31 PC10 PC11 PC12 PC13 PC14 PC15 PC0 PC1 VDDCORE GND PC2 PC3 PC4 PC5 PC6 VDDIOM GND VDDPLL PLLRCA GNDPLL XOUT XIN VDDOSC GNDOSC XOUT32 XIN32 Pin Number 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Signal Name VDDPLL PLLRCB GNDPLL VDDIOP GND PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 VDDIOP GND PA14 PA15 PA16 PA17 VDDCORE GND PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 Pin Number 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Signal Name PA27 PA28 VDDIOP GND PA29 PA30 PA31/BMS PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 VDDIOP GND PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 JTAGSEL TDI TDO TCK Pin Number 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Signal Name TMS NTRST VDDIOP GND TST0 TST1 NRST VDDCORE GND PB23 PB24 PB25 PB26 PB27 PB28 PB29 HDMA HDPA DDM DDP VDDIOP GND VDDIOM GND A0/NBS0 A1/NBS2/NWR2 A2 A3 A4 A5 A6 A7 A8 A9 A10 SDA10 15 1768IS–ATARM–30-Sep-05 Table 4-1. Pin Number 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 AT91RM9200 Pinout for 208-lead PQFP Package (Continued) Signal Name A11 VDDIOM GND A12 A13 A14 A15 VDDCORE GND A16/BA0 A17/BA1 A18 A19 A20 A21 A22 Pin Number 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Signal Name PC7 PC8 PC9 VDDIOM GND NCS0/BFCS NCS1/SDCS NCS2 NCS3/SMCS NRD/NOE/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS Pin Number 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 Signal Name CAS SDWE D0 D1 D2 D3 VDDIOM GND D4 D5 D6 VDDCORE GND D7 D8 D9 Pin Number 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Signal Name D10 D11 D12 D13 D14 D15 VDDIOM GND PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 Note: 1. Shaded cells define the pins powered by VDDIOM. 4.2.2 Mechanical Overview of the 208-lead PQFP Package Figure 4-1 shows the orientation of the 208-lead PQFP package. A detailed mechanical description is given in the section Mechanical Characteristics. Figure 4-1. 208-lead PQFP Pinout (Top View) 156 157 105 104 208 1 52 53 16 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 4.2.3 Table 4-2. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 256-ball BGA Package Pinout AT91RM9200 Pinout for 256-ball BGA Package Signal Name TDI JTAGSEL PB20 PB17 PD11 PD8 VDDIOP PB9 PB4 PA31/BMS VDDIOP PA23 PA19 GND PA14 VDDIOP PA13 TDO PD13 PB18 PB21 PD12 PD9 GND PB10 PB5 PB0 VDDIOP PA24 PA17 PA15 PA11 PA12 PA7 TMS PD15 Pin C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 Signal Name PD14 PB22 PB19 PD10 PB13 PB12 PB6 PB1 GND PA20 PA18 VDDCORE GND PA8 PD5 TST1 VDDIOP VDDIOP GND VDDIOP PD7 PB14 VDDIOP PB8 PB2 GND PA22 PA21 PA16 PA10 PD6 PD4 NRST NTRST GND TST0 Pin E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 F1 F2 F3 F4 F5 F6 F7 F9 F11 F12 F13 F14 F15 F16 F17 G1 G2 G3 G4 G5 G6 G12 G13 Signal Name TCK GND PB15 GND PB7 PB3 PA29 PA26 PA25 PA9 PA6 PD3 PD0 PD16 GND PB23 PB25 PB24 VDDCORE PB16 PB11 PA30 PA28 PA4 PD2 PD1 PA5 PLLRCB PD19 PD17 GND PB26 PD18 PB27 PA27 PA0 Pin G14 G15 G16 G17 H1 H2 H3 H4 H5 H13 H14 H15 H16 H17 J1 J2 J3 J4 J5 J6 J12 J13 J14 J15 J16 J17 K1 K2 K3 K4 K5 K13 K14 K15 K16 K17 Signal Name PA1 PA2 PA3 XIN32 PD23 PD20 PD22 PD21 VDDIOP VDDPLL VDDIOP GNDPLL GND XOUT32 PD25 PD27 PD24 PD26 PB28 PB29 GND GNDOSC VDDOSC VDDPLL GNDPLL XIN HDPA DDM HDMA VDDIOP DDP PC5 PC4 PC6 VDDIOM XOUT 17 1768IS–ATARM–30-Sep-05 Table 4-2. Pin L1 L2 L3 L4 L5 L6 L12 L13 L14 L15 L16 L17 M1 M2 M3 M4 M5 M6 M7 M9 M11 M12 M13 M14 M15 M16 M17 N1 AT91RM9200 Pinout for 256-ball BGA Package (Continued) Signal Name GND HDPB HDMB A6 GND VDDIOP PC10 PC15 PC2 PC3 VDDCORE PLLRCA VDDIOM GND A3 A1/NBS2/NWR2 A10 A2 GND NCS1/SDCS D4 GND PC13 PC1 PC0 GND PC14 A0/NBS0 Pin N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 Signal Name A5 A9 A4 A14 SDA10 A8 A21 NRD/NOE/CFOE RAS D2 GND PC28 PC31 PC30 PC11 PC12 A7 A13 A12 VDDIOM A11 A22 PC9 NWR0/NWE/CFWE SDCKE D1 D5 D10 Pin P13 P14 P15 P16 P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 Signal Name D15 PC26 PC27 VDDIOM GND GND GND A18 A20 PC8 VDDIOM NCS3/SMCS NWR3/NBS3/ CFIOW D0 VDDIOM D8 D13 PC17 VDDIOM PC24 PC29 VDDIOM A15 VDDCORE A17/BA1 PC7 VDDIOM NCS2 Pin T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name NWR1/NBS1/ CFIOR SDWE GND VDDCORE D9 D12 GND PC19 PC21 PC23 PC25 VDDCORE GND A16/BA0 A19 GND NCS0/BFCS SDCK CAS D3 D6 D7 D11 D14 PC16 PC18 PC20 PC22 Note: 1. Shaded cells define the pins powered by VDDIOM. 4.2.4 Mechanical Overview of the 256-ball BGA Package Figure 4-2 on page 19 shows the orientation of the 256-ball BGA Package. A detailed mechanical description is given in the section Mechanical Characteristics. 18 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary Figure 4-2. 256-ball BGA Pinout (Top View) 4.3 Peripheral Multiplexing on PIO Lines The AT91RM9200 features four PIO controllers: • PIOA and PIOB, multiplexing I/O lines of the peripheral set. • PIOC, multiplexing the data bus bits 16 to 31 and several External Bus Interface control signals. Using PIOC pins increases the number of general-purpose I/O lines available but prevents 32-bit memory access. • PIOD, available in the 256-ball BGA package option only, multiplexing outputs of the peripheral set and the ETM port. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers A, B, C and D. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application. The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral mode. If equal to “I/O”, the PIO line resets in input with the pull-up enabled so that the device is maintained in a static state as soon as the NRST pin is asserted. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is in the “Reset State” column, the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case for pins controlling memories, either address lines or chip selects, and that require the pin to be driven as soon as NRST raises. Note that the pull-up resistor is also enabled in this case. See Table 4-3 on page 20, Table 4-4 on page 21, Table 4-5 on page 22 and Table 4-6 on page 23. 19 1768IS–ATARM–30-Sep-05 4.3.1 Table 4-3. PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A Application Usage Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Comments I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A MISO MOSI SPCK NPCS0 NPCS1 NPCS2 NPCS3 ETXCK/EREFCK ETXEN ETX0 ETX1 ECRS/ECRSDV ERX0 ERX1 ERXER EMDC EMDIO TXD0 RXD0 SCK0 CTS0 RTS0 RXD2 TXD2 SCK2 TWD TWCK MCCK MCCDA MCDA0 DRXD DTXD Peripheral B PCK3 PCK0 IRQ4 IRQ5 PCK1 TXD3 RXD3 PCK2 MCCDB MCDB0 MCDB1 MCDB2 MCDB3 TCLK0 TCLK1 TCLK2 IRQ6 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 IRQ3 PCK1 IRQ2 IRQ1 TCLK3 TCLK4 TCLK5 CTS2 RTS2 20 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 4.3.2 Table 4-4. PIO Controller B Multiplexing Multiplexing on PIO Controller B PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 Peripheral A TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TF2 TK2 TD2 RD2 RK2 RF2 RI1 DTR1 TXD1 RXD1 SCK1 DCD1 CTS1 DSR1 RTS1 PCK0 FIQ IRQ0 EF100 Peripheral B RTS3 CTS3 SCK3 MCDA1 MCDA2 MCDA3 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 ETX2 ETX3 ETXER ERX2 ERX3 ERXDV ECOL ERXCK Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Application Usage Comments 21 1768IS–ATARM–30-Sep-05 4.3.3 PIO Controller C Multiplexing The PIO Controller C has no multiplexing and only peripheral A lines are used. Selecting Peripheral B on the PIO Controller C has no effect. Table 4-5. Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Peripheral A BFCK BFRDY/SMOE BFAVD BFBAA/SMWE BFOE BFWE NWAIT A23 A24 A25/CFRNW NCS4/CFCS NCS5/CFCE1 NCS6/CFCE2 NCS7 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O A23 A24 A25 NCS4 NCS5 NCS6 NCS7 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Application Usage Comments 22 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 4.3.4 PIO Controller D Multiplexing The PIO Controller D multiplexes pure output signals on peripheral A connections, in particular from the EMAC MII interface and the ETM Port on the peripheral B connections. The PIO Controller D is available only in the 256-ball BGA package option of the AT91RM9200. Table 4-6. Multiplexing on PIO Controller D PIO Controller D I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 TD0 TD1 TD2 NPCS1 NPCS2 NPCS3 RTS0 RTS1 RTS2 RTS3 DTR1 Peripheral A ETX0 ETX1 ETX2 ETX3 ETXEN ETXER DTXD PCK0 PCK1 PCK2 PCK3 TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Function Application Usage Comments 23 1768IS–ATARM–30-Sep-05 4.3.5 Pin Name Description Table 4-7 gives details on the pin name classified by peripheral. Table 4-7. Pin Name Pin Description List Function Power Type Active Level Comments VDDIOM VDDIOP VDDPLL VDDCORE VDDOSC GND GNDPLL GNDOSC Memory I/O Lines Power Supply Peripheral I/O Lines Power Supply Oscillator and PLL Power Supply Core Chip Power Supply Oscillator Power Supply Ground PLL Ground Oscillator Ground Power Power Power Power Power Ground Ground Ground 3.0V to 3.6V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V 1.65V to 1.95V Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Crystal Input Main Crystal Output 32KHz Crystal Input 32KHz Crystal Output PLL A Filter PLL B Filter Programmable Clock Output ICE and JTAG TCK TDI TDO TMS NTRST JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal JTAG Selection ETM TSYNC TCLK TPS0 - TPS2 TPK0 - TPK15 Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Trace Packet Port Reset/Test NRST TST0 - TST1 Microcontroller Reset Test Mode Select Input Input Low No on-chip pull-up, Schmitt trigger Must be tied low for normal operation, Schmitt trigger Output Output Output Output Input Input Output Input Input Input Low Schmitt trigger Internal Pull-up, Schmitt trigger Tri-state Internal Pull-up, Schmitt trigger Internal Pull-up, Schmitt trigger Schmitt trigger Input Output Input Output Input Input Output 24 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary Table 4-7. Pin Name Pin Description List (Continued) Function Memory Controller Type Active Level Comments BMS Boot Mode Select Debug Unit Input DRXD DTXD Debug Receive Data Debug Transmit Data AIC Input Output Debug Receive Data Debug Transmit Data IRQ0 - IRQ6 FIQ External Interrupt Inputs Fast Interrupt Input PIO Input Input PA0 - PA31 PB0 - PB29 PC0 - PC31 PD0 - PD27 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D EBI I/O I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset D0 - D31 A0 - A25 Data Bus Address Bus SMC I/O Output Pulled-up input at reset 0 at reset NCS0 - NCS7 NWR0 - NWR3 NOE NRD NUB NLB NWE NWAIT NBS0 - NBS3 Chip Select Lines Write Signal Output Enable Read Signal Upper Byte Select Lower Byte Select Write Enable Wait Signal Byte Mask Signal Output Output Output Output Output Output Output Input Output EBI for CompactFlash Support Low Low Low Low Low Low Low Low Low 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset 1 at reset CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Output Output Output Output Output Output Output Low Low Low Low Low Low 25 1768IS–ATARM–30-Sep-05 Table 4-7. Pin Name Pin Description List (Continued) Function Type EBI for NAND Flash/SmartMedia Support Active Level Comments SMCS SMOE SMWE NAND Flash/SmartMedia Chip Select NAND Flash/SmartMedia Output Enable NAND Flash/SmartMedia Write Enable SDRAM Controller Output Output Output Low Low Low SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Burst Flash Controller Low Low High Low BFCK BFCS BFAVD BFBAA BFOE BFRDY BFWE Burst Flash Clock Burst Flash Chip Select Burst Flash Address Valid Burst Flash Address Advance Burst Flash Output Enable Burst Flash Ready Burst Flash Write Enable Output Output Output Output Output Input Output Multimedia Card Interface Low Low Low Low High Low MCCK MCCDA MCDA0 - MCDA3 MCCDB MCDB0 - MCDB3 Multimedia Card Clock Multimedia Card A Command Multimedia Card A Data Multimedia Card B Command Multimedia Card B Data USART Output I/O I/O I/O I/O SCK0 - SCK3 TXD0 - TXD3 RXD0 - RXD3 RTS0 - RTS3 CTS0 - CTS3 DSR1 DTR1 DCD1 RI1 Serial Clock Transmit Data Receive Data Ready To Send Clear To Send Data Set Ready Data Terminal Ready Data Carrier Detect Ring Indicator I/O Output Input Output Input Input Output Input Input 26 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary Table 4-7. Pin Name Pin Description List (Continued) Function USB Device Port Type Active Level Comments DDM DDP USB Device Port Data USB Device Port Data + USB Host Port Analog Analog HDMA HDPA HDMB HDPB USB Host Port A Data USB Host Port A Data + USB Host Port B Data USB Host Port B Data + Ethernet MAC Analog Analog Analog Analog EREFCK ETXCK ERXCK ETXEN ETX0 - ETX3 ETXER ERXDV ECRSDV ERX0 - ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Reference Clock Transmit Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Carrier Sense and Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force 100 Mbits/sec. Input Input Input Output Output Output Input Input Input Input Input Input Output I/O Output Synchronous Serial Controller High RMII only MII only MII only ETX0 - ETX1 only in RMII MII only MII only RMII only ERX0 - ERX1 only in RMII MII only MII only RMII only TD0 - TD2 RD0 - RD2 TK0 - TK2 RK0 - RK2 TF0 - TF2 RF0 - RF2 Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Timer/Counter Output Input I/O I/O I/O I/O TCLK0 - TCLK5 TIOA0 - TIOA5 TIOB0 - TIOB5 External Clock Input I/O Line A I/O Line B Input I/O I/O 27 1768IS–ATARM–30-Sep-05 Table 4-7. Pin Name Pin Description List (Continued) Function SPI Type Active Level Comments MISO MOSI SPCK NPCS0 NPCS1 - NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select Two-Wire Interface I/O I/O I/O I/O Output Low Low TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O 28 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 4.4 Peripheral Identifiers The AT91RM9200 embeds a wide range of peripherals. Table 4-8 defines the peripheral identifiers of the AT91RM9200. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 4-8. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Peripheral Identifiers Peripheral Mnemonic AIC SYSIRQ PIOA PIOB PIOC PIOD US0 US1 US2 US3 MCI UDP TWI SPI SSC0 SSC1 SSC2 TC0 TC1 TC2 TC3 TC4 TC5 UHP EMAC AIC AIC AIC AIC AIC AIC AIC Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D USART 0 USART 1 USART 2 USART 3 Multimedia Card Interface USB Device Port Two-wire Interface Serial Peripheral Interface Synchronous Serial Controller 0 Synchronous Serial Controller 1 Synchronous Serial Controller 2 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 Timer/Counter 4 Timer/Counter 5 USB Host Port Ethernet MAC Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 Peripheral Name Advanced Interrupt Controller External Interrupt FIQ 29 1768IS–ATARM–30-Sep-05 4.4.1 System Interrupt The System Interrupt is the wired-OR of the interrupt signals coming from: • the Memory Controller • the Debug Unit • the System Timer • the Real-Time Clock • the Power Management Controller The clock of these peripherals cannot be controlled and the Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 4.4.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ6, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 30 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 4.5 Product Memory Mapping A first level of address decoding is performed by the Memory Controller, i.e., by the implementation of the Advanced System Bus (ASB) with additional features. Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The area 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M bytes of internal memory area. The area 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. 4.5.1 External Memory Mapping External Memory Mapping 256M Bytes 256M Bytes 256M Bytes 256M Bytes 0x0000 0000 0x0FFF FFFF Figure 4-3. Internal Memories Chip Select 0 Chip Select 1 Chip Select 2 Chip Select 3 Chip Select 4 Chip Select 5 Chip Select 6 Chip Select 7 SMC or BFC SMC or SDRAMC SMC SMC SMC SMC SMC SMC CompactFlash NAND Flash/SmartMedia 0x1000 0000 0x1FFF FFFF 0x2000 0000 0x2FFF FFFF 0x3000 0000 0x3FFF FFFF 0x4000 0000 256M Bytes 256M Bytes 256M Bytes 256M Bytes 256M Bytes 0x4FFF FFFF 0x5000 0000 0x5FFF FFFF 0x6000 0000 0x6FFF FFFF 0x7000 0000 0x7FFF FFFF 0x8000 0000 0x8FFF FFFF 0x9000 0000 6 x 256M Bytes 1,536 bytes 0xEFFF FFFF Undefined (Abort) 256M Bytes 0xF000 0000 0xFFFF FFFF Peripherals 31 1768IS–ATARM–30-Sep-05 4.5.2 4.5.2.1 Internal Memory Mapping Internal RAM The AT91RM9200 integrates a high-speed, 16-Kbyte internal SRAM. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x20 0000. After Remap, the SRAM is also available at address 0x0. 4.5.2.2 Internal ROM The AT91RM9200 integrates a 128-Kbyte Internal ROM. At any time, the ROM is mapped at address 0x10 0000. It is also accessible at address 0x0 after reset and before the Remap Command if the BMS is tied high during reset. 4.5.2.3 USB Host Port The AT91RM9200 integrates a USB Host Port Open Host Controller Interface (OHCI). The registers of this interface are directly accessible on the ASB Bus and are mapped like a standard internal memory at address 0x30 0000. Figure 4-4. Internal Memory Mapping 0x0000 0000 Internal Memory Area 0 0x000F FFFF 1 MBytes 0x0010 0000 0x001F FFFF Internal Memory Area 1 Internal ROM Internal Memory Area 2 Internal SRAM Internal Memory Area 3 USB Host Port 1 MBytes 0x0020 0000 256Mbytes 0x002F FFFF 1 MBytes 0x0030 0000 0x003F FFFF 0x0040 0000 1 MBytes Undefined Area (Abort) 0x0FFF FFFF 252M bytes 32 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 4.5.3 4.5.3.1 Peripheral Mapping System Peripherals Mapping The System Peripherals are mapped to the top 4K bytes of the address space, between the addresses 0xFFFF F000 and 0xFFFF FFFF. Each peripheral has 256 or 512 bytes. Figure 4-5. System Peripherals Mapping Peripheral Name 0xFFFF F000 AIC 0xFFFF F1FF Size Advanced Interrupt Controller 512 bytes/128 registers 0xFFFF F200 DBGU 0xFFFF F3FF Debug Unit 512 bytes/128 registers 0xFFFF F400 PIOA PIO Controller A 512 bytes/128 registers 0xFFFF F5FF 0xFFFF F600 PIOB PIO Controller B 512 bytes/128 registers 0xFFFF F7FF 0xFFFF F800 PIOC PIO Controller C 512 bytes/128 registers 0xFFFF F9FF 0xFFFF FA00 PIOD PIO Controller D 512 bytes/128 registers 0xFFFF FBFF 0xFFFF FC00 PMC 0xFFFF FCFF Power Management Controller 256 bytes/64 registers 0xFFFF FD00 ST 0xFFFF FDFF System Timer 256 bytes/64 registers 0xFFFF FE00 RTC 0xFFFF FEFF Real-time Clock 256 bytes/64 registers 0xFFFF FF00 MC 0xFFFF FFFF Memory Controller 256 bytes/64 registers 33 1768IS–ATARM–30-Sep-05 4.5.3.2 User Peripherals Mapping The User Peripherals are mapped in the upper 256M bytes of the address space, between the addresses 0xFFFA 0000and 0xFFFE 3FFF. Each peripheral has a 16-Kbyte address space. Figure 4-6. User Peripherals Mapping Peripheral Name 0xF000 0000 Size Reserved 0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF TC0, TC1, TC2 Timer/Counter 0, 1 and 2 16K Bytes 0xFFFA 4000 0xFFFA 7FFF 0xFFFA 8000 TC3, TC4, TC5 Timer/Counter 3, 4 and 5 16K Bytes Reserved 0xFFFA FFFF 0xFFFB 0000 0xFFFB 3FFF UDP USB Device Port 16K Bytes 0xFFFB 4000 0xFFFB 7FFF MCI Multimedia Card Interface 16K Bytes 0xFFFB 8000 0xFFFB BFFF TWI Two-Wire Interface 16K Bytes 0xFFFB C000 0xFFFB FFFF EMAC Ethernet MAC 16K Bytes 0xFFFC 0000 0xFFFC 3FFF USART0 Universal Synchronous Asynchronous Receiver Transmitter 0 Universal Synchronous Asynchronous Receiver Transmitter 1 Universal Synchronous Asynchronous Receiver Transmitter 2 Universal Synchronous Asynchronous Receiver Transmitter 3 Serial Synchronous Controller 0 16K Bytes 0xFFFC 4000 0xFFFC 7FFF USART1 16K Bytes 0xFFFC 8000 0xFFFC BFFF USART2 16K Bytes 0xFFFC C000 0xFFFC FFFF USART3 16K Bytes 0xFFFD 0000 0xFFFD 3FFF SSC0 16K Bytes 0xFFFD 4000 0xFFFD 7FFF SSC1 Serial Synchronous Controller 1 16K Bytes 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 SSC2 Serial Synchronous Controller 2 16K Bytes Reserved 0xFFFD FFFF 0xFFFE 0000 0xFFFE 3FFF 0xFFFE 4000 SPI Serial Peripheral Interface 16K Bytes Reserved 0xFFFE FFFF 34 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary 4.6 4.6.1 Peripheral Implementation USART The USART describes features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91RM9200, only the USART1 implements these signals, named DTR1, DSR1, DCD1 and RI1. The USART0, USART2 and USART3 do not implement all the modem signals. Only RTS and CTS (RTS0 and CTS0, RTS2 and CTS2, RTS3 and CTS3, respectively) are implemented in these USARTs for other features. Thus, programming the USART0, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated. 4.6.2 Timer Counter The Timer Counter 0 to 5 are described with five generic clock inputs, TIMER_CLOCK1 to TIMER_CLOCK5. In the AT91RM9200, these clock inputs are connected to the Master Clock (MCK), to the Slow Clock (SLCK) and to divisions of the Master Clock. Table 4-9 gives the correspondence between the Timer Counter clock inputs and clocks in the AT91RM9200. Each Timer Counter 0 to 5 displays the same configuration. Table 4-9. Timer Counter Clocks Assignment Clock MCK/2 MCK/8 MCK/32 MCK/128 SLCK TC Clock Input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 35 1768IS–ATARM–30-Sep-05 5. Revision History Doc. Rev Lit°1768A Lit°1768B Lit°1768C Lit°1768D Lit°1768E Lit°1768F Doc. Rev 1768GS Source Comments • Date Qualified: May 2001 • Date Qualified: September 2001 • Date Qualified: November 2001 • Date Qualified: 5 Mar-02 • Date Qualified: 12-Julr-02 • Date Qualified: 5 Feb-03 Source Review Comments • Date Qualified: 04-Sep-03 • Page 2; Added Description. • Page 3; Updated Figure 1, Block Diagram, remove reference to Multi-master Memory Controller. • Page 4; Added section Key Features. Updated all descriptions of key blocks • Page 17; Added text to section Peripheral Mulitplexing on PIO Lines. • Page 18; Expanded Table 3, Multiplexing on PIO Controller A. • Page 19: Expanded Table 4, Multiplexing on PIO Controller B. • Page 20; Expanded Table 5, Multiplexing on PIO Controller C. • Page 21; Expanded Table 6, Multiplexing on PIO Controller D. • Page 27; Updated Table 8, Peripheral Identifiers, Peripheral ID 1 description. • Page 28; Added section Product Memory Mapping. • Page 30; Updated and corrected Figure 6, System Peripherals Mapping. • Page 31; Updated and corrected Figure 7, User Peripherals Mapping. Doc. Rev 1768HS Source CSRs/Review Comments • Date Qualified: Unqualified/Internal on Intranet 27-Jan-05 • Global; Reformat in Corporate Template. • Global; Peripheral Data Controller (PDC) nenamed Peripheral DMA Controller. CSR 04-066 CSR 03-209 CSR 03-244 CSR 04-315 CSR 03-209 • Page 1; Features: USART Hardware Handshaking. Software Handshaking removed. • Page 3; Figure 1: NWAIT pin added to block diagram. • Page 14; Table 1. AT91RM9200 Pinout for 208-lead PQFP package, pins 28, 30, 37 and 39 names changed • Page 23; Table 7. Pin Description, ICE and JTAG description, “Internal Pullup” added to comments for all signals, except TDO. • Page 24; Table 7. Pin Description, NWAIT pin added. 36 AT91RM9200 Summary 1768IS–ATARM–30-Sep-05 AT91RM9200 Summary Doc. Rev 1768IS CSR 05-348 Source Comments Corrected power consumption values on page 1. In Table 4-7, “Pin Description List,” on page 24 added mention of Schmitt trigger for pins JTAGSEL, TDI, TCK, TMS, NTRST, TST0, TST1 and NRST. 37 1768IS–ATARM–30-Sep-05 A tmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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