Features
• ARM7TDMI® ARM® Thumb® Processor Core
– High-performance 32-bit RISC – High-density 16-bit Thumb Instruction Set – Leader in MIPS/Watt – Embedded ICE (In Circuit Emulation) 4 Kbytes Internal RAM Clock Manager (CM) with Programmable PLL – PLL Multiplier from x2 to x20 – 32.768 kHz Oscillator for Low-power Operation – Master Clock Divider/multiplier Fully Programmable External Bus Interface (EBI) through Advanced Memory Controller (AMC) – Maximum External Address Space of 16 Mbytes, Up to Six Chip Select Lines 8-level Priority, Vectored Interrupt Controller – Individually Maskable, Two External Interrupts including One Fast Interrupt Line 11-channel Peripheral Data Controller (PDC) 49 Programmable I/O Lines One 3-channel 16-bit General Purpose Timers (GPT) – Three Configurable Modes: Counter, PWM, Capture – Three Multi-purpose I/O Pins Per Channel Four 16-bit Simple Timers (ST) 4-channel 16-bit Pulse Width Modulation (PWM) Two 16-bit Capture Modules (CAPT) CAN Controller 2.0A and 2.0B Full CAN (16 Buffers) Three USARTs – Six Peripheral Data Controller (PDC) Channels – Support for Up to 9-bit Data Lengths – Support for J1587 Protocol and LIN (Software) Protocols Master SPI Interface – Two Peripheral Data Controller (PDC) Channels – 8- to 16-bit Programmable Data Length – Four External Chip Select Lines One 8-channel 10-bit Analog-to-digital Converter (ADC) – One Peripheral Data Controller (PDC) Channel Programmable Watch Timer (WT) Programmable Watchdog (WD) Power Management Controller (PMC) – CPU and Peripherals Can Be Deactivated Individually Fully Static Operation Up to 40 MHz – 3.0V to 3.6V Core, Memory and Analog Voltage Range – 3.0 V to 5.5V Compliant I/Os – -40° to +85°C Operating Temperature Range Available in a 144-pin LQFP
• •
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AT91 ARM® Thumb®-based Microcontroller AT91SAM7A1
• • • •
• • • • •
•
• • • • •
•
6048A–ATARM–03-Mar-05
1. Description
The AT91SAM7A1 is a member of the Atmel Smart Automotive Microcontrollers product family, based on the ARM7TDMI embedded processor. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91SAM7A1 has a direct connection to off-chip memory, including Flash, through the fully-programmable External Bus Interface. An 8-level priority vectored Interrupt Controller in conjunction with the Peripheral Data Controller significantly improves the real-time performance of the device. The device is manufactured using high-density CMOS technology. By combining the ARM7TDMI processor with an on-chip RAM and a wide range of peripheral functions on a monolithic chip, the AT91SAM7A1 is a powerful device that provides a flexible, cost-effective solution to many compute-intensive embedded control applications in the automotive and industrial world.
2. Pin Configuration
The AT91SAM7A1 is available in a 144-lead LQFP package.
2.1
144-lead LQFP Package
Figure 2-1 shows the orientation of the 144-lead LQFP package. A detailed mechanical description is given in the section Mechanical Characteristics. Figure 2-1. 144-lead LQFP Package
144 109 108 1
36 37 72
73
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6048A–ATARM–03-Mar-05
AT91SAM7A1
2.2 144-lead LQFP Package Pinout
AT91SAM7A1 Pinout for 144-lead LQFP Package
Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Name ADD11 ADD12 ADD13 ADD14 ADD15 GND3V (IO) VDD3V (CORE) VDD5V (IO) IRQ0 FIQ T0TIOA0/MPIO T0TIOB0/MPIO T0TCLK0/MPIO T0TIOA1/MPIO T0TIOB1/MPIO T0TCLK1/MPIO T0TIOA2/MPIO T0TIOB2/MPIO GND5V (I/O) T0TCLK2/MPIO TXD0/MPIO RXD0/MPIO SCK0/MPIO TXD1/MPIO RXD1/MPIO SCK1/MPIO VDD5V (I/O) SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS0/NSS/MPIO NPCS1/MPIO NPCS2/MPIO NPCS3/MPIO PIOA0 PIOA1 Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Name GND5V (I/O) PIOA2 PIOA3 VDD5V (I/O) PIOA4 PIOA5 PIOA6 PIOA7 PIOA8 PIOA9 GND5V (I/O) PIOA10 PIOA11 PIOA12 PIOA13 PIOA14 PIOA15 PIOA16 PIOA17 PWM0/MPIO VDD5V (I/O) PWM1/MPIO PWM2/MPIO PWM3/MPIO CAPT0/MPIO CAPT1/MPIO NRESET CANRX0 CANTX0 TXD2/MPIO RXD2/MPIO SCK2/MPIO GND5V (I/O) VDD3V (ANA) VREFP0 ANA0IN0 Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Name ANA0IN1 ANA0IN2 ANA0IN3 ANA0IN4 ANA0IN5 ANA0IN6 ANA0IN7 GND3V (ANA) VDD3V (PLL) MCKI MCKO PLLRC GND3V (PLL) VDD3V (RTCK) RTCKI RTCKO GND3V (RTCK) VDD3V (I/O) GND3V (CORE) GND3V (I/O) SCANEN TEST TMS TDO TDI TCK NWAIT ADD21/CS6 NCS3 NCS2 NWR1/NUB ADD0/NLB NCS1 NOE/NRD NCS0 ADD1
Table 2-1.
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Name D0 D8 D1 D9
VDD3V (I/O) GND3V (I/O+CORE) VDD3V (I/O+CORE) D2 D10 D3 D11 D4 D12 D5 D13 D6 D14 D7 D15 ADD17 ADD16 NWR0/NWE ADD19 ADD18 ADD7 ADD6 GND3V (I/O+CORE) VDD3V (I/O+CORE) ADD2 ADD3 ADD4 ADD5 ADD8 ADD20/CS7 ADD9 ADD10
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6048A–ATARM–03-Mar-05
3. Signal Description
Table 3-1.
Signal Name
Pin Description
Function Type(1) EBI(2) The EBI is tri-stated when NRESET is at a logical low level. Internal pull-downs on data bus bits. ADD20 and ADD21 are address lines at reset. Level(1) Comments
ADD[19:1]
External address bus
O
(Z)
ADD0/NLB ADD20/CS7 ADD21/CS6 D[15:0]
(3)
External address line/Lower byte enable External address line/Chip select External address line/Chip select External data bus Output enable Write enable Chip select lines Upper byte enable Wait input
O O O I/O O O O O I GIC
L (Z) H (Z) H (Z) (Z) L (Z) L (Z) L (Z) L (Z) L Internal pull-up (must be connected to VCC or leave unconnected for normal operation if functionality not used)
NOE/NRD NWR0/NWE NCS[3:0] NWR1/NUB NWAIT
IRQ0 FIQ
External interrupt line Fast interrupt line
I I Power-on Reset
NRESET
Hardware reset input
I Master Clock
L
Schmitt input with internal filter
MCKI MCKO PLLRC
Master clock input Master clock output PLL RC network input
I O I Real-time Clock
Connected to external crystal (4 to 16 MHz)
RTCKI RTCKO
32.768 kHz clock input 32.768 kHz clock output
I O UPIO
Connected to external 32.768 kHz crystal
UPIO[17:0]
Unified I/O
I/O (I) USART0
(Z)
General purpose I/O
SCK0/MPIO RXD0/MPIO TXD0/MPIO
USART0 clock line USART0 receive line USART0 transmit line
I/O (I) I/O (I) I/O (I) USART1
(Z) (Z) (Z)
Multiplexed with general purpose I/O Multiplexed with general purpose I/O Multiplexed with general purpose I/O
SCK1/MPIO
USART1 clock line
I/O (I)
(Z)
Multiplexed with general purpose I/O
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AT91SAM7A1
6048A–ATARM–03-Mar-05
AT91SAM7A1
Table 3-1.
Signal Name RXD1/MPIO TXD1/MPIO
Pin Description (Continued)
Function USART1 receive line USART1 transmit line Type(1) I/O (I) I/O (I) USART2 Level(1) (Z) (Z) Comments Multiplexed with general purpose I/O Multiplexed with general purpose I/O
SCK2/MPIO RXD2/MPIO TXD2/MPIO
USART2 clock line USART2 receive line USART2 transmit line
I/O (I) I/O (I) I/O (I) Capture
(Z) (Z) (Z)
Multiplexed with general purpose I/O Multiplexed with general purpose I/O Multiplexed with general purpose I/O
CAPT[1:0]/MPIO
Capture input
I/O (I) PWM
(Z)
Multiplexed with general purpose I/O
PWM[3:0]/MPIO
Pulse Width Modulation output
I/O (I) Timer 0
(Z)
Multiplexed with general purpose I/O
T0TIOA[2:0]/MPIO T0TIOB[2:0]/MPIO T0TCLK[2:0]/MPIO
Capture/waveform I/O Trigger/waveform I/O External clock/trigger/input
I/O (I) I/O (I) I/O (I) ADC
(Z) (Z) (Z)
Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O
ANAIN[7:0] VREFP
Analog input Positive voltage reference
I I SPI
SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS[3:1]/MPIO NPCS0/NSS/MPIO
SPI clock line SPI master in slave out SPI master out slave in SPI chip select SPI chip select (master and slave)
I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) CAN0
(Z) (Z) (Z) (Z) (Z)
Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O Multiplexed with a general purpose I/O
CANRX0 CANTX0
CAN0 receive line CAN0 transmit line
I O JTAG
L L (H)
SCANEN TDI TDO TMS TCK TEST
Scan enable (Factory test) Test Data In Test Data Out Test Mode Select Test Clock Factory test
I I O I I I
H
Internal pull-down (must be connected to GND or leave unconnected for normal operation) Schmitt trigger, internal pull-up
Schmitt trigger, internal pull-up Schmitt trigger, internal pull-up H Internal pull-down (must be connected to GND or leave unconnected for normal operation)
Power Supply and Ground VDD3V (CORE) 3.3V for core -
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6048A–ATARM–03-Mar-05
Table 3-1.
Signal Name
Pin Description (Continued)
Function Ground for core 3.3V for core and 3V I/O Ground for core and 3V I/O 3.3V for RTCK oscillator Ground for RTCK oscillator 3.3V for PLL and master oscillator Ground for PLL and master oscillator 3.3V for analog cells Analog Ground for analog cells 3.3V for functional I/O Ground for functional I/O 3.3V to 5V for functional I/O Ground for functional I/O Type(1) Level(1) Comments
GND3V (CORE) VDD3V (I/O+CORE) GND3V (I/O+CORE) VDD3V (RTCK) GND3V (RTCK) VDD3V (PLL) GND3V (PLL) VDD3V (ANA) GND3V (ANA) VDD3V (I/O) GND3V (I/O) VDD5V (I/O) GND5V (I/O) Notes:
1. Values in brackets are values at reset: H (high level), L (low level), Z (tri-state), I (input), O (output). 2. The EBI bus (address bus A[21:0], data bus D[15:0] and control lines NOE/NRD, NWR0/NWE, NWR1/NUB and NCS[3:0]) is tri-stated when NRESET is at logical 0. This allows external equipment to access the external memory devices (e.g., for Flash programming). It is up to the application to add an external pull-up on the chip select lines in order to avoid EBI conflicts at reset. 3. The EBI data bus D[15:0] has an internal pull-down.
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AT91SAM7A1
6048A–ATARM–03-Mar-05
AT91SAM7A1
4. Block Diagram
Figure 4-1. AT91SAM7A1 Block Diagram
5V SCANEN GND3V VDD3V 3V
NWAIT
TEST
IRQ0
TMS
TDO
TCK
FIQ
TDI
VDD5V GND5V
I/O Power Supply
Core Power Supply Advanced Interrupt Controller SPI
Select
JTAG
Advanced Memory Controller EBI
SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS0/MPIO NPCS1/MPIO NPCS2/MPIO NPCS3/MPIO RXD0/MPIO TXD0/MPIO SCK0/MPIO RXD1/MPIO TXD1/MPIO SCK1/MPIO RXD2/MPIO TXD2/MPIO SCK2/MPIO
Embedded ICE Arbiter ASB Controller SFM AMBATM Bridge ARM7TDMI Core
PIO 2 PDC Channels USART0 2 PDC Channels USART1 2 PDC Channels USART2 2 PDC Channels Timer GPT0 Simple Timers ST0 CH0 CH1 Clock Manager
PLLON
11 Channel PDC Controller
ADD[19:1] ADD0/NLB ADD20/CS7 ADD21/CS6 NOE/NRD NWR0/NWE NWR1 /NUB 1 NCS[3:0] D[15:0]
3V
4 KB Internal RAM Reset NRESET
PIO
5V
PIO
Watch Dog
32.768 MHz
PIO
LFCLK 64 PLL
PLL x MCK 4 - 8 MHz
RT Osc
RTCKI RTCKO
5V
MC Osc
MCKI MCKO PLLRC
3V
T0TIOA0/MPIO T0TIOB0/MPIO T0TCLK0/MPIO T0TIOA1/MPIO T0TIOB1/MPIO T0TCLK1/MPIO T0TIOA2/MPIO T0TIOB2/MPIO T0TCLK2/MPIO
PIO TC0 ST1 CH0 PIO TC1 CH1 CORECLK Capture 0 CH0 PIO
AT91SAM7A1
1 PDC Channel Capture 1
CAPT0/MPIO
PIO TC2 WT
CH0
PIO
CAPT1/MPIO
1 PDC Channel PWM CH0 PWM0/MPIO PIO PWM1/MPIO PWM2/MPIO PWM3/MPIO 5V
Analog Power Suppy
1 PDC Channel CAN0 ADC0 8-channel 10-bit ADC UPIO Full Speed 16 Buffers
CH1 CH2 CH3
VDDANA
CANRX0
GNDANA
ANA0IN[7:0]
CANTX0
VREFP
Analog
5V
UPIO[17:0]
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6048A–ATARM–03-Mar-05
5. Product Overview
5.1
5.1.1
Register Considerations
Enable/Disable/Status Registers In order to reduce code size and subsequently increase speed when accessing internal peripherals, most of the registers have been split into three address locations: • The first address location (Enable or Set Register) is used to set a bit to a logical 1. • The second address location (Disable or Clear Register) is used to set a bit to a logical 0. • The third address location (Status register or Mask Register) gives the current state of the bit. To set a bit to a logical 1 in the Status or Mask Register, a write command in the Enable or Set Register must be performed with the corresponding bit at a logical 1. To set a bit to a logical 0 in the Status or Mask Register, a write command in the Disable or Clear Register must be performed with the corresponding bit at a logical 1.
5.1.2
Example Supposing that the US0_PSR register value is 0x00000000. To enable the RXD and SCK pins as PIOs in the USART0 block, 0x00050000 must be written in the US0_PER register. The value read in the US0_PSR register will be 0x00050000. Now if the software wants to disable the RXD pin as a PIO (i.e. enable it for USART0 use), a write access to the US0_PDR register with the value 0x00040000 must be performed. The new value read in the US0_PSR register will be 0x00010000.
5.1.3
Key Access to Registers Some bits in registers can be set to a value (0 or 1) only if the right key is written at the same time. Example 1 The TESTEN bit in the SFM_TM register can be set to a logical 0 or 1 only if the KEY[15:0] bits are equal to 0xD64A. To enable test mode, 0xD64A0002 must be written in the SFM_TM register. To disable test mode, 0xD64A0000 must be written in the SFM_TM register.
5.1.3.1
5.1.3.2
Example 2 To set the RTCKEN bit in the CM_CS register to logical 1, a write access to the CM_CE register must be done with a value of 0x23050080. To set the RTCKEN bit in the CM_CS register to logical 0, a write access to the CM_CD register must be done with a value of 0x18070080.
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AT91SAM7A1
5.2
5.2.1
Power Consumption
Working Modes The AT91SAM7A1 microcontroller provides different working modes.
Table 5-1.
Mode
Working Modes
Note The master clock oscillator, the PLL and the internal divider are switched off. The real time oscillator is enabled. The low frequency clock is selected from the real time oscillator and used as a system clock (i.e., 32.768 kHz used for GIC, WD, WT, ST and any peripheral needed for interrupt generation). CORECLK = RTCK, LFCLK = RTCK The PLL is switched off. The system clock is the master clock (CORECLK = MCK) or the master clock divided by β (CORECLK = MCK/β, β in the range [2:256]). Master oscillator and PLL are enabled. The system clock is the clock from the PLL, CORECLK = α x MCK (α in the range [x2:x20])
Low-power Mode (LPM)
Slow Mode (SLM) Operational (OPE)
5.2.2
Low-power Mode Low-power mode is defined as the state in which: • Master clock oscillator and PLL are stopped • Low frequency oscillator (32.768 kHz) is used as an internal system clock for core and all peripherals (CORECLK = RTCK, LFCLK = RTCK) The total power dissipation of the AT91SAM7A1 embedded system, when in low power mode, is estimated to be 170 µW maximum, at an operating voltage of 3.3V, over the operating temperature range. Additional conditions are: ARM core stopped, PDC stopped, all modules disabled except ST0, ST1, WT, WD and PMC working at 32.768 kHz.
5.2.3
Slow Mode Slow mode is defined as the state in which: • Master clock oscillator is enabled, divided by β (β in the range [2:256]) and used as the system clock (CORECLK = MCK or MCK/β) • The low frequency clock can still be used as low frequency clock for peripherals (LFCLK = RTCK or MCK/β) The total power dissipation of the AT91SAM7A1 embedded system, when in halt mode, is estimated to be 78 mW with CORECLK = MCK, at an operating voltage of 3.3V, over the operating temperature range and with ARM core and modules working at CORECLK frequency = 4 MHz. With CORECLK = MCK/64, total power dissipation is estimated at 4 mW, at an operating voltage of 3.3V, over the operating temperature range and with ARM core and modules working at CORECLK frequency = 62.5 kHz (i.e., 4 MHz/64).
5.2.4
Operational Mode Operational mode is defined as the state in which: • Master clock oscillator and PLL are enabled, system clock is taken from the PLL output (CORECLK = α x MCK, where α is in the range [2:20]) • The Low frequency clock can still be used as low frequency clock for peripherals (LFCLK = RTCK or MCK/β, β in the range [2:256]) The total power dissipation of the AT91SAM7A1 embedded system, when in operational mode, is estimated to be 605 mW maximum, at an operating voltage of 3.3V, over the operat9
6048A–ATARM–03-Mar-05
ing temperature range and with ARM core and modules working at CORECLK frequency = 32 MHz (i.e., MCK = 4 MHz, PLL multiplier = 8).
5.3
Reset
The application must ensure a reset of at least 5 ms to allow time for the system clock to stabilize (CORECLK). The 32.768 kHz clock (RTCK) will be stabilized 300 ms after the reset is asserted. Software should not use or program the peripherals (WD, WT, ST) which are using this clock until it is stabilized.
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AT91SAM7A1
5.4 Electrical Characteristics
AT91SAM7A1 Pin Connections for 144-lead LQFP Package
Pad PC3B01D PC3B01D PC3B01D PC3B01D Pin Name 37 38 39 40 41 42 43 PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3T02 PC3T02 PC3B02 PC3T02 PC3T02 PC3T02 PC3T02 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 65 66 67 68 69 70 71 72 ADD11 ADD12 ADD13 ADD14 ADD15 GND3V (IO) VDD3V (CORE) VDD5V (IO) IRQ0 FIQ T0TIOA0/MPIO T0TIOB0/MPIO T0TCLK0/MPIO T0TIOA1/MPIO T0TIOB1/MPIO T0TCLK1/MPIO T0TIOA2/MPIO T0TIOB2/MPIO GND5V (I/O) T0TCLK2/MPIO TXD0/MPIO RXD0/MPIO SCK0/MPIO TXD1/MPIO RXD1/MPIO SCK1/MPIO VDD5V (I/O) SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS0/NSS/MPIO NPCS1/MPIO NPCS2/MPIO NPCS3/MPIO PIOA0 PIOA1 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B04 MC5B04 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 Pad PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 Pin Name 73 74 75 76 77 78 79 80 MC5D00 81 MC5D00 82 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 GND5V (I/O) PIOA2 PIOA3 VDD5V (I/O) PIOA4 PIOA5 PIOA6 PIOA7 PIOA8 PIOA9 GND5V (I/O) PIOA10 PIOA11 PIOA12 PIOA13 PIOA14 PIOA15 PIOA16 PIOA17 PWM0/MPIO VDD5V (I/O) PWM1/MPIO PWM2/MPIO PWM3/MPIO CAPT0/MPIO CAPT1/MPIO NRESET MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B02 MC5B02 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B03 MC5B03 MC5B03 MC5B03 MC5B03 MC5B03 MC5B04 MC5B04 Pad Pin Name 109 ANA0IN1 110 ANA0IN2 111 ANA0IN3 112 ANA0IN4 113 ANA0IN5 114 ANA0IN6 115 ANA0IN7 116 GND3V (ANA) 117 VDD3V (PLL) 118 MCKI 119 MCKO 120 PLLRC 121 GND3V (PLL) 122 VDD3V (RTCK) 123 RTCKI 124 RTCKO 125 GND3V (RTCK) 126 VDD3V (I/O) 127 GND3V (CORE) 128 GND3V (I/O) 129 SCANEN 130 TEST 131 TMS 132 TDO 133 TDI 134 TCK PC3D01D PC3D01D PC3D21U PC3T03 PC3D21U PC3D21U PC3D01U PC3T02 PC3T02 PC3T02 PC3B02 PC3T02 PC3T02 PC3B02 PC3T02 PC3T02 OSC33K OSC33K OSC16M OSC16M PLL080M1 Pad AIMUX1 AIMUX1 AIMUX1 AIMUX1 AIMUX1 AIMUX1 AIMUX1
Table 5-2.
Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 D0 D8 D1 D9 VDD3V (I/O)
GND3V (I/O+CORE) VDD3V (I/O+CORE) D2 D10 D3 D11 D4 D12 D5 D13 D6 D14 D7 D15 ADD17 ADD16 NWR0/NWE ADD19 ADD18 ADD7 ADD6 GND3V (I/O+CORE) VDD3V (I/O+CORE) ADD2 ADD3 ADD4 ADD5 ADD8 ADD20/CS7 ADD9 ADD10
MC5D20 135 NWAIT MC5D00 136 ADD21/CS6 MC5O01 137 NCS3 MC5B01 MC5B01 MC5B01 138 NCS2 139 NWR1/NUB 140 ADD0/NLB 141 NCS1 142 NOE/NRD ANAIN AIMUX1 143 NCS0 144 ADD1
100 CANRX0 101 CANTX0 102 TXD2/MPIO 103 RXD2/MPIO 104 SCK2/MPIO 105 GND5V (I/O) 106 VDD3V (ANA) 107 VREFP0 108 ANA0IN0
Note: Note: Note: Note:
Pins 7, 28 and 43, i.e. VDD3V (CORE) and VDD3V (I/O + CORE), are internally connected together. Pins 6, 27 and 127, i.e. GND3V (CORE) and GND3V (I/O + CORE), are internally connected together. Pins K6, K4 and H4, i.e. VDD3V (CORE) and VDD3V (I/O + CORE), are internally connected together. Pins G4, J4 and D6, i.e. GND3V (CORE) and GND3V (I/O + CORE), are internally connected together.
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6048A–ATARM–03-Mar-05
Pad types are given in Table 5-3 below.
Table 5-3.
Pad MC5B01 MC5B02 MC5B03 MC5B04 MC5O01 MC5D00 MC5D20 PC3D01D PC3D01U PC3D21 PC3D21U PC3T01 PC3T02 PC3T03 PC3B01D PC3B01 PC3B02 PC3B03 OSCK33 OSC16M PLL080M 1 AIMUX1 Notes:
Pad Types
Type 5 V CMOS bidirectional pad 5 V CMOS bidirectional pad 5 V CMOS bidirectional pad 5 V CMOS bidirectional pad 5 V CMOS output pad 5 V CMOS non-inverting input pad 5 V CMOS schmitt non-inverting input pad 3 V CMOS non-inverting input pad with pulldown resistor 3 V CMOS non-inverting input pad with pullup resistor 3 V CMOS schmitt non-inverting input pad 3V CMOS schmitt non-inverting input pad with pull-up resistor 3 V CMOS three state output pad 3 V CMOS three state output pad 3 V CMOS three state output pad 3 V CMOS bidirectional pad with pull-down resistor 3 V CMOS non-inverting bidirectional pad 3 V CMOS non-inverting bidirectional pad 3 V CMOS non-inverting bidirectional pad 32.768 kHz crystal oscillator pad 2-6 MHz crystal oscillator pad 20 MHz to 80 MHz single pad PhaseLocked Loop Analog input pad 0.120 ns/pF 0.060 ns/pF 0.040 ns/pF 0.118 ns/pF 0.120 ns/pF 0.060 ns/pF 0.040 ns/pF 0.116 ns/pF 0.058 ns/pF 0.039 ns/pF 0.116 ns/pF 0.116 ns/pF 0.058 ns/pF 0.039 ns/pF 1.357 ns 1.002 ns 0.943 ns 1.357 ns 1.372 ns 1.010 ns 0.948 ns 1.011 ns 0.781 ns 0.800 ns 1.040 ns 1.033 ns 0.789 ns 0.808 ns 2 mA AC 0.3 mA DC 4 mA AC 0.3 mA DC 6 mA AC 0.3 mA DC 2 mA AC 0.3 mA DC 2 mA AC 0.3 mA DC 6 mA AC 0.3 mA DC 6 mA AC 0.3 mA DC DTPDHL(1) 0.144 ns/pF 0.072 ns/pF 0.036 ns/pF 0.018 ns/pF 0.144 ns/pF DTPDLH(2) 0.131 ns/pF 0.066 ns/pF 0.033 ns/pF 0.017 ns/pF 0.131 ns/pF TPDHL(3) 2.327 ns 2.298 ns 2.727 ns 3.265 ns 2.310 ns TPDLH(4) 2.192 ns 2.179 ns 2.034 ns 2.449 ns 2.174 ns Output Current 2 mA AC 2 mA DC 4 mA AC 4 mA DC 8 mA AC 8 mA DC 16 mA AC 16 mA DC 2 mA AC 2 mA DC
1. Differential (load-dependent) propagation delay, high-to-low or high impedance-to-low (VDD = 3.3 V, Temp. = 25°C, Input Slope = 1 ns) 2. Differential (load-dependent) propagation delay, low-to-high or high impedance-to-high (VDD = 3.3 V, Temp. = 25°C, Input Slope = 1 ns) 3. Propagation delay, high-to-low (VDD = 3.3 V, Temp. = 25°C, Input Slope = 1 ns) 4. Propagation delay, low-to-high (VDD = 3.3 V, Temp. = 25°C, Input Slope = 1 ns)
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5.4.1 Propagation Delay The propagation delay time shown in Table 5-3, “Pad Types,” on page 12, is the time in nanoseconds from the 50% point of the input to the 50% point of the output. Figure 5-1. Propagation Delay
Output Buffer 1 ns Input Slope Pad Line Capacitance (c) GND Input Slope low to high transition
50% TPDLH
Pad Slope low to high transition
50% DTPDLHxC
Line Slope low to high transition
50%
Input Slope high to low transition
50% TPDHL
Pad Slope high to low transition DTPDHLxC Line Slope high to low transition 50%
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6. Clocks
6.1 Crystals
Crystals with 10 pF load capacitance can be directly connected to the oscillator pads. Nevertheless, it is recommended to implement the circuitry as described hereafter and in Figure 6-1 below. Figure 6-1. Circuitry for 10 pF Load Capacitance
MCKO or RTCKO
RD
C2 VSS Crystal
MCKI or RTCKI
C1 VSS
If the crystal recommended capacitor Cx is greater than 10 pF, then C1 and C2 must be added. Cx can be approximated to: Cx = (C1 x C2)/(C1 + C2). Value of resistor RD depends on crystal frequency and manufacturer. Typical values of RD are given in Table 6-1 (values should be adjusted in the application environment). Table 6-1.
Signal MCKO RTCKO
Typical Crystal Series Resistor
RD 0Ω 10 kΩ Conditions Crystal: CP12A-4MHz-S1-4085-1050 (NDK®) Crystal: MC-306 32.768K-A (EPSON®)
6.2
Phase Locked Loop
The AT91SAM7A1 microcontroller integrates a programmable PLL. The PLL requires an external RC network as described hereafter and in Figure 6-2 below. Figure 6-2. External RC Network
PLLRC R C4 VSS C3 VSS
The optimum response with a simple RC filter is obtained when: Equation1: K0 × IP R × C4 0.4 < ⎛ ---------------------------------- ⎞ × ----------------- < 1with an optimum value of 0.707 ⎝ n × ( C 3 + C 4 )⎠ 2
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Where: • K0 is the PLL VCO gain (typ 105.106 Hz/V, min 65.106 Hz/V, max 172.106 Hz/V) • IP is the peak current delivered by the charge pump into the filter (typ. 350 µA, min. 50 µA, max. 800 µA) • n is the division ratio of the divider (i.e., PLL multiplication factor) Stability can be improved with an additional capacitor C3. The value of C3 must be chosen so that: Equation 2:
C4 4 < ------ < 15 C3
Equation 3:
Π × f CKR K0 × Ip ⎛ ---------------------------------- ⎞ ≤---------------------⎝ n × ( C 3 + C 4 )⎠ 5
Where: • fCKR is the PLL input frequency (i.e., MCK). Phase jitter for the PLL is 200 ps typical. 6.2.1 Table 6-2.
Code fCKR fCK Wlow jCK n K0 IP
PLL Characteristics PLL Characteristics
Parameter Input frequency Output frequency Duty cycle Jitter Division ratio VCO gain CHP current With ratio 1:1 1:1 65 50 105 350 Conditions Min 0.02 20 50 200 1:1024 172 800 MHz/V mA Typ Max 30 30 Unit MHz MHz % ps
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6.3
6.3.1
Clock Timings
Master Clock The master clock is the clock generated by the master clock oscillator. The master clock (MCK) characteristics are given in Table 6-3.
Table 6-3.
Symbol 1/tMP tMP tMH tML
Master Clock Timings
Parameter Master oscillator frequency Master clock period Master clock high time Master clock low time Minimum 4000 62.5 0.40 x tMP 0.40 x tMP 0.50 x tMP 0.50 x tMP Typical Maximum 16000 250 0.60 x tMP 0.60 x tMP Unit kHz ns ns ns
Figure 6-3.
Master Clock Waveform
tMH MCK 0.3VVDD3V 0.7VVDD3V
tML
tMP
6.3.2
32.768 kHz Frequency Clock The 32.768 kHz clock is the clock generated by the real time clock oscillator. The real time clock (RTCK) characteristics are given below in Table 6-4. Low Frequency Clock Timings
Parameter 32.768kHz oscillator frequency 32.768kHz clock period 32.768kHz clock high time 32.768kHz clock low time Duty cycle (tRTCH/tRTCP) 0.40 x tRTCP 0.40 x tRTCP 40 Minimum Typical 32.768 30517.58 0.50 x tRTCP 0.50 x tRTCP 50 0.60 x tRTCP 0.60 x tRTCP 60 Maximum Unit kHz ns ns ns %
Table 6-4.
Symbol 1/tRTCP tRTCP tRTCH tRTCL DtRTCP
Figure 6-4.
32.768 kHz Clock Waveform
tRTCH RTCK 0.3VVDD3V 0.7VVDD3V
tRTCL
tRTCP
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6.3.3 Core Clock The core clock is the clock used in the system for the core and peripheral. The core clock (CORECLK) characteristics are given in Table 6-5. Table 6-5.
Symbol 1/tCP tCP tCH tCL DtCP
Core Clock Timings
Parameter Core clock frequency Core clock period Core clock high time Core clock low time Duty cycle (tCH/tCP) Minimum 32.768 25 0.40 x tCP 0.40 x tCP 40 0.50 x tCP 0.50 x tCP 50 Maximum 40000 30517.58 0.60 x tCP 0.60 x tCP 60 Unit kHz ns ns ns %
Figure 6-5.
Core Clock Waveform
tCH CORECLK 0.3VVDD3V 0.7VVDD3V
tCL
tCP
6.4
6.4.1
Internal Oscillator Characteristics
Core Clock Oscillator Core Clock Oscillator
Parameter Duty cycle Operating frequency Startup time Startup time Internal capacitance (MCKI/GND) Internal capacitance (MCKO/GND) Equivalent load capacitance (MCKI/MCKO) Drive level Equivalent Series Resistance Equivalent Series Resistance Shunt capacitance Load capacitance Motional capacitance 1. These values are not characterized. Fundamental @ 8 Mhz Fundamental @ 4 Mhz Crystal Crystal @ 4 MHz Crystal @ 4 MHz 10(1) 3(1) Crystal @ 4 MHz Crystal @ 8 MHz 10 10 5 50(1) 100(1) 50(1) 6 pF pF fF Conditions Crystal @ 4 MHz Min 40 4 Typ 50 Max 60 16 10 5(1) Unit % MHz ms ms pF pF pF W
Table 6-6.
Code Du Opf tSU tSU C1 C2 CL DL Rs Rs Cs CL Cm Note:
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6.4.2 Table 6-7.
Code Du tsu C1 C2 CL DL Rs Cs
Real Time Clock Oscillator Real Time Clock Oscillator
Parameter Duty cycle Startup time Internal capacitance (RTCKI/GND) Internal capacitance (RTCKO/GND) Equivalent load capacitance (RTCKI/RTCKO) Drive level Series resistance Shunt capacitance Load capacitance Crystal Crystal Crystal @ 32.768 kHz Crystal @ 32.768 kHz 1 0.8 10 4 20 20 10 1 60 1.7 Conditions @ 32.768 kHz Min 40 Typ 50 Max 60 1.5 Unit % s pF pF pF µW kOhm pF pF fF
Cm
Motional capacitance
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7. Memory Map
The AT91SAM7A1 microcontroller memory space is 4 Gbytes. When the AT91SAM7A1D microcontroller is reset, the ARM core is in reboot mode to access the external memory (usually a ROM) on NCS0 at address 0x00000000. The internal RAM is located at address 0x00300000. When the software execute the remap command (write 1 in RCB bit in AMC_RCR register), the internal RAM is automatically located at address 0x00000000 and the external memory accessed on the NCS0 is located in the memory space from 0x40000000 to 0x7FFFFFFF depending on the AMC_CSR0 register in the Advanced Memory Controller, then the chip is in remap mode.
7.1
Reboot Mode
Table 7-1. Internal Memory (Reboot Mode)
Size 2 Mbytes 0xFFE00000 0xFFDFFFFF 4090 Mbytes 0x00400000 0x003FFFFF 0x00300000 0x002FFFFF 1 Mbytes 0x00200000 0x001FFFFF 1 Mbytes 0x00100000 0x000FFFFF 1 Mbytes 0x00000000 External memory on NCS0 No Reserved Yes Reserved No 1 Mbytes (4 Kbytes repeated 256 times) 4 Kbytes internal RAM No Reserved Yes Application Peripheral devices Abort Generation No
Memory Space 0xFFFFFFFF
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7.2
Remap Mode
Table 7-2. Internal Memory (Remap Mode)
Size 2 Mbytes 0xFFE00000 0xFFDFFFFF 2046 Mbytes 0x80000000 0x7FFFFFFF 1024 Mbytes 0x40000000 0x3FFFFFFF 1021 Mbytes 0x00300000 0x002FFFFF 2 Mbytes 0x00100000 0x000FFFFF 0x00000000 1 Mbytes (4 Kbytes repeated 256 times) 4 Kbytes internal RAM No Reserved No Reserved Yes Up to 6 external memories repeated within the page size programmed in the AMC_CSRx register Yes, outside of defined page size in the AMC_CSRx Reserved Yes Application Peripheral devices Abort Generation No
Memory Space 0xFFFFFFFF
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7.3 External Memories
The AT91SAM7A1 external memories can be relocated in the address space from 0x40000000 to 0x7FFFFFFF. The configuration of the base address and the page size of each EBI chip select line (NCS[3:0], CS[7:6]) is done through the Advanced Memory Controller (AMC) registers. It is to be noted that the two most significant bits of the base address are fixed to 01b allocating these memories in the second of the four Gbytes memory spaces. The maximum external memory space is 16 Mbytes (i.e. CS[7:6] used as address lines). Table 7-3. External Memory
Size Up to 1 Mbytes 0x(01XXb)XX00000 0x(01XXb)X1FFFFF Up to 2 Mbytes 0x(01XXb)XX00000 0x(01XXb)X3FFFFF Up to 4 Mbytes 0x(01XXb)XX00000 0x(01XXb)X3FFFFF Up to 4 Mbytes 0x(01XXb)XX00000 0x(01XXb)X3FFFFF Up to 4 Mbytes 0x(01XXb)XX00000 0x(01XXb)X3FFFFF Up to 4 Mbytes 0x(01XXb)XX00000 External memory on NCS0 External memory on NCS1 External memory on NCS2 External memory on NCS3 External memory on CS6 Application External memory on CS7
Memory Space 0x(01XXb)XXFFFFF
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7.4
Peripheral Resources
The peripheral modules of the AT91SAM7A1 embedded system are listed in Table 7-4. Table 7-4.
Peripheral AMC SFM Watchdog Watch Timer USART0
Peripheral Resources
Address 0xFFE00000 0xFFF00000 0xFFFA0000 0xFFFA4000 0xFFFA8000 IRQ source 2 3 4 TX: Ch1 RX: Ch2 PDC Channel RX: Ch0 3 PIO
USART1
0xFFFAC000
5 TX: Ch3 RX: Ch4
3
USART2
0xFFFB0000
6 TX: Ch5 RX: Ch6
3
SPI ADC0 (8-channel 10-bit)
0xFFFB4000 0xFFFC0000
7 TX: Ch7 10 12 Ch10 Ch8 Ch9 -
7
GPT0 (3 Channels)
0xFFFC8000
13 14
9
PWM (4 Channels) CAN (16 Channels) UPIO Capture CAPT0 Capture CAPT1 Simple Timer ST0 Simple Timer ST1 CM PMC PDC GIC
0xFFFD0000 0xFFFD4000 0xFFFD8000 0xFFFDC000 0xFFFE0000 0xFFFE4000 0xFFFE8000 0xFFFEC000 0xFFFF4000 0xFFFF8000 0xFFFFF000
16 20 21 22 23 24 25 -
4
19 1 1
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8. Power Management Block
In order to reduce power consumption, the AT91SAM7A1 microcontroller provides a power management block in some peripherals used to switch on/off the peripheral clocks (peripheral and PIO block). This function is independent of the Power Management Controller (peripheral) used to switch on/off the ARM7TDMI core and the PDC clocks. Three registers are provided: • PERIPHERAL_ECR (at peripheral offset 0x0050) enables the clock • PERIPHERAL_DCR (at peripheral offset 0x0054) disables the clock • PERIPHERAL_PMSR (at peripheral offset 0x0058) gives the status of the clock Two bits are provided in these registers : • Bit 0 controls the PIO block of the peripheral • Bit 1 controls the peripheral function When the peripheral clock (and/or the PIO clock) is disabled, the clock is immediately stopped. When the clock is re-enabled, the peripheral controller (and/or the PIO controller) resumes action where it left off. The interrupt registers are common to the peripheral controller and its PIO controller. The clock on the interrupt registers and its associated logic are stopped only if both the peripheral controller clock and the PIO controller clock are stopped. Table 8-1 lists the different power management blocks. Table 8-1.
Module AMC SFM Watchdog Watch Timer USART0 USART1 USART2 SPI ADC0 GPT0 TC0 GPT0 TC1 GPT0 TC2
AT91SAM7A1 Power Managment Blocks
Power Management Block Present No No No No Yes Yes Yes Yes Yes Yes Yes Yes Module PWM CAN UPIO CAPT0 CAPT1 Simple Timer ST0 Simple Timer ST1 CM PMC PDC GIC Power Management Block Present Yes Yes Yes Yes Yes Yes Yes No Yes No No
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9. PIO Controller Block
Figure 9-1. PIO Controller Block Diagram
1 0 0 1 0
Pad Output Enable
Peripheral_OSR Peripheral Output Enable
Pad Output Peripheral_MDSR
1 0
Peripheral_PSR
Peripheral_SODR Peripheral Output
Peripheral_PSR Pad Input
0
0
Peripheral Input
1
Synchro Resynch Peripheral Input Peripheral_PDSR Event Trig Peripheral_SR
Peripheral_IMR Peripheral Controller Peripheral_int
To match different applications, the AT91SAM7A1 peripherals have their dedicated pins multiplexed with general-purpose I/O pins (MPIO). Table 9-1 lists the modules sharing the dedicated pins with MPIOs. Table 9-1.
Module AMC SFM Watchdog Watch Timer USART0 USART1 USART2
PIO Block Multiplexing
PIO Block Present No No No No Yes Yes Yes Number of MPIO 3 3 3 Name of PIO Lines TXD0, RXD0, SCK0 TXD1, RXD1, SCK1 TXD2, RXD2, SCK2
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Table 9-1.
Module SPI ADC0 GPT0 TC0 GPT0 TC1 GPT0 TC2 PWM CAN UPIO CAPT0 CAPT1 Simple Timer ST0 Simple Timer ST1 CM PMC PDC GIC
PIO Block Multiplexing (Continued)
PIO Block Present Yes No Yes Yes Yes Yes No Yes Yes Yes No No No No No No Number of MPIO 7 3 3 3 4 18 1 1 Name of PIO Lines MISO, MOSI, SPCK, NPCS[3:0] TIOA0, TIOB0, TCLK0 TIOA1, TIOB1, TCLK1 TIOA2, TIOB2, TCLK2 PWM[3:0] UPIO[17:0] CAPT0 CAPT1 -
Each PIO block in the peripheral is controlled through the peripheral interface. The PIO block clock is enabled/disabled by the peripheral Power Management Controller (see Table 7-4 on page 22).
9.1
Multiplexed I/O Lines
All I/O lines are multiplexed with an I/O signal of the peripheral. After reset, the pin is controlled by the peripheral PIO controller. When a peripheral signal is not used in an application, the corresponding pin can be used as a parallel I/O. Each parallel I/O line is bi-directional, whether the peripheral defines the signal as input or output. Figure 9-1 on page 24 shows the multiplexing of the peripheral signals with the PIO controller signal. Each pin of the peripheral can be independently controlled using the Peripheral_PER (PIO Enable) and Peripheral_PDR (PIO Disable) registers. The Peripheral_PSR (PIO Status) indicates whether the pin is controlled by the peripheral or by the PIO controller block.
9.1.1
Output Selection The user can select the direction of each individual I/O signal (input or output) using the Peripheral_OER (Output Enable) and Peripheral_ODR (Output Disable) registers. The output status of the I/O signal can be read in the Peripheral_OSR (Output Status) register. The direction defined has effect only if the pin is configured to be controlled by the PIO controller block.
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9.1.2
I/O Levels Each pin can be configured to be independently driven high or low. The level is defined in different ways, according to the following conditions. If a pin is controlled by the PIO controller block and is defined as an output (see Output Selection above), the level is programmed using the Peripheral_SODR (Set Output Data) and Peripheral_CODR (Clear Output Data) registers. In this case, the programmed value can be read in the Peripheral_ODSR (Output Data Status) register. If a pin is controlled by the PIO controller block and is not defined as an output, the level is determined by the external circuit. If a pin is not controlled by the PIO controller block, the state of the pin is defined by the Peripheral controller. In all cases, the level on the pin can be read in the Peripheral_PDSR (Pin Data Status) register.
9.1.3
Interrupts Each PIO controller block also provides an internal interrupt signal shared with the peripheral interrupt. Each PIO can be programmed to generate an interrupt when a level change occurs. This is controlled by the Peripheral_IER (Interrupt Enable) and Peripheral_IDR (Interrupt Disable) registers which enable/disable the I/O interrupt (and the peripheral interrupts) by setting/clearing the corresponding bit in the Peripheral_IMR. When a change in level occurs, the corresponding bit in the Peripheral_SR (Interrupt Status) register is set whether the pin is used as a PIO or a peripheral signal and whether it is defined as input or output. If the corresponding interrupt in Peripheral_IMR (Interrupt Mask) register is enabled, the PIO interrupt is asserted. The PIO interrupt is cleared when: • a write access is performed on the Peripheral_CISR register (with the corresponding bit set at a logical 1) or • a read access is performed in the Peripheral_SR register (if no Peripheral_CISR register is present in the peripheral)
9.1.4
User Interface Each individual MPIO is associated with a bit position in the PIO controller user interface registers. Each of these registers is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero.
9.1.5
Open Drain/Push-pull Output The PIO can either be configured as an open drain output (only drives a low level) or as a push pull output (drives high and low levels). When the PIO is configured as open drain (multidriver), an external pull-up is necessary to guarantee a logic level (logical one) when the pin is not being driven. The PERIPHERAL_MDER (Multidriver Enable) and PERIPHERAL_MDDR (Multidriver Disable) registers control this option and respectively configure the I/O as open drain or push pull. The multidriver option can be selected whether the I/O pin is controlled by the PIO controller or the peripheral controller. Bits at logical one in the PERIPHERAL_MDSR (Multidriver Status) indicate pins configured as open drain.
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10. Advanced Memory Controller (AMC)
The AT91SAM7A1 microcontroller is provided with an Advanced Memory Controller allowing the software to configure external and internal memory mapping (at boot level). The external 16-bit data bus interface is called the External Bus Interface (EBI) and is the physical layer used to connect external devices to the AT91SAM7A1 microcontroller. Subsequently, the EBI generates the signals which control the access to the external memory or peripheral devices. The EBI is fully programmable through the Advanced Memory Controller (AMC) and can address up to 16 Mbytes. It has up to six chip selects and a 22-bit address bus. The AT91SAM7A1 can only boot on a 16-bit external memory device connected to the NCS0 signal. All the other chip select lines (NCS[3:1] and CS[7:6]) can be configured to access 8- or 16-bit memory devices.
10.1
Boot on NCS0
By default, the AT91SAM7A1 boots on a 16-bit external memory device connected on NCS0. At reset, access through NCS0 is configured as follows (in the AMC_CSR0 register): • 8 wait states (WSE = 1, NWS = 7 in AMC_CSR0) • 16-bit data bus width (DBW[1:0] = 01b) • Base address is at 0x00000000 • Byte access type is configured as Byte Write Access, BAT = 0 • The number of data float time is 0 (TDF[2:0] = 000b) • The EBI is configured in normal read protocol (DRP = 0 in AMC_MCR register) The user can modify the chip select 0 configuration, programming the AMC_CSR0 with exact boot memory characteristics. The base address becomes effective after the remap command (set to a logical 1 the RCB in AMC_RCR), but the other parameters are changed immediately after the write access in the AMC_CSR0 register.
10.2
External Memory Mapping
The memory map associates the internal 32-bit address space with the external 22-bit address bus. The memory map is defined by programming the base address and page size of the external memories. If the physical memory device is smaller than the programmed page size, it wraps around and appears to be repeated within the page. The AMC correctly handles any valid access to the memory device within the page. In the event of an access request to an address outside any programmed page, an abort signal is generated. Two types of abort are possible: instruction prefetch abort and data abort. The corresponding exception vector addresses are respectively 0x0000000C and 0x00000010. It is up to the system programmer to program the error handling routine to use in case of an abort (see the ARM7TDMI datasheet for further information). The AT91SAM7A1 microcontroller must be wired so the NCS0 accesses a non volatile 16-bit memory as shown in Figure 10-6 on page 32 or Figure 10-7 on page 32.
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10.3
10.3.1
External Memory Device Connection
Data Bus Width Each chip select can access 8- or 16-bit data bus devices. This option is selected by the DBW[1:0] bits in the corresponding AMC_CSRx register. NCS0 is used at reset to access a 16-bit memory device (DBW[1:0] = 01b).
10.3.2
Byte Select or Byte Write Access Each chip select can operate with one of two different types of write access by setting the Byte Access Type (BAT) bit in the corresponding AMC_CSRx register. • Byte select access (BAT = 1): Uses one write signal, one read signal, and two signals to select upper and/or lower memory bank in a 16-bit memory. Typically used with 16-bit memories, except when the user wants to connect 2 x 8-bit memories in parallel. In this case, this is considered a 16-bit memory by the AMC. • Byte write access (BAT = 0): Uses two byte write signals to select two different 8-bit devices and a single read signal. This mode is used at reset to boot on the memory connected on NCS0 (Chip Select 0). Typically used with 2 x 8-bit memories.
10.3.3
Byte Select Access (BAT = 1) This mode is selected by setting the bit BAT to 1 in AMC_CSRx registers and is typically used to connect 16-bit devices in a memory page, except when user wants to connect 2 x 8-bit devices in parallel, in that case seen by the AMC this is a 16-bit memory page. Users can use the upper/lower bank selection signals NUB and NLB to have either an 8-bit or a 16-bit access.
10.3.3.1
16-bit Access Device Connection A typical 16-bit memory (e.g., Flash memory) device connection with 16-bit access is shown in Figure 10-1. • The signal A0/NLB is not used • The signal NWR1/NUB is not used • The signal NWR0/NWE is used as NWE and enables half-word writes. • The signal NRD/NOE is used as NOE and enables half-word reads. Figure 10-1. EBI Connection for External 16-bit Memory Device, 16-bit Access Only
EBI 16-bit External Memory
D[15:0] A[21:1] NWE NOE N CS
D[15:0] A[20:0] NWE NOE NCE
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In the same configuration as above, Figure 10-2 shows how to connect 2 x 8-bit memory devices with 16-bit access. Figure 10-2. EBI Connection for 2 x 8-bit Memory Devices, 16-bit Access Only
EBI 8-bit External Memory (LSB)
D[15:0] A[21:1] NWE NOE NCS
D[15:0] D[7:0]
D[7:0] A[20:0] NWE NOE NCE
8-bit External Memory (MSB)
D[15:8] D[7:0] A[20:0] NWE NOE NCE
10.3.3.2
8-bit or 16-bit Access Device Connection A typical 16-bit memory (e.g., SRAM) device connection with 8-bit or 16-bit access is shown in Figure 10-3. The 16-bit memory allows upper/lower bank selection and NUB, NLB are used to have an 8-bit access. • The signal A0/NLB is used as NLB and enables the lower byte for both read and write operations. • The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write operations. • The signal NWR0/NWE is used as NWE and enables half-word or byte writes. • The signal NRD/NOE is used as NOE and enables half-word and byte reads.
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Figure 10-3. EBI Connection for External 16-bit Memory Devices, 8-bit or 16-bit Access
EBI 16-bit External Memory D[15:0] A[20:0] NLB NUB NWE NOE NCE
D[15:0] A[21:1] NLB NUB NWE NOE NCS
10.3.4
Byte Write Access (BAT = 0) This mode is selected by setting the bit BAT to 0 in AMC_CSRx registers and is typically used to connect 2 x 8-bit devices as a 16-bit memory page. This is the mode selected at reset on NCS0. In this mode, users can interface the EBI with one or two 8-bit memories. If the EBI is interfaced with two 8-bit memories, the users have the choice of either an 8-bit or a 16-bit access.
10.3.4.1
8-bit Access Device Connection A typical 8-bit memory device connection with 8-bit access is shown in Figure 10-4. DBW[1:0] should be for a 8-bit-data bus width and only NWR0 is used • The signal A0/NLB is used as A0. • The signal NWR1/NUB is not used. • The signal NWR0/NWE is used as NWR0 and enables lower byte writes. • The signal NRD/NOE is used as NRD and enables byte reads. Figure 10-4. EBI Connection for External 8-bit Memory Device, 8-bit Access Only
EBI 8-bit External Memory
D[7:0] A[21:0] NWR0 NRD NCS
D[7:0] A[21:0] NWE NOE NCE
10.3.4.2
8-bit or 16-bit Access Device Connection A typical 2 x 8-bit memory device connection with 8-bit or 16-bit access is shown in Figure 105. • The signal A0/NLB is not used. • The signal NWR1/NUB is used as NWR1 and enables upper byte writes.
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• The signal NWR0/NWE is used as NWR0 and enables lower byte writes. • The signal NRD/NOE is used as NRD and enables half-word and byte reads. Figure 10-5. EBI Connection for External 2x8-bit Memory Devices, 8-bit or 16-bit Access
EBI 8-Bit External Memory (LSB) D[15:0] D[15:0] A[21:1] NWR0 NRD NCS NWR1 8-Bit External Memory (MSB) D[7:0] D[7:0] A[20:0] NWE NOE NCE
D[15:8] D[7:0] A[20:0] NWE NOE NCE
10.3.4.3
16-bit Access Device Connection A typical 16-bit memory device connection with 16-bit access only is shown in Figure 10-6. In this case, the AT91SAM7A1 is in byte write access mode and boots on the 16-bit memory. NWR1 and NWR0 are used by the EBI but only NWR0 is used by the memory, enabling a 16bit access. The correct mode for this configuration is byte select access and should be set in the boot. • The signal A0/NLB is not used. • The signal NWR1/NUB is not used. • The signal NWR0/NWE is used as NWR0 and enables half-word writes. • The signal NRD/NOE is used as NRD and enables half-word and byte reads.
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Figure 10-6. EBI Connection for External 16-bit Memory Devices, 16-bit Access Only
EBI 16-bit External Memory
D[15:0] A[21:1] NWR0 NRD NCS
D[15:0] A[20:0] NWE NOE NCE
If users want to boot on a RAM memory for debug purposes, the RAM memory should be connected the same way as a Flash memory (NUB and NLB of the RAM memory connected to the ground) to emulate a pure 16-bit Flash memory as shown in Figure 10-7. Figure 10-7. EBI Connected to an External 16-bit RAM Memory Device, 16-bit Access Only Used as a Boot Memory for Debug Purpose
EBI 16-bit RAM External Memory NLB NUB D[15:0] A[20:0] NWE NOE NCE
D[15:0] A[21:1] NWR0 NRD NCS
10.4
External Bus Interface Timings
Simple read and write access cycles are explained in detail where read access can be done through two modes: • Standard read protocol • Early read protocol which increases the EBI performance for read access. The EBI can automatically insert wait states during the external access cycles. These wait states are applied within the actual access cycle. Data float wait states can also be inserted and applied between cycles. Data float wait states depend on the previous access.
10.4.1 10.4.1.1
Read Access Standard Read Protocol Standard read protocol (default read mode) implements a read cycle in which NRD/NOE is active during the second half of the read cycle. The first half of the read cycle allows time to ensure completion of the previous access, as well as the output of address and NCS before the read cycle begins.
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During a standard read protocol external memory access, NCS is set low and address is valid at the beginning of the access while NRD/NOE goes low only in the second half the read cycle to avoid bus conflict. Figure 10-8. Standard Read Address
Address Address Valid
NCS
NOE/NRD
10.4.1.2
Early Read Protocol Early read protocol provides more memory access time for a read access by asserting NRD at the beginning of the read cycle. This mode is selected by setting the bit DRP in AMC_MCR register. In the case of successive read cycles in the same memory, NRD remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol can allow a faster timing of the EBI to be used. However, an extra data float wait state is required in some cases to avoid contentions on the external bus. Figure 10-9. Early Read Address
Address Address Valid
NCS
NOE/NRD
10.4.2
Write Access In a write access cycle, NWE (or NWR0, NWR1) is active during the second half of the write cycle. The first half of the write cycle allows time to ensure completion of the previous access as well as the address and NCS set up time before NWE (or NWR0, NWR1) is asserted. During an external write memory access, NCS is set low and address is valid at the beginning of the access while NWE (or NWR0, NWR1) goes low only in the second half of the write cycle to avoid bus conflict. NWE (or NWR0, NWR1) goes high at the end of the write cycle unless wait states are asserted.
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Figure 10-10. Write Access
Address
Address Valid
NCS
NWE
10.4.3
Wait States The EBI can automatically insert wait states during the external access cycles. These wait states are applied within the actual access cycle. Different types of wait states are possible: • Standard wait states • Data float wait states • External wait states
10.4.3.1
Standard Wait State Each chip select line can be programmed to insert one or more wait states during an external access. This is done by setting the WSE bit in the corresponding AMC_CSRx register. The number of cycles to insert is programmed in the NWS[2:0] field in the same register. Wait states are inserted within cycles and delay the read and write access cycles. • Wait state with read cycle The read cycle is delayed one cycle for each wait state programmed. In early mode, NOE/NRD goes low at the start of the read cycle. In standard mode, this signal goes low at the half of the first cycle. Figure 10-11. Read Cycle with One Wait State
Address
Address Valid
NCS
NOE/NRD
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Figure 10-12. Read Cycle with Two Wait States
Address Address Valid
NCS
NOE/NRD
• Wait state with write cycle The write cycle is delayed one cycle for each wait state programmed. NWE (or NWR0, NWR1) goes high one half cycle before the end of the write cycle. Figure 10-13. Write Cycle with One Wait State
Address
Address Valid
NCS
NWE
Figure 10-14. Write Cycle with Two Wait States
Address Address Valid
NCS
NOE/NRD
10.4.3.2
Data Float Wait State Data float wait states are added to avoid data bus conflict. After a read access, data float wait states allow more time for the external memory to release the data bus. After a write access, data float wait states allow more time for the EBI to release the data bus. The Data Float Output time (tDF) for each external memory device is programmed in the TDF field of the AMC_CSRx register for the corresponding chip select. The value (0 - 7 clock cycles) indicates the number of data float wait states to be inserted. Data float wait states are asserted between accesses.
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Data float wait state insertion depends on the previous access. Table 10-1 describes the data float wait states applied between external access cycles. Table 10-1. Data Float States Applied
Number of Data Float Wait States Applied Previous Access NCSx Read NCSx Read NCSx Write NCSx Write NCSx Read NCSx Read NCSx Write NCSx Write Next Access NCSx Read NCSx Write NCSx Read NCSx Write NCSy Read NCSy Write NCSy Read NCSy Write Early Read Mode 0 nTDF 1 0 Max(1, nTDFx) Max(1, nTDFx) 1 1 Standard Read Mode 0 nTDF 0 0 Max(1, nTDFx) Max(1, nTDFx) 1 1
Table 10-2.
Previous Access NCSx Read NCSx Read NCSx Write NCSx Write NCSx Read NCSx Read NCSx Write NCSx Write
Examples
Early Read Mode Next Access NCSx Read NCSx Write NCSx Read NCSx Write NCSy Read NCSy Write NCSy Read NCSy Write TDFx = 0 0 0 1 0 1 1 1 1 TDFx = 1 0 1 1 0 1 1 1 1 TDFx = 2 0 2 1 0 2 2 1 1 TDFx = 3 0 3 1 0 3 3 1 1 TDFx = 0 0 0 0 0 1 1 1 1 Standard Read Mode TDFx = 1 0 1 0 0 1 1 1 1 TDFx = 2 0 2 0 0 2 2 1 1 TDFx = 3 0 3 0 0 3 3 1 1
Illustrations from Figure 10-15 on page 37 to Figure 10-29 on page 41 give a complete description of how data float wait states apply.
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Figure 10-15. Read and Write Access on Different Chip Select with NTDF = 0 or 1
Read Mem 1 ADDRESS NCS1 NCS2 NOE/NRD NWE Data Read Mem 1 Write Mem 2 Address 1 Data Float Write Mem 2 Address 2 Data Float
Figure 10-16. Read and Write Access on Different Chip Select with NTDF = 2
NTDF = 2 Read Mem 1 ADDRESS NCS1 NCS2 NOE/NRD NWE Data Read Mem 1 Write Mem 2 Address 1 Data Float Data Float Write Mem 2 Address 2 Data Float
Figure 10-17. Standard Read and Write Access on the Same Chip Select with NTDF = 2
Read ADDRESS NCS NOE/NRD NWE Data Read Data 1 Write Data 2 Address 1 Data Float Data Float Write Address 2 Data Float
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Figure 10-18. Sequential Early Read Access on the Same Chip Select with One Wait State
Read ADDRESS NCS NOE/NRD Data Data 1 Data 2 Address 1 Write Address 2 Data Float
Figure 10-19. Sequential Early Read Access on the Same Chip Select with No Wait State
Read ADDRESS NCS NOE/NRD Data Data1 Data 2 Data 3 Address 1 Read Address 2 Read Address 3 Data Float
Figure 10-20. Sequential Read Access on Different Chip Select with NTDF = 2
NTDF = 2 Read Mem 1 ADDRESS NCS1 NCS2 NOE/NRD Data Read Mem 1 Read Mem 2 Address 1 Data Float Data Float Read Mem 2 Address 2 Data Float
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Figure 10-21. Sequential Read Access on Different Chip Select with NTDF = 0 or 1
Read Mem 1 ADDRESS NCS1 NCS2 NOE/NRD Data Read Mem 1 Read Mem 2 Address 1 Data Float Read Mem 2 Address 2 Data Float
Figure 10-22. Sequential Standard Read Access on the Same Chip Select with One Wait State
Read ADDRESS NCS NOE/NRD Data Data1 Data 2 Address 1 Read Address 2 Data Float
Figure 10-23. Sequential Standard Read Access on the Same Chip Select with No Wait State
Read ADDRESS NCS NOE/NRD Data Data 1 Data 2 Data 3 Address 1 Read Address 2 Read Address 3 Data Float
Figure 10-24. Sequential Write Access on the Same Chip Select with One Wait State
Read ADDRESS NCS NWE Data Data 1 Data 2 Address 1 Write Address 2 Data Float
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Figure 10-25. Sequential Write Access on the Same Chip Select with No Wait State
Write ADDRESS NCS NWE Data Data 1 Data 2 Data 3 Address 1 Write Address 2 Write Address 3 Data Float
Figure 10-26. Sequential Write Access on Different Chip Select
Write Mem 1 ADDRESS NCS1 NCS2 NWE Data Write Mem 1 Write Mem 2 Address 1 Data Float Write Mem 2 Address 2 Data Float
Figure 10-27. Write and Early Read on the Same Chip Select
Write ADDRESS NCS NOE/NRD NWE Data Write Data 1 Read Data 2 Address 1 Data Float Read Address 2 Data Float
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Figure 10-28. Write and Read on Different Chip Select
Write Mem 1 ADDRESS NCS1 NCS2 NOE/NRD NWE Data Write Mem 1 Read Mem 2 Address 1 Data Float Read Mem 2 Address 2 Data Float
Figure 10-29. Write and Standard Read on the Same Chip Select
Write ADDRESS NCS NOE/NRD NWE Data Write Data 1 Read Data 2 Address 1 Read Address 2 Data Float
10.4.3.3
External Wait States The NWAIT input can be used to add wait states at any time. The NWAIT signal is active low and is detected on the rising edge of the CORECLK signal. If the NWAIT signal is active on the rising edge of the CORECLK signal, the EBI adds a wait state and does not change either the output signal or its internal counters and state. When the NWAIT signal is released, the EBI finishes the access sequence after a minimum of two CORECLK periods and a maximum of three CORECLK periods (the positive edge of the NWAIT signal is internally resynchronized with the falling edge of the CORECLK signal and the ARM core finishes the access cycle two CORECLK periods after it has been sampled high with the falling edge of CORECLK). In case of an external NWAIT, the number of internal wait states NWS must be calculated as in the equation below to verify the conditions in Table 10-5, “Timings for External NWAIT,” on page 47. t WSCSAWSL < ( 0.5 + NWS ) × ( t CYCLE – load_delay ) Case 1: No internal wait states (NWS = 0) External NWAIT must be activated before the first rising edge of CORECLK (Figure 10-31) else it is not detected (Figure 10-32).
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Figure 10-30. External Accesses with 0 Internal Wait States and no NWAIT
CORECLK
NCS
Address
NOE/NRD
NWE
NWAIT
Figure 10-31. External Accesses with 0 Internal Wait States and NWAIT Detected
CORECLK
NCS
Address
NOE/NRD
NWE
NWAIT
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Figure 10-32. External Accesses with 0 Internal Wait States and NWAIT Not Detected
CORECLK
NCS
Address
NOE/NRD
NWE
NWAIT
Case 2: With internal wait states (NWS ≥ 1) As no CORECLK output signal is provided on the device, NWAIT timings are given relative to the address change and chip select activation. At high frequencies, it may be necessary to add internal wait states in order to allow an external device to decode the chip select and address lines and to drive the NWAIT input correctly (tWSADCWSL, tWSCSAWSL and tWSPL must be respected). Figure 10-33. External Accesses with One Internal Wait State and One NWAIT
CORECLK
NCS
Address
NOE/NRD
NWE
NWAIT
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Figure 10-34. External Accesses with x Internal Wait States and y NWAIT
CORECLK
NCS
Address
NOE/NRD
NWE
NWAIT
10.4.4
Timings The following tables show the minimum and maximum timings for external memory read/write cycles (valid for the recommended operating conditions) for a capacitive load of 15 pF, 40 pF and 60 pF.
Table 10-3.
Read Access trADCRDV2
Timings for Read Access
Load = 15pf Description Address change to read data valid (read/write memory, 0 wait state, standard read) Address change to read data valid (all other cases) Min Max tCYCLE 19.2ns (1 + NWS) * tCYCLE 11.0ns (1 + NWS) * tCYCLE 10.5ns (0.5 + NWS) * tCYCLE 11.5ns (1 + NWS) * tCYCLE 11.6ns (1 + NWS) * tCYCLE 18.5ns (1 + NWS) * tCYCLE 12.0ns Min Load = 40pf Max tCYCLE 22.9ns (1 + NWS) * tCYCLE 12.9ns (1 + NWS) * tCYCLE 12.4ns (0.5 + NWS) * tCYCLE 13.4ns (1 + NWS) * tCYCLE 13.5ns (1 + NWS) * tCYCLE 22.2ns (1 + NWS) * tCYCLE 13.8ns Min Load = 60pf Max tCYCLE 25.8ns (1 + NWS) * tCYCLE 14.4ns (1 + NWS) * tCYCLE 13.9ns (0.5 + NWS) * tCYCLE 14.9ns (1 + NWS) * tCYCLE 15.0ns (1 + NWS) * tCYCLE 25.1ns (1 + NWS) * tCYCLE 15.3ns
trADCRDV1
trCSLRDV
Chip select low to read data valid
trOELRDV1
Output enable low to read data valid (standard read) Output enable low to read data valid (early read) Byte select low to read data valid (read/write memory, 0 wait state, standard read) Byte select low to read data valid (all other cases)
trOELRDV2
trBSLRDV2
trBSLRDV1
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Table 10-3.
Read Access trDH
Timings for Read Access (Continued)
Load = 15pf Description Data hold time from address change/NCS high/NOE high Data Hi-Z to output enable low (previous is a write cycle, standard read) Data Hi-Z to output enable low (previous is a write cycle, early read) Data Hi-Z to chip select low (previous is a write cycle, standard read) Address/CS/NUB/NLB hold time from read high Min 0 Max Min 0 Load = 40pf Max Min 0 Load = 60pf Max
trDHZOEL1
-1.5ns 0.5 * tCYCLE 1.5ns 0.5 * tCYCLE 2.8ns 4.8ns
-3.4ns 0.5 * tCYCLE 3.4ns 0.5 * tCYCLE 4.7ns 7.0ns
-4.8ns 0.5 * tCYCLE 4.8ns 0.5 * tCYCLE 6.1ns 8.8ns
trrDHZOEL2
trDHZCSL
trADHRH
Figure 10-35. Read Access Waveform
trADCRDV 1/2 ADDRESS Address Valid trCSLRDV NCSx trDHZCSL trDH
CSx
trBSLRDV 1/2 NUB/NLB trOELRDV1 (standard) trOELRDV2 (early) NOE/NRD trDHZOEL2 trDHZOEL1 NWE trADHRH
D[0:15]
Data Out
Data In Valid
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Table 10-4.
Write Access twADSWL
Timings for Write Access
Load = 15pf Description Address/NCS/NUB/NLB setup time to write low Write pulse low (one or more wait states) Write pulse low (0 wait state) Data setup time to write high (one or more wait states) Data setup time to write high (0 Wait State) Address/CS/NUB/NLB hold time from write high Output enable high (previous is a read cycle) to data drive Chip select high (previous is a read cycle) to data drive Data hold time from write high (one or more wait states) Data hold time from write high (0 wait state) Min 0.5 * tCYCLE 2.0ns (1 + NWS) * tCYCLE 1.6ns 0.5 * tCYCLE 2.1ns (1 + NWS) * tCYCLE 3.6ns 0.5 * tCYCLE 4.1ns 2.6ns 0.5 * tCYCLE 5.7ns 1.5 * tCYCLE 4.3ns tCYCLE 3.8ns 0.5 * tCYCLE 4.1ns Max Load = 40pf Min 0.5 * tCYCLE 2.0ns (1 + NWS) * tCYCLE 1.6ns 0.5 * tCYCLE 2.1ns (1 + NWS) * tCYCLE 5.5ns 0.5 * tCYCLE 6.0ns 3.3ns 0.5 * tCYCLE 7.5ns 1.5 * tCYCLE 6.2ns tCYCLE 5.6ns 0.5 * tCYCLE 5.9ns Max Load = 60pf Min 0.5 * tCYCLE 2.0ns (1 + NWS) * tCYCLE 1.7ns 0.5 * tCYCLE 2.2ns (1 + NWS) * tCYCLE 7.0ns 0.5 * tCYCLE 7.5ns 3.9ns 0.5 * tCYCLE 8.9ns 1.5 * tCYCLE 7.6ns tCYCLE 7.0ns 0.5 * tCYCLE 7.4ns Max
twWPL1
twWPL2
twDSWH1
twDSWH2 twADHWH twOEHDD twCSHDD twDHWH1 twDHWH2
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Figure 10-36. Write Access Waveform
ADDRESS twADHWH 1/2 twADSWL NUB/NLB (Byte Select) NCSx (Write Select) twWPL 1/2 NWE (Byte Select) NW0/NW1 (Write Select) twOEHDD NOE twCSHDD NCSy twDSWH 1/2 twDHWH 1/2
D [15:0]
Data Out Valid
Table 10-5.
Write Access twSADCWSL
Timings for External NWAIT
Load = 15pf Description Address/NUB/NLB change to NWAIT active Chip select active to NWAIT active NWAIT pulse NWAIT inactive to address/NUB/NLB/chip select change tCYCLE 2 * tCYCLE 3 * tCYCLE Min Max (0.5 + NWS) * tCYCLE 16.8ns (0.5 + NWS) * tCYCLE 15.8ns tCYCLE 2 * tCYCLE 3 * tCYCLE Min Load = 40pf Max (0.5 + NWS) * tCYCLE 23.5ns (0.5 + NWS) * tCYCLE 22.5ns tCYCLE 2 * tCYCLE 3 * tCYCLE Min Load = 60pf Max (0.5 + NWS) * tCYCLE 26.9ns (0.5 + NWS) * tCYCLE 25.8ns
twSCSAWSL twSPL twSWSHADC
Figure 10-37. External NWAIT Waveform
twSADCWSL ADDRESS twSWSHADC
NUB/NLB (Byte Select) NCS
twSCSAWSL
twSPL NWAIT
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10.4.4.1
EBI Timings Calculation Table 10-6 and Table 10-7 show estimated timings relative to operating condition limits (worst case: VDD3V = 3.0V, Temp = +85°C) with a 40 pF load on address and control lines except for chip select lines with a 15 pF load. Table 10-6.
Symbol EBI5 EBI24 EBI1 EBI2 EBI6 EBI7
General-purpose EBI Signals
Parameter CORECLK falling to NCS, CS active CORECLK falling to NCS, CS inactive CORECLK falling to A[21:0] active CORECLK falling to A[21:0] inactive NWAIT setup before CORECLK rising NWAIT hold after CORECLK rising Min 4.57 4.52 5.62 5.87 4.32 0 Max 11.44 11.45 14.28 13.33 Units ns ns ns ns ns ns
Table 10-7.
Symbol EBI8 EBI9 EBI12 EBI10 EBI11 EBI20 EBI21 EBI22 EBI19
EBI Write Signals
Parameter CORECLK rising to NWR active (no wait) CORECLK rising to NWR active (wait) CORECLK rising to D[15:0] out valid CORECLK falling to NWR inactive (no wait) CORECLK rising to NWR inactive (wait) NWR high to A[21:1], NCS, CS changes (wait states) Data out valid before NWR high Data out valid after NWR high NWR high to A[21:1], NCS, CS changes (no wait states) Min 5.25 5.25 5.90 5.15 5.22 3.38 0.5 x tCP - 6.00 0.5 x tCP - 5.90 3.30 9.53 Max 13.29 13.29 17.76 13.08 12.75 9.53 Units ns ns ns ns ns ns ns ns ns
Table 10-8.
Symbol EBI25 EBI26 EBI13 EBI23 EBI14 EBI15 EBI16 EBI17 EBI18 Note:
EBI Read Signals
Parameter CORECLK falling to NUB/NLB active CORECLK falling to NUB/NLB inactive CORECLK falling to NRD active (early) CORECLK falling to NRD inactive CORECLK rising to NRD active (standard) D[15:0] in setup before CORECLK falling D[15:0] in hold after CORECLK falling NRD high to A[21:1], NCS, CS changes D[15:0] hold after NRD high Min 5.05 5.38 5.82 5.67 5.67 0.00 0.00 7.02 0.00 9.21 Max 14.28 13.52 13.93 13.92 13.85 2.60 Units ns ns ns ns ns ns ns ns ns
For tCP , tCH and tCL (see ”Core Clock” on page 17).
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Figure 10-38. External Bus Interface Signals Relative to CORECLK
CORECLK EBI5 NCS EBI24
CS EBI1 A[21:0] EBI6 NWAIT EBI25 EBI7 EBI26
no wait
EBI2
wait
NUB/NLB EBI13 NOE/NRD (early) EBI14 NOE/NRD (standard) EBI15 D[15:0] read EBI8 NWE/NWR1 (no WS) EBI9 NWE/NWR1 (with WS) EBI12 D{15:0} (write) no wait wait EBI21 EBI22 EBI22 EBI10 EBI11 EBI19 EBI20 EBI16 EBI23 EBI17 EBI15
If a different load is applied, the new timing can be calculated as follows: For a high-to-low transition on the signal:
EBI Xnew = EBI X + Derating Factor × { TPDHL new + ( DTPDHL new × C new ) ] – [ TPDHL + ( DTPDHL × C ) ] } [
For a low-to-high transition on the signal:
[ EBI Xnew = EBI X + Derating Factor × { TPDLH new + ( DTPDLH new × C new ) ] – [ TPDLH + ( DTPDLH × C ) ] }
where: • Derating factor equals 1.65V in worst conditions (i.e., 3.0V @ +85°C) and 0.64 in best conditions (i.e., 3.6V @ -40°C) • TPDHL is propagation delay, high-to-low • TPDLH is propagation delay, low-to-high • DTPDHL is differential (load-dependent) propagation delay, high-to-low or high impedanceto-low
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• DTPDLH is differential (load-dependent) propagation delay, low-to-high or high impedanceto-high • CNEW is the new capacitive charge on the affected signal • C is the current capacitive charge on the signal (40 pF load for all signals except for chip select lines - 15pF -)
10.5
Advanced Memory Controller (AMC) Memory Map
AMC Memory Map(1)
Register AMC Chip Select Register 0 AMC Chip Select Register 1 AMC Chip Select Register 2 AMC Chip Select Register 3 Reserved AMC Chip Select Register 6 AMC Chip Select Register 7 AMC Remap Control Register AMC Memory Control Register Notes: Name AMC_CSR0 AMC_CSR1 AMC_CSR2 AMC_CSR3 --AMC_CSR6 AMC_CSR7 AMC_RCR AMC_MCR Access Read/Write Read/Write Read/Write Read/Write --Read/Write Read/Write Read/Write Read/Write Reset State 0x4000203D 0x48000000 0x50000000 0x58000000 --0x70000000 0x78000000 0x00000000 0x00000000
Table 10-9.
Address 0xFFE0 0000 0xFFE0 0004 0xFFE0 0008 0xFFE0 000C 0xFFE0 0010 0xFFE0 0014 0xFFE0 0018 0xFFE0 001C 0xFFE0 0020 0xFFE0 0024
1. The software must set the AMC Registers for correct operation.
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10.5.1 AMC Chip Select Register 0 Name: AMC_CSR0 Access: Read/Write Base Address: 0xFFE0 0000
31 – 23 30 – 22 BA[3:0] 15 – 7 PAGES0 14 – 6 – 13 CSEN 5 WSE 12 BAT 4 29 28 27 BA[9:4] 21 20 19 – 11 18 – 10 TDF[2:0] 2 17 – 9 16 – 8 PAGES1 0 DBW[1:0] 26 25 24
3 NWS[2:0]
1
• BA[9:0]: Base Address Bits [31:30] are set by hardware, so the base address can only be in the memory space 0x40000000-0x7FFFFFFF. The other bits contain the highest bits of the base address. If the page size is larger than 1 Mbyte, the unused bits of the base address are ignored by the AMC decoder. • CSEN: Chip Select Enable 0: Chip select is disabled. 1: Chip select is enabled. • BAT: Byte Access Type 0: Byte write access type. 1: Byte select access type. • TDF[2:0]: Data Float Output Time These bits select the number of cycles added after a memory transfer.
TDF[2:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Cycles Added 0 1 2 3 4 5 6 7
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• PAGES[1:0]: Page Size These bits select the memory page size.
PAGES[1:0] 0 0 1 1 0 1 0 1 Page Size 1 Mbytes 4 Mbytes 16 Mbytes 64 Mbytes Active Bits in Base Address 12 (31-20) 10 (31-22) 8 (31-24) 6 (31-26)
• WSE: Wait State Enable 0: Wait state generation is disabled. No wait state is inserted. 1: Wait state generation is enabled. • NWS[2:0]: Number of Wait States These bits select the number of wait states added. This field is only valid if the WSE bit is set.
NWS[2:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 WS Added 1 2 3 4 5 6 7 8
• DBW[1:0]: Data Bus Width Type of data bus selected.
DBW[1:0] 0 0 1 1 0 1 0 1 Data Bus Width Reserved 16-bit Data Bus 8-bit Data Bus Reserved
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10.5.2 AMC Chip Select Register x (x = 1..3) Name: AMC_CSRx Access: Read/Write Base Address: 0xFFE0 0004, 0xFFE0 0008, 0xFFE0 000C
31 – 23 30 – 22 BA[3:0] 15 – 7 PAGES0 14 – 6 – 13 CSEN 5 WSE 12 BAT 4 29 28 27 BA[9:4] 21 20 19 – 11 18 – 10 TDF[2:0] 2 17 – 9 16 – 8 PAGES1 0 DBW[1:0] 26 25 24
3 NWS[2:0]
1
• BA[9:0]: Base Address Bits [31:30] are set by hardware, so the base address can only be in the memory space 0x40000000-0x7FFFFFFF. The other bits contain the highest bits of the base address. If the page size is larger than 1Mbyte, the unused bits of the base address are ignored by the AMC decoder. For AMC_CSR1 default value after reset is BA[9:0] = 0x080 (i.e., default base address = 0x48000000) For AMC_CSR2 default value after reset is BA[9:0] = 0x100 (i.e., default base address = 0x50000000) For AMC_CSR3 default value after reset is BA[9:0] = 0x180 (i.e., default base address = 0x58000000) • CSEN: Chip Select Enable 0: Chip select is disabled. 1: Chip select is enabled. • BAT: Byte Access Type 0: Byte write access type. 1: Byte select access type. • TDF[2:0]: Data Float Output Time These bits select the number of cycles added after a memory transfer.
TDF[2:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Cycles Added 0 1 2 3 4 5 6 7
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• PAGES[1:0]: Page Size These bits select the memory page size.
PAGES[1:0] 0 0 1 1 0 1 0 1 Page Size 1 Mbytes 4 Mbytes 16 Mbytes 64 Mbytes Active Bits in Base Address 12 (31-20) 10 (31-22) 8 (31-24) 6 (31-26)
• WSE: Wait State Enable 0: Wait state generation is disabled. No wait state is inserted. 1: Wait state generation is enabled. • NWS[2:0]: Number of Wait States These bits select the number of wait states added. This field is only valid if the WSE bit is set.
NWS[2:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 WS Added 1 2 3 4 5 6 7 8
• DBW[1:0]: Data Bus Width Type of data bus selected.
DBW[1:0] 0 0 1 1 0 1 0 1 Data Bus Width Reserved 16-bit Data Bus 8-bit Data Bus Reserved
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10.5.3 AMC Chip Select Register x (x = 6..7) Name: AMC_CSRx Access: Read/Write Base Address: 0xFFE0 0018, 0xFFE0 001C
31 – 23 30 – 22 BA[3:0] 15 – 7 PAGES0 14 – 6 – 13 CSEN 5 WSE 12 BAT 4 29 28 27 BA[9:4] 21 20 19 – 11 18 – 10 TDF[2:0] 2 17 – 9 16 – 8 PAGES1 0 DBW[1:0] 26 25 24
3 NWS[2:0]
1
• BA[9:0]: Base Address Bits [31:30] are set by hardware, so the base address can only be in the memory space 0x40000000-0x7FFFFFFF. The other bits contain the highest bits of the base address. If the page size is larger than 1Mbyte, the unused bits of the base address are ignored by the AMC decoder. For AMC_CSR6 default value after reset is BA[9:0] = 0x300 (i.e., default base address = 0x70000000) For AMC_CSR7 default value after reset is BA[9:0] = 0x380 (i.e., default base address = 0x78000000) • CSEN: Chip Select Enable 0: Chip select is disabled. 1: Chip select is enabled. Reset value for CSEN is 0, A21/CS6 and A20/CS7 are configured as address lines after reset. • BAT: Byte Access Type 0: Byte write access type. 1: Byte select access type. • TDF[2:0]: Data Float Output Time These bits select the number of cycles added after a memory transfer.
TDF[2:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Cycles Added 0 1 2 3 4 5 6 7
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• PAGES[1:0]: Page Size These bits select the memory page size.
PAGES[1:0] 0 0 1 1 0 1 0 1 Page Size 1 Mbytes 4 Mbytes 16 Mbytes 64 Mbytes Active Bits in Base Address 12 (31-20) 10 (31-22) 8 (31-24) 6 (31-26)
• WSE: Wait State Enable 0: Wait state generation is disabled. No wait state is inserted. 1: Wait state generation is enabled. • NWS[2:0]: Number of Wait States These bits select the number of wait states added. This field is only valid if the WSE bit is set.
NWS[2:0] 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 WS Added 1 2 3 4 5 6 7 8
• DBW[1:0]: Data Bus Width Type of data bus selected.
DBW[1:0] 0 0 1 1 0 1 0 1 Data Bus Width Reserved 16-bit Data Bus 8-bit Data Bus Reserved
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10.5.4 AMC Remap Control Register Name: AMC_RCR Access: Read/Write Base Address: 0xFFE0 0020
31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 RCB
• RCB: Remap Command Bit 0: No effect 1: Performs the remapping of the two memory devices (internal RAM and external memory on NCS0). Memory map switches from 'reboot' mode to 'remap mode'. This bit is read at logical 0 in reboot mode and at logical 1 in remap mode.
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10.5.5 AMC Memory Control Register Name: AMC_MCR Access: Read/Write Base Address: 0xFFE0 0024
31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 DRP 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 25 – 17 – 9 – 1 ALE[2:0] 24 – 16 – 8 – 0
• DRP: Data Read Protocol 0: Standard read protocol for all external memory devices enabled. 1: Early read protocol for all external memory devices enabled. • ALE[2:0]: Address Line Enable These bits indicate the number of valid chip select lines.
Maximum Addressable Space per Chip Select Line 4 Mbytes 4 Mbytes 2 Mbytes 1 Mbytes
ALE2 0 1 1 1
ALE1 x 0 1 1
ALE0 x x 0 1
Valid Address Bits ADD[21:0] ADD[21:0] ADD[20:0] ADD[19:0]
Valid Chip Select NCS[3:0] NCS[3:0] NCS[3:0], CS6 NCS[3:0], CS6, CS7
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11. Clock Manager (CM)
The AT91SAM7A1 microcontroller provides: • 32.768 kHz oscillator (real-time clock oscillator) • 4 MHz to 16 MHz oscillator • Programmable PLL (x2 to x20) • Programmable master clock divider Clock management is done through the Clock Manager (CM). This allows the user to select between the different working modes LPM, SLM and OPE. At power-up, the master clock oscillator and the real-time clock oscillator are enabled. As the application may or may not use the real-time clock oscillator, the DIVCLK clock is used as the low-frequency clock (LFCLK). This ensures that both the CORECLK and the LFCLK clock can be used at power-up. At power-up, the PLL is disabled (PLLSCLT = 0 in the CM_CS register) to allow the user to select the application CORECLK frequency. Figure 11-1. Clock Management
Oscillator
MCK MCKI 0 Master Clock Oscillator (4 - 16 MHz) PLLCLK Programmable PLL (x2 to x20) .2 0 1 1 1 1 CM_CS.5 DIVSLCT CM_CS.3 LFSLCT CM_CS.2 PLLSLCT CM_PDIV.15 PLLDIV2 0 0
MCKO
CORECLK
MCKEN PLLEN PLLRC .N
DIVCLK DIVEN 0 LFCLK 1 RTCSLCT CM_CS.6 RTCSEL
CM_MDIV MDIV[6:0] RTCKI Real Time Clock Oscillator (32.768 kHz)
RTCK
RTCKO
CM_CS.7 RTCKEN
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Table 11-1 lists the different working modes depending on the value set in the CM_CS register. The grayed row shows values at reset. Table 11-1.
CM_C S7 RTCK EN 0
Clock Selection
CM_C S3 LFSL CT X CM_C S5 DIVSL CT 1 CM_CS 2 PLLSL CT X CM_C S1 PLLDI V2 X CM_C S8 MCKE N 1 CM_C S9 PLLE N 0 CM_CS 13 DIVEN 1 CM_CS 14 RTCSL CT 0 CORECLK MCK/ (2x(MDIV+1) ) MCK LFCLK MCK/ (2x(MDIV+ 1)) MCK/ (2x(MDIV+ 1)) MCK/ (2x(MDIV+ 1)) MCK/ (2x(MDIV+ 1)) RTCK RTCK RTCK RTCK RTCK MCK/ (2x(MDIV+ 1)) MCK/ (2x(MDIV+ 1)) MCK/ (2x(MDIV+ 1)) MCK/ (2x(MDIV+ 1)) MCK/ (2x(MDIV+ 1)) SLM Mode
CM_C S6 RTCS EL X
0
X
X
0
0
X
1
0
1
0
SLM
0
X
0
0
1
0
1
1
1
0
MCKxPMUL (MCKxPMUL ) /2 RTCK MCK/ (2x(MDIV+1) ) MCK MCKxPMUL (MCKxPMUL ) /2 MCK/ (2x(MDIV+1) ) MCK/ (2x(MDIV+1) ) MCK
OPE
0 1 1 1 1 1
X 1 1 1 1 1
0 1 0 0 0 0
0 X 1 0 0 0
1 X X 0 1 1
1 X X X 0 1
1 0 1 1 1 1
1 0 0 0 1 1
1 0 1 0 0 0
0 1 1 1 1 1
OPE LPM SLM SLM OPE OPE
1
0
1
X
X
X
1
0
1
0
SLM
1
0
0
1
X
X
1
0
1
0
SLM
1
0
0
0
0
X
1
0
1
0
SLM
1
0
0
0
1
0
1
1
1
0
MCKxPMUL
OPE
1
0
0
0
1
1
1
1
1
0
(MCKxPMUL )/2
OPE
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11.1 Clock Manager (CM) Memory Map
CM Memory Map
Register CM Clock Enable CM Clock Disable CM Clock Status CM PLL Stabilization Time CM PLL Divider CM Oscillator Stabilization Time CM Master Clock Divider Name CM_CE CM_CD CM_CS CM_PST CM_PDIV CM_OST CM_MDIV Access Write-only Write-only Read-only Read/Write Read/Write Read/Write Read/Write Reset State ----0x00002180 0x000000B0 0x0000800A 0x000000B0 0x0000001F
Table 11-2.
Address 0xFFFEC000 0xFFFEC004 0xFFFEC008 0xFFFEC00C 0xFFFEC010 0xFFFEC014 0xFFFEC018
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11.1.1 CM Clock Enable Register Name: CM_CE Access: Write-only Base Address: 0xFFFEC000
31 30 29 28 27 CLKEKEY[15:8] 20 19 CLKEKEY[7:0] 12 – 4 – 11 – 3 LFSLCT 26 25 24
23
22
21
18
17
16
15 – 7 RTCKEN
14 – 6 RTCSEL
13 – 5 DIVSLCT
10 – 2 PLLSLCT
9 – 1 –
8 – 0 –
• CLKEKEY[15:0]: Key for Write Access into the CM_CE Register Any write in the CM_CD register bits will be effective only if CLKEKEY[15:0] is equal to 0x2305. 11.1.2 CM Clock Disable Register Name: CM_CD Access: Write-only Base Address: 0xFFFEC004
31 30 29 28 27 CLKDKEY[15:8] 20 19 CLKDKEY[7:0] 12 – 4 – 11 – 3 LFSLCT 26 25 24
23
22
21
18
17
16
15 – 7 RTCKEN
14 – 6 RTCSEL
13 – 5 DIVSLCT
10 – 2 PLLSLCT
9 – 1 –
8 – 0 –
• CLKDKEY[15:0]: Key for Write Access into the CM_CD Register Any write in the CM_CD register bits will be effective only if CLKDKEY[15:0] is equal to 0x1807.
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11.1.3 CM Clock Status Register Name: CM_CS Access: Read-only Base Address: 0xFFFEC008
31 – 23 – 15 – 7 RTCKEN 30 – 22 – 14 RTCSLCT 6 RTCSEL 29 – 21 – 13 DIVEN 5 DIVSLCT 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 LFSLCT 26 – 18 – 10 – 2 PLLSLCT 25 – 17 – 9 PLLEN 1 – 24 – 16 – 8 MCKEN 0 –
• PLLSLCT: PLL/Master Clock Selection 0: Selects MCK clock (deselects PLLCLK or PLLCLK/2 clock). 1: Selects PLLCLK or PLLCLK/2 clock (deselects MCK clock). • LFSLCT: Low Frequency Clock Selection 0: Allows selection of MCK, PLLCLK, PLLCK/2 or DIVCLK. 1: Selects low frequency clock LFCLK (also disables master clock oscillator and PLL). • DIVSLCT: Programmable Clock Selection 0: Allows selection of MCK, PLLCK or PLLCLK/2 (also deselects the DIVCLK clock). 1: Selects DIVCLK, i.e. MCK divided by MDIV[6:0] (also deselects the master clock or PLL clock). • RTCSEL: RTC frequency clock selection 0: Selects the DIVCLK clock for low power clock (deselects the RTCK clock). 1: Selects the RTCK clock for low power clock (deselects the DIVCLK clock). • RTCKEN: Low Frequency Clock Oscillator 0: The low frequency clock oscillator is disabled. 1: The low frequency clock oscillator is enabled. • MCKEN: Master Clock Oscillator Enable 0: MCKEN signal is at a logical 0. The master clock oscillator is disabled and bypassed. 1: MCKEN signal is at a logical 1. The master clock oscillator is activated. • PLLEN: PLL Enable 0: PLLEN signal is at a logical 0. PLL is deactivated. 1: PLLEN signal is at a logical 1. PLL is enabled.
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• DIVEN: Programmable Divider Enable 0: DIVEN signal is at a logical 0. The programmable divider is disabled. 1: DIVEN signal is at a logical 1. The programmable divider is enabled. • RTCSLCT: Low Frequency Clock Selection 0: RTCSLCT signal is at a logical 0. The DIVCLK is selected for LFCLK. 1: RTCSLCT signal is at a logical 1. The RTCK is selected for LFCLK.
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11.1.4 CM PLL Stabilization Timer Register Name: CM_PST Access: Read/Write Base Address: 0xFFFEC00C
31 30 29 28 27 PSTKEY[15:8] 20 PSTKEY[7:0] 15 – 7 14 – 6 13 – 5 12 – 4 PSTB[7:0] 11 – 3 10 – 2 9 PSTB[9:8] 1 0 8 19 26 25 24
23
22
21
18
17
16
• PSTB[9:0]: PLL Stabilization Time Number of clock cycles needed before PLL stabilization. This register must be configured by the software after a hardware reset and before using the PLL. The required time for PLL stabilization is TSETUP minimum and is based on the MCK/256 clock (MCKEN = 1). The default value is 0x000000B0 guaranteeing 176 x 256 MCK clock cycles (i.e., 11.264 ms with MCK = 4.0 MHz). When the clock manager is configured in LPM mode and the program enables both the PLL and the master oscillator, PSTB should include the oscillator stabilization time and the PLL stabilization time. This is due to the fact that PSTB counter and OSTB counter decrement in parallel. The PLL transient behavior before mathematical locking (phase error between the reference signal and derived signal less than ± 2π) is complex and difficult to describe using simple mathematical expression. Thus, there is no general formula giving the set-up time for any step-response transient behavior that unlocks the loop. Nevertheless, this set-up time can be approximated by a simple loop filter capacitor charging time TSETUP in the worst case: T SETUP ≤α ⋅ where: – C3 and C4 are the loop filter capacitors, – Ip the charge pump current (see ”PLL Characteristics” on page 15), – α is a margin factor, set to 3 or 4 as a minimum This formula overestimates the required time, but gives an easy way to approximate this setup time. • PSTKEY[15:0]: Key for Write Access into the CM_PST Register Any write in PSTB[9:0] are effective only if PSTKEY[15:0] is equal to 0x59C1. These bits are always read at 0.
Note: Write accesses to this register aren only valid if PLLEN is at logical 0 (i.e., PLL not enabled).
C3 + C4 VDDPLLV 3 -------------------- ⋅ ------------------------------IP 2
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11.1.5 CM PLL Divider Register Name: CM_PDIV Access: Read/Write Base Address: 0xFFFEC010
31 30 29 28 27 PDIVKEY[15:8] 20 PDIVKEY[7:0] 15 PLLDIV2 7 – 14 – 6 – 13 – 5 – 12 – 4 11 – 3 10 – 2 PMUL[4:0] 9 – 1 8 – 0 19 26 25 24
23
22
21
18
17
16
• PMUL[4:0]: PLL Multiplier These bits select the PLL multiplier.
PMUL[4:0] 0 1 2 3 … 19 20 21 to 31 Note: PLL Multiplier Remains in previous state Remains in previous state(1) 2 3 … 19 20 Remains in previous state
Multiplying the MCK clock by 1 is equivalent to bypassing the PLL (i.e., CM_CS.2 = 0, CM_CS.3 = 0, CM_CS.5 = 0)
• PLLDIV2: PLL Divider 0: Selects PLLCLK clock (deselects PLLCLK/2) 1: Selects PLLCLK/2 clock (deselects PLLCLK) • PDIVKEY[15:0]: Key for Write Access into the CM_PDIV Register Any write in the PMUL[4:0] bits will only be effective if the PDIVKEY[15:0] is equal to 0x762D. These bits are always read at 0. The output frequency of the PLL is equal to: MCK x PMUL[4:0], where MCK is the PLL input clock.
Note: Write accesses to this register are only valid if PLLEN is at logical 0 (i.e., PLL disabled).
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11.1.6 CM Oscillator Stabilization Timer Register Name: CM_OST Access: Read/Write Base Address: 0xFFFEC014
31 30 29 28 27 OSTKEY[15:8] 20 OSTKEY[7:0] 15 – 7 14 – 6 13 – 5 12 – 4 OSTB[7:0] 11 – 3 10 – 2 9 OSTB[9:8] 1 0 8 19 26 25 24
23
22
21
18
17
16
• OSTB[9:0]: Oscillator Stabilization Time Number of clock cycles needed before master oscillator stabilization. This register must be configured by the software after a hardware reset and before using the master oscillator. The required time for master oscillator stabilization is 4 ms maximum and is based on the MCK/256 clock. The default value is 0x000000B0 guaranteeing 176 x 256 MCK clock cycles (i.e., 11.264 ms with MCK = 4.0 MHz) • OSTKEY[15:0]: Key for Write Access into the CM_OST Register Any write in the OSTB[9:0] bits will only be effective if the OSTKEY[15:0] bits are equal to 0xDB5A. These bits are always read at 0.
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11.1.7 CM Master Clock Divider Register Name: CM_MDIV Access: Read/Write Base Address: 0xFFFEC0018
31 30 29 28 27 MDIVKEY[15:8] 20 19 MDIVKEY[7:0] 12 – 4 11 – 3 MDIV[6:0] 26 25 24
23
22
21
18
17
16
15 – 7 –
14 – 6
13 – 5
10 – 2
9 – 1
8 – 0
• MDIV[6:0]: Master Clock Divider MDIV[6:0] is used to divide the MCK clock and generate the DIVCLK. Default value for MDIV[6:0] is 0x1F.
MCK DIVCLK = --------------------------------------------------2 × ( MDIV[6:0] + 1 )
• MDIVKEY[15:0]: Key for Write Access into the CM_MDIV Register Any write in the MDIV[6:0] bits is effective only if the MDIVKEY[15:0] bits are equal to 0xACDC. These bits are always read at 0.
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12. Special Function Mode (SFM)
The AT91SAM7A1 provides registers which implement the following special functions: • Chip identification • Reset status • Test mode
12.1
Chip Identification
Chip identification is done via three registers: the Chip ID (SFM_CIDR), the Extended Chip ID (SFM_EXID) and the manufacturer ID. These registers give information on: • Internal memories used (type and size) • Europe Technologies® project code
12.2
Reset Status
The AT91SAM7A1 includes the Reset Status (SFM_RSR) register to give the last cause of reset (i.e., hardware reset or internal watchdog reset).
12.3
Test Mode
The AT91SAM7A1 provides functional test mode in order to check or test some registers in internal peripherals. The test mode is entered using the SFM_TM register. It must be noted that this test mode is different from the factory test mode entered through the external pins TEST and SCANEN.
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12.4
Special Function Mode (SFM) Memory Map
SFM Memory Map
Register SFM Chip ID SFM Extended Chip ID SFM Reset Status Reserved SFM Test Mode Name SFM_CIDR SFM_EXID SFM_RSR --SFM_TM Access Read-only Read-only Read-only --Read/Write Reset State 0x80000300 0x02001102 0x0000006C or 0x00000053 --0x00000000
Base Address: 0xFFF0000 Table 12-1.
Offset 0xFFF0000 0xFFF0004 0xFFF0008 0xFFF0000C 0xFFF00014
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12.4.1 SFM Chip ID Register Name: SFM_CIDR Access: Read-only Base Address: 0xFFF0000
31 EXT 23 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 ARCH[3:0] 15 14 NVPMT[3:0] 7 6 NVDMS[3:0] 5 4 3 2 NVPMS[3:0] 13 12 11 10 IRS[3:0] 1 0 9 8 25 – 17 24 – 16
• NVPMS[3:0]: Non Volatile Program Memory Size 0000b: None. Other: Memory size = 2(14+NVPMS[3:0]) bytes. • NVDMS[3:0]: Non Volatile Data Memory Size 0000b: None. Other: Reserved. • IRS[3:0]: Internal RAM Size Internal RAM size = 2(9+IRS[3:0]) bytes. • NVPMT[3:0]: Non Volatile Program Memory Type 0000b: ROMless. 0001b: Mask ROM. Other: Reserved. • ARCH[3:0]: Core Architecture 0000b: ARM7TDMI. Other: Reserved. • EXT: Extension Flag 0: No extended chip ID. 1: Extended chip ID existing.
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12.4.2 SFM Extended Chip ID Register Name: SFM_EXID Access: Read-only Base Address: 0x004
31 EXT 23 30 – 22 PRJCF[3:0] 15 14 PRJCT[3:0] 7 6 REVS[3:0] 5 4 3 2 REVT[3:0] 13 12 11 10 REVF[3:0] 1 0 29 – 21 28 – 20 27 26 TYPE[3:0] 19 18 PRJCS[3:0] 9 8 17 16 25 24
• REVT[3:0]: Revision Number Third Digit Revision number third digit coded in BCD. • REVS[3:0]: Revision Number Second Digit Revision number second digit coded in BCD. • REVF[3:0]: Revision number first digit Revision number first digit coded in BCD. • PRJCT[3:0]: Project Code Third Digit Project code third digit coded in BCD. • PRJCS[3:0]: Project Code Second Digit Project code second digit coded in BCD. • PRJCF[3:0]: Project Code First Digit Project code first digit coded in BCD. • TYPE[3:0]: Project Code Type 0000b: Metering. 0001b: Automotive. 0010b: Industry. Other: Reserved.
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12.4.3 SFM Reset Status Register Name: SFM_RSR Access: Read-only Base Address: 0xFFF0008
31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RESET[7:0] 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24
16
8
0
This register gives the last cause of reset. • RESET[7:0]: Cause of Reset 0x6C: External reset on NRESET pin. 0x53: Internal watchdog reset.
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12.4.4 SFM Test Mode Register Name: SFM_TM Access: Read/Write Base Address: 0xFFF00014
31 30 29 28 KEY[15:8] 23 22 21 20 KEY[7:0] 15 – 7 – 14 – 6 – 13 – 5 – 12 – 4 – 11 – 3 – 10 – 2 – 9 – 1 TESTEN 8 19 18 17 16 27 26 25 24
0 –
This register must only be used for debug purposes.
• TESTEN: Test Enable 0: Disable test mode (the internal TEST_ENABLE signal is driven low at peripherals input). 1: Enable test mode (the internal TEST_ENABLE signal is driven high at peripherals input). • KEY[15:0]: Test Key for Test Mode Entry TESTEN bit can only be set/reset if the correct KEY word is entered: KEY[15:0] = 0xD64A.
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13. Watchdog Timer (WD)
The watchdog timer (WD) is used to prevent the system from locking-up, for example in infinite software loops. If the software does not clear the watchdog between watchdog pending interrupt and a programmed timeout delay, then it can generate an interrupt or internal reset. The watchdog timer has a 16-bit down counter. Bits 15 to 10 of the value loaded when the watchdog is restarted are programmable using the HPVC[4:0] parameter in WD_MR register. The software can control the action to perform when the WD counter overflows (i.e., reaches 0): • If the RSTEN bit is set in the WD_OMR register, an internal reset is generated. • If the WDOVF bit is set in the WD_IMR register, an interrupt is generated on the Generic Interrupt Controller (GIC). Multiple clock sources are available to the watchdog counter (see Figure 31 : Watchdog block diagram). The SYSCLK bit in the WD_MR register is used to select the source input: • WDSCLK = CORECLK if SYSCLK bit is at a logical 1 • WDSCLK = LFCLK if SYSCLK bit is at a logical 0 If the SYSCLK bit is at a logical 1 (i.e., the CORECLK clock input is selected), the WDSCLK is then divided by the SYSCAL[10:0] divider generating the WDPDIVCLK clock. If the SYSCLK bit is at a logical 0 (i.e., the LFCLK clock input is selected), the WDPDIVCLK = WDSCLK (i.e., WDPDIVCLK = LFCLK). The WDPDIVCLK is then divided by the WDPDIV[2:0] divider and provided to the downcounter input WDCLK. Table 13-1.
WD_MR.3 SYSCLK 0 WDSCLK LFCLK WDPIDCLK LFCLK CORECLK SYSCAL[10:0]divider WDCLK LFCLK WDPDIV[2:0]divider CORECLK SYSCAL[10:0]divider x WDPDIV[2:0]divider
WD Counter Clock Dividers
1
CORECLK
All write accesses are protected by control access keys to help prevent corruption of the watchdog should an error condition occur. To update the contents of the mode and control registers, it is necessary to write the correct bit pattern to the control access key bits at the same time as the control bits are written (the same write access).
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13.1
Architecture
The WD contains a programmable length down-counter. The count length determines the timeout period, and is controlled by loading the upper bits (15 to 11) of the counter with a programmed value HPCV[4:0]. The lower bits (10 to 0) of the counter are loaded with 0x7FF. The time-out period (in seconds) is:
(HPCV[4 : 0] × 2 )+ 0xFFF + 1 = (HPCV[4 : 0] × 2 )+ 2048
11 11
WDCLK freq
WDCLK freq
When the counter reaches 0x00FF, the watchdog can generate a watchdog pending interrupt. The pending interrupt occurs after:
(HPCV[4 : 0] × 2 ) + 1792 seconds
11
WDCLK freq
In order to prevent an internal reset (if RSTEN bit is set in the WD_OMR) or interrupt (if bit WDOVF is set in the WD_IMR), the software must reset the counter before it reaches 0 by writing the correct key in the WD_CR register (0xC071). The time (in seconds) between the WD pending interrupt and the WD overflow is:
256 WDCLK freq
When the counter reaches 0, it triggers the programmed action (internal reset or interrupt). If no WD reset is programmed (i.e., RSTEN is at a logical 0) when the WD reaches 0, it is reset to the programmed value and continues to count, unless it is disabled. This enables it to generate periodic interrupts. Figure 13-1. Watchdog Block Diagram
WD_CTR COUNT[15:0] (HPCV[4:0]
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