AT91SAM7A1_06

Features • ARM7TDMI® ARM® Thumb® Processor Core – High-performance 32-bit RISC – High-density 16-bit Thumb Instruction Set – Leader in MIPS/Watt – Embedded ICE (In Circuit Emulation) 4 Kbytes Internal RAM Clock Manager (CM) with Programmable PLL – PLL Multiplier from x2 to x20 – 32.768 kHz Oscillator for Low-power Operation – Master Clock Divider/multiplier Fully Programmable External Bus Interface (EBI) through Advanced Memory Controller (AMC) – Maximum External Address Space of 16 Mbytes, Up to Six Chip Select Lines 8-level Priority, Vectored Interrupt Controller – Individually Maskable, Two External Interrupts including One Fast Interrupt Line 11-channel Peripheral Data Controller (PDC) 49 Programmable I/O Lines One 3-channel 16-bit General Purpose Timers (GPT) – Three Configurable Modes: Counter, PWM, Capture – Three Multi-purpose I/O Pins Per Channel Four 16-bit Simple Timers (ST) 4-channel 16-bit Pulse Width Modulation (PWM) Two 16-bit Capture Modules (CAPT) CAN Controller 2.0A and 2.0B Full CAN (16 Buffers) Three USARTs – Six Peripheral Data Controller (PDC) Channels – Support for Up to 9-bit Data Lengths – Support for LIN (Software) Protocol Master SPI Interface – Two Peripheral Data Controller (PDC) Channels – 8- to 16-bit Programmable Data Length – Four External Chip Select Lines One 8-channel 10-bit Analog-to-digital Converter (ADC) – One Peripheral Data Controller (PDC) Channel Programmable Watch Timer (WT) Programmable Watchdog (WD) Power Management Controller (PMC) – CPU and Peripherals Can Be Deactivated Individually Fully Static Operation Up to 40 MHz – 3.0V to 3.6V Core, Memory and Analog Voltage Range – 3.0 V to 5.5V Compliant I/Os – -40° to +85°C Operating Temperature Range Available in a 144-pin LQFP • • • AT91 ARM Thumb-based Microcontrollers AT91SAM7A1 Summary • • • • • • • • • • • • • • • • NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6048C–ATARM–29-Jun-06 1. Description The AT91SAM7A1 is a member of the Atmel Smart ARM Microcontrollers product family, based on the ARM7TDMI embedded processor. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The AT91SAM7A1 has a direct connection to off-chip memory, including Flash, through the fully-programmable External Bus Interface. An 8-level priority vectored Interrupt Controller in conjunction with the Peripheral Data Controller significantly improves the real-time performance of the device. The device is manufactured using high-density CMOS technology. By combining the ARM7TDMI processor with an on-chip RAM and a wide range of peripheral functions on a monolithic chip, the AT91SAM7A1 is a powerful device that provides a flexible, cost-effective solution to many compute-intensive embedded control applications in the industrial world. 2 AT91SAM7A1 6048C–ATARM–29-Jun-06 AT91SAM7A1 2. Block Diagram Figure 2-1. AT91SAM7A1 Block Diagram 5V-compliant VDDCORE SCANEN 3V3 Supply NWAIT TEST IRQ0 GND TMS TDO TCK FIQ TDI VDDIO GND I/O Power Supply Core Power Supply Generic Interrupt Controller SPI Select JTAG SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS0/MPIO NPCS1/MPIO NPCS2/MPIO NPCS3/MPIO RXD0/MPIO TXD0/MPIO SCK0/MPIO RXD1/MPIO TXD1/MPIO SCK1/MPIO 5V-compliant RXD2/MPIO TXD2/MPIO SCK2/MPIO EBI Embedded ICE Arbiter ASB Controller SFM AMBATM Bridge ARM7TDMI Core PIO 2 PDC Channels USART0 2 PDC Channels USART1 2 PDC Channels USART2 2 PDC Channels Timer GPT0 Simple Timers ST0 CH0 CH1 Clock Manager PLLON 11 Channel PDC Controller Reset NRESET PIO PIO Watch Dog 32.768 MHz 64 PLL PLL x MCK 4 - 8 MHz MC Osc MCKI MCKO PLLRC T0TIOA0/MPIO T0TIOB0/MPIO T0TCLK0/MPIO T0TIOA1/MPIO T0TIOB1/MPIO T0TCLK1/MPIO T0TIOA2/MPIO T0TIOB2/MPIO T0TCLK2/MPIO PIO TC0 ST1 CH0 PIO TC1 CH1 CORECLK Capture 0 CH0 PIO AT91SAM7A1 1 PDC Channel Capture 1 CAPT0/MPIO PIO TC2 WT CH0 PIO CAPT1/MPIO 5V-compliant 1 PDC Channel PWM CH0 PWM0/MPIO PIO PWM1/MPIO PWM2/MPIO PWM3/MPIO Analog Power Suppy 1 PDC Channel CAN0 ADC0 8-channel 10-bit ADC UPIO Full Speed 16 Buffers CH1 CH2 CH3 VDDANA CANRX0 ANA0IN[7:0] CANTX0 GND VREFP Analog Supply 5V-compliant UPIO[17:0] 3V3 Supply PIO LFCLK RT Osc RTCKI RTCKO 5V-compliant 4 KB Internal RAM 3V3 Supply Advanced Memory Controller ADD[19:1] ADD0/NLB ADD20/CS7 ADD21/CS6 NOE/NRD NWR0/NWE NWR1 /NUB 1 NCS[3:0] D[15:0] 3 6048C–ATARM–29-Jun-06 3. Pin Configuration Table 3-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Configuration Name D0 D8 D1 D9 VDDCORE GND(2) Pad PC3B01D PC3B01D PC3B01D PC3B01D Pin 37 38 39 40 41 42 Name ADD11 ADD12 ADD13 ADD14 ADD15 GND VDDCORE VDDIO IRQ0 FIQ T0TIOA0/MPIO T0TIOB0/MPIO T0TCLK0/MPIO T0TIOA1/MPIO T0TIOB1/MPIO T0TCLK1/MPIO T0TIOA2/MPIO T0TIOB2/MPIO GND T0TCLK2/MPIO TXD0/MPIO RXD0/MPIO SCK0/MPIO TXD1/MPIO RXD1/MPIO SCK1/MPIO VDDIO SPCK/MPIO MISO/MPIO MOSI/MPIO NPCS0/MPIO NPCS1/MPIO NPCS2/MPIO NPCS3/MPIO PIOA0 PIOA1 (1) Pad PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 Pin 73 74 75 76 77 78 79 80 Name GND PIOA2 PIOA3 VDDIO PIOA4 PIOA5 PIOA6 PIOA7 PIOA8 PIOA9 GND PIOA10 PIOA11 PIOA12 PIOA13 PIOA14 PIOA15 PIOA16 PIOA17 PWM0/MPIO VDDIO PWM1/MPIO PWM2/MPIO PWM3/MPIO CAPT0/MPIO CAPT1/MPIO NRESET CANRX0 CANTX0 TXD2/MPIO RXD2/MPIO SCK2/MPIO GND VDDANA VREFP ANA0IN0 Pad Pin 109 Name ANA0IN1 ANA0IN2 ANA0IN3 ANA0IN4 ANA0IN5 ANA0IN6 ANA0IN7 GND VDDCORE MCKI MCKO PLLRC GND VDDCORE RTCKI RTCKO GND VDDIO GND(2) GND SCANEN TEST TMS TDO TDI TCK NWAIT ADD21/CS6 NCS3 NCS2 NWR1/NUB ADD0/NLB NCS1 NOE/NRD NCS0 ADD1 Pad AIMUX1 AIMUX1 AIMUX1 AIMUX1 AIMUX1 AIMUX1 AIMUX1 MC5B04 MC5B04 110 111 112 MC5B03 MC5B03 MC5B03 MC5B03 MC5B03 MC5B03 113 114 115 116 117 118 119 VDDCORE D2 D10 D3 D11 D4 D12 D5 D13 D6 D14 D7 D15 ADD17 ADD16 (1) 43 PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3B01D PC3T02 PC3T02 PC3B02 PC3T02 PC3T02 PC3T02 PC3T02 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 MC5D00 MC5D00 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 81 82 83 84 85 86 87 88 89 90 91 OSC16M OSC16M PLL080M1 MC5B02 MC5B02 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 120 121 122 123 124 125 126 127 128 129 OSC33K OSC33K MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 92 93 94 95 96 97 98 99 PC3D01D PC3D01D PC3D21U PC3T03 PC3D21U PC3D21U PC3D01U PC3T02 PC3T02 PC3T02 PC3B02 PC3T02 PC3T02 PC3B02 PC3T02 PC3T02 NWR0/NWE ADD19 ADD18 ADD7 ADD6 GND (2) (1) MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5D20 MC5D00 MC5O01 MC5B01 MC5B01 MC5B01 130 131 132 133 134 135 136 137 138 139 140 141 142 VDDCORE ADD2 ADD3 ADD4 ADD5 ADD8 64 PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 PC3T02 65 66 67 68 69 70 71 72 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B01 MC5B04 MC5B04 100 101 102 103 104 105 106 107 108 ADD20/CS7 ADD9 ADD10 ANAIN AIMUX1 143 144 Notes: 1. Pins 7, 28 and 43 are connected internally. 2. Pins 6, 27 and 127 are connected internally. 4 AT91SAM7A1 6048C–ATARM–29-Jun-06 AT91SAM7A1 4. Pin Description Table 4-1. Module Pin Description Name ADD[19:1] ADD0/NLB ADD20/CS7 ADD21/CS6 Function External address bus External address line/Lower byte enable External address line/Chip select External address line/Chip select External data bus Output enable Write enable Chip select lines Upper byte enable Wait Input External interrupt line Fast interrupt line Hardware reset input Master clock input Master clock output PLL RC network input 32.768 kHz clock input 32.768 kHz clock output Unified I/O USART0 clock line USART0 receive line USART0 transmit line USART1 clock line USART1 receive line USART1 transmit line USART2 clock line USART2 receive line USART2 transmit line Capture input Pulse Width Modulation output Type(1) O O O O I/O O O O O I I I I I O I I O I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) (Z) (Z) (Z) (Z) (Z) (Z) (Z) (Z) (Z) (Z) (Z) (Z) Connected to external 32.768 kHz crystal General-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Multiplexed with general-purpose I/O Connected to external crystal (4 to 16 MHz) L Schmitt input with internal filter Level(1) (Z) L (Z) H (Z) H (Z) (Z) L (Z) L (Z) L (Z) L (Z) L Internal pull-up (must be connected to VCC or leave unconnected for normal operation) The EBI is tri-stated when NRESET is at a logical low level. Internal pulldowns on data bus bits. ADD20 and ADD21 are address lines at reset. Comments EBI(2) D[15:0](3) NOE/NRD NWR0/NWE NCS[3:0] NWR1/NUB NWAIT IRQ0 GIC FIQ Power-on Reset Master Clock NRESET MCKI MCKO PLLRC Real-time Clock UPIO RTCKI RTCKO UPIO[17:0] SCK0/MPIO USART0 RXD0/MPIO TXD0/MPIO SCK1/MPIO USART1 RXD1/MPIO TXD1/MPIO SCK2/MPIO USART2 RXD2/MPIO TXD2/MPIO Capture PWM CAPT[1:0]/MPIO PWM[3:0]/MPIO 5 6048C–ATARM–29-Jun-06 Table 4-1. Module Pin Description Name T0TIOA[2:0]/MPIO Function Capture/waveform I/O Trigger/waveform I/O External clock/trigger/input Analog input Positive voltage reference SPI clock line SPI master in slave out SPI master out slave in SPI chip select SPI chip select CAN0 receive line CAN0 transmit line Scan enable (Factory test) Test Data In Test Data Out Test Mode Select Test Clock Factory test Core Power Supply Analog Power Supply I/O Lines Power Supply Ground Type(1) I/O (I) I/O (I) I/O (I) I I I/O (I) I/O (I) I/O (I) I/O (I) I/O (I) I O I I O I I I – – – – H Schmitt trigger, internal pull-up Schmitt trigger, internal pull-up Internal pull-down (must be connected to GND or leave unconnected for normal operation) 3.3V 3.3V 3.3V to 5V (Z) (Z) (Z) (Z) (Z) L L (H) H Internal pull-down (must be connected to GND or leave unconnected for normal operation) Schmitt trigger, internal pull-up Multiplexed with a general-purpose I/O Multiplexed with a general-purpose I/O Multiplexed with a general-purpose I/O Multiplexed with a general-purpose I/O Multiplexed with a general-purpose I/O Level(1) (Z) (Z) (Z) Comments Multiplexed with a general-purpose I/O Multiplexed with a general-purpose I/O Multiplexed with a general-purpose I/O Timer T0 T0TIOB[2:0]/MPIO T0TCLK[2:0]/MPIO ANAIN[7:0] ADC VREFP SPCK/MPIO MISO/MPIO SPI MOSI/MPIO NPCS[3:1]/MPIO NPCS0/MPIO CANRX0 CAN0 CANTX0 SCANEN TDI TDO JTAG TMS TCK TEST VDDCORE Power Supplies VDDANA VDDIO GND Notes: 1. Values in brackets are values at reset H (high level), L (low level), Z (tri-state), I (input), O (output). 2. The EBI bus (address bus A[21:0], data bus D[15:0] and control lines NOE/NRD, NWR0/NWE, NWR1/NUB and NCS[3:0]) is tri-stated when NRESET is at a logical 0. This allows external equipment to access the external memory devices (e.g., for Flash programming). It is up to the application to add an external pull-up on the chip select lines in order to avoid EBI conflicts at reset. 3. The EBI data bus D[15:0] has an internal pull-down. 6 AT91SAM7A1 6048C–ATARM–29-Jun-06 AT91SAM7A1 5. Architectural Overview The AT91SAM7A1 architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). The ASB is designed for maximum performance. It interfaces the processor with the on-chip 32-bit memories and the external memories and devices by means of the External Bus Interface (EBI). The APB is designed for accesses to onchip peripherals and is optimized for low power consumption. The AMBA™ Bridge provides an interface between the ASB and the APB. The AT91SAM7A1 peripherals are designed to be programmed with a minimum number of instructions. Each peripheral has a 16 Kbyte address space allocated in the upper 1 Mbytes of the 4 Gbyte address space. Except for the interrupt controller, the peripheral base address is the lowest address of its memory space. The peripheral register set is composed of control, mode, data, status and interrupt registers. To maximize the efficiency of bit manipulation, frequentlywritten registers are mapped into three memory locations. The first address is used to set the individual register bits, the second resets the bits and the third address reads the value stored in the register. A bit can be set or reset by writing a one to the corresponding position at the appropriate address. Writing a zero has no effect. Individual bits can thus be modified without having to use costly read-modify-write and complex bit manipulation instructions. The ARM7TDMI processor operates in little-endian mode in the AT91SAM7A1 microcontroller. The processor's internal architecture and the ARM and Thumb instruction sets are described in the ARM7TDMI datasheet. The ARM Standard In-Circuit-Emulation debug interface is supported via the ICE port of the AT91SAM7A1 microcontroller (This is not a standard IEEE 1149.1 JTAG Boundary Scan interface). 6. Advanced Memory Controller (AMC) The AT91SAM7A1 embeds 4 Kbytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 36 MIPS @ 40 MHz by using the ARM instruction set of the processor, minimizing system power consumption and improving on the performance of separate memory solutions. 7. External Bus Interface (EBI) The EBI generates the signals that control the accesses to the external memories or peripheral devices. The EBI is fully programmable and can address up to 6 Mbytes. It has four chip selects and a 21-bit address bus, the upper bit of which is multiplexed with a chip select. Separate read and write control signals allow for direct memory and peripheral interfacing. The EBI supports different access protocols, allowing single clock cycle memory accesses. The main features are: • External Memory Mapping • Up to 4 chip select lines • Byte write or byte select lines • 8-bit or 16-bit data bus • External wait • Remap of boot memory • Two different read protocols • Programmable wait state generation 7 6048C–ATARM–29-Jun-06 8. Generic Interrupt Controller (GIC) The AT91SAM7A1 has an 8-level priority, individually maskable, vectored interrupt controller. This feature substantially reduces the software and real time overhead in handling internal and external interrupts. The interrupt controller is connected to the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor's nFIQ line can only be asserted by the external fast interrupt request input, the FIQ. The nIRQ line can be asserted by the interrupts generated by the on-chip peripherals and the external interrupt request line, IRQ0. An 8-level priority encoder allows the customer to define the priority between the different nIRQ interrupt sources. Internal sources are programmed to be level sensitive or edge triggered. External sources can be programmed to be positive or negative edge triggered or high or low level sensitive. 9. Parallel I/O Controller (PIO) The AT91SAM7A1 has 49 configurable I/O lines. Thirty-two pins (unified PIO) on the AT91SAM7A1 are dedicated as general purpose I/O pins (UPIO0 - UPIO31). Other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The unified PIO pins are controlled by a dedicated module; the others pins are configured in each module. 10. Peripheral Data Controller (PDC) An on-chip, 11-channel Peripheral Data Controller (PDC) transfers data between the on-chip peripherals and the on- and off-chip memories without processor intervention. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART and of the SPI. A single PDC channel is connected to each ADC and each Capture. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64 Kbytes without reprogramming the starting address. As a result, the performance of the microcontroller is increased and the power consumption reduced. 11. Universal Synchronous/Asynchronous Receiver/Transmitter (USART) The AT91SAM7A1 provides three identical, full-duplex Universal Synchronous/Asynchronous Receiver/Transmitters that are connected to the Peripheral Data Controller. The main features are: • Programmable Baud Rate Generator • Parity, framing and overrun error detection • Line break generation and detection • Automatic echo, local & remote loopback modes • Multi-drop mode: address detection and generation • Interrupt generation • Two Dedicated Peripheral Data Controller channels • 5-, 6-, 7-, 8- and 9-bit character length • Idle flag for J1587 protocol. • Smart card transmission error feature • Support LIN 1.2 protocol with H/W layer 8 AT91SAM7A1 6048C–ATARM–29-Jun-06 AT91SAM7A1 12. Serial Peripheral Interface (SPI) The AT91SAM7A1 features an SPI that provides communication with external devices in master or slave mode. The SPI has four external chip selects that can be connected to up to 15 devices. The data length is programmable from 8-bit to 16-bit. As for the USART, a two-channel PDC is used to move data directly between memory and the SPI without CPU intervention for maximum real-time processing throughput. 13. Controller Area Network (CAN) The AT91SAM7A1 provides one CAN (2.0A and 2.0B). These are serial communications protocols that efficiently support distributed real-time control with a very high level of security (16 mailboxes). The main features are: • Prioritization of messages • Multi-master • System wide data consistency • Error detection and error signaling • Automatic retransmission of corrupted messages • Automatic reply after receive a remote frame • Time stamp on each transfer • Multicast reception with time synchronization • Continuous reception mode 14. General-purpose Timer (GPT) The AT91SAM7A1 features three general-purpose timers. Each timer can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each general-purpose timer has one external clock input, five internal clock inputs, and three multi-purpose input/output signals that can be configured by the user. Each timer drives an internal interrupt signal that can be programmed to generate processor interrupts via the GIC (Generic Interrupt Controller). Three general-purpose timers are grouped in the same block. This block has two global registers that act upon all three GPTs. The Block Control Register allows the three timers to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each timer, allowing them to be chained. 15. Simple Timer (ST) Simple Timers provide basic functions for timing calculation. Each channel of this timer has a specific prescalar and a 16-bit counter. The prescalar defines the clock frequency of the channel counter. The 16-bit counter starts down-counting when a value different to zero is loaded. An interrupt is generated when the counter is null. 9 6048C–ATARM–29-Jun-06 16. Capture Module (CAPT) The capture module is a frame analyzer. It stores the period of time between two edges of a signal in a register. This period is described as a number of counter cycles. The capture allows data transfers with the PDC. 17. Pulse Width Modulator (PWM) The AT91SAM7A1 includes four PWM channels. Each channel can generate pulses. The frequency and the duty cycle of each channel can be configured. 18. Watch Timer (WT) The watch timer provides a seconds counter and an alarm function. The alarm register has a resolution of 30.5 µs. This allows a 32-bit register to have sufficient range to cater for a 24 or 36 hour period. 19. Watchdog (WD) The AT91SAM7A1 has an internal watchdog that can be used to prevent system lock-up if the software becomes trapped in a deadlock. 20. Special Function Module (SFM) The AT91SAM7A1 provides registers which implement the following special functions: • Chip identification • RESET status 21. Analog-to-digital Converter (ADC) The 8-channel, 10-bit Analog-to-Digital Converter (ADC) is based on a Successive Approximation Register (SAR) approach. The ADC has eight analog input pins, ANA0IN0 to ANA0IN7, and provides an interrupt signal to the AIC. The ADC has two dedicated analog power supply pins, VDDANA and GND, and the input reference voltage pin, VREFP. Each channel can be enabled or disabled independently, and has its own data register. The ADC can be configured to automatically enter Sleep Mode after a conversion sequence, and can be triggered by the software. The ADC allows a data transfer with the PDC. 22. Power Management Controller (PMC) The AT91SAM7A1 Power Management Controller allows optimization of power consumption. The PMC enables/disables the clock inputs of PDC and ARM core. Moreover, the main oscillator, the PLL and the analog peripherals can be put in standby mode, allowing minimum power consumption to be obtained. The PMC provides the following operating modes: • Normal: Clock generator provides clock to chip • Wait mode: ARM core clock is deactivated • Slow mode: clock generator is deactivated, the system is clocked at 32.768 kHz Each peripheral clock can be independently stopped or started directly in the peripheral to further reduce power consumption in Normal, Wait and Slow Modes. 10 AT91SAM7A1 6048C–ATARM–29-Jun-06 AT91SAM7A1 23. ICE Debug Mode ARM Standard Embedded In Circuit Emulation is supported via the ICE port. It is connected to a host computer via an external ICE Interface. In ICE Debug Mode, the ARM core responds with a non-JTAG chip ID which identifies the core to the ICE system. This is not JTAG IEEE 1149.1 compliant. 11 6048C–ATARM–29-Jun-06 24. Packaging Information Figure 24-1. 144-lead LQFP Package Orientation (Top View) 144 109 108 1 36 37 72 73 12 AT91SAM7A1 6048C–ATARM–29-Jun-06 AT91SAM7A1 Figure 24-2. 144-pin LQFP Version A (Foundry Reference) aaa bbb PIN 1 θ1 θ2 S ccc θ3 ddd R1 R2 0.25 θ c c1 L1 Table 24-1. Symbol A A1 A2 D D1 E E1 R2 R1 Q Q1 Q2 Q3 Package Dimensions in mm Min Nom Max 1.60 0.05 1.35 1.40 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.08 0.08 0° 0° 11° 11° 12° 12° 13° 13° 3.5° 7° aaa bbb ccc ddd 0.20 0.15 1.45 Symbol c L L1 S b e D2 E2 0.20 0.17 0.20 0.50 BSC 17.50 17.50 Tolerances of form and position 0.20 0.20 0.08 0.08 0.27 Min 0.09 0.45 0.60 1.00 REF Nom Max 0.20 0.75 13 6048C–ATARM–29-Jun-06 25. Soldering Profile Table 25-1 gives the recommended soldering profile from J-STD-20. Table 25-1. Soldering Profile Convection or IR/Convection Average Ramp-up Rate (183° C to Peak) Preheat Temperature 125° C ±25° C Temperature Maintained Above 183° C Time within 5° C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° C to Peak Temperature 3° C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0° C or 235 +5/-0° C 6° C/sec. 6 min. max 60 sec. 215 to 219° C or 235 +5/-0° C 10° C/sec. VPR 10° C/sec. Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235° C, not 220° C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 25-2. Table 25-2. Parameter Convection VPR IR/Convection Notes: Recommended Package Reflow Conditions(1, 2, 3) Temperature 220 +5/-0° C 215 to 219° C 220 +5/-0° C 1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220° C (unless 235° C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. A maximum of three reflow passes is allowed per component. 14 AT91SAM7A1 6048C–ATARM–29-Jun-06 AT91SAM7A1 26. Ordering Information Table 26-1. AT91SAM7A1 Ordering Information Package LQFP144 Package Type Green Temperature Operating Range Industrial (-40° C to +85° C) Ordering Code AT91SAM7A1-AU 15 6048C–ATARM–29-Jun-06 Revision History Doc. Rev. 6048AS 6048BS Date 22-Jul-04 03-Mar-05 Comments First issue. Removed Preliminary status. Changed package from TQFP to LQFP, type Green. Removed references to Automotive applications. “Features” on page 1, “Description” on page 2 replaced with features and description from full datasheet. 2740 Change Request Ref. 6048CS 29-JUN-06 16 AT91SAM7A1 6048C–ATARM–29-Jun-06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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