Features
• Incorporates the ARM7TDMI ® ARM® Thumb® Processor
– High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt Embedded ICE In-circuit Emulation, Debug Communication Channel Support 256 Kbytes of Internal High-speed Flash, Organized in 1024 Pages of 256 Bytes – Single Cycle Access at Up to 30 MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms – 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities 32K Bytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed Memory Controller (MC) – Embedded Flash Controller, Abort Status and Misalignment Detection – Memory Protection Unit Reset Controller (RSTC) – Based on Three Power-on Reset Cells – Provides External Reset Signal Shaping and Reset Sources Status Clock Generator (CKGR) – Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL Power Management Controller (PMC) – Power Optimization Capabilities, including Slow Clock Mode (Down to 500 Hz), Idle Mode, Standby Mode and Backup Mode – Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Four External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) – 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signal to the System – Counter May Be Stopped While the Processor is in Debug Mode or in Idle State Real-time Timer (RTT) – 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator Two Parallel Input/Output Controllers (PIO) – Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up resistor and Synchronous Output Shutdown Controller (SHDWC) – Programmable Shutdown Pin and Wake-up Circuitry Four 32-bit Battery Backup Registers for a Total of 16 Bytes One 8-channel 20-bit PWM Controller (PMWC) One USB 2.0 Full Speed (12 Mbits per Second) Device Port – On-chip Transceiver, 2-Kbyte Configurable Integrated FIFOs Nineteen Peripheral Data Controller (PDC) Channels Two CAN 2.0B Active Controllers, Supporting 11-bit Standard and 29-bit Extended Identifiers – 16 Fully Programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two 8-channel 10-bit Analog-to-Digital Converter
• •
• • • • •
AT91 ARM® Thumb®-based Microcontrollers AT91SAM7A3 Preliminary
•
• • •
• •
• • • • • • •
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Preliminary
• Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) • • •
– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interfaces (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects Three 3-channel 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROM’s Supported Multimedia Card Interface (MCI) – Compliant with Multimedia Cards and SD Cards – Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant IEEE 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: – Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and the External Components, Enables 3.3V Single Supply Mode – 3.3 VDDIO I/O Lines and Flash Power Supply – 1.8V VDDCORE Core Power Supply – 3V to 3.6V VDDANA Analog Power Supply – 3V to 3.6V VDDBU Backup Power Supply 5V-tolerant I/Os Fully Static Operation: 0 Hz to 60 MHz at 1.65V and 85°C Worst Case Conditions Available in a 100-lead LQFP Package
• • • •
• • •
Description
The AT91SAM7A3 is a member of a series of 32-bit ARM7® microcontrollers with an integrated CAN controller. It features a 256-Kbyte high-speed Flash and 32-Kbyte SRAM, a large set of peripherals, including two 2.0B full CAN controllers, and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface. Built-in lock bits protect the firmware from accidental overwrite. The AT91SAM7A3 integrates a complete set of features facilitating debug, including a JTAG In-Circuit-Emulation interface, misalignment detector, interrupt driven debug communication channel for user configurable trace on a console, and JTAG boundary scan for board level debug and test. By combining a high-performance 32-bit RISC processor with a high-density 16-bit instruction set, Flash and SRAM memory, a wide range of peripherals including CAN controllers, 10-bit ADC, Timers and serial communication channels, on a monolithic chip, the AT91SAM7A3 is ideal for many compute-intensive embedded control applications in the automotive, medical and industrial world.
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Block Diagram
Figure 1. AT91SAM7A3 Block Diagram
TDI TDO TMS TCK JTAGSEL TST FIQ IRQ0-IRQ3 DRXD DTXD PCK0-PCK3 PLLRC XIN XOUT GNDBU VDDBU FWKUP WKUP0 WKUP1 SHDW VDDBU VDDIO VDDCORE NRST
PIO
JTAG SCAN System Controller AIC
PDC
ICE
ARM7TDMI Processor
1.8 V Voltage Regulator
VDDIN GND VDDOUT
DBGU
PDC
FLASH 256K Bytes Memory Controller SRAM 32K Bytes
Embedded Flash Controller Memory Protection Unit Address Decoder Abort Status Misalignment Detection
PLL OSC
GPBR
PMC
RCOSC
RTT Shutdown Controller
Peripheral Bridge Peripheral Data Controller
19 channels
POR POR POR PIT
TWI
APB
FIFO
Transceiver
Reset Controller
USB Device
DDM DDP
WDT PIOA
RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 NPCS00 NPCS01 NPCS02 NPCS03 MISO0 MOSI0 SPCK0 NPCS10 NPCS11 NPCS12 NPCS13 MISO1 MOSI1 SPCK1 MCCK MCCDA MCDA0-MCDA3 AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 ADTRG0 ADVREFP VDDANA GNDANA AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 ADTRG1
CAN0 CAN1
PDC
PIOB
USART0
PDC PDC
PWMC
USART1
PDC PDC
PDC
USART2
PDC PDC
PDC PDC
SSC1
PDC
SPI0
PDC PDC
PIO
SSC0
TWD TWCK CANRX0 CANTX0 CANRX1 CANTX1 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TCLK3 TCLK4 TCLK5 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 TCLK6 TCLK7 TCLK8 TIOA6 TIOB6 TIOA7 TIOB7 TIOA8 TIOB8
Timer Counter TC0 TC1
PDC PDC
SPI1
PIO
TC2 Timer Counter TC3 TC4 TC5
MCI
PDC
ADC0
PDC
Timer Counter TC6
ADC1
TC7 TC8
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Signal Description
Table 1. Signal Description
Signal Name Function Power VDDIN VDDIO VDDBU VDDANA VDDOUT VDDCORE VDDPLL GND GNDANA GNDBU GNDPLL 1.8V Voltage Regulator Power Supply I/O Lines and Flash Power Supply Backup I/O Lines Power Supply Analog Power Supply 1.8V Voltage Regulator Output 1.8V Core Power Supply 1.8V PLL Power Supply Ground Analog Ground Backup Ground PLL Ground Power Power Power Power Power Power Power Ground Ground Ground Ground Clocks, Oscillators and PLLs XIN XOUT PLLRC PCK0 - PCK3 SHDW WKUP0 - WKUP1 FWKUP Main Oscillator Input Main Oscillator Output PLL Filter Programmable Clock Output Shut-Down Control Wake-Up Inputs Force Wake Up Input Output Input Output Output Input Input ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Reset/Test NRST TST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data Input Output I/O Input Low Pull-down resistor Input Input Output Input Input No pull-up resistor Pull-down resistor No pull-up resistor No pull-up resistor Driven at 0V only. Do not tie over VDDBU Accept between 0V and VDDBU Accept between 0V and VDDBU 2.7V to 3.6V 3V to 3.6V 3V to 3.6V 3V to 3.6V 1.85V typical 1.65V to 1.95V 1.65V to 1.95V Type Active Level Comments
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Table 1. Signal Description (Continued)
Signal Name Function AIC IRQ0 - IRQ3 FIQ External Interrupt Inputs Fast Interrupt Input PIO PA0 - PA31 PB0 - PB29 Parallel IO Controller A Parallel IO Controller B I/O I/O Multimedia Card Interface MCCK MCCDA MCDA0 - MCDA3 Multimedia Card Clock Multimedia Card A Command Multimedia Card A Data Output I/O I/O USB Device Port DDM DDP USB Device Port Data USB Device Port Data + USART SCK0 - SCK1 - SCK2 TXD0 - TXD1 - TXD2 RXD0 - RXD1 RXD2 RTS0 - RTS1 - RTS2 CTS0 - CTS1 - CTS2 Serial Clock Transmit Data Receive Data Request To Send Clear To Send I/O I/O Input Output Input Synchronous Serial Controller TD0 - TD1 RD0 - RD1 TK0 - TK1 RK0 - RK1 TF0 - TF1 RF0 - RF1 Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter TCLK0 - TCLK8 TIOA0 - TIOA8 TIOB0 - TIOB8 External Clock Input I/O Line A I/O Line B Input I/O I/O PWM Controller PWM0 - PWM7 PWM Channels Output Analog Analog Pulled-up input at reset Pulled-up input at reset Input Input Type Active Level Comments
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Table 1. Signal Description (Continued)
Signal Name Function SPI MISO0-MISO1 MOSI0-MOSI1 SPCK0-SPCK1 NPCS00-NPCS10 NPCS01 - NPCS03 NPCS11 - NPCS13 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Two-wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O Analog-to-Digital Converter AD00-AD07 AD10-AD17 ADVREFP ADTRG0 - ADTRG1 Analog Inputs Analog Positive Reference ADC Trigger Analog Analog Input CAN Controller CANRX0-CANRX1 CANTX0-CANTX1 CAN Inputs CAN Outputs Input Output Digital pulled-up inputs at reset Low Low Type Active Level Comments
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Package and Pinout
100-lead LQFP Mechanical Overview
Figure 2 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in “AT91SAM7A3 Mechanical Characteristics” on page 553.
Figure 2. 100-lead LQFP Pinout (Top View)
75 76 51 50
100 1 25
26
Pinout
Table 2. Pinout in 100-lead LQFP Package
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 GND NRST TST PB13 PB12 PB11 PB10 PB9 PB8 PB7 PB6 PB5 PB4 PB3 VDDIO GND VDDCORE PB2 PB1 PB0 PA0 PA1 PA2 PA3 GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDBU FWKUP WKUP0 WKUP1 SHDW GNDBU PA4 PA5 PA6 PA7 PA8 PA9 VDDIO GND VDDCORE PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 VDDCORE GND VDDIO PA28 PA29 PA30 PA31 JTAGSEL TDI TMS TCK TDO GND VDDPLL XOUT XIN GNDPLL 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PLLRC VDDANA ADVREFP GNDANA PB14/AD00 PB15/AD01 PB16/AD02 PB17/AD03 PB18/AD04 PB19/AD05 PB20/AD06 PB21/AD07 VDDIO PB22/AD10 PB23/AD11 PB24/AD12 PB25/AD13 PB26/AD14 PB27/AD15 PB28/AD16 PB29/AD17 DDM DDP VDDOUT VDDIN
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Power Considerations
Power Supplies
The AT91SAM7A3 has seven types of power supply pins: • • • • VDDIN pin. It powers the voltage regulator; voltage ranges from 2.7V to 3.6V, 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND. VDDIO pin. It powers the I/O lines, the Flash and the USB transceivers; voltage ranges from 3.0V to 3.6V, 3.3V nominal. VDDOUT pin. It is the output of the 1.8V voltage regulator. VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It might be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly. VDDPLL pins. They power the PLL; voltage ranges from 1.65V to 1.95V, 1.8V typical. They can be connected to the VDDOUT pin with decoupling capacitor. VDDBU pin. It powers the Slow Clock oscillator and the Real Time Clock, as well as a part of the System Controller; ranges from 3.0V and 3.6V, 3.3V nominal. VDDANA pin. It powers the ADC; ranges from 3.0V and 3.6V, 3.3V nominal.
• • •
Separated ground pins are provided for VDDPLL, VDDIO, VDDBU and VDDANA. The ground pins are respectively GNDPLL, GND, GNDBU and GNDANA.
Voltage Regulator
The AT91SAM7A3 embeds a voltage regulator that consumes less than 120 µA static current and draws up to 100 mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 3.3 µF (or 4.7 µF) X7R capacitor must be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.
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Typical Powering Schematics
3.3V Single Supply The AT91SAM7A3 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and VDDPLL. Figure 3 shows the power schematics to be used for USB bus-powered systems. Figure 3. 3.3V System Single Power Supply Schematics
VDDBU VDDANA DC/DC Converter USB Connector up to 5.5V 3.3V VDDOUT VDDIO VDDIN Voltage Regulator
VDDCORE VDDPLL
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Preliminary
I/O Lines Considerations
JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5V-tolerant, TDI is not. TMS, TDI and TCK do not integrate any resistors and have to be pulled-up externally. TDO is an output, driven at up to VDDIO. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor so that it can be left unconnected for normal operations.
Test Pin
The TST pin is used for manufacturing tests and integrates a pull-down resistor so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the NRST signal to reset all the components of the system. All the I/O lines PA0 to PA31 and PB0 to PB29 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage at up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, especially at reset, as all the I/O lines default as inputs with pull-up resistor enabled at reset.
Reset Pin
PIO Controller A and B Lines
Shutdown Logic Pins
The SHDW pin is an open drain output. It can be tied to VDDBU with an external pull-up resistor. The FWUP, WKUP0 and WKUP1 pins are input-only. They can accept voltages only between 0V and VDDBU. It is recommended to tie these pins either to GND or to VDDBU with an external resistor.
I/O Line Drive Levels
All the I/O lines can draw up to 2 mA.
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Processor and Architecture
ARM7TDMI Processor
• • RISC Processor Based on ARMv4T Von Neumann Architecture – – – • – – – Runs at up to 60 MHz, providing 0.9 MIPS/MHz ARM high-performance 32-bit Instruction Set Thumb high code density 16-bit Instruction Set Instruction Fetch (F) Instruction Decode (D) Execute (E) Two instruction sets
Three-stage pipeline architecture
Debug and Test Features •
Integrated embedded in-circuit emulator – – – Two watchpoint units Test access port accessible through a JTAG protocol Debug communication channel Two-pin UART Debug communication channel interrupt handling Chip ID Register
•
Debug Unit – – –
•
IEEE1149.1 JTAG Boundary-scan on all digital pins Bus Arbiter – Handles requests from the ARM7TDMI and the Peripheral Data Controller Three internal 1Mbyte memory areas One 256 Mbyte embedded peripheral area Source, Type and all parameters of the access leading to an abort are saved Facilitates debug by detection of bad pointers Alignment checking of all data accesses Abort generation in case of misalignment Remaps the Internal SRAM in place of the embedded non-volatile memory Allows handling of dynamic exception vectors Individually programmable size between 1K Bytes and 1M Bytes Individually programmable protection against write and/or user access Peripheral protection against write and/or user access Embedded Flash interface, up to three programmable wait states Address Decoder Provides Selection Signals for – –
Memory Controller
• •
•
Abort Status Registers – –
•
Misalignment Detector – –
•
Remap Command – –
•
16-area Memory Protection Unit – – –
•
Embedded Flash Controller –
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– – – – Read-optimized interface, buffering and anticipating the 16-bit requests, reducing the required wait states Password-protected program, erase and lock/unlock sequencer Automatic consecutive programming, erasing and locking operations Interrupt generation in case of forbidden operation
Peripheral Data Controller
• •
Handles data transfer between peripherals and memories Nineteen Channels – – – – – – Two for each USART Two for the Debug Unit Two for each Serial Synchronous Controller Two for each Serial Peripheral Interface One for the Multimedia Card Interface One for each Analog-to-Digital Converter One Master Clock cycle needed for a transfer from memory to peripheral Two Master Clock cycles needed for a transfer from peripheral to memory
•
Low bus arbitration overhead – –
•
Next Pointer management for reducing interrupt latency requirements
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Memory
Embedded Memories
• 256 Kbytes of Flash Memory – – – – – – • – 1024 pages of 256 bytes. Fast access time, 30 MHz single cycle access in worst case conditions. Page programming time: 4 ms, including page auto-erase Full erase time: 10 ms 10,000 write cycles, 10-year data retention capability 16 lock bits, each protecting 64 pages Single-cycle access at full speed
32 Kbytes of Fast SRAM
Memory Mapping
Internal RAM The AT91SAM7A3 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. The AT91SAM7A3 features one bank of 256 Kbytes of Flash. The Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command. Figure 4. Internal Memory Mapping
0x0000 0000
0x000F FFFF
Internal Flash
Flash Before Remap SRAM After Remap Internal Flash
1M Bytes
0x0010 0000 1M Bytes
0x001F FFFF
0x0020 0000 256M Bytes
0x002F FFFF 0x0030 0000
Internal SRAM
1M Bytes
Undefined Areas (Abort)
253M Bytes
0x0FFF FFFF
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Embedded Flash
Flash Organization The Flash block of the AT91SAM7A3 is organized in 1024 pages of 256 bytes. It reads as 65,536 32-bit words. The Flash block contains a 256-byte write buffer, accessible through a 32-bit interface. Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface mapped within the Memory Controller on the APB. The User Interface allows: • • • • • programming of the access parameters of the Flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors
The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. Lock Regions The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the Flash against inadvertent Flash erasing or programming commands. The AT91SAM7A3 has 16 lock regions. Each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 kbytes. The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.
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System Controller
The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.
Figure 5. System Controller Block Diagram
System Controller
irq0-irq1-irq2-irq3 fiq periph_irq[2..27] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd wdt_fault WDRPROC jtag_nreset
Boundary Scan TAP Controller
nirq nfiq
Advanced Interrupt Controller
proc_nreset int PCK debug
ARM7TDMI
ice_nreset dbgu_irq force_ntrst
Debug Unit
force_ntrst dbgu_txd
VDDIO POR VDDCORE POR
NRST
periph_nreset ice_nreset jtag_nreset flash_poe proc_nreset
Reset Controller
proc_nreset rstc_irq
Embedded Flash
VDDBU POR
SLCK
VDDCORE Powered Real-Time Timer
rtt_irq MCK proc_nreset
SLCK periph_nreset FWKUP WKUP0 WKUP1 SHDW
Memory Controller
Shutdown Controller VDDBU Powered RCOSC
SLCK
4 General-Purpose Backup Regs
XIN XOUT
MAIN OSC
MAINCK periph_clk[2..27] pck[0-3] UDPCK periph_clk[27] periph_nreset periph_irq[27]
PLLRC
PLL
int periph_nreset MCK debug periph_nreset SLCK debug idle proc_nreset periph_nreset periph_clk[2..3] dbgu_rxd
PLLCK
Power Management Controller
PCK UDPCK MCK pmc_irq idle
USB Device Port
Periodic Interval Timer Watchdog Timer
pit_irq periph_clk[4..26] periph_nreset
wdt_irq wdt_fault WDRPROC periph_irq{2..3] irq0-irq1-irq2-irq3
periph_irq[4..26]
Embedded Peripherals
PIOs Controller
fiq dbgu_txd in out enable
PA0-PA31 PB0-PB29
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Preliminary
System Controller Mapping
The System Controller peripherals are all mapped to the highest 4K bytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 6 shows the mapping of the System Controller and of the Memory Controller Figure 6. System Controller Mapping
Address
0xFFFF F000
Peripheral
Peripheral Name
Size
AIC
0xFFFF F1FF 0xFFFF F200
Advanced Interrupt Controller
512 Bytes/128 registers
DBGU
0xFFFF F3FF 0xFFFF F400
Debug Unit
512 Bytes/128 registers
PIOA
0xFFFF F5FF 0xFFFF F600
PIO Controller A
512 Bytes/128 registers
PIOB
0xFFFF F5FF 0xFFFF F800
PIO Controller B
512 Bytes/128 registers
Reserved
0xFFFF FBFF 0xFFFF FC00
PMC
0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD10 0xFFFF FC1F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FD80
Power Management Controller Reset Controller Shutdown Controller Real-time Timer Periodic Interval Timer Watchdog Timer
256 Bytes/64 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers
RSTC SHDWC RTT PIT WDT Reserved Reserved GPBR Reserved
General Purpose Backup Registers
16 Bytes/4 registers
0xFFFF FF00
MC
0xFFFF FFFF
Memory Controller
256 Bytes/64 registers
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Reset Controller
The Reset Controller is based on three power-on reset cells. It gives the status of the last reset, indicating whether it is a general reset, a wake-up reset, a software reset, a user reset or a watchdog reset. In addition, it controls the internal resets and the NRST pin output. It shapes a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: – – – – RC Oscillator ranges between 22 KHz and 42 KHz Main Oscillator frequency ranges between 3 and 20 MHz Main Oscillator can be bypassed PLL output ranges between 80 and 220 MHz
Clock Generator
It provides SLCK, MAINCK and PLLCK. Figure 7. Clock Generator Block Diagram
Clock Generator
Embedded RC Oscillator XIN XOUT
Slow Clock SLCK
Main Oscillator
Main Clock MAINCK
PLLRC
PLL and Divider
PLL Clock PLLCK Control
Status
Power Management Controller
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Preliminary
Power Management Controller
The Power Management Controller uses the Clock Generator outputs to provide: – – – – – the Processor Clock PCK the Master Clock MCK the USB Clock UDPCK all the peripheral clocks, independently controllable four programmable clock outputs
The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thereby reducing power consumption while waiting an interrupt. Figure 8. Power Management Controller Block Diagram
Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int
periph_clk[2..26]
Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64
pck[0..3]
USB Clock Controller ON/OFF PLLCK Divider /1,/2,/4
UDPCK
Advanced Interrupt Controller
• •
Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor Individually maskable and vectored interrupt sources – – – – – Source 0 is reserved for the Fast Interrupt Input (FIQ) Source 1 is reserved for system peripherals (ST, PMC, DBGU, etc.) Other sources control the peripheral interrupts or external interrupts Programmable edge-triggered or level-sensitive internal sources Programmable positive/negative edge-triggered or high/low level-sensitive external sources Drives the normal interrupt nIRQ of the processor Handles priority of the interrupt sources Higher priority interrupts can be served during service of a lower priority interrupt Optimizes interrupt service routine branch and execution
•
8-level Priority Controller – – –
•
Vectoring –
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– – • • • – – – One 32-bit vector register per interrupt source Interrupt vector register reads the corresponding current interrupt vector Easy debugging by preventing automatic operations Permits redirecting any interrupt source on the fast interrupt Provides processor synchronization on events without triggering an interrupt
Protect Mode Fast Forcing General Interrupt Mask
Debug Unit
•
Comprises – – – – One two-pin UART One interface for the Debug Communication Channel (DCC) support One set of chip ID registers One interface allowing ICE access prevention USART-compatible user interface Programmable baud rate generator Parity, framing and overrun error Automatic Echo, Local Loopback and Remote Loopback Channel Modes Offers visibility of COMMRX and COMMTX signals from the ARM Processor Identification of the device revision, sizes of the embedded memories, set of peripherals Chip ID is 0x170A0940 (Version 0)
•
Two-pin UART – – – –
• •
Debug Communication Channel Support – – – Chip ID Registers
Period Interval Timer Watchdog Timer
• • • •
20-bit programmable counter plus 12-bit interval counter 12-bit key-protected Programmable Counter running on prescaled SLCK Provides reset or interrupt signals to the system Counter may be stopped while the processor is in debug state or in idle mode 32-bit free-running counter with alarm Programmable 16-bit prescaler for SCLK accuracy compensation Software programmable assertion of the SHDW open-drain pin De-assertion programmable with the pins WKUP0, WKUP1 and FWKUP The PIO Controllers A and B respectively control 32 and 30 programmable I/O Lines Fully programmable through Set/Clear Registers Multiplexing of two peripheral functions per I/O Line For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – – Input change interrupt Half a clock period Glitch filter
Real-time Timer
• •
Shutdown Controller
• •
PIO Controllers A and B
• • • •
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– – – • Multi-drive option enables driving in open drain Programmable pull up on each I/O line Pin data status register, supplies visibility of the level on the pin at any time
Synchronous output, provides Set and Clear of several I/O lines in a single write
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Peripherals
Peripheral Mapping
Each User Peripheral is allocated 16K bytes of address space. Figure 9. User Peripherals Mapping
Address
0xF000 0000
Peripheral
Peripheral Name
Size
Reserved
0xFFF7 FFFF
0xFFF8 0000
0xFFF8 3FFF
CAN0
CAN Controller 0
16K Bytes
0xFFF8 4000
0xFFF8 7FFF 0xFFF8 8000
CAN1
CAN Controller 1
16K Bytes
Reserved
0xFFF9 FFFF
0xFFFA 0000
0xFFFA 3FFF
TC0, TC1, TC2
Timer/Counter 0, 1 and 2
16K Bytes
0xFFFA 4000
0xFFFA 7FFF
TC3, TC4, TC5
Timer/Counter 3, 4 and 5
16K Bytes
0xFFFA 8000
0xFFFA BFFF
TC6, TC7, TC8
Timer/Counter 6, 7 and 8
16K Bytes
0xFFFA C000
0xFFFA FFFF
MCI
Multimedia Card Interface
16K Bytes
0xFFFB 0000
0xFFFB 3FFF 0xFFFB 4000
UDP
USB Device Port
16K Bytes
Reserved
0xFFFB 7FFF
0xFFFB 8000
0xFFFB BFFF 0xFFFB C000
TWI
Two-Wire Interface
16K Bytes
Reserved 0xFFFC 0000
0xFFFB FFFF
USART0
0xFFFC 3FFF
Universal Synchronous Asynchronous Receiver Transmitter 0 Universal Synchronous Asynchronous Receiver Transmitter 1 Universal Synchronous Asynchronous Receiver Transmitter 1 PWM Controller Serial Synchronous Controller 0
16K Bytes
0xFFFC 4000
0xFFFC 7FFF
USART1
16K Bytes
0xFFFC 8000
USART2
16K Bytes
0xFFFC BFFF
0xFFFC C000 PWMC
0xFFFC FFFF
16K Bytes
0xFFFD 0000
0xFFFD 3FFF
SSC0
16K Bytes
0xFFFD 4000
0xFFFD 7FFF
SSC1
Serial Synchronous Controller 1
16K Bytes
0xFFFD 8000
0xFFFD BFFF
ADC0
Analog-to-Digital Converter 0
16K Bytes
0xFFFD C000
0xFFFD FFFF
ADC1
Analog-to-Digital Converter 1
16K Bytes
0xFFFE 0000
0xFFFE 3FFF
SPI0
Serial Peripheral Interface 0
16K Bytes
0xFFFE 4000
0xFFFE 7FFF 0xFFFE 8000
SPI1
Serial Peripheral Interface 1
16K Bytes
Reserved
0xFFFE FFFF
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Peripheral Multiplexing on PIO Lines
The AT91SAM7A3 features two PIO controllers, PIOA and PIOB, which multiplex the I/O lines of the peripheral set. PIO Controllers A and B control respectively 32 and 30 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with Analog Input of both ADC Controllers. Table 3 on page 23 and Table 4 on page 24 define how the I/O lines of the peripherals A, B or Analog Input are multiplexed on the PIO Controllers A and B. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only may be duplicated within both tables. At reset, all I/O lines are automatically configured as input with the programmable pullup enabled, so that the device is maintained in a static state as soon as a reset occurs.
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PIO Controller A Multiplexing
Table 3. Multiplexing on PIO Controller A
PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A TWD TWCK RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 RXD2 TXD2 NPCS00 NPCS01 NPCS02 NPCS03 MISO0 MOSI0 SPCK0 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 CANRX0 CANTX0 CANRX1 CANTX1 DRXD DTXD TCLK3 TCLK6 TCLK7 TCLK8 MCDA1 MCDA2 MCDA3 MCDA0 MCCDA MCCK PCK0 PCK1 PCK2 PCK3 IRQ0 IRQ1 TCLK4 TCLK5 NPSC10 NPCS11 NPCS12 NPCS13 MISO1 MOSI1 SPCK1 Peripheral B ADTRG0 ADTRG1 Comment Function Application Usage Comments
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PIO Controller B Multiplexing
Table 4. Multiplexing on PIO Controller B
PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 Peripheral A IRQ2 IRQ3 TF0 TK0 TD0 RD0 RK0 RF0 FIQ TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TIOA3 TIOB3 TIOA4 TIOB4 TIOA5 TIOB5 TIOA6 TIOB6 TIOA7 TIOB7 TIOA8 TIOB8 RTS1 CTS1 SCK1 RTS2 CTS2 SCK2 Peripheral B PWM5 PWM6 PWM7 PCK0 PCK1 PCK2 PCK3 CANTX1 TF1 TK1 RK1 RF1 TD1 RD1 PWM0 PWM1 PWM2 PWM3 PWM4 NPCS11 NPCS12 NPCS13 AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 Comment Function Application Usage Comments
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Peripheral Identifiers
The AT91SAM7A3 embeds a wide range of peripherals. Table 5 defines the Peripheral Identifiers of the AT91SAM7A3. Unique peripheral identifiers are defined for both the AIC and the PMC. Table 5. Peripheral Identifiers
Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Peripheral Mnemonic AIC SYSIRQ PIOA PIOB CAN0 CAN1 US0 US1 US2 MCI TWI SPI0 SPI1 SSC0 SSC1 TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7 TC8 ADC0 ADC1
(1) (1) (1)
Peripheral Name Advanced Interrupt Controller
External Interrupt FIQ
Parallel I/O Controller A Parallel I/O Controller B CAN Controller 0 CAN Controller 1 USART 0 USART 1 USART 2 Multimedia Card Interface Two-wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Timer/Counter 3 Timer/Counter 4 Timer/Counter 5 Timer/Counter 6 Timer/Counter 7 Timer/Counter 8 Analog-to Digital Converter 0 Analog-to Digital Converter 1 PWM Controller USB Device Port Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 IRQ3
PWMC UDP AIC AIC AIC AIC
Note:
1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller and ADC are continuously clocked.
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Serial Peripheral Interface
• Supports communication with external serial devices – – – – • – – – – – – Four chip selects with external decoder allow communication with up to 15 peripherals Serial memories, such as DataFlash® and 3-wire EEPROMs Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors External co-processors 8- to 16-bit programmable data length per chip select Programmable phase and polarity per chip select Programmable transfer delays per chip select between consecutive transfers and between clock and data Programmable delay between consecutive transfers Selectable mode fault detection Maximum frequency at up to Master Clock
Master or slave serial peripheral bus interface
Two-wire Interface
• • • •
Master Mode only Compatibility with standard two-wire serial memories One, two or three bytes for slave address Sequential read/write operations Programmable Baud Rate Generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications – – – – – – – – – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode Parity generation and error detection Framing error detection, overrun error detection MSB- or LSB-first Optional break generation and detection By 8 or by 16 over-sampling receiver frequency Hardware handshaking RTS-CTS Receiver time-out and transmitter timeguard Optional Multi-drop Mode with address generation and detection
USART
• •
• • • •
RS485 with driver control signal ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – – – NACK handling, error counter with repetition and iteration limit Communication at up to 115.2 Kbps Remote Loopback, Local Loopback, Automatic Echo IrDA modulation and demodulation Test Modes
Serial Synchronous Controller
• •
Provides serial synchronous communication links used in audio and telecom applications Contains an independent receiver and transmitter and a common clock divider
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• • • Offers a configurable frame sync and data length Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal Three 16-bit Timer Counter Channels Wide range of functions including: – – – – – – – • – – Frequency Measurement Event Counting Interval Measurement Pulse Generation Delay Timing Pulse Width Modulation Up/down Capabilities Three external clock inputs Five internal clock inputs as defined in Table 6.
Timer Counter
• •
Each channel is user-configurable and contains:
Table 6. Timer Counter Clock Assignment
TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024
– –
Two multi-purpose input/output signals Two global registers that act on all three TC Channels
PWM Controller
• •
Eight channels, one 20-bit counter per channel Common clock generator, providing thirteen different clocks – – A Modulo n counter providing eleven clocks Two independent linear dividers working on modulo n counter outputs Independent enable/disable commands Independent clock selection Independent period and duty cycle, with double buffering Programmable selection of the output waveform polarity Programmable center or left aligned output waveform
•
Independent channel programming – – – – –
USB Device Port
• • •
USB V2.0 full-speed compliant,12 Mbits per second. Embedded USB V2.0 full-speed transceiver Six endpoints
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– – – – • • – Endpoint 0: 8 bytes Endpoint 1 and 2: 64 bytes ping-pong Endpoint 3: 64 bytes Endpoint 4 and 5: 512 bytes ping-pong Ping-pong Mode (two memory banks) for isochronous and bulk endpoints
Embedded 2,376-byte dual-port RAM for endpoints Suspend/resume logic Compatibility with MultiMedia card specification version 2.2 Compatibility with SD Memory card specification version 1.0 Cards clock rate up to Master Clock divided by 2 Embeds power management to slow down clock rate when not used Supports up to sixteen slots (through multiplexing) – One slot for one MultiMedia card bus (up to 30 cards) or one SD memory card
Multimedia Card Interface
• • • • •
• •
Supports stream, block and multi-block data read and write Supports connection to Peripheral Data Controller – Minimizes processor intervention for large buffer transfers
CAN Controller
• • •
Fully compliant with CAN 2.0B active controllers Bit rates up to 1Mbit/s 16 object-oriented mailboxes, each with the following properties: – – – – – – – – – – – – CAN specification 2.0 Part A or 2.0 Part B programmable for each message Object-configurable as receive (with overwrite or not) or transmit Local tag and mask filters up to 29-bit identifier/channel 32-bit access to data registers for each mailbox data object Uses a 16-bit time stamp on receive and transmit messages Hardware concatenation of ID unmasked bit fields to speed up family ID processing 16-bit internal timer for Time Stamping and Network synchronization Programmable reception buffer length up to 16 mailbox object Priority management between transmission mailboxes Autobaud and listening mode Low power mode and programmable wake-up on bus activity or by the application Data, remote, error and overload frame handling
Analog-to-Digital Converter
• • • • • •
8-channel ADC 10-bit 384K samples/sec Successive Approximation Register ADC -2/+2 LSB Integral Non Linearity, -1/+2 LSB Differential Non Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs Individual enable and disable of each channel External voltage reference for better accuracy on low-voltage inputs
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• Multiple trigger sources – – – • – • Hardware or software trigger External pins: ADTRG0 and ADTRG1 Timer Counter 0 to 5 outputs: TIOA0 to TIOA5 Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels
Sleep Mode and conversion sequencer
All analog inputs are shared with digital signals
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ARM7TDMI Processor Overview
Overview
The ARM7TDMI core executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density. The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages. The main features of the ARM7TDMI processor are: • • ARM7TDMI Based on ARMv4T Architecture Two Instruction Sets – – • – – – ARM High-performance 32-bit Instruction Set Thumb High Code Density 16-bit Instruction Set Instruction Fetch (F) Instruction Decode (D) Execute (E)
Three-Stage Pipeline Architecture
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ARM7TDMI Processor
For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B)
Instruction Type Data Type
Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries. Unaligned data access behavior depends on which instruction is used where.
ARM7TDMI Operating Mode
The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes: User: The normal ARM program execution state FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system Abort mode: Implements virtual memory and/or memory protection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources.
ARM7TDMI Registers
The ARM7TDMI processor has a total of 37registers: • • 31 general-purpose 32-bit registers 6 status registers
These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer. At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer
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. Table 7. ARM7TDMI ARM Modes and Registers Layout
User and System Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC
Supervisor Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC
Abort Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC
Undefined Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC
Interrupt Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC
Fast Interrupt Mode
R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC
CPSR
CPSR SPSR_SVC
CPSR SPSR_ABORT
CPSR SPSR_UNDEF
CPSR SPSR_IRQ
CPSR SPSR_FIQ
Mode-specific banked registers
Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a general-purpose register to be specified. Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor. Modes and Exception Handling All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers.
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A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: • • • • four ALU flags (Negative, Zero, Carry, and Overflow) two interrupt disable bits (one for each type of interrupt) one bit to indicate ARM or Thumb execution five bits to encode the current processor mode
All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception. Exception Types
The ARM7TDMI s upports five types of exception and a privileged processing mode for each type. The types of exceptions are:
• • • • •
fast interrupt (FIQ) normal interrupt (IRQ) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupts (SWIs)
Exceptions are generated by internal and external sources. More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state. To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways: • • by using a data-processing instruction with the S-bit set, and the PC as the destination by using the Load Multiple with Restore CPSR instruction (LDM)
ARM Instruction Set Overview
The ARM instruction set is divided into: • • • • • • Branch instructions Data processing instructions Status register transfer instructions Load and Store instructions Coprocessor instructions Exception-generating instructions
ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 8 gives the ARM instruction mnemonic list.
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Table 8. ARM Instruction Mnemonic List
Mnemonic
MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC
Operation
Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor
Mnemonic
CDP MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR STRH STRB STRBT STRT STM SWPB MRC STC
Operation
Coprocessor Data Processing Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor
Thumb Instruction Set Overview
The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • • • • • Branch instructions Data processing instructions Load and Store instructions Load and Store Multiple instructions Exception-generating instruction
In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14)
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and the Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 9 gives the Thumb instruction mnemonic list. Table 9. Thumb Instruction Mnemonic List
Mnemonic
MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH
Operation
Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack
Mnemonic
MVN ADC SBC CMN NEG BIC ORR LSR ROR
Operation
Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right
BL SWI STR STRH STRB LDRSB STMIA POP
Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack
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AT91SAM7A3 Debug and Test Features
Overview
The AT91SAM7A3 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.
Block Diagram
Figure 10. Debug and Test Block Diagram
TMS TCK TDI
Boundary TAP
ICE/JTAG TAP
JTAGSEL TDO
ICE
Reset and Test
POR TST
ARM7TDMI
PIO
DTXD DRXD
PDC
DBGU
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Application Examples
Debug Environment
Figure 11 on page 38 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 11. Application Debug Environment Example
Host Debugger ICE/JTAG Interface
ICE/JTAG Connector
AT91SAM7A3
RS232 Connector
Terminal
AT91SAM7A3-based Application Board
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Test Environment
Figure 12 on page 39 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 12. Application Test Environment Example
Test Adaptor
Tester
JTAG Interface
ICE/JTAG Connector
Chip n
Chip 2
AT91SAM7A3
Chip 1
AT91SAM7A3-based Application Board In Test
Debug and Test Pin Description
Table 10. D ebug and Test Pin List
Pin Name Function Reset/Test NRST TST Microcontroller Reset Test Mode Select ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Input Input Output Input Input Input/Output Input Low High Type Active Level
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Functional Description
Test Pin
One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. The ARM7TDMI embedded In-circuit Emulator is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is examined through an ICE/JTAG port. The ARM7TDMI processor contains hardware extensions for advanced debugging features: • In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system. In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor.
Embedded Incircuit Emulator
•
There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).
Debug Unit
The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. The Debug Unit can be used to upload an application into the internal SRAM. It is activated by the boot program when no valid application is detected. The protocol used to load the application is XMODEM. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM7A3 Debug Unit Chip ID value is 0x170a940 on 32-bit width For further details on the Debug Unit, see the Debug Unit section.
IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed.
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A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 186 bits that correspond to active pins and associated control signals. Each AT91SAM7A3 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 11. AT91SAM7A3 JTAG Boundary Scan Register
Bit Number 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 PB5 IN/OUT PB6 IN/OUT PB7 IN/OUT PB8 IN/OUT PB9 IN/OUT PB10 IN/OUT PB11 IN/OUT PB12 IN/OUT PB13 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 11. AT91SAM7A3 JTAG Boundary Scan Register (Continued)
Bit Number 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 PA5 IN/OUT PA4 IN/OUT PA3 IN/OUT PA2 IN/OUT PA1 IN/OUT PA0 IN/OUT PB0 IN/OUT PB1 IN/OUT PB2 IN/OUT PB3 IN/OUT PB4 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 11. AT91SAM7A3 JTAG Boundary Scan Register (Continued)
Bit Number 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 PA16 IN/OUT PA15 IN/OUT PA14 IN/OUT PA13 IN/OUT PA12 IN/OUT PA11 IN/OUT PA10 IN/OUT PA9 IN/OUT PA8 IN/OUT PA7 IN/OUT PA6 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 11. AT91SAM7A3 JTAG Boundary Scan Register (Continued)
Bit Number 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 PA27 IN/OUT PA26 IN/OUT PA25 IN/OUT PA24 IN/OUT PA23 IN/OUT PA22 IN/OUT PA21 IN/OUT PA20 IN/OUT PA19 IN/OUT PA18 IN/OUT PA17 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 11. AT91SAM7A3 JTAG Boundary Scan Register (Continued)
Bit Number 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 PB20 IN/OUT PB19 IN/OUT PB18 IN/OUT PB17 IN/OUT PB16 IN/OUT PB15 IN/OUT PB14 IN/OUT PA31 IN/OUT PA30 IN/OUT PA29 IN/OUT PA28 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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Table 11. AT91SAM7A3 JTAG Boundary Scan Register (Continued)
Bit Number 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PB29 IN/OUT PB28 IN/OUT PB27 IN/OUT PB26 IN/OUT PB25 IN/OUT PB24 IN/OUT PB23 IN/OUT PB22 IN/OUT PB21 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL
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ID Code Register
Access: Read-only
31 30 29 28 27 26 25 24
VERSION
23 22 21 20 19
PART NUMBER
18 17 16
PART NUMBER
15 14 13 12 11 10 9 8
PART NUMBER
7 6 5 4 3
MANUFACTURER IDENTITY
2 1 0
MANUFACTURER IDENTITY
1
VERSION[31:28]: Product Version Number Set to 0x1. PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B05 MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B0503F
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6042A–ATARM–23-Dec-04
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Reset Controller (RSTC)
Overview
The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.
Block Diagram
Figure 13. Reset Controller Block Diagram
Reset Controller
Main Supply POR Backup Supply POR Startup Counter rstc_irq Reset State Manager proc_nreset
user_reset
NRST
nrst_out
NRST Manager
exter_nreset
periph_nreset
backup_neset WDRPROC wd_fault
SLCK
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6042A–ATARM–23-Dec-04
Functional Description
The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • • • • proc_nreset: Processor reset line. It also resets the Watchdog Timer. backup_nreset: Affects all the peripherals powered by VDDBU. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on.
NRST Manager
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14 shows the block diagram of the NRST Manager. Figure 14. NRST Manager
RSTC_MR RSTC_SR
URSTIEN rstc_irq
RSTC_MR
URSTS NRSTL
Other interrupt sources user_reset
URSTEN
NRST
RSTC_MR
ERSTL nrst_out External Reset Timer exter_nreset
NRST Signal or Interrupt
The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.
NRST External Reset Control
The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) S low Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.
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This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator.
Reset States
The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. A general reset occurs when VDDBU is powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remains valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shut down. Figure 15 shows how the General Reset affects the reset signals.
General Reset
Figure 15. General Reset State
SLCK MCK Backup Supply POR output
Any Freq.
Startup Time
backup_nreset
Processor Startup = 3 cycles
proc_nreset RSTTYP periph_nreset
XXX
0x0 = General Reset
XXX
NRST (nrst_out)
EXTERNAL RESET LENGTH = 2 cycles
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6042A–ATARM–23-Dec-04
Wake-up Reset
The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then reenabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR. Figure 16. Wake-up State
SLCK MCK Main Supply POR output
Any Freq.
backup_nreset
Resynch. 2 cycles Processor Startup = 3 cycles
proc_nreset
RSTTYP
XXX
0x1 = WakeUp Reset
XXX
periph_nreset
NRST (nrst_out)
EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1)
User Reset
The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. Th e NR ST Man age r gua rante es th at the NR ST line is asser te d for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. How-
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ever, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 17. User Reset State
SLCK MCK
Any Freq.
NRST
Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles
proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset
NRST (nrst_out)
>= EXTERNAL RESET LENGTH
Software Reset
The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR).
•
The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset
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6042A–ATARM–23-Dec-04
is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 18. Software Reset
SLCK MCK
Any Freq.
Write RSTC_CR
Resynch. 1 cycle Processor Startup = 3 cycles
proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1
EXTERNAL RESET LENGTH 8 cycles (ERSTL=2)
Any
XXX
0x3 = Software Reset
SRCMP in RSTC_SR
Watchdog Reset
The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. If WDRPROC = 1, only the processor reset is asserted.
•
The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.
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Figure 19. Watchdog Reset
SLCK MCK
Any Freq.
wd_fault
Processor Startup = 3 cycles
proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset
NRST (nrst_out)
EXTERNAL RESET LENGTH 8 cycles (ERSTL=2)
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Reset State Priorities
The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • • • • • • Backup Reset Wake-up Reset Watchdog Reset Software Reset User Reset When in User Reset: – – • – – • – – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated. A watchdog event has priority over the current state. The NRST has no effect. The processor reset is active and so a Software Reset cannot be programmed. A User Reset cannot be entered.
Particular cases are listed below:
When in Software Reset:
When in Watchdog Reset:
Reset Controller Status Register
The Reset Controller status register (RSTC_SR) provides several status fields: • • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 20). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.
• •
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Figure 20. Reset Controller Status and Interrupt
MCK read RSTC_SR
Peripheral Access
2 cycle resynchronization NRST NRSTL
2 cycle resynchronization
URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1)
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Reset Controller (RSTC) User Interface
Table 12. R eset Controller (RSTC) Register Mapping
Offset 0x00 0x04 0x08 Note: Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0001 0x0000_0000 0x0000_0000 Back-up Reset Value
1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply.
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Reset Controller Control Register
Register Name: RSTC_CR Access Type:
31
W rite-only
30 29 28 KEY 27 26 25 24
23 – 15 – 7 –
22 – 14 – 6 –
21 – 13 – 5 –
20 – 12 – 4 –
19 – 11 – 3 EXTRST
18 – 10 – 2 PERRST
17 – 9
16 – 8 – 0 PROCRST
1 –
• PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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Reset Controller Status Register
Register Name: RSTC_SR Access Type:
31 – 23 – 15 – 7 –
Read-only
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 25 – 17 SRCMP 9 RSTTYP 1 – 24 – 16 NRSTL 8
2 –
0 URSTS
• URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.
RSTTYP 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0
Reset Type General Reset Wake Up Reset Watchdog Reset Software Reset User Reset
Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low
• NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = N o software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy.
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Reset Controller Mode Register
Register Name: RSTC_MR Access Type:
31
Read/Write
30 29 28 KEY 27 26 25 24
23 – 15 – 7 –
22 – 14 – 6 –
21 – 13 – 5 –
20 – 12 – 4 URSTIEN
19 – 11
18 – 10 ERSTL
17 – 9
16 – 8
3 –
2 –
1 –
0 URSTEN
• URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation.
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Real-time Timer (RTT)
Overview Block Diagram
Figure 21. Real-time Timer
RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm
The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value.
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Functional Description
The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is reached by writing RTPRES at 1. In this case, the period of the signal provided to the Real-time Timer counter is 30.52 µs (when Slow Clock is 32.768 Hz) and the maximum the Real-time Timer can cover is 131072 seconds, corresponding to more than 36 days. The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm reg ister is se t to its ma ximum value, co rrespo nding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
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Figure 22. RTT Counting
APB cycle APB cycle
MCK
RTPRES - 1 Prescaler 0
RTT
0
...
ALMV-1
ALMV
ALMV+1
ALMV+2
ALMV+3
RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface
read RTT_SR
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Real-time Timer (RTT) User Interface
Table 13. R eal-time Timer Register Mapping
Offset 0x00 0x04 0x08 0x0C Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000
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Real-time Timer Mode Register
Register Name: RTT_MR Access Type:
31 – 23 – 15
Read/Write
30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RTPRES 27 – 19 – 11 26 – 18 RTTRST 10 25 – 17 RTTINCIEN 9 24 – 16 ALMIEN 8
7
6
5
4 RTPRES
3
2
1
0
• RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows: RTPRES = 0: The Prescaler Period is equal to 216 RTPRES ≠ 0: The Prescaler Period is equal to RTPRES. • ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.
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Real-time Timer Alarm Register
Register Name: RTT_AR Access Type:
31
Read/Write
30 29 28 ALMV 27 26 25 24
23
22
21
20 ALMV
19
18
17
16
15
14
13
12 ALMV
11
10
9
8
7
6
5
4 ALMV
3
2
1
0
• ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer.
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Real-time Timer Value Register
Register Name: RTT_VR Access Type:
31
Read-only
30 29 28 CRTV 27 26 25 24
23
22
21
20 CRTV
19
18
17
16
15
14
13
12 CRTV
11
10
9
8
7
6
5
4 CRTV
3
2
1
0
• CRTV: Current Real-time Value Returns the current value of the Real-time Timer.
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Real-time Timer Status Register
Register Name: RTT_SR Access Type:
31 – 23 – 15 – 7 –
Read-only
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 RTTINC 24 – 16 – 8 – 0 ALMS
• ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR.
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Periodic Interval Timer (PIT)
Overview
The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time.
Block Diagram
Figure 23. Periodic Interval Timer
PIT_MR
PIV
=?
PIT_MR
PITIEN
set
0
PIT_SR
PITS
reset
pit_irq
0
0
1
0
1
12-bit Adder
read PIT_PIVR
MCK
20-bit Counter
Prescaler
MCK/16
CPIV
PIT_PIVR
PICNT
CPIV
PIT_PIIR
PICNT
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Functional Description
The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 24 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state.
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Figure 24. Enabling/Disabling PIT with PITEN
APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle
CPIV PICNT PITS (PIT_SR) APB Interface
0
1 0
PIV - 1
PIV 1
0 0
1
read PIT_PIVR
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Periodic Interval Timer (PIT) User Interface
Table 14. Periodic Interval Timer (PIT) Register Mapping
Offset 0x00 0x04 0x08 0x0C Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000
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Periodic Interval Timer Mode Register
Register Name: PIT_MR Access Type:
31 – 23 – 15
Read/Write
30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 PIV 27 – 19 26 – 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16
7
6
5
4 PIV
3
2
1
0
• PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt.
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Periodic Interval Timer Status Register
Register Name: PIT_SR Access Type:
31 – 23 – 15 – 7 –
Read-only
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 PITS
• PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.
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Periodic Interval Timer Value Register
Register Name: PIT_PIVR Access Type:
31
Read-only
30 29 28 PICNT 27 26 25 24
23
22 PICNT
21
20
19
18 CPIV
17
16
15
14
13
12 CPIV
11
10
9
8
7
6
5
4 CPIV
3
2
1
0
Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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Periodic Interval Timer Image Register
Register Name: PIT_PIIR Access Type:
31
Read-only
30 29 28 PICNT 27 26 25 24
23
22 PICNT
21
20
19
18 CPIV
17
16
15
14
13
12 CPIV
11
10
9
8
7
6
5
4 CPIV
3
2
1
0
• CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
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Watchdog Timer (WDT)
Overview
The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.
Block Diagram
Figure 25. Watchdog Timer Block Diagram
write WDT_MR WDT_MR WDT_CR
WV
reload 1 0
WDRSTT
12-bit Down Counter
WDT_MR reload
WDD
Current Value
1/128
SLCK
1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock
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Receiver
Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. Figure 2. Start Bit Detection
Sampling Clock
DRXD
True Start Detection Baud Rate Clock
D0
Figure 3. Character Reception
Example: 8-bit, parity enabled 1 stop
0.5 bit period 1 bit period
DRXD
Sampling
D0 D1 True Start Detection
D2
D3
D4
D5
D6
D7 Parity Bit
Stop Bit
Receiver Ready
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read.
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Figure 4. Receiver Ready
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P
RXRDY
Read DBGU_RHR
Receiver Overrun
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 5. Receiver Overrun
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY OVRE
RSTSTA
Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 6. Parity Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY PARE
Wrong Parity Bit
RSTSTA
Receiver Framing Error
When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 7. Receiver Framing Error
DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop
RXRDY FRAME
Stop Bit Detected at 0
RSTSTA
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Transmitter
Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 8. Character Transmission
Example: Parity enabled Baud Rate Clock DTXD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
Transmitter Control
When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed.
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Figure 9. Transmitter Control
DBGU_THR
Data 0 Data 1
Shift Register
Data 0
Data 1
DTXD
S
Data 0
P
stop
S
Data 1
P
stop
TXRDY TXEMPTY
Write Data 0 in DBGU_THR
Write Data 1 in DBGU_THR
Peripheral Data Controller
Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR.
Test Modes
The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission.
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Figure 10. Test Modes
Automatic Echo Receiver RXD
Transmitter
Disabled
TXD
Local Loopback Receiver
Disabled
RXD
VDD Transmitter
Disabled
TXD
Remote Loopback Receiver
VDD Disabled RXD
Transmitter
Disabled
TXD
Debug Communication Channel Support
The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel:
MRC p14, 0, Rd, c1, c0, 0
Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0
Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger.
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Chip Identifier
The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: • • • • • • EXT - shows the use of the extension identifier register NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size ARCH - identifies the set of embedded peripheral SRAMSIZ - indicates the size of the embedded SRAM EPROC - indicates the embedded ARM processor VERSION - gives the revision of the silicon
The second register is device-dependent and reads 0 if the bit EXT is 0.
ICE Access Prevention
The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible.
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Debug Unit (DBGU) User Interface
Table 27. D ebug Unit (DBGU) Register Mapping
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 - 0x003C 0X0040 0X0044 0X0048 0x004C - 0x00FC 0x0100 - 0x0124 Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Force NTRST Register Reserved PDC Area Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR – DBGU_CIDR DBGU_EXID DBGU_FNR – – Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write – Read-only Read-only Read/Write – – Reset Value – 0x0 – – 0x0 – 0x0 – 0x0 – – – 0x0 – –
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Debug Unit Control Register
Name: Access Type:
31
DBGU_CR Write-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8 RSTSTA 0
–
7 TXDIS
–
6 TXEN
–
5 RXDIS
–
4 RXEN
–
3 RSTTX
–
2 RSTRX
–
1
–
–
• RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. • RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. • RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. • RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. • TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. • TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. • RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR.
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Debug Unit Mode Register
Name: Access Type:
31
DBGU_MR Read/Write
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15 CHMODE 7
–
14
–
13
–
12
–
11
–
10 PAR
–
9
–
8
–
6 5
–
4 3
–
1 0
2
–
–
–
–
–
–
–
–
• PAR: Parity Type
PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity
• CHMODE: Channel Mode
CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback
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Debug Unit Interrupt Enable Register
Name: Access Type:
31 COMMRX 23
DBGU_IER Write-only
30 COMMTX 22 29 28 27 26 25 24
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12 RXBUFF 4 ENDTX
–
11 TXBUFE 3 ENDRX
–
10
–
9 TXEMPTY 1 TXRDY
–
8
–
7 PARE
–
6 FRAME
–
5 OVRE
–
2
–
0 RXRDY
–
• RXRDY: Enable RXRDY Interrupt • TXRDY: Enable TXRDY Interrupt • ENDRX: Enable End of Receive Transfer Interrupt • ENDTX: Enable End of Transmit Interrupt • OVRE: Enable Overrun Error Interrupt • FRAME: Enable Framing Error Interrupt • PARE: Enable Parity Error Interrupt • TXEMPTY: Enable TXEMPTY Interrupt • TXBUFE: Enable Buffer Empty Interrupt • RXBUFF: Enable Buffer Full Interrupt • COMMTX: Enable COMMTX (from ARM) Interrupt • COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt.
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Debug Unit Interrupt Disable Register
Name: Access Type:
31 COMMRX 23
DBGU_IDR Write-only
30 COMMTX 22 29 28 27 26 25 24
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12 RXBUFF 4 ENDTX
–
11 TXBUFE 3 ENDRX
–
10
–
9 TXEMPTY 1 TXRDY
–
8
–
7 PARE
–
6 FRAME
–
5 OVRE
–
2
–
0 RXRDY
–
• RXRDY: Disable RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Disable End of Receive Transfer Interrupt • ENDTX: Disable End of Transmit Interrupt • OVRE: Disable Overrun Error Interrupt • FRAME: Disable Framing Error Interrupt • PARE: Disable Parity Error Interrupt • TXEMPTY: Disable TXEMPTY Interrupt • TXBUFE: Disable Buffer Empty Interrupt • RXBUFF: Disable Buffer Full Interrupt • COMMTX: Disable COMMTX (from ARM) Interrupt • COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt.
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Debug Unit Interrupt Mask Register
Name: Access Type:
31 COMMRX 23
DBGU_IMR Read-only
30 COMMTX 22 29 28 27 26 25 24
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12 RXBUFF 4 ENDTX
–
11 TXBUFE 3 ENDRX
–
10
–
9 TXEMPTY 1 TXRDY
–
8
–
7 PARE
–
6 FRAME
–
5 OVRE
–
2
–
0 RXRDY
–
• RXRDY: Mask RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Mask End of Receive Transfer Interrupt • ENDTX: Mask End of Transmit Interrupt • OVRE: Mask Overrun Error Interrupt • FRAME: Mask Framing Error Interrupt • PARE: Mask Parity Error Interrupt • TXEMPTY: Mask TXEMPTY Interrupt • TXBUFE: Mask TXBUFE Interrupt • RXBUFF: Mask RXBUFF Interrupt • COMMTX: Mask COMMTX Interrupt • COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
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6042A–ATARM–23-Dec-04
Debug Unit Status Register
Name: Access Type:
31 COMMRX 23
DBGU_SR Read-only
30 COMMTX 22 29 28 27 26 25 24
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12 RXBUFF 4 ENDTX
–
11 TXBUFE 3 ENDRX
–
10
–
9 TXEMPTY 1 TXRDY
–
8
–
7 PARE
–
6 FRAME
–
5 OVRE
–
2
–
0 RXRDY
–
• RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. • TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. • ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active. • ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. • OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. • PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. • TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active.
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• RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active.
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6042A–ATARM–23-Dec-04
Debug Unit Receiver Holding Register
Name: Access Type:
31
DBGU_RHR Read-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4 RXCHR
–
3
–
2
–
1
–
0
• RXCHR: Received Character Last received character if RXRDY is set.
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Debug Unit Transmit Holding Register
Name: Access Type:
31
DBGU_THR Write-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4 TXCHR
–
3
–
2
–
1
–
0
• TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
Debug Unit Baud Rate Generator Register
Name: Access Type:
31
DBGU_BRGR Read/Write
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12 CD
–
11
–
10
–
9
–
8
7
6
5
4 CD
3
2
1
0
• CD: Clock Divisor
CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16)
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Debug Unit Chip ID Register
Name: Access Type:
31 EXT 23 22 ARCH 15 14 NVPSIZ2 7 6 EPROC 5 4 3 2 VERSION 13 12 11 10 NVPSIZ 1 0
DBGU_CIDR Read-only
30 29 NVPTYP 21 20 19 18 SRAMSIZ 9 8 28 27 26 ARCH 17 16 25 24
• VERSION: Version of the device • EPROC: Embedded Processor
EPROC 0 0 1 1 0 1 0 0 1 0 0 1 Processor ARM946ES ARM7TDMI ARM920T ARM926EJS
• NVPSIZ: Nonvolatile Program Memory Size
NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved
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• NVPSIZ2: Second Nonvolatile Program Memory Size
NVPSIZ2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved
• SRAMSIZ: Internal SRAM Size
SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes Reserved Reserved 4K bytes Reserved 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 128K bytes 256K bytes 96K bytes 512K bytes
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• ARCH: Architecture Identifier
ARCH Hex 0x40 0x63 0x55 0x42 0x92 0x34 0x70 0x71 0x72 0x73 0x19 Bin 0100 0000 0110 0011 0101 0101 0100 0010 1001 0010 0011 0100 0111 0000 0111 0001 0111 0010 0111 0011 0001 1001 Architecture AT91x40 Series AT91x63 Series AT91x55 Series AT91x42 Series AT91x92 Series AT91x34 Series AT91SAM7Sxx and AT91SAM7Axx Series AT91SAM7Xxx Series AT91SAM7Exx Series AT91SAM7Lxx Series AT91SAM9xx Series
• NVPTYP: Nonvolatile Program Memory Type
NVPTYP 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 Memory ROM ROMless or on-chip Flash SRAM emulating ROM Embedded Flash Memory ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size
• EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists.
Debug Unit Chip ID Extension Register
Name: Access Type:
31
DBGU_EXID Read-only
30 29 28 EXID 27 26 25 24
23
22
21
20 EXID
19
18
17
16
15
14
13
12 EXID
11
10
9
8
7
6
5
4 EXID
3
2
1
0
• EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0.
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Debug Unit Force NTRST Register
Name: Access Type:
31
DBGU_FNR Read/Write
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0 FNTRST
–
–
–
–
–
–
–
• FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the ice_nreset signal. 1 = NTRST of the ARM processor’s TAP controller is held low.
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Parallel Input/Output Controller (PIO)
Overview
The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: • • • • • An input change interrupt enabling level change detection on any I/O line. A glitch filter providing rejection of pulses lower than one-half of clock cycle. Multi-drive capability similar to an open drain I/O line. Control of the the pull-up of the I/O line. Input visibility and output control.
The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation.
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Block Diagram
Figure 11. Block Diagram
PIO Controller
AIC PIO Interrupt
PMC
PIO Clock
Data, Enable
Embedded Peripheral
Up to 32 peripheral IOs
PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31
APB
Application Block Diagram
Figure 12. Application Block Diagram
On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals
PIO Controller
Keyboard Driver General Purpose I/Os External Devices
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Product Dependencies
Pin Multiplexing
Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product.
External Interrupt Lines
The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information.
Power Management
Interrupt Generation
For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled.
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Functional Description
The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 13. In this description each signal shown represents but one of up to 32 possible indexes.
Figure 13. I/O Line Control Logic
PIO_OER[0] PIO_OSR[0] PIO_ODR[0]
1
PIO_PUER[0] PIO_PUSR[0] PIO_PUDR[0]
Peripheral A Output Enable Peripheral B Output Enable PIO_ASR[0] PIO_ABSR[0] PIO_BSR[0] Peripheral A Output Peripheral B Output
0
0 0
1 PIO_PER[0] PIO_PSR[0] PIO_PDR[0] 0
0
1
PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 1
1
1
PIO_SODR[0] PIO_ODSR[0] PIO_CODR[0]
Pad 0
Peripheral A Input Peripheral B Input
PIO_PDSR[0] 0 Edge Detector Glitch Filter PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] 1
PIO_ISR[0]
(Up to 32 possible inputs) PIO Interrupt
PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31]
Pull-up Resistor Control
206
Each I/O line is designed with an embedded pull-up resistor. The value of this resistor is about 100 kΩ (see the product electrical characteristics for more details about this value). The pull-
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up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0.
I/O Line or Peripheral Function Selection
When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device.
Peripheral A or B Selection
The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR.
Output Control
When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_PDR (Output Disable Register). The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on
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6042A–ATARM–23-Dec-04
the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line.
Synchronous Data Output
Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OSWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0.
Multi Drive Control (Open Drain)
Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multidriver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0.
Output Line Timings
Figure 14 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 14 also shows when the feedback in PIO_PDSR is available.
Figure 14. Output Line Timings
MCK
Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0
APB Access
APB Access
PIO_ODSR 2 cycles PIO_PDSR 2 cycles
Inputs
The level on each I/O line can be read through PIO_PDSR (Peripheral Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral.
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Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled.
Input Glitch Filtering
Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 15. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled.
Figure 15. Input Glitch Filter Timing
MCK up to 1.5 cycles Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 up to 2.5 cycles 1 cycle up to 2 cycles 1 cycle 1 cycle 1 cycle
Input Change Interrupt
The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled.
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Figure 16. Input Change Interrupt Timings
MCK
Pin Level
PIO_ISR
Read PIO_ISR
APB Access
APB Access
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I/O Lines Programming Example
The programing example as shown in Table 28 below is used to define the following configuration. • • • • • • • 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), opendrain, with pull-up resistor Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pullup resistors, glitch filters and input change interrupts Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor
Table 28. Programming Example
Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0
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Parallel Input/Output Controller (PIO) User Interface
Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 29. Parallel Input/Output Controller (PIO) Register Mapping
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C Register PIO Enable Register PIO Disable Register PIO Status Register (1) Reserved Output Enable Register Output Disable Register Output Status Register Reserved Glitch Input Filter Enable Register Glitch Input Filter Disable Register Glitch Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register(2) Pin Data Status Register
(3)
Name PIO_PER PIO_PDR PIO_PSR
Access Write-only Write-only Read-only
Reset Value – – 0x0000 0000
PIO_OER PIO_ODR PIO_OSR
Write-only Write-only Read-only
– – 0x0000 0000
PIO_IFER PIO_IFDR PIO_IFSR
Write-only Write-only Read-only
– – 0x0000 0000
PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR
Write-only Write-only Read-only Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only
– – 0x0000 0000
Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register
(4)
– – 0x00000000 0x00000000 – – 0x00000000
PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR
Multi-driver Enable Register Multi-driver Disable Register Multi-driver Status Register Reserved Pull-up Disable Register Pull-up Enable Register Pad Pull-up Status Register Reserved
PIO_PUDR PIO_PUER PIO_PUSR
Write-only Write-only Read-only
– – 0x00000000
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Table 29. Parallel Input/Output Controller (PIO) Register Mapping (Continued)
Offset 0x0070 0x0074 0x0078 0x007C - 0x009C 0x00A0 0x00A4 0x00A8 0x00AC - 0x00FC Notes: 1. 2. 3. 4. Register Peripheral A Select Register Peripheral B Select Register AB Status Register(5) Reserved Output Write Enable Output Write Disable Output Write Status Register Reserved PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only – – 0x00000000
(5) (5)
Name PIO_ASR PIO_BSR PIO_ABSR
Access Write-only Write-only Read-only
Reset Value – – 0x00000000
Reset value of PIO_PSR depends on the product implementation. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. Reset value of PIO_PDSR depends on the level of the I/O lines. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register.
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PIO Controller PIO Enable Register
Name: Access Type:
31
PIO_PER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin).
PIO Controller PIO Disable Register
Name: Access Type:
31
PIO_PDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
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PIO Controller PIO Status Register
Name: Access Type:
31
PIO_PSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive).
PIO Controller Output Enable Register
Name: Access Type:
31
PIO_OER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line.
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PIO Controller Output Disable Register
Name: Access Type:
31
PIO_ODR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line.
PIO Controller Output Status Register
Name: Access Type:
31
PIO_OSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output.
216
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AT91SAM7A3 Preliminary
PIO Controller Input Filter Enable Register
Name: Access Type:
31
PIO_IFER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line.
PIO Controller Input Filter Disable Register
Name: Access Type:
31
PIO_IFDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line.
217
6042A–ATARM–23-Dec-04
PIO Controller Input Filter Status Register
Name: Access Type:
31
PIO_IFSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line.
PIO Controller Set Output Data Register
Name: Access Type:
31
PIO_SODR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line.
218
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PIO Controller Clear Output Data Register
Name: Access Type:
31
PIO_CODR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line.
PIO Controller Output Data Status Register
Name: Access Type:
31
PIO_ODSR Read-only or Read/Write
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1.
219
6042A–ATARM–23-Dec-04
PIO Controller Pin Data Status Register
Name: Access Type:
31
PIO_PDSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1.
PIO Controller Interrupt Enable Register
Name: Access Type:
31
PIO_IER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line.
220
AT91SAM7A3 Preliminary
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AT91SAM7A3 Preliminary
PIO Controller Interrupt Disable Register
Name: Access Type:
31
PIO_IDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line.
PIO Controller Interrupt Mask Register
Name: Access Type:
31
PIO_IMR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line.
221
6042A–ATARM–23-Dec-04
PIO Controller Interrupt Status Register
Name: Access Type:
31
PIO_ISR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
PIO Multi-driver Enable Register
Name: Access Type:
31
PIO_MDER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line.
222
AT91SAM7A3 Preliminary
6 042A–ATARM–23-Dec-04
AT91SAM7A3 Preliminary
PIO Multi-driver Disable Register
Name: Access Type:
31
PIO_MDDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line.
PIO Multi-driver Status Register
Name: Access Type:
31
PIO_MDSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only.
223
6042A–ATARM–23-Dec-04
PIO Pull Up Disable Register
Name: Access Type:
31
PIO_PUDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line.
PIO Pull Up Enable Register
Name: Access Type:
31
PIO_PUER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line.
224
AT91SAM7A3 Preliminary
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AT91SAM7A3 Preliminary
PIO Pull Up Status Register
Name: Access Type:
31
PIO_PUSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line.
PIO Peripheral A Select Register
Name: Access Type:
31
PIO_ASR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function.
225
6042A–ATARM–23-Dec-04
PIO Peripheral B Select Register
Name: Access Type:
31
PIO_BSR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function.
PIO Peripheral A B Status Register
Name: Access Type:
31
PIO_ABSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B.
226
AT91SAM7A3 Preliminary
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AT91SAM7A3 Preliminary
PIO Output Write Enable Register
Name: Access Type:
31
PIO_OWER Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line.
PIO Output Write Disable Register
Name: Access Type:
31
PIO_OWDR Write-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line.
227
6042A–ATARM–23-Dec-04
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AT91SAM7A3 Preliminary
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AT91SAM7A3 Preliminary
PIO Output Write Status Register
Name: Access Type:
31
PIO_OWSR Read-only
30 29 28 27 26 25 24
P31
23
P30
22
P29
21
P28
20
P27
19
P26
18
P25
17
P24
16
P23
15
P22
14
P21
13
P20
12
P19
11
P18
10
P17
9
P16
8
P15
7
P14
6
P13
5
P12
4
P11
3
P10
2
P9
1
P8
0
P7
P6
P5
P4
P3
P2
P1
P0
• P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line.
229
6042A–ATARM–23-Dec-04
230
AT91SAM7A3 Preliminary
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AT91SAM7A3 Preliminary
Serial Peripheral Interface (SPI)
Overview
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
•
•
231
6042A–ATARM–23-Dec-04
Block Diagram
Figure 17. Block Diagram
PDC APB SPCK MISO MCK SPI Interface DIV PIO MOSI NPCS0/NSS NPCS1 NPCS2 MCK(1) N Interrupt Control NPCS3
PMC
SPI Interrupt
Note:
1. N = 32
Application Block Diagram
Figure 18. Application Block Diagram: Single Master/Multiple Slave Implementation
SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS
232
AT91SAM7A3 Preliminary
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AT91SAM7A3 Preliminary
Signal Description
Table 30. Signal Description
Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input
Product Dependencies
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions.
Power Management Interrupt
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI.
233
6042A–ATARM–23-Dec-04
Functional Description
Modes of Operation
The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode.
Data Transfer
Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 31 shows the four modes and corresponding parameter settings. Table 31. SPI Bus Protocol Mode
SPI Mode 0 1 2 3 CPOL 0 0 1 1 CPHA 1 0 1 0
Figure 19 and Figure 20 show examples of data transfers.
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Figure 19. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8
SPCK (CPOL = 1)
MOSI (from master)
MSB
6
5
4
3
2
1
LSB
MISO (from slave)
MSB
6
5
4
3
2
1
LSB
*
NSS (to slave)
* Not defined, but normally MSB of previous character received.
Figure 20. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8
SPCK (CPOL = 1)
MOSI (from master)
MSB
6
5
4
3
2
1
LSB
MISO (from slave)
*
MSB
6
5
4
3
2
1
LSB
NSS (to slave)
* Not defined but normally LSB of previous character transmitted.
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Master Mode Operations
When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. No transfer is started when writing into the SPI_TDR if the PCS field does not select a slave. The PCS field is set by writing the SPI_TDR in variable mode, or the SPI_MR in fixed mode, depending on the value of PCS field. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, no data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 21 on page 237 shows a block diagram of the SPI when operating in Master Mode. Figure 22 on page 238 shows a flow chart describing how transfers are handled.
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Master Mode Block Diagram Figure 21. Master Mode Block Diagram
FDIV MCK
SPI_CSR0..3 SCBR 0 Baud Rate Generator SPCK
MCK/N
1 SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB
SPI_RDR RD
RDRF OVRES
MISO
Shift Register
MSB
MOSI
SPI_TDR TD SPI_CSR0..3 CSAAT PS SPI_MR PCS 0 SPI_TDR PCS 1 NPCS0 PCSDEC Current Peripheral SPI_RDR PCS NPCS3 NPCS2 NPCS1 TDRE
MSTR NPCS0 MODFDIS
MODF
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Master Mode Flow Diagram Figure 22. Master Mode Flow Diagram S
SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ?
0 1 CSAAT ? PS ? Variable peripheral yes 0 Fixed peripheral
0 0 PS ? Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral
1
SPI_TDR(PCS) = NPCS ? no NPCS = 0xF
SPI_MR(PCS) = NPCS ? no NPCS = 0xF
1
NPCS = SPI_TDR(PCS)
Delay DLYBCS
Delay DLYBCS
NPCS = SPI_TDR(PCS)
NPCS = SPI_MR(PCS), SPI_TDR(PCS)
Delay DLYBS
Serializer = SPI_TDR(TD) TDRE = 1
Data Transfer
SPI_RDR(RD) = Serializer RDRF = 1
Delay DLYBCT
0 TDRE ?
1
1 CSAAT ?
0 NPCS = 0xF
Delay DLYBCS
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Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK) or the Master Clock divided by 32, by a value between 2 and 255. The selection between Master Clock or Master Clock divided by N is done by the FDIV value set in the Mode Register This allows a maximum operating baud rate at up to Master Clock/2 and a minimum operating baud rate of MCK divided by 255*32. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. Transfer Delays Figure 23 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: • The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select
•
•
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 23. Programmable Delays
Chip Select 1
Chip Select 2
SPCK DLYBCS DLYBS DLYBCT DLYBCT
Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: • • Fixed Peripheral Select: SPI exchanges data with only one peripheral Variable Peripheral Select: Data can be exchanged with more than one peripheral
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Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS fields of the Chip Select Registers have no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Peripheral Deselection When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. Figure 24 shows different peripheral deselection cases and the effect of the CSAAT bit.
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Figure 24. Peripheral Deselection
CSAAT = 0 CSAAT = 1
TDRE
DLYBCT A DLYBCS PCS = A A A
DLYBCT A DLYBCS PCS = A A
NPCS[0..3]
Write SPI_TDR
TDRE
DLYBCT A DLYBCS PCS=A A A
DLYBCT A DLYBCS PCS = A A
NPCS[0..3]
Write SPI_TDR
TDRE NPCS[0..3]
DLYBCT A DLYBCS PCS = B B A
DLYBCT B DLYBCS PCS = B
Write SPI_TDR
Mode Fault Detection
A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. As this pin is generally configured in open-drain, it is important that a pull up resistor is connected on the NPCS0 line, so that a high level is guaranteed and no spurious mode fault is detected. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR).
SPI Slave Mode
When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode.
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The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If RDRF is already high when the data is transferred, the Overrun bit rises and the data transfer to SPI_RDR is aborted. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 25 shows a block diagram of the SPI when operating in Slave Mode. Figure 25. Slave Mode Functional Block Diagram
SPCK NSS SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RD RDRF OVRES SPI Clock
Shift Register
MSB
MISO
SPI_TDR FLOAD TD TDRE
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Serial Peripheral Interface (SPI) User Interface
Table 32. Serial Peripheral Interface (SPI) Register Mapping
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x004C - 0x00FC 0x100 - 0x124 Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 – Read/Write Read/Write Read/Write Read/Write – 0x0 0x0 0x0 0x0 – Register Register Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0
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SPI Control Register
Name: Access Type:
31
SPI_CR W rite-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
LASTXFER
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
SWRST
–
–
–
–
–
SPIDIS
SPIEN
• SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. • SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. • LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed.
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SPI Mode Register
Name: Access Type:
31
SPI_MR Read/Write
30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
–
15
–
14
–
13
–
12 11 10
PCS
9 8
–
7
–
6
–
5
–
4
–
3
–
2
–
1
–
0
LLB
–
–
MODFDIS
FDIV
PCSDEC
PS
MSTR
• MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. • PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 16 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 15. • FDIV: Clock Selection 0 = The SPI operates at MCK. 1 = The SPI operates at MCK/N. • MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. • LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in Master Mode only.
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• PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods (or 6*N MCK periods if FDIV is set) will be inserted by default. Otherwise, the following equation determines the delay: If FDIV is 0: D LYBCS Delay Between Chip Selects = ---------------------MCK If FDIV is 1: D LYBCS × N Delay Between Chip Selects = ---------------------------------MCK NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected)
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SPI Receive Data Register
Name: Access Type:
31
SPI_RDR Read-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12 11 10
PCS
9 8
RD
7 6 5 4 3 2 1 0
RD
• RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.
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SPI Transmit Data Register
Name: Access Type:
31
SPI_TDR W rite-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
LASTXFER
16
–
15
–
14
–
13
–
12 11 10
PCS
9 8
TD
7 6 5 4 3 2 1 0
TD
• TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS • LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected)
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SPI Status Register
Name: Access Type:
31
SPI_SR Read-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
SPIENS
8
–
7
–
6
–
5
–
4
–
3
–
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
• RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. • TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. • MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. • OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. • ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR or SPI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR or SPI_RNCR. • ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR or SPI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR or SPI_TNCR. • RXBUFF: RX Buffer Full 0 = SPI_RCR or SPI_RNCR has a value other than 0. 1 = Both SPI_RCR and SPI_RNCR has a value of 0. • TXBUFE: TX Buffer Empty 0 = SPI_TCR or SPI_TNCR has a value other than 0. 1 = Both SPI_TCR and SPI_TNCR has a value of 0.
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• NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled.
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SPI Interrupt Enable Register
Name: Access Type:
31
SPI_IER W rite-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
• RDRF: Receive Data Register Full Interrupt Enable • TDRE: SPI Transmit Data Register Empty Interrupt Enable • MODF: Mode Fault Error Interrupt Enable • OVRES: Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable • TXEMPTY: Transmission Registers Empty Enable • NSSR: NSS Rising Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt.
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SPI Interrupt Disable Register
Name: Access Type:
31
SPI_IDR W rite-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
• RDRF: Receive Data Register Full Interrupt Disable • TDRE: SPI Transmit Data Register Empty Interrupt Disable • MODF: Mode Fault Error Interrupt Disable • OVRES: Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable • TXEMPTY: Transmission Registers Empty Disable • NSSR: NSS Rising Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt.
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SPI Interrupt Mask Register
Name: Access Type:
31
SPI_IMR Read-only
30 29 28 27 26 25 24
–
23
–
22
–
21
–
20
–
19
–
18
–
17
–
16
–
15
–
14
–
13
–
12
–
11
–
10
–
9
–
8
–
7
–
6
–
5
–
4
–
3
–
2
TXEMPTY
1
NSSR
0
TXBUFE
RXBUFF
ENDTX
ENDRX
OVRES
MODF
TDRE
RDRF
• RDRF: Receive Data Register Full Interrupt Mask • TDRE: SPI Transmit Data Register Empty Interrupt Mask • MODF: Mode Fault Error Interrupt Mask • OVRES: Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask • TXEMPTY: Transmission Registers Empty Mask • NSSR: NSS Rising Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled.
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SPI Chip Select Register
Name: Access Type:
31
SPI_CSR0... SPI_CSR3 Read/Write
30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
7 6 5 4 3 2 1 0
BITS
CSAAT
–
NCPHA
CPOL
• CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. • NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used.
BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Bits Per Transfer 8 9 10 11 12 13 14 15 16 Reserved Reserved Reserved Reserved
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BITS 1101 1110 1111 Bits Per Transfer Reserved Reserved Reserved
• SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: If FDIV is 0: MCK SPCK Baudrate = -------------SCBR If FDIV is 1: MCK SPCK Baudrate = -----------------------------( N × SCBR )
Note:
N = 32
Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: If FDIV is 0: DLYBS Delay Before SPCK = -----------------MCK If FDIV is 1: N × DLYBS Delay Before SPCK = ----------------------------MCK
Note:
N = 32
• DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: If FDIV is 0: 255
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32 × DLYBCT SCBR Delay Between Consecutive Transfers = ------------------------------------- + ---------------MCK 2 MCK If FDIV is 1: 32 × N × DLYBCT N × SCB R Delay Between Consecutive Transfers = ------------------------------------------------ + ------------------------MCK 2 MCK
Note:
N = 32
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Two-wire Interface (TWI)
Overview
The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byteoriented transfer format. It can be used with any Atmel two-wire bus Serial EEPROM. The TWI is programmable as a master with sequential or single-byte access. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Figure 26. Block Diagram
APB Bridge
Block Diagram
TWCK PIO Two-wire Interface TWD
PMC
MCK
TWI Interrupt
AIC
Application Block Diagram
Figure 27. Application Block Diagram
VDD R TWD TWCK R
Host with TWI Interface
AT24LC16 U1 Slave 1
AT24LC16 U2 Slave 2
LCD Controller U3 Slave 3
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Product Dependencies
I/O Lines Description
Table 33. I/O Lines Description
Pin Name TWD TWCK Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output
Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 27 on page 257). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or opencollector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: • Program the PIO controller to: – – Dedicate TWD and TWCK as peripheral lines. Define TWD and TWCK as open-drain.
Power Management
•
Enable the peripheral clock.
The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI.
Interrupt
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Functional Description
Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 29 on page 259). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 28 on page 259). • • A high-to-low transition on the TWD line while TWCK is high defines the START condition. A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 28. START and STOP Conditions
TWD
TWCK Start Stop
Figure 29. Transfer Format
TWD
TWCK
Start
Address
R/W
Ack
Data
Ack
Data
Ack
Stop
Modes of Operation
The TWI has two modes of operation: • • Master transmitter mode Master receiver mode
The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it generates the clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR). This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks.
Transmitting Data
After the master initiates a Start condition, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction (write or read). If this bit is 0, it indicates a write operation (transmit operation). If the bit is 1, it indicates a request for data read (receive operation). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse, the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NAK bit in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). After writing in the transmit-holding register (TWI_THR), setting the START bit in
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the control register starts the transmission. The data is shifted in the internal shifter and when an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR (see Figure 31 below). The master generates a stop condition to end the transfer. The read sequence begins by setting the START bit. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. The TWI interface performs various transfer formats (7-bit slave address, 10-bit slave address). The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, IADRSZ must be set to 0. For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). Figure 30. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P
Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A DATA A P
One byte internal address TWD S DADR W A IADR(7:0) A DATA A P
Figure 31. Master Write with One Byte Internal Address and Multiple Data Bytes
TWD S DADR W A IADR(7:0) A DATA A DATA A DATA A P
TXCOMP Write THR TXRDY Write THR Write THR Write THR
Figure 32. Master Read with One, Two or Three Bytes Internal Address and One Data Byte
Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A S DADR R A
DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A S DADR R A DATA
N
P
N
P
One byte internal address TWD S DADR W A IADR(7:0) A S DADR R A DATA N P
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Figure 33. Master Read with One Byte Internal Address and Multiple Data Bytes
TWD S DADR W A IADR(7:0) A S DADR R A DATA A DATA N P
TXCOMP Write START Bit RXRDY Write STOP Bit
Read RHR
Read RHR
• • • • • •
S = Start P = Stop W = Write/Read A = Acknowledge DADR= Device Address IADR = Internal Address
Figure 34 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 34. Internal Address Usage
S T A R T W R I T E S T O P
Device Address 0 M S B
FIRST WORD ADDRESS
SECOND WORD ADDRESS
DATA
LRA S/C BW K
M S B
A C K
LA SC BK
A C K
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Read/Write Flowcharts
The following flowcharts shown in Figure 35 on page 262 and in Figure 36 on page 263 give examples for read and write operations in Master Mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 35. TWI Write in Master Mode
START
Set TWI clock: TWI_CWGR = clock
Set the control register: - Master enable TWI_CR = MSEN
Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Write ==> bit MREAD = 0
Internal address size = 0? Set theinternal address TWI_IADR = address
Yes Load transmit register TWI_THR = Data to send Start the transfer TWI_CR = START
Read status register
TWI_THR = data to send TXRDY = 0? Yes
Data to send? Yes
Stop the transfer TWI_CR = STOP
Read status register
TXCOMP = 0?
Yes
END
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Figure 36. TWI Read in Master Mode
START
Set TWI clock: TWI_CWGR = clock
Set the control register: - Master enable - Slave disable TWI_CR = MSEN
Set the Master Mode register: - Device slave address - Internal address size - Transfer direction bit Read ==> bit MREAD = 0
Internal address size = 0? Set the internal address TWI_IADR = address
Yes Start the transfer TWI_CR = START
Read status register
RXRDY = 0?
Yes
Data to read? Yes
Stop the transfer TWI_CR = STOP
Read status register
TXCOMP = 0?
Yes
END
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Two-wire Interface (TWI) User Interface
Table 34. Two-wire Interface (TWI) Register Mapping
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038-0x00FC Register Control Register Master Mode Register Reserved Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Name TWI_CR TWI_MMR – TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR – Access Write-only Read/Write – Read/Write Read/Write Read-only Write-only Write-only Read-only Read-only Read/Write – Reset Value N/A 0x0000 – 0x0000 0x0000 0x0008 N/A N/A 0x0000 0x0000 0x0000 –
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TWI Control Register
Register Name: Access Type:
31 – 23 – 15 – 7 SWRST
TWI_CR W rite-only
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 MSDIS 26 – 18 – 10 – 2 MSEN 25 – 17 – 9 – 1 STOP 24 – 16 – 8 – 0 START
• START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent with the mode register as soon as the user writes a character in the holding register. • STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read or write mode. In single data byte master read or write, the START and STOP must both be set. In multiple data bytes master read or write, the STOP must be set before ACK/NACK bit transmission. In master read mode, if a NACK bit is received, the STOP is automatically performed. In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. • MSEN: TWI Master Transfer Enabled 0 = No effect. 1 = If MSDIS = 0, the master data transfer is enabled. • MSDIS: TWI Master Transfer Disabled 0 = No effect. 1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset.
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TWI Master Mode Register
Register Name: Address Type :
31 – 23 – 15 – 7 –
TWI_MMR Read/Write
30 – 22 29 – 21 28 – 20 27 – 19 DADR 11 – 3 – 26 – 18 25 – 17 24 – 16
14 – 6 –
13 – 5 –
12 MREAD 4 –
10 – 2 –
9 IADRSZ 1 –
8
0 –
• IADRSZ: Internal Device Address Size
IADRSZ[9:8] 0 0 1 1 0 1 0 1
No internal device address One-byte internal device address Two-byte internal device address Three-byte internal device address
• MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. • DADR: Device Address The device address is used in Master Mode to access slave devices in read or write mode.
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TWI Internal Address Register
Register Name: Access Type:
31 – 23
TWI_IADR Read/Write
30 – 22 29 – 21 28 – 20 IADR 27 – 19 26 – 18 25 – 17 24 – 16
15
14
13
12 IADR
11
10
9
8
7
6
5
4 IADR
3
2
1
0
• IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ.
TWI Clock Waveform Generator Register
Register Name: Access Type:
31 – 23 – 15
TWI_CWGR Read/Write
30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CHDIV 27 – 19 – 11 26 – 18 25 – 17 CKDIV 9 24 – 16
10
8
7
6
5
4 CLDIV
3
2
1
0
• CLDIV: Clock Low Divider The SCL low period is defined as follows:
CKDIV
T low = ( ( CLDIV × 2
) + 3 ) × T MCK
• CHDIV: Clock High Divider The SCL high period is defined as follows:
CKDIV
T high = ( ( CHDIV × 2
) + 3 ) × T MCK
• CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods.
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TWI Status Register
Register Name: Access Type:
31 – 23 – 15 – 7 UNRE
TWI_SR Read-only
30 – 22 – 14 – 6 OVRE 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 TXRDY 25 – 17 – 9 – 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP
• TXCOMP: Transmission Completed 0 = In master, during the length of the current frame. In slave, from START received to STOP received. 1 = When both holding and shift registers are empty and STOP condition has been sent (in Master) or received (in Slave), or when MSEN is set (enable TWI). • RXRDY: Receive Holding Register Ready 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. • TXRDY: Transmit Holding Register Ready 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). • OVRE: Overrun Error 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. • UNRE: Underrun Error 0 = No underrun error 1 = No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a STOP bit in Master Mode. Reset by read in TWI_SR when TXCOMP is set. • NACK: Not Acknowledged 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
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TWI Interrupt Enable Register
Register Name: Access Type:
31 – 23 – 15 – 7 UNRE
TWI_IER W rite-only
30 – 22 – 14 – 6 OVRE 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 TXRDY 25 – 17 – 9 – 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP
• TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • OVRE: Overrun Error • UNRE: Underrun Error • NACK: Not Acknowledge 0 = No effect. 1 = Enables the corresponding interrupt.
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TWI Interrupt Disable Register
Register Name: Access Type:
31 – 23 – 15 – 7 UNRE
TWI_IDR W rite-only
30 – 22 – 14 – 6 OVRE 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 TXRDY 25 – 17 – 9 – 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP
• TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • OVRE: Overrun Error • UNRE: Underrun Error • NACK: Not Acknowledge 0 = No effect. 1 = Disables the corresponding interrupt.
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TWI Interrupt Mask Register
Register Name: Access Type:
31 – 23 – 15 – 7 UNRE
TWI_IMR Read-only
30 – 22 – 14 – 6 OVRE 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 TXRDY 25 – 17 – 9 – 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP
• TXCOMP: Transmission Completed • RXRDY: Receive Holding Register Ready • TXRDY: Transmit Holding Register Ready • OVRE: Overrun Error • UNRE: Underrun Error • NACK: Not Acknowledge 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled.
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TWI Receive Holding Register
Register Name: Access Type:
31 – 23 – 15 – 7
TWI_RHR Read-only
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0
• RXDATA: Master or Slave Receive Holding Data
TWI Transmit Holding Register
Register Name: Access Type:
31 – 23 – 15 – 7
TWI_THR Read/Write
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0
• TXDATA: Master or Slave Transmit Holding Data
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Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
Description
The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver timeout enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral Data Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor.
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Block Diagram
Figure 37. USART Block Diagram
Peripheral Data Controller Channel Channel
USART
PIO Controller
RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS
PMC MCK MCK/DIV Baud Rate Generator SCK
DIV
User Interface SLCK
APB
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Application Block Diagram
Figure 38. Application Block Diagram
PPP Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver
USART
RS232 Drivers
RS485 Drivers
Smart Card Slot
IrDA Transceivers
Serial Port
Differential Bus
I/O Lines Description
Table 35. I/O Line Description
Name SCK TXD RXD CTS RTS Description Serial Clock Transmit Serial Data Receive Serial Data Clear to Send Request to Send Type I/O I/O Input Input Output Low Low Active Level
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Product Dependencies
I/O Lines
The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled.
Power Management
Interrupt
The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode.
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Functional Description
The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – – – – – – – • – – – – – – – • • • • MSB- or LSB-first 1, 1.5 or 2 stop bits Parity even, odd, marked, space or none By 8 or by 16 over-sampling receiver frequency Optional hardware handshaking Optional break management Optional multidrop serial communication MSB- or LSB-first 1 or 2 stop bits Parity even, odd, marked, space or none By 8 or by 16 over-sampling frequency Optional hardware handshaking Optional break management Optional multidrop serial communication
High-speed 5- to 9-bit full-duplex synchronous serial communication
RS485 with driver control signal ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit InfraRed IrDA Modulation and Demodulation Test modes – Remote loopback, local loopback, automatic echo
Baud Rate Generator
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: • • • the Master Clock MCK a division of the Master Clock, the divider being product dependent, but generally set to 8 the external clock, available on the SCK pin
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK.
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Figure 39. Baud Rate Generator
USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC
SCK
Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate.
SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over ) CD )
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1.
Baud Rate Calculation Example
Table 36 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error.
Table 36. Baud Rate Example (OVER = 0)
Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000 14 318 180 Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 23.30 6 8 8 12 13 20 20 23 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 38 908.10 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% 1.31% Error
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Table 36. Baud Rate Example (OVER = 0) (Continued)
Source Clock 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 60 000 000 70 000 000 Expected Baud Rate 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 Calculation Result 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 97.66 113.93 CD 24 30 39 40 40 52 53 54 65 81 98 114 Actual Baud Rate 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 38 265.31 38 377.19 Error 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% 0.35% 0.06%
The baud rate is calculated with the following formula: B audRate = MCK ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%.
ExpectedBaudRate Error = 1 – ⎛ --------------------------------------------------⎞ ⎝ ActualBaudRate ⎠
Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR.
------------------------------------BaudRate = SelectedClock CD
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula:
Di B = ----- × f Fi
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• • •
Di is the bit-rate adjustment factor Fi is the clock frequency division factor f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 37. Table 37. Binary and Decimal Values for D
DI field Di (decimal) 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 38. Table 38. Binary and Decimal Values for F
FI field Fi (decimal 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048
Table 39 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 39. Possible Values for the Fi/Di Ratio
Fi/Di 1 2 4 8 16 32 12 20 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4
If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 40 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock.
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Figure 40. Elementary Time Unit (ETU)
FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD
1 ETU
Receiver and Transmitter Control
After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The reset commands have the same effect as a hardware reset on the corresponding logic. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally.
Synchronous and Asynchronous Modes
Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only.
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Figure 41. Character Transmit
Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD
Start Bit
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY raises. Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in US_THR while TXRDY is active has no effect and the written character is lost. Figure 42. Transmitter Status
Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Write US_THR TXRDY
TXEMPTY
Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. The number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as
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soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 43 and Figure 44 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 43. Asynchronous Start Detection
Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling
Start Detection RXD Sampling
1
2
3
4
5
6
01 Start Rejection
7
2
3
4
Figure 44. Asynchronous Character Reception
Example: 8-bit, Parity Enabled
Baud Rate Clock RXD Start Detection
16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples
D0
D1
D2
D3
D4
D5
D6
D7
Parity Bit
Stop Bit
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Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 45 illustrates a character reception in synchronous mode. Figure 45. Synchronous Mode Character Reception
Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock
RXD Sampling
Start
D0
D1
D2
D3
D4
D5
D6
D7 Parity Bit
Stop Bit
Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 46. Receiver Status
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
RSTSTA = 1
Write US_CR Read US_RHR
RXRDY OVRE
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Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, which is discussed in a separate paragraph. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the odd parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0.If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 40 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. I Table 40. Parity Bit Examples
Character A A A A A Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None
When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 47 illustrates the parity bit status setting and clearing. Figure 47. Parity Error
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit
RSTSTA = 1
Write US_CR PARE
RXRDY
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Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 48, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. Figure 48. Timeguard Operations
TG = 4 Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
TG = 4
Write US_THR TXRDY
TXEMPTY
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Table 41 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 41. Maximum Timeguard Length Depending on Baud Rate
Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 Bit time µs 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21
Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises.
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The user can either: • Obtain an interrupt when a time-out is detected after having received at least one character. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. Obtain a periodic interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1.
•
If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 49 shows the block diagram of the Receiver Time-out feature. Figure 49. Receiver Time-out Block Diagram
Baud Rate Clock TO
1 STTTO
D
Q
Clock
16-bit Time-out Counter Load
16-bit Value = TIMEOUT
Character Received RETTO
Clear
0
Table 42 gives the maximum time-out period for some standard baud rates.t Table 42. Maximum Time-out Period
Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 56000 57600 200000 Bit Time µs 1 667 833 417 208 104 69 52 35 30 18 17 5 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 1 170 1 138 328
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Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 50. Framing Error Status
Baud Rate Clock RXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
RSTSTA = 1
Write US_CR FRAME
RXRDY
Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored.
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After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 51 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STP BRK) commands on the TXD line. Figure 51. Break Transmission
Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Break Transmùission STPBRK = 1
End of Break
STTBRK = 1 Write US_CR TXRDY
TXEMPTY
Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 52. Figure 52. Connection with a Remote Device for Hardware Handshaking
USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS
Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2.
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The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 53 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 53. Receiver Behavior when Operating with Hardware Handshaking
RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1
Figure 54 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 54. Transmitter Behavior when Operating with Hardware Handshaking
CTS
TXD
ISO7816 Mode
The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 277). The USART connects to a smart card as shown in Figure 55. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when
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the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 55. Connection of a Smart Card to the USART
USART SCK TXD CLK I/O Smart Card
When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 56. If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 57. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 56. T = 0 Protocol without Parity Error
Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit
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Figure 57. T = 0 Protocol with Parity Error
Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1
Repetition
Receive Error Counter
The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise.
Receive NACK Inhibit
Transmit Character Repetition
When the USART is transmitting a character and gets a NACK, it can automatically repeat the chara cte r b efore moving on to the n ext o ne. Rep etition is enab led by writin g th e MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1.
Disable Successive Receive NACK
The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set.
Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR).
IrDA Mode
The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 58. The modulator and demodulator are compliant
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with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 58. Connection to IrDA Transceivers
USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD
IrDA Transceivers
The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. "0" is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 43. Table 43. IrDA Pulse Duration
Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s Pulse Duration (3/16) 78.13 µs 19.53 µs 9.77 µs 4.88 µs 3.26 µs 1.63 µs
Figure 59 shows an example of character transmission.
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Figure 59. IrDA Modulation
Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Start Bit 1
TXD
Bit Period
3 16 Bit Period
IrDA Baud Rate Table 44 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 44. IrDA Baud Rate Error
Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 38 400 38 400 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 2 11 18 22 4 22 36 43 6 33 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% 0.00% 1.38% 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 4.88 4.88 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13
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IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 60 illustrates the operations of the IrDA demodulator. Figure 60. IrDA Demodulator Operations
MCK
RXD
Counter Value
6
5
4
3
2
6
6
5
4
3
2
1
0
Pulse Accepted
Receiver Input
Pulse Rejected Driven Low During 16 Baud Rate Clock Cycles
As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly.
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RS485 Mode
The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 61. Figure 61. Typical Connection to a RS485 Bus
USART
RXD
TXD RTS
Differential Bus
The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 62 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 62. Example of RTS Drive with Timeguard
TG = 4 Baud Rate Clock TXD
Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit
Write US_THR TXRDY
TXEMPTY
RTS
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Test Modes
The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 63. Normal Mode Configuration
RXD Receiver
TXD Transmitter
Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 64. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 64. Automatic Echo Mode Configuration
RXD Receiver
TXD Transmitter
Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 65. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 65. Local Loopback Mode Configuration
RXD Receiver
Transmitter
1
TXD
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Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 66. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 66. Remote Loopback Mode Configuration
Receiver 1 RXD
TXD Transmitter
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USART User Interface
Table 45. USART Memory Map
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x2C - 0x3C 0x0040 0x0044 0x0048 0x004C 0x100 - 0x128 Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR – US_FIDI US_NER – US_IF – Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write Read/Write Read/Write – Read/Write Read-only – Read/Write – Reset State – – – – 0 – 0 – 0 0 0 – 0x174 – – 0 –
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USART Control Register
Name: Access Type:
31 – 23 – 15 RETTO 7 TXDIS
US_CR Write-only
30 – 22 – 14 RSTNACK 6 TXEN 29 – 21 – 13 RSTIT 5 RXDIS 28 – 20 – 12 SENDA 4 RXEN 27 – 19 RTSDIS 11 STTTO 3 RSTTX 26 – 18 RTSEN 10 STPBRK 2 RSTRX 25 – 17 – 9 STTBRK 1 – 24 – 16 – 8 RSTSTA 0 –
• RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE and RXBRK in the US_CSR. • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted.
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• STTTO: Start Time-out 0: No effect 1: Starts waiting for a character before clocking the time-out counter. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. • RETTO: Rearm Time-out 0: No effect 1: Restart Time-out • RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1.
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USART Mode Register
Name: Access Type:
31 – 23 – 15 CHMODE 7 CHRL 6 5 USCLKS
US_MR Read/Write
30 – 22 – 14 29 – 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 – 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24
18 CLKO 10 PAR 2
16 MSBF 8 SYNC 0
1 USART_MODE
• USART_MODE
USART_MODE 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 x 0 1 0 1 0 1 0 1 0 x Mode of the USART Normal RS485 Hardware Handshaking Reserved IS07816 Protocol: T = 0 Reserved IS07816 Protocol: T = 1 Reserved IrDA Reserved
• USCLKS: Clock Selection
USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK / DIV Reserved SCK
• CHRL: Character Length.
CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits
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• SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • PAR: Parity Type
PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode
• NBSTOP: Number of Stop Bits
NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved
• CHMODE: Channel Mode
CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin.
• MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CKLO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling.
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• INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. • FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority).
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USART Interrupt Enable Register
Name: Access Type:
31 – 23 – 15 – 7 PARE
US_IER Write-only
30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITERATION 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY
• RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • ENDRX: End of Receive Transfer Interrupt Enable • ENDTX: End of Transmit Interrupt Enable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITERATION: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Enable • RXBUFF: Buffer Full Interrupt Enable • NACK: Non Acknowledge Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt.
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USART Interrupt Disable Register
Name: Access Type:
31 – 23 – 15 – 7 PARE
US_IDR Write-only
30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITERATION 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY
• RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • ENDRX: End of Receive Transfer Interrupt Disable • ENDTX: End of Transmit Interrupt Disable • OVRE: Overrun Error Interrupt Disable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITERATION: Iteration Interrupt Disable • TXBUFE: Buffer Empty Interrupt Disable • RXBUFF: Buffer Full Interrupt Disable • NACK: Non Acknowledge Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt.
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USART Interrupt Mask Register
Name: Access Type:
31 – 23 – 15 – 7 PARE
US_IMR Read-only
30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITERATION 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY
• RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • ENDRX: End of Receive Transfer Interrupt Mask • ENDTX: End of Transmit Interrupt Mask • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITERATION: Iteration Interrupt Mask • TXBUFE: Buffer Empty Interrupt Mask • RXBUFF: Buffer Full Interrupt Mask • NACK: Non Acknowledge Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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USART Channel Status Register
Name: Access Type:
31 – 23 CTS 15 – 7 PARE
US_CSR Read-only
30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITERATION 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 – 16 – 8 TIMEOUT 0 RXRDY
• RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. • ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. • ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. • OVRE: Overrun Error 0: No overrun error has occurred since since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command.
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• TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There is at least one character in either US_THR or the Transmit Shift Register. • ITERATION: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSIT. 1: Maximum number of repetitions has been reached since the last RSIT. • TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. • RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. • NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. • CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. • CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1.
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USART Receive Holding Register
Name: Access Type:
31 – 23 – 15 – 7
US_RHR Read-only
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 RXCHR 0
• RXCHR: Received Character Last character received if RXRDY is set.
USART Transmit Holding Register
Name: Access Type:
31 – 23 – 15 – 7
US_THR Write-only
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 TXCHR 0
• TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set.
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USART Baud Rate Generator Register
Name: Access Type:
31 – 23 – 15
US_BRGR Read/Write
30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CD 7 6 5 4 CD 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8
• CD: Clock Divider
USART_MODE ≠ ISO7816 CD OVER = 0 0 1 to 65535 Baud Rate = Selected Clock/16/CD SYNC = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816
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USART Receiver Time-out Register
Name: Access Type:
31
US_RTOR Read/Write
30 29 28 27 26 25 24
– 23 – 15
– 22 – 14
– 21 – 13
– 20 – 12 TO
– 19 – 11
– 18 – 10
– 17 – 9
– 16 – 8
7
6
5
4 TO
3
2
1
0
• TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period.
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USART Transmitter Timeguard Register
Name: Access Type:
31 – 23 – 15 – 7
US_TTGR Read/Write
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TG 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0
• TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period.
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USART FI DI RATIO Register
Name: Access Type: Reset Value:
31 – 23 – 15 – 7
US_FIDI Read/Write 0x174
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FI_DI_RATIO 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 – 9 FI_DI_RATIO 1 24 – 16 – 8
2
0
• FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO.
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USART Number of Errors Register
Name: Access Type:
31 – 23 – 15 – 7
US_NER Read-only
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 NB_ERRORS 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0
• NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read.
USART IrDA FILTER Register
Name: Access Type:
31 – 23 – 15 – 7
US_IF Read/Write
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IRDA_FILTER 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0
• IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator.
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Synchronous Serial Controller (SSC)
Overview
The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. Transfers contain up to 16 data of up to 32 bits. They can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: • • • CODECs in master or slave mode DAC through dedicated serial interface, particularly I2S Magnetic card reader
Block Diagram
Figure 67. Block Diagram
ASB
APB Bridge
PDC APB TF TK TD SSC Interface PIO RF RK Interrupt Control RD
PMC
MCK
SSC Interrupt
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Application Block Diagram
Figure 68. Application Block Diagram
OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management
Serial AUDIO
Codec
Line Interface
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Pin Name List
Table 46. I/O Lines Description
Pin Name RF RK RD TF TK TD Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output
Product Dependencies
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode.
Power Management Interrupt
The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register.
Functional Description
This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. Each level of the clock must be stable for at least two master clock periods.
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Figure 69. SSC Functional Block Diagram
Transmitter
Clock Output Controller
TK
MCK
Clock Divider
TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller
TX clock
Frame Sync Controller
TF
Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register
TD
APB User Interface
Load Shift
Receiver
Clock Output Controller
RK
RK Input TX Clock RF TF Start Selector
Receive Clock RX Clock Controller
Frame Sync Controller
RF
Receive Shift Register Receive Holding Register Receive Sync Holding Register
RD
RX PDC PDC Interrupt Control
Load Shift
AIC
Clock Management
The transmitter clock can be generated by: • • • • • • an external clock received on the TK I/O pad the receiver clock the internal clock divider an external clock received on the RK I/O pad the transmitter clock the internal clock divider
The receiver clock can be generated by:
Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave-mode data transfers.
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Clock Divider
Figure 70. Divided Clock Block diagram
Clock Divider SSC_CMR MCK /2
12-bit Counter
Divided Clock
The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal or greater to 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless if the DIV value is even or odd. Figure 71. Divided Clock Generation
Master Clock
Divided Clock DIV = 1 Divided Clock Frequency = MCK/2
Master Clock
Divided Clock DIV = 3 Divided Clock Frequency = MCK/6
Table 47. Bit Rate
Maximum MCK / 2
Minimum
MCK / 8190
Transmitter Clock Management
The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results.
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Figure 72. Transmitter Clock Management
SSC_TCMR.CKS SSC_TCMR.CKO
TK
Receiver Clock Divider Clock 0 1 SSC_TCMR.CKI Transmitter Clock
TK
Receiver Clock Management
The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) might lead to unpredictable results. Figure 73. Receiver Clock Management
SSC_RCMR.CKS SSC_RCMR.CKO
RK
Transmitter Clock Divider Clock 0 1 SSC_RCMR.CKI Receiver Clock
RK
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Transmitter Operations
A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 324. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 326. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 74. Transmitter Block Diagram
SSC_CR.TXEN
SSC_SR.TXEN
SSC_CR.TXDIS SSC_TFMR.DATDEF
1 RF Transmitter Clock TF SSC_TFMR.MSBF 0
SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD
Start Selector
Transmit Shift Register
SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR
0
1
SSC_TSHR
SSC_TFMR.FSLEN
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Receiver Operations
A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 324. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 326. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register in function of data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register, if another transfer occurs before read the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register.
Figure 75. Receiver Block Diagram
SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS
RF Receiver Clock
TF
SSC_RFMR.MSBF
SSC_RFMR.DATNB
Start Selector
Receive Shift Register
RD
SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN
SSC_RHR SSC_RFMR.DATLEN
Start
The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: • • • • • Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. Synchronously with the transmitter/receiver On detection of a falling/rising edge on TK/RK On detection of a low level/high level on TK/RK On detection of a level change or an edge on TK/RK
A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Detection on TF/RF input/output is done through the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR).
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Generating a Frame Sync signal is not possible without generating it on its related output. Figure 76. Transmit Start Mode
TK TF (Input)
Start = Low Level on TF
TD (Output) TD (Output)
X
BO
B1 STTDLY
Start = Falling Edge on TF
X
BO
B1 STTDLY X BO B1 STTDLY
Start = High Level on TF
TD (Output) TD (Output) TD (Output) TD (Output) X
Start = Rising Edge on TF
BO
B1 STTDLY
Start = Level Change on TF
X
BO
B1
BO
B1 STTDLY
Start = Any Edge on TF
X
BO
B1
BO
B1 STTDLY
Figure 77. Receive Pulse/Edge Start Modes
RK RF (Input)
Start = Low Level on RF
RD (Input) RD (Input)
X
BO
B1 STTDLY
Start = Falling Edge on RF
X
BO
B1 STTDLY X BO B1 STTDLY
Start = High Level on RF
RD (Input) RD (Input) RD (Input) RD (Input) X
Start = Rising Edge on RF
BO
B1 STTDLY
Start = Level Change on RF
X
BO
B1
BO
B1 STTDLY
Start = Any Edge on RF
X
BO
B1
BO
B1 STTDLY
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Frame Sync
The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • • Programmable low or high levels during data transfer are supported. Programmable high levels before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1-bit time up to 16-bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Synchro signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register then shifted out. Frame Sync Edge Detection Th e Fra me Sync Edge de tectio n is pro gra mme d b y the FSED GE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). The data framing format of both the transmitter and the receiver are largely programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: • • • • • • The event that starts the data transfer (START). The delay in number of bit periods between the start event and the first data bit (STTDLY). The length of the data (DATLEN) The number of data to be transferred for each start event (DATNB). The length of Synchronization transferred for each start event (FSLEN). The bit sense: most or lowest significant bit first (MSBF). Additionally, the transmitter can be used to transfer Synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR.
Data Format
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Table 48. D ata Frame Registers
Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR SSC_RCMR SSC_RCMR Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN PERIOD STTDLY up to 512 up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number Word transmitter in frame 1 most significant bit in first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay
Figure 78. Transmit and Receive Frame Format in Edge/Pulse Start Modes
Start PERIOD TF/RF
(1)
Start
FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data
From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored
TD (If FSDEN = 0) RD
DATNB
Note:
1. Example of Input on falling edge of TF/RF.
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Figure 79. Transmit Frame Format in Continuous Mode
Start
TD
Data From SSC_THR DATLEN
Data From SSC_THR DATLEN
Default
Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR
Note:
1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.
Figure 80. Receive Frame Format in Continuous Mode
Start = Enable Receiver
RD
Data To SSC_RHR DATLEN
Data To SSC_RHR DATLEN
Note:
1. STTDLY is set to 0.
Loop Mode
The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC Controller can be programmed to generate an interrupt when it detects an event. The Interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register), which respectively enable and disable the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC.
Interrupt
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Figure 81. Interrupt Block Diagram
SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear
SSC Interrupt
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SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 82. Audio Application Block Diagram
Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER
Clock SCK Word Select WS
Data SD
MSB Left Channel
LSB
MSB Right Channel
Figure 83. Codec Application Block Diagram
Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC
Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend
Serial Data In
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Figure 84. Time Slot Application Block Diagram
SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot
CODEC Second Time Slot
Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend
Serial Data in
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Synchronous Serial Controller (SSC) User Interface
Table 49. Synchronous Serial Controller (SSC) Register Mapping
Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100 - 0x124 Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Reserved Reserved Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Register Register Name SSC_CR SSC_CMR – – SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR – – SSC_RSHR SSC_TSHR – – SSC_SR SSC_IER SSC_IDR SSC_IMR – – Access Write Read/Write – – Read/Write Read/Write Read/Write Read/Write Read Write – – Read Read/Write – – Read Write Write Read – – Reset – 0x0 – – 0x0 0x0 0x0 0x0 0x0 – – – 0x0 0x0 – – 0x000000CC – – 0x0 – –
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SSC Control Register
Name: Access Type:
31 – 23 – 15 SWRST 7 –
SSC_CR Write-only
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 TXDIS 1 RXDIS 24 – 16 – 8 TXEN 0 RXEN
• RXEN: Receive Enable 0: No effect. 1: Enables Data Receive if RXDIS is not set(1). • RXDIS: Receive Disable 0: No effect. 1: Disables Data Receive (1). • TXEN: Transmit Enable 0: No effect. 1: Enables Data Transmit if TXDIS is not set(1). • TXDIS: Transmit Disable 0: No effect. 1: Disables Data Transmit(1) . • SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR.
Note: 1. Only the data management is affected
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SSC Clock Mode Register
Name: Access Type:
31 – 23 – 15 – 7
SSC_CMR Read/Write
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DIV 27 – 19 – 11 3 26 – 18 – 10 DIV 2 1 0 25 – 17 – 9 24 – 16 – 8
• DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190.
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SSC Receive Clock Mode Register
Name: Access Type:
31 23 15 – 7 –
SSC_RCMR Read/Write
30 22 14 – 6 – 29 21 13 – 5 CKI 28 PERIOD 20 STTDLY 12 – 4 11 3 CKO 10 START 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24
• CKS: Receive Clock Selection
CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock Signal RK Pin Reserved
• CKO: Receive Clock Output Mode Selection CKO
0x0 0x1 0x2-0x7
Receive Clock Output Mode
None Continuous Receive Clock Reserved
RK pin Input-only Output
• CKI: Receive Clock Inversion 0: The data and the Frame Sync signal are sampled on Receive Clock falling edge. 1: The data and the Frame Sync signal are shifted out on Receive Clock rising edge. CKI does not affect the RK output clock signal.
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• START: Receive Start Selection
START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit Start Detection of a low level on RF input Detection of a high level on RF input Detection of a falling edge on RF input Detection of a rising edge on RF input Detection of any level change on RF input Detection of any edge on RF input Reserved
• STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Please Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock.
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SSC Receive Frame Mode Register
Name: Access Type:
31 – 23 – 15 – 7 MSBF
SSC_RFMR Read/Write
30 – 22 14 – 6 – 29 – 21 FSOS 13 – 5 LOOP 28 – 20 12 – 4 27 – 19 11 3 26 – 18 FSLEN 10 DATNB 2 DATLEN 1 0 9 8 25 – 17 24 FSEDGE 16
• DATLEN: Data Length 0x0 is not supported. The value of DATLEN can be set between 0x1 and 0x1F. The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the Receiver. If DATLEN is less than or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred. For any other value, 32-bit words are transferred. • LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start. If 0, only 1 data word is transferred. Up to 16 data words can be transferred. • FSLEN: Receive Frame Sync Length This field defines the length of the Receive Frame Sync Signal and the number of bits sampled and stored in the Receive Sync Data Register. Only when FSOS is set on negative or positive pulse. • FSOS: Receive Frame Sync Output Selection FSOS
0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7
Selected Receive Frame Sync Signal
None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved
RF pin Input-only Output Output Output Output Output Undefined
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• FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync sets RXSYN in the SSC Status Register. FSEDGE
0x0 0x1
Frame Sync Edge Detection
Positive Edge Detection Negative Edge Detection
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SSC Transmit Clock Mode Register
Name: Access Type:
31 23 15 – 7 –
SSC_TCMR Read/Write
30 22 14 – 6 – 29 21 13 – 5 CKI 28 PERIOD 20 STTDLY 12 – 4 11 3 CKO 10 START 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24
• CKS: Transmit Clock Selection CKS
0x0 0x1 0x2 0x3
Selected Transmit Clock
Divided Clock RK Clock signal TK Pin Reserved
• CKO: Transmit Clock Output Mode Selection CKO
0x0 0x1 0x2-0x7
Transmit Clock Output Mode
None Continuous Transmit Clock Reserved
TK pin Input-only Output
• CKI: Transmit Clock Inversion 0: The data and the Frame Sync signal are shifted out on Transmit Clock falling edge. 1: The data and the Frame Sync signal are shifted out on Transmit Clock rising edge. CKI affects only the Transmit Clock and not the output clock signal.
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• START: Transmit Start Selection START
0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8-0xF
Transmit Start
Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled) and immediately after the end of transfer of the previous data. Receive Start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved
• STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Please Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock.
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SSC Transmit Frame Mode Register
Name: Access Type:
31 – 23 FSDEN 15 – 7 MSBF
SSC_TFMR Read/Write
30 – 22 14 – 6 – 29 – 21 FSOS 13 – 5 DATDEF 28 – 20 12 – 4 27 – 19 11 3 26 – 18 FSLEN 10 DATNB 2 DATLEN 1 0 9 8 25 – 17 24 FSEDGE 16
• DATLEN: Data Length 0x0 is not supported. The value of DATLEN can be set between 0x1 and 0x1F. The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the Receiver. If DATLEN is less than or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred. For any other value, 32-bit words are transferred. • DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. • DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start. If 0, only 1 data word is transferred and up to 16 data words can be transferred. • FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. If 0, the Transmit Frame Sync signal is generated during one Transmit Clock period and up to 16 clock period pulse length is possible. • FSOS: Transmit Frame Sync Output Selection
FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF Pin Input-only Output Output Output Output Output Undefined
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• FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
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• FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync sets TXSYN (Status Register). FSEDGE
0x0 0x1
Frame Sync Edge Detection
Positive Edge Detection Negative Edge Detection
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SSC Receive Holding Register
Name: Access Type:
31 23 15 7
SSC_RHR Read-only
30 22 14 6 29 21 13 5 28 RDAT 20 RDAT 12 RDAT 4 RDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
• RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR.
SSC Transmit Holding Register
Name: Access Type:
31 23 15 7
SSC_THR Write only
30 22 14 6 29 21 13 5 28 TDAT 20 TDAT 12 TDAT 4 TDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24
TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR.
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SSC Receive Synchronization Holding Register
Name: Access Type:
31 – 23 – 15 7
SSC_RSHR Read/Write
30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 RSDAT 4 RSDAT 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8
• RSDAT: Receive Synchronization Data Right aligned regardless of the number of data bits defined by FSLEN in SSC_RFMR.
SSC Transmit Synchronization Holding Register
Name: Access Type:
31 – 23 – 15 7
SSC_TSHR Read/Write
30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 TSDAT 4 TSDAT 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8
• TSDAT: Transmit Synchronization Data Right aligned regardless of the number of data bits defined by FSLEN in SSC_TFMR.
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SSC Status Register
Register Name: Access Type:
31 – 23 – 15 – 7 RXBUFF
SSC_SR Read-only
30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 RXEN 9 – 1 TXEMPTY 24 – 16 TXEN 8 – 0 TXRDY
• TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register. 1: SSC_THR is empty. • TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from Transmit Shift Register. 1: Last data written in SSC_THR has been loaded in Transmit Shift Register and transmitted by it. • ENDTX: End of Transmission 0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. • TXBUFE: Transmit Buffer Empty 0: SSC_TCR or SSC_TNCR have a value other than 0. 1: Both SSC_TCR and SSC_TNCR have a value of 0. • RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. • OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. • ENDRX: End of Reception 0: Data is written on the Receive Counter Register or Receive Next Counter Register. 1: End of PDC transfer when Receive Counter Register has arrived at zero. • RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. • TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register.
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• RXSYN: Receive Sync 0: A Rx Sync has not occurred since the last read of the Status Register. 1: A Rx Sync has occurred since the last read of the Status Register.
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• TXEN: Transmit Enable 0: Transmit data is disabled. 1: Transmit data is enabled. • RXEN: Receive Enable 0: Receive data is disabled. 1: Receive data is enabled.
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SSC Interrupt Enable Register
Register Name: Access Type:
31 – 23 – 15 – 7 RXBUFF
SSC_IER W rite-only
30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY
• TXRDY: Transmit Ready • TXEMPTY: Transmit Empty • ENDTX: End of Transmission • TXBUFE: Transmit Buffer Empty • RXRDY: Receive Ready • OVRUN: Receive Overrun • ENDRX: End of Reception • RXBUFF: Receive Buffer Full • TXSYN: Tx Sync • RXSYN: Rx Sync 0: No effect. 1: Enables the corresponding interrupt.
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SSC Interrupt Disable Register
Register Name: Access Type:
31 – 23 – 15 – 7 RXBUFF
SSC_IDR W rite-only
30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY
• TXRDY: Transmit Ready • TXEMPTY: Transmit Empty • ENDTX: End of Transmission • TXBUFE: Transmit Buffer Empty • RXRDY: Receive Ready • OVRUN: Receive Overrun • ENDRX: End of Reception • RXBUFF: Receive Buffer Full • TXSYN: Tx Sync • RXSYN: Rx Sync 0: No effect. 1: Disables the corresponding interrupt.
350
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SSC Interrupt Mask Register
Register Name: Access Type:
31 – 23 – 15 – 7 RXBUFF
SSC_IMR Read-only
30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 – 1 TXEMPTY 24 – 16 – 8 – 0 TXRDY
• TXRDY: Transmit Ready • TXEMPTY: Transmit Empty • ENDTX: End of Transmission • TXBUFE: Transmit Buffer Empty • RXRDY: Receive Ready • OVRUN: Receive Overrun • ENDRX: End of Reception • RXBUFF: Receive Buffer Full • TXSYN: Tx Sync • RXSYN: Rx Sync 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
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Timer/Counter (TC)
Overview
The Timer/Counter (TC) includes three identical 16-bit Timer/Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer/Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained.
Block Diagram
Figure 85. Timer/Counter Block Diagram
TIMER_CLOCK1
Parallel I/O Controller TCLK0 TIOA1
TIMER_CLOCK2 TIMER_CLOCK3
TCLK0 TCLK1 TCLK2 TIOA0 TIOB0
TIOA2 TCLK1
XC0 XC1 XC2 TC0XC0S
Timer/Counter Channel 0
TIOA
TIOA0
TIOB
TIMER_CLOCK4 TIMER_CLOCK5
TCLK2
TIOB0
SYNC
INT0
TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S
SYNC
Timer/Counter Channel 1
TIOA
TIOA1
TIOB
TIOB1 INT1
TIOA1 TIOB1
TCLK0 TCLK1 TCLK2 TIOA0 TIOA1
XC0 XC1 XC2 TC2XC2S
Timer/Counter Channel 2
TIOA
TIOA2
TIOB
TIOB2
SYNC
TIOA2 TIOB2
INT2
Timer Counter Advanced Interrupt Controller
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Table 50. Signal Name Description
Block/Channel Signal Name XC0, XC1, XC2 TIOA Channel Signal TIOB INT SYNC Description External Clock Inputs Capture Mode: Timer/Counter Input Waveform Mode: Timer/Counter Output Capture Mode: Timer/Counter Input Waveform Mode: Timer/Counter Input/output Interrupt Signal Output Synchronization Input Signal
Pin Name List
Table 51. TC pin list
Pin Name TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2 Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O
Product Dependencies
I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer/Counter clock. The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC.
Power Management Interrupt
Functional Description
TC Description
16-bit Counter The three channels of the Timer/Counter are independent and identical in operation. The registers for channel programming are listed in Table 53 on page 366. Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set.
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The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 86. Each channel can independently select an internal or external clock source for its counter: • • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 External clock signals: XC0, XC1 or XC2
This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2).
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock
Figure 86. Clock Selection
TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI
Selected Clock
BURST
1
Clock Control
The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 87. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. 355
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•
The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled.
Figure 87. Clock Control
Selected Clock Trigger
CLKSTA
CLKEN
CLKDIS
Q Q S R
S R
Counter Clock
Stop Event
Disable Event
TC Operating Modes
Each channel can independently operate in two different modes: • • Capture Mode provides measurement on signals. Waveform Mode provides wave generation.
The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: • • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR.
•
The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR.
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If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock.
Capture Operating Mode
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 88 shows the configuration of the TC channel when programmed in Capture Mode.
Capture Registers A and B
Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten.
Trigger Conditions
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled.
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Figure 88. Capture Mode
358
CLKI CLKSTA CLKEN CLKDIS
TCCLKS
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
Q Q R S R
S
TIMER_CLOCK5
XC0
XC1 LDBSTOP LDBDIS
XC2
BURST Register C
1 16-bit Counter CLK OVF RESET Trig
Capture Register A SWTRG
AT91SAM7A3 Preliminary
Capture Register B Compare RC = ETRGEDG Edge Detector LDRA LDRB CPCTRG
CPCS LOVRS LDRAS LDRBS ETRGS COVFS TC1_SR
SYNC
ABETRG
MTIOB
TIOB
MTIOA If RA is not loaded or RB is Loaded
Edge Detector If RA is Loaded
Edge Detector
TC1_IMR
TIOA
Timer/Counter Channel
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INT
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Waveform Operating Mode
Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 89 shows the configuration of the TC channel when programmed in Waveform Operating Mode. Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.
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Edge Detector
TIOB TC1_IMR
BSWTRG
Timer/Counter Channel
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INT
Output Controller
AT91SAM7A3 Preliminary
CLKSTA ACPC CLKI CLKEN CLKDIS
BURST Register A WAVSEL Compare RA = 16-bit Counter
CLK RESET OVF
Register B
Register C ASWTRG
1
Compare RB =
Compare RC =
SWTRG
BCPC Trig BCPB WAVSEL MTIOB
SYNC
EEVT BEEVT EEVTEDG ENETRG CPCS CPAS CPBS ETRGS COVFS TC1_SR
Output Controller
360
Q
CPCDIS
TCCLKS
TIMER_CLOCK1
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
S R
ACPA MTIOA
TIMER_CLOCK5
Q R
CPCSTOP
S
XC0
XC1
Figure 89. Waveform Mode
XC2
AEEVT
TIOA
TIOB
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WAVSEL = 00
When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 90. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 91. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 90. WAVSEL= 00 without trigger
Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 91. WAVSEL= 00 with trigger
Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
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WAVSEL = 10
When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 92. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 93. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 92. WAVSEL = 10 Without Trigger
Counter Value 0xFFFF Counter cleared by compare match with RC RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 93. WAVSEL = 10 With Trigger
Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger
RA
Waveform Examples TIOB
Time
TIOA
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WAVSEL = 01
When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 94. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 95. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 94. WAVSEL = 01 Without Trigger
Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF
RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 95. WAVSEL = 01 With Trigger
Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF
Counter incremented by trigger
RA
Waveform Examples TIOB
Time
TIOA
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WAVSEL = 11
When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 96. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 97. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1).
Figure 96. WAVSEL = 11 Without Trigger
Counter Value 0xFFFF Counter decremented by compare match with RC RC RB
RA
Waveform Examples TIOB
Time
TIOA
Figure 97. WAVSEL = 11 With Trigger
Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger
RA
Waveform Examples TIOB
Time
TIOA
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External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The parameter EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR.
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Timer/Counter (TC) User Interface
Global Register Mapping
Table 52. Timer/Counter (TC) Global Register Mapping
Offset 0x00 0x40 0x80 0xC0 0xC4 Channel/Register TC Channel 0 TC Channel 1 TC Channel 2 TC Block Control Register TC Block Mode Register TC_BCR TC_BMR Name Access See Table 53 See Table 53 See Table 53 Write-only Read/Write – 0 Reset Value
TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in Table 53 . The offset of each of the channel registers in Table 53 is in relation to the offset of the corresponding channel as mentioned in Table 53.
Channel Memory Mapping
Table 53. Timer/Counter (TC) Channel Memory Mapping
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30-0xFC Note: Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Name TC_CCR TC_CMR – – TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR – Access Write-only Read/Write – – Read-only Read/Write Read/Write
(1) (1)
Reset Value – 0 – – 0 0 0 0 0 – – 0 –
Read/Write Read-only Write-only Write-only Read-only –
1. Read only if WAVE = 0
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TC Block Control Register
Register Name: TC_BCR Access Type:
31 – 23 – 15 – 7 –
Write-only
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 SYNC
• SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
TC Block Mode Register
Register Name: TC_BMR Access Type:
31 – 23 – 15 – 7 –
Read/Write
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 TC2XC2S 28 – 20 – 12 – 4 27 – 19 – 11 – 3 TCXC1S 26 – 18 – 10 – 2 25 – 17 – 9 – 1 TC0XC0S 24 – 16 – 8 – 0
• TC0XC0S: External Clock Signal 0 Selection
TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2
• TC1XC1S: External Clock Signal 1 Selection
TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2
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• TC2XC2S: External Clock Signal 2 Selection
TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1
TC Channel Control Register
Register Name: TC_CCR Access Type:
31 – 23 – 15 – 7 –
Write-only
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SWTRG 25 – 17 – 9 – 1 CLKDIS 24 – 16 – 8 – 0 CLKEN
• CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. • SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started.
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TC Channel Mode Register: Capture Mode
Register Name: TC_CMR Access Type:
31 – 23 – 15 WAVE = 0 7 LDBDIS
Read/Write
30 – 22 – 14 CPCTRG 6 LDBSTOP 29 – 21 – 13 – 5 BURST 28 – 20 – 12 – 4 11 – 3 CLKI 27 – 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 – 18 25 – 17 LDRA 8 24 – 16
• TCCLKS: Clock Selection
TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2
• CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection
BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock.
• LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. • LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs.
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• ETRGEDG: External Trigger Edge Selection
ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge
• ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection
LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA
• LDRB: RB Loading Selection
LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA
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TC Channel Mode Register: Waveform Mode
Register Name: TC_CMR Access Type:
31 BSWTRG 23 ASWTRG 15 WAVE = 1 7 CPCDIS 6 CPCSTOP 14 WAVSEL 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS
Read/Write
30 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24
• TCCLKS: Clock Selection
TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2
• CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection
BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock.
• CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. • CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC.
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• EEVTEDG: External Event Edge Selection
EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge
• EEVT: External Event Selection
EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input(1) output output output
1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms.
• ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. • WAVSEL: Waveform Selection
WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare
• WAVE = 1 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. • ACPA: RA Compare Effect on TIOA
ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle
• ACPC: RC Compare Effect on TIOA
ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle
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• AEEVT: External Event Effect on TIOA
AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle
• ASWTRG: Software Trigger Effect on TIOA
ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle
• BCPB: RB Compare Effect on TIOB
BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle
• BCPC: RC Compare Effect on TIOB
BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle
• BEEVT: External Event Effect on TIOB
BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle
• BSWTRG: Software Trigger Effect on TIOB
BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle
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TC Counter Value Register
Register Name: TC_CV Access Type:
31 – 23 – 15
Read-only
30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CV 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8
7
6
5
4 CV
3
2
1
0
• CV: Counter Value CV contains the counter value in real time.
TC Register A
Register Name: TC_RA Access Type:
31 – 23 – 15
Read-only if WAVE = 0, Read/Write if WAVE = 1
30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RA 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8
7
6
5
4 RA
3
2
1
0
• RA: Register A RA contains the Register A value in real time.
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TC Register B
Register Name: TC_RB Access Type:
31 – 23 – 15
Read-only if WAVE = 0, Read/Write if WAVE = 1
30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RB 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8
7
6
5
4 RB
3
2
1
0
• RB: Register B RB contains the Register B value in real time.
TC Register C
Register Name: TC_RC Access Type:
31 – 23 – 15
Read/Write
30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RC 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8
7
6
5
4 RC
3
2
1
0
• RC: Register C RC contains the Register C value in real time.
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TC Status Register
Register Name: TC_SR Access Type:
31 – 23 – 15 – 7 ETRGS
Read-only
30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 MTIOB 10 – 2 CPAS 25 – 17 MTIOA 9 – 1 LOVRS 24 – 16 CLKSTA 8 – 0 COVFS
• COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. • CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. • LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. 376
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• MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
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TC Interrupt Enable Register
Register Name: TC_IER Access Type:
31 – 23 – 15 – 7 ETRGS
Write-only
30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS
• COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. • CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. • CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. • CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. • LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. • ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt.
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TC Interrupt Disable Register
Register Name: TC_IDR Access Type:
31 – 23 – 15 – 7 ETRGS
Write-only
30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS
• COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). • CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). • CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). • CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). • ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt.
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TC Interrupt Mask Register
Register Name: TC_IMR Access Type:
31 – 23 – 15 – 7 ETRGS
Read-only
30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS
• COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. • CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. • CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. • CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. • LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. • LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. • ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled.
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Pulse Width Modulation Controller (PWM)
Overview
The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock. All PWM macrocell accesses are made through APB mapped registers. Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
Block Diagram
Figure 98. Pulse Width Modulation Controller Block Diagram
PWM Controller
PWMx Channel
Period Update Duty Cycle Comparator
PWMx PWMx
Clock Selector
Counter
PIO
PWM0 Channel
Period Update Duty Cycle Comparator
PWM0 PWM0
Clock Selector
MCK
Counter
PMC
Clock Generator
APB Interface
Interrupt Generator
AIC
APB
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I/O Lines Description
Each channel outputs one waveform on one external I/O line. Table 54. I/O Line Description
Name Description Type Output
PWMx
PWM Waveform Output for channel x
Product Dependencies
I/O Lines
The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not not be enabled. If an application requires only four channels then just four PIO lines will be assigned to PWM output.
Power Management
The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. Configuring the PWM does not require the PWM clock to be enabled.
Interrupt Sources
The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the PWM interrupt requires the AIC to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode.
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Functional Description
The PWM macrocell is primarily composed of a clock generator module and 8 channels. – – – Clocked by the system clock, MCK, the clock generator module provides 13 clocks. Each channel can independently choose one of the clock generator outputs. Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers.
PWM Clock Generator
Figure 99. Functional View of the Clock Generator Block Diagram
MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024
Divider A
clkA
PREA
DIVA
PWM_MR
Divider B
clkB
PREB
DIVB
PWM_MR
Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks: – – a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, F MCK/8, FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024 two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB
Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM
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Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR). After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management Controller.
PWM Channel
Block Diagram Figure 100. Functional View of the Channel Block Diagram
inputs from clock generator
Channel
Clock Selector Internal Counter PWMx output waveform
Comparator
inputs from APB bus
Each of the 8 channels is composed of three blocks: • • A clock selector which selects one of the clocks provided by the clock generator described in Section “PWM Clock Generator” on page 383. An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is 20 bits. A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration.
•
Waveform Properties
The different properties of output waveforms are: • the internal clock selection . The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0. the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. If the waveform is left aligned then: period = 1/fchannel_x_clock * CPRD If the waveform is center aligned then: period = 2/fchannel_x_clock * CPRD the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left aligned then: duty cycle = (period - 1/fchannel_x_clock * CDTY) / period If the waveform is center aligned, then: duty cycle = ((period / 2) - 1/fchannel_x_clock * CDTY)) / (period / 2) the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level.
•
•
•
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• the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned.
Figure 101. Non Overlapped Center Aligned Waveforms
No overlap
PWM0
PWM1
Period
Note:
1. See Figure 102 on page 386 for a detailed description of center aligned waveforms.
When center aligned, the internal channel counter increases up to CPRD and decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period. Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel. Waveforms are fixed at 0 when: • • • • CDTY = CPRD and CPOL = 0 CDTY = 0 and CPOL = 1 CDTY = 0 and CPOL = 0 CDTY = CPRD and CPOL = 1
Waveforms are fixed at 1 (once the channel is enabled) when:
The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled.
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Figure 102. Waveform Properties
PWM_MCKx
CHIDx(PWM_SR)
CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1
PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx)
Period Output Waveform PWMx CPOL(PWM_CMRx) = 0
Output Waveform PWMx CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx)
Left Aligned CALG(PWM_CMRx) = 0
Period Output Waveform PWMx CPOL(PWM_CMRx) = 0
Output Waveform PWMx CPOL(PWM_CMRx) = 1
CHIDx(PWM_ISR)
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PWM Controller Operations
Initialization Before enabling the output channel, this channel must have been configured by the software application: • • • • • • • • Configuration of the clock generator if DIVA and DIVB are required Selection of the clock for each channel (CPRE field in the PWM_CMRx register) Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) Configuration of the period for each channel (CPRD in the PWM_CPRDx register) Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register) Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register) Enable Interrupts (Writing CHIDx in the PWM_IER register) Enable the PWM channel (Writing CHIDx in the PWM_ENA register)
It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register. • In such a situation, all channels may have the same clock selector configuration and the same period specified.
Signal Modulation
It is possible to modulate the output waveform duty cycle or period. To prevent an unexpected output waveform when modifying the waveform parameters while the channel is still enabled, PWM_CPRDx and PWM_CDTYx registers are double buffered. Th e user can write a new pe riod value or du ty cycle value in the upda te re gister (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. According to the CPD field in the PWM_CMRx register, PWM_CUPDx either updates the PWM_CPRDx or PWM_CDTYx. The software can be synchronized to the waveform period by enabling the interrupt for the considered channel. The Interrupt Service Routine associated with the PWM channel must: • • clear the interrupt by reading the PWM_ISR register set the new value for the duty-cycle or the period in the PWM_CUPDx register
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Pulse Width Modulation Controller (PWM) User Interface
Table 55. Pulse Width Modulation Controller Registers
Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x4C - 0xFC 0x100 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 ... 0x220 0x224 0x228 0x22C 0x230 ... Register PWM Mode Register PWM Enable Register PWM Disable Register PWM Status Register PWM Interrupt Enable Register PWM Interrupt Disable Register PWM Interrupt Mask Register PWM Interrupt Status Register Reserved Reserved Channel 0 Mode Register Channel 0 Duty Cycle Register Channel 0 Period Register Channel 0 Counter Register Channel 0 Update Register Reserved Channel 1 Mode Register Channel 1 Duty Cycle Register Channel 1 Period Register Channel 1 Counter Register Channel 1 Update Register ... PWM_CMR1 PWM_CDTY1 PWM_CPRD1 PWM_CCNT1 PWM_CUPD1 ... Read/Write Read/Write Read/Write Read-only Write-only ... 0x0 0x0 0x0 0x0 ... Name PWM_MR PWM_ENA PWM_DIS PWM_SR PWM_IER PWM_IDR PWM_IMR PWM_ISR – – PWM_CMR0 PWM_CDTY0 PWM_CPRD0 PWM_CCNT0 PWM_CUPD0 Access Read/Write Write-only Write-only Read-only Write-only Write-only Read-only Read-only – – Read/Write Read/Write Read/Write Read-only Write-only Peripheral Reset Value 0 0 0 0 – – 0x0 0x0 0x0 0x0 -
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PWM Mode Register
Register Name: PWM_MR Access Type:
31 – 23
Read/Write
30 – 22 29 – 21 28 – 20 DIVB 27 26 PREB 19 18 17 16 25 24
15 – 7
14 – 6
13 – 5
12 – 4 DIVA
11
10 PREA
9
8
3
2
1
0
• DIVA, DIVB: CLKA, CLKB Divide Factor
DIVA, DIVB 0 1 2-255 CLKA, CLKB CLKA, CLKB clock is turned off CLKA, CLKB clock is clock selected by PREA, PREB CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor.
• PREA, PREB
PREA, PREB 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Other 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Divider Input Clock MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Reserved
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PWM Enable Register
Register Name: PWM_ENA Access Type:
31 – 23 – 15 – 7 CHID7
W rite-only
30 – 22 – 14 – 6 CHID6 29 – 21 – 13 – 5 CHID5 28 – 20 – 12 – 4 CHID4 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0
• CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x.
PWM Disable Register
Register Name: PWM_DIS Access Type:
31 – 23 – 15 – 7 CHID7
W rite-only
30 – 22 – 14 – 6 CHID6 29 – 21 – 13 – 5 CHID5 28 – 20 – 12 – 4 CHID4 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0
• CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x.
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PWM Status Register
Register Name: PWM_SR Access Type:
31 – 23 – 15 – 7 CHID7
Read-only
30 – 22 – 14 – 6 CHID6 29 – 21 – 13 – 5 CHID5 28 – 20 – 12 – 4 CHID4 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0
• CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled.
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PWM Interrupt Enable Register
Register Name: PWM_IER Access Type:
31 – 23 – 15 – 7 CHID7
W rite-only
30 – 22 – 14 – 6 CHID6 29 – 21 – 13 – 5 CHID5 28 – 20 – 12 – 4 CHID4 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0
• CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x.
PWM Interrupt Disable Register
Register Name: PWM_IDR Access Type:
31 – 23 – 15 – 7 CHID7
W rite-only
30 – 22 – 14 – 6 CHID6 29 – 21 – 13 – 5 CHID5 28 – 20 – 12 – 4 CHID4 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0
• CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x.
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PWM Interrupt Mask Register
Register Name: PWM_IMR Access Type:
31 – 23 – 15 – 7 CHID7
Read-only
30 – 22 – 14 – 6 CHID6 29 – 21 – 13 – 5 CHID5 28 – 20 – 12 – 4 CHID4 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0
• CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled.
PWM Interrupt Status Register
Register Name: PWM_ISR Access Type:
31 – 23 – 15 – 7 CHID7
Read-only
30 – 22 – 14 – 6 CHID6 29 – 21 – 13 – 5 CHID5 28 – 20 – 12 – 4 CHID4 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0
• CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register.
Note: Reading PWM_ISR automatically clears CHIDx flags.
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PWM Channel Mode Register
Register Name: PWM_CMRx Access Type:
31 – 23 – 15 – 7 –
Read/Write
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 26 – 18 – 10 CPD 2 CPRE 25 – 17 – 9 CPOL 1 24 – 16 – 8 CALG 0
• CPRE: Channel Pre-scaler
CPRE 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Other 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Channel Pre-scaler MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 CLKA CLKB Reserved
• CALG: Channel Alignment 0 = The period is left aligned. 1 = The period is center aligned. • CPOL: Channel Polarity 0 = The output waveform starts at a low level. 1 = The output waveform starts at a high level. • CPD: Channel Update Period 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1 = Writing to the PWM_CUPDx will modify the period at the next period start event.
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PWM Channel Duty Cycle Register
Register Name: PWM_CDTYx Access Type:
31
Read/Write
30 29 28 CDTY 27 26 25 24
23
22
21
20 CDTY
19
18
17
16
15
14
13
12 CDTY
11
10
9
8
7
6
5
4 CDTY
3
2
1
0
Only the first 20 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx).
PWM Channel Period Register
Register Name: PWM_CPRDx Access Type:
31
Read/Write
30 29 28 CPRD 27 26 25 24
23
22
21
20 CPRD
19
18
17
16
15
14
13
12 CPRD
11
10
9
8
7
6
5
4 CPRD
3
2
1
0
Only the first 20 bits (internal channel counter size) are significant. • CPRD: Channel Period If the waveform is left aligned (CALG set to 0 in the PWM_CMRx register), the waveform period is CPRD * TMCK / CPRE. If the waveform is center aligned (CALG set to 1 in the PWM_CMRx register), the waveform period is 2 * CPRD * TMCK / CPRE.
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PWM Channel Counter Register
Register Name: PWM_CCNTx Access Type:
31
Read-only
30 29 28 CNT 27 26 25 24
23
22
21
20 CNT
19
18
17
16
15
14
13
12 CNT
11
10
9
8
7
6
5
4 CNT
3
2
1
0
• CNT: Channel Counter Register Internal counter value. This register is reset when: • • the channel is enabled (writing CHIDx in the PWM_ENA register). the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned.
PWM Channel Update Register
Register Name: PWM_CUPDx Access Type:
31
W rite-only
30 29 28 CUPD 27 26 25 24
23
22
21
20 CUPD
19
18
17
16
15
14
13
12 CUPD
11
10
9
8
7
6
5
4 CUPD
3
2
1
0
This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle. Only the first 20 bits (internal channel counter size) are significant.
CPD (PWM_CMRx Register) 0 1 The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the beginning of the next period. The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning of the next period.
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USB Device Port (UDP)
Overview
The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral. This feature is mandatory for isochronous endpoints. Thus the device maintains the maximum bandwidth (1M bytes/s) by working with endpoints with two banks of DPR. Table 56. U SB Endpoint Description
Endpoint Number 0 1 3 3 4 5 Mnemonic EP0 EP1 EP2 EP3 EP4 EP5 Dual-bank No Yes Yes No Yes Yes Max. Endpoint Size 8 64 64 64 512 512 Endpoint Type Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt Control/Bulk/Interrupt Bulk/Iso/Interrupt Bulk/Iso/Interrupt
Suspend and resume are automatically detected by the USB device, which notifies the processor by raising an interrupt. Depending on the product, an external signal can be used to send a wake-up to the USB host controller.
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Block Diagram
Figure 103. Block Diagram
Atmel Bridge APB to MCU Bus
USB Device
txoen
MCK UDPCK
U s e r I n t e r f a c e
W r a p p e r
Dual Port RAM FIFO
W r a p p e r
eopn
Serial Interface Engine
12 MHz
txd rxdm rxd rxdp
Embedded USB Transceiver
DP DM
SIE
udp_int
Suspend/Resume Logic Master Clock Domain Recovered 12 MHz Domain
external_resume
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by reading and writing 8-bit values to APB registers. The UDP peripheral requires two clocks: one peripheral clock used by the MCK domain and a 48 MHz clock used by the 12 MHz domain. A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake-up once in system mode. The host is then notified that the device asks for a resume. This optional feature must be also negotiated with the host during the enumeration.
Product Dependencies
For further details on the USB Device hardware implementation, see “USB Device Port” on page 27. The USB physical transceiver is integrated into the product. The bidirectional differential signals DP and DM are available from the product boundary. Two I/O lines may be used by the application: • One to check that VBUS is still available from the host. Self-powered devices may use this entry to be notified that the host has been powered off. In this case, the board pull-up on DP must be disabled in order to prevent feeding current to the host. One to control the board pull-up on DP. Thus, when the device is ready to communicate with the host, it activates its DP pull-up through this control line.
•
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I/O Lines
DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver is controlled by the USB device peripheral. To reserve an I/O line to check VBUS, the programmer must first program the PIO controller to assign this I/O in input PIO mode. To reserve an I/O line to control the board pull-up, the programmer must first program the PIO controller to assign this I/O in output PIO mode.
Power Management
The USB device peripheral requires a 48 MHz clock. This clock must be generated by a PLL with an accuracy of ± 0.25%. Thus, the USB device receives two clocks from the Power Management Controller (PMC): the master clock, MCK, used to drive the peripheral user interface, and the UDPCK, used to interface with the bus USB signals (recovered 12 MHz domain).
Interrupt
The USB device interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the USB device interrupt requires programming the AIC before configuring the UDP.
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Typical Connection
Figure 104. Board Schematic to Interface USB Device Peripheral
PAm
USB_CNX
15 kΩ
22 kΩ
3V3
1.5 kΩ
47 kΩ PAn
USB_DP_PUP
System Reset 27Ω
33 pF 2 1 100 nF 27Ω 15 pF
Type B 4 Connector
DM DP 15 pF
3
USB_CNX is an input signal used to check if the host is connected USB_DP_PUP is an output signal used to enable pull-up on DP. Figure 104 shows automatic activation of pull-up after reset.
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Functional Description
USB V2.0 Fullspeed Introduction
The USB V2.0 full-speed provides communication services between host and attached USB devices. Each device is offered with a collection of communication flows (pipes) associated with each endpoint. Software on the host communicates with an USB device through a set of communication flows.
Figure 105. Example of USB V2.0 Full-speed Communication Control
USB Host V2.0 Software Client 1 Software Client 2
Data Flow: Control Transfer Data Flow: Isochronous In Transfer Data Flow: Isochronous Out Transfer
EP0 EP1 EP2 USB Device 2.0 Block 1
Data Flow: Control Transfer Data Flow: Bulk In Transfer Data Flow: Bulk Out Transfer
EP0 EP4 EP5 USB Device 2.0 Block 2
USB V2.0 Full-speed Transfer Types
A communication flow is carried over one of four transfer types defined by the USB device.
Table 57. U SB Communication Flow
Transfer Control Isochronous Interrupt Bulk Direction Bi-directional Uni-directional Uni-directional Uni-directional Bandwidth Not guaranteed Guaranteed Not guaranteed Not guaranteed Endpoint Size 8, 16, 32, 64 1 - 1023 ≤64 8, 16, 32, 64 Error Detection Yes Yes Yes Yes Retrying Automatic No Yes Yes
USB Bus Transactions
Each transfer results in one or more transactions over the USB bus. There are five kinds of transactions flowing across the bus in packets: 1. Setup Transaction 2. Data IN Transaction 3. Data OUT Transaction 4. Status IN Transaction 5. Status OUT Transaction
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USB Transfer Event Definitions
As indicated below, transfers are sequential events carried out on the USB bus. Table 58. U SB Transfer Events
Control Transfers(1) (3)
• • • • • • • • •
Setup transaction > Data IN transactions > Status OUT transaction Setup transaction > Data OUT transactions > Status IN transaction Setup transaction > Status IN transaction Data IN transaction > Data IN transaction Data OUT transaction > Data OUT transaction Data IN transaction > Data IN transaction Data OUT transaction > Data OUT transaction Data IN transaction > Data IN transaction Data OUT transaction > Data OUT transaction
Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes:
1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake.
Handling Transactions with USB V2.0 Device Peripheral
Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: • • • The USB device automatically acknowledges the setup packet RXSETUP is set in the USB_CSRx register An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint.
Thus, firmware must detect the RXSETUP polling the USB_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO.
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Figure 106. Setup Transaction Followed by a Data OUT Transaction
Setup Received Setup Handled by Firmware Data Out Received
USB Bus Packets
Setup PID
Data Setup
ACK PID
Data OUT PID
Data OUT
NAK PID
Data OUT PID
Data OUT
ACK PID
RXSETUP Flag
Interrupt Pending
Set by USB Device
Cleared by Firmware Set by USB Device Peripheral
RX_Data_BKO (USB_CSRx)
FIFO (DPR) Content
XX
Data Setup
XX
Data OUT
Data IN Transaction
Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes. To perform a Data IN transaction using a non ping-pong endpoint: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s USB_CSRx register (TXPKTRDY must be cleared). 2. The microcontroller writes data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s USB_FDRx register, 3. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s USB_CSRx register. 4. The microcontroller is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s USB_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set.
Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer.
Using Endpoints Without Ping-pong Attributes
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Figure 107. Data IN Transfer for Non Ping-pong Endpoint
Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus
USB Bus Packets
Data IN PID
Data IN 1
ACK PID
Data IN PID
NAK PID
Data IN PID
Data IN 2
ACK PID
TXPKTRDY Flag (USB_CSRx) Cleared by USB Device Interrupt Pending TXCOMP Flag (USB_CSRx) Cleared by Firmware Set by the Firmware Data Payload Written in FIFO Start to Write Data Payload in FIFO Interrupt Pending
FIFO (DPR) Content
Data IN 1
Load In Progress
Data IN 2
Load In Progress
Using Endpoints With Ping-pong Attribute
The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. To be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 108. Bank Swapping Data IN Transfer for Ping-pong Endpoints
Microcontroller 1st Data Payload Write Bank 0 Endpoint 1 USB Device Read USB Bus
Read and Write at the Same Time
2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1
Data IN Packet 1st Data Payload
Data IN Packet 2nd Data Payload
Bank 0 Endpoint 1
Data IN Packet 3rd Data Payload
When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s USB_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s USB_FDRx register.
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3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s USB_CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s USB_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s USB_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent rising TXPKTRDY in the endpoint’s USB_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 109. Data IN Transfer for Ping-pong Endpoint
Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1
USB Bus Packets
Data IN PID
Data IN
ACK PID
Data IN PID
Data IN
ACK PID
TXPKTRDY Flag (USB_MCSRx)
Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (USB_CSRx)
Cleared by USB Device, Data Payload Fully Transmitted Set by USB Device
Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device
Interrupt Cleared by Firmware
FIFO (DPR) Written by Microcontroller Bank 0
Read by USB Device
Written by Microcontroller
FIFO (DPR) Bank 1
Written by Microcontroller
Read by USB Device
Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set is too long, some Data IN packets may be NACKed, reducing the bandwidth. Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once 407
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Data OUT Transaction Without Ping-pong Attributes
the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s USB_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s USB_CSRx register. 5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the endpoint’s USB_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s USB_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 110. Data OUT Transfer for Non Ping-pong Endpoints
Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload
USB Bus Packets
Data OUT PID
Data OUT 1
ACK PID
Data OUT2 Data OUT2 NAK PID PID
Data OUT PID
Data OUT2
ACK PID
RX_DATA_BK0 (USB_CSRx)
Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device
FIFO (DPR) Content
Data OUT 1 Written by USB Device
Data OUT 1 Microcontroller Read
An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO.
Using Endpoints With Ping-pong Attributes
During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device.
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Figure 111. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints
Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus
Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1
Bank 1 Endpoint 1
Data IN Packet 2nd Data Payload
Bank 0 Endpoint 1
Data IN Packet 3rd Data Payload
When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s USB_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s USB_CSRx register. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s USB_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s USB_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s USB_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s USB_FDRx register. 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s USB_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0.
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Figure 112. Data OUT Transfer for Ping-pong Endpoint
Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload
USB Bus Packets
Data OUT PID
Data OUT 1
ACK PID
Data OUT PID
Data OUT 2
ACK PID
Data OUT PID
Data OUT 3
A P
RX_DATA_BK0 Flag (USB_CSRx)
Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0
Cleared by Firmware
RX_DATA_BK1 Flag (USB_CSRx)
Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1
Cleared by Firmware Interrupt Pending
FIFO (DPR) Bank 0
Data OUT1 Write by USB Device
Data OUT 1 Read By Microcontroller
Data OUT 3 Write In Progress
FIFO (DPR) Bank 1
Data OUT 2 Write by USB Device
Data OUT 2 Read By Microcontroller
Note:
An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set.
Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. Status Transaction A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction.
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Figure 113. Control Read and Write Sequences
Setup Stage Data Stage Status Stage
Control Read
Setup TX
Data OUT TX
Data OUT TX
Status IN TX
Setup Stage
Data Stage
Status Stage
Control Write
Setup TX
Data IN TX
Data IN TX
Status OUT TX
Setup Stage
Status Stage
No Data Control
Notes:
Setup TX
Status IN TX
1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data).
Status IN Transfer
Once a control request has been processed, the device returns a status to the host. This is a zero length Data IN transaction. 1. The microcontroller waits for TXPKTRDY in the USB_CSRx endpoint’s register to be cleared. (At this step, TXPKTRDY must be cleared because the previous transaction was a setup transaction or a Data OUT transaction.) 2. Without writing anything to the USB_FDRx endpoint’s register, the microcontroller sets TXPKTRDY. The USB device generates a Data IN packet using DATA1 PID. 3. This packet is acknowledged by the host and TXPKTRDY is set in the USB_CSRx endpoint’s register. Figure 114. Data Out Followed by Status IN Transfer.
Host Sends the Last Data Payload to the Device USB Bus Packets Device Sends a Status IN to the Host
Data OUT PID
Data OUT
NAK PID
Data IN PID
ACK PID
Interrupt Pending RX_DATA_BKO (USB_CSRx) Cleared by Firmware Set by USB Device Cleared by USB Device TXPKTRDY (USB_CSRx) Set by Firmware
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Status OUT Transfer
O nce a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. This is a zero length Data OUT transaction. 1. The USB device receives a zero length packet. It sets RX_DATA_BK0 flag in the USB_CSRx register and acknowledges the zero length packet. 2. The microcontroller is notified that the USB device has received a zero length packet sent by the host polling RX_DATA_BK0 in the USB_CSRx register. An interrupt is pending while RX_DATA_BK0 is set. The number of bytes received in the endpoint’s USB_BCR register is equal to zero. 3. The microcontroller must clear RX_DATA_BK0. Figure 115. Data IN Followed by Status OUT Transfer
Device Sends the Last Data Payload to Host USB Bus Packets Data IN PID Data IN ACK PID Device Sends a Status OUT to Host Data OUT PID ACK PID Interrupt Pending RX_DATA_BKO (USB_CSRx) Set by USB Device Cleared by Firmware
TXCOMP (USB_CSRx) Set by USB Device Cleared by Firmware
Stall Handshake
A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) • A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) To abort the current request, a protocol stall is used, but uniquely with control transfer.
•
The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the USB_CSRx endpoint’s register. 2. The host receives the stall packet. 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set.
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Figure 116. Stall Handshake (Data IN Transfer)
USB Bus Packets Data IN PID Stall PID
Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device
Figure 117. Stall Handshake (Data OUT Transfer)
USB Bus Packets Data OUT PID Data OUT Stall PID
FORCESTALL
Set by Firmware Interrupt Pending
STALLSENT Set by USB Device
Cleared by Firmware
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Controlling Device States
A USB device has several possible states. Refer to Chapter 9 of the U niversal Serial Bus Specification, Rev 2.0. Figure 118. USB Device State Diagram
Attached
Hub Reset or Deconfigured
Hub Configured
Bus Inactive
Powered
Bus Activity Power Interruption
Suspended
Reset
Bus Inactive
Default
Reset Address Assigned Bus Inactive Bus Activity
Suspended
Address
Bus Activity Device Deconfigured Device Configured Bus Inactive
Suspended
Configured
Bus Activity
Suspended
Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the UDP device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse. The wake-up feature is not mandatory for all devices and must be negotiated with the host.
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From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The USB host stops driving a reset state once it has detected the device’s pull-up on DP. The unmasked flag ENDBURST is set in the register UDP_ISR and an interrupt is triggered. The UDP software enables the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. After a set address standard device request, the USB host peripheral enters the address state. Before this, it achieves the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To m ove to address s tate, t he driv er sof tware set s the FA DDEN f lag in t he UDP_GLB_STATE, sets its new address, and sets the FEN bit in the UDP_FADDR register. From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register. This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks may be switched off. However, the transceiver and the USB peripheral must not be switched off, otherwise the resume is not detected. Receiving a Host Resume In suspend mode, the USB transceiver and the USB peripheral must be powered to detect the RESUME. However, the USB device peripheral may not be clocked as the WAKEUP signal is asynchronous. Once the resume is detected on the bus, the signal WAKEUP in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register. Sending an External Resume The External Resume is negotiated with the host and enabled by setting the ESR bit in the USB_GLB_STATE. An asynchronous event on the ext_resume_pin of the peripheral generates a WAKEUP interrupt. On early versions of the USP peripheral, the K-state on the USB line is generated immediately. This means that the USB device must be able to answer to the ho st very q uickly . On r ece nt ver sio ns, the softwa re se ts the R MWU PE bit in th e UDP_GLB_STATE register once it is ready to communicate with the host. The K-state on the bus is then generated. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register.
From Default State to Address State
Enabling Suspend
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USB Device Port (UDP) User Interface
Table 59. U SB Device Port (UDP) Register Mapping
Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 . . . See Note 1 0x050 . . . See Note 2 0x070 0x074 0x078 - 0x0FC Notes: Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint 0 Control and Status Register . . . Endpoint 4 Control and Status Register Endpoint 0 FIFO Data Register . . . Endpoint 4 FIFO Data Register Reserved Transceiver Control Register Reserved USB_FDR4 – USB_TXVC – Read/write – Read/write – 0x0000_0000 – 0x0000_0100 – USB _CSR4 USB_FDR0 Read/write Read/write 0x0000_0000 0x0000_0000 Name USB_FRM_NUM USB_GLB_STAT USB_FADDR – USB_IER USB_IDR USB_IMR USB_ISR USB_ICR – USB_RST_EP – USB _CSR0 Access Read Read/write Read/write – Write Write Read Read Write – Read/write – Read/write – 0x0000_0000 – 0x0000_1200 0x0000_0000 Reset State 0x0000_0000 0x0000_0010 0x0000_0100 –
1. The addresses of the USB_CSRx registers are calculated as: 0x030 + 4(Endpoint Number - 1). 2. The addresses of the USB_FDRx registers are calculated as: 0x050 + 4(Endpoint Number - 1).
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USB Frame Number Register
Register Name: Access Type:
31 – 23 – 15 – 7
USB_FRM_NUM Read-only
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FRM_NUM 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 FRM_OK 9 FRM_NUM 1 24 – 16 FRM_ERR 8
2
0
• FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). • FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. • FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP.
Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L.
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USB Global State Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_GLB_STAT Read/Write
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 RMWUPE 27 – 19 – 11 – 3 RSMINPR 26 – 18 – 10 – 2 ESR 25 – 17 – 9 – 1 CONFG 24 – 16 – 8 – 0 FADDEN
This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the USB_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • ESR: Enable Send Resume 0 = Disables the Remote Wake Up sequence. 1 = Remote Wake Up can be processed and the pin send_resume is enabled. • RSMINPR: A Resume Has Been Sent to the Host Read: 0 = No effect. 1 = A Resume has been received from the host during Remote Wake Up feature.
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• RMWUPE: Remote Wake Up Enable 0 = Must be cleared after receiving any HOST packet or SOF interrupt. 1 = Enables the K-state on the USB cable if ESR is enabled.
USB Function Address Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_FADDR Read/Write
30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 FADD 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 FEN 0
• FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. • FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host.
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USB Interrupt Enable Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_IER Write-only
30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT
• EP0INT: Enable Endpoint 0 Interrupt • EP1INT: Enable Endpoint 1 Interrupt • EP2INT: Enable Endpoint 2Interrupt • EP3INT: Enable Endpoint 3 Interrupt • EP4INT: Enable Endpoint 4 Interrupt • EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. • RXSUSP: Enable USB Suspend Interrupt 0 = No effect. 1 = Enables USB Suspend Interrupt. • RXRSM: Enable USB Resume Interrupt 0 = No effect. 1 = Enables USB Resume Interrupt. • EXTRSM: Enable External Resume Interrupt 0 = No effect. 1 = Enables External Resume Interrupt. • SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. • WAKEUP: Enable USB bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt.
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USB Interrupt Disable Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_IDR Write-only
30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT
• EP0INT: Disable Endpoint 0 Interrupt • EP1INT: Disable Endpoint 1 Interrupt • EP2INT: Disable Endpoint 2 Interrupt • EP3INT: Disable Endpoint 3 Interrupt • EP4INT: Disable Endpoint 4 Interrupt • EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. • RXSUSP: Disable USB Suspend Interrupt 0 = No effect. 1 = Disables USB Suspend Interrupt. • RXRSM: Disable USB Resume Interrupt 0 = No effect. 1 = Disables USB Resume Interrupt. • EXTRSM: Disable External Resume Interrupt 0 = No effect. 1 = Disables External Resume Interrupt. • SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt • WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt.
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USB Interrupt Mask Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_IMR Read-only
30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT
• EP0INT: Mask Endpoint 0 Interrupt • EP1INT: Mask Endpoint 1 Interrupt • EP2INT: Mask Endpoint 2 Interrupt • EP3INT: Mask Endpoint 3 Interrupt • EP4INT: Mask Endpoint 4 Interrupt • EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. • RXSUSP: Mask USB Suspend Interrupt 0 = USB Suspend Interrupt is disabled. 1 = USB Suspend Interrupt is enabled. • RXRSM: Mask USB Resume Interrupt. 0 = USB Resume Interrupt is disabled. 1 = USB Resume Interrupt is enabled. • EXTRSM: Mask External Resume Interrupt 0 = External Resume Interrupt is disabled. 1 = External Resume Interrupt is enabled. • SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. • WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled.
Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register USB_IMR is enabled.
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USB Interrupt Status Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_ISR Read-only
30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 ENDBUSRES 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT
• EP0INT: Endpoint 0 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding USB_CSR0 bit. • EP1INT: Endpoint 1 Interrupt Status 0 = No Endpoint1 Interrupt pending. 1 = Endpoint1 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR1: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding USB_CSR1 bit. • EP2INT: Endpoint 2 Interrupt Status 0 = No Endpoint2 Interrupt pending. 1 = Endpoint2 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR2: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1
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TXCOMP set to 1 STALLSENT set to 1 EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding USB_CSR2 bit. • EP3INT: Endpoint 3 Interrupt Status 0 = No Endpoint3 Interrupt pending. 1 = Endpoint3 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR3: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding USB_CSR3 bit. • EP4INT: Endpoint 4 Interrupt Status 0 = No Endpoint4 Interrupt pending. 1 = Endpoint4 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR4: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP4INT is a sticky bit. Interrupt remains valid until EP4INT is cleared by writing in the corresponding USB_CSR4 bit. • EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint5 Interrupt pending. 1 = Endpoint5 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading USB_CSR5: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP5INT is a sticky bit. Interrupt remains valid until EP5INT is cleared by writing in the corresponding USB_CSR5 bit. • RXSUSP: USB Suspend Interrupt Status 0 = No USB Suspend Interrupt pending. 1 = USB Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. • RXRSM: USB Resume Interrupt Status 0 = No USB Resume Interrupt pending.
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1 =USB Resume Interrupt has been raised. The USB device sets this bit when a USB resume signal is detected at its port. • EXTRSM: External Resume Interrupt Status 0 = No External Resume Interrupt pending. 1 = External Resume Interrupt has been raised. This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus. • SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a USB reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. • WAKEUP: USB Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear.
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USB Interrupt Clear Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_ICR Write-only
30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 – 28 – 20 – 12 ENDBURST 4 – 27 – 19 – 11 SOFINT 3 – 26 – 18 – 10 EXTRSM 2 – 25 – 17 – 9 RXRSM 1 – 24 – 16 – 8 RXSUSP 0 –
• RXSUSP: Clear USB Suspend Interrupt 0 = No effect. 1 = Clears USB Suspend Interrupt. • RXRSM: Clear USB Resume Interrupt 0 = No effect. 1 = Clears USB Resume Interrupt. • EXTRSM: Clear External Resume Interrupt 0 = No effect. 1 = Clears External Resume Interrupt. • SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. • ENDBURST: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. • WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt.
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USB Reset Endpoint Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_RST_EP Read/write
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 EP4 27 – 19 – 11 – 3 EP3 26 – 18 – 10 – 2 EP2 25 – 17 – 9 – 1 EP1 24 – 16 – 8 – 0 EP0
• EP0: Reset Endpoint 0 • EP1: Reset Endpoint 1 • EP2: Reset Endpoint 2 • EP3: Reset Endpoint 3 • EP4: Reset Endpoint 4 • EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear USB_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in USB_CSRx register.
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USB Endpoint Control and Status Register
Register Name: Access Type:
31 – 23
USB_CSRx [x = 0..4] Read/Write
30 – 22 29 – 21 28 – 20 RXBYTECNT 27 – 19 26 25 RXBYTECNT 17 24
18
16
15 EPEDS 7 DIR
14 – 6 RX_DATA_ BK1
13 – 5 FORCE STALL
12 – 4 TXPKTRDY
11 DTGLE 3 STALLSENT ISOERROR
10
9 EPTYPE 1 RX_DATA_ BK0
8
2 RXSETUP
0 TXCOMP
• TXCOMP: Generates an IN packet with data previously written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. • RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the USB_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. • RXSETUP: Sends STALL to the Host (Control Endpoints) This flag generates an interrupt while it is set to one. Read:
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0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the USB_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transactions is not accepted while RXSETUP is set. • STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints) / ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake.
ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = Data values can be written in the FIFO. 1 = Data values can not be written in the FIFO. Write: 0 = No effect. 430
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1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the USB_FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. • FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Write-only 0 = No effect. 1 = Sends STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: Notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. • RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO’s Bank 1. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through USB_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. • DIR: Transfer Direction (only available for control endpoints) Read/Write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before USB_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. • EPTYPE[2:0]: Endpoint Type Read/Write
000 001 101 Control Isochronous OUT Isochronous IN
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Read/Write
010 110 011 111 Bulk OUT Bulk IN Interrupt OUT Interrupt IN
• DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the U niversal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions.
• EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. • RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the USB_FDRx register.
USB FIFO Data Register
Register Name: Access Type:
31 – 23 – 15 –
USB_FDRx [x = 0..4] Read/Write
30 – 22 – 14 – 29 – 21 – 13 – 28 – 20 – 12 – 27 – 19 – 11 – 26 – 18 – 10 – 25 – 17 – 9 – 24 – 16 – 8 –
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7
6
5
4 FIFO_DATA
3
2
1
0
• FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding USB_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information.
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USB Transceiver Control Register
Register Name: Access Type:
31 – 23 – 15 – 7 –
USB_TXVC Read/write
30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 TXVDIS 0 –
• TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared.
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MultiMedia Card Interface (MCI)
Description
The MultiMedia Card Interface (MCI) supports the MultiMediaCard (MMC) Specification V2.2 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral Data Controller channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of one slot. Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with an SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMediaCard on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology.
Block Diagram
Figure 119. Block Diagram
APB Bridge
PDC APB MCCK MCCDA MCI Interface PMC MCK PIO MCDA0 MCDA1 MCDA2 Interrupt Control MCDA3
MCI Interrupt
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Application Block Diagram
Figure 120. Application Block Diagram
Application Layer ex: File System, Audio, Security, etc.
Physical Layer MCI Interface
1 2 3 4 5 6 78 1234567 MMC 9
SDCard
Pin Name List
Table 1. I/O Lines Description
Pin Name MCCDA MCCK MCDA0 - MCDA3 Note: Pin Description Command/response Clock Data 0..3 of Slot A Type(1) I/O/PP/OD I/O I/O/PP Comments CMD of an MMC or SD Card CLK of an MMC or SD Card DAT0 of an MMC DAT[0..3] of an SD Card
1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
Product Dependencies
I/O Lines
The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first to configure the PMC to enable the MCI clock. The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI.
Power Management Interrupt
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Bus Topology
Figure 121. Multimedia Memory Card Bus Topology
1234567 MMC
The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 2. Bus Topology
Pin Number 1 2 3 4 5 6 7 Note: Name RSV CMD VSS1 VDD CLK VSS2 DAT[0] Type(1) NC I/O/PP/OD S S I/O S I/O/PP Description Not connected Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 MCCDx VSS VDD MCCK VSS MCDx0 MCI Pin Name (Slot x)
1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
Figure 122. MMC Bus Connections (One Slot)
MCI
MCCDA
MCDA0
MCCK
1234567 MMC1
1234567 MMC2
1234567 MMC3
Figure 123. SD Memory Card Bus Topology
1 2 3 4 5 6 78 9
SD CARD
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The SD Memory Card bus includes the signals listed in Table 3. Table 3. SD Memory Card Bus Signals
Pin Number 1 2 3 4 5 6 7 8 9 Note: Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type(1) I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 Data line Bit 2 MCI Pin Name (Slot x) MCDx3 MCCDx VSS VDD MCCK VSS MCDx0 MCDx1 MCDx2
1. I: input, O: output, PP: Push Pull, OD: Open Drain
Figure 124. SD Card Bus Connections with One Slot
MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78
SD CARD
When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs.
MultiMedia Card Operations
After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line.
•
•
Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification Version 2.2. See also Table 4 on page 439. MultiMediaCard bus data transfers are composed of these tokens.
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There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCCK. Two types of data transfer commands are defined: • Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. Block-oriented commands: These commands send a data block succeeded by CRC bits.
•
Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read. The MCI provides a set of registers to perform the entire range of MultiMedia Card operations.
Command Response Operation
After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The bit PWSEN allows saving power by dividing the MCI clock by 2PWSDIV (MCI_MR) when the bus is inactive. The command and the response of the card are clocked out with the rising edge of the MCCK. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification Version 2.2. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command:
Host Command CMD S T Content CRC E Z NID C ycles ****** Z S T CID Content Z Z Z
The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 4 and Table 5. Table 4. ALL_SEND_CID Command Description
CMD Index CMD2 Type bcr Argument [31:0] stuff bits Resp R2 Abbreviation ALL_SEND_CID Command Description Asks all cards to send their CID numbers on the CMD line
Note:
bcr means broadcast command with response.
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Table 5. Fields and Values for MCI_CMDR Command Register
Field CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command)
The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • • Fill the argument register (MCI_ARGR) with the command argument. Set the command register (MCI_CMDR) (see Table 5).
The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method.
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Figure 125. Command/Response Functional Flow Diagram
Set the command argument MCI_ARGR = Argument(1)
Set the command MCI_CMDR = Command
Read MCI_SR
Wait for command ready status flag
0 CMDRDY
1
Check error bits in the status register (1)
Yes Status error flags?
Read response if required RETURN ERROR(1) RETURN OK
Note:
1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMediaCard specification).
Data Transfer Operation
The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These operations can be done using the features of the Peripheral Data Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length must be defined in the mode register.
Read Operation
The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 126), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. These two methods can be applied for all MultiMedia Card read functions.
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Figure 126. Read Functional Flow Diagram
Send command SEL_DESEL_CARD to select the card
Send command SET_BLOCKLEN
No Read with PDC
Yes
Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght PROPAG = 1
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Finally: CAN_BR = 0x005F0133
CAN Bus Synchronization
Two types of synchronization are distinguished: “hard synchronization” at the start of a frame and “resynchronization” inside a frame. After a hard synchronization, the bit time is restarted with the end of the SYNC segment, regardless of the phase error. Resynchronization causes a reduction or increase in the bit time so that the position of the sample point is shifted with respect to the detected edge. The effect of resynchronization is the same as that of hard synchronization when the magnitude of the phase error of the edge causing the resynchronization is less than or equal to the programmed value of the resynchronization jump width (tSJW). When the magnitude of the phase error is larger than the resynchronization jump width and • • and the phase error is positive, then PHASE_SEG1 is lengthened by an amount equal to the resynchronization jump width. the phase error is negative, then PHASE_SEG2 is shortened by an amount equal to the resynchronization jump width.
Autobaud Mode
The autobaud feature is enabled by setting the ABM field in the CAN_MR register. In this mode, the CAN controller is only listening to the line without acknowledging the received messages. It can not send any message. The errors flags are updated. The bit timing can be adjusted until no error occurs (good configuration found). In this mode, the error counters are frozen. To go back to the standard mode, the ABM bit must be cleared in the CAN_MR register. There are five different error types that are not mutually exclusive. Each error concerns only specific fields of the CAN data frame (refer to the Bosch CAN specification for their correspondence): • CRC error (CERR bit in the CAN_SR register): With the CRC, the transmitter calculates a checksum for the CRC bit sequence from the Start of Frame bit until the end of the Data Field. This CRC sequence is transmitted in the CRC field of the Data or Remote Frame. Bit-stuffing error (SERR bit in the CAN_SR register): If a node detects a sixth consecutive equal bit level during the bit-stuffing area of a frame, it generates an Error Frame starting with the next bit-time. Bit error (BERR bit in CAN_SR register): A bit error occurs if a transmitter sends a dominant bit but detects a recessive bit on the bus line, or if it sends a recessive bit but detects a dominant bit on the bus line. An error frame is generated and starts with the next bit time. Form Error (FERR bit in the CAN_SR register): If a transmitter detects a dominant bit in one of the fix-formatted segments CRC Delimiter, ACK Delimiter or End of Frame, a form error has occurred and an error frame is generated. Acknowledgment error (AERR bit in the CAN_SR register): The transmitter checks the Acknowledge Slot, which is transmitted by the transmitting node as a recessive bit, contains a dominant bit. If this is the case, at least one other node has received the frame correctly. If not, an Acknowledge Error has occured and the transmitter will start in the next bit-time an Error Frame transmission.
Error Detection
•
•
•
•
Fault Confinement
To distinguish between temporary and permanent failures, every CAN controller has two error counters: REC (Receive Error Counter) and TEC (Transmit Error Counter). The counters are incremented upon detected errors and respectively are decremented upon correct transmissions or receptions. Depending on the counter values, the state of the node changes: the initial state of the CAN controller is Error Active, meaning that the controller can send Error Active flags. The controller changes to the Error Passive state if there is an accumulation of
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errors. If the CAN controller fails or if there is an extreme accumulation of errors, there is a state transition to Bus Off. Figure 136. Line Error Mode
Init
TEC > 127 or REC > 127
ERROR ACTIVE
128 occurences of 11 consecutive recessive bits or CAN controller reset
ERROR PASSIVE
TEC < 127 and REC < 127
BUS OFF
TEC > 255
An error active unit takes part in bus communication and sends an active error frame when the CAN controller detects an error. An error passive unit cannot send an active error frame. It takes part in bus communication, but when an error is detected, a passive error frame is sent. Also, after a transmission, an error passive unit waits before initiating further transmission. A bus off unit is not allowed to have any influence on the bus. For fault confinment, two errors counters (TEC and REC) are implemented. These counters are accessible via the CAN_ECR register. The state of the CAN controller is automatically updated according to these counter values. If the CAN controller is in Error Active state, then the ERRA bit is set in the CAN_SR register. The corresponding interrupt is pending while the interrupt is not masked in the CAN_IMR register. If the CAN controller is in Error Passive Mode, then the ERRP bit is set in the CAN_SR register and an interrupt remains pending while the ERRP bit is set in the CAN_IMR register. If the CAN is in Bus-off Mode, then the BOFF bit is set in the CAN_SR register. As for ERRP and ERRA, an interrupt is pending while the BOFF bit is set in the CAN_IMR register. When one of the error counters values exceeds 96, an increased error rate is indicated to the controller through the WARN bit in CAN_SR register, but the node remains error active. The corresponding interrupt is pending while the interrupt is set in the CAN_IMR register. Refer to the Bosch CAN specification v2.0 for details on fault confinment. Overload The overload frame is provided to request a delay of the next data or remote frame by the receiver node (“Request overload frame”) or to signal certain error conditions (“Reactive overload frame”) related to the intermission field respectively. Reactive overload frames are transmitted after detection of the following error conditions: • • Detection of a dominant bit during the first two bits of the intermission field Detection of a dominant bit in the last bit of EOF by a receiver, or detection of a dominant bit by a receiver or a transmitter at the last bit of an error or overload frame delimiter
The CAN controller can generate a request overload frame automatically after each message sent to one of the CAN controller mailboxes. This feature is enabled by setting the OVL bit in the CAN_MR register.
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Reactive overload frames are automatically handled by the CAN controller even if the OVL bit in the CAN_MR register is not set. An overload flag is generated in the same way as an error flag, but error counters do not increment.
Low-power mode
In Low-power Mode, the CAN controller cannot send or receive messages. All mailboxes are inactive. In Low-power Mode, the SLEEP signal in the CAN_SR register is set; otherwise, the WAKEUP signal in the CAN_SR register is set. These two fields are exclusive except after a CAN controller reset (WAKEUP and SLEEP are stuck at 0 after a reset). After power-up reset, the Lowpower Mode is disabled and the WAKEUP bit is set in the CAN_SR register only after detection of 11 consecutive recessive bits on the bus.
Enabling Low-power Mode
A software application can enable Low-power Mode by setting the LPM bit in the CAN_MR global register. The CAN controller enters Low-power Mode once all pending transmit messages are sent. When the CAN controller enters Low-power Mode, the SLEEP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while SLEEP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. The WAKEUP signal is automatically cleared once SLEEP is set. Reception is disabled while the SLEEP signal is set to one in the CAN_SR register. It is important to note that those messages with higher priority than the last message transmitted can be received between the LPM command and entry in Low-power Mode. Once in Low-power Mode, the CAN controller clock can be switched off by programming the chip’s Power Management Controller (PMC). The CAN controller drains only the static current. Error counters are disabled while the SLEEP signal is set to one. Thus, to enter Low-power Mode, the software application must: – – Set LPM field in the CAN_MR register Wait for SLEEP signal rising
Now the CAN Controller clock can be disabled. This is done by programming the Power Management Controller (PMC). Figure 137. Enabling Low-power Mode
Arbitration lost
CAN BUS LPEN= 1 LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR) MRDY (CAN_MSR1) MRDY (CAN_MSR3)
Mailbox 1
Mailbox 3
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Disabling Low-power Mode
The CAN controller can be awake after detecting a CAN bus activity. Bus activity detection is done by an external module that may be embedded in the chip. When it is notified of a CAN bus activity, the software application disables Low-power Mode by programming the CAN controller. To disable Low-power Mode, the software application must: – – Enable the CAN Controller clock. This is done by programming the Power Management Controller (PMC). Clear LPM field in the CAN_MR register
The CAN controller synchronizes itself with the bus activity by checking for eleven consecutive “recessive” bits. Once synchronized, the WAKEUP signal in the CAN_SR register is set. Depending on the corresponding mask in the CAN_IMR register, an interrupt is generated while WAKEUP is set. The SLEEP signal in the CAN_SR register is automatically cleared once WAKEUP is set. WAKEUP signal is automatically cleared once SLEEP is set. If no message is being sent on the bus, then the CAN controller is able to send a message eleven bit times after disabling Low-power Mode. If there is bus activity when Low-power mode is disabled, the CAN controller is synchronized with the bus activity in the next interframe. The previous message is lost (see Figure 138).
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Figure 138. Disabling Low-power Mode
Bus Activity Detected Message x Interframe synchronization
CAN BUS LPM (CAN_MR) SLEEP (CAN_SR) WAKEUP (CAN_SR)
Message lost
MRDY (CAN_MSRx)
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Functional Description
CAN Controller Initialization
After power-up reset, the CAN controller is disabled. The CAN controller clock must be activated by the Power Management Controller (PMC) and the CAN controller interrupt line must be enabled by the interrupt controller (AIC). The CAN controller must be initialized with the CAN network parameters. The CAN_BR register defines the sampling point in the bit time period. CAN_BR must be set before the CAN controller is enabled by setting the CANEN field in the CAN_MR register. The CAN controller is enabled by setting the CANEN flag in the CAN_MR register. At this stage, the internal CAN controller state machine is reset, error counters are reset to 0, error flags are reset to 0. Once the CAN controller is enabled, bus synchronization is done automatically by scanning eleven recessive bits. The WAKEUP bit in the CAN_SR register is automatically set to 1 when the CAN controller is synchronized (WAKEUP and SLEEP are stuck at 0 after a reset). The CAN controller can start listening to the network in Autobaud Mode. In this case, the error counters are locked and a mailbox is configured in Receive Mode. By scanning error flags, the CAN_BR register values synchronized with the network. Once no error has been detected, the application disables the Autobaud Mode, clearing the ABM field in the CAN_MR register. Figure 139. Possible Initialization Procedure
Enable CAN Controller Clock (PMC) Enable CAN Controller Interrupt Line (AIC)
Configure a Mailbox in Reception Mode
Change CAN_BR value (ABM == 1 and CANEN == 1)
Errors ? (CAN_SR or CAN_MSRx)
Yes
No ABM = 0 and CANEN = 0
CANEN = 1 (ABM == 0)
End of Initialization
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CAN Controller Interrupt Handling
There are two different types of interrupts. One type of interrupt is a message-object related interrupt, the other is a system interrupt that handles errors or system-related interrupt sources. All interrupt sources can be masked by writing the corresponding field in the CAN_IDR register. They can be unmasked by writing to the CAN_IER register. After a power-up reset, all interrupt sources are disabled (masked). The current mask status can be checked by reading the CAN_IMR register. The CAN_SR register gives all interrupt source states. The following events may initiate one of the two interrupts: • Message object interrupt – Data registers in the mailbox object are available to the application. In Receive Mode, a new message was received. In Transmit Mode, a message was transmitted successfully. A sent transmission was aborted. Bus-off interrupt: The CAN module enters the bus-off state. Error-passive interrupt: The CAN module enters Error Passive Mode. Error-active Mode: The CAN module is neither in Error Passive Mode nor in Busoff mode. Warn Limit interrupt: The CAN module is in Error-active Mode, but at least one of its error counter value exceeds 96. Wake-up interrupt: This interrupt is generated after a wake-up and a bus synchronization. Sleep interrupt: This interrupt is generated after a Low-power Mode enable once all pending messages in transmission have been sent. Internal timer counter overflow interrupt: This interrupt is generated when the internal timer rolls over. Timestamp interrupt: This interrupt is generated after the reception or the transmission of a start of frame or an end of frame. The value of the internal counter is copied in the CAN_TIMESTP register.
– • – – – – – – – –
System interrupts
All interrupts are cleared by clearing the interrupt source except for the internal timer counter overflow interrupt and the timestamp interrupt. These interrupts are cleared by reading the CAN_SR register.
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CAN Controller Message Handling
Receive Handling Two modes are available to configure a mailbox to receive messages. In Receive Mode, the first message received is stored in the mailbox data register. In R eceive with Overwrite Mode, the last message received is stored in the mailbox. A mailbox is in Receive Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance Mask must be set before the Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. Message data are stored in the mailbox data register until the software application notifies that data processing has ended. This is done by asking for a new transfer command, setting the MTCR flag in the CAN_MCRx register. This automatically clears the MRDY signal. The MMI flag in the CAN_MSRx register notifies the software that a message has been lost by the mailbox. This flag is set when messages are received while MRDY is set in the CAN_MSRx register. This flag is cleared by reading the CAN_MSRs register. A receive mailbox prevents from overwriting the first message by new ones while MRDY flag is set in the CAN_MSRx register. See Figure 140. Figure 140. Receive Mailbox
Message ID = CAN_MIDx
Simple Receive Mailbox
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx)
Message 1
Message 2 lost
Message 3
(CAN_MDLx CAN_MDHx) MTCR (CAN_MCRx)
Message 1
Message 3
Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx
Note:
In the case of ARM architecture, CAN_MSRx, CAN_MDLx, CAN_MDHx can be read using an optimized ldm assembler instruction.
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Receive with Overwrite Mailbox
A mailbox is in Receive with Overwrite Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Receive Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first message is received. When the first message has been accepted by the mailbox, the MRDY flag is set. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt is masked depending on the mailbox flag in the CAN_IMR global register. If a new message is received while the MRDY flag is set, this new message is stored in the mailbox data register, overwriting the previous message. The MMI flag in the CAN_MSRx register notifies the software that a message has been dropped by the mailbox. This flag is cleared when reading the CAN_MSRx register. The CAN controller may store a new message in the CAN data registers while the application reads them. To check that CAN_MDHx and CAN_MDLx do not belong to different messages, the application must check the MMI field in the CAN_MSRx register before and after reading CAN_MDHx and CAN_MDLx. If the MMI flag is set again after the data registers have been read, the software application has to re-read CAN_MDHx and CAN_MDLx (see Figure 141).
Figure 141. Receive with Overwrite Mailbox
Message ID = CAN_MIDx
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) (CAN_MDLx CAN_MDHx) MTCR (CAN_MCRx)
Message 1
Message 2
Message 3
Message 4
Message 1
Message 2
Message 3
Message 4
Reading CAN_MSRx Reading CAN_MDHx & CAN_MDLx Writing CAN_MCRx
Chaining Mailboxes
Several mailboxes may be used to receive a buffer split into several messages with the same ID. In this case, the mailbox with the lowest number is serviced first. The field PRIOR in the CAN_MMRx register has no effect. If Mailbox 0 and Mailbox 5 accept messages with the same ID, the first message is received by Mailbox 0 and the second message is received by Mailbox 5. Mailbox 0 must be configured in Receive Mode (i.e., the first message received is considered) and Mailbox 5 must be configured in Receive with Overwrite Mode. Mailbox 0 cannot be configured in Receive with Overwrite Mode; otherwise, all messages are accepted by this mailbox and Mailbox 5 is never serviced. If several mailboxes are chained to receive a buffer split into several messages, all mailboxes except the last one (with the highest number) must be configured in Receive Mode. The first message received is handled by the first mailbox, the second one is refused by the first mailbox and accepted by the second mailbox, the last message is accepted by the last mailbox and refused by previous ones (see Figure 142).
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Figure 142. Chaining Three Mailboxes to Receive a Buffer Split into Three Messages
Buffer split in 3 messages
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz)
Message s1
Message s2
Message s3
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR
If the number of mailboxes is not sufficient (the MMI flag of the last mailbox raises), the user must read each data received on the last mailbox in order to retrieve all the messages of the buffer split (see Figure 143). Figure 143. Chaining Three Mailboxes to Receive a Buffer Split into Four Messages
Buffer split in 4 messages
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MRDY (CAN_MSRy) MMI (CAN_MSRy) MRDY (CAN_MSRz) MMI (CAN_MSRz)
Message s1
Message s2
Message s3
Message s4
Reading CAN_MSRx, CAN_MSRy and CAN_MSRz Reading CAN_MDH & CAN_MDL for mailboxes x, y and z Writing MBx MBy MBz in CAN_TCR
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Transmission Handling
A mailbox is in Transmit Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance mask must be set before Receive Mode is enabled. After Transmit Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first command is sent. When the MRDY flag is set, the software application can prepare a message to be sent by writing to the CAN_MDx registers. The message is sent once the software asks for a transfer command setting the MTCR bit and the message data length in the CAN_MCRx register. The MRDY flag remains at zero as long as the message has not been sent or aborted. It is important to note that no access to the mailbox data register is allowed while the MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked depending on the mailbox flag in the CAN_IMR global register. It is also possible to send a remote frame setting the MRTR bit instead of setting the MDLC field. The answer to the remote frame is handled by another reception mailbox. In this case, the device acts as a consumer but with the help of two mailboxes. It is possible to handle the remote frame emission and the answer reception using only one mailbox configured in Consumer Mode. Refer to the section “Remote Frame Handling” on page 497. Several messages can try to win the bus arbitration in the same time. The message with the highest priority is sent first. Several transfer request commands can be generated in the same time by setting MBx bits in the CAN_MTCR register. The priority is set in the PRIOR field of the CAN_MMRx register. Priority 0 is the highest priority, priority 15 is the lowest priority. Thus it is possible to use a part of the message ID to set the PRIOR field. If two mailboxes have the same priority, the message of the mailbox with the lowest number is sent first. Thus if mailbox 0 and mailbox 5 have the same priority and have a message to send at the same time, then the message of the mailbox 0 is sent first. Setting the MACR bit in the CAN_MCRx register aborts the transmission. Transmission for several mailboxes can be aborted by writing MBx fields in the CAN_MACR register. If the message is being sent when the abort command is set, then the application is notified by the MRDY bit set and not the MABT in the CAN_MSRx register. Otherwise, if the message has not been sent, then the MRDY and the MABT are set in the CAN_MSR register. When the bus arbitration is lost by a mailbox message, the CAN controller tries to win the next bus arbitration with the same message if this one still has the highest priority. Messages to be sent are re-tried automatically until they win the bus arbitration. This feature can be disabled by setting the bit DRPT in the CAN_MR register. In this case if the message was not sent the first time it was transmitted to the CAN transceiver, it is automatically aborted. The MABT flag is set in the CAN_MSRx register until the next transfer command. Figure 144 shows three MBx message attempts being made (MRDY of MBx set to 0). The first MBx message is sent, the second is aborted and the last one is trying to be aborted but too late bacause it has already been transmitted to the CAN transceiver.
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Figure 144. Transmitting Messages
CAN BUS MRDY (CAN_MSRx) MABT (CAN_MSRx) MTCR (CAN_MCRx) MACR (CAN_MCRx) Reading CAN_MSRx Writing CAN_MDHx & CANMDLx Abort MBx message Try to Abort MBx message MBx message MBx message
Remote Frame Handling
Producer/consumer model is an efficient means of handling broadcasted messages. The push model allows a producer to broadcast messages; the pull model allows a customer to ask for messages. Figure 145. Producer / Consumer Model
Producer
Request
PUSH MODEL
CAN Data Frame
Consumer
Indication(s)
PULL MODEL
Producer
Indications CAN Remote Frame
Consumer
Request(s)
Response
CAN Data Frame Confirmation(s)
In Pull Mode, a consumer transmits a remote frame to the producer. When the producer receives a remote frame, it sends the answer accepted by one or many consumers. Using transmit and receive mailboxes, a consumer must dedicate two mailboxes, one in Transmit Mode to send remote frames, and at least one in Receive Mode to capture the producer’s answer. The same structure is applicable to a producer: one reception mailbox is required to get the remote frame and one transmit mailbox to answer.
497
6042A–ATARM–23-Dec-04
Mailboxes can be configured in Producer or Consumer Mode. A lonely mailbox can handle the remote frame and the answer. With sixteen mailboxes, the CAN controller can handle sixteen independent producers/consumers.
Producer Configuration
A mailbox is in Producer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Producer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically set until the first transfer command. The software application prepares data to be sent by writing to the CAN_MDHx and the CAN_MDLx register then by setting the MTCR register in the CAN_MCRx register. Data is sent after the reception of a remote frame as soon as it wins the bus arbitration. The MRDY flag remains at zero as long as the message has not been sent or aborted. No access to the mailbox data register can be done while MRDY flag is cleared. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register. If a remote frame is received while no data are ready to be sent (signal MRDY set in the CAN_MSRx register), then the MMI signal is set in the CAN_MSRx register. This bit is cleared by reading the CAN_MSRx register. The MRTR field in the CAN_MSRx register has no meaning. This field is used only when using Receive and Receive with Overwrite modes. After a remote frame has been received, the mailbox functions like a transmit mailbox. The message with the highest priority is sent first. The transmitted message is aborted by setting the MACR field in the MAC_MCR register. Please refer to the section “Transmission Handling” on page 496.
Figure 146. Producer Handling
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) Reading CAN_MSRx Remote Frame Message 1 Remote Frame Remote Frame Message 2
(CAN_MDLx CAN_MDHx)
Message 1
Message 2
Consumer Configuration
A mailbox is in Consumer Mode once the MOT field in the CAN_MMRx register has been configured. Message ID and Message Acceptance masks must be set before Receive Mode is enabled. After Consumer Mode is enabled, the MRDY flag in the CAN_MSR register is automatically cleared until the first transfer request command. The software application sends a remote frame by setting the MTCR bit in the CAN_MCRx register or the MBx bit in the global CAN_TCR register. The application is notified of the answer by the MRDY flag set in the CAN_MSRx register. The application can read the data contents in the CAN_MDHx and CAN_MDLx registers. An interrupt is pending for the mailbox while the MRDY flag is set. This interrupt can be masked according to the mailbox flag in the CAN_IMR global register.
498
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The MRTR field in the CAN_MCRx register has no effect. This field is used only when using Transmit Mode. After a remote frame has been sent, the consumer mailbox functions as a reception mailbox. The first message received is stored in the mailbox data registers. If other messages intended for this mailbox have been sent while the MRDY flag is set in the CAN_MSRx register, they will be lost. The application is notified by reading the MMI field in the CAN_MSRx register. The read operation automatically clears the MMI flag. If several messages are answered by the Producer, the CAN controller may have one mailbox in consumer configuration, zero or several mailboxes in Receive Mode and one mailbox in Receive with Overwrite Mode. In this case, the consumer mailbox must have a lower number than the Receive with Overwrite mailbox (e.g., MBX0 and MBX3). The transfer command can be triggered for all mailboxes at the same time by setting several MBx fields in the CAN_TCR register. Figure 147. Consumer Handling
CAN BUS MRDY (CAN_MSRx) MMI (CAN_MSRx) MTCR (CAN_MCRx) Remote Frame Message x Remote Frame Message y
(CAN_MDLx CAN_MDHx)
Message x
Message y
499
6042A–ATARM–23-Dec-04
CAN Controller Timing Modes
Using the free running 16-bit internal timer, the CAN controller can be set in one of the two following timing modes: • • Timestamping Mode: The value of the internal timer is captured at each Start Of Frame or each End Of Frame. Time Triggered Mode: The mailbox transfer operation is triggered when the internal timer reaches the mailbox trigger.
Timestamping Mode is enabled by clearing the TTM bit in the CAN_MR register. Time Triggered Mode is enabled by setting the TTM bit in the CAN_MR register. Timestamping Mode Each mailbox has its own timestamp value. Each time a message is sent or received by a mailbox, the 16-bit value MTIMESTAMP of the CAN_TIMESTP register is transfered to the LSB bits of the CAN_MSRx register. The value read in the CAN_MSRx register correponds to the internal timer value at the Start Of Frame or the End Of Frame of the message handled by the mailbox.
Figure 148. Mailbox Timestamp
Start of Frame End of Frame
CAN BUS CAN_TIM
Message 1
Message 2
TEOF (CAN_MR) TIMESTAMP (CAN_TSTP) MTIMESTAMP (CAN_MSRx) MTIMESTAMP (CAN_MSRy) Timestamp 1 Timestamp 2
Timestamp 1 Timestamp 2
Time Triggered Mode
In Time Triggered Mode, basic cycles can be split into several time windows. A basic cycle starts with a reference message. Each time a window is defined from the reference message, a transmit operation should occur within a pre-defined time window. A mailbox must not win the arbitration in a previous time window, and it must not be retried if the arbitration is lost in the time window.
Figure 149. Time Triggered Operations
Time Cycle Reference Message Reference Message
Time Windows for Messages Global Time
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Time Trigger Mode is enabled by setting the TTM field in the CAN_MR register. In Time Triggered Mode, as in Timestamp Mode, the CAN_TIMESTP field captures the values of the internal counter, but the MTIMESTAMP fields in the CAN_MSRx registers are not active and are read at 0.
Synchronization by a Reference Message
In Time Triggered Mode, the internal timer counter is automatically reset when a new message is received in the last mailbox. This reset occurs after the reception of the End Of Frame on the rising edge of the MRDY signal in the CAN_MSRx register. This allows synchronization of the internal timer counter with the reception of a reference message and the start a new time window. A time mark is defined for each mailbox. It is defined in the 16-bit MTIMEMARK field of the CAN_MMRx register. At each internal timer clock cycle, the value of the CAN_TIM is compared with e ach ma ilbox time mark. Whe n the internal timer counter reaches the MTIMEMARK value, an internal timer event for the mailbox is generated for the mailbox. In Time Triggered Mode, transmit operations are delayed until the internal timer event for the mailbox. The application prepares a message to be sent by setting the MTCR in the CAN_MCRx register. The message is not sent until the CAN_TIM value is less than the MTIMEMARK value defined in the CAN_MMRx register. If the transmit operation is failed, i.e., the message loses the bus arbitration and the next transmit attempt is delayed until the next internal time trigger event. This prevents overlapping the next time window, but the message is still pending and is retried in the next time window when CAN_TIM value equals the MTIMEMARK value. It is also possible to prevent a retry by setting the DRPT field in the CAN_MR register.
Transmitting within a Time Window
Freezing the Internal Timer Counter
The internal counter can be frozen by setting TIMFRZ in the CAN_MR register. This prevents an unexpected roll-over when the counter reaches FFFFh. When this occurs, it automatically freezes until a new reset is issued, either due to a message received in the last mailbox or any other reset counter operations. The TOVF bit in the CAN_SR register is set when the counter is frozen. The TOVF bit in the CAN_SR register is cleared by reading the CAN_SR register. Depending on the corresponding interrupt mask in the CAN_IMR register, an interrupt is generated when TOVF is set.
501
6042A–ATARM–23-Dec-04
Figure 150. Time Triggered Operations
End of Frame Message x Arbitration Lost Message y Arbitration Win
CAN BUS
Reference Message
Message y Internal Counter Reset
CAN_TIM Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MRDY (CAN_MSRx) MTIMEMARKy == CAN_TIM MTIMEMARKx == CAN_TIM
Timer Event y MRDY (CAN_MSRy)
Time Window Basic Cycle
End of Frame
Message x Arbitration Win Message x
CAN BUS CAN_TIM
Reference Message
Internal Counter Reset
Cleared by software MRDY (CAN_MSRlast_mailbox_number) Timer Event x MRDY (CAN_MSRx) Time Window Basic Cycle MTIMEMARKx == CAN_TIM
502
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Controller Area Network (CAN) Controller User Interface
Table 63. C ontroller Area Network (CAN) Register Mapping
Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x0100 - 0x01FC 0x0200 0x0204 0x0208 0x020C 0x0210 0x0214 0x0218 0x021C 0x0220 0x0224 0x0228 0x022C 0x0230 0x0234 0x0238 0x023C ... Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Baudrate Register Timer Register Timestamp Register Error Counter Register Transfer Command Register Abort Command Register Reserved Mailbox 0 Mode Register Mailbox 0 Acceptance Mask Register Mailbox 0 ID Register Mailbox 0 Family ID Register Mailbox 0 Status Register Mailbox 0 Data Low Register Mailbox 0 Data High Register Mailbox 0 Control Register Mailbox 1 Mode Register Mailbox 1 Acceptance Mask Register Mailbox 1 ID register Mailbox 1 Family ID Register Mailbox 1 Status Register Mailbox 1 Data Low Register Mailbox 1 Data High Register Mailbox 1 Control Register ... Name CAN_MR CAN_IER CAN_IDR CAN_IMR CAN_SR CAN_BR CAN_TIM CAN_TIMESTP CAN_ECR CAN_TCR CAN_ACR – CAN_MMR0 CAN_MAM0 CAN_MID0 CAN_MFID0 CAN_MSR0 CAN_MDL0 CAN_MDH0 CAN_MCR0 CAN_MMR1 CAN_MAM1 CAN_MID1 CAN_MFID1 CAN_MSR1 CAN_MDL1 CAN_MDH1 CAN_MCR1 ... Access Read-Write Write-only Write-only Read-only Read-only Read/Write Read-only Read-only Read-only Write-only Write-only – Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read/Write Write-only Read/Write Read/Write Read/Write Read-only Read-only Read/Write Read/Write Write-only ... Reset State 0x0 0x0 0x0 0x0 0x0 0x0 0x0 – 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 -
503
6042A–ATARM–23-Dec-04
CAN Mode Register
Name: Access Type:
31 – 23 – 15 – 7 DRPT
CAN_MR Read/Write
30 – 22 – 14 – 6 TIMFRZ 29 – 21 – 13 – 5 TTM 28 – 20 – 12 – 4 TEOF 27 – 19 – 11 – 3 OVL 26 25 24
18 – 10 – 2 ABM
17 – 9 – 1 LPM
16 – 8 – 0 CANEN
• CANEN: CAN Controller Enable 0 = The CAN Controller is disabled. 1 = The CAN Controller is enabled. • LPM: Disable/Enable Low Power Mode w Power Mode. 1 = Enable Low Power M CAN controller enters Low Power Mode once all pending messages have been transmitted. • ABM: Disable/Enable Autobaud/Listen mode 0 = Disable Autobaud/listen mode. 1 = Enable Autobaud/listen mode. • OVL: Disable/Enable Overload Frame 0 = No overload frame is generated. 1 = An overload frame is generated after each successful reception for mailboxes configured in Receive with/without overwrite Mode, Producer and Consumer. • TEOF: Timestamp messages at each end of Frame 0 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each Start Of Frame. 1 = The value of CAN_TIM is captured in the CAN_TIMESTP register at each End Of Frame. • TTM: Disable/Enable Time Triggered Mode 0 = Time Triggered Mode is disabled. 1 = Time Triggered Mode is enabled. • TIMFRZ: Enable Timer Freeze 0 = The internal timer continues to be incremented after it reached 0xFFFF. 1 = The internal timer stops incrementing after reaching 0xFFFF. It is restarted after a timer reset. See “Freezing the Internal Timer Counter” on page 501. • DRPT: Disable Repeat 0 = When a transmit mailbox loses the bus arbitration, the transfer request remains pending.
504
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1 = When a transmit mailbox lose the bus arbitration, the transfer request is automatically aborted. It automatically raises the MABT and MRDT flags in the corresponding CAN_MSRx.
505
6042A–ATARM–23-Dec-04
CAN Interrupt Enable Register
Name: Access Type:
31 – 23 TSTP 15 MB15 7 MB7
CAN_IER Write-only
30 – 22 TOVF 14 MB14 6 MB6 29 – 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0
• MBx: Mailbox x Interrupt Enable 0 = No effect. 1 = Enable Mailbox x interrupt. • ERRA: Error Active mode Interrupt Enable 0 = No effect. 1 = Enable ERRA interrupt. • WARN: Warning Limit Interrupt Enable 0 = No effect. 1 = Enable WARN interrupt. • ERRP: Error Passive mode Interrupt Enable 0 = No effect. 1 = Enable ERRP interrupt. • BOFF: Bus-off mode Interrupt Enable 0 = No effect. 1 = Enable BOFF interrupt. • SLEEP: Sleep Interrupt Enable 0 = No effect. 1 = Enable SLEEP interrupt. • WAKEUP: Wakeup Interrupt Enable 0 = No effect. 1 = Enable SLEEP interrupt. • TOVF: Timer Overflow Interrupt Enable 0 = No effect. 1 = Enable TOVF interrupt. • TSTP: TimeStamp Interrupt Enable 0 = No effect. 506
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1 = Enable TSTP interrupt. • CERR: CRC Error Interrupt Enable 0 = No effect. 1 = Enable CRC Error interrupt. • SERR: Stuffing Error Interrupt Enable 0 = No effect. 1 = Enable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Enable 0 = No effect. 1 = Enable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Enable 0 = No effect. 1 = Enable Form Error interrupt. • BERR: Bit Error Interrupt Enable 0 = No effect. 1 = Enable Bit Error interrupt.
507
6042A–ATARM–23-Dec-04
CAN Interrupt Disable Register
Name: Access Type:
31 – 23 TSTP 15 MB15 7 MB7
CAN_IDR Write-only
30 – 22 TOVF 14 MB14 6 MB6 29 – 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0
• MBx: Mailbox x Interrupt Disable 0 = No effect. 1 = Disable Mailbox x interrupt. • ERRA: Error Active Mode Interrupt Disable 0 = No effect. 1 = Disable ERRA interrupt. • WARN: Warning Limit Interrupt Disable 0 = No effect. 1 = Disable WARN interrupt. • ERRP: Error Passive mode Interrupt Disable 0 = No effect. 1 = Disable ERRP interrupt. • BOFF: Bus-off mode Interrupt Disable 0 = No effect. 1 = Disable BOFF interrupt. • SLEEP: Sleep Interrupt Disable 0 = No effect. 1 = Disable SLEEP interrupt. • WAKEUP: Wakeup Interrupt Disable 0 = No effect. 1 = Disable WAKEUP interrupt. • TOVF: Timer Overflow Interrupt 0 = No effect. 1 = Disable TOVF interrupt. • TSTP: TimeStamp Interrupt Disable 0 = No effect. 508
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1 = Disable TSTP interrupt.
• CERR: CRC Error Interrupt Disable 0 = No effect. 1 = Disable CRC Error interrupt. • SERR: Stuffing Error Interrupt Disable 0 = No effect. 1 = Disable Stuffing Error interrupt. • AERR: Acknowledgment Error Interrupt Disable 0 = No effect. 1 = Disable Acknowledgment Error interrupt. • FERR: Form Error Interrupt Disable 0 = No effect. 1 = Disable Form Error interrupt. • BERR: Bit Error Interrupt Disable 0 = No effect. 1 = Disable Bit Error interrupt.
509
6042A–ATARM–23-Dec-04
CAN Interrupt Mask Register
Name: Access Type:
31 – 23 TSTP 15 MB15 7 MB7
CAN_IMR Read-only
30 – 22 TOVF 14 MB14 6 MB6 29 – 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0
• MBx: Mailbox x Interrupt Mask 0 = Mailbox x interrupt is disabled. 1 = Mailbox x interrupt is enabled. • ERRA: Error Active mode Interrupt Mask 0 = ERRA interrupt is disabled.. 1 = ERRA interrupt is enabled. • WARN: Warning Limit Interrupt Mask 0 = Warning Limit interrupt is disabled. 1 = Warning Limit interrupt is enabled. • ERRP: Error Passive Mode Interrupt Mask 0 = ERRP interrupt is disabled. 1 = ERRP interrupt is enabled. • BOFF: Bus-off Mode Interrupt Mask 0 = BOFF interrupt is disabled. 1 = BOFF interrupt is enabled. • SLEEP: Sleep Interrupt Mask 0 = SLEEP interrupt is disabled. 1 = SLEEP interrupt is enabled. • WAKEUP: Wakeup Interrupt Mask 0 = WAKEUP interrupt is disabled. 1 = WAKEUP interrupt is enabled. • TOVF: Timer Overflow Interrupt Mask 0 = TOVF interrupt is disabled. 1 = TOVF interrupt is enabled. • TSTP: Timestamp Interrupt Mask 0 = TSTP interrupt is disabled. 510
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1 = TSTP interrupt is enabled.
• CERR: CRC Error Interrupt Mask 0 = CRC Error interrupt is disabled. 1 = CRC Error interrupt is enabled. • SERR: Stuffing Error Interrupt Mask 0 = Bit Stuffing Error interrupt is disabled. 1 = Bit Stuffing Error interrupt is enabled. • AERR: Acknowledgment Error Interrupt Mask 0 = Acknowledgment Error interrupt is disabled. 1 = Acknowledgment Error interrupt is enabled. • FERR: Form Error Interrupt Mask 0 = Form Error interrupt is disabled. 1 = Form Error interrupt is enabled. • BERR: Bit Error Interrupt Mask 0 = Bit Error interrupt is disabled. 1 = Bit Error interrupt is enabled.
511
6042A–ATARM–23-Dec-04
CAN Status Register
Name: Access Type:
31 OVLSY 23 TSTP 15 MB15 7 MB7
CAN_SR Read-only
30 TBSY 22 TOVF 14 MB14 6 MB6 29 RBSY 21 WAKEUP 13 MB13 5 MB5 28 BERR 20 SLEEP 12 MB12 4 MB4 27 FERR 19 BOFF 11 MB11 3 MB3 26 AERR 18 ERRP 10 MB10 2 MB2 25 SERR 17 WARN 9 MB9 1 MB1 24 CERR 16 ERRA 8 MB8 0 MB0
• MBx: Mailbox x Event 0 = No event occured on Mailbox x. 1 = An event occured on Mailbox x. An event corresponds to MRDY, MABT fields in the CAN_MSRx register. • ERRA: Error Active mode 0 = CAN controller is not in error active mode 1 = CAN controller is in error active mode This flag is set depending on TEC and REC counter values. It is set when node is neither in error passive mode nor in bus off mode. This flag is automatically reset when above condition is not satisfied. • WARN: Warning Limit 0 = CAN controller Warning Limit is not reached. 1 = CAN controller Warning Limit is reached. This flag is set depending on TEC and REC counters values. It is set when at least one of the counters values exceeds 96. This flag is automatically reset when above condition is not satisfied. • ERRP: Error Passive mode 0 = CAN controller is not in error passive mode 1 = CAN controller is in error passive mode This flag is set depending on TEC and REC counters values. A node is error passive when TEC counter is greater or equal to 128 (decimal) or when the REC counter is greater or equal to 128 (decimal) and less than 256. This flag is automatically reset when above condition is not satisfied. • BOFF: Bus Off mode 0 = CAN controller is not in bus-off mode 1 = CAN controller is in bus-off mode This flag is set depending on TEC counter value. A node is bus off when TEC counter is greater or equal to 256 (decimal). 512
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This flag is automatically reset when above condition is not satisfied.
• SLEEP: CAN controller in Low power Mode. 0 = CAN controller is not in low power mode. 1 = CAN controller is in low power mode. This flag is automatically reset when Low power mode is disabled • WAKEUP: CAN controller is not in Low power Mode. 0 = CAN controller is in low power mode. 1 = CAN controller is not in low power mode. When a WAKEUP event occurs, the CAN controller is synchronized with the bus activity. Messages can be transmitted or received. The CAN controller clock must be available when a WAKEUP event occurs. This flag is automatically reset when the CAN Controller enters Low Power mode. • TOVF: Timer Overflow 0 = The timer has not rolled-over FFFFh to 0000h. 1 = The timer rolls-over FFFFh to 0000h. This flag is automatically cleared reading CAN_SR register. • TSTP Timestamp 0 = No bus activity has been detected. 1 = A start of frame or an end of frame has been detected (according to the TEOF field in the CAN_MR register). This flag is automatically cleared by reading the CAN_SR register. • CERR: Mailbox CRC Error 0 = No CRC error occurred during a previous transfer. 1 = A CRC error occurred during a previous transfer. A CRC error has been detected during last reception. This flag is automatically cleared reading CAN_SR register. • SERR: Mailbox Stuffing Error 0 = No stuffing error occurred during a previous transfer. 1 = A stuffing error occurred during a previous transfer. A form error results from the detection of more than five consecutive bit with the same polarity. This flag is automatically cleared by reading CAN_SR register. • AERR: Acknowledgment Error 0 = No acknowledgment error occured during a previous transfer. 1 = An acknowledgment error occured during a previous transfer. An acknowledgment error is detected when no detection of the dominant bit in the acknowledge slot occurs. This flag is automatically cleared reading CAN_SR register. • FERR: Form Error
513
6042A–ATARM–23-Dec-04
0 = No form error occurred during a previous transfer 1 = A form error occurred during a previous transfer A form error results from violations on one or more of the fixed form of the following bit fields: – – – – – CRC delimiter ACK delimiter End of frame Error delimiter Overload delimiter
This flag is automatically cleared by reading CAN_SR register. • BERR: Bit Error 0 = No bit error occurred during a previous transfer. 1 = A bit error occurred during a previous transfer. A bit error is set when the bit value monitored on the line is different from the bit value sent. This flag is automatically cleared by reading CAN_SR register. • RBSY: Receiver busy 0 = CAN receiver is not receiving a frame. 1 = CAN receiver is receiving a frame. Receiver busy. This status bit is set by hardware while CAN receiver is acquiring or monitoring a frame (remote, data, overload or error frame). It is automatically reset when CAN is not receiving. • TBSY: Transmitter busy 0 = CAN transmitter is not transmitting a frame. 1 = CAN transmitter is transmitting a frame. Transmitter busy. This status bit is set by hardware while CAN transmitter is generating a frame (remote, data, overload or error frame). It is automatically reset when CAN is not transmitting. • OVLSY: Overload busy 0 = CAN transmitter is not transmitting an overload frame. 1 = CAN transmitter is transmitting a overload frame. It is automatically reset when the bus is not transmitting an overload frame.
514
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CAN Baudrate Register
Name: Access Type:
31 – 23 – 15 – 7 –
CAN_BR Read/Write
30 – 22 29 – 21 28 – 20 27 – 19 BRP 11 – 3 – 26 – 18 25 – 17 24 SMP 16
14 – 6
13 SYNC 5 PHASE1
12
10
9 PROPAG 1 PHASE2
8
4
2
0
Any modification on one of the fields of the CANBR register must be done while CAN module is disabled. • PHASE2: Phase 2 segment This phase is used to compensate the edge phase error. t PHS2 = t CSC × ( PHASE2 + 1 ) • PHASE1: Phase 1 segment This phase is used to compensate for edge phase error. t PHS1 = t CSC × ( PHASE1 + 1 ) • PROPAG: Programming time segment This part of the bit time is used to compensate for the physical delay times within the network. t PRS = t CSC × ( PROPAG + 1 ) • SYNC: Re-synchronization jump width To compensate for phase shifts between clock oscillators of different controlers on bus. The controller must re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the maximum of clock cycles a bit period may be shortened or lenghtened by re-synchronization. t SJW = t CSC × ( SYNC + 1 ) • BRP: Baudrate Prescaler. This field allows user to program the period of the CAN system clock to determine the individual bit timing. Tcsc = (BRP + 1) / MCK • SMP: Sampling Mode 0 = The incoming bit stream is sampled once at sample point. 1 = The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point. SMP Sampling Mode is automatically disabled if BRP = 0.
515
6042A–ATARM–23-Dec-04
CAN Timer Register
Name: Access Type:
31 – 23 – 15 TIMER15 7 TIMER7
CAN_TIM Read-only
30 – 22 – 14 TIMER14 6 TIMER6 29 – 21 – 13 TIMER13 5 TIMER5 28 – 20 – 12 TIMER12 4 TIMER4 27 – 19 – 11 TIMER11 3 TIMER3 26 – 18 – 10 TIMER10 2 TIMER2 25 – 17 – 9 TIMER9 1 TIMER1 24 – 16 – 8 TIMER8 0 TIMER0
• TIMERx: Timer This field represents the internal CAN controller 16-bit timer value.
516
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CAN Timestamp Register
Name: Access Type:
31 – 23 – 15
MTIMESTAMP 15
CAN_TIMESTP Read-only
30 – 22 – 14
MTIMESTAMP 14
29 – 21 – 13
MTIMESTAMP 13
28 – 20 – 12
MTIMESTAMP 12
27 – 19 – 11
MTIMESTAMP 11
26 – 18 – 10
MTIMESTAMP 10
25 – 17 – 9
MTIMESTAMP 9
24 – 16 – 8
MTIMESTAMP 8
7
MTIMESTAMP 7
6
MTIMESTAMP 6
5
MTIMESTAMP 5
4
MTIMESTAMP 4
3
MTIMESTAMP 3
2
MTIMESTAMP 2
1
MTIMESTAMP 1
0
MTIMESTAMP 0
• MTIMESTAMPx: Timestamp This field represents the internal CAN controller 16-bit timer value. If the TEOF bit is cleared in the CAN_MR register, the internal Timer Counter value is captured in the MTIMESTAMP field at each start of frame. Else the value is captured at each end of frame. When the value is captured, the TSTP flag is set in the CAN_SR register. If the TSTP mask in the CAN_IMR register is set, an interrupt is generated while TSTP flag is set in the CAN_SR register. This flag is cleared by reading the CAN_SR register.
517
6042A–ATARM–23-Dec-04
CAN Error Counter Register
Name: Access Type:
31 – 23
CAN_ECR Read-only
30 – 22 29 – 21 28 – 20 TEC 27 – 19 26 – 18 25 – 17 24 – 16
15 – 7
14 – 6
13 – 5
12 – 4 REC
11 – 3
10 – 2
9 – 1
8 – 0
• REC: Receive Error Counter When a receiver detects an error, REC will be increased by one, except when the detected error is a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG. When a receiver detects a dominant bit as the first bit after sending an ERROR FLAG, REC is increased by 8. When a receiver detects a BIT ERROR while sending an ACTIVE ERROR FLAG, REC is increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits, each receiver increases its REC by 8. After succesful reception of a message, REC is decreased by 1 if it was between 1 and 127. If REC was 0, it stays 0, and if it was greater than 127, then it is set to a value between 119 and 127. • TEC: Transmit Error Counter When a tansmitter sends an ERROR FLAG, TEC is increased by 8 except when – – the transmitter is error passive and detects an ACKNOWLEDGMENT ERROR because of not detecting a dominant ACK and does not detect a dominant bit while sending its PASSIVE ERROR FLAG. the transmitter sends an ERROR FLAG because a STUFF ERROR occurred during arbitration and should have been receissive and has been sent as recessive but monitored as dominant.
When a transmitter detects a BIT ERROR while sending an ACTIVE ERROR FLAG or an OVERLOAD FLAG, the TEC will be increased by 8. Any node tolerates up to 7 consecutive dominant bits after sending an ACTIVE ERROR FLAG, PASSIVE ERROR FLAG or OVERLOAD FLAG. After detecting the 14th consecutive dominant bit (in case of an ACTIVE ERROR FLAG or an OVERLOAD FLAG) or after detecting the 8th consecutive dominant bit following a PASSIVE ERROR FLAG, and after each sequence of additional eight consecutive dominant bits every transmitter increases its TEC by 8. After a succesfull transmission the TEC is decreased by 1 unless it was already 0.
518
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CAN Transfer Command Register
Name: Access Type:
31 TIMRST 23 – 15 MB15 7 MB7
CAN_TCR Write-only
30 – 22 – 14 MB14 6 MB6 29 – 21 – 13 MB13 5 MB5 28 – 20 – 12 MB12 4 MB4 27 – 19 – 11 MB11 3 MB3 26 – 18 – 10 MB10 2 MB2 25 – 17 – 9 MB9 1 MB1 24 – 16 – 8 MB8 0 MB0
This register initializes several transfer requests at the same time. • MBx: Transfer Request for Mailbox x
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description It receives the next message. This triggers a new reception. Sends data prepared in the mailbox as soon as possible. Sends a remote frame. Sends data prepared in the mailbox after receiving a remote frame from a consumer.
This flag clears the MRDY and MABT flags in the correponding CAN_MSRx register. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn, starting with the mailbox with the highest priority. If several mailboxes have the same priority, then the mailbox with the lowest number is sent first (i.e., MB0 will be transfered before MB1). • TIMRST: Timer Reset Resets the internal timer counter. If the internal timer counter is frozen, this command automatically re-enables it. This command is useful in Time Triggered mode.
519
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CAN Abort Command Register
Name: Access Type:
31 – 23 – 15 MB15 7 MB7
CAN_ACR Write-only
30 – 22 – 14 MB14 6 MB6 29 – 21 – 13 MB13 5 MB5 28 – 20 – 12 MB12 4 MB4 27 – 19 – 11 MB11 3 MB3 26 – 18 – 10 MB10 2 MB2 25 – 17 – 9 MB9 1 MB1 24 – 16 – 8 MB8 0 MB0
This register initializes several abort requests at the same time. • MBx: Abort Request for Mailbox x
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Cancels transfer request if the message has not been transmitted to the CAN transceiver. Cancels the current transfer before the remote frame has been sent. Cancels the current transfer. The next remote frame is not serviced.
It is possible to set MACR field (in the CAN_MCRx register) for each mailbox.
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CAN Message Mode Register
Name: Access Type:
31 – 23 – 15 MTIMEMARK 15 7
MTIMEMARK7
CAN_MMRx Read/Write
30 – 22 – 14 MTIMEMARK 14 6
MTIMEMARK6
29 – 21 – 13 MTIMEMARK 13 5
MTIMEMARK5
28 – 20 – 12 MTIMEMARK 12 4
MTIMEMARK4
27 – 19
26
25 MOT
24
18 PRIOR
17
16
11 MTIMEMARK 11 3
MTIMEMARK3
10 MTIMEMARK 10 2
MTIMEMARK2
9
MTIMEMARK9
8
MTIMEMARK8
1
MTIMEMARK1
0
MTIMEMARK0
• MTIMEMARK: Mailbox Timemark This field is active in Time Triggered Mode. Transmit operations are allowed when the internal timer counter reaches the Mailbox Timemark. See “Transmitting within a Time Window” on page 501. In Timestamp Mode, MTIMEMARK is set to 0. • PRIOR: Mailbox Priority When several mailboxes try to transmit a message at the same time, the mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 is serviced before MBx 15 if they have the same priority). • MOT: Mailbox Object Type This field allows the user to define the type of the mailbox. All mailboxes are independently configurable. Five different types are possible for each mailbox:
MOT 0 0 0 0 0 1 0 1 0 Mailbox Object Type Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox. Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded. Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message. Transmit mailbox. Mailbox is configured for transmission. Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer. Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents. Reserved
0 1 1
1 0 0
1 0 1
1
1
X
521
6042A–ATARM–23-Dec-04
CAN Message Acceptance Mask Register
Name: Access Type:
31 – 23
CAN_MAMx Read/Write
30 – 22 29 MIDE 21 MIDvA 28 27 26 MIDvA 18 25 24
20
19
17 MIDvB
16
15
14
13
12 MIDvB
11
10
9
8
7
6
5
4 MIDvB
3
2
1
0
To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MAMx registers. • MIDvB: Complementary bits for identifier in extended frame mode Acceptance mask for corresponding field of the message IDvB register of the mailbox. • MIDvA: Identifier for standard frame mode Acceptance mask for corresponding field of the message IDvA register of the mailbox. • MIDE: Identifier Version 0= Compares IDvA from the received frame with the CAN_MIDx register masked with CAN_MAMx register. 1= Compares IDvA and IDvB from the received frame with the CAN_MIDx register masked with CAN_MAMx register.
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CAN Message ID Register
Name: Access Type:
31 – 23
CAN_MIDx Read/Write
30 – 22 29 MIDE 21 MIDvA 28 27 26 MIDvA 18 25 24
20
19
17 MIDvB
16
15
14
13
12 MIDvB
11
10
9
8
7
6
5
4 MIDvB
3
2
1
0
To prevent concurrent access with the internal CAN core, the application must disable the mailbox before writing to CAN_MIDx registers. • MIDvB: Complementary bits for identifier in extended frame mode If MIDE is cleared, MIDvB value is 0. • MIDE: Identifier Version This bit allows the user to define the version of messages processed by the mailbox. If set, mailbox is dealing with version 2.0 Part B messages; otherwise, mailbox is dealing with version 2.0 Part A messages. • MIDvA: Identifier for standard frame mode
523
6042A–ATARM–23-Dec-04
CAN Message Family ID Register
Name: Access Type:
31 – 23
CAN_MFIDx Read-only
30 – 22 29 – 21 28 27 26 MFID 18 25 24
20 MFID
19
17
16
15
14
13
12 MFID
11
10
9
8
7
6
5
4 MFID
3
2
1
0
• MFID: Family ID This field contains the concatenation of CAN_MIDx register bits masked by the CAN_MAMx register. This field is useful to speed up message ID decoding. The message acceptance procedure is described below. As an example:
CAN_MIDx = 0x305A4321 CAN_MAMx = 0x3FF0F0FF CAN_MFIDx = 0x000000A3
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CAN Message Status Register
Name: Access Type:
31 – 23 MRDY 15
MTIMESTAMP 15
CAN_MSRx Read only
30 – 22 MABT 14
MTIMESTAMP 14
29 – 21 – 13
MTIMESTAMP 13
28 – 20 MRTR 12
MTIMESTAMP 12
27 – 19
26 – 18 MDLC
25 – 17
24 MMI 16
11
MTIMESTAMP 11
10
MTIMESTAMP 10
9
MTIMESTAMP 9
8
MTIMESTAMP 8
7
MTIMESTAMP 7
6
MTIMESTAMP 6
5
MTIMESTAMP 5
4
MTIMESTAMP 4
3
MTIMESTAMP 3
2
MTIMESTAMP 2
1
MTIMESTAMP 1
0
MTIMESTAMP 0
These register fields are updated each time a message transfer is received or aborted. MMI is cleared reading the CAN_MSRx register. MRDY, MABT are cleared by writing MTCR or MACR in the CAN_MCRx register. Warning: MRTR and MDLC state depends partly on the mailbox object type. • MTIMESTAMP: Timer value This field is updated only when time-triggered operations are disabled (TTM cleared in CAN_MR register). If the TEOF field in the CAN_MR register is cleared, TIMESTAMP is the internal timer value at the start of frame of the last message received or sent by the mailbox. If the TEOF field in the CAN_MR register is set, TIMESTAMP is the internal timer value at the end of frame of the last message received or sent by the mailbox. In Time Triggered Mode, MTIMESTAMP is set to 0. • MDLC: Mailbox Data Length Code
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Length of the first mailbox message received Length of the last mailbox message received No action Length of the mailbox message received No action
• MRTR: Mailbox Remote Transmission Request
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description The first frame received has the RTR bit set. The last frame received has the RTR bit set. Reserved Reserved Reserved
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• MABT: Mailbox Message Abort An interrupt is triggered when MABT is set. 0 = Previous transfer is not aborted. 1 = Previous transfer has been aborted. This flag is cleared writing to CAN_MCRx register
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Reserved Reserved Previous transfer has been aborted since the last abort command (MACR set in the CAN_MCRx register). The remote frame transfer request has been aborted. The response to the remote frame transfer has been aborted since the last abort command (MACR set in the CAN_MCRx register).
• MRDY: Mailbox Ready An interrupt is triggered when MRDY is set. 0 = Mailbox data registers can not be read/written by the software application. CAN_MDx are locked by the CAN_MDx. 1 = Mailbox data registers can be read/written by the software application. This flag is cleared by writing to CAN_MCRx register.
Mailbox Object Type Receive Description At least one message has been received since the last mailbox transfer order. Data from the first frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. At least one frame has been received since the last mailbox transfer order. Data from the last frame received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. Mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1. At least one message has been received since the last mailbox transfer order. Data from the first message received can be read in the CAN_MDxx registers. After setting the MOT field in the CAN_MMR, MRDY is reset to 0. A remote frame has been received, mailbox data have been transmitted. After setting the MOT field in the CAN_MMR, MRDY is reset to 1.
Receive with overwrite
Transmit Consumer
Producer
• MMI: Mailbox Message Ignored 0 = No message has been ignored during the previous transfer 1 = At least one message has been ignored during the previous transfer
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Cleared by reading the CAN_MSRx register.
Mailbox Object Type Receive Description Set when at least two messages intended for the mailbox have been sent. The first one is available in the mailbox data register. Others have been ignored. A mailbox with a lower priority may have accepted the message. Set when at least two messages intended for the mailbox have been sent. The last one is available in the mailbox data register. Previous ones have been lost. Reserved A remote frame has been sent by the mailbox but several messages have been received. The first one is available in the mailbox data register. Others have been ignored. Another mailbox with a lower priority may have accepted the message. A remote frame has been received, but no data are available to be sent.
Receive with overwrite
Transmit Consumer
Producer
527
6042A–ATARM–23-Dec-04
CAN Message Data Low Register
Name: Access Type:
31
CAN_MDLx Read/Write
30 29 28 MDL 27 26 25 24
23
22
21
20 MDL
19
18
17
16
15
14
13
12 MDL
11
10
9
8
7
6
5
4 MDL
3
2
1
0
• MDL: Message Data Low Value When MRDY field is set in the CAN_MSRx register, the lower 32 bits of a received message can be read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDL value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set.
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CAN Message Data High Register
Name: Access Type:
31
CAN_MDHx Read/Write
30 29 28 MDH 27 26 25 24
23
22
21
20 MDH
19
18
17
16
15
14
13
12 MDH
11
10
9
8
7
6
5
4 MDH
3
2
1
0
• MDH: Message Data High Value When MRDY field is set in the CAN_MSRx register, the upper 32 bits of a received message are read or written by the software application. Otherwise, the MDH value is locked by the CAN controller to send/receive a new message. In Receive with overwrite, the CAN controller may modify MDH value while the software application reads MDH and MDL registers. To check that MDH and MDL do not belong to different messages, the application has to check the MMI field in the CAN_MSRx register. In this mode, the software application must re-read CAN_MDH and CAN_MDL, while the MMI bit in the CAN_MSRx register is set.
529
6042A–ATARM–23-Dec-04
CAN Message Control Register
Name: Access Type:
31 – 23 MTCR 15 – 7 –
CAN_MCRx Write-only
30 – 22 MACR 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 MRTR 12 – 4 – 27 – 19 26 – 18 MDLC 11 – 3 – 10 – 2 – 9 – 1 – 8 – 0 – 25 – 17 24 – 16
• MDLC: Mailbox Data Length Code
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action. No action. Length of the mailbox message. No action. Length of the mailbox message to be sent after the remote frame reception.
• MRTR: Mailbox Remote Transmission Request
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Set the RTR bit in the sent frame No action, the RTR bit in the sent frame is set automatically No action
Consumer situations can be handled automatically by setting the mailbox object type in Consumer. This requires only one mailbox. It can also be handled using two mailboxes, one in reception, the other in transmission. The MRTR and the MTCR bits must be set in the same time.
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• MACR: Abort Request for Mailbox x
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description No action No action Cancels transfer request if the message has not been transmitted to the CAN transceiver. Cancels the current transfer before the remote frame has been sent. Cancels the current transfer. The next remote frame will not be serviced.
It is possible to set MACR field for several mailboxes in the same time, setting several bits to the CAN_ACR register. • MTCR: Mailbox Transfer Command
Mailbox Object Type Receive Receive with overwrite Transmit Consumer Producer Description Allows the reception of the next message. Triggers a new reception. Sends data prepared in the mailbox as soon as possible. Sends a remote transmission frame. Sends data prepared in the mailbox after receiving a remote frame from a consumer.
This flag clears the MRDY and MABT flags in the CAN_MSRx register. When several mailboxes are requested to be transmitted simultaneously, they are transmitted in turn. The mailbox with the highest priority is serviced first. If several mailboxes have the same priority, the mailbox with the lowest number is serviced first (i.e., MBx0 will be serviced before MBx 15 if they have the same priority). It is possible to set MTCR for several mailboxes at the same time by writing to the CAN_TCR register.
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6042A–ATARM–23-Dec-04
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AT91SAM7A3 Electrical Characteristics
Absolute Maximum Ratings
Table 64. Absolute Maximum Ratings*
Operating Temperature (Industrial)..... -40° C to +85 ° C Storage Temperature ......................... -60°C to +150°C Voltage on Input Pins with Respect to Ground .........................-0.3V to +5.5V Maximum Operating Voltage (VDDCORE and VDDPLL) ................................. 1.95V Maximum Operating Voltage (VDDIO, VDDIN, VDDBU and VDDANA) ............. 3.6V Total DC Output Current on all I/O lines .......... 200 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
533
6042A–ATARM–23-Dec-04
DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C and for VDDIO between 3.0 and 3.6V. Table 65. D C Characteristics
Symbol VVDDCORE VVDDPLL VVDDIO VVDDBU VVDDANA VIL VIH VOL VOH ILEAK IPULLUP C IN Parameter DC Supply Core DC Supply PLL DC Supply I/Os and Flash DC Supply Backup I/O Lines DC Supply Analog Input Low-level Voltage Input High-level Voltage Output Low-level Voltage Output High-level Voltage Input Leakage Current Input Pull-up Current Input Capacitance 100-pin LQFP Package On V VDDCORE = 1.8V, MCK = 0 Hz, excluding POR All inputs driven TMS, TDI, TCK, NRST = 1 ISC Static Current On V VDDBU = 3.6V, Logic cells consumption, excluding POR and RCOSC cells All inputs driven FWKUP, WKUP0, WKUP1 = 0 IO Output Current PA0-PA31 PB0-PB29 TA = 25°C 30 IO = 2 m A IO = 2 m A Pullup resistors disabled (Typ: TA = 25°C, Max: TA = 85°C) 143 VDDIO - 0.4 20 321 200 600 14.1 200 µA TA = 85°C 350 2300 Conditions Min 1.65 1.65 3.0 3.0 3.0 -0.3 2.0 Typ Max 1.95 1.95 3.6 3.6 3.6 0.8 5.5 0.4 Units V V V V V V V V V nA µA pF
TA = 25°C
47
60 nA
TA = 85°C
576
784 2 mA
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Table 66. 1.8V Voltage Regulator Characteristics
Symbol VDDIN VDDOUT IVDDIN TSTART Parameter Supply Voltage Output Voltage After startup, no load Current Consumption During startup, no load Startup Time PSRR IO Maximum DC Output Current Cload = 2.2 µF, after VDDIN > 3.0V DC to 100 kHz VDDIN = 3.3V VDDIN = 2.7V 35 130 100 100 150 mA µS dB mA mA Conditions Min 2.7 1.65 Typ 3.3 1.8 70 Max 3.6 1.95 120 Units V V µA
535
6042A–ATARM–23-Dec-04
Power Consumption
• • • Typical power consumption of PLLs, Slow Clock and Main Oscillator. Power consumption of power supply in three different modes: Active, Ultra Low-power and Backup. Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock.
Power Consumption versus Modes
The values in Table 67 and Table 68 on page 537 are estimated values of the power consumption with operating conditions as follows: • • • • • • VDDIN= VDDIO= V DDBU= VDDANA = 3.3V VDDCORE = VDDPLL = 1.8V TA = 25° C MCK = 60 MHz USB Pads deactivated There is no consumption on the I/Os of the device
Figure 151. Measures Schematics
VDDBU AMP1
VDDANA
VDDIO
3.3V AMP2
VDDIN Voltage Regulator VDDOUT 1.8V
AMP3 VDDCORE
VDDPLL
These figures represent the power consumption estimated on the power supplies.
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Table 67. Power Consumption for different Modes(1)
Mode Active Conditions Flash is read. ARM Core clock is 60 MHz. Analog-to-Digital Converter activated. All peripheral clocks activated. onto AMP2 onto AMP3 Ultra low power Flash is in standby mode. ARM Core clock is 500 Hz. Analog-to-Digital Converter de-activated. All peripheral clocks de-activated. onto AMP2 onto AMP3 Device only VDDBU powered 6.5 onto AMP1 µA 79 76 mA Consumption Unit
113 35
µA
Backup
Table 68. Power Consumption by Peripheral in Active Mode
Peripheral PIO Controller USART ADC UDP PWM CAN TWI SPI MCI SSC Timer Counter Channels Consumption 0.5 1.1 0.7 1.2 0.4 1.3 0.2 1.0 1.5 1.3 0.2 mA Unit
537
6042A–ATARM–23-Dec-04
Power Consumption versus Master Clock Frequency in Active Mode
Figure 152 produces estimated values with operating conditions as follows: • • • • • • • • • • VDDIN= VDDIO= V DDBU= VDDANA = 3.3V VDDCORE = VDDPLL = 1.8V TA = 25° C MCK in the MHz range Flash is read Two analog-to-digital converters are activated USB pads deactivated All peripheral clocks activated PLL activated There is no consumption on the I/Os of the device
Figure 152 presents the power consumption estimated on the power supply. Figure 152. Power Consumption versus MCK Frequency in the MHz Range
Current Consumption at 3.3V
100000 78,638 Consumption (µa)
6 042A–ATARM–23-Dec-04
40,378 21,248 11,683 6,901 4,509 3,314 10000
1000 0.9375 1.875 3.75 7.5 Frequency (MHz) 15 30 60
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Power Consumption versus Master Clock Frequency in Ultra Low-power Mode
Figure 153 produces estimated values with operating conditions as follows: • • • • • • • • • VDDIN= VDDIO= V DDBU= VDDANA = 3.3V VDDCORE = VDDPLL = 1.8V TA = 25° C Flash is inactive MCK in the kHz range USB pads deactivated All peripheral clocks deactivated PLL deactivated There is no consumption on the I/Os of the device
Figure 153 presents the power consumption estimated on the power supply. Figure 153. Power Consumption versus MCK Frequency in Ultra Low-power Mode
Current Consumption at 3.3V
1000
112.5 0.5 1
113 2
114 4
116 8
120.1 16
128.1 32
144.3 100
Frequency (kHz)
Consumption (µa)
539
6042A–ATARM–23-Dec-04
Crystal Oscillator Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified.
RC Oscillator Characteristics
Table 69. R C Oscillator Characteristics
Symbol 1/(t CPRC) Parameter RC Oscillator Frequency Duty Cycle tST IOSC Startup Time Current Consumption VDDBU = 3V After Startup Time Conditions VDDBU = 3V Min 22 45 Typ 32 50 Max 42 55 75 2.5 Unit KHz % µs µA
Main Oscillators Characteristics
Table 70. Main Oscillator Characteristics
Symbol 1/(t CPMAIN) CL1, CL2 CL Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2 ) Equivalent Load Capacitance Duty Cycle tST Startup Time VDDPLL = 1.2 to 2V CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz Active mode @20 MHz Standby mode @2V Notes: 1. CS is the shunt capacitance 350 40 Conditions Min 3 Typ 16 25 12.5 50 60 14.5 1.4 1 550 1 Max 20 Unit MHz pF pF %
ms
IOSC
Current Consumption
µA µA
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XIN Clock Characteristics
Table 71. XIN Clock Electrical Characteristics
Symbol 1/(t CPXIN) tCPXIN tCHXIN tCLXIN CIN RIN Notes: Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pulldown Resistor (1) (1) 20.0 0.4 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN 0.6 x tCPXIN 25 500 pF kΩ Conditions Min Max 50.0 Units MHz ns
1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register. See “PMC Clock Generator Main Oscillator Register” on page 171.)
PLL Characteristics
Table 72. Phase Lock Loop Characteristics
Symbol FOUT Parameter Output Frequency Conditions Field OUT of CKGR_PLL is 00 Field OUT of CKGR_PLL is 10 FIN IPLL Input Frequency Current Consumption Active mode Standby mode Note: Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. Min 80 150 1 Typ Max 160 220 32 4 1 Unit MHz MHz MHz mA µA
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6042A–ATARM–23-Dec-04
USB Transceiver Characteristics
Electrical Characteristics
Table 73. Electrical Parameters
Symbol Input Levels VIL VIH VDI VCM CIN I REXT Output Levels VOL VOH VCRS Low Level Output High Level Output Output Signal Crossover Voltage Measured with RL of 1.425 kOhm tied to 3.6V Measured with RL of 14.25 kOhm tied to GND Measure conditions described in Figure 154 0.0 2.8 1.3 0.3 3.6 2.0 V V V Low Level High Level Differential Input Sensivity Differential Input Common Mode Range Transceiver capacitance Hi-Z State Data Line Leakage Recommended External USB Series Resistor Capacitance to ground on each line 0V < VIN < 3.3V In series with each USB pin with ±5% -10 27 |(D+) - (D-)| 2.0 0.2 0.8 2.5 9.18 +10 0.8 V V V V pF µA
Ω
Parameter
Conditions
Min
Typ
Max
Unit
Switching Characteristics
Table 74. In Low Speed
Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 400 pF CLOAD = 400 pF CLOAD = 400 pF Min 75 75 80 Typ Max 300 300 125 Unit ns ns %
Table 75. In Full Speed
Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 50 pF CLOAD = 50 pF Min 4 4 90 Typ Max 20 20 111.11 Unit ns ns %
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Figure 154. USB Data Signal Rise and Fall Times
Rise Time VCRS 10% Differential Data Lines tR (a) REXT=27 ohms Fosc = 6MHz/750kHz Buffer (b) Cload tF 90% 10% Fall Time
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Analog-to-Digital Converter Characteristics
Table 76. C hannel Conversion Time and ADC Clock
Parameter ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Throughput Rate ADC Clock = 5 MHz ADC Clock = 5 MHz Return from Idle Mode 600 2 384 Conditions Min Typ Max 5 20 Units MHz µs ns µs kSPS
Table 77. External Voltage Reference Input
Parameter ADVREF Input Voltage Range ADVREF Average Current On 13 samples with ADC Clock = 5 MHz Conditions Min 2.6 12 Max VVDDANA 250 Units V µA
Table 78. Analog Inputs
Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 1 12 14 Typ Max VADVREF µA pF Units
Table 79. Transfer Characteristics
Parameter Resolution Integral Non-linearity ADC Clock = 5 MHz Differential Non-linearity ADC Clock = 5 MHz Offset Error Gain Error ±2 ±2 ±2 LSB LSB LSB ±3 ±1 LSB LSB Conditions Min Typ 10 ±2 Max Units Bit LSB
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Applicable Conditions and Derating Data
These conditions and derating process apply to the following paragraphs: Clock Characteristics, Embedded Flash Characteristics and JTAG/ICE Timings.
Conditions and Timings Computation
The delays are given as typical values under the following conditions: • • • • • • VDDIO = 3.3V VDDCORE = 1.8V Ambient Temperature = 25°C Load Capacitance = 0 pF The output level change detection is (0.5 x VDDIO). The input level is 0.8V for a low-level detection and is 2.0V for a high-level detection.
The minimum and maximum values given in the AC characteristics tables of this datasheet take into account process variation and design. In order to obtain the timingfor other conditions, the following equation should be used:
t = δT ° × ⎛ ( δVDDCORE × t DATASHEET ) + ⎛ δVDDIO × ⎝ ⎝ where:
• • • • • •
( ∑C SIGNAL × δCSIGNAL)⎞ ⎞ ⎠⎠
δT° is the derating factor in temperature given in Figure 155 on page 546. δVDDCORE is the derating factor for the Core Power Supply given in Figure 156 on page 546.
tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. δVDDIO is the derating factor for the IO Power Supply given in Figure 157 on page 547. CSIGNAL is the capacitance load on the considered output pin(1). δCSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet.
1. The user must take into account the package capacitance load contribution (CIN) described in “DC Characteristics” on page 534, Table 65 on page 534.
The input delays are given as typical values.
Note:
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Temperature Derating Factor
Figure 155. Derating Curve for Different Operating Temperatures
1.2
1.1
Derating Factor
1
0.9
0.8 -40 -20 0 20 40 60 80
Operating Temperature (°C)
VDDCORE Voltage Derating Factor
Figure 156. Derating Curve for Different Core Supply Voltages
1.2 1.15 Derating Factor 1.1 1.05 1 0.95 0.9 1.65 1.7 1.75 1.8 1.85 1.9 1.95
Core Supply Voltage (V)
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VDDIO Voltage Derating Factor
Figure 157. Derating Curve for Different IO Supply Voltages
1.1
1.05
Derating Factor
1
0.95
0.9 3 3.1 3.2 3.3 3.4 3.5 3.6
I/O Supply Voltage (V)
Note:
The derating factor in this example is applicable only to timings related to output pins.
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Clocks Characteristics
These parameters are given in the following conditions: • • VDDCORE = 1.8V Ambient Temperature = 25°C
The temperature derating factor described in “Temperature Derating Factor” on page 546 and VDDCORE voltage derating factor described in “VDDCORE Voltage Derating Factor” on page 546 are both applicable to these characteristics.
Master Clock Characteristics
Table 80. Master Clock Waveform Parameters
Symbol
1/(t CPMCK)
Parameter
Master Clock Frequency
Conditions
Min
Max
81
Units
MHz
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AT91SAM7A3 AC Characteristics
Embedded Flash Characteristics
Table 81. D C Flash Characteristics
Symbol
TPU ISB
Parameter
Power-up delay Standby current
Conditions
Min
Max
30
Units
µs µA
@ 25°C onto VDDCORE = 1.8V onto VDDIO = 3.3V Random Read @ 40MHz onto VDDCORE = 1.8V onto VDDIO = 3.3V
10 20 3.0 0.8 400 5.5
mA
ICC
Active current Write onto VDDCORE = 1.8V onto VDDIO = 3.3V µA mA
The maximum operating frequency is given in Table 81 but is limited by the Embedded Flash access time when the processor is fetching code out of it. Table 82 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory. Table 82. Embedded Flash Wait States
FWS
0 1 2 3
Read Operations
1 cycle 2 cycles 3 cycles 4 cycles
Maximum Operating Frequency (MHz)
40 80 1/(tCPMCK) 1/(tCPMCK)
Table 83. AC Flash Characteristics
Parameter
Program Cycle Time per page including auto-erase Full Chip Erase 10 2 ms ms
Condition
per page including auto-erase
Min
Max
4
Units
ms
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JTAG/ICE Timings
ICE Interface Signals
Table 84 shows timings relative to operating condition limits defined in the section “Conditions and Timings Computation” on page 545.
Table 84. ICE Interface Timing Specification
Symbol
ICE 0 ICE 1 ICE 2 ICE 3 ICE 4 ICE 5
Parameter
TCK Low Half-period TCK High Half-period TCK Period TDI, TMS, Setup before TCK High TDI, TMS, Hold after TCK High TDO Hold Time
Conditions
Min
51 51 102 0 5
Max
Units
ns ns ns ns ns ns ns/pF 12 ns ns/pF
CTDO = 0 pF CTDO derating
3 0.034
ICE 6
TCK Low to TDO Valid
CTDO = 0 pF CTDO derating
0.034
Figure 158. ICE Interface Signals
ICE2 TCK ICE0 ICE1
TMS/TDI ICE3 ICE4
TDO ICE5 ICE6
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JTAG Interface Signals
The following table shows timings relative to operating condition limits defined in the section “Conditions and Timings Computation” on page 545.
Table 85. JTAG Interface Timing specification
Symbol
JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5
Parameter
TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time
Conditions
Min
6.5 5.5 12 0 4
Max
Units
ns ns ns ns ns ns ns/pF
CTDO = 0 pF CTDO derating
4 0.034 11 0.034 0 5
JTAG6 JTAG7 JTAG8 JTAG9
TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time
CTDO = 0 pF CTDO derating
ns ns/pF ns ns ns ns/pF
COUT = 0 pF COUT derating
7 0.032 16 0.032
JTAG10
TCK to Device Outputs Valid
COUT = 0 pF COUT derating
ns ns/pF
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Figure 159. JTAG Interface Signals
JTAG2 TCK JTAG JTAG1
0
TMS/TDI JTAG3 JTAG4
TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8
Device Outputs JTAG9 JTAG10
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AT91SAM7A3 Mechanical Characteristics
Thermal Considerations
Thermal Data
In Table 86, the device lifetime is estimated using the MIL-217 standard in the “moderately controlled” environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section “Junction Temperature” on page 554.) Note that the user must be extremely cautious with this MTBF calculation. It should be noted that the MIL-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 86. MTBF Versus Junction Temperature
Junction Temperature (TJ) (°C)
100 125 150 175
Estimated Lifetime (MTBF) (Year)
8 4 2 1
Table 87 summarizes the thermal resistance data depending on the package. Table 87. Thermal Resistance Data
Symbol
θJA θJC
Parameter
Junction-to-ambient thermal resistance Junction-to-case thermal resistance
Condition
Still Air
Package
LQFP100 LQFP100
Typ
38.3
Unit
°C/W
8.7
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Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following: 1. T J = T A + ( P D × θ JA ) 2. T J = T A + ( P D × ( θ HEATSINK + θ JC ) )
where: • • • θ JA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 87 on page 553. θ JC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 87 on page 553. θ HEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
• •
PD = device power consumption (W) estimated from data provided in the section “Power Consumption” on page 536. TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C.
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Package Drawings
Figure 160. 100-lead LQFP Package Drawing
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Table 88. 100-lead LQFP Package Dimensions
Millimeter Symbol
A A1 A2 D D1 E E1 R2 R1
Θ Θ1 Θ2 Θ3
Inch Max
1.60
Min
Nom
Min
Nom
Max
0.63
0.05 1.35 1.40 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.08 0.08 0° 0° 11 ° 11 ° 0.09 0.45 0.60 1.00 REF 0.20 0.17 0.20 0.50 BSC 12.00 12.00 12° 12° 3.5°
0.15 1.45
0.002 0.053 0.055 0.630 BSC 0.551 BSC 0.630 BSC 0.551 BSC
0.006 0.057
0.20
0.003 0.003
0.008
7° 13° 13° 0.20 0.75
0° 0° 11° 11° 0.004 0.018
3.5° 12° 12°
7° 13° 13° 0.008
c L L1 S b e D2 E2
0.024 0.039 REF
0.030
0.008 0.27 0.007 0.008 0.020 BSC 0.472 0.472 Tolerances of form and position 0.011
aaa bbb ccc ddd
0.20 0.20 0.08 0.08
0.008 0.008 0.003 0.003
Table 89. D evice and 100-lead LQFP Package Maximum Weight
800 mg
Table 90. 100-lead LQFP Package Characteristics
Moisture Sensitivity Level 3
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Soldering Profile
Table 91 gives the recommended soldering profile from J-STD-20. Table 91. Soldering Profile
Convection or IR/Convection
Average Ramp-up Rate (183° C to Peak) Preheat Temperature 125° C ±25 ° C Temperature Maintained Above 183° C Time within 5° C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° C to Peak Temperature 3° C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0° C or 235 +5/-0° C 6° C/sec. 6 min. max 60 sec. 215 to 219° C or 235 +5/-0° C 10° C/sec.
VPR
10° C/sec.
Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235° C, not 220° C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 92. Table 92. R ecommended Package Reflow Conditions (1, 2, 3)
Parameter
Convection VPR IR/Convection
Temperature
235 +5/-0° C 235 +5/-0° C 235 +5/-0° C
When certain small thin packages are used on boards without larger packages, these small packages may be classified at 220°C instead of 235°C.
Notes: 1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220° C (unless 235 ° C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability.
A maximum of three reflow passes is allowed per component.
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AT91SAM7A3 Ordering Information
Table 93. Ordering Information
Ordering Code
AT91SAM7A3-AJ
Package
LQFP 100
Temperature Operating Range
Industrial (-40 ° C to 85° C)
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Document Details
Title Literature Number AT91SAM7A3 6042
Revision History
Version A 23-Dec-2004
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Table of Contents
Features............................................................................................................... 1 Description .......................................................................................................... 2 Block Diagram..................................................................................................... 3 Signal Description ............................................................................................. 4 Package and Pinout............................................................................................ 7 100-lead LQFP Mechanical Overview.............................................................. 7 Pinout ............................................................................................................... 7 Power Considerations........................................................................................ 8 Power Supplies ................................................................................................ 8 Voltage Regulator ............................................................................................ 8 Typical Powering Schematics .......................................................................... 9 I/O Lines Considerations ................................................................................. 10 JTAG Port Pins .............................................................................................. 10 Test Pin .......................................................................................................... 10 Reset Pin........................................................................................................ 10 PIO Controller A and B Lines ......................................................................... 10 Shutdown Logic Pins...................................................................................... 10 I/O Line Drive Levels...................................................................................... 10 Processor and Architecture............................................................................. 11 ARM7TDMI Processor ................................................................................... 11 Debug and Test Features .............................................................................. 11 Memory Controller.......................................................................................... 11 Peripheral Data Controller.............................................................................. 12 Memory .............................................................................................................. 13 Embedded Memories ..................................................................................... 13 Memory Mapping ........................................................................................... 13 Embedded Flash ............................................................................................ 14 System Controller............................................................................................. 15 System Controller Mapping ............................................................................ 16 Reset Controller ............................................................................................. 17 Clock Generator ............................................................................................. 17 Power Management Controller ...................................................................... 18 Advanced Interrupt Controller ........................................................................ 18 Debug Unit ..................................................................................................... 19 Period Interval Timer...................................................................................... 19 Watchdog Timer............................................................................................. 19 Real-time Timer.............................................................................................. 19 Shutdown Controller....................................................................................... 19 PIO Controllers A and B................................................................................. 19 Peripherals ........................................................................................................ 21 Peripheral Mapping ........................................................................................ 21 Peripheral Multiplexing on PIO Lines ............................................................. 22 PIO Controller A Multiplexing ......................................................................... 23 PIO Controller B Multiplexing ......................................................................... 24 Peripheral Identifiers ........................................................................................ 25 Serial Peripheral Interface.............................................................................. 26
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Two-wire Interface.......................................................................................... USART ........................................................................................................... Serial Synchronous Controller ....................................................................... Timer Counter ................................................................................................ PWM Controller .............................................................................................. USB Device Port ............................................................................................ Multimedia Card Interface .............................................................................. CAN Controller ............................................................................................... Analog-to-Digital Converter............................................................................ 26 26 26 27 27 27 28 28 28
ARM7TDMI Processor Overview .................................................................. 31
Overview............................................................................................................ ARM7TDMI Processor ...................................................................................... Instruction Type.............................................................................................. Data Type....................................................................................................... ARM7TDMI Operating Mode.......................................................................... ARM7TDMI Registers .................................................................................... ARM Instruction Set Overview ....................................................................... Thumb Instruction Set Overview .................................................................... 31 32 32 32 32 32 34 35
AT91SAM7A3 Debug and Test Features ..................................................... 37
Overview............................................................................................................ Block Diagram................................................................................................... Application Examples ...................................................................................... Debug Environment ....................................................................................... Test Environment ............................................................................................. Debug and Test Pin Description ..................................................................... Functional Description..................................................................................... Test Pin .......................................................................................................... Embedded In-circuit Emulator ........................................................................ Debug Unit ..................................................................................................... IEEE 1149.1 JTAG Boundary Scan ............................................................... ID Code Register............................................................................................ 37 37 38 38 39 39 40 40 40 40 40 47
Reset Controller (RSTC) ............................................................................... 49
Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... NRST Manager .............................................................................................. Reset States................................................................................................... Reset State Priorities ..................................................................................... Reset Controller Status Register.................................................................... Reset Controller (RSTC) User Interface.......................................................... Reset Controller Control Register .................................................................. Reset Controller Status Register.................................................................... 49 49 50 50 51 56 56 58 59 60
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Reset Controller Mode Register..................................................................... 61
Real-time Timer (RTT) ................................................................................... 63
Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Real-time Timer (RTT) User Interface ............................................................. Real-time Timer Mode Register ..................................................................... Real-time Timer Alarm Register..................................................................... Real-time Timer Value Register ..................................................................... Real-time Timer Status Register .................................................................... 63 63 64 66 67 68 69 70
Periodic Interval Timer (PIT)......................................................................... 71
Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Periodic Interval Timer (PIT) User Interface ................................................... Periodic Interval Timer Mode Register ........................................................... Periodic Interval Timer Status Register.......................................................... Periodic Interval Timer Value Register........................................................... Periodic Interval Timer Image Register .......................................................... 71 71 72 74 75 76 77 78
Watchdog Timer (WDT) ................................................................................. 79
Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Watchdog Timer (WDT) User Interface ........................................................... Watchdog Timer Control Register .................................................................. Watchdog Timer Mode Register .................................................................... Watchdog Timer Status Register ................................................................... 79 79 80 82 83 84 85
Shutdown Controller (SHDWC) .................................................................... 87
Description ........................................................................................................ Block Diagram................................................................................................... I/O Lines Description........................................................................................ Product Dependencies..................................................................................... Power Management ....................................................................................... Functional Description..................................................................................... Shutdown Controller (SHDWC) User Interface .............................................. Shutdown Control Register ............................................................................ Shutdown Mode Register............................................................................... Shutdown Status Register.............................................................................. 87 87 88 88 88 88 89 90 91 92
Memory Controller......................................................................................... 93
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Overview............................................................................................................ 93 Block Diagram................................................................................................... 93 Functional Description..................................................................................... 94 Bus Arbiter ..................................................................................................... 94 Address Decoder ........................................................................................... 94 Remap Command .......................................................................................... 95 Abort Status ................................................................................................... 96 Memory Protection Unit.................................................................................. 96 Embedded Flash Controller ........................................................................... 97 Misalignment Detector ................................................................................... 97 Memory Controller (MC) User Interface .......................................................... 98 MC Remap Control Register .......................................................................... 99 MC Abort Status Register ............................................................................ 100 MC Abort Address Status Register .............................................................. 101 MC Protection Unit Area 0 to 15 Registers .................................................. 102 MC Protection Unit Peripheral...................................................................... 103 MC Protection Unit Enable Register ............................................................ 103
Embedded Flash Controller (EFC) ............................................................. 105
Description ...................................................................................................... Functional Description................................................................................... Embedded Flash Organization..................................................................... Read Operations .......................................................................................... Write Operations .......................................................................................... Flash Commands ......................................................................................... Embedded Flash Controller (EFC) User Interface ....................................... MC Flash Mode Register ............................................................................. MC Flash Command Register ...................................................................... MC Flash Status Register ............................................................................ 105 105 105 106 108 108 112 113 115 117
Peripheral Data Controller (PDC) ............................................................... 119
Overview.......................................................................................................... Block Diagram................................................................................................. Functional Description................................................................................... Configuration................................................................................................ Memory Pointers .......................................................................................... Transfer Counters ........................................................................................ Data Transfers ............................................................................................. Priority of PDC Transfer Requests ............................................................... Peripheral Data Controller (PDC) User Interface ......................................... PDC Receive Pointer Register..................................................................... PDC Receive Counter Register ................................................................... PDC Transmit Pointer Register .................................................................... PDC Transmit Counter Register .................................................................. PDC Receive Next Pointer Register ............................................................ 119 119 120 120 120 120 121 121 122 123 123 124 124 125
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PDC Receive Next Counter Register ........................................................... PDC Transmit Next Pointer Register ........................................................... PDC Transmit Next Counter Register .......................................................... PDC Transfer Control Register .................................................................... PDC Transfer Status Register......................................................................
125 126 126 127 128
Advanced Interrupt Controller (AIC) .......................................................... 129
Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ AIC Detailed Block Diagram .......................................................................... I/O Line Description........................................................................................ Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Functional Description................................................................................... Interrupt Source Control............................................................................... Interrupt Latencies ....................................................................................... Normal Interrupt ........................................................................................... Fast Interrupt................................................................................................ Protect Mode................................................................................................ Spurious Interrupt......................................................................................... General Interrupt Mask ................................................................................ Advanced Interrupt Controller (AIC) User Interface .................................... Base Address............................................................................................... AIC Source Mode Register .......................................................................... AIC Source Vector Register ......................................................................... AIC Interrupt Vector Register ....................................................................... AIC FIQ Vector Register ...................................................................................... AIC Interrupt Status Register ....................................................................... AIC Interrupt Pending Register .................................................................... AIC Interrupt Mask Register ......................................................................... AIC Core Interrupt Status Register .............................................................. AIC Interrupt Enable Command Register..................................................... AIC Interrupt Disable Command Register .................................................... AIC Interrupt Clear Command Register ....................................................... AIC Interrupt Set Command Register .......................................................... AIC End of Interrupt Command Register ..................................................... AIC Spurious Interrupt Vector Register ........................................................ AIC Debug Control Register......................................................................... AIC Fast Forcing Enable Register................................................................ AIC Fast Forcing Disable Register ............................................................... AIC Fast Forcing Status Register................................................................. 129 129 129 130 130 130 130 130 130 132 132 134 135 137 140 141 141 142 142 143 144 144 145 146 146 147 147 148 148 149 149 150 150 151 151 152 152
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Clock Generator........................................................................................... 153
Description ................................................................................................... Slow Clock RC Oscillator ............................................................................. Main Oscillator ............................................................................................. Divider and PLL Block .................................................................................. 153 153 153 155
Power Management Controller (PMC) ....................................................... 157
Description ................................................................................................... Master Clock Controller................................................................................ Processor Clock Controller .......................................................................... USB Clock Controller ................................................................................... Peripheral Clock Controller .......................................................................... Programmable Clock Output Controller ....................................................... Programming Sequence .............................................................................. Clock Switching Details ................................................................................ Power Management Controller (PMC) User Interface ................................ 157 157 157 158 158 158 159 162 165
Debug Unit (DBGU) ..................................................................................... 179
Overview.......................................................................................................... Block Diagram................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Source ........................................................................................... UART Operations............................................................................................ Baud Rate Generator ................................................................................... Receiver ....................................................................................................... Transmitter ................................................................................................... Peripheral Data Controller............................................................................ Test Modes .................................................................................................. Debug Communication Channel Support..................................................... Chip Identifier ............................................................................................... ICE Access Prevention ................................................................................ Debug Unit (DBGU) User Interface ............................................................... Debug Unit Control Register ........................................................................ Debug Unit Mode Register ........................................................................... Debug Unit Interrupt Enable Register .......................................................... Debug Unit Interrupt Disable Register ......................................................... Debug Unit Interrupt Mask Register ............................................................. Debug Unit Status Register.......................................................................... Debug Unit Receiver Holding Register ........................................................ Debug Unit Transmit Holding Register......................................................... Debug Unit Baud Rate Generator Register.................................................. Debug Unit Chip ID Register........................................................................ 179 180 181 181 181 181 181 181 182 184 185 185 186 187 187 188 189 190 191 192 193 194 196 197 197 198
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Debug Unit Chip ID Extension Register ....................................................... 200 Debug Unit Force NTRST Register.............................................................. 201
Parallel Input/Output Controller (PIO) ....................................................... 203
Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Product Dependencies................................................................................... Pin Multiplexing ............................................................................................ External Interrupt Lines ................................................................................ Power Management ..................................................................................... Interrupt Generation ..................................................................................... Functional Description................................................................................... Pull-up Resistor Control ............................................................................... I/O Line or Peripheral Function Selection .................................................... Peripheral A or B Selection .......................................................................... Output Control.............................................................................................. Synchronous Data Output............................................................................ Multi Drive Control (Open Drain) .................................................................. Output Line Timings ..................................................................................... Inputs ........................................................................................................... Input Glitch Filtering ..................................................................................... Input Change Interrupt ................................................................................. I/O Lines Programming Example .................................................................. Parallel Input/Output Controller (PIO) User Interface.................................. PIO Controller PIO Enable Register............................................................. PIO Controller PIO Disable Register............................................................ PIO Controller PIO Status Register.............................................................. PIO Controller Output Enable Register ........................................................ PIO Controller Output Disable Register ....................................................... PIO Controller Output Status Register ......................................................... PIO Controller Input Filter Enable Register .................................................. PIO Controller Input Filter Disable Register ................................................. PIO Controller Input Filter Status Register................................................... PIO Controller Set Output Data Register ..................................................... PIO Controller Clear Output Data Register .................................................. PIO Controller Output Data Status Register ................................................ PIO Controller Pin Data Status Register ...................................................... PIO Controller Interrupt Enable Register ..................................................... PIO Controller Interrupt Disable Register..................................................... PIO Controller Interrupt Mask Register ........................................................ PIO Controller Interrupt Status Register ...................................................... PIO Multi-driver Enable Register.................................................................. PIO Multi-driver Disable Register................................................................. PIO Multi-driver Status Register................................................................... PIO Pull Up Disable Register .......................................................................
viii
203 204 204 205 205 205 205 205 206 206 207 207 207 208 208 208 208 209 209 211 212 214 214 215 215 216 216 217 217 218 218 219 219 220 220 221 221 222 222 223 223 224
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PIO Pull Up Enable Register........................................................................ PIO Pull Up Status Register ......................................................................... PIO Peripheral A Select Register................................................................. PIO Peripheral B Select Register................................................................. PIO Peripheral A B Status Register ............................................................. PIO Output Write Enable Register ............................................................... PIO Output Write Disable Register .............................................................. PIO Output Write Status Register ................................................................ 224 225 225 226 226 227 227 229
Serial Peripheral Interface (SPI) ................................................................. 231
Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Signal Description ......................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Modes of Operation...................................................................................... Data Transfer ............................................................................................... Master Mode Operations.............................................................................. SPI Slave Mode ........................................................................................... Serial Peripheral Interface (SPI) User Interface .......................................... SPI Control Register .................................................................................... SPI Mode Register ....................................................................................... SPI Receive Data Register .......................................................................... SPI Transmit Data Register ......................................................................... SPI Status Register...................................................................................... SPI Interrupt Enable Register ...................................................................... SPI Interrupt Disable Register...................................................................... SPI Interrupt Mask Register ......................................................................... SPI Chip Select Register.............................................................................. 231 232 232 233 233 233 233 233 234 234 234 236 241 243 244 245 247 248 249 251 252 253 254
Two-wire Interface (TWI) ............................................................................. 257
Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Product Dependencies................................................................................... I/O Lines Description.................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Transfer Format ........................................................................................... Modes of Operation...................................................................................... 257 257 257 258 258 258 258 259 259 259
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Transmitting Data ......................................................................................... Read/Write Flowcharts................................................................................. Two-wire Interface (TWI) User Interface ...................................................... TWI Control Register.................................................................................... TWI Master Mode Register .......................................................................... TWI Internal Address Register ..................................................................... TWI Clock Waveform Generator Register.................................................... TWI Status Register ..................................................................................... TWI Interrupt Enable Register...................................................................... TWI Interrupt Disable Register..................................................................... TWI Interrupt Mask Register ........................................................................ TWI Receive Holding Register ..................................................................... TWI Transmit Holding Register ....................................................................
259 262 264 265 266 267 267 268 269 270 271 272 272
Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 273
Description ...................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ I/O Lines Description ..................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Baud Rate Generator ................................................................................... Receiver and Transmitter Control ................................................................ Synchronous and Asynchronous Modes...................................................... ISO7816 Mode ............................................................................................. IrDA Mode .................................................................................................... RS485 Mode ................................................................................................ Test Modes .................................................................................................. USART User Interface ................................................................................... USART Control Register .............................................................................. USART Mode Register................................................................................. USART Interrupt Enable Register ................................................................ USART Interrupt Disable Register ............................................................... USART Interrupt Mask Register................................................................... USART Channel Status Register ................................................................. USART Receive Holding Register ............................................................... USART Transmit Holding Register .............................................................. USART Baud Rate Generator Register ....................................................... USART Receiver Time-out Register ............................................................ USART Transmitter Timeguard Register ..................................................... USART FI DI RATIO Register ...................................................................... USART Number of Errors Register .............................................................. USART IrDA FILTER Register .....................................................................
x
273 274 275 275 276 276 276 276 277 277 281 281 291 293 297 298 300 301 303 306 307 308 309 311 311 312 313 314 315 316 316
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Synchronous Serial Controller (SSC)........................................................ 317
Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Pin Name List .................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Clock Management ...................................................................................... Clock Divider ................................................................................................ Transmitter Operations ................................................................................ Receiver Operations .................................................................................... Start.............................................................................................................. Frame Sync.................................................................................................. Data Format ................................................................................................. Loop Mode ................................................................................................... Interrupt........................................................................................................ SSC Application Examples ............................................................................ Synchronous Serial Controller (SSC) User Interface ................................. SSC Control Register................................................................................... SSC Clock Mode Register ........................................................................... SSC Receive Clock Mode Register ............................................................. SSC Receive Frame Mode Register ............................................................ SSC Transmit Clock Mode Register ............................................................ SSC Transmit Frame Mode Register ........................................................... SSC Receive Holding Register .................................................................... SSC Transmit Holding Register ................................................................... SSC Receive Synchronization Holding Register.......................................... SSC Transmit Synchronization Holding Register......................................... SSC Status Register .................................................................................... SSC Interrupt Enable Register..................................................................... SSC Interrupt Disable Register .................................................................... SSC Interrupt Mask Register ....................................................................... 317 317 318 319 319 319 319 319 319 320 321 323 324 324 326 326 328 328 330 332 333 334 335 337 339 341 344 344 345 345 346 349 350 351
Timer/Counter (TC)...................................................................................... 353
Overview.......................................................................................................... Block Diagram................................................................................................. Pin Name List .................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... 353 353 354 354 354 354 354 354
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TC Description ............................................................................................. Capture Operating Mode.............................................................................. Waveform Operating Mode .......................................................................... Timer/Counter (TC) User Interface ................................................................ Global Register Mapping ............................................................................. Channel Memory Mapping ........................................................................... TC Block Control Register............................................................................ TC Block Mode Register .............................................................................. TC Channel Control Register ....................................................................... TC Channel Mode Register: Capture Mode ................................................. TC Channel Mode Register: Waveform Mode ............................................. TC Counter Value Register .......................................................................... TC Register A............................................................................................... TC Register B............................................................................................... TC Register C .............................................................................................. TC Status Register ....................................................................................... TC Interrupt Enable Register ....................................................................... TC Interrupt Disable Register....................................................................... TC Interrupt Mask Register ..........................................................................
354 357 359 366 366 366 367 367 368 369 371 374 374 375 375 376 378 379 380
Pulse Width Modulation Controller (PWM) ............................................... 381
Overview.......................................................................................................... Block Diagram................................................................................................. I/O Lines Description...................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Functional Description................................................................................... PWM Clock Generator ................................................................................. PWM Channel .............................................................................................. PWM Controller Operations ......................................................................... Pulse Width Modulation Controller (PWM) User Interface.......................... PWM Mode Register .................................................................................... PWM Enable Register .................................................................................. PWM Disable Register ................................................................................. PWM Status Register................................................................................... PWM Interrupt Enable Register ................................................................... PWM Interrupt Disable Register................................................................... PWM Interrupt Mask Register ...................................................................... PWM Interrupt Status Register .................................................................... PWM Channel Mode Register...................................................................... PWM Channel Duty Cycle Register ............................................................. PWM Channel Period Register .................................................................... PWM Channel Counter Register .................................................................. PWM Channel Update Register ...................................................................
xii
381 381 382 382 382 382 382 383 383 384 387 388 389 390 390 391 392 392 393 393 394 395 395 397 397
AT91SAM7A3 Preliminary
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AT91SAM7A3 Preliminary
USB Device Port (UDP) ............................................................................... 399
Overview.......................................................................................................... Block Diagram................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Typical Connection......................................................................................... Functional Description................................................................................... USB V2.0 Full-speed Introduction ................................................................ Handling Transactions with USB V2.0 Device Peripheral............................ Controlling Device States............................................................................. USB Device Port (UDP) User Interface ......................................................... USB Frame Number Register ...................................................................... USB Global State Register........................................................................... USB Function Address Register .................................................................. USB Interrupt Enable Register..................................................................... USB Interrupt Disable Register .................................................................... USB Interrupt Mask Register ....................................................................... USB Interrupt Status Register ...................................................................... USB Interrupt Clear Register ....................................................................... USB Reset Endpoint Register ...................................................................... USB Endpoint Control and Status Register ................................................. USB FIFO Data Register.............................................................................. USB Transceiver Control Register ............................................................... 399 400 400 401 401 401 402 403 403 404 414 416 417 418 419 420 421 422 424 427 428 429 432 434
MultiMedia Card Interface (MCI) ................................................................. 435
Description ...................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Pin Name List ................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Bus Topology.................................................................................................. MultiMedia Card Operations .......................................................................... Command - Response Operation ................................................................ Data Transfer Operation .............................................................................. Read Operation ............................................................................................ Write Operation ............................................................................................ SD Card Operations........................................................................................ MultiMedia Card Interface (MCI) User Interface ........................................... MCI Control Register.................................................................................... MCI Mode Register ...................................................................................... 435 435 436 436 436 436 436 436 437 438 439 441 441 443 445 446 447 448
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MCI Data Timeout Register.......................................................................... MCI SD Card Register ................................................................................. MCI Argument Register................................................................................ MCI Command Register............................................................................... MCI SD Response Register ......................................................................... MCI SD Receive Data Register.................................................................... MCI SD Transmit Data Register................................................................... MCI Status Register ..................................................................................... MCI Interrupt Enable Register...................................................................... MCI Interrupt Disable Register..................................................................... MCI Interrupt Mask Register .......................................................................
449 450 450 451 453 454 454 455 458 459 460
Analog-to-digital Converter (ADC) ............................................................. 461
Overview.......................................................................................................... Block Diagram................................................................................................. Signal Description .......................................................................................... Product Dependencies................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Analog Inputs ............................................................................................... I/O Lines....................................................................................................... Timer Triggers .............................................................................................. Conversion Performances ............................................................................. Functional Description................................................................................... Analog-to-digital Conversion ........................................................................ Conversion Reference ................................................................................. Conversion Resolution ................................................................................. Conversion Results ...................................................................................... Conversion Triggers ..................................................................................... Sleep Mode and Conversion Sequencer ..................................................... ADC Timings ................................................................................................ Analog-to-digital Converter (ADC) User Interface ....................................... ADC Control Register................................................................................... ADC Mode Register ..................................................................................... ADC Channel Enable Register..................................................................... ADC Channel Disable Register .................................................................... ADC Channel Status Register...................................................................... ADC Status Register .................................................................................... ADC Last Converted Data Register ............................................................. ADC Interrupt Enable Register..................................................................... ADC Interrupt Disable Register .................................................................... ADC Interrupt Mask Register ....................................................................... ADC Channel Data Register ........................................................................ 461 461 462 462 462 462 462 462 462 462 463 463 463 463 463 465 466 466 467 468 469 471 471 472 473 474 475 475 476 476
Controller Area Network (CAN) .................................................................. 477
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AT91SAM7A3 Preliminary
Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ I/O Lines Description ..................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ CAN Controller Features................................................................................ CAN Protocol Overview ............................................................................... Mailbox Organization ................................................................................... Time Management Unit................................................................................ CAN 2.0 Standard Features ......................................................................... Low-power mode.......................................................................................... Functional Description................................................................................... CAN Controller Initialization ......................................................................... CAN Controller Interrupt Handling ............................................................... CAN Controller Message Handling .............................................................. CAN Controller Timing Modes ..................................................................... Controller Area Network (CAN) Controller User Interface ......................... CAN Mode Register ..................................................................................... CAN Interrupt Enable Register..................................................................... CAN Interrupt Disable Register .................................................................... CAN Interrupt Mask Register ....................................................................... CAN Status Register .................................................................................... CAN Baudrate Register................................................................................ CAN Timer Register ..................................................................................... CAN Timestamp Register ............................................................................ CAN Error Counter Register ........................................................................ CAN Transfer Command Register ............................................................... CAN Abort Command Register .................................................................... CAN Message Mode Register...................................................................... CAN Message Acceptance Mask Register .................................................. CAN Message ID Register ........................................................................... CAN Message Family ID Register ............................................................... CAN Message Status Register .................................................................... CAN Message Data Low Register ............................................................... CAN Message Data High Register............................................................... CAN Message Control Register ................................................................... 477 478 478 478 479 479 479 479 480 480 480 483 484 488 491 491 492 493 500 503 504 506 508 510 512 515 516 517 518 519 520 521 522 523 524 525 528 529 530
AT91SAM7A3 Electrical Characteristics ................................................... 533
Absolute Maximum Ratings........................................................................... DC Characteristics.......................................................................................... Power Consumption....................................................................................... Power Consumption versus Modes ............................................................. Power Consumption versus Master Clock Frequency in Active Mode......... 533 534 536 536 538
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Power Consumption versus Master Clock Frequency in Ultra Low-power Mode 539
Crystal Oscillator Characteristics ................................................................. RC Oscillator Characteristics ....................................................................... Main Oscillators Characteristics................................................................... XIN Clock Characteristics ............................................................................ PLL Characteristics ...................................................................................... USB Transceiver Characteristics .................................................................. Electrical Characteristics .............................................................................. Switching Characteristics ............................................................................. Analog-to-Digital Converter Characteristics................................................ Applicable Conditions and Derating Data .................................................... Conditions and Timings Computation .......................................................... Temperature Derating Factor ....................................................................... VDDCORE Voltage Derating Factor ............................................................ VDDIO Voltage Derating Factor................................................................... Clocks Characteristics ................................................................................... Master Clock Characteristics .......................................................................
540 540 540 541 541 542 542 542 544 545 545 546 546 547 548 548
AT91SAM7A3 AC Characteristics .............................................................. 549
Embedded Flash Characteristics .................................................................. JTAG/ICE Timings .......................................................................................... ICE Interface Signals ................................................................................... JTAG Interface Signals ................................................................................ 549 550 550 551
AT91SAM7A3 Mechanical Characteristics ................................................ 553
Thermal Considerations................................................................................. Thermal Data ............................................................................................... Junction Temperature .................................................................................. Package Drawings .......................................................................................... Soldering Profile ............................................................................................. 553 553 554 555 557
AT91SAM7A3 Ordering Information .......................................................... 558 Document Details ............................................................................................. i
Revision History ................................................................................................ i
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6 042A–ATARM–23-Dec-04
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6042A–ATARM–23-Dec-04
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