AT91SAM7S128

Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In-circuit Emulation, Debug Communication Channel Support 128 Kbytes of Internal High-speed Flash, Organized in 512 Pages of 256 Bytes – Single Cycle Access at Up to 30 MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms – 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit – Fast Flash Programming Interface for High Volume Production 32 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed Memory Controller (MC) – Embedded Flash Controller, Abort Status and Misalignment Detection Reset Controller (RSTC) – Based on Power-on Reset and Low-power Factory-calibrated Brown-out Detector – Provides External Reset Signal Shaping and Reset Source Status Clock Generator (CKGR) – Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL Power Management Controller (PMC) – Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode – Three Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) – 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle Mode Real-time Timer (RTT) – 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator One Parallel Input/Output Controller (PIOA) – Thirty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up resistor and Synchronous Output Eleven Peripheral DMA Controller (PDC) Channels One USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 328-byte Configurable Integrated FIFOs • • • • AT91 ARM® Thumb®-based Microcontrollers AT91SAM7S128 Preliminary • • • • • • • • • • 6116A–ATARM–15-Apr-05 • One Synchronous Serial Controller (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Two Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Manchester Encoder/Decoder – Full Modem Line Support on USART1 One Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects One Three-channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs Supported One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os IEEE 1149.1 JTAG Boundary Scan on All Digital Pins 5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each Power Supplies – Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components – 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brown-out Detector Fully Static Operation: Up to 55 MHz at 1.65V and 85° C Worst Case Conditions Available in a 64-lead LQFP Green Package • • • • • • • • • • • 1. Description Atmel’s AT91SAM7S128 is a member of a series of low pincount Flash microcontrollers based on the 32-bit ARM RISC processor. It features a 128 Kbyte high-speed Flash and a 32 Kbyte SRAM, a large set of peripherals, including a USB 2.0 device, and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality. The AT91SAM7S128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brown-out detector and a watchdog running off an integrated RC oscillator. The AT91SAM7S128 is a general-purpose microcontroller. Its integrated USB Device port makes it an ideal device for peripheral applications requiring connectivity to a PC or cellular phone. Its aggressive price point and high level of integration pushes its scope of use far into the cost-sensitive, high-volume consumer market. 2 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 2. Block Diagram Figure 2-1. AT91SAM7S128 Block Diagram TDI TDO TMS TCK JTAGSEL JTAG SCAN ICE ARM7TDMI Processor 1.8 V Voltage Regulator VDDIN GND VDDOUT VDDCORE TST FIQ System Controller AIC PIO IRQ0-IRQ1 Memory Controller Embedded Flash Controller Address Decoder Misalignment Detection VDDIO SRAM 32 Kbytes PCK0-PCK2 PLLRC XIN XOUT PLL OSC RCOSC PMC Abort Status VDDFLASH Flash 128 Kbytes ERASE VDDCORE BOD POR Reset Controller Peripheral Bridge PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN2 VDDCORE NRST Peripheral DMA Controller 11 Channels PIT WDT RTT DRXD DTXD PIO Fast Flash Programming Interface APB PDC FIFO Transceiver DBGU PDC USB Device DDM DDP PIOA RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 RI1 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADVREF PDC PWMC PDC USART0 PDC PDC SSC PDC USART1 Timer Counter PIO PDC PDC TC0 TC1 SPI PDC PDC TC2 TWI PWM0 PWM1 PWM2 PWM3 TF TK TD RD RK RF TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK ADC PIO 3 6116A–ATARM–15-Apr-05 3. Signal Description Table 3-1. Signal Name Signal Description List Function Power Type Active Level Comments VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL GND Voltage and ADC Regulator Power Supply Input Voltage Regulator Output Flash Power Supply I/O Lines Power Supply Core Power Supply PLL Ground Power Power Power Power Power Power Ground 3.0 to 3.6V 1.85V nominal 3.0V to 3.6V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V Clocks, Oscillators and PLLs XIN XOUT PLLRC PCK0 - PCK2 Main Oscillator Input Main Oscillator Output PLL Filter Programmable Clock Output Input Output Input Output ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Reset/Test NRST TST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input Input Input Input Output I/O Input Low High Pull-up resistor Pull-down resistor Input High Pull-down resistor Input Input Output Input Input No pull-up resistor Pull-down resistor No pull-up resistor No pull-up resistor 4 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function PIO Type Active Level Comments PA0 - PA31 Parallel IO Controller A I/O USB Device Port Pulled-up input at reset DDM DDP USB Device Port Data USB Device Port Data + USART Analog Analog SCK0 - SCK1 TXD0 - TXD1 RXD0 - RXD1 RTS0 - RTS1 CTS0 - CTS1 DCD1 DTR1 DSR1 RI1 Serial Clock Transmit Data Receive Data Request To Send Clear To Send Data Carrier Detect Data Terminal Ready Data Set Ready Ring Indicator I/O I/O Input Output Input Input Output Input Input Synchronous Serial Controller TD RD TK RK TF RF Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter TCLK0 - TCLK2 TIOA0 - TIOA2 TIOB0 - TIOB2 External Clock Inputs I/O Line A I/O Line B Input I/O I/O PWM Controller PWM0 - PWM3 PWM Channels SPI Output MISO MOSI SPCK NPCS0 NPCS1-NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select 1 to 3 I/O I/O I/O I/O Output Low Low 5 6116A–ATARM–15-Apr-05 Table 3-1. Signal Name Signal Description List (Continued) Function Type Two-Wire Interface Active Level Comments TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O Analog-to-Digital Converter AD0-AD3 AD4-AD7 ADTRG ADVREF Analog Inputs Analog Inputs ADC Trigger ADC Reference Analog Analog Input Analog Fast Flash Programming Interface Digital pulled-up inputs at reset Analog Inputs PGMEN0-PGMEN2 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command Input Input I/O Output Output Input Input Input Low High Low Low 6 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 4. Package and Pinout The AT91SAM7S128 is available in a 64-lead LQFP package. 4.1 64-lead LQFP Mechanical Overview Figure 4-1 shows the orientation of the 64-lead LQFP package. A detailed mechanical description is given in the section Mechanical Characteristics of the full datasheet. Figure 4-1. 64-lead LQFP Package Pinout (Top View) 48 49 33 32 64 1 16 17 4.2 Pinout AT91SAM7S128 Pinout in 64-lead LQFP Package ADVREF GND AD4 AD5 AD6 AD7 VDDIN VDDOUT PA17/PGMD5/AD0 PA18/PGMD6/AD1 PA21/PGMD9 VDDCORE PA19/PGMD7/AD2 PA22/PGMD10 PA23/PGMD11 PA20/PGMD8/AD3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 GND VDDIO PA16/PGMD4 PA15/PGMD3 PA14/PGMD2 PA13/PGMD1 PA24/PGMD12 VDDCORE PA25/PGMD13 PA26/PGMD14 PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/PGMM0 PA7/PGMNVALID 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 TDI PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD PA27/PGMD15 PA28 NRST TST PA29 PA30 PA3 PA2/PGMEN2 VDDIO GND PA1/PGMEN1 PA0/PGMEN0 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 TDO JTAGSEL TMS PA31 TCK VDDCORE ERASE DDM DDP VDDIO VDDFLASH GND XOUT XIN/PGMCK PLLRC VDDPLL Table 4-1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 7 6116A–ATARM–15-Apr-05 5. Power Considerations 5.1 Power Supplies The AT91SAM7S128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND. • VDDOUT pin. It is the output of the 1.8V voltage regulator. • VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V to 3.6V, 3.3V nominal. Note that supplying less than 3.0V to VDDIO prevents any use of the USB transceivers. • VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal. • VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly. • VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin. No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane. 5.2 Power Consumption The AT91SAM7S128 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brown-out detector is deactivated. Activating the brown-out detector adds 20 µA static current. The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA. 5.3 Voltage Regulator The AT91SAM7S128 embeds a voltage regulator that is managed by the System Controller. In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current. The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1 mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 8 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 5.4 Typical Powering Schematics The AT91SAM7S128 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1 shows the power schematics to be used for USB bus-powered systems. Figure 5-1. 3.3V System Single Power Supply Schematic VDDFLASH Power Source ranges from 4.5V (USB) to 18V DC/DC Converter VDDIO VDDIN 3.3V VDDOUT Voltage Regulator VDDCORE VDDPLL 9 6116A–ATARM–15-Apr-05 6. I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level. The pin JTAGSEL integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. 6.2 Test Pin The pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S128 when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the pin TST and the pins PA0 and PA1 should be tied high and PA2 tied low. Driving the pin TST at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results. 6.3 Reset Pin The pin NRST is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset all the components of the system. The pin NRST integrates a permanent pull-up resistor to VDDIO. 6.4 ERASE Pin The pin ERASE is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. 6.5 PIO Controller A Lines All the I/O lines PA0 to PA31 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset. 10 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 6.6 I/O Line Drive Levels The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 150 mA. 11 6116A–ATARM–15-Apr-05 7. Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs at up to 55 MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM® high-performance 32-bit instruction set – Thumb® high code density 16-bit instruction set • Three-stage pipeline architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 7.2 Debug and Test Features • Integrated embedded in-circuit emulator – Two watchpoint units – Test access port accessible through a JTAG protocol – Debug communication channel • Debug Unit – Two-pin UART – Debug communication channel interrupt handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on all digital pins 7.3 Memory Controller • Bus Arbiter – Handles requests from the ARM7TDMI and the Peripheral DMA Controller • Address decoder provides selection signals for – Three internal 1 Mbyte memory areas – One 256 Mbyte embedded peripheral area • Abort Status Registers – Source, Type and all parameters of the access leading to an abort are saved – Facilitates debug by detection of bad pointers • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap Command – Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors • Embedded Flash Controller – Embedded Flash interface, up to three programmable wait states 12 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary – Prefetch buffer, bufferizing and anticipating the 16-bit requests, reducing the required wait states – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 7.4 Peripheral DMA Controller • Handles data transfer between peripherals and memories • Eleven channels – Two for each USART – Two for the Debug Unit – Two for the Serial Synchronous Controller – Two for the Serial Peripheral Interface – One for the Analog-to-digital Converter • Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements 13 6116A–ATARM–15-Apr-05 8. Memory • 128 Kbytes of Flash Memory – 512 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in worst case conditions – Page programming time: 4 ms, including page auto-erase – Page programming without auto-erase: 2 ms – Full chip erase time: 10 ms – 10,000 write cycles, 10-year data retention capability – 8 lock bits, each protecting 8 sectors of 64 pages – Protection Mode to secure contents of the Flash • 32 Kbytes of Fast SRAM – Single-cycle access at full speed 8.1 8.1.1 Memory Mapping Internal SRAM The AT91SAM7S128 embeds a high-speed 32-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.1.2 Internal Flash The AT91SAM7S128 features one bank of 128 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command. Figure 8-1. Internal Memory Mapping 0x0000 0000 0x000F FFFF Flash Before Remap SRAM After Remap Internal Flash 1 M Bytes 0x0010 0000 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 Internal SRAM 1 M Bytes Undefined Areas (Abort) 253 M Bytes 0x0FFF FFFF 14 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 8.2 8.2.1 Embedded Flash Flash Overview The Flash of the AT91SAM7S128 is organized in 512 pages of 256 bytes. The 131,072 bytes are organized in 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions. When Flash is not used (read or write access), it is automatically placed into standby mode. 8.2.2 Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows: • programming of the access parameters of the Flash (number of wait states, timings, etc.) • starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. • getting the end status of the last command • getting error status • programming interrupts on the end of the last commands or on errors The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. 8.2.3 Lock Regions The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-regions erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 8 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.2.4 Security Bit Feature The AT91SAM7S128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command "Set Security Bit" of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted. 15 6116A–ATARM–15-Apr-05 It is important to note that the assertion of the ERASE pin should always be longer than 50 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application. 8.2.5 Non-volatile Brownout Detector Control T wo general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state. These two GPNVM bits can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface. • GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default. • The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default. 8.2.6 Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 8.3 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 is tied low. 16 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 9. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 9-1. System Controller Block Diagram System Controller jtag_nreset Boundary Scan TAP Controller irq0-irq1 fiq periph_irq[2..14] nirq Advanced Interrupt Controller int nfiq proc_nreset PCK debug ARM7TDMI pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq ice_nreset force_ntrst MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset cal gpnvm[0] en gpnvm[1] flash_wrdis ice_nreset jtag_nreset Debug Unit dbgu_irq force_ntrst dbgu_txd security_bit Periodic Interval Timer Real-Time Timer Watchdog Timer wdt_fault WDRPROC bod_rst_en pit_irq flash_poe rtt_irq flash_wrdis cal wdt_irq gpnvm[0..1] Embedded Flash MCK proc_nreset BOD Reset Controller periph_nreset proc_nreset Memory Controller POR flash_poe rstc_irq SLCK NRST Voltage Regulator Mode Controller standby Voltage Regulator cal RCOSC XIN SLCK periph_clk[2..14] pck[0-2] UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend OSC XOUT MAINCK Power Management Controller PCK UDPCK MCK USB Device Port PLLRC PLL PLLCK pmc_irq int idle periph_clk[4..14] periph_nreset periph_nreset usb_suspend periph_nreset periph_clk[2] dbgu_rxd periph_irq{2] irq0-irq1 Embedded Peripherals periph_irq[4..14] PIO Controller fiq dbgu_txd in PA0-PA31 out enable 17 6116A–ATARM–15-Apr-05 9.1 System Controller Mapping The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 9-2 shows the mapping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space. Figure 9-2. System Controller Mapping Address 0xFFFF F000 Peripheral Peripheral Name Size AIC 0xFFFF F1FF 0xFFFF F200 Advanced Interrupt Controller 512 Bytes/128 registers DBGU 0xFFFF F3FF 0xFFFF F400 Debug Unit 512 Bytes/128 registers PIOA 0xFFFF F5FF 0xFFFF F600 PIO Controller A 512 Bytes/128 registers Reserved 0xFFFF FBFF 0xFFFF FC00 PMC 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 Power Management Controller Reset Controller Real-time Timer Periodic Interval Timer Watchdog Timer Voltage Regulator Mode Controller 256 Bytes/64 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 4 Bytes/1 register RSTC Reserved RTT PIT WDT Reserved VREG Reserved MC 0xFFFF FFFF Memory Controller 256 Bytes/64 registers 18 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 9.2 Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. In addition, it controls the internal resets and the NRST pin output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. Note that if NRST is used as a reset output signal for external devices during power-off, the brownout detector must be activated. 9.2.1 Brownout Detector and Power-on Reset The AT91SAM7S128 embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply. The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device. The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE. Only VDDCORE is monitored, as a voltage drop on VDDFLASH or any other power supply of the device cannot affect the Flash. When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot-, defined as Vbot - hyst/2), the brownout output is immediately activated. When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs. The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated. The brownout detector is low-power, as it consumes less than 20 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash. 19 6116A–ATARM–15-Apr-05 9.3 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 220 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-3. Clock Generator Block Diagram Clock Generator Embedded RC Oscillator Slow Clock SLCK XIN XOUT Main Oscillator Main Clock MAINCK PLLRC PLL and Divider PLL Clock PLLCK Status Control Power Management Controller 20 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 9.4 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • three programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. Figure 9-4. Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int periph_clk[2..14] Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 pck[0..2] USB Clock Controller ON/OFF PLLCK Divider /1,/2,/4 usb_suspend UDPCK 9.5 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals RTT, PIT, EFC, PMC, DBGU, etc.) – Other sources control the peripheral interrupts or external interrupts – Programmable edge-triggered or level-sensitive internal sources – Programmable positive/negative edge-triggered or high/low level-sensitive external sources • 8-level Priority Controller – Drives the normal interrupt of the processor – Handles priority of the interrupt sources 21 6116A–ATARM–15-Apr-05 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes interrupt service routine branch and execution – One 32-bit vector register per interrupt source – Interrupt vector register reads the corresponding current interrupt vector • Protect Mode – Easy debugging by preventing automatic operations • Fast Forcing – Permits redirecting any interrupt source on the fast interrupt • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt 9.6 Debug Unit • Comprises: – One two-pin UART – One Interface for the Debug Communication Channel (DCC) support – One set of Chip ID Registers – One Interface providing ICE Access Prevention • Two-pin UART – Implemented features are compatible with the USART – Programmable Baud Rate Generator – Parity, Framing and Overrun Error – Automatic Echo, Local Loopback and Remote Loopback Channel Modes • Debug Communication Channel Support – Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of peripherals – Chip ID is 0x270c0740 (VERSION 0) 9.7 Periodic Interval Timer • 20-bit programmable counter plus 12-bit interval counter 9.8 Watchdog Timer • 12-bit key-protected Programmable Counter running on prescaled SCLK • Provides reset or interrupt signals to the system • Counter may be stopped while the processor is in debug state or in idle mode 9.9 Real-time Timer • 32-bit free-running counter with alarm running on prescaled SCLK • Programmable 16-bit prescaler for SLCK accuracy compensation 22 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 9.10 PIO Controller • One PIO Controller, controlling 32 I/O lines • Fully programmable through set/clear registers • Multiplexing of two peripheral functions per I/O line • For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) – Input change interrupt – Half a clock period glitch filter – Multi-drive option enables driving in open drain – Programmable pull-up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 9.11 Voltage Regulator Controller The aim of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). 23 6116A–ATARM–15-Apr-05 10. Peripherals 10.1 Peripheral Mapping Each peripheral is allocated 16 Kbytes of address space. Figure 10-1. User Peripheral Mapping Peripheral Name 0xF000 0000 Size Reserved 0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF 0xFFFA 4000 TC0, TC1, TC2 Timer/Counter 0, 1 and 2 16 Kbytes Reserved 0xFFFA FFFF 0xFFFB 0000 0xFFFB 3FFF 0xFFFB 4000 UDP USB Device Port 16 Kbytes Reserved 0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000 TWI Two-Wire Interface 16 Kbytes Reserved 0xFFFC 0000 0xFFFB FFFF USART0 0xFFFC 3FFF Universal Synchronous Asynchronous Receiver Transmitter 0 Universal Synchronous Asynchronous Receiver Transmitter 1 16 Kbytes 0xFFFC 4000 0xFFFC 7FFF 0xFFFC 8000 USART1 16 Kbytes Reserved 0xFFFC BFFF 0xFFFC C000 PWMC 0xFFFC FFFF 0xFFFD 0000 PWM Controller 16 Kbytes Reserved 0xFFFD 3FFF 0xFFFD 4000 0xFFFD 7FFF SSC Serial Synchronous Controller 16 Kbytes 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 ADC Analog-to-Digital Converter 16 Kbytes Reserved 0xFFFD FFFF 0xFFFE 0000 0xFFFE 3FFF 0xFFFE 4000 SPI Serial Peripheral Interface 16 Kbytes Reserved 0xFFFE FFFF 24 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 10.2 Peripheral Multiplexing on PIO Lines The AT91SAM7S128 features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set. PIO Controller A controls 32 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller. Table 10-1 on page 26 defines how the I/O lines of the peripherals A, B or the analog inputs are multiplexed on the PIO Controller A. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only may be duplicated in the table. All pins reset in their Parallel I/O lines function are configured in input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected. 25 6116A–ATARM–15-Apr-05 10.3 PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A Application Usage Comments High-Drive High-Drive High-Drive High-Drive Function Comments Table 10-1. I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A PWM0 PWM1 PWM2 TWD TWCK RXD0 TXD0 RTS0 CTS0 DRXD DTXD NPCS0 MISO MOSI SPCK TF TK TD RD RK RF RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DTR1 DSR1 RI1 IRQ1 NPCS1 Peripheral B TIOA0 TIOB0 SCK0 NPCS3 TCLK0 NPCS3 PCK0 PWM3 ADTRG NPCS1 NPCS2 PWM0 PWM1 PWM2 PWM3 TIOA1 TIOB1 PCK1 PCK2 FIQ IRQ0 PCK1 NPCS3 PWM0 PWM1 PWM2 TIOA2 TIOB2 TCLK1 TCLK2 NPCS2 PCK2 AD0 AD1 AD2 AD3 26 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 10.4 Peripheral Identifiers The AT91SAM7S128 embeds a wide range of peripherals. Table 10-2 defines the Peripheral Identifiers of the AT91SAM7S128. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-2. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 29 30 31 Peripheral Identifiers Peripheral Mnemonic AIC SYSIRQ PIOA Reserved ADC(1) SPI US0 US1 SSC TWI PWMC UDP TC0 TC1 TC2 Reserved AIC AIC Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 Analog-to Digital Converter Serial Peripheral Interface USART 0 USART 1 Synchronous Serial Controller Two-wire Interface PWM Controller USB Device Port Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 (1) Peripheral Name Advanced Interrupt Controller System Interrupt Parallel I/O Controller A External Interrupt FIQ Note: 1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller is continuously clocked. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion. 10.5 Serial Peripheral Interface • Supports communication with external serial devices – Four chip selects with external decoder allow communication with up to 15 peripherals – Serial memories, such as DataFlash® and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select 27 6116A–ATARM–15-Apr-05 – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection – Maximum frequency at up to Master Clock 10.6 Two-wire Interface • Master Mode only • Compatibility with standard two-wire serial memories • One, two or three bytes for slave address • Sequential read/write operations 10.7 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode – 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB or LSB first – Optional break generation and detection – By 8 or by 16 over-sampling receiver frequency – Hardware handshaking RTS - CTS – Modem Signals Management DTR-DSR-DCD-RI on USART1 – Receiver time-out and transmitter timeguard – Multi-drop Mode with address generation and detection – Manchester Encoder/Decoder • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.8 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal 28 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.9 Timer Counter • Three 16-bit Timer Counter Channels – Three output compare or two input capture • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs, as defined in Table 10-3 Table 10-3. Timer Counter Clocks Assignment Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 TC Clock Input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 – Two multi-purpose input/output signals – Two global registers that act on all three TC channels 10.10 PWM Controller • Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs • Independent channel programming – Independent enable/disable commands – Independent clock selection – Independent period and duty cycle, with double bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 29 6116A–ATARM–15-Apr-05 10.11 USB Device Port • USB V2.0 full-speed compliant,12 Mbits per second. • Embedded USB V2.0 full-speed transceiver • Embedded 328-byte dual-port RAM for endpoints • Four endpoints – Endpoint 0: 8 bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Ping-pong Mode (two memory banks) for bulk endpoints • Suspend/resume logic 10.12 Analog-to-digital Converter • 8-channel ADC • 10-bit 384 Ksamples/sec. Successive Approximation Register ADC • -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity • Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs • External voltage reference for better accuracy on low voltage inputs • Individual enable and disable of each channel • Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four of eight analog inputs shared with digital signals 30 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 11. ARM7TDMI Processor Overview 11.1 Overview The ARM7TDMI core executes both the 32-bit ARM® and 16-bit Thumb® instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages. The main features of the ARM7tDMI processor are: • ARM7TDMI Based on ARMv4T Architecture • Two Instruction Sets – ARM® High-performance 32-bit Instruction Set – Thumb® High Code Density 16-bit Instruction Set • Three-Stage Pipeline Architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 31 6116A–ATARM–15-Apr-05 11.2 ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) 11.2.1 Instruction Type Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). 11.2.2 Data Type ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries. Unaligned data access behavior depends on which instruction is used where. 11.2.3 ARM7TDMI Operating Mode The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes: User: The normal ARM program execution state FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system Abort mode: Implements virtual memory and/or memory protection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources. 11.2.4 ARM7TDMI Registers The ARM7TDMI processor has a total of 37registers: • 31 general-purpose 32-bit registers • 6 status registers These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer. At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer. 32 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Table 11-1. User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC ARM7TDMI ARM Modes and Registers Layout Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC CPSR CPSR SPSR_SVC CPSR SPSR_ABORT CPSR SPSR_UNDEF CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a generalpurpose register to be specified. Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor. 11.2.4.1 Modes and Exception Handling All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers. 33 6116A–ATARM–15-Apr-05 A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. 11.2.4.2 Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: • four ALU flags (Negative, Zero, Carry, and Overflow) • two interrupt disable bits (one for each type of interrupt) • one bit to indicate ARM or Thumb execution • five bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception. 11.2.4.3 Exception Types The ARM7TDMI supports five types of exception and a privileged processing mode for each type. The types of exceptions are: • fast interrupt (FIQ) • normal interrupt (IRQ) • memory aborts (used to implement memory protection or virtual memory) • attempted execution of an undefined instruction • software interrupts (SWIs) Exceptions are generated by internal and external sources. More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state. To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways: • by using a data-processing instruction with the S-bit set, and the PC as the destination • by using the Load Multiple with Restore CPSR instruction (LDM) 11.2.5 ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions • Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 11-2 gives the ARM instruction mnemonic list. 34 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Mnemonic CDP MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR STRH STRB STRBT STRT STM SWPB MRC STC Operation Coprocessor Data Processing Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor 11.2.6 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store Multiple instructions • Exception-generating instruction In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the 35 6116A–ATARM–15-Apr-05 Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 11-3 gives the Thumb instruction mnemonic list. Table 11-3. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack BL SWI STR STRH STRB LDRSB STMIA POP Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Mnemonic MVN ADC SBC CMN NEG BIC ORR LSR ROR Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right 36 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 12. AT91SAM7S128 Debug and Test Features 12.1 Description The AT91SAM7S128 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 12.2 Block Diagram Figure 12-1. Debug and Test Block Diagram TMS TCK TDI Boundary TAP ICE/JTAG TAP JTAGSEL TDO ICE Reset and Test POR TST ARM7TDMI PIO DTXD DRXD PDC DBGU 37 6116A–ATARM–15-Apr-05 12.3 12.3.1 Application Examples Debug Environment Figure 12-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 12-2. Application Debug Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector AT91SAM7S128 RS232 Connector Terminal AT91SAM7S128-based Application Board 38 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 12.3.2 Test Environment Figure 12-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91SAM7S128 Chip 1 AT91SAM7S128-based Application Board In Test 12.4 Debug and Test Pin Description Table 12-1. Pin Name Debug and Test Pin List Function Reset/Test Type Active Level NRST TST Microcontroller Reset Test Mode Select ICE and JTAG Input/Output Input Low High TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Debug Unit Input Input Output Input Input DRXD DTXD Debug Receive Data Debug Transmit Data Input Output 39 6116A–ATARM–15-Apr-05 12.5 12.6 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 12.6.1 Embedded In-circuit Emulator The ARM7TDMI embedded In-circuit Emulator is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is examined through an ICE/JTAG port. The ARM7TDMI processor contains hardware extensions for advanced debugging features: • In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system. • In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor. There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B). 12.6.2 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two Peripheral DMA Controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM7S128 Debug Unit Chip ID value is 0x270a0740 on 32-bit width. For further details on the Debug Unit, see ”Debug Unit (DBGU)” on page 177. 12.6.3 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. 40 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 12.6.3.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 96 bits that correspond to active pins and associated control signals. Each AT91SAM7S128 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-2. AT91SAM7S128 JTAG Boundary Scan Register Pin Name Pin Type Associated BSR Cells INPUT PA17/PGMD5/AD0 IN/OUT OUTPUT CONTROL INPUT PA18/PGMD6/AD1 IN/OUT OUTPUT CONTROL INPUT PA21/PGMD9 IN/OUT OUTPUT CONTROL INPUT PA19/PGMD7/AD2 IN/OUT OUTPUT CONTROL INPUT PA20/PGMD8/AD3 IN/OUT OUTPUT CONTROL INPUT PA16/PGMD4 IN/OUT OUTPUT CONTROL INPUT PA15/PGM3 IN/OUT OUTPUT CONTROL INPUT PA14/PGMD2 IN/OUT OUTPUT CONTROL INPUT PA13/PGMD1 IN/OUT OUTPUT CONTROL Bit Number 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 41 6116A–ATARM–15-Apr-05 Table 12-2. AT91SAM7S128 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PA22/PGMD10 IN/OUT OUTPUT CONTROL INPUT PA23/PGMD11 IN/OUT OUTPUT CONTROL INPUT PA24/PGMD12 IN/OUT OUTPUT CONTROL INPUT PA12/PGMD0 IN/OUT OUTPUT CONTROL INPUT PA11/PGMM3 IN/OUT OUTPUT CONTROL INPUT PA10/PGMM2 IN/OUT OUTPUT CONTROL INPUT PA9/PGMM1 IN/OUT OUTPUT CONTROL INPUT PA8/PGMM0 IN/OUT OUTPUT CONTROL INPUT PA7/PGMNVALID IN/OUT OUTPUT CONTROL INPUT PA6/PGMNOE IN/OUT OUTPUT CONTROL INPUT PA5/PGMRDY IN/OUT OUTPUT CONTROL INPUT PA4/PGMNCMD IN/OUT OUTPUT CONTROL Bit Number 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 42 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Table 12-2. AT91SAM7S128 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PA25/PGMD13 IN/OUT OUTPUT CONTROL INPUT PA26/PGMD14 IN/OUT OUTPUT CONTROL INPUT PA27/PGMD15 IN/OUT OUTPUT CONTROL INPUT PA28 IN/OUT OUTPUT CONTROL INPUT PA3 IN/OUT OUTPUT CONTROL INPUT PA2/PGMEN2 IN/OUT OUTPUT CONTROL INPUT PA1/PGMEN1 IN/OUT OUTPUT CONTROL INPUT PA0/PGMEN0 IN/OUT OUTPUT CONTROL INPUT PA29 IN/OUT OUTPUT CONTROL INPUT PA30 IN/OUT OUTPUT CONTROL INPUT PA31 IN/OUT OUTPUT CONTROL ERASE IN INPUT Bit Number 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 43 6116A–ATARM–15-Apr-05 12.6.4 ID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 • VERSION[31:28]: Product Version Number Set to 0x1. • PART NUMBER[27:12]: Product Part Number Set to 0x5B0A. • MANUFACTURER IDENTITY[11:1] Set to 0x01F. • Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 05b0_A03F. 44 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 13. Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state. 13.2 Block Diagram Figure 13-1. Reset Controller Block Diagram Reset Controller bod_rst_en brown_out Brownout Manager bod_reset Main Supply POR Startup Counter Reset State Manager rstc_irq proc_nreset user_reset NRST nrst_out NRST Manager exter_nreset periph_nreset WDRPROC wd_fault SLCK 45 6116A–ATARM–15-Apr-05 13.3 Functional Description The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 13.3.1 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager. Figure 13-2. NRST Manager RSTC_MR RSTC_SR URSTIEN rstc_irq RSTC_MR URSTS NRSTL Other interrupt sources user_reset URSTEN NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset 13.3.1.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 13.3.1.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 46 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. 13.3.2 Brownout Manager Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal. The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read. The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled. Figure 13-3. Brownout Manager bod_rst_en bod_reset RSTC_MR BODIEN RSTC_SR brown_out BODSTS Other interrupt sources rstc_irq 47 6116A–ATARM–15-Apr-05 13.3.3 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.3.3.1 Power-up Reset When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the device. The startup time, as shown in Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset. When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately. Figure 13-4. Power-up Reset SLCK MCK Main Supply POR output proc_nreset periph_nreset Any Freq. Startup Time Processor Startup = 3 cycles NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles 48 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 13.3.3.2 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 13-5. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset NRST (nrst_out) >= EXTERNAL RESET LENGTH 49 6116A–ATARM–15-Apr-05 13.3.3.3 Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered. When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset. Figure 13-6. Brownout Reset State SLCK MCK brown_out or bod_reset Resynch. 2 cycles Processor Startup = 3 cycles Any Freq. proc_nreset RSTTYP periph_nreset Any XXX 0x5 = Brownout Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 50 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 13.3.3.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 13-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) Any XXX 0x3 = Software Reset SRCMP in RSTC_SR 51 6116A–ATARM–15-Apr-05 13.3.3.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 13-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 52 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 13.3.4 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Power-up Reset • Brownout Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 13.3.5 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. • NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. • URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 13-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. • BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt. 53 6116A–ATARM–15-Apr-05 Figure 13-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 54 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 13.4 Reset Controller (RSTC) User Interface Reset Controller (RSTC) Register Mapping Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0000 0x0000_0000 Table 13-1. Offset 0x00 0x04 0x08 55 6116A–ATARM–15-Apr-05 13.4.1 Reset Controller Control Register RSTC_CR Write-only 30 29 28 KEY 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 – 19 – 11 – 3 EXTRST 18 – 10 – 2 PERRST 17 – 9 – 1 – 16 – 8 – 0 PROCRST 27 26 25 24 Register Name: Access Type: 31 • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 56 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 13.4.2 Reset Controller Status Register RSTC_SR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 25 – 17 SRCMP 9 RSTTYP 1 BODSTS 24 – 16 NRSTL 8 Register Name: Access Type: 31 – 23 – 15 – 7 – 2 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • BODSTS: Brownout Detection Status 0 = No brownout high-to-low transition happened since the last read of RSTC_SR. 1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 Reset Type Power-up Reset Watchdog Reset Software Reset User Reset Brownout Reset Comments VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low BrownOut reset occurred • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 57 6116A–ATARM–15-Apr-05 13.4.3 Reset Controller Mode Register RSTC_MR Read/Write 30 29 28 KEY 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 URSTIEN 19 – 11 18 – 10 ERSTL 3 – 2 – 1 – 0 URSTEN 17 – 9 16 BODIEN 8 27 26 25 24 Register Name: Access Type: 31 • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • BODIEN: Brownout Detection Interrupt Enable 0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 58 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 14. Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value. 14.2 Block Diagram Figure 14-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm 14.3 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 59 6116A–ATARM–15-Apr-05 The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Figure 14-2. RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 60 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 14.4 Real-time Timer (RTT) User Interface Real-time Timer (RTT) Register Mapping Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 Table 14-1. Offset 0x00 0x04 0x08 0x0C 61 6116A–ATARM–15-Apr-05 14.4.1 Real-time Timer Mode Register RTT_MR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RTPRES 7 6 5 4 RTPRES 3 2 1 0 27 – 19 – 11 26 – 18 RTTRST 10 25 – 17 RTTINCIEN 9 24 – 16 ALMIEN 8 Register Name: Access Type: 31 – 23 – 15 • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows: RTPRES = 0: The Prescaler Period is equal to 216 RTPRES ≠ 0: The Prescaler Period is equal to RTPRES. • ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 62 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 14.4.2 Real-time Timer Alarm Register RTT_AR Read/Write 30 29 28 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: 31 • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.4.3 Real-time Timer Value Register RTT_VR Read-only 30 29 28 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Register Name: Access Type: 31 • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 63 6116A–ATARM–15-Apr-05 14.4.4 Real-time Timer Status Register RTT_SR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 RTTINC 24 – 16 – 8 – 0 ALMS Register Name: Access Type: 31 – 23 – 15 – 7 – • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 64 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 15. Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset pit_irq 0 0 1 0 1 12-bit Adder read PIT_PIVR MCK 20-bit Counter Prescaler MCK/16 CPIV PIT_PIVR PICNT CPIV PIT_PIIR PICNT 65 6116A–ATARM–15-Apr-05 15.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. 66 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Figure 15-2. Enabling/Disabling PIT with PITEN APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle CPIV PICNT PITS (PIT_SR) APB Interface 0 1 0 PIV - 1 PIV 1 0 0 1 read PIT_PIVR 67 6116A–ATARM–15-Apr-05 15.4 Periodic Interval Timer (PIT) User Interface Periodic Interval Timer (PIT) Register Mapping Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 Table 15-1. Offset 0x00 0x04 0x08 0x0C 68 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 15.4.1 Periodic Interval Timer Mode Register PIT_MR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 PIV 7 6 5 4 PIV 3 2 1 0 27 – 19 26 – 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16 Register Name: Access Type: 31 – 23 – 15 • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 15.4.2 Periodic Interval Timer Status Register PIT_SR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 PITS Register Name: Access Type: 31 – 23 – 15 – 7 – • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 69 6116A–ATARM–15-Apr-05 15.4.3 Periodic Interval Timer Value Register PIT_PIVR Read-only 30 29 28 PICNT 23 22 PICNT 15 14 13 12 CPIV 7 6 5 4 CPIV 3 2 1 0 11 10 21 20 19 18 CPIV 9 8 17 16 27 26 25 24 Register Name: Access Type: 31 Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 15.4.4 Periodic Interval Timer Image Register PIT_PIIR Read-only 30 29 28 PICNT 23 22 PICNT 15 14 13 12 CPIV 7 6 5 4 CPIV 3 2 1 0 11 10 21 20 19 18 CPIV 9 8 17 16 27 26 25 24 Register Name: Access Type: 31 • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 70 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 16. Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.2 Block Diagram Figure 16-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WV reload 1 0 WDRSTT 12-bit Down Counter WDT_MR reload WDD Current Value 1/128 SLCK Data IN transactions > Status OUT transaction Control Transfers(1) (3) • Setup transaction > Data OUT transactions > Status IN transaction • Setup transaction > Status IN transaction • Data IN transaction > Data IN transaction • Data OUT transaction > Data OUT transaction • Data IN transaction > Data IN transaction • Data OUT transaction > Data OUT transaction • Data IN transaction > Data IN transaction • Data OUT transaction > Data OUT transaction Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake. 33.5.2 33.5.2.1 Handling Transactions with USB V2.0 Device Peripheral Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: • The USB device automatically acknowledges the setup packet • RXSETUP is set in the UDP_ CSRx register • An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_ CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. 414 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Figure 33-4. Setup Transaction Followed by a Data OUT Transaction Setup Received Setup Handled by Firmware Data Out Received USB Bus Packets Setup PID Data Setup ACK PID Data OUT PID Data OUT NAK PID Data OUT PID Data OUT ACK PID RXSETUP Flag Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) FIFO (DPR) Content XX Data Setup XX Data OUT 33.5.2.2 Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes. 33.5.2.3 Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_ CSRx register (TXPKTRDY must be cleared). 2. The microcontroller writes data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_ FDRx register, 3. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_ CSRx register. 4. The microcontroller is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_ CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer. 415 6116A–ATARM–15-Apr-05 Figure 33-5. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus USB Bus Packets Data IN PID Data IN 1 ACK PID Data IN PID NAK PID Data IN PID Data IN 2 ACK PID TXPKTRDY Flag (UDP_CSRx) Cleared by USB Device Interrupt Pending TXCOMP Flag (UDP_CSRx) Cleared by Firmware Start to Write Data Payload in FIFO Set by the Firmware Data Payload Written in FIFO Interrupt Pending FIFO (DPR) Content Data IN 1 Load In Progress Data IN 2 Load In Progress 33.5.2.4 Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. To be able to guarantee a constant bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 33-6. Bank Swapping Data IN Transfer for Ping-pong Endpoints Microcontroller Write Bank 0 Endpoint 1 USB Device Read USB Bus 1st Data Payload Read and Write at the Same Time 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Data IN Packet 1st Data Payload Data IN Packet 2nd Data Payload Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 416 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_ CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_ FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_ CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_ FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_ CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent rising TXPKTRDY in the endpoint’s UDP_ CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 33-7. Data IN Transfer for Ping-pong Endpoint Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 USB Bus Packets Data IN PID Data IN ACK PID Data IN PID Data IN ACK PID TXPKTRDY Flag (UDP_MCSRx) Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (UDP_CSRx) Cleared by USB Device, Data Payload Fully Transmitted Set by USB Device Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device Interrupt Cleared by Firmware FIFO (DPR) Written by Microcontroller Bank 0 Read by USB Device Written by Microcontroller FIFO (DPR) Bank 1 Written by Microcontroller Read by USB Device Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set is too long, some Data IN packets may be NACKed, reducing the bandwidth. 417 6116A–ATARM–15-Apr-05 33.5.2.5 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. 33.5.2.6 Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_ CSRx register. 5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the endpoint’s UDP_ FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. 7. A new Data OUT packet can be accepted by the USB device. Figure 33-8. Data OUT Transfer for Non Ping-pong Endpoints Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT2 PID Data OUT2 NAK PID Data OUT PID Data OUT2 ACK PID RX_DATA_BK0 (UDP_CSRx) Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device FIFO (DPR) Content Data OUT 1 Written by USB Device Data OUT 1 Microcontroller Read An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO. 418 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 33.5.2.7 Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data payload sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 33-9. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Data IN Packet nd Data Payload 2 Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_ CSRx register. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_ FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_ CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s UDP_ CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 419 6116A–ATARM–15-Apr-05 10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_ FDRx register. 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_ CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 33-10. Data OUT Transfer for Ping-pong Endpoint Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT PID Data OUT 2 ACK PID Data OUT PID Data OUT 3 A P RX_DATA_BK0 Flag (UDP_CSRx) Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 Cleared by Firmware RX_DATA_BK1 Flag (UDP_CSRx) Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 Cleared by Firmware Interrupt Pending FIFO (DPR) Bank 0 Data OUT1 Write by USB Device Data OUT 1 Read By Microcontroller Data OUT 3 Write In Progress FIFO (DPR) Bank 1 Data OUT 2 Write by USB Device Data OUT 2 Read By Microcontroller Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 33.5.2.8 Status Transaction A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. 420 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Figure 33-11. Control Read and Write Sequences Setup Stage Data Stage Status Stage Control Read Setup TX Data OUT TX Data OUT TX Status IN TX Setup Stage Data Stage Status Stage Control Write Setup TX Data IN TX Data IN TX Status OUT TX Setup Stage Status Stage No Data Control Setup TX Status IN TX Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 33.5.2.9 Status IN Transfer Once a control request has been processed, the device returns a status to the host. This is a zero length Data IN transaction. 1. The microcontroller waits for TXPKTRDY in the UDP_ CSRx endpoint’s register to be cleared. (At this step, TXPKTRDY must be cleared because the previous transaction was a setup transaction or a Data OUT transaction.) 2. Without writing anything to the UDP_ FDRx endpoint’s register, the microcontroller sets TXPKTRDY. The USB device generates a Data IN packet using DATA1 PID. 3. This packet is acknowledged by the host and TXPKTRDY is set in the UDP_ CSRx endpoint’s register. 421 6116A–ATARM–15-Apr-05 Figure 33-12. Data Out Followed by Status IN Transfer. Host Sends the Last Data Payload to the Device Device Sends a Status IN to the Host USB Bus Packets Data OUT PID Data OUT NAK PID Data IN PID ACK PID Interrupt Pending RX_DATA_BKO (UDP_CSRx) Cleared by Firmware Set by USB Device Cleared by USB Device TXPKTRDY (UDP_CSRx) Set by Firmware 33.5.2.10 Status OUT Transfer Once a control request has been processed and the requested data returned, the host acknowledges by sending a zero length packet. This is a zero length Data OUT transaction. 1. The USB device receives a zero length packet. It sets RX_DATA_BK0 flag in the UDP_ CSRx register and acknowledges the zero length packet. 2. The microcontroller is notified that the USB device has received a zero length packet sent by the host polling RX_DATA_BK0 in the UDP_ CSRx register. An interrupt is pending while RX_DATA_BK0 is set. The number of bytes received in the endpoint’s UDP_ BCR register is equal to zero. 3. The microcontroller must clear RX_DATA_BK0. Figure 33-13. Data IN Followed by Status OUT Transfer Device Sends the Last Data Payload to Host USB Bus Packets Device Sends a Status OUT to Host Data IN PID Data IN ACK PID Data OUT PID ACK PID Interrupt Pending RX_DATA_BKO (UDP_CSRx) Set by USB Device Cleared by Firmware TXCOMP (UDP_CSRx) Set by USB Device Cleared by Firmware 33.5.2.11 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) 422 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary • A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) • To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_ CSRx endpoint’s register. 2. The host receives the stall packet. 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. Figure 33-14. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 33-15. Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID FORCESTALL Set by Firmware Interrupt Pending STALLSENT Set by USB Device Cleared by Firmware 423 6116A–ATARM–15-Apr-05 33.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 33-16. USB Device State Diagram Attached Hub Reset or Deconfigured Hub Configured Bus Inactive Powered Bus Activity Power Interruption Suspended Reset Bus Inactive Default Reset Address Assigned Bus Inactive Bus Activity Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Suspended Configured Bus Activity Suspended Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 uA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse. The wake-up feature is not mandatory for all devices and must be negotiated with the host. 424 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 33.5.3.1 From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The USB host stops driving a reset state once it has detected the device’s pull-up on DP. The unmasked flag ENDBURSES is set in the register UDP_ISR and an interrupt is triggered. The UDP software enables the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. 33.5.3.2 From Default State to Address State After a set address standard device request, the USB host peripheral enters the address state. Before this, it achieves the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STATE, sets its new address, and sets the FEN bit in the UDP_FADDR register. 33.5.3.3 From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. 33.5.3.4 Enabling Suspend When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register. This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks may be switched off. However, the transceiver and the USB peripheral must not be switched off, otherwise the resume is not detected. 33.5.3.5 Receiving a Host Resume In suspend mode, the USB transceiver and the USB peripheral must be powered to detect the RESUME. However, the USB device peripheral may not be clocked as the WAKEUP signal is asynchronous. Once the resume is detected on the bus, the signal WAKEUP in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register. 33.5.3.6 Sending an External Resume The External Resume is negotiated with the host and enabled by setting the ESR bit in the UDP_ GLB_STATE. An asynchronous event on the ext_resume_pin of the peripheral generates a WAKEUP interrupt. On early versions of the USP peripheral, the K-state on the USB line is generated immediately. This means that the USB device must be able to answer to the host very 425 6116A–ATARM–15-Apr-05 quickly. On recent versions, the software sets the RMWUPE bit in the UDP_GLB_STATE register once it is ready to communicate with the host. The K-state on the bus is then generated. The WAKEUP bit must be cleared as soon as possible by setting WAKEUP in the UDP_ICR register. 426 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 33.6 USB Device Port (UDP) User Interface UDP Memory Map Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint 0 Control and Status Register . . . Endpoint 3 Control and Status Register Endpoint 0 FIFO Data Register . . . Endpoint 3 FIFO Data Register Reserved Transceiver Control Register Reserved UDP_ FDR3 – UDP_ TXVC – Read/Write – Read/Write – 0x0000_0000 – 0x0000_0000 – UDP_CSR3 UDP_ FDR0 Read/Write Read/Write 0x0000_0000 0x0000_0000 Name UDP_ FRM_NUM UDP_ GLB_STAT UDP_ FADDR – UDP_ IER UDP_ IDR UDP_ IMR UDP_ ISR UDP_ ICR – UDP_ RST_EP – UDP_CSR0 Access Read Read/Write Read/Write – Write Write Read Read Write – Read/Write – Read/Write – 0x0000_0000 – 0x0000_1200 0x0000_XX00 Reset State 0x0000_0000 0x0000_0010 0x0000_0100 – Table 33-4. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 . . . See Note: (1) 0x050 . . . See Note: (2) 0x070 0x074 0x078 - 0xFC Notes: 1. The addresses of the UDP_ CSRx registers are calculated as: 0x030 + 4(Endpoint Number - 1). 2. The addresses of the UDP_ FDRx registers are calculated as: 0x050 + 4(Endpoint Number - 1). 427 6116A–ATARM–15-Apr-05 33.6.1 UDP Frame Number Register UDP_ FRM_NUM Read-only 30 --22 – 14 – 6 29 --21 – 13 – 5 28 --20 – 12 – 4 FRM_NUM 27 --19 – 11 – 3 26 --18 – 10 25 --17 FRM_OK 9 FRM_NUM 1 24 --16 FRM_ERR 8 Register Name: Access Type: 31 --23 – 15 – 7 2 0 • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). • FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. • FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. 428 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 33.6.2 UDP Global State Register UDP_ GLB_STAT Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 RMWUPE 27 – 19 – 11 – 3 RSMINPR 26 – 18 – 10 – 2 ESR 25 – 17 – 9 – 1 CONFG 24 – 16 – 8 – 0 FADDEN Register Name: Access Type: 31 – 23 – 15 – 7 – This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_ FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • ESR: Enable Send Resume 0 = Disables the Remote Wake Up sequence. 1 = Remote Wake Up can be processed and the pin send_resume is enabled. • RSMINPR: A Resume Has Been Sent to the Host Read: 0 = No effect. 1 = A Resume has been received from the host during Remote Wake Up feature. 429 6116A–ATARM–15-Apr-05 • RMWUPE: Remote Wake Up Enable 0 = Must be cleared after receiving any HOST packet or SOF interrupt. 1 = Enables the K-state on the USB cable if ESR is enabled. 33.6.3 UDP Function Address Register UDP_ FADDR Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 FADD 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 FEN 0 Register Name: Access Type: 31 – 23 – 15 – 7 – • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. • FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. 430 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 33.6.4 UDP Interrupt Enable Register UDP_ IER Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 28 – 20 – 12 – 4 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT Register Name: Access Type: 31 – 23 – 15 – 7 – • EP0INT: Enable Endpoint 0 Interrupt • EP1INT: Enable Endpoint 1 Interrupt • EP2INT: Enable Endpoint 2Interrupt • EP3INT: Enable Endpoint 3 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. • RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt. • RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt. • EXTRSM: Enable External Resume Interrupt 0 = No effect. 1 = Enables External Resume Interrupt. • SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. • WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt. 431 6116A–ATARM–15-Apr-05 33.6.5 UDP Interrupt Disable Register UDP_ IDR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 28 – 20 – 12 – 4 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT Register Name: Access Type: 31 – 23 – 15 – 7 – • EP0INT: Disable Endpoint 0 Interrupt • EP1INT: Disable Endpoint 1 Interrupt • EP2INT: Disable Endpoint 2 Interrupt • EP3INT: Disable Endpoint 3 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. • RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt. • RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt. • EXTRSM: Disable External Resume Interrupt 0 = No effect. 1 = Disables External Resume Interrupt. • SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt • WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt. 432 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 33.6.6 UDP Interrupt Mask Register UDP_ IMR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 28 – 20 – 12 – 4 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT Register Name: Access Type: 31 – 23 – 15 – 7 – • EP0INT: Mask Endpoint 0 Interrupt • EP1INT: Mask Endpoint 1 Interrupt • EP2INT: Mask Endpoint 2 Interrupt • EP3INT: Mask Endpoint 3 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. • RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled. • RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled. • EXTRSM: Mask External Resume Interrupt 0 = External Resume Interrupt is disabled. 1 = External Resume Interrupt is enabled. • SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. • WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_ IMR is enabled. 433 6116A–ATARM–15-Apr-05 33.6.7 UDP Interrupt Status Register UDP_ ISR Read-only 30 – 22 – 14 – 29 – 21 – 13 WAKEUP 28 – 20 – 12 ENDBUSRE S 4 27 – 19 – 11 SOFINT 26 – 18 – 10 EXTRSM 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT Register Name: Access Type: 31 – 23 – 15 – 7 – 6 – 5 3 EP3INT 2 EP2INT • EP0INT: Endpoint 0 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_ CSR0 bit. • EP1INT: Endpoint 1 Interrupt Status 0 = No Endpoint1 Interrupt pending. 1 = Endpoint1 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR1: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP1INT is a sticky bit. Interrupt remains valid until EP1INT is cleared by writing in the corresponding UDP_ CSR1 bit. • EP2INT: Endpoint 2 Interrupt Status 0 = No Endpoint2 Interrupt pending. 1 = Endpoint2 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR2: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 434 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary TXCOMP set to 1 STALLSENT set to 1 EP2INT is a sticky bit. Interrupt remains valid until EP2INT is cleared by writing in the corresponding UDP_ CSR2 bit. • EP3INT: Endpoint 3 Interrupt Status 0 = No Endpoint3 Interrupt pending. 1 = Endpoint3 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_ CSR3: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP3INT is a sticky bit. Interrupt remains valid until EP3INT is cleared by writing in the corresponding UDP_ CSR3 bit. • RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. • RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ ICR register. • EXTRSM: External Resume Interrupt Status 0 = No External Resume Interrupt pending. 1 = External Resume Interrupt has been raised. This interrupt is raised when, in suspend mode, an asynchronous rising edge on the send_resume is detected. If RMWUPE = 1, a resume state is sent in the USB bus. • SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. 435 6116A–ATARM–15-Apr-05 This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. • WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ ICR register. 33.6.8 UDP Interrupt Clear Register UDP_ ICR Register Name: 436 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 WAKEUP 5 – 28 – 20 – 12 ENDBURSES 4 – 27 – 19 – 11 SOFINT 3 – 26 – 18 – 10 EXTRSM 2 – 25 – 17 – 9 RXRSM 1 – 24 – 16 – 8 RXSUSP 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt. • EXTRSM: Clear External Resume Interrupt 0 = No effect. 1 = Clears External Resume Interrupt. • SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. • ENDBURSES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt. • WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt. 437 6116A–ATARM–15-Apr-05 33.6.9 UDP Reset Endpoint Register UDP_ RST_EP Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 EP3 26 – 18 – 10 – 2 EP2 25 – 17 – 9 – 1 EP1 24 – 16 – 8 – 0 EP0 Register Name: Access Type: 31 – 23 – 15 – 7 – • EP0: Reset Endpoint 0 • EP1: Reset Endpoint 1 • EP2: Reset Endpoint 2 • EP3: Reset Endpoint 3 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear UDP_ CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_ CSRx register. 438 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 33.6.10 UDP Endpoint Control and Status Register UDP_ CSRx [x = 0..3] Read/Write 30 – 22 29 – 21 28 – 20 RXBYTECNT 15 EPEDS 7 DIR 14 – 6 RX_DATA_ BK1 13 – 5 FORCE STALL 12 – 4 TXPKTRDY 11 DTGLE 3 STALLSENT ISOERROR 10 9 EPTYPE 1 RX_DATA_ BK0 8 27 – 19 26 25 RXBYTECNT 17 24 Register Name: Access Type: 31 – 23 18 16 2 RXSETUP 0 TXCOMP • TXCOMP: Generates an IN packet with data previously written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. • RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. • RXSETUP: Sends STALL to the Host (Control Endpoints) This flag generates an interrupt while it is set to one. Read: 439 6116A–ATARM–15-Apr-05 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_ FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set. • STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints) / ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = Data values can be written in the FIFO. 1 = Data values can not be written in the FIFO. Write: 0 = No effect. 1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent. 440 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_ FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. • FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Write-only 0 = No effect. 1 = Sends STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: Notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. • RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO’s Bank 1. 1 = No effect. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_ FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. • DIR: Transfer Direction (only available for control endpoints) Read/Write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before UDP_ CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. • EPTYPE[2:0]: Endpoint Type Read/Write 000 001 101 010 Control Isochronous OUT Isochronous IN Bulk OUT 441 6116A–ATARM–15-Apr-05 Read/Write 110 011 111 Bulk IN Interrupt OUT Interrupt IN • DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. • EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. • RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_ FDRx register. 442 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 33.6.11 UDP FIFO Data Register UDP_ FDRx [x = 0..3] Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FIFO_DATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Register Name: Access Type: 31 – 23 – 15 – 7 • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_ CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. 33.6.12 UDP Transceiver Control Register UDP_ TXVC Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 TXVDIS 0 – Register Name: Access Type: 31 – 23 – 15 – 7 – • TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared. 443 6116A–ATARM–15-Apr-05 444 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 34. Analog-to-digital Converter (ADC) 34.1 Overview The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates an 8-to-1 analog multiplexer, making possible the analog-todigital conversions of up to eight analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These features reduce both power consumption and processor intervention. Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time. 34.2 Block Diagram Figure 34-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels ADC Trigger Selection ADTRG Control Logic ADC Interrupt AIC VDDIN ADVREF ASB AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND Successive Approximation Register Analog-to-Digital Converter APB PIO User Interface Peripheral Bridge PDC 445 6116A–ATARM–15-Apr-05 34.3 Signal Description ADC Pin Description Description Analog power supply Reference voltage Analog input channels External trigger Table 34-1. Pin Name VDDIN ADVREF AD0 - AD7 ADTRG 34.4 34.4.1 Product Dependencies Power Management The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into Sleep Mode, the Power Management Controller has no effect on the ADC behavior. 34.4.2 Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the ADC interrupt requires the AIC to be programmed first. 34.4.3 Analog Inputs The pins AD0 to AD7 can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND. 34.4.4 I/O Lines The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function. 34.4.5 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be non-connected. 34.4.6 Conversion Performances For performance and electrical characteristics of the ADC, see Section 35.7 ”ADC Characteristics”, on page 472. 446 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 34.5 34.5.1 Functional Description Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the ”ADC Mode Register” on page 453 and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in the Product definition section. 34.5.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 34.5.3 Conversion Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0. Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized. 34.5.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel. 447 6116A–ATARM–15-Apr-05 Figure 34-2. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) Conversion Time Conversion Time DRDY (ADC_SR) If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR. The OVRE and GOVRE flags are automatically cleared when ADC_SR is read. 448 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Figure 34-3. GOVRE and OVREx Flag Behavior ADTRG CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR ADC_CDR0 ADC_CDR1 Undefined Data Undefined Data Undefined Data Data A Data A Data B Data C Read ADC_SR Data C Data B EOC0 (ADC_SR) Conversion Conversion Read ADC_CDR0 EOC1 (ADC_SR) Conversion Read ADC_CDR1 GOVRE (ADC_SR) DRDY (ADC_SR) OVRE0 (ADC_SR) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. 34.5.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the bit TRGEN in the Mode Register (ADC_MR). If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits 449 6116A–ATARM–15-Apr-05 for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. 34.5.6 Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode Register ADC_MR. The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the PDC. Note: The reference voltage pins always remain connected in normal mode as in sleep mode. 34.5.7 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the SHTIM field. See the section DC Characteristics in the product datasheet. 450 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 34.6 Analog-to-digital Converter (ADC) User Interface Analog-to-Digital Converter (ADC) Register Mapping Register Control Register Mode Register Reserved Reserved Channel Enable Register Channel Disable Register Channel Status Register Status Register Last Converted Data Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Data Register 0 Channel Data Register 1 Channel Data Register 2 Channel Data Register 3 Channel Data Register 4 Channel Data Register 5 Channel Data Register 6 Channel Data Register 7 Reserved Name ADC_CR ADC_MR – – ADC_CHER ADC_CHDR ADC_CHSR ADC_SR ADC_LCDR ADC_IER ADC_IDR ADC_IMR ADC_CDR0 ADC_CDR1 ADC_CDR2 ADC_CDR3 ADC_CDR4 ADC_CDR5 ADC_CDR6 ADC_CDR7 – Access Write-only Read/Write – – Write-only Write-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only – Reset State – 0x00000000 – – – – 0x00000000 0x000C0000 0x00000000 – – 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 – Table 34-2. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50 - 0xFC 451 6116A–ATARM–15-Apr-05 34.6.1 ADC Control Register ADC_CR Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – – START SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion. 452 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 34.6.2 ADC Mode Register ADC_MR Read/Write 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 19 18 SHTIM 17 16 – 15 – 14 – 13 12 11 STARTUP 10 9 8 – 7 – 6 5 4 3 PRESCAL 2 1 0 – – SLEEP LOWRES TRGSEL TRGEN • TRGEN: Trigger Enable TRGEN 0 1 Selected TRGEN Hardware triggers are disabled. Starting a conversion is only possible by software. Hardware trigger selected by TRGSEL field is enabled. • TRGSEL: Trigger Selection TRGSEL 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected TRGSEL TIOA Ouput of the Timer Counter Channel 0 TIOA Ouput of the Timer Counter Channel 1 TIOA Ouput of the Timer Counter Channel 2 Reserved Reserved Reserved External trigger Reserved • LOWRES: Resolution LOWRES 0 1 Selected Resolution 10-bit resolution 8-bit resolution • SLEEP: Sleep Mode SLEEP 0 1 Selected Mode Normal Mode Sleep Mode 453 6116A–ATARM–15-Apr-05 • PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 ) • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock • SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+1) / ADCClock 454 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 34.6.3 ADC Channel Enable Register ADC_CHER Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. 34.6.4 ADC Channel Disable Register ADC_CHDR Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. 455 6116A–ATARM–15-Apr-05 34.6.5 ADC Channel Status Register ADC_CHSR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled. 456 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 34.6.6 ADC Status Register ADC_SR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 OVRE7 7 OVRE6 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. 1 = Corresponding analog channel is enabled and conversion is complete. • OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_SR. 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR. • DRDY: Data Ready 0 = No data has been converted since the last read of ADC_LCDR. 1 = At least one data has been converted and is available in ADC_LCDR. • GOVRE: General Overrun Error 0 = No General Overrun Error occurred since the last read of ADC_SR. 1 = At least one General Overrun Error has occurred since the last read of ADC_SR. • ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR. • RXBUFF: RX Buffer Full 0 = ADC_RCR or ADC_RNCR have a value other than 0. 1 = Both ADC_RCR and ADC_RNCR have a value of 0. 457 6116A–ATARM–15-Apr-05 34.6.7 ADC Last Converted Data Register ADC_LCDR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 LDATA 0 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 34.6.8 ADC Interrupt Enable Register ADC_IER Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 OVRE7 7 OVRE6 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion Interrupt Enable x • OVREx: Overrun Error Interrupt Enable x • DRDY: Data Ready Interrupt Enable • GOVRE: General Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 458 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 34.6.9 ADC Interrupt Disable Register ADC_IDR Write-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 OVRE7 7 OVRE6 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion Interrupt Disable x • OVREx: Overrun Error Interrupt Disable x • DRDY: Data Ready Interrupt Disable • GOVRE: General Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 459 6116A–ATARM–15-Apr-05 34.6.10 ADC Interrupt Mask Register ADC_IMR Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 OVRE7 7 OVRE6 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion Interrupt Mask x • OVREx: Overrun Error Interrupt Mask x • DRDY: Data Ready Interrupt Mask • GOVRE: General Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 34.6.11 ADC Channel Data Register ADC_CDRx Read-only 30 29 28 27 26 25 24 Register Name: Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 DATA 0 DATA • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled. 460 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 35. AT91SAM7S128 Electrical Characteristics 35.1 Absolute Maximum Ratings Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 35-1. Operating Temperature (Industrial).........-40° C to +85° C Storage Temperature.............................-60°C to +150°C Voltage on Input Pins with Respect to Ground-...........................-0.3V to +5.5V Maximum Operating Voltage (VDDCORE, and VDDPLL)....................................1.95V Maximum Operating Voltage (VDDIO, VDDIN and VDDFLASH)...........................3.6V Total DC Output Current on all I/O lines..............150 mA 461 6116A–ATARM–15-Apr-05 35.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified and are certified for a junction temperature up to TJ = 100°C. Table 35-2. Symbol VVDDCORE VVDDPLL VVDDIO VVDDFLASH VIL VIH VOL VOH ILEAK IPULLUP CIN DC Characteristics Parameter DC Supply Core DC Supply PLL DC Supply I/Os DC Supply Flash Input Low-level Voltage Input High-level Voltage Output Low-level Voltage Output High-level Voltage Input Leakage Current Input Pull-up Current Input Capacitance 64-LQFP Package On VVDDCORE = 1.85V, MCK = 0 Hz TA = 25°C 26 IO = 8 mA IO = 8 mA Pull-up resistors disabled (Typ: TA = 25°C, Max: TA = 85°C) 143 VDDIO - 0.4 20 321 200 600 13.9 50 µA TA = 85°C 260 500 Conditions Min 1.65 1.65 3.0 3.0 -0.3 2.0 Typ Max 1.95 1.95 3.6 3.6 0.8 5.5 0.4 Units V V V V V V V V nA µA pF ISC Static Current All inputs driven at 1 (including TMS, TDI, TCK, NRST) Flash in standby mode All peripherials off PA0-PA3 16 8 6 mA mA V/ms IO TSLOPE Output Current PA4-PA31 Supply Core Slope Note that even during startup, VVDDFLASH must always be superior or equal to VVDDCORE. Table 35-3. Symbol VVDDIN VVDDOUT IVDDIN TSTART IO IO 1.8V Voltage Regulator Characteristics Parameter Supply Voltage Output Voltage Current consumption After startup, Idle mode, no load Startup Time Maximum DC Output Current Maximum DC Output Current Cload = 2.2 µF, after VDDIN > 2.7V VDDIN = 3.3V VDDIN = 3.3V, in Idle Mode 25 150 100 1 µA µS mA mA IO = 20 mA After startup, no load Conditions Min 3.0 1.81 Typ 3.3 1.85 90 Max 3.6 1.89 Units V V µA 462 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Table 35-4. Symbol VBOTVHYST IDD TSTART Brownout Detector Characteristics Parameter Threshold Level Hysteresis Current Consumption BOD off (GPNVM0 bit inactive) Startup Time 100 1 200 µA µs VHYST = VBOT+ - VBOTBOD on (GPNVM0 bit active) Conditions Min 1.65 Typ 1.68 50 12 Max 1.71 65 18 Units V mV µA 463 6116A–ATARM–15-Apr-05 35.3 Power Consumption • Typical power consumption of PLLs, Slow Clock and Main Oscillator. • Power consumption of power supply in two different modes: Active and ultra Low-power. • Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. 35.3.1 Power Consumption Versus Modes The values in Table 35-5 and Table 35-6 on page 465 are estimated values of the power consumption with operating conditions as follows: • VDDIO = VDDIN = VDDFLASH= 3.3V • VDDCORE = VDDPLL = 1.85V • TA = 25° C • MCK = 50 MHz • There is no consumption on the I/Os of the device Figure 35-1. Measure Schematics: VDDFLASH VDDIO 3.3V AMP1 VDDIN Voltage Regulator VDDOUT 1.8V AMP2 VDDCORE VDDPLL 464 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary These figures represent the power consumption estimated on the power supplies.. Table 35-5. Mode Power Consumption for Different Modes Conditions Voltage regulator is on. Brown Out Detector is activated. Flash is read. ARM Core clock is 50MHz. Analog-to-Digital Converter activated. All peripheral clocks activated. onto AMP1 onto AMP2 Voltage regulator is in Low-power mode. Brown Out Detector is de-activated. Flash is in standby mode. ARM Core clock is 500Hz. Analog-to-Digital Converter de-activated. All peripheral clocks de-activated. onto AMP1 onto AMP2 Consumption Unit Active 31.3 29.3 mA Ultra low power 44 10 µA 35.3.2 Peripheral Power Consumption in Active Mode Table 35-6. Peripheral PIO Controller USART ADC UDP PWM TWI SPI SSC Power Consumption by Peripheral Consumption 0.4 0.9 0.7 1.0 0.3 0.2 0.9 1.1 0.2 mA Unit Timer Counter Channels 465 6116A–ATARM–15-Apr-05 35.3.3 Power Consumption versus Master Clock Frequency in Active Mode Figure 35-2 produces estimated values with operating conditions as follows: • VDDIO = VDDIN = VDDFLASH= 3.3V • VDDCORE = VDDPLL = 1.85V • TA = 25° C • MCK in the MHz range • Voltage regulator is on • Brown-out Detector is activated • Flash is read • Analog-to-Digital Converter activated • All peripheral clocks activated • USB Pads deactivated • There is no consumption on the I/Os of the device Figure 35-2 presents the power consumption estimated on the power supply. Figure 35-2. Power Consumption versus MCK Frequency in Active Mode Current Consumption at 3.3V 100,000 31,278 16,219 8,685 4,918 1,622 2,063 3,035 1,000 10,000 Consumption (µA) 6116A–ATARM–15-Apr-05 100 0.78125 1.5625 3.125 6.25 12.5 25 50 Frequency (MHz) 466 AT91SAM7S128 Preliminary AT91SAM7S128 Preliminary 35.3.4 Power Consumption versus Master Clock Frequency in Ultra Low-power Mode Figure 35-3 produces estimated values with operating conditions as follows: • VDDIO = VDDIN = VDDFLASH= 3.3V • VDDCORE = VDDPLL = 1.85V • TA = 25° C • Voltage regulator is in Low-power mode • Brown Out Detector is de-activated • Flash is in standby mode • Analog-to-digital Converter de-activated • All peripheral clocks de-activated • PLL in standby • Main oscillator in standby • USB Pads deactivated • There is no consumption on the I/Os of the device Figure 35-3 presents the power consumption estimated on the power supply. Figure 35-3. Power Consumption versus MCK Frequency in the Ultra Low Power Mode Current Consumption at 3.3V 100 35.2 35.3 35.7 36.4 37.7 40.5 46 10 0.5 1 2 4 Frequency (KHz) 8 16 32 Consumption (µA) 467 6116A–ATARM–15-Apr-05 35.4 35.4.1 Crystal Oscillators Characteristics RC Oscillator Characteristics RC Oscillator Characteristics Parameter RC Oscillator Frequency Duty Cycle Conditions VDDPLL = 1.65V Min 22 45 VDDPLL = 1.65V After Startup Time Typ 32 50 Max 42 55 75 1.9 Unit KHz % µs µA Table 35-7. Symbol 1/(tCPRC) tST IOSC Startup Time Current Consumption 35.4.2 Main Oscillator Characteristics Main Oscillator Characteristics Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Equivalent Load Capacitance Duty Cycle VDDPLL = 1.2 to 2V CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz Active mode 40 Conditions Min 3 Typ 16 25 12.5 50 60 14.5 1.4 1 550 1 Max 20 Unit MHz pF pF % Table 35-8. Symbol 1/(tCPMAIN) CL1, CL2 CL tST Startup Time ms µA µA IOSC Note: Current Consumption Standby mode 1. CS is the shunt capacitance 35.4.3 XIN Clock Characteristics XIN Clock Electrical Characteristics Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pull-down Resistor (1) (1) Table 35-9. Symbol 1/(tCPXIN) tCPXIN tCHXIN tCLXIN CIN RIN Note: Conditions Min Max 50.0 Units MHz ns 20.0 0.4 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN 0.6 x tCPXIN 25 500 pF kΩ 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register, see Section 24.9.7 ”PMC Clock Generator Main Oscillator Register” on page 169. 468 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 35.5 PLL Characteristics Table 35-10. Phase Lock Loop Characteristics Symbol FOUT FIN IPLL Note: Parameter Output Frequency Input Frequency Active mode Current Consumption Standby mode Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. 1 µA Conditions 00 Field out of CKGR_PLL is: 10 150 1 220 32 4 MHz MHz mA Min 80 Typ Max 160 Unit MHz 469 6116A–ATARM–15-Apr-05 35.6 35.6.1 USB Transceiver Characteristics Electrical Characteristics Table 35-11. Electrical Parameters Symbol Input Levels VIL VIH VDI VCM CIN I REXT Output Levels VOL VOH VCRS Low Level Output High Level Output Output Signal Crossover Voltage Measured with RL of 1.425 kOhm tied to 3.6V Measured with RL of 14.25 kOhm tied to GND Measure conditions described in Figure 35-4 0.0 2.8 1.3 0.3 3.6 2.0 V V V Low Level High Level Differential Input Sensitivity Differential Input Common Mode Range Transceiver capacitance Hi-Z State Data Line Leakage Recommended External USB Series Resistor Capacitance to ground on each line 0V < VIN < 3.3V In series with each USB pin with ±5% -10 27 |(D+) - (D-)| 2.0 0.2 0.8 2.5 9.18 +10 0.8 V V V V pF µA Ω Parameter Conditions Min Typ Max Unit 35.6.2 Switching Characteristics Table 35-12. In Low Speed Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 400 pF CLOAD = 400 pF CLOAD = 400 pF Min 75 75 80 Typ Max 300 300 125 Unit ns ns % Table 35-13. In Full Speed Symbol tFR tFE tFRFM Parameter Transition Rise Time Transition Fall Time Rise/Fall time Matching Conditions CLOAD = 50 pF CLOAD = 50 pF Min 4 4 90 Typ Max 20 20 111.11 Unit ns ns % 470 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Figure 35-4. USB Data Signal Rise and Fall Times Rise Time VCRS 10% Differential Data Lines tR (a) REXT=27 ohms Fosc = 6MHz/750kHz Buffer (b) Cload tF 90% 10% Fall Time 471 6116A–ATARM–15-Apr-05 35.7 ADC Characteristics Table 35-14. Channel Conversion Time and ADC CLock Parameter ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Throughput Rate ADC Clock = 5 MHz ADC Clock = 5 MHz Return from Idle Mode 600 2 384 Conditions Min Typ Max 5 20 Units MHz µs ns µs kSPS Table 35-15. External Voltage Reference Input Parameter ADVREF Input Voltage Range ADVREF Average Current On 13 samples with ADC Clock = 5 MHz Conditions Min 2.6 12 Max VDDIN 250 Units V µA Table 35-16. Analog Inputs Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 1 12 14 Typ Max VADVREF µA pF Units Table 35-17. Transfer Characteristics Parameter Resolution Integral Non-linearity Differential Non-linearity Offset Error Gain Error Min Typ 10 ±3 ±2 ±2 ±2 Max Units Bit LSB LSB LSB LSB 472 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 36. AT91SAM7S128 AC Characteristics 36.1 Applicable Conditions and Derating Data These conditions and derating process apply to the following paragraphs: Clock Characteristics, Embedded Flash Characteristics and JTAG/ICE Timings. 36.1.1 Conditions and Timings Computation All delays are given as typical values under the following conditions: • VDDIO = 3.3V • VDDCORE = 1.8V • Ambient Temperature = 25°C • Load Capacitance = 0 pF • The output level change detection is (0.5 x VDDIO). • The input level is 0.8V for a low-level detection and is 2.0V for a high-level detection. The minimum and maximum values given in the AC characteristics tables of this datasheet take into account process variation and design. In order to obtain the timing for other conditions, the following equation should be used: t = δT ° × ⎛ ( δVDDCORE × t DATASHEET ) + ⎛ δVDDIO × ⎝ ⎝ where: ( ∑CSIGNAL × δCSIGNAL )⎞ ⎞ ⎠⎠ • δT° is the derating factor in temperature given in Figure 36-1 on page 474. • δVDDCORE is the derating factor for the Core Power Supply given in Figure 36-2 on page 474. • tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. • δVDDIO is the derating factor for the IO Power Supply given in Figure 36-3 on page 475. • CSIGNAL is the capacitance load on the considered output pin(1). • δCSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet. The input delays are given as typical values. Note: The user must take into account the package capacitance load contribution (CIN) described in Table 35-2, “DC Characteristics,” on page 462. 473 6116A–ATARM–15-Apr-05 36.1.2 Temperature Derating Factor Figure 36-1. Derating Curve for Different Operating Temperatures 1,1 1,05 Derating Factor 1 0,95 0,9 0 ,85 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Operating Temperature (°C) 36.1.3 VDDCORE Voltage Derating Factor Figure 36-2. Derating Curve for Different Core Supply Voltages 1,15 1,1 Derating Factor 1,05 1 0,95 0 ,9 1,65 1,7 1,75 1,8 Core Supply Voltage (V) 1,85 1,9 1,95 474 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 36.1.4 VDDIO Voltage Derating Factor Figure 36-3. Derating Curve for Different IO Supply Voltages 1,1 1,05 Derating Factor 1 0,95 0,9 3 3,1 3,2 3,3 3,4 3,5 3,6 I/O Supply Voltage (V) Note: The derating factor in this example is applicable only to timings related to output pins. 475 6116A–ATARM–15-Apr-05 36.2 Clock Characteristics • VDDCORE = 1.8V • Ambient Temperature = 25°C These parameters are given in the following conditions: The Temperature Derating Factor described in ”Applicable Conditions and Derating Data” on page 473, section ”Temperature Derating Factor” on page 474 and VDDCORE Voltage Derating Factor described in ”Applicable Conditions and Derating Data” on page 473, section ”VDDCORE Voltage Derating Factor” on page 474 are both applicable to these characteristics. 36.2.1 Master Clock Characteristics Master Clock Waveform Parameters Parameter Master Clock Frequency Conditions Min Max 73 Units MHz Table 36-1. Symbol 1/(tCPMCK) 476 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 36.3 Embedded Flash Characteristics DC Flash Characteristics Parameter Power-up delay @25°C onto VDDCORE = 1.8V onto VDDFLASH = 3.3V ISB Standby current @85°C onto VDDCORE = 1.8V onto VDDFLASH = 3.3V Random Read @ 40MHz onto VDDCORE = 1.8V onto VDDFLASH = 3.3V ICC Active current Write onto VDDCORE = 1.8V onto VDDFLASH = 3.3V 400 5.5 µA mA 10 120 3.0 0.8 µA Conditions Min Max 30 10 30 Units µS Table 36-2. Symbol TPU µA mA The maximum operating frequency is given in Table 36-2 but is limited by the Embedded Flash access time when the processor is fetching code out of it. Table 36-3 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory. Table 36-3. Embedded Flash Wait States FWS 0 1 2 3 Read Operations 1 cycle 2 cycles 3 cycles 4 cycles Maximum Operating Frequency (MHz) 40 1/(tCPMCK) 1/(tCPMCK) 1/(tCPMCK) Table 36-4. Parameter AC Flash Characteristics Conditions per page including auto-erase Min Max 4 2 10 Units ms ms ms Program Cycle Time per page without auto-erase Full Chip Erase 477 6116A–ATARM–15-Apr-05 36.4 36.4.1 JTAG/ICE Timings ICE Interface Signals Table 36-5 shows timings relative to operating condition limits defined in the section ”Conditions and Timings Computation” on page 473. ICE Interface Timing Specification Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS, Setup before TCK High TDI, TMS, Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid CTDO = 0 pF CTDO derating Conditions Min 51 51 102 0 3 10 0.037 16 0.037 Max Units ns ns ns ns ns ns ns/pF ns ns/pF Table 36-5. Symbol ICE0 ICE1 ICE2 ICE3 ICE4 ICE5 ICE6 Figure 36-4. ICE Interface Signals ICE2 TCK ICE0 ICE1 TMS/TDI ICE3 ICE4 TDO ICE5 ICE6 478 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 36.4.2 JTAG Interface Signals The following table shows timings relative to operating condition limits defined in the section Section 36.1.1 ”Conditions and Timings Computation” on page 473. JTAG Interface Timing specification Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time COUT = 0 pF COUT derating TCK to Device Outputs Valid COUT = 0 pF COUT derating CTDO = 0 pF CTDO derating 0 3 4 0.037 15 0.037 Conditions Min 6.5 5.5 12 2 3 2 0.037 13 0.037 Max Units ns ns ns ns ns ns ns/pF ns ns/pF ns ns ns ns/pF ns ns/pF Table 36-6. Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 479 6116A–ATARM–15-Apr-05 Figure 36-5. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8 Device Outputs JTAG9 JTAG10 480 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 37. AT91SAM7S128 Mechanical Characteristics 37.1 37.1.1 Thermal Considerations Thermal Data In Table 37-1, the device lifetime is estimated using the MIL-217 standard in the “moderately controlled” environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see “Junction Temperature” below.) Note that the user must be extremely cautious with this MTBF calculation. It should be noted that the MIL-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 37-1. MTBF Versus Junction Temperature Estimated Lifetime (MTBF) (Year) 13.3 Junction Temperature (TJ) (°C) 100 Table 37-2 summarizes the thermal resistance data depending on the package. Table 37-2. Symbol θJA θJC Thermal Resistance Data Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Condition Still Air Package LQFP64 LQFP64 Typ 49.0 °C/W 14.1 Unit 37.1.2 Junction Temperature The average chip-junction temperature, TJ, in °C can be obtained from the following: 1. 2. T J = T A + ( P D × θ JA ) T J = T A + ( P D × ( θ HEATSINK + θ JC ) ) where: • θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 37-2 on page 481. • θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 37-2 on page 481. • θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet. • PD = device power consumption (W) estimated from data provided in the section Section 35.3 ”Power Consumption” on page 464. • TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. 481 6116A–ATARM–15-Apr-05 37.2 Package Drawings Figure 37-1. 64-lead LQFP Package Drawing 482 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Table 37-3. Symbol Min A A1 A2 D D1 E E1 R2 R1 q θ1 θ2 θ3 c L L1 S b e D2 E2 0.20 0.17 0.08 0.08 0° 0° 11° 11° 0.09 0.45 – 0.05 1.35 Nom – – 1.40 12.00 BSC 10.00 BSC 12.00 BSC 10.00 BSC – – 3.5° – 12° 12° – 0.60 1.00 REF – 0.20 0.50 BSC. 7.50 7.50 Tolerances of Form and Position aaa bbb ccc ddd 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 – 0.27 0.008 0.007 0.20 – 7° – 13° 13° 0.20 0.75 0.003 0.003 0° 0° 11° 11° 0.004 0.018 Max 1.60 0.15 1.45 Min – 0.002 0.053 Nom – – 0.055 0.472 BSC 0.383 BSC 0.472 BSC 0.383 BSC – – 3.5° – 12° 12° – 0.024 0.039 REF – 0.008 0.020 BSC. 0.285 0.285 – 0.011 0.008 – 7° – 13° 13° 0.008 0.030 Max 0.063 0.006 0.057 64-lead LQFP Package Dimensions (in mm) Millimeter Inch Table 37-4. 750 Device and 64-lead LQFP Package Maximum Weight mg Table 37-5. 64-lead LQFP Package Characteristics 3 Moisture Sensitivity Level 483 6116A–ATARM–15-Apr-05 Table 37-6. Package Reference MS-026 e2 JEDEC Drawing Reference JESD97 Classification This package respects the recommendations of the NEMI User Group. 37.3 Soldering Profile Table 37-7 gives the recommended soldering profile from J-STD-020C. Table 37-7. Soldering Profile Green Package 3° C/sec. max. 180 sec. max. 60 sec. to 150 sec. 20 sec. to 40 sec. 260 +0 ° C 6° C/sec. max. 8 min. max. Profile Feature Average Ramp-up Rate (217°C to Peak) Preheat Temperature 175°C ±25°C Temperature Maintained Above 217°C Time within 5° C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25° C to Peak Temperature Note: The package is certified to be backward compatible with Pb/Sn soldering profile. A maximum of three reflow passes is allowed per component. 484 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 37.4 AT91SAM7S128 Ordering Information Ordering Information Package LQFP 64 Package Type Green ROM Code Revision 001 Temperature Operating Range Industrial (-40° C to 85° C) Table 37-8. Ordering Code AT91SAM7S128-AU-001 485 6116A–ATARM–15-Apr-05 486 AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary Table of Contents Features ..................................................................................................... 1 1 2 3 4 Description ............................................................................................... 2 Block Diagram .......................................................................................... 3 Signal Description ................................................................................... 4 Package and Pinout ................................................................................. 7 4.164-lead LQFP Mechanical Overview .........................................................................7 4.2Pinout ........................................................................................................................7 5 Power Considerations ............................................................................. 8 5.1Power Supplies .........................................................................................................8 5.2Power Consumption ..................................................................................................8 5.3Voltage Regulator ......................................................................................................8 5.4Typical Powering Schematics ...................................................................................9 6 I/O Lines Considerations ....................................................................... 10 6.1JTAG Port Pins ........................................................................................................10 6.2Test Pin ...................................................................................................................10 6.3Reset Pin .................................................................................................................10 6.4ERASE Pin ..............................................................................................................10 6.5PIO Controller A Lines .............................................................................................10 6.6I/O Line Drive Levels ...............................................................................................11 7 Processor and Architecture .................................................................. 12 7.1ARM7TDMI Processor ............................................................................................12 7.2Debug and Test Features ........................................................................................12 7.3Memory Controller ...................................................................................................12 7.4Peripheral DMA Controller ......................................................................................13 8 Memory ................................................................................................... 14 8.1Memory Mapping .....................................................................................................14 8.2Embedded Flash .....................................................................................................15 8.3Fast Flash Programming Interface ..........................................................................16 9 System Controller .................................................................................. 17 9.1System Controller Mapping .....................................................................................18 9.2Reset Controller ......................................................................................................19 i 6116A–ATARM–15-Apr-05 9.3Clock Generator ......................................................................................................20 9.4Power Management Controller ................................................................................21 9.5Advanced Interrupt Controller .................................................................................21 9.6Debug Unit ..............................................................................................................22 9.7Periodic Interval Timer ............................................................................................22 9.8Watchdog Timer ......................................................................................................22 9.9Real-time Timer .......................................................................................................22 9.10PIO Controller ........................................................................................................23 9.11Voltage Regulator Controller .................................................................................23 10 Peripherals ............................................................................................. 24 10.1Peripheral Mapping ...............................................................................................24 10.2Peripheral Multiplexing on PIO Lines ....................................................................25 10.3PIO Controller A Multiplexing ................................................................................26 10.4Peripheral Identifiers .............................................................................................27 10.5Serial Peripheral Interface .....................................................................................27 10.6Two-wire Interface .................................................................................................28 10.7USART ..................................................................................................................28 10.8Serial Synchronous Controller ...............................................................................28 10.9Timer Counter .......................................................................................................29 10.10PWM Controller ...................................................................................................29 10.11USB Device Port .................................................................................................30 10.12Analog-to-digital Converter ..................................................................................30 11 ARM7TDMI Processor Overview .......................................................... 31 11.1Overview ...............................................................................................................31 11.2ARM7TDMI Processor ..........................................................................................32 12 AT91SAM7S128 Debug and Test Features .......................................... 37 12.1Description ............................................................................................................37 12.2Block Diagram .......................................................................................................37 12.3Application Examples ............................................................................................38 12.4Debug and Test Pin Description ............................................................................39 12.5Functional Description ...........................................................................................40 12.6Test Pin .................................................................................................................40 13 Reset Controller (RSTC) ........................................................................ 45 13.1Overview ...............................................................................................................45 13.2Block Diagram .......................................................................................................45 ii AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 13.3Functional Description ...........................................................................................46 13.4Reset Controller (RSTC) User Interface ................................................................55 14 Real-time Timer (RTT) ............................................................................ 59 14.1Overview ...............................................................................................................59 14.2Block Diagram .......................................................................................................59 14.3Functional Description ...........................................................................................59 14.4Real-time Timer (RTT) User Interface ...................................................................61 15 Periodic Interval Timer (PIT) ................................................................. 65 15.1Overview ...............................................................................................................65 15.2Block Diagram .......................................................................................................65 15.3Functional Description ...........................................................................................66 15.4Periodic Interval Timer (PIT) User Interface ..........................................................68 16 Watchdog Timer (WDT) ......................................................................... 71 16.1Overview ...............................................................................................................71 16.2Block Diagram .......................................................................................................71 16.3Functional Description ...........................................................................................72 16.4Watchdog Timer (WDT) User Interface .................................................................74 17 Voltage Regulator Mode Controller (VREG) ........................................ 77 17.1Overview ...............................................................................................................77 17.2Voltage Regulator Power Controller (VREG) User Interface .................................78 18 Memory Controller (MC) ........................................................................ 79 18.1Overview ...............................................................................................................79 18.2Block Diagram .......................................................................................................79 18.3Functional Description ...........................................................................................80 18.4Memory Controller (MC) User Interface ................................................................83 19 Embedded Flash Controller (EFC) ....................................................... 87 19.1Overview ..............................................................................................................87 19.2Functional Description ...........................................................................................87 19.3Embedded Flash Controller (EFC) User Interface .................................................97 20 Fast Flash Programming Interface (FFPI) .......................................... 103 20.1Overview .............................................................................................................103 20.2Parallel Fast Flash Programming ........................................................................104 20.3Serial Fast Flash Programming ...........................................................................111 iii 6116A–ATARM–15-Apr-05 21 Peripheral DMA Controller (PDC) ....................................................... 117 21.1Overview .............................................................................................................117 21.2Block Diagram .....................................................................................................117 21.3Functional Description .........................................................................................118 21.4Peripheral DMA Controller (PDC) User Interface ................................................120 22 Advanced Interrupt Controller (AIC) .................................................. 127 22.1Overview .............................................................................................................127 22.2Block Diagram .....................................................................................................127 22.3Application Block Diagram ..................................................................................127 22.4AIC Detailed Block Diagram ................................................................................128 22.5I/O Line Description .............................................................................................128 22.6Product Dependencies ........................................................................................128 22.7Functional Description .........................................................................................130 22.8Advanced Interrupt Controller (AIC) User Interface .............................................140 23 Clock Generator ................................................................................... 151 23.1Overview .............................................................................................................151 23.2Slow Clock RC Oscillator .....................................................................................151 23.3Main Oscillator .....................................................................................................151 23.4Divider and PLL Block .........................................................................................153 24 Power Management Controller ........................................................... 155 24.1Overview .............................................................................................................155 24.2Master Clock Controller .......................................................................................155 24.3Processor Clock Controller ..................................................................................156 24.4USB Clock Controller ..........................................................................................156 24.5Peripheral Clock Controller .................................................................................156 24.6Programmable Clock Output Controller ...............................................................157 24.7Programming Sequence ......................................................................................157 24.8Clock Switching Details .......................................................................................161 24.9Power Management User Interface ....................................................................164 25 Debug Unit (DBGU) .............................................................................. 177 25.1Overview .............................................................................................................177 25.2Block Diagram .....................................................................................................178 25.3Product Dependencies ........................................................................................179 25.4UART Operations ................................................................................................179 25.5Debug Unit (DBGU) User Interface ....................................................................187 iv AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 26 Parallel Input/Output Controller (PIO) ................................................ 201 26.1Overview .............................................................................................................201 26.2Block Diagram .....................................................................................................202 26.3Application Block Diagram ..................................................................................202 26.4Product Dependencies ........................................................................................203 26.5Functional Description .........................................................................................204 26.6I/O Lines Programming Example ........................................................................209 26.7Parallel Input/Output Controller (PIO) User Interface ..........................................210 27 Serial Peripheral Interface (SPI) ......................................................... 227 27.1Overview .............................................................................................................227 27.2Block Diagram .....................................................................................................228 27.3Application Block Diagram ..................................................................................228 27.4Signal Description ...............................................................................................229 27.5Product Dependencies ........................................................................................229 27.6Functional Description .........................................................................................230 27.7Serial Peripheral Interface (SPI) User Interface .................................................239 28 Two-wire Interface (TWI) ..................................................................... 253 28.1Overview .............................................................................................................253 28.2Block Diagram .....................................................................................................253 28.3Application Block Diagram ..................................................................................253 28.4Product Dependencies ........................................................................................254 28.5Functional Description .........................................................................................255 28.6Two-wire Interface (TWI) User Interface ............................................................260 29 Universal Synchronous Asynchronous Receiver Transmitter (USART) ................................................................................................ 269 29.1Overview .............................................................................................................269 29.2Block Diagram .....................................................................................................270 29.3Application Block Diagram ..................................................................................271 29.4I/O Lines Description ..........................................................................................271 29.5Product Dependencies ........................................................................................272 29.6Functional Description .........................................................................................273 29.7USART User Interface ........................................................................................306 30 Synchronous Serial Controller (SSC) ................................................ 323 30.1Overview .............................................................................................................323 30.2Block Diagram .....................................................................................................324 v 6116A–ATARM–15-Apr-05 30.3Application Block Diagram ..................................................................................324 30.4Pin Name List ......................................................................................................325 30.5Product Dependencies ........................................................................................325 30.6Functional Description .........................................................................................326 30.7SSC Application Examples ..................................................................................337 30.8Synchronous Serial Controller (SSC) User Interface .........................................339 31 Timer/Counter (TC) .............................................................................. 357 31.1Overview .............................................................................................................357 31.2Block Diagram .....................................................................................................357 31.3Pin Name List ......................................................................................................358 31.4Product Dependencies ........................................................................................358 31.5Functional Description .........................................................................................358 31.6Timer/Counter (TC) User Interface ......................................................................371 32 Pulse Width Modulation Controller (PWM) ........................................ 389 32.1Overview .............................................................................................................389 32.2Block Diagram .....................................................................................................389 32.3I/O Lines Description ...........................................................................................390 32.4Product Dependencies ........................................................................................390 32.5Functional Description .........................................................................................391 32.6Pulse Width Modulation Controller (PWM) User Interface ..................................399 33 USB Device Port (UDP) ........................................................................ 409 33.1Description ..........................................................................................................409 33.2Block Diagram .....................................................................................................410 33.3Product Dependencies ........................................................................................410 33.4Typical Connection ..............................................................................................412 33.5Functional Description .........................................................................................413 33.6USB Device Port (UDP) User Interface ...............................................................427 34 Analog-to-digital Converter (ADC) ..................................................... 445 34.1Overview .............................................................................................................445 34.2Block Diagram .....................................................................................................445 34.3Signal Description ...............................................................................................446 34.4Product Dependencies ........................................................................................446 34.5Functional Description .........................................................................................447 34.6Analog-to-digital Converter (ADC) User Interface ...............................................451 vi AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 AT91SAM7S128 Preliminary 35 AT91SAM7S128 Electrical Characteristics ........................................ 461 35.1Absolute Maximum Ratings .................................................................................461 35.2DC Characteristics ..............................................................................................462 35.3Power Consumption ............................................................................................464 35.4Crystal Oscillators Characteristics .......................................................................468 35.5PLL Characteristics .............................................................................................469 35.6USB Transceiver Characteristics .........................................................................470 35.7ADC Characteristics ...........................................................................................472 36 AT91SAM7S128 AC Characteristics ................................................... 473 36.1Applicable Conditions and Derating Data ............................................................473 36.2Clock Characteristics ...........................................................................................476 36.3Embedded Flash Characteristics .......................................................................477 36.4JTAG/ICE Timings ...............................................................................................478 37 AT91SAM7S128 Mechanical Characteristics .................................... 481 37.1Thermal Considerations ......................................................................................481 37.2Package Drawings ..............................................................................................482 37.3Soldering Profile ..................................................................................................484 37.4AT91SAM7S128 Ordering Information ................................................................485 Table of Contents....................................................................................... i Revision History..................................................................................... viii vii 6116A–ATARM–15-Apr-05 Revision History Doc. Rev. 6116A Date 15-Apr-05 Comments First issue. Qualified on web. Change Request Ref. viii AT91SAM7S128 Preliminary 6116A–ATARM–15-Apr-05 A tmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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