AT91SAM7S32-AI

Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE In-circuit Emulation, Debug Communication Channel Support 32 Kbytes of Internal High-speed Flash, Organized in 256 Pages of 128 Bytes – Single Cycle Access at Up to 30 MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms – 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Security Bit Guaranteeing Code Confidentiality – Fast Flash Programming Interface for High Volume Production 8 Kbytes of Internal High-speed SRAM, Single-cycle Access at Maximum Speed Memory Controller (MC) – Embedded Flash Controller, Abort Status and Misalignment Detection Reset Controller (RSTC) – Based on Power-on Reset and Low-power Factory-calibrated Brownout Detector – Allows External Reset Signal Shaping and Reset Source Status Clock Generator (CKGR) – Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL Power Management Controller (PMC) – Software Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode – Three Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – One External Interrupt Source and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) – 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle Mode Real-time Timer (RTT) – 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator One Parallel Input/Output Controller (PIOA) – Twenty-one Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output Nine Peripheral Data Controller (PDC) Channels One Synchronous Serial Controller (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support One Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects One Three-channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, Two multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability • • • • • • AT91 ARM® Thumb®-based Microcontrollers AT91SAM7S32 • Preliminary • • • • • • • • • • 6071A–ATARM–28-Oct-04 • One Four-channel 16-bit PWM Controller (PWMC) • One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs Supported One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os IEEE 1149.1 JTAG Boundary Scan on All Digital Pins 5V-tolerant I/Os, including Four High-current Drive I/O lines, Up to 16 mA Each Power Supplies – Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components – 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector • Fully Static Operation: Up to 55 MHz at 1.65V and 85 °C Worst Case Conditions • Available in a 48-lead LQFP Package • • • • Description Atmel’s AT91SAM7S32 is a member of a series of low pin count Flash microcontrollers based on the 32-bit ARM RISC processor. It features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM, a large set of peripherals and a complete set of system functions minimizing the number of external components. The device is an ideal migration path for 8-bit microcontroller users looking for additional performance and extended memory. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality. The AT91SAM7S32 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. The AT91SAM7S32 is a general-purpose microcontroller. Its aggressive price point and high level of integration pushes its scope of use far into the cost-sensitive, high-volume consumer market. 2 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Block Diagram Figure 1. AT91SAM7S32 Block Diagram TDI TDO TMS TCK JTAGSEL JTAG SCAN ICE ARM7TDMI Processor 1.8 V Voltage Regulator VDDIN GND VDDOUT VDDCORE TST FIQ System Controller AIC PIO IRQ0 Memory Controller Embedded Flash Controller Address Decoder Misalignment Detection VDDIO SRAM 8 Kbytes PCK0-PCK2 PLLRC XIN XOUT PLL OSC PMC Abort Status VDDFLASH RCOSC VDDCORE Flash 32 Kbytes ERASE BOD POR Reset Controller Peripheral Bridge VDDCORE NRST Peripheral Data Controller 9 Channels PIT WDT RTT DRXD DTXD PIO APB Fast Flash Programming Interface PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD7 PGMNCMD PGMEN0-PGMEN1 DBGU PDC PDC PIOA PWMC RXD0 TXD0 SCK0 RTS0 CTS0 NPCS0 NPCS1 NPCS2 NPCS3 MISO MOSI SPCK ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADVREF PDC PWM0 PWM1 PWM2 PWM3 TF TK TD RD RK RF TCLK0 TIOA0 TIOB0 TIOA1 TIOB1 USART PIO PDC PDC PDC SSC PDC SPI PDC PDC Timer Counter TC0 TC1 ADC TC2 TWI TWD TWCK PIO 3 6071A–ATARM–28-Oct-04 Signal Description Table 1. Signal Description List Signal Name Function Table 1 gives details on the signal names classified by peripheral. Type Power Active Level Comments VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL GND Main Power Supply Input Voltage Regulator Output Flash Power Supply I/O Lines Power Supply Core Power Supply PLL Ground Power Power Power Power Power Power Ground Clocks, Oscillators and PLLs 3.0V to 3.6V 1.85V nominal 3.0V to 3.6V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V XIN XOUT PLLRC PCK0 - PCK2 Main Oscillator Input Main Oscillator Output PLL Filter Programmable Clock Output Input Output Input Output ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Input Input Output Input Input Flash Memory No pull-up resistor No pull-up resistor No pull-up resistor Pull-down resistor ERASE Flash and NVM Configuration Bits Erase Command Reset/Test Input High Pull-down resistor NRST TST Microcontroller Reset Test Mode Select Debug Unit I/O Input Low Pull-Up resistor Pull-down resistor DRXD DTXD Debug Receive Data Debug Transmit Data AIC Input Output IRQ0 FIQ External Interrupt Input Fast Interrupt Input PIO Input Input PA0 - PA20 Parallel IO Controller A USART I/O Pulled-up input at reset 4 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Table 1. Signal Description List (Continued) Signal Name SCK0 TXD0 RXD0 RTS0 CTS0 Function Serial Clock Transmit Data Receive Data Request To Send Clear To Send Type I/O I/O Input Output Input Synchronous Serial Controller TD RD TK RK TF RF Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter TCLK0 TIOA0 - TIOA1 TIOB0 - TIOB1 External Clock Input I/O Line A I/O Line B Input I/O I/O PWM Controller PWM0 - PWM3 PWM Channels SPI MISO MOSI SPCK NPCS0 NPCS1-NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select 1 to 3 I/O I/O I/O I/O Output Low Low Output Active Level Comments Two-Wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O Analog-to-Digital Converter AD0-AD3 AD4-AD7 ADTRG ADVREF Analog Inputs Analog Inputs ADC Trigger ADC Reference Analog Analog Input Analog Fast Flash Programming Interface PGMEN0-PGMEN1 PGMM0-PGMM3 Programming Enabling Programming Mode Input Input Digital pulled-up inputs at reset Analog Inputs 5 6071A–ATARM–28-Oct-04 Table 1. Signal Description List (Continued) Signal Name PGMD0 - PGMD7 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD Function Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command Type I/O Output Output Input Input Input Low High Low Low Active Level Comments 6 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Package and Pinout The AT91SAM7S32 is available in a 48-lead LQFP package. 48-lead LQFP Mechanical Figure 2 shows the orientation of the 48-lead LQFP package. A detailed mechanical description is given in the section Mechanical Characteristics of the product datasheet. Overview Figure 2. 48-lead LQFP Package Pinout (Top View) 36 37 25 24 48 1 12 13 Pinout Table 2. AT91SAM7S32 Pinout in 48-lead LQFP Package 1 2 3 4 5 6 7 8 9 10 11 12 ADVREF GND AD4 AD5 AD6 AD7 VDDIN VDDOUT PA17/PGMD5/AD0 PA18/PGMD6/AD1 PA19/PGMD7/AD2 PA20/AD3 13 14 15 16 17 18 19 20 21 22 23 24 VDDIO PA16/PGMD4 PA15/PGMD3 PA14/PGMD2 PA13/PGMD1 VDDCORE PA12/PGMD0 PA11/PGMM3 PA10/PGMM2 PA9/PGMM1 PA8/PGMM0 PA7/PGMNVALID 25 26 27 28 29 30 31 32 33 34 35 36 TDI PA6/PGMNOE PA5/PGMRDY PA4/PGMNCMD NRST TST PA3 PA2 VDDIO GND PA1/PGMEN1 PA0/PGMEN0 37 38 39 40 41 42 43 44 45 46 47 48 TDO JTAGSEL TMS TCK VDDCORE ERASE VDDFLASH GND XOUT XIN/PGMCK PLLRC VDDPLL 7 6071A–ATARM–28-Oct-04 Power Considerations Power Supplies The AT91SAM7S32 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • • • • • VDDIN pin. It powers the voltage regulator; voltage ranges from 3.0V to 3.6V, 3.3V nominal. If the voltage regulator is not used, VDDIN should be connected to GND. VDDOUT pin. It is the output of the 1.8V voltage regulator. VDDIO pin. It powers the I/O lines and the USB transceivers; dual voltage range is supported. Ranges from 3.0V to 3.6V, 3.3V nominal. VDDFLASH pin. It powers a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal. VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly. VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin. • No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane. Power Consumption The AT91SAM7S32 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current. The dynamic power consumption on VDDCORE is less than 50 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA. Voltage Regulator The AT91SAM7S32 embeds a voltage regulator that is managed by the System Controller. In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current. The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 20 µA static current and draws 1 mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor must be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor must be connected between VDDOUT and GND. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 8 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Typical Powering Schematics The AT91SAM7S32 supports a 3.3V single supply mode. The internal regulator is connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 3. 3.3V System Single Power Supply Schematic VDDFLASH Power Source DC/DC Converter ranges from 4.5V to 18V 3.3V VDDIO VDDIN Voltage Regulator VDDOUT VDDCORE VDDPLL 9 6071A–ATARM–28-Oct-04 I/O Lines Considerations JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs. TMS and TCK are 5-V tolerant, TDI is not. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull resistor. The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level. The pin JTAGSEL integrates a permanent pull-down resistor of about 15 kW to GND, so that it can be left unconnected for normal operations. Test Pin The pin TST is used for manufacturing test or fast programming mode of the AT91SAM7S32 when asserted high. The pin TST integrates a permanent pull-down resistor of about 15 kW to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the pin TST and the pin PA0 and PA1 should be both tied high. Driving the pin TST at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results. Reset Pin The pin NRST is bi-directional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the pin NRST as system user reset, and the use of the signal NRST to reset all the components of the system. The pin NRST integrates a permanent pull-up resistor to VDDIO. ERASE Pin The pin ERASE is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 kW to GND, so that it can be left unconnected for normal operations. All the I/O lines PA0 to PA20 are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled can lead to unpredictable results. Care should be taken, in particular at reset, as all the I/O lines default in input with pull-up resistor enabled at reset. PIO Controller Lines I/O Line Drive Levels The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 100 mA. 10 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Processor and Architecture ARM7TDMI Processor • • RISC processor based on ARMv4T Von Neumann architecture – – – • – – – Runs at up to 55 MHz, providing 0.9 MIPS/MHz ARM ® high-performance 32-bit instruction set Thumb® high code density 16-bit instruction set Instruction Fetch (F) Instruction Decode (D) Execute (E) Two instruction sets Three-stage pipeline architecture Debug and Test Features • Integrated embedded in-circuit emulator – – – Two watchpoint units Test access port accessible through a JTAG protocol Debug communication channel Two-pin UART Debug communication channel interrupt handling Chip ID Register • Debug Unit – – – • IEEE1149.1 JTAG Boundary-scan on all digital pins Bus Arbiter – Handles requests from the ARM7TDMI and the Peripheral Data Controller Three internal 1 Mbyte memory areas One 256 Mbyte embedded peripheral area Source, Type and all parameters of the access leading to an abort are saved Facilitates debug by detection of bad pointers Alignment checking of all data accesses Abort generation in case of misalignment Remaps the SRAM in place of the embedded non-volatile memory Allows handling of dynamic exception vectors Embedded Flash interface, up to three programmable wait states Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states Key-protected program, erase and lock/unlock sequencer Single command for erasing, programming and locking operations Interrupt generation in case of forbidden operation Address decoder provides selection signals for – – Memory Controller • • • Abort Status Registers – – • Misalignment Detector – – • Remap Command – – • Embedded Flash Controller – – – – – 11 6071A–ATARM–28-Oct-04 Peripheral Data Controller • • Handles data transfer between peripherals and memories Nine channels – – – – – Two for the USART Two for the Debug Unit Two for the Serial Synchronous Controller Two for the Serial Peripheral Interface One for the Analog-to-digital Converter One Master Clock cycle needed for a transfer from memory to peripheral Two Master Clock cycles needed for a transfer from peripheral to memory • Low bus arbitration overhead – – • Next Pointer management for reducing interrupt latency requirements 12 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Memories • 32 Kbytes of Flash Memory – – – – – – – – • – 256 pages of 128 bytes Fast access time, 30 MHz single-cycle access in worst case conditions Page programming time: 4 ms, including page auto-erase Page programming without auto-erase: 2 ms Full chip erase time: 10 ms 10,000 write cycles, 10-year data retention capability 8 lock bits, each protecting 8 sectors of 32 pages Protection Mode to secure contents of the Flash Single-cycle access at full speed 8 Kbytes of Fast SRAM Memory Mapping Internal SRAM The AT91SAM7S32 embeds a high-speed 8-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. The AT91SAM7S32 features one bank of 32 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset and before the Remap Command. Figure 4. Internal Memory Mapping 0x0000 0000 0x000F FFFF Internal Flash Flash Before Remap SRAM After Remap Internal Flash 1 M Bytes 0x0010 0000 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 Internal SRAM 1 M Bytes Undefined Areas (Abort) 253 M Bytes 0x0FFF FFFF 13 6071A–ATARM–28-Oct-04 Embedded Flash Flash Overview The Flash of the AT91SAM7S32 is organized in 256 pages of 128 bytes. The 32,768 bytes are organized in 32-bit words. The Flash contains a 128-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions. Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows: • • • • • programming of the access parameters of the Flash (number of wait states, timings, etc.) starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. getting the end status of the last command getting error status programming interrupts on the end of the last commands or on errors The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. Lock Regions The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7S32 contains 8 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes. If a locked-regions erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 8 NVM bits are software programmable through the EFC User Interface. The command "Set Lock Bit" enables the protection. The command "Clear Lock Bit" unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. Security Bit Feature The AT91SAM7S32 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command "Set Security Bit" of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 50 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application. 14 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Non-volatile Brownout Detector Control Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain as defined by the user. These two GPNVM bits can be cleared or set respectively through the commands "Clear General-purpose NVM Bit" and "Set General-purpose NVM Bit" of the EFC User Interface. • GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default. The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default. • Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high. Fast Flash Programming Interface 15 6071A–ATARM–28-Oct-04 System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. Figure 5. System Controller Block Diagram System Controller jtag_nreset Boundary Scan TAP Controller irq0 fiq periph_irq[2..14] nirq Advanced Interrupt Controller int nfiq proc_nreset PCK debug ARM7TDMI pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq ice_nreset force_ntrst dbgu_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset cal gpnvm[0] en gpnvm[1] flash_wrdis Debug Unit Periodic Interval Timer Real-Time Timer Watchdog Timer wdt_fault WDRPROC bod_rst_en force_ntrst dbgu_txd security_bit pit_irq flash_poe rtt_irq flash_wrdis cal wdt_irq gpnvm[0..1] Embedded Flash MCK periph_nreset proc_nreset proc_nreset BOD jtag_nreset Memory Controller POR flash_poe Reset Controller ice_nreset rstc_irq NRST SLCK Voltage Regulator Mode Controller standby cal Voltage Regulator RCOSC XIN SLCK periph_clk[2..14] pck[0-2] OSC XOUT MAINCK Power Management Controller PCK MCK PLLRC PLL PLLCK pmc_irq int idle periph_clk[4..14] periph_nreset periph_nreset periph_nreset periph_clk[2] dbgu_rxd periph_irq{2] irq0 Embedded Peripherals periph_irq[4..14] PIO Controller fiq dbgu_txd in PA0-PA20 out enable 16 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary System Controller Mapping The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 6 shows the mapping of the System Controller. Note that the Memory Controller configuration user interface is also mapped within this address space. Figure 6. System Controller Mapping Address 0xFFFF F000 Peripheral Peripheral Name Size AIC 0xFFFF F1FF 0xFFFF F200 Advanced Interrupt Controller 512 Bytes/128 registers DBGU 0xFFFF F3FF 0xFFFF F400 Debug Unit 512 Bytes/128 registers PIOA 0xFFFF F5FF 0xFFFF F600 PIO Controller A 512 Bytes/128 registers Reserved 0xFFFF FBFF 0xFFFF FC00 PMC 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 Power Management Controller Reset Controller Real-time Timer Periodic Interval Timer Watchdog Timer Voltage Regulator Mode Controller 256 Bytes/64 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 4 Bytes/1 register RSTC Reserved RTT PIT WDT Reserved VREG Reserved MC 0xFFFF FFFF Memory Controller 256 Bytes/64 registers 17 6071A–ATARM–28-Oct-04 Reset Controller The Reset Controller is based on a power-on reset cell and one brownout detector. It gives the status of the last reset, indicating whether it is a power-up reset, a software reset, a user reset, a watchdog reset or a brownout reset. In addition, it controls the internal resets and the NRST pin output. It allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. The AT91SAM7S32 embeds a brownout detection circuit and a power-on reset cell. Both are supplied with and monitor VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or power-down sequences or if brownouts occur on the VDDCORE power supply. The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device. The brownout detector monitors the VDDCORE level during operation by comparing it to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE. Only VDDCORE is monitored, as a voltage drop on VDDFLASH or any other power supply of the device cannot affect the Flash. When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot-, defined as Vbot - hyst/2), the brownout output is immediately activated. When VDDCORE increases above the trigger level (Vbot+, defined as Vbot + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs. The threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated. The brownout detector is low-power, as it consumes less than 20 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash. Brownout Detector and Power-on Reset 18 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • • • • RC Oscillator ranges between 22 KHz and 42 KHz Main Oscillator frequency ranges between 3 and 20 MHz Main Oscillator can be bypassed PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 7. Clock Generator Block Diagram Clock Generator Embedded RC Oscillator Slow Clock SLCK XIN XOUT Main Oscillator Main Clock MAINCK PLLRC PLL and Divider PLL Clock PLLCK Status Control Power Management Controller 19 6071A–ATARM–28-Oct-04 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • • • • the Processor Clock PCK the Master Clock MCK all the peripheral clocks, independently controllable three programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. Figure 8. Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int periph_clk[2..14] Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 pck[0..2] Advanced Interrupt Controller • • Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor Individually maskable and vectored interrupt sources – – – – – Source 0 is reserved for the Fast Interrupt Input (FIQ) Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) Other sources control the peripheral interrupts or external interrupts Programmable edge-triggered or level-sensitive internal sources Programmable positive/negative edge-triggered or high/low level-sensitive external sources Drives the normal interrupt of the processor Handles priority of the interrupt sources Higher priority interrupts can be served during service of lower priority interrupt Optimizes interrupt service routine branch and execution One 32-bit vector register per interrupt source Interrupt vector register reads the corresponding current interrupt vector Easy debugging by preventing automatic operations • 8-level Priority Controller – – – • Vectoring – – – • Protect Mode – 20 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary • • Fast Forcing – – Permits redirecting any interrupt source on the fast interrupt Provides processor synchronization on events without triggering an interrupt General Interrupt Mask Debug Unit • Comprises: – – – – One two-pin UART One Interface for the Debug Communication Channel (DCC) support One set of Chip ID Registers One interface providing ICE Access Prevention Implemented features are compatible with the USART Programmable Baud Rate Generator Parity, Framing and Overrun Error Automatic Echo, Local Loopback and Remote Loopback Channel Modes Offers visibility of COMMRX and COMMTX signals from the ARM Processor Identification of the device revision, sizes of the embedded memories, set of peripherals Chip ID is 0x27080340 (VERSION 0) • Two-pin UART – – – – • • Debug Communication Channel Support – – – Chip ID Registers Periodic Interval Timer Watchdog Timer • • • • 20-bit programmable counter plus 12-bit interval counter 12-bit key-protected Programmable Counter running on prescaled SLCK Provides reset or interrupt signals to the system Counter may be stopped while the processor is in debug state or in idle mode 32-bit free-running counter with alarm running on prescaled SLCK Programmable 16-bit prescaler for SLCK accuracy compensation One PIO Controller, controlling 21 I/O lines Fully programmable through set/clear registers Multiplexing of two peripheral functions per I/O line For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) – – – – – Input change interrupt Half a clock period glitch filter Multi-drive option enables driving in open drain Programmable pull-up on each I/O line Pin data status register, supplies visibility of the level on the pin at any time Real-time Timer • • PIO Controller • • • • • Synchronous output, provides Set and Clear of several I/O lines in a single write Voltage Regulator Controller The aim of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). 21 6071A–ATARM–28-Oct-04 Peripherals Peripheral Mapping Each peripheral is allocated 16 Kbytes of address space. Figure 9. User Peripheral Mapping Peripheral Name 0xF000 0000 Size Reserved 0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF 0xFFFA 4000 TC0, TC1, TC2 Timer/Counter 0, 1 and 2 16 Kbytes Reserved 0xFFFA FFFF 0xFFFB 0000 Reserved 0xFFFB 3FFF 0xFFFB 4000 Reserved 0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000 TWI Two-Wire Interface 16 Kbytes Reserved 0xFFFC 0000 0xFFFB FFFF USART 0xFFFC 3FFF Universal Synchronous Asynchronous Receiver Transmitter 16 Kbytes 0xFFFC 4000 Reserved 0xFFFC 7FFF 0xFFFC 8000 Reserved 0xFFFC BFFF 0xFFFC C000 PWMC 0xFFFC FFFF 0xFFFD 0000 PWM Controller 16 Kbytes Reserved 0xFFFD 3FFF 0xFFFD 4000 0xFFFD 7FFF SSC Serial Synchronous Controller 16 Kbytes 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 ADC Analog-to-Digital Converter 16 Kbytes Reserved 0xFFFD FFFF 0xFFFE 0000 0xFFFE 3FFF 0xFFFE 4000 SPI Serial Peripheral Interface 16 Kbytes Reserved 0xFFFE FFFF 22 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Peripheral Multiplexing on PIO Lines The AT91SAM7S32 features one PIO controller, PIOA, that multiplexes the I/O lines of the peripheral set. PIO Controller A controls 21 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller. Table 3 on page 23 defines how the I/O lines of the peripherals A, B or the analog inputs are multiplexed on PIO Controller A. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only may be duplicated in the table. All pins reset in their Parallel I/O lines function are configured in input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected. PIO Controller A Multiplexing Table 3. Multiplexing on PIO Controller A PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 Peripheral A PWM0 PWM1 PWM2 TWD TWCK RXD0 TXD0 RTS0 CTS0 DRXD DTXD NPCS0 MISO MOSI SPCK TF TK TD RD RK RF Peripheral B TIOA0 TIOB0 SCK0 NPCS3 TCLK0 NPCS3 PCK0 PWM3 ADTRG NPCS1 NPCS2 PWM0 PWM1 PWM2 PWM3 TIOA1 TIOB1 PCK1 PCK2 FIQ IRQ0 AD0 AD1 AD2 AD3 Comments High-Drive High-Drive High-Drive High-Drive Function Application Usage Comments 23 6071A–ATARM–28-Oct-04 Peripheral Identifiers The AT91SAM7S32 embeds a wide range of peripherals. Table 4 defines the Peripheral Identifiers of the AT91SAM7S32. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 4. Peripheral Identifiers Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 - 29 30 31 Peripheral Mnemonic AIC SYSIRQ(1) PIOA Reserved ADC(1) SPI US Reserved SSC TWI PWMC Reserved TC0 TC1 TC2 Reserved AIC Reserved Advanced Interrupt Controller IRQ0 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 Synchronous Serial Controller Two-wire Interface PWM Controller Analog-to Digital Converter Serial Peripheral Interface USART Peripheral Name Advanced Interrupt Controller System Interrupt Parallel I/O Controller A External Interrupt FIQ Note: 1. Setting SYSIRQ and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller is continuously clocked. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion. Serial Peripheral Interface • Supports communication with external serial devices – – – – Four chip selects with external decoder allow communication with up to 15 peripherals Serial memories, such as DataFlash® and 3-wire EEPROMs Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors External co-processors 8- to 16-bit programmable data length per chip select Programmable phase and polarity per chip select Programmable transfer delays between consecutive transfers and between clock and data per chip select Programmable delay between consecutive transfers Selectable mode fault detection Maximum frequency at up to Master Clock • Master or slave serial peripheral bus interface – – – – – – 24 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Two-wire Interface • • • • Master Mode only Compatibility with standard two-wire serial memories One, two or three bytes for slave address Sequential read/write operations Programmable Baud Rate Generator 5- to 9-bit full-duplex synchronous or asynchronous serial communications – – – – – – – – – – • • • • 1, 1.5 or 2 stop bits in Asynchronous Mode 1 or 2 stop bits in Synchronous Mode Parity generation and error detection Framing error detection, overrun error detection MSB or LSB first Optional break generation and detection By 8 or by 16 over-sampling receiver frequency Hardware handshaking RTS - CTS Receiver time-out and transmitter timeguard Multi-drop Mode with address generation and detection USART • • RS485 with driver control signal ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – – – NACK handling, error counter with repetition and iteration limit Communication at up to 115.2 Kbps Remote Loopback, Local Loopback, Automatic Echo IrDA modulation and demodulation Test Modes Serial Synchronous Controller • • • • • Provides serial synchronous communication links used in audio and telecom applications Contains an independent receiver and transmitter and a common clock divider Offers a configurable frame sync and data length Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal Three 16-bit Timer Counter Channels – Three output compare or two input capture Frequency measurement Event counting Interval measurement Pulse generation Delay timing Pulse Width Modulation Up/down capabilities Wide range of functions including: – – – – – – – Timer Counter • • 25 6071A–ATARM–28-Oct-04 • Each channel is user-configurable and contains: – – Three external clock inputs Five internal clock inputs, as defined in Table 5 Table 5. Timer Counter Clocks Assignment TC Clock Input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 – – Two multi-purpose input/output signals Two global registers that act on all three TC channels PWM Controller • • Four channels, one 16-bit counter per channel Common clock generator, providing thirteen different clocks – – One Modulo n counter providing eleven clocks Two independent linear dividers working on modulo n counter outputs Independent enable/disable commands Independent clock selection Independent period and duty cycle, with double buffering Programmable selection of the output waveform polarity Programmable center or left aligned output waveform • Independent channel programming – – – – – Analog-to-digital Converter • • • • • • • 8-channel ADC 10-bit 100 Ksamples/sec. Successive Approximation Register ADC -2/+2 LSB Integral Non Linearity, -1/+2 LSB Differential Non Linearity Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs External voltage reference for better accuracy on low voltage inputs Individual enable and disable of each channel Multiple trigger source – – – Hardware or software trigger External trigger pin Timer Counter 0 to 1 outputs TIOA0 to TIOA1 trigger Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Sleep Mode and conversion sequencer – • Four of eight analog inputs shared with digital signals 26 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary ARM7TDMI Processor Overview Overview The ARM7TDMI core executes both the 32-bit ARM ® and 16-bit Thumb ® instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages. The main features of the ARM7tDMI processor are: • • ARM7TDMI Based on ARMv4T Architecture Two Instruction Sets – – • – – – ARM® High-performance 32-bit Instruction Set Thumb® High Code Density 16-bit Instruction Set Instruction Fetch (F) Instruction Decode (D) Execute (E) Three-Stage Pipeline Architecture 27 6071A–ATARM–28-Oct-04 ARM7TDMI Processor For further details on ARM7TDMI, refer to the following ARM documents: ARM Architecture Reference Manual (DDI 0100E) ARM7TDMI Technical Reference Manual (DDI 0210B) Instruction Type Data Type Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state). ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries. Unaligned data access behavior depends on which instruction is used where. ARM7TDMI Operating Mode The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes: User: The normal ARM program execution state FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system Abort mode: Implements virtual memory and/or memory protection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources. ARM7TDMI Registers The ARM7TDMI processor has a total of 37registers: • • 31 general-purpose 32-bit registers 6 status registers These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer. At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing. Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction. R14 holds the return address after a subroutine call. R13 is used (by software convention) as a stack pointer 28 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary . Table 6. ARM7TDMI ARM Modes and Registers Layout User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC CPSR CPSR SPSR_SVC CPSR SPSR_ABORT CPSR SPSR_UNDEF CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32-bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a general-purpose register to be specified. Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor. Modes and Exception Handling All exceptions have banked registers for R14 and R13. After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception. R13 is banked across exception modes to provide each exception handler with a private stack pointer. The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers. 29 6071A–ATARM–28-Oct-04 A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions. Status Registers All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds: • • • • four ALU flags (Negative, Zero, Carry, and Overflow) two interrupt disable bits (one for each type of interrupt) one bit to indicate ARM or Thumb execution five bits to encode the current processor mode All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception. Exception Types The ARM7TDMI s upports five types of exception and a privileged processing mode for each type. The types of exceptions are: • • • • • fast interrupt (FIQ) normal interrupt (IRQ) memory aborts (used to implement memory protection or virtual memory) attempted execution of an undefined instruction software interrupts (SWIs) Exceptions are generated by internal and external sources. More than one exception can occur in the same time. When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state. To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways: • • by using a data-processing instruction with the S-bit set, and the PC as the destination by using the Load Multiple with Restore CPSR instruction (LDM) ARM Instruction Set Overview The ARM instruction set is divided into: • • • • • • Branch instructions Data processing instructions Status register transfer instructions Load and Store instructions Coprocessor instructions Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]). Table 7 gives the ARM instruction mnemonic list. 30 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Table 7. ARM Instruction Mnemonic List Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Mnemonic CDP MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR STRH STRB STRBT STRT STM SWPB MRC STC Operation Coprocessor Data Processing Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • • • • • Branch instructions Data processing instructions Load and Store instructions Load and Store Multiple instructions Exception-generating instruction In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) 31 6071A–ATARM–28-Oct-04 and the Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15. Table 8 gives the Thumb instruction mnemonic list. Table 8. Thumb Instruction Mnemonic List Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Mnemonic MVN ADC SBC CMN NEG BIC ORR LSR ROR Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right BL SWI STR STRH STRB LDRSB STMIA POP Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack 32 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary AT91SAM7S32 Debug and Test Features Description The AT91SAM7S32 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. Block Diagram Figure 10. Debug and Test Block Diagram TMS TCK TDI Boundary TAP ICE/JTAG TAP JTAGSEL TDO ICE Reset and Test POR TST ARM7TDMI PIO DTXD DRXD PDC DBGU 33 6071A–ATARM–28-Oct-04 Application Examples Debug Environment Figure 11 on page 34 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. Figure 11. Application Debug Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector AT91SAM7Sxx RS232 Connector Terminal AT91SAM7Sxx-based Application Board 34 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Test Environment Figure 12 on page 35 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 12. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91SAM7Sxx Chip 1 AT91SAM7Sxx-based Application Board In Test Debug and Test Pin Description Table 9. Debug and Test Pin List Pin Name Function Reset/Test NRST TST Microcontroller Reset Test Mode Select ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Input Input Output Input Input Input/Output Input Low High Type Active Level 35 6071A–ATARM–28-Oct-04 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. The ARM7TDMI embedded In-circuit Emulator is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is examined through an ICE/JTAG port. The ARM7TDMI processor contains hardware extensions for advanced debugging features: • In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system. In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor. Embedded Incircuit Emulator • There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B). Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. The Debug Unit can be used to upload an application into the internal SRAM. It is activated by the boot program when no valid application is detected. The protocol used to load the application is XMODEM. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM7S32 Debug Unit Chip ID value is 0x27080340 on 32-bit width. For further details on the Debug Unit, see“Debug Unit (DBGU)” on page 173. IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. 36 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 96 bits that correspond to active pins and associated control signals. Each AT91SAM7S32 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 10. AT91SAM7S32 JTAG Boundary Scan Register Bit Number 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 PA13/PGMD1 IN/OUT PA14/PGMD2 IN/OUT PA15/PGM3 IN/OUT PA16/PGMD4 IN/OUT PA20/PGMD8/AD3 IN/OUT PA19/PGMD7/AD2 IN/OUT INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL internal PA18/PGMD6/AD1 IN/OUT PA17/PGMD5/AD0 IN/OUT Pin Name Pin Type Associated BSR Cells INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL 37 6071A–ATARM–28-Oct-04 Table 10. AT91SAM7S32 JTAG Boundary Scan Register (Continued) 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 PA4/PGMNCMD IN/OUT PA5/PGMRDY IN/OUT PA6/PGMNOE IN/OUT PA7/PGMNVALID IN/OUT PA8/PGMM0 IN/OUT PA9/PGMM1 IN/OUT PA10/PGMM2 IN/OUT PA11/PGMM3 IN/OUT PA12/PGMD0 IN/OUT INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL internal internal internal 38 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Table 10. AT91SAM7S32 JTAG Boundary Scan Register (Continued) 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERASE IN INPUT internal internal internal PA0/PGMEN0 IN/OUT PA1/PGMEN1 IN/OUT PA2 IN/OUT PA3 IN/OUT INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL internal internal internal internal 39 6071A–ATARM–28-Oct-04 ID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 VERSION[31:28]: Product Version Number Set to 0x1. PART NUMBER[27:12]: Product Part Number Set to 0x5B07. MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 05B0_703F. 40 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Reset Controller (RSTC) Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. A brownout detection is also available to prevent the processor from falling into an unpredictable state. Block Diagram Figure 13. Reset Controller Block Diagram Reset Controller bod_rst_en brown_out Brownout Manager bod_reset Main Supply POR Startup Counter Reset State Manager rstc_irq proc_nreset user_reset NRST nrst_out NRST Manager exter_nreset periph_nreset WDRPROC wd_fault SLCK 41 6071A–ATARM–28-Oct-04 Functional Description The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • • • proc_nreset: Processor reset line. It also resets the Watchdog Timer. periph_nreset: Affects the whole set of embedded peripherals. nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14 shows the block diagram of the NRST Manager. Figure 14. NRST Manager RSTC_MR RSTC_SR URSTIEN rstc_irq RSTC_MR URSTS NRSTL Other interrupt sources user_reset URSTEN NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) S low Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. 42 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. Brownout Manager Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal. The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read. The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR. At factory, the brownout reset is disabled. Figure 15. Brownout Manager bod_rst_en bod_reset RSTC_MR BODIEN RSTC_SR brown_out BODSTS Other interrupt sources rstc_irq 43 6071A–ATARM–28-Oct-04 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the device. The startup time, as shown in Figure 16, is hardcoded to comply with the Slow Clock Oscillator startup time. After the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset. When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately. Power-up Reset Figure 16. Power-up Reset SLCK MCK Any Freq. Main Supply POR output Startup Time proc_nreset periph_nreset Processor Startup = 3 cycles NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles 44 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. Th e NR ST Man age r gua rante es th at the NR ST line is asser te d for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 17. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset NRST (nrst_out) >= EXTERNAL RESET LENGTH 45 6071A–ATARM–28-Oct-04 Brownout Reset When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted. The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered. When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset. Figure 18. Brownout Reset State SLCK MCK brown_out or bod_reset Any Freq. Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x5 = Brownout Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 46 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). • The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 19. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 47 6071A–ATARM–28-Oct-04 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. If WDRPROC = 1, only the processor reset is asserted. • The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 20. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 48 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • • • • • • Power-up Reset Brownout Reset Watchdog Reset Software Reset User Reset When in User Reset: – – • – – • – – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. A software reset is impossible, since the processor reset is being activated. A watchdog event has priority over the current state. The NRST has no effect. The processor reset is active and so a Software Reset cannot be programmed. A User Reset cannot be entered. Particular cases are listed below: When in Software Reset: When in Watchdog Reset: Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 21). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt. • • • 49 6071A–ATARM–28-Oct-04 Figure 21. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 50 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Reset Controller (RSTC) User Interface Table 11. Reset Controller Registers Offset 0x00 0x04 0x08 Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0000 0x0000_0000 51 6071A–ATARM–28-Oct-04 Reset Controller Control Register Register Name: RSTC_CR Access Type: 31 Write-only 30 29 28 KEY 27 26 25 24 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 – 19 – 11 – 3 EXTRST 18 – 10 – 2 PERRST 17 – 9 – 1 – 16 – 8 – 0 PROCRST • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 52 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Reset Controller Status Register Register Name: RSTC_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 25 – 17 SRCMP 9 RSTTYP 1 BODSTS 24 – 16 NRSTL 8 2 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • BODSTS: Brownout Detection Status 0 = No brownout high-to-low transition happened since the last read of RSTC_SR. 1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 1 1 0 1 1 0 0 0 0 1 0 1 Reset Type Power-up Reset Watchdog Reset Software Reset User Reset Brownout Reset Comments VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low BrownOut reset occurred • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 53 6071A–ATARM–28-Oct-04 Reset Controller Mode Register Register Name: RSTC_MR Access Type: 31 Read/Write 30 29 28 KEY 27 26 25 24 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 URSTIEN 19 – 11 18 – 10 ERSTL 17 – 9 16 BODIEN 8 3 – 2 – 1 – 0 URSTEN • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • BODIEN: Brownout Detection Interrupt Enable 0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2 (ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 54 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Real-time Timer (RTT) Overview Block Diagram Figure 22. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value. 55 6071A–ATARM–28-Oct-04 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is reached by writing RTPRES at 1. In this case, the period of the signal provided to the Real-time Timer counter is 30.52 µs (when Slow Clock is 32.768 Hz) and the maximum the Real-time Timer can cover is 131072 seconds, corresponding to more than 36 days. The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm reg ister is se t to its ma ximum value, co rrespo nding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 56 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Figure 23. RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 57 6071A–ATARM–28-Oct-04 Real-time Timer (RTT) User Interface Table 12. Real-time Timer Register Mapping Offset 0x00 0x04 0x08 0x0C Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 58 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Real-time Timer Mode Register Register Name: RTT_MR Access Type: 31 – 23 – 15 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RTPRES 27 – 19 – 11 26 – 18 RTTRST 10 25 – 17 RTTINCIEN 9 24 – 16 ALMIEN 8 7 6 5 4 RTPRES 3 2 1 0 • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows: RTPRES = 0: The Prescaler Period is equal to 216 RTPRES ≠ 0: The Prescaler Period is equal to RTPRES. • ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 59 6071A–ATARM–28-Oct-04 Real-time Timer Alarm Register Register Name: RTT_AR Access Type: 31 Read/Write 30 29 28 ALMV 27 26 25 24 23 22 21 20 ALMV 19 18 17 16 15 14 13 12 ALMV 11 10 9 8 7 6 5 4 ALMV 3 2 1 0 • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 60 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Real-time Timer Value Register Register Name: RTT_VR Access Type: 31 Read-only 30 29 28 CRTV 27 26 25 24 23 22 21 20 CRTV 19 18 17 16 15 14 13 12 CRTV 11 10 9 8 7 6 5 4 CRTV 3 2 1 0 • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 61 6071A–ATARM–28-Oct-04 Real-time Timer Status Register Register Name: RTT_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 RTTINC 24 – 16 – 8 – 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 62 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Periodic Interval Timer (PIT) Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. Block Diagram Figure 24. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset pit_irq 0 0 1 0 1 12-bit Adder read PIT_PIVR MCK 20-bit Counter Prescaler MCK/16 CPIV PIT_PIVR PICNT CPIV PIT_PIIR PICNT 63 6071A–ATARM–28-Oct-04 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 25 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. 64 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Figure 25. Enabling/Disabling PIT with PITEN APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle CPIV PICNT PITS (PIT_SR) APB Interface 0 1 0 PIV - 1 PIV 1 0 0 1 read PIT_PIVR 65 6071A–ATARM–28-Oct-04 Periodic Interval Timer (PIT) User Interface Table 13. Periodic Interval Timer (PIT) Register Mapping Offset 0x00 0x04 0x08 0x0C Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 66 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: 31 – 23 – 15 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 PIV 27 – 19 26 – 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16 7 6 5 4 PIV 3 2 1 0 • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 67 6071A–ATARM–28-Oct-04 Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 68 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: 31 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 69 6071A–ATARM–28-Oct-04 Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: 31 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 70 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Watchdog Timer (WDT) Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. Block Diagram Figure 26. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WV reload 1 0 WDRSTT 12-bit Down Counter WDT_MR reload WDD Current Value 1/128 SLCK 2.7V VDDIN = 3.3V VDDIN = 3.3V, in Idle Mode Conditions Min 3.0 1.81 Typ 3.3 1.85 90 100 20 150 100 1 Max 3.6 1.89 Units V V µA mA µA µS mA mA 406 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Table 85. Brownout Detector Characteristics Symbol VBOTVHYST IDD TSTART Parameter Threshold Level Hysteresis Current Consumption BOD off (GPNVM0 bit inactive) Startup Time 100 1 200 µA µs VHYST = VBOT+ - VBOTBOD on (GPNVM0 bit active) Conditions Min 1.65 Typ 1.68 50 12 Max 1.71 65 18 Units V mV µA 407 6071A–ATARM–28-Oct-04 Power Consumption • • • Typical power consumption of PLLs, Slow Clock and Main Oscillator. Power consumption of power supply in two different modes: Active and ultra Low-power. Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock. Power Consumption Versus Modes The values in Table 86 and Table 87 on page 410 are estimated values of the power consumption with operating conditions as follows: • • • • • VDDIO = VDDIN = VDDFLASH = 3.3V VDDCORE = VDDPLL = 1.85V TA = 25°C MCK = 50 MHz There is no consumption on the I/Os of the device Figure 171. Measure Schematics: VDDFLASH VDDIO 3.3V AMP1 VDDIN Voltage Regulator VDDOUT 1.8V AMP2 VDDCORE VDDPLL 408 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary These figures represent the power consumption estimated on the power supplies.. Table 86. Power Consumption for Different Modes Mode Active Conditions Voltage regulator is on. Brown Out Detector is activated. Flash is read. ARM Core clock is 50MHz. Analog-to-Digital Converter activated. All peripheral clocks activated. onto AMP1 onto AMP2 Ultra low power Voltage regulator is in Low-power mode. Brown Out Detector is de-activated. Flash is in standby mode. ARM Core clock is 500Hz. Analog-to-Digital Converter de-activated. All peripheral clocks de-activated. onto AMP1 onto AMP2 31.3 29.3 mA Consumption Unit 36.2 35.2 µA 409 6071A–ATARM–28-Oct-04 Peripheral Power Consumption in Active Mode Table 87. Power Consumption by Peripheral Peripheral PIO Controller USART ADC PWM TWI SPI SSC Timer Counter Channels Consumption 0.4 0.9 0.7 0.3 mA 0.2 0.9 1.1 0.2 Unit 410 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Power Consumption versus Master Clock Frequency in Active Mode Figure 172 produces estimated values with operating conditions as follows: • • • • • • • • • • VDDIO = VDDIN = VDDFLASH = 3.3V VDDCORE = VDDPLL = 1.85V TA = 25°C MCK in the MHz range Voltage regulator is on Brown-out Detector is activated Flash is read Analog-to-Digital Converter activated All peripheral clocks activated There is no consumption on the I/Os of the device Figure 172 presents the power consumption estimated on the power supply. Figure 172. Power Consumption versus MCK Frequency in Active Mode Current Consumption at 3.3V 100,000 31,278 16,219 8,685 4,918 1,622 2,063 3,035 1,000 10,000 Consumption (µA) 100 0.78125 1.5625 3.125 6.25 12.5 25 50 Frequency (MHz) 411 6071A–ATARM–28-Oct-04 Power Consumption versus Master Clock Frequency in Ultra Low-power Mode Figure 173 produces estimated values with operating conditions as follows: • • • • • • • • • • • VDDIO = VDDIN = VDDFLASH = 3.3V VDDCORE = VDDPLL = 1.85V TA = 25°C Voltage regulator is in Low-power mode Brown Out Detector is de-activated Flash is in standby mode Analog-to-digital Converter de-activated All peripheral clocks de-activated PLL in standby Main oscillator in standby There is no consumption on the I/Os of the device Figure 173 presents the power consumption estimated on the power supply. Figure 173. Power Consumption versus MCK Frequency in the Ultra Low Power Mode Current Consumption at 3.3V 100 35.2 35.3 35.7 36.4 37.7 40.5 46 10 0.5 1 2 4 Frequency (KHz) 8 16 32 412 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 Consumption (µA) AT91SAM7S32 Preliminary Crystal Oscillators Characteristics RC Oscillator Characteristics Table 88. RC Oscillator Characteristics Symbol 1/(t CPRC) Parameter RC Oscillator Frequency Duty Cycle tST IOSC Startup Time Current Consumption VDDPLL = 1.65V After Startup Time Conditions VDDPLL = 1.65V Min 22 45 Typ 32 50 Max 42 55 75 1.9 Unit KHz % µs µA Main Oscillator Characteristics Table 89. Main Oscillator Characteristics Symbol 1/(t CPMAIN) CL1, CL2 CL Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2 ) Equivalent Load Capacitance Duty Cycle tST Startup Time VDDPLL = 1.2 to 2V CS = 3 pF(1) 1/(tCPMAIN) = 3 MHz CS = 7 pF(1) 1/(tCPMAIN) = 16 MHz CS = 7 pF(1) 1/(tCPMAIN) = 20 MHz Active mode Standby mode Notes: 1. CS is the shunt capacitance 40 Conditions Min 3 Typ 16 25 12.5 50 60 14.5 1.4 1 550 1 Max 20 Unit MHz pF pF % ms IOSC Current Consumption µA µA XIN Clock Characteristics Table 90. XIN Clock Electrical Characteristics Symbol 1/(t CPXIN) tCPXIN tCHXIN tCLXIN CIN RIN Note: Parameter XIN Clock Frequency XIN Clock Period XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance XIN Pull-down Resistor (1) (1) Conditions Min Max 50.0 Units MHz ns 20.0 0.4 x tCPXIN 0.4 x tCPXIN 0.6 x tCPXIN 0.6 x tCPXIN 25 500 pF kΩ 1. These characteristics apply only when the Main Oscillator is in bypass mode (i.e., when MOSCEN = 0 and OSCBYPASS = 1 in the CKGR_MOR register, see “PMC Clock Generator Main Oscillator Register” on page 166). 413 6071A–ATARM–28-Oct-04 PLL Characteristics Table 91. Phase Lock Loop Characteristics Symbol FOUT FIN IPLL Parameter Output Frequency Input Frequency Current Consumption Active mode Standby mode Note: Startup time depends on PLL RC filter. A calculation tool is provided by Atmel. Conditions 00 Field out of CKGR_PLL is: 10 150 1 220 32 4 1 MHz MHz mA µA Min 80 Typ Max 160 Unit MHz 414 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary ADC Characteristics Table 92. Channel Conversion Time and ADC CLock Parameter ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Throughput Rate ADC Clock = 5 MHz ADC Clock = 5 MHz Return from Idle Mode 600 2 384 Conditions Min Typ Max 5 20 Units MHz µs ns µs kSPS Table 93. External Voltage Reference Input Conditions Parameter ADVREF Input Voltage Range ADVREF Average Current On 13 samples with ADC Clock = 5 MHz Min 2.6 12 Max VDDIN 250 Units V µA Table 94. Analog Inputs Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 1 12 14 Typ Max VADVREF µA pF Units Table 95. Transfer Characteristics Parameter Resolution Integral Non-linearity ADC Clock = 5 MHz Differential Non-linearity ADC Clock = 5 MHz Offset Error Gain Error ±2 ±2 ±2 LSB LSB LSB ±3 ±1 LSB LSB Conditions Min Typ 10 ±2 Max Units Bit LSB 415 6071A–ATARM–28-Oct-04 AT91SAM7S32 AC Characteristics Applicable Conditions and Derating Data These conditions and derating process apply to the following paragraphs: Clock Characteristics, Embedded Flash Characteristics and JTAG/ICE Timings. Conditions and Timings Computation All delays are given as typical values under the following conditions: • • • • • • VDDIO = 3.3V VDDCORE = 1.8V Ambient Temperature = 25°C Load Capacitance = 0 pF The output level change detection is (0.5 x VDDIO). The input level is 0.8V for a low-level detection and is 2.0V for a high-level detection. The minimum and maximum values given in the AC characteristics tables of this datasheet take into account process variation and design. In order to obtain the timing for other conditions, the following equation should be used: where: • • • • • • δT° is the derating factor in temperature given in Figure 174 on page 417. δVDDCORE is the derating factor for the Core Power Supply given in Figure 175 on page 417. tDATASHEET is the minimum or maximum timing value given in this datasheet for a load capacitance of 0 pF. δVDDIO is the derating factor for the IO Power Supply given in Figure 176 on page 418. CSIGNAL is the capacitance load on the considered output pin(1). δCSIGNAL is the load derating factor depending on the capacitance load on the related output pins given in Min and Max in this datasheet. The user must take into account the package capacitance load contribution (CIN ) described in Table 83, “DC Characteristics,” on page 406. The input delays are given as typical values. Note: 416 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 ∑ t = δ T ° × ( ( δ VDDCORE × t DATASHEET ) + ( δ VDDIO × ( C SIGNAL × δ CSIGNAL ) ) ) AT91SAM7S32 Preliminary Temperature Derating Factor Figure 174. Derating Curve for Different Operating Temperatures 1,1 1,05 Derating Factor 1 0,95 0,9 0 ,85 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Operating Temperature (°C) VDDCORE Voltage Derating Factor Figure 175. Derating Curve for Different Core Supply Voltages 1,2 1,15 1,1 Derating Factor 1,05 1 0,95 0,9 0,85 0 ,8 1,65 1,7 1,75 1,8 Core Supply Voltage (V) 1,85 1,9 1,95 417 6071A–ATARM–28-Oct-04 VDDIO Voltage Derating Factor Figure 176. Derating Curve for Different IO Supply Voltages 1,15 1,1 Derating Factor 1,05 1 0,95 0,9 0,85 3 3,1 3,2 3,3 3,4 3,5 3,6 I/O Supply Voltage (V) Note: The derating factor in this example is applicable only to timings related to output pins. 418 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Clock Characteristics These parameters are given in the following conditions: • • VDDCORE = 1.8V Ambient Temperature = 25°C The Temperature Derating Factor described in “AT91SAM7S32 AC Characteristics” on page 416 and “VDDCORE Voltage Derating Factor” on page 417 are both applicable to these characteristics. Master Clock Characteristics Table 96. Master Clock Waveform Parameters Symbol 1/(t CPMCK) Parameter Master Clock Frequency Conditions Min Max 73 Units MHz 419 6071A–ATARM–28-Oct-04 Embedded Flash Characteristics Table 97. DC Flash Characteristics Symbol TPU ISB Parameter Power-up delay Standby current @85°C onto VDDCORE = 1.8V onto VDDFLASH = 3.3V Random Read @ 40MHz onto VDDCORE = 1.8V onto VDDFLASH = 3.3V ICC Active current Write onto VDDCORE = 1.8V onto VDDFLASH = 3.3V 500 8.0 µA mA Conditions Min Max 30 0 30 5.0 1.0 Units µS µA mA The maximum operating frequency is given in Table 97 but is limited by the Embedded Flash access time when the processor is fetching code out of it. Table 98 gives the device maximum operating frequency depending on the field FWS of the MC_FMR register. This field defines the number of wait states required to access the Embedded Flash Memory. Table 98. Embedded Flash Wait States FWS 0 1 2 3 Read Operations 1 cycle 2 cycles 3 cycles 4 cycles Maximum Operating Frequency (MHz) 40 1/(tCPMCK) 1/(tCPMCK) 1/(tCPMCK) Table 99. AC Flash Characteristics Parameter Program Cycle Time per page without auto-erase Full Chip Erase 10 2 ms ms Conditions per page including auto-erase Min Max 4 Units ms 420 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary JTAG/ICE Timings ICE Interface Signals Table 100 shows timings relative to operating condition limits defined in the section “Conditions and Timings Computation” on page 416. Table 100. ICE Interface Timing Specification Symbol ICE0 ICE1 ICE2 ICE3 ICE4 ICE5 Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS, Setup before TCK High TDI, TMS, Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid CTDO = 0 pF CTDO derating Conditions Min 51 51 102 3 0 3 0.037 13 0.037 Max Units ns ns ns ns ns ns ns/pF ns ns/pF ICE6 Figure 177. ICE Interface Signals ICE2 TCK ICE0 ICE1 TMS/TDI ICE3 ICE4 TDO ICE5 ICE6 421 6071A–ATARM–28-Oct-04 JTAG Interface Signals The following table shows timings relative to operating condition limits defined in the section “Conditions and Timings Computation” on page 416. Table 101. JTAG Interface Timing specification Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time CTDO = 0 pF CTDO derating TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time COUT = 0 pF COUT derating TCK to Device Outputs Valid COUT = 0 pF COUT derating CTDO = 0 pF CTDO derating 0 3 4 0.037 20 0.037 Conditions Min 6.5 5.5 12 2 3 2 0.037 15 0.037 Max Units ns ns ns ns ns ns ns/pF ns ns/pF ns ns ns ns/pF ns ns/pF JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 422 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Figure 178. JTAG Interface Signals JTAG2 TCK JTAG JTAG1 0 TMS/TDI JTAG3 JTAG4 TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8 Device Outputs JTAG9 JTAG10 423 6071A–ATARM–28-Oct-04 AT91SAM7S32 Mechanical Characteristics Thermal Considerations Thermal Data In Table 102, the device lifetime is estimated using the MIL-217 standard in the “moderately controlled” environmental model (this model is described as corresponding to an installation in a permanent rack with adequate cooling air), depending on the device Junction Temperature. (For details see the section “Junction Temperature” on page 425.) Note that the user must be extremely cautious with this MTBF calculation. It should be noted that the MIL-217 model is pessimistic with respect to observed values due to the way the data/models are obtained (test under severe conditions). The life test results that have been measured are always better than the predicted ones. Table 102. MTBF Versus Junction Temperature Junction Temperature (TJ) (°C) 100 125 150 175 Estimated Lifetime (MTBF) (Year) 17.5 9 5 3 Table 103 summarizes the thermal resistance data depending on the package. Table 103. Thermal Resistance Data Symbol θJA θJC Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Condition Still Air Package LQFP48 LQFP48 Typ 49.5 Unit °C/W 12.7 424 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Junction Temperature The average chip-junction temperature, TJ, in °C can be obtained from the following: 7. 8. T J = T A + ( P D × θ JA ) T J = T A + ( P D × ( θ HEATSINK + θ JC ) ) where: • • • θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 103 on page 424. θJC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 103 on page 424. θHEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet. • • PD = device power consumption (W) estimated from data provided in the section “Power Consumption” on page 408. TA = ambient temperature (°C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in °C. 425 6071A–ATARM–28-Oct-04 Package Drawings Figure 179. 48-lead LQFP Package Drawing 426 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Table 104. 48-lead LQFP Package Dimensions (in mm) Table 105. Device and 48-lead LQFP Package Maximum Weight 700 mg Table 106. 48-lead LQFP Package Characteristics Moisture Sensitivity Level 3 427 6071A–ATARM–28-Oct-04 Soldering Profile Table 107 gives the recommended soldering profile from J-STD-20. Table 107. Soldering Profile Convection or IR/Convection Average Ramp-up Rate (183°C to Peak) Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature 3°C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max 60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec. VPR 10°C/sec. Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C (IR reflow). Recommended package reflow conditions depend on package thickness and volume. See Table 108. Table 108. Recommended Package Reflow Conditions (1, 2, 3) Parameter Convection VPR IR/Convection Temperature 235 +5/-0°C 235 +5/-0°C 235 +5/-0°C When certain small thin packages are used on boards without larger packages, these small packages may be classified at 220°C instead of 235°C. Notes: 1. The packages are qualified by Atmel by using IR reflow conditions, not convection or VPR. 2. By default, the package level 1 is qualified at 220°C (unless 235°C is stipulated). 3. The body temperature is the most important parameter but other profile parameters such as total exposure time to hot temperature or heating rate may also influence component reliability. A maximum of three reflow passes is allowed per component. 428 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary AT91SAM7S32 Ordering Information Table 109. Ordering Information Ordering Code AT91SAM7S32-AI Package LQFP 48 Temperature Operating Range Industrial (-40°C to 85°C) 429 6071A–ATARM–28-Oct-04 430 AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Table of Contents Features............................................................................................................... 1 Description .......................................................................................................... 2 Block Diagram..................................................................................................... 3 Signal Description ............................................................................................ 4 Package and Pinout ......................................................................................... 7 48-lead LQFP Mechanical Overview................................................................ 7 Pinout ............................................................................................................... 7 Power Considerations........................................................................................ 8 Power Supplies ................................................................................................ 8 Power Consumption ......................................................................................... 8 Voltage Regulator ............................................................................................ 8 Typical Powering Schematics .......................................................................... 9 I/O Lines Considerations ................................................................................. 10 JTAG Port Pins .............................................................................................. 10 Test Pin .......................................................................................................... 10 Reset Pin........................................................................................................ 10 ERASE Pin ..................................................................................................... 10 PIO Controller Lines ....................................................................................... 10 I/O Line Drive Levels...................................................................................... 10 Processor and Architecture............................................................................. 11 ARM7TDMI Processor ................................................................................... 11 Debug and Test Features .............................................................................. 11 Memory Controller.......................................................................................... 11 Peripheral Data Controller.............................................................................. 12 Memories ........................................................................................................... 13 Memory Mapping ........................................................................................... 13 Embedded Flash ............................................................................................ 14 Fast Flash Programming Interface ................................................................. 15 System Controller............................................................................................. 16 System Controller Mapping ............................................................................ 17 Reset Controller ............................................................................................. 18 Clock Generator ............................................................................................. 19 Power Management Controller ...................................................................... 20 Advanced Interrupt Controller ........................................................................ 20 Debug Unit ..................................................................................................... 21 Periodic Interval Timer ................................................................................... 21 Watchdog Timer............................................................................................. 21 Real-time Timer.............................................................................................. 21 PIO Controller ................................................................................................ 21 Voltage Regulator Controller.......................................................................... 21 Peripherals ........................................................................................................ 22 Peripheral Mapping ........................................................................................ 22 Peripheral Multiplexing on PIO Lines ............................................................. 23 Peripheral Identifiers ...................................................................................... 24 Serial Peripheral Interface.............................................................................. 24 Two-wire Interface.......................................................................................... 25 i 6071A–ATARM–28-Oct-04 USART ........................................................................................................... Serial Synchronous Controller ....................................................................... Timer Counter ................................................................................................ PWM Controller .............................................................................................. Analog-to-digital Converter ............................................................................ 25 25 25 26 26 ARM7TDMI Processor Overview .................................................................. 27 Overview............................................................................................................ ARM7TDMI Processor ...................................................................................... Instruction Type.............................................................................................. Data Type....................................................................................................... ARM7TDMI Operating Mode.......................................................................... ARM7TDMI Registers .................................................................................... ARM Instruction Set Overview ....................................................................... Thumb Instruction Set Overview .................................................................... 27 28 28 28 28 28 30 31 AT91SAM7S32 Debug and Test Features ................................................... 33 Description ........................................................................................................ Block Diagram................................................................................................... Application Examples ...................................................................................... Debug Environment ....................................................................................... Test Environment ........................................................................................... Debug and Test Pin Description ..................................................................... Functional Description..................................................................................... Test Pin.............................................................................................................. Embedded In-circuit Emulator ........................................................................ Debug Unit ..................................................................................................... IEEE 1149.1 JTAG Boundary Scan ............................................................... ID Code Register............................................................................................ 33 33 34 34 35 35 36 36 36 36 36 40 Reset Controller (RSTC) ............................................................................... 41 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... NRST Manager .............................................................................................. Brownout Manager ......................................................................................... Reset States................................................................................................... Reset State Priorities ..................................................................................... Reset Controller Status Register.................................................................... Reset Controller (RSTC) User Interface.......................................................... Reset Controller Control Register .................................................................. Reset Controller Status Register.................................................................... Reset Controller Mode Register..................................................................... 41 41 42 42 43 44 49 49 51 52 53 54 ii AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Real-time Timer (RTT) ................................................................................... 55 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Real-time Timer (RTT) User Interface ............................................................. Real-time Timer Mode Register ..................................................................... Real-time Timer Alarm Register..................................................................... Real-time Timer Value Register ..................................................................... Real-time Timer Status Register .................................................................... 55 55 56 58 59 60 61 62 Periodic Interval Timer (PIT)......................................................................... 63 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Periodic Interval Timer (PIT) User Interface ................................................... Periodic Interval Timer Mode Register ........................................................... Periodic Interval Timer Status Register.......................................................... Periodic Interval Timer Value Register........................................................... Periodic Interval Timer Image Register .......................................................... 63 63 64 66 67 68 69 70 Watchdog Timer (WDT) ................................................................................. 71 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Watchdog Timer (WDT) User Interface ........................................................... Watchdog Timer Control Register .................................................................. Watchdog Timer Mode Register .................................................................... Watchdog Timer Status Register ................................................................... 71 71 72 74 75 76 77 Voltage Regulator Mode Controller (VREG)................................................ 79 Overview............................................................................................................ 79 Voltage Regulator Power Controller (VREG) User Interface ........................ 79 Voltage Regulator Mode Register .................................................................. 79 Memory Controller (MC)................................................................................ 81 Overview............................................................................................................ Block Diagram................................................................................................... Functional Description..................................................................................... Bus Arbiter ..................................................................................................... Address Decoder ........................................................................................... Remap Command .......................................................................................... Abort Status ................................................................................................... Embedded Flash Controller ........................................................................... Misalignment Detector ................................................................................... 81 81 82 82 82 83 84 84 84 iii 6071A–ATARM–28-Oct-04 Memory Controller (MC) User Interface .......................................................... MC Remap Control Register .......................................................................... MC Abort Status Register .............................................................................. MC Abort Address Status Register ................................................................ 85 86 87 88 Embedded Flash Controller (EFC) ............................................................... 89 Overview............................................................................................................ 89 Functional Description..................................................................................... 89 Embedded Flash Organization....................................................................... 89 Read Operations ............................................................................................ 91 Write Operations ............................................................................................ 93 Flash Commands ........................................................................................... 93 Embedded Flash Controller (EFC) User Interface ......................................... 98 MC Flash Mode Register ............................................................................... 99 MC Flash Command Register ...................................................................... 100 MC Flash Status Register ............................................................................ 102 Fast Flash Programming Interface (FFPI) ................................................. 103 Overview.......................................................................................................... Parallel Fast Flash Programming.................................................................. Device Configuration.................................................................................... Signal Names............................................................................................... Entering Programming Mode ....................................................................... Read Handshaking....................................................................................... Device Operations........................................................................................ Serial Fast Flash Programming..................................................................... Device Configuration.................................................................................... Entering Serial Programming Mode ............................................................. Read/Write Handshake ................................................................................ Device Operations........................................................................................ 103 104 104 105 106 107 108 112 112 113 113 114 Peripheral Data Controller (PDC) ............................................................... 117 Overview.......................................................................................................... Block Diagram................................................................................................. Functional Description................................................................................... Configuration................................................................................................ Memory Pointers .......................................................................................... Transfer Counters ........................................................................................ Data Transfers ............................................................................................. Priority of PDC Transfer Requests ............................................................... Peripheral Data Controller (PDC) User Interface ......................................... PDC Receive Pointer Register..................................................................... PDC Receive Counter Register ................................................................... PDC Transmit Pointer Register .................................................................... PDC Transmit Counter Register .................................................................. 117 117 118 118 118 118 119 119 120 121 121 122 122 iv AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary PDC Receive Next Pointer Register ............................................................ PDC Receive Next Counter Register ........................................................... PDC Transmit Next Pointer Register ........................................................... PDC Transmit Next Counter Register .......................................................... PDC Transfer Control Register .................................................................... PDC Transfer Status Register...................................................................... 123 123 124 124 125 126 Advanced Interrupt Controller (AIC) .......................................................... 127 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ AIC Detailed Block Diagram .......................................................................... I/O Line Description........................................................................................ Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Functional Description................................................................................... Interrupt Source Control............................................................................... Interrupt Latencies ....................................................................................... Normal Interrupt ........................................................................................... Fast Interrupt................................................................................................ Protect Mode................................................................................................ Spurious Interrupt......................................................................................... General Interrupt Mask ................................................................................ Advanced Interrupt Controller (AIC) User Interface .................................... Base Address............................................................................................... AIC Source Mode Register .......................................................................... AIC Source Vector Register ......................................................................... AIC Interrupt Vector Register ....................................................................... AIC FIQ Vector Register ...................................................................................... AIC Interrupt Status Register ....................................................................... AIC Interrupt Pending Register .................................................................... AIC Interrupt Mask Register ......................................................................... AIC Core Interrupt Status Register .............................................................. AIC Interrupt Enable Command Register..................................................... AIC Interrupt Disable Command Register .................................................... AIC Interrupt Clear Command Register ....................................................... AIC Interrupt Set Command Register .......................................................... AIC End of Interrupt Command Register ..................................................... AIC Spurious Interrupt Vector Register ........................................................ AIC Debug Control Register......................................................................... AIC Fast Forcing Enable Register................................................................ AIC Fast Forcing Disable Register ............................................................... AIC Fast Forcing Status Register................................................................. 127 127 127 128 128 128 128 128 128 130 130 132 133 135 138 139 139 140 140 141 142 142 143 144 144 145 145 146 146 147 147 148 148 149 149 150 150 v 6071A–ATARM–28-Oct-04 Clock Generator........................................................................................... 151 Description ...................................................................................................... Slow Clock RC Oscillator ............................................................................. Main Oscillator ............................................................................................. Divider and PLL Block .................................................................................. 151 151 151 153 Power Management Controller (PMC) ....................................................... 154 Description ................................................................................................... Master Clock Controller................................................................................ Processor Clock Controller .......................................................................... Peripheral Clock Controller .......................................................................... Programmable Clock Output Controller ....................................................... Programming Sequence .............................................................................. Clock Switching Details ................................................................................ Power Management Controller (PMC) User Interface ................................ 154 154 154 155 155 155 158 161 Debug Unit (DBGU) ..................................................................................... 173 Overview.......................................................................................................... Block Diagram................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Source ........................................................................................... UART Operations............................................................................................ Baud Rate Generator ................................................................................... Receiver ....................................................................................................... Transmitter ................................................................................................... Peripheral Data Controller............................................................................ Test Modes .................................................................................................. Debug Communication Channel Support..................................................... Chip Identifier ............................................................................................... ICE Access Prevention ................................................................................ Debug Unit User Interface ............................................................................. Debug Unit Control Register ........................................................................ Debug Unit Mode Register ........................................................................... Debug Unit Interrupt Enable Register .......................................................... Debug Unit Interrupt Disable Register ......................................................... Debug Unit Interrupt Mask Register ............................................................. Debug Unit Status Register.......................................................................... Debug Unit Receiver Holding Register ........................................................ Debug Unit Transmit Holding Register......................................................... Debug Unit Baud Rate Generator Register.................................................. Debug Unit Chip ID Register........................................................................ Debug Unit Chip ID Extension Register ....................................................... 173 174 175 175 175 175 175 175 176 178 179 179 180 181 181 182 183 184 185 186 187 188 190 191 191 192 195 vi AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Debug Unit Force NTRST Register.............................................................. 195 Parallel Input/Output Controller (PIO) ....................................................... 197 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Product Dependencies................................................................................... Pin Multiplexing ............................................................................................ External Interrupt Lines ................................................................................ Power Management ..................................................................................... Interrupt Generation ..................................................................................... Functional Description................................................................................... Pull-up Resistor Control ............................................................................... I/O Line or Peripheral Function Selection .................................................... Peripheral A or B Selection .......................................................................... Output Control.............................................................................................. Synchronous Data Output............................................................................ Multi Drive Control (Open Drain) .................................................................. Output Line Timings ..................................................................................... Inputs ........................................................................................................... Input Glitch Filtering ..................................................................................... Input Change Interrupt ................................................................................. I/O Lines Programming Example .................................................................. Parallel Input/Output Controller (PIO) User Interface.................................. PIO Controller PIO Enable Register............................................................. PIO Controller PIO Disable Register............................................................ PIO Controller PIO Status Register.............................................................. PIO Controller Output Enable Register ........................................................ PIO Controller Output Disable Register ....................................................... PIO Controller Output Status Register ......................................................... PIO Controller Input Filter Enable Register .................................................. PIO Controller Input Filter Disable Register ................................................. PIO Controller Input Filter Status Register................................................... PIO Controller Set Output Data Register ..................................................... PIO Controller Clear Output Data Register .................................................. PIO Controller Output Data Status Register ................................................ PIO Controller Pin Data Status Register ...................................................... PIO Controller Interrupt Enable Register ..................................................... PIO Controller Interrupt Disable Register..................................................... PIO Controller Interrupt Mask Register ........................................................ PIO Controller Interrupt Status Register ...................................................... PIO Multi-driver Enable Register.................................................................. PIO Multi-driver Disable Register................................................................. PIO Multi-driver Status Register................................................................... PIO Pull Up Disable Register ....................................................................... PIO Pull Up Enable Register........................................................................ 197 198 198 199 199 199 199 199 200 200 201 201 201 202 202 202 202 203 203 205 206 208 208 209 209 210 210 211 211 212 212 213 213 214 214 215 215 216 216 217 217 218 218 vii 6071A–ATARM–28-Oct-04 PIO Pull Up Status Register ......................................................................... PIO Peripheral A Select Register................................................................. PIO Peripheral B Select Register................................................................. PIO Peripheral A B Status Register ............................................................. PIO Output Write Enable Register ............................................................... PIO Output Write Disable Register .............................................................. PIO Output Write Status Register ................................................................ 219 219 220 220 221 221 222 Serial Peripheral Interface (SPI) ................................................................. 223 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Signal Description ......................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Modes of Operation...................................................................................... Data Transfer ............................................................................................... Master Mode Operations.............................................................................. SPI Slave Mode ........................................................................................... Serial Peripheral Interface (SPI) User Interface .......................................... SPI Control Register .................................................................................... SPI Mode Register ....................................................................................... SPI Receive Data Register .......................................................................... SPI Transmit Data Register ......................................................................... SPI Status Register...................................................................................... SPI Interrupt Enable Register ...................................................................... SPI Interrupt Disable Register...................................................................... SPI Interrupt Mask Register ......................................................................... SPI Chip Select Register.............................................................................. 223 224 224 225 225 225 225 225 226 226 226 228 233 235 236 237 239 240 241 243 244 245 246 Two-wire Interface (TWI) ............................................................................. 249 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Product Dependencies................................................................................... I/O Lines Description.................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Transfer Format ........................................................................................... Modes of Operation...................................................................................... Transmitting Data ......................................................................................... 249 249 249 250 250 250 250 251 251 251 251 viii AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary Read/Write Flowcharts................................................................................. Two-wire Interface (TWI) User Interface ...................................................... TWI Control Register.................................................................................... TWI Master Mode Register .......................................................................... TWI Internal Address Register ..................................................................... TWI Clock Waveform Generator Register.................................................... TWI Status Register ..................................................................................... TWI Interrupt Enable Register...................................................................... TWI Interrupt Disable Register..................................................................... TWI Interrupt Mask Register ........................................................................ TWI Receive Holding Register ..................................................................... TWI Transmit Holding Register .................................................................... 254 256 257 258 259 259 260 261 262 263 264 264 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 265 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ I/O Lines Description ..................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Baud Rate Generator ................................................................................... Receiver and Transmitter Control ................................................................ Synchronous and Asynchronous Modes...................................................... ISO7816 Mode ............................................................................................. IrDA Mode .................................................................................................... RS485 Mode ................................................................................................ Modem Mode ............................................................................................... Test Modes .................................................................................................. USART User Interface ................................................................................... USART Control Register .............................................................................. USART Mode Register................................................................................. USART Interrupt Enable Register ................................................................ USART Interrupt Disable Register ............................................................... USART Interrupt Mask Register................................................................... USART Channel Status Register ................................................................. USART Receive Holding Register ............................................................... USART Transmit Holding Register .............................................................. USART Baud Rate Generator Register ....................................................... USART Receiver Time-out Register ............................................................ USART Transmitter Timeguard Register ..................................................... USART FI DI RATIO Register ...................................................................... USART Number of Errors Register .............................................................. USART IrDA FILTER Register ..................................................................... 265 266 267 267 268 268 268 268 269 269 273 273 283 285 288 289 290 292 293 295 298 299 300 301 303 303 304 305 306 307 308 308 ix 6071A–ATARM–28-Oct-04 Synchronous Serial Controller (SSC)........................................................ 309 Overview.......................................................................................................... Block Diagram................................................................................................. Application Block Diagram ............................................................................ Pin Name List .................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... Clock Management ...................................................................................... Clock Divider ................................................................................................ Transmitter Operations ................................................................................ Receiver Operations .................................................................................... Start.............................................................................................................. Frame Sync.................................................................................................. Data Format ................................................................................................. Loop Mode ................................................................................................... Interrupt........................................................................................................ SSC Application Examples ............................................................................ Synchronous Serial Controller (SSC) User Interface ................................. SSC Control Register................................................................................... SSC Clock Mode Register ........................................................................... SSC Receive Clock Mode Register ............................................................. SSC Receive Frame Mode Register ............................................................ SSC Transmit Clock Mode Register ............................................................ SSC Transmit Frame Mode Register ........................................................... SSC Receive Holding Register .................................................................... SSC Transmit Holding Register ................................................................... SSC Receive Synchronization Holding Register.......................................... SSC Transmit Synchronization Holding Register......................................... SSC Status Register .................................................................................... SSC Interrupt Enable Register..................................................................... SSC Interrupt Disable Register .................................................................... SSC Interrupt Mask Register ....................................................................... 309 309 310 311 311 311 311 311 311 312 313 315 316 316 318 318 320 320 322 324 325 325 326 328 330 332 334 334 335 335 336 338 339 340 Timer/Counter (TC)...................................................................................... 341 Overview.......................................................................................................... Block Diagram................................................................................................. Pin Name List .................................................................................................. Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt........................................................................................................ Functional Description................................................................................... 341 341 342 342 342 342 342 342 x AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary TC Description ............................................................................................. Capture Operating Mode.............................................................................. Waveform Operating Mode .......................................................................... Timer/Counter (TC) User Interface ................................................................ Global Register Mapping ............................................................................. Channel Memory Mapping ........................................................................... TC Block Control Register............................................................................ TC Block Mode Register .............................................................................. TC Channel Control Register ....................................................................... TC Channel Mode Register: Capture Mode ................................................. TC Channel Mode Register: Waveform Mode ............................................. TC Counter Value Register .......................................................................... TC Register A............................................................................................... TC Register B............................................................................................... TC Register C .............................................................................................. TC Status Register ....................................................................................... TC Interrupt Enable Register ....................................................................... TC Interrupt Disable Register....................................................................... TC Interrupt Mask Register .......................................................................... 342 345 347 354 354 354 355 355 356 357 359 362 362 363 363 364 366 367 368 Pulse Width Modulation Controller (PWM) ............................................... 369 Overview.......................................................................................................... Block Diagram................................................................................................. I/O Lines Description...................................................................................... Product Dependencies................................................................................... I/O Lines....................................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Functional Description................................................................................... PWM Clock Generator ................................................................................. PWM Channel .............................................................................................. PWM Controller Operations ......................................................................... PWM User Interface ........................................................................................ PWM Register Mapping ............................................................................... PWM Mode Register .................................................................................... PWM Enable Register .................................................................................. PWM Disable Register ................................................................................. PWM Status Register................................................................................... PWM Interrupt Enable Register ................................................................... PWM Interrupt Disable Register................................................................... PWM Interrupt Mask Register ...................................................................... PWM Interrupt Status Register .................................................................... PWM Channel Mode Register...................................................................... PWM Channel Duty Cycle Register ............................................................. PWM Channel Period Register .................................................................... PWM Channel Counter Register .................................................................. 369 369 370 370 370 370 370 371 371 372 376 378 378 379 380 380 381 382 382 383 383 384 385 386 387 xi 6071A–ATARM–28-Oct-04 PWM Channel Update Register ................................................................... 387 PWM Version Register................................................................................. 388 Analog-to-digital Converter (ADC) ............................................................. 389 Overview.......................................................................................................... Block Diagram................................................................................................. Signal Description .......................................................................................... Product Dependencies................................................................................... Power Management ..................................................................................... Interrupt Sources.......................................................................................... Analog Inputs ............................................................................................... I/O Lines....................................................................................................... Timer Triggers .............................................................................................. Conversion Performances............................................................................ Functional Description................................................................................... Analog-to-digital Conversion ........................................................................ Conversion Reference ................................................................................. Conversion Resolution ................................................................................. Conversion Results ...................................................................................... Conversion Triggers ..................................................................................... Sleep Mode and Conversion Sequencer ..................................................... ADC Timings ................................................................................................ Analog-to-digital Converter (ADC) User Interface ....................................... ADC Control Register................................................................................... ADC Mode Register ..................................................................................... ADC Channel Enable Register..................................................................... ADC Channel Disable Register .................................................................... ADC Channel Status Register...................................................................... ADC Status Register .................................................................................... ADC Last Converted Data Register ............................................................. ADC Interrupt Enable Register..................................................................... ADC Interrupt Disable Register .................................................................... 389 389 390 390 390 390 390 390 390 390 391 391 391 391 391 393 394 394 395 396 397 399 399 400 401 402 403 404 AT91SAM7S32 Electrical Characteristics ................................................. 405 Absolute Maximum Ratings........................................................................... DC Characteristics.......................................................................................... Power Consumption....................................................................................... Power Consumption Versus Modes ............................................................. Peripheral Power Consumption in Active Mode ........................................... Power Consumption versus Master Clock Frequency in Active Mode......... Power Consumption versus Master Clock Frequency in Ultra Low-power Mode .................................................................................. Crystal Oscillators Characteristics ............................................................... RC Oscillator Characteristics ....................................................................... Main Oscillator Characteristics..................................................................... 405 406 408 408 410 411 412 413 413 413 xii AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 AT91SAM7S32 Preliminary XIN Clock Characteristics ............................................................................ 413 PLL Characteristics ........................................................................................ 414 ADC Characteristics ...................................................................................... 415 AT91SAM7S32 AC Characteristics ............................................................ 416 Applicable Conditions and Derating Data .................................................... Conditions and Timings Computation .......................................................... Temperature Derating Factor ....................................................................... VDDCORE Voltage Derating Factor ............................................................ VDDIO Voltage Derating Factor................................................................... Clock Characteristics ..................................................................................... Master Clock Characteristics ....................................................................... Embedded Flash Characteristics ................................................................. JTAG/ICE Timings .......................................................................................... ICE Interface Signals ................................................................................... JTAG Interface Signals ................................................................................ 416 416 417 417 418 419 419 420 421 421 422 AT91SAM7S32 Mechanical Characteristics .............................................. 424 Thermal Considerations................................................................................. Thermal Data ............................................................................................... Junction Temperature .................................................................................. Package Drawings .......................................................................................... Soldering Profile ............................................................................................. AT91SAM7S32 Ordering Information............................................................ 424 424 425 426 428 429 Table of Contents i Revision History .............................................................................................. xiv xiii 6071A–ATARM–28-Oct-04 Revision History Doc. Rev. 6071A Comments •Date: 28-Oct-04 xiv AT91SAM7S32 Preliminary 6071A–ATARM–28-Oct-04 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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