AT91SAM7X128

www.DataSheet4U.com Features • Incorporates the ARM7TDMI® ARM® Thumb® Processor – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Internal High-speed Flash – 512 Kbytes (AT91SAM7X512) Organized in Two Banks of 1024 Pages of 256 Bytes (Dual Plane) – 256 Kbytes (AT91SAM7X256) Organized in 1024 Pages of 256 Bytes (Single Plane) – 128 Kbytes (AT91SAM7X128) Organized in 512 Pages of 256 Bytes (Single Plane) – Single Cycle Access at Up to 30 MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms – 10,000 Write Cycles, 10-year Data Retention Capability, Sector Lock Capabilities, Flash Security Bit – Fast Flash Programming Interface for High Volume Production Internal High-speed SRAM, Single-cycle Access at Maximum Speed – 128 Kbytes (AT91SAM7X512) – 64 Kbytes (AT91SAM7X256) – 32 Kbytes (AT91SAM7X128) Memory Controller (MC) – Embedded Flash Controller, Abort Status and Misalignment Detection Reset Controller (RSTC) – Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout Detector – Provides External Reset Signal Shaping and Reset Source Status Clock Generator (CKGR) – Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL Power Management Controller (PMC) – Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and Idle Mode – Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel interrupt, Programmable ICE Access Prevention Periodic Interval Timer (PIT) – 20-bit Programmable Counter plus 12-bit Interval Counter Windowed Watchdog (WDT) – 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System – Counter May Be Stopped While the Processor is in Debug State or in Idle Mode Real-time Timer (RTT) – 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator • AT91 ARM Thumb-based Microcontrollers AT91SAM7X512 AT91SAM7X256 AT91SAM7X128 • • • Summary Preliminary • • • • • • NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. • 6120DS–ATARM–03-Oct-06 • Two Parallel Input/Output Controllers (PIO) – Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output Thirteen Peripheral DMA Controller (PDC) Channels One USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 1352-byte Configurable Integrated FIFOs One Ethernet MAC 10/100 base-T – Media Independent Interface (MII) or Reduced Media Independent Interface (RMII) – Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive One Part 2.0A and Part 2.0B Compliant CAN Controller – Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter One Synchronous Serial Controller (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Two Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Full Modem Line Support on USART1 Two Master/Slave Serial Peripheral Interfaces (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects One Three-channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit Power Width Modulation Controller (PWMC) One Two-wire Interface (TWI) – Master Mode Support Only, All Two-wire Atmel EEPROMs Supported One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os SAM-BA™ Boot Assistance – Default Boot program – Interface with SAM-BA Graphic User Interface IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins 5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each Power Supplies – Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components – 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions Available in 100-lead LQFP Green and 100-ball TFBGA Green Packages • • • • • • • • • • • • • • • • • 2 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 1. Description Atmel's AT91SAM7X512/256/128 is a member of a series of highly integrated Flash microcontrollers based on the 32-bit ARM RISC processor. It features 512/256/128 Kbyte high-speed Flash and 128/64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC and a CAN controller. A complete set of system functions minimizes the number of external components. The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality. The AT91SAM7X512/256/128 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator. By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of peripheral functions, including USART, SPI, CAN Controller, Ethernet MAC, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the AT91SAM7X512/256/128 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications requiring communication over, for example, Ethernet, CAN wired and Zigbee ™ w ireless networks. 1.1 Configuration Summary of the AT91SAM7X512/256/128 The AT91SAM7X512, AT91SAM7X256 and AT91SAM7X128 differ only in memory sizes. Table 1-1 summarizes the configurations of the three devices. Table 1-1. Device AT91SAM7X512 AT91SAM7X256 AT91SAM7X128 Configuration Summary Flash 512 Kbytes 256 Kbytes 128 Kbytes Flash Organization dual plane single plane single plane SRAM 128 Kbytes 64 Kbytes 32 Kbytes 3 6120DS–ATARM–03-Oct-06 2. AT91SAM7X512/256/128 Block Diagram Figure 2-1. TDI TDO TMS TCK JTAGSEL AT91SAM7X512/256/128 Block Diagram JTAG SCAN ICE ARM7TDMI Processor 1.8 V Voltage Regulator VDDIN GND VDDOUT VDDCORE TST FIQ System Controller AIC PIO IRQ0-IRQ1 Memory Controller PDC PDC VDDIO DRXD DTXD DBGU Embedded Flash Controllers Abort Status SRAM 128/64/32 Kbytes Address Decoder Misalignment Detection PCK0-PCK3 PLLRC XIN XOUT VDDFLASH PLL OSC RCOSC PMC Peripheral Bridge Flash 512/256/128 Kbytes ERASE VDDCORE VDDFLASH VDDCORE NRST BOD POR Reset Controller Peripheral DMA Controller 13 Channels ROM Fast Flash Programming Interface PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1 PIT APB WDT RTT PIOA RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 DCD1 DSR1 DTR1 RI1 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK ADTRG AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ADVREF SAM-BA DMA FIFO Ethernet MAC 10/100 PDC PIOB USART0 PDC PDC FIFO Transceiver ETXCK-ERXCK-EREFCK ETXEN-ETXER ECRS-ECOL, ECRSDV ERXER-ERXDV ERX0-ERX3 ETX0-ETX3 EMDC EMDIO EF100 VDDFLASH DDM DDP USART1 USB Device PIO PDC PDC PWMC PDC SPI0 PDC PDC SSC PDC Timer Counter SPI1 TC0 PDC PDC TC1 TC2 ADC TWI CAN PWM0 PWM1 PWM2 PWM3 TF TK TD RD RK RF TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK CANRX CANTX PIO 4 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 PIO AT91SAM7X512/256/128 Preliminary Summary 3. Signal Description Table 3-1. Signal Name Signal Description List Function Power Type Active Level Comments VDDIN VDDOUT VDDFLASH VDDIO VDDCORE VDDPLL GND Voltage Regulator and ADC Power Supply Input Voltage Regulator Output Flash and USB Power Supply I/O Lines Power Supply Core Power Supply PLL Ground Power Power Power Power Power Power Ground 3V to 3.6V 1.85V 3V to 3.6V 3V to 3.6V 1.65V to 1.95V 1.65V to 1.95V Clocks, Oscillators and PLLs XIN XOUT PLLRC PCK0 - PCK3 Main Oscillator Input Main Oscillator Output PLL Filter Programmable Clock Output Input Output Input Output ICE and JTAG TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Input Input Output Input Input Flash Memory ERASE Flash and NVM Configuration Bits Erase Command Reset/Test NRST TST Microcontroller Reset Test Mode Select Debug Unit DRXD DTXD Debug Receive Data Debug Transmit Data AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input PIO PA0 - PA30 PB0 - PB30 Parallel IO Controller A Parallel IO Controller B I/O I/O Pulled-up input at reset Pulled-up input at reset Input Input Input Output I/O Input Low High Pull-up resistor, Open Drain Output Pull-down resistor Input High Pull-down resistor No pull-up resistor. Pull-down resistor. No pull-up resistor No pull-up resistor. 5 6120DS–ATARM–03-Oct-06 Table 3-1. Signal Name Signal Description List (Continued) Function Type USB Device Port Active Level Comments DDM DDP USB Device Port Data USB Device Port Data + USART Analog Analog SCK0 - SCK1 TXD0 - TXD1 RXD0 - RXD1 RTS0 - RTS1 CTS0 - CTS1 DCD1 DTR1 DSR1 RI1 Serial Clock Transmit Data Receive Data Request To Send Clear To Send Data Carrier Detect Data Terminal Ready Data Set Ready Ring Indicator I/O I/O Input Output Input Input Output Input Input Synchronous Serial Controller TD RD TK RK TF RF Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync Output Input I/O I/O I/O I/O Timer/Counter TCLK0 - TCLK2 TIOA0 - TIOA2 TIOB0 - TIOB2 External Clock Inputs I/O Line A I/O Line B Input I/O I/O PWM Controller PWM0 - PWM3 PWM Channels Output Serial Peripheral Interface - SPIx SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1-NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select 1 to 3 I/O I/O I/O I/O Output Low Low Two-wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock I/O I/O 6 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary Table 3-1. Signal Name Signal Description List (Continued) Function Type Analog-to-Digital Converter Active Level Comments AD0-AD3 AD4-AD7 ADTRG ADVREF Analog Inputs Analog Inputs ADC Trigger ADC Reference Analog Analog Input Analog Fast Flash Programming Interface Digital pulled-up inputs at reset Analog Inputs PGMEN0-PGMEN1 PGMM0-PGMM3 PGMD0-PGMD15 PGMRDY PGMNVALID PGMNOE PGMCK PGMNCMD Programming Enabling Programming Mode Programming Data Programming Ready Data Direction Programming Read Programming Clock Programming Command Input Input I/O Output Output Input Input Input CAN Controller Low High Low Low CANRX CANTX CAN Input CAN Output Input Output Ethernet MAC 10/100 EREFCK ETXCK ERXCK ETXEN ETX0 - ETX3 ETXER ERXDV ECRSDV ERX0 - ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Reference Clock Transmit Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Carrier Sense and Data Valid Receive Data Receive Error Carrier Sense Collision Detected Management Data Clock Management Data Input/Output Force 100 Mbits/sec. Input Input Input Output Output Output Input Input Input Input Input Input Output I/O Output High RMII only MII only MII only ETX0 - ETX1 only in RMII MII only MII only RMII only ERX0 - ERX1 only in RMII MII only MII only RMII only 7 6120DS–ATARM–03-Oct-06 4. Package The AT91SAM7X512/256/128 is available in 100-lead LQFP Green and 100-ball TFBGA RoHScompliant packages. 4.1 100-lead LQFP Package Outline Figure 4-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical description is given in the Mechanical Characteristics section. Figure 4-1. 100-lead LQFP Package Outline (Top View) 75 76 51 50 100 1 25 26 8 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 4.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100-lead LQFP Pinout Pinout in 100-lead LQFP Package 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 PA18/PGMD6 PB9 PB8 PB14 PB13 PB6 GND VDDIO PB5 PB15 PB17 VDDCORE PB7 PB12 PB0 PB1 PB2 PB3 PB10 PB11 PA19/PGMD7 PA20/PGMD8 VDDIO PA21/PGMD9 PA22/PGMD10 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 TDI GND PB16 PB4 PA23/PGMD11 PA24/PGMD12 NRST TST PA25/PGMD13 PA26/PGMD14 VDDIO VDDCORE PB18 PB19 PB20 PB21 PB22 GND PB23 PB24 PB25 PB26 PA27/PGMD15 PA28 PA29 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 TDO JTAGSEL TMS TCK PA30 PA0/PGMEN0 PA1/PGMEN1 GND VDDIO PA3 PA2 VDDCORE PA4/PGMNCMD PA5/PGMRDY PA6/PGMNOE PA7/PGMNVALID ERASE DDM DDP VDDFLASH GND XIN/PGMCK XOUT PLLRC VDDPLL ADVREF GND AD4 AD5 AD6 AD7 VDDOUT VDDIN PB27/AD0 PB28/AD1 PB29/AD2 PB30/AD3 PA8/PGMM0 PA9/PGMM1 VDDCORE GND VDDIO PA10/PGMM2 PA11/PGMM3 PA12/PGMD0 PA13/PGMD1 PA14/PGMD2 PA15/PGMD3 PA16/PGMD4 PA17/PGMD5 Table 4-1. 9 6120DS–ATARM–03-Oct-06 4.3 100-ball TFBGA Package Outline Figure 4-2 shows the orientation of the 100-ball TFBGA package. A detailed mechanical description is given in the Mechanical Characteristics section of the full datasheet. Figure 4-2. 100-ball TFBGA Package Outline (Top View) TOP VIEW 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K BALL A1 4.4 Pin 100-ball TFBGA Pinout Signal Name Pin Signal Name Pin Signal Name Pin Signal Name Pinout in 100-ball TFBGA Package A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 PA22/PGMD10 PA21/PGMD9 PA20/PGMD8 PB1 PB7 PB5 PB8 PB9 PA18/PGMD6 VDDIO TDI PA19/PGMD7 PB11 PB2 PB12 PB15 PB14 PA14/PGMD2 PA16/PGMD4 PA17/PGMD5 PB16 PB4 PB10 PB3 PB0 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 PB17 PB13 PA13/PGMD1 PA12/PGMD0 PA15/PGMD3 PA23/PGMD11 PA24/PGMD12 NRST TST PB19 PB6 PA10/PGMM2 VDDIO PB27/AD0 PA11/PGMM3 PA25/PGMD13 PA26/PGMD14 PB18 PB20 TMS GND VDDIO PB28/AD1 VDDIO GND F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 PB21 PB23 PB25 PB26 TCK PA6/PGMNOE ERASE VDDCORE GND VDDIN PB22 PB24 PA27/PGMD15 TDO PA2 PA5/PGMRDY VDDCORE GND PB30/AD3 VDDOUT VDDCORE PA28 JTAGSEL PA3 PA4/PGMNCMD H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 PA7/PGMNVALID PA9/PGMM1 PA8/PGMM0 PB29/AD2 PLLRC PA29 PA30 PA0/PGMEN0 PA1/PGMEN1 VDDFLASH GND XIN/PGMCK XOUT GND VDDPLL VDDCORE VDDCORE DDP DDM GND AD7 AD6 AD5 AD4 ADVREF 10 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 5. Power Considerations 5.1 Power Supplies The AT91SAM7X512/256/128 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are: • VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V, 3.3V nominal. In order to decrease current consumption, if the voltage regulator and the ADC are not used, VDDIN, ADVREF, AD4, AD5, AD6 and AD7 should be connected to GND. In this case, VDDOUT should be left unconnected. • VDDOUT pin. It is the output of the 1.8V voltage regulator. • VDDIO pin. It powers the I/O lines; voltage ranges from 3.0V to 3.6V, 3.3V nominal. • VDDFLASH pin. It powers the USB transceivers and a part of the Flash and is required for the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal. • VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly. • VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the VDDOUT pin. No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane. 5.2 Power Consumption The AT91SAM7X512/256/128 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 28 µA static current. The dynamic power consumption on VDDCORE is less than 90 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA. 5.3 Voltage Regulator The AT91SAM7X512/256/128 embeds a voltage regulator that is managed by the System Controller. In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current. The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA static current and draws 1 mA of output current. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or 1 nF) NPO capacitor should be connected between VDDOUT and GND as close to the chip as possible. One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and GND. 11 6120DS–ATARM–03-Oct-06 Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R. 5.4 Typical Powering Schematics The AT91SAM7X512/256/128 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1 shows the power schematics to be used for USB bus-powered systems. Figure 5-1. 3.3V System Single Power Supply Schematic VDDFLASH Power Source ranges from 4.5V (USB) to 18V DC/DC Converter VDDIO VDDIN 3.3V VDDOUT Voltage Regulator VDDCORE VDDPLL 12 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 6. I/O Lines Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and are not 5-V tolerant. TMS, TDI and TCK do not integrate a pull-up resistor. TDO is an output, driven at up to VDDIO, and has no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. The JTAGSEL pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. 6.2 Test Pin The TST pin is used for manufacturing test or fast programming mode of the AT91SAM7X512/256/128 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied to low. Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results. 6.3 Reset Pin The NRST pin is bidirectional with an open drain output buffer. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the signal NRST to reset all the components of the system. The NRST pin integrates a permanent pull-up resistor to VDDIO. 6.4 ERASE Pin The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. This pin is debounced by the RC oscillator to improve the glitch tolerance. When the pin is tied to high during less than 100 ms, ERASE pin is not taken into account. The pin must be tied high during more than 220 ms to perform the re-initialization of the Flash. 6.5 PIO Controller Lines All the I/O lines, PA0 to PA30 and PB0 to PB30, are 5V-tolerant and all integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers. 5V-tolerant means that the I/O lines can drive voltage level according to VDDIO, but can be driven with a voltage of up to 5.5V. However, driving an I/O line with a voltage over VDDIO while the programmable pull-up resistor is enabled will create a current path through the pull-up resis- 13 6120DS–ATARM–03-Oct-06 tor from the I/O line to VDDIO. Care should be taken, in particular at reset, as all the I/O lines default to input with pull-up resistor enabled at reset. 6.6 I/O Lines Current Drawing The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently. The remaining I/O lines can draw only 8 mA. However, the total current drawn by all the I/O lines cannot exceed 200 mA. 14 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 7. Processor and Architecture 7.1 ARM7TDMI Processor • RISC processor based on ARMv4T Von Neumann architecture – Runs at up to 55 MHz, providing 0.9 MIPS/MHz • Two instruction sets – ARM high-performance 32-bit instruction set – Thumb high code density 16-bit instruction set • Three-stage pipeline architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) 7.2 Debug and Test Features • Integrated embedded in-circuit emulator – Two watchpoint units – Test access port accessible through a JTAG protocol – Debug communication channel • Debug Unit – Two-pin UART – Debug communication channel interrupt handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on all digital pins 7.3 Memory Controller • Programmable Bus Arbiter – Handles requests from the ARM7TDMI, the Ethernet MAC and the Peripheral DMA Controller • Address decoder provides selection signals for – Three internal 1 Mbyte memory areas – One 256 Mbyte embedded peripheral area • Abort Status Registers – Source, Type and all parameters of the access leading to an abort are saved – Facilitates debug by detection of bad pointers • Misalignment Detector – Alignment checking of all data accesses – Abort generation in case of misalignment • Remap Command – Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors 15 6120DS–ATARM–03-Oct-06 • Embedded Flash Controller – Embedded Flash interface, up to three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required wait states – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation 7.4 Peripheral DMA Controller • Handles data transfer between peripherals and memories • Thirteen channels – Two for each USART – Two for the Debug Unit – Two for the Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for the Analog-to-digital Converter • Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory • Next Pointer management for reducing interrupt latency requirements 16 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 8. Memories 8.1 AT91SAM7X512 • 512 Kbytes of dual-plane Flash Memory – 2 contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase: 3 ms – Full chip erase time: 15 ms – 10,000 write cycles, 10-year data retention capability – 32 lock bits, protecting 32 sectors of 64 pages – Protection Mode to secure contents of the Flash • 128 Kbytes of Fast SRAM – Single-cycle access at full speed 8.2 AT91SAM7X256 • 256 Kbytes of Flash Memory – 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase: 3 ms – Full chip erase time: 15 ms – 10,000 write cycles, 10-year data retention capability – 16 lock bits, each protecting 16 sectors of 64 pages – Protection Mode to secure contents of the Flash • 64 Kbytes of Fast SRAM – Single-cycle access at full speed 8.3 AT91SAM7X128 • 128 Kbytes of Flash Memory – 512 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase: 3 ms – Full chip erase time: 15 ms – 10,000 write cycles, 10-year data retention capability – 8 lock bits, each protecting 8 sectors of 64 pages – Protection Mode to secure contents of the Flash • 32 Kbytes of Fast SRAM – Single-cycle access at full speed 17 6120DS–ATARM–03-Oct-06 Figure 8-1. AT91SAM7X512/256/128 Memory Mapping Internal Memory Mapping 0x0000 0000 Note: (1) Can be ROM, Flash or SRAM depending on GPNVM2 and REMAP Boot Memory (1) Flash before Remap SRAM after Remap 1 MBytes 0x000F FFF 0x0010 0000 Internal Flash 0x001F FFF 0x0020 0000 1 MBytes Internal SRAM 0x002F FFF 0x0030 0000 1 MBytes Address Memory Space 0x0000 0000 0x003F FFF 0x0040 0000 Internal ROM 1 MBytes Internal Memories 256 MBytes Reserved 252 MBytes 0x0FFF FFFF 0x1000 0000 0x0FFF FFFF System Controller Mapping 0xFFFF F000 AIC 0xFFFF F1FF 0xFFFF F200 DBGU 0xFFFF F3FF 0xFFFF F400 PIOA 16 Kbytes 0xFFFF F5FF 0xFFFF F600 PIOB TWI Reserved USART0 USART1 Reserved PWMC CAN SSC ADC EMAC SPI0 SPI1 Reserved 0xFFFF EFFF 0xFFFF F000 0xFFFF FFFF SYSC 0xFFFF FFFF 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 16 Kbytes 0xFFFF FD60 0xFFFF FC6F 0xFFFF FD70 0xFFFF FEFF 0xFFFF FF00 VREG Reserved MC 256 Bytes/64 registers 4 Bytes/1 register 16 Kbytes 16 Kbytes 0xFFFF FCFF 0xFFFF FD00 0xFFFF FD0F 16 Kbytes 0xFFFF F7FF 0xFFFF F800 Reserved 0xFFFF FBFF 0xFFFF FC00 PMC 256 Bytes/64 registers 512 Bytes/128 registers 512 Bytes/128 registers 512 Bytes/128 registers 512 Bytes/128 registers Peripheral Mapping 0xF000 0000 Reserved 0xFFF9 FFFF 0xFFFA 0000 0xFFFA 3FFF 0xFFFA 4000 0xFFFA FFFF 0xFFFB 0000 0xFFFB 3FFF 0xFFFB 4000 Reserved 0xFFFB 7FFF 0xFFFB 8000 0xFFFB BFFF 0xFFFB C000 0xEFFF FFFF Undefined (Abort) 14 x 256 MBytes 3,584 MBytes TC0, TC1, TC2 Reserved UDP 16 Kbytes 0xF000 0000 0xFFFB FFFF 0xFFFC 0000 0xFFFC 3FFF 0xFFFC 4000 Internal Peripherals 256 MBytes 0xFFFC 7FFF 0xFFFC 8000 0xFFFC BFFF 0xFFFC C000 RSTC Reserved 16 Bytes/4 registers 0xFFFF FFFF 0xFFFC FFFF 0xFFFD 0000 0xFFFD 3FFF 0xFFFD 4000 0xFFFD 7FFF 0xFFFD 8000 0xFFFD BFFF 0xFFFD C000 0xFFFD FFFF 0xFFFE 0000 0xFFFE 3FFF 0xFFFE 4000 0xFFFE 7FFF 0xFFFE 8000 0xFFFF FD20 0xFFFF FC2F 0xFFFF FD30 0xFFFF FC3F 0xFFFF FD40 0xFFFF FD4F RTT PIT WDT Reserved 16 Bytes/4 registers 16 Bytes/4 registers 16 Bytes/4 registers 18 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 8.4 8.4.1 Memory Mapping Internal SRAM • The AT91SAM7X512 embeds a high-speed 128 Kbyte SRAM bank. • The AT91SAM7X256 embeds a high-speed 64 Kbyte SRAM bank. • The AT91SAM7X128 embeds a high-speed 32 Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0. 8.4.2 Internal ROM The AT91SAM7X512/256/128 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA program. 8.4.3 Internal Flash • The AT91SAM7X512 features two banks (dual plane) of 256 Kbytes of Flash. • The AT91SAM7X256 features one bank (single plane) of 256 Kbytes of Flash. • The AT91SAM7X128 features one bank (single plane) of 128 Kbytes of Flash. At any time, the Flash is mapped to address 0x0010 0000. It is also accessible at address 0x0 after the reset, if GPNVM bit 2 is cleared and before the Remap Command. A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash. This GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface. Setting the GPNVM Bit 2 selects the boot from the Flash. Asserting ERASE clears the GPNVM Bit 2 and thus selects the boot from the ROM by default. Figure 8-2. Internal Memory Mapping with GPNVM Bit 2 = 0 (default) 0x0000 0000 0x000F FFFF ROM Before Remap SRAM After Remap Internal FLASH 1 M Bytes 0x0010 0000 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 Internal SRAM 1 M Bytes 1 M Bytes 252 M Bytes Internal ROM 0x003F FFFF 0x0040 0000 Undefined Areas (Abort) 0x0FFF FFFF 19 6120DS–ATARM–03-Oct-06 Figure 8-3. Internal Memory Mapping with GPNVM Bit 2 = 1 0x0000 0000 0x000F FFFF Flash Before Remap SRAM After Remap Internal FLASH 1 M Bytes 0x0010 0000 1 M Bytes 0x001F FFFF 0x0020 0000 256M Bytes 0x002F FFFF 0x0030 0000 Internal SRAM 1 M Bytes 1 M Bytes 252 M Bytes Internal ROM 0x003F FFFF 0x0040 0000 Undefined Areas (Abort) 0x0FFF FFFF 8.5 8.5.1 Embedded Flash Flash Overview • The Flash of the AT91SAM7X512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. The 524,288 bytes are organized in 32-bit words. • The Flash of the AT91SAM7X256 is organized in 1024 pages of 256 bytes (single plane). It reads as 65,536 32-bit words. • The Flash of the AT91SAM7X128 is organized in 512 pages of 256 bytes (single plane). It reads as 32,768 32-bit words. The Flash contains a 256-byte write buffer, accessible through a 32-bit interface. The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions. When Flash is not used (read or write access), it is automatically placed into standby mode. 8.5.2 Embedded Flash Controller The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows: • programming of the access parameters of the Flash (number of wait states, timings, etc.) • starting commands such as full erase, page erase, page program, NVM bit set, NVM bit clear, etc. • getting the end status of the last command • getting error status • programming interrupts on the end of the last commands or on errors The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode. Two EFCs are embedded in the AT91SAM7X512 to control each bank of 256 KBytes. Dualplane organization allows concurrent read and program functionality. Read from one memory 20 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary plane may be performed even while program or erase functions are being executed in the other memory plane. One EFC is embedded in the AT91SAM7X256/128 to control the single plane of 256/128 KBytes. 8.5.3 8.5.3.1 Lock Regions AT91SAM7X512 Two Embedded Flash Controllers each manage 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 32 NVM bits are software programmable through both of the EFC User Interfaces. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.5.3.2 AT91SAM7X256 The Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 16 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.5.3.3 AT91SAM7X128 The Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7X128 contains 8 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes. If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt. The 8 NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region. Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash. 8.5.4 Security Bit Feature The AT91SAM7X512/256/128 features a security bit, based on a specific NVM-Bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast 21 6120DS–ATARM–03-Oct-06 Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash. This security bit can only be enabled, through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted. It is important to note that the assertion of the ERASE pin should always be longer than 220 ms. As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application. 8.5.5 Non-volatile Brownout Detector Control Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state. These two GPNVM bits can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface. • GPNVM Bit 0 is used as a brownout detector enable bit. Setting the GPNVM Bit 0 enables the BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM Bit 0 and thus disables the brownout detector by default. • The GPNVM Bit 1 is used as a brownout reset enable signal for the reset controller. Setting the GPNVM Bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM Bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default. 8.5.6 Calibration Bits Eight NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits. 8.6 Fast Flash Programming Interface The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers. The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands. The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high. 8.7 SAM-BA Boot Assistant The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program insitu the on-chip Flash memory. The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port. • Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection. 22 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary • Communication via the USB Device Port is limited to an 18.432 MHz crystal. The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI). The SAM-BA Boot is in ROM and is mapped at address 0x0 when the GPNVM Bit 2 is set to 0. When GPNVM bit 2 is set to 1, the device boots from the Flash. When GPNVM bit 2 is set to 0, the device boots from ROM (SAM-BA). 23 6120DS–ATARM–03-Oct-06 9. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF. Figure 9-1 on page 25 shows the System Controller Block Diagram. Figure 8-1 on page 18 shows the mapping of the User Interface of the System Controller peripherals. Note that the Memory Controller configuration user interface is also mapped within this address space. 24 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary Figure 9-1. System Controller Block Diagram System Controller jtag_nreset Boundary Scan TAP Controller irq0-irq1 fiq periph_irq[2..19] nirq Advanced Interrupt Controller int nfiq proc_nreset PCK debug ARM7TDMI pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq efc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK periph_nreset SLCK debug idle proc_nreset cal gpnvm[0] en gpnvm[1] flash_wrdis power_on_reset jtag_nreset bod_rst_en dbgu_irq force_ntrst dbgu_txd power_on_reset force_ntrst Debug Unit security_bit Periodic Interval Timer Real-Time Timer Watchdog Timer wdt_fault WDRPROC pit_irq flash_poe rtt_irq flash_wrdis cal wdt_irq gpnvm[0..2] Embedded Flash efc_irq MCK proc_nreset BOD Memory Controller POR flash_poe Reset Controller periph_nreset proc_nreset NRST SLCK rstc_irq Voltage Regulator Mode Controller standby Voltage Regulator cal RCOSC XIN SLCK periph_clk[2..18] pck[0-3] UDPCK periph_clk[11] periph_nreset periph_irq[11] usb_suspend OSC XOUT MAINCK Power Management Controller PCK UDPCK MCK USB Device Port PLLRC PLL PLLCK pmc_irq int idle periph_clk[4..19] periph_nreset periph_nreset usb_suspend periph_nreset periph_clk[2-3] dbgu_rxd periph_irq{2-3] irq0-irq1 Embedded Peripherals periph_irq[4..19] PIO Controller fiq dbgu_txd in PA0-PA30 PB0-PB30 out enable 25 6120DS–ATARM–03-Oct-06 9.1 Reset Controller • Based on one power-on reset cell and one brownout detector • Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog Reset, Brownout Reset • Controls the internal resets and the NRST pin output • Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets any requirement. 9.1.1 Brownout Detector and Power-on Reset The AT91SAM7X512/256/128 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE. Both signals are provided to the Flash to prevent any code corruption during power-up or powerdown sequences or if brownouts occur on the power supplies. The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device. The brownout detector monitors the VDDCORE and VDDFLASH levels during operation by comparing them to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE or VDDFLASH. When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot18-, defined as Vbot18 - hyst/2), the brownout output is immediately activated. When VDDCORE increases above the trigger level (Vbot18+, defined as Vbot18 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs. The VDDCORE threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated. When the brownout detector is enabled and VDDFLASH decreases to a value below the trigger level (Vbot33-, defined as Vbot33 - hyst/2), the brownout output is immediately activated. When VDDFLASH increases above the trigger level (Vbot33+, defined as Vbot33 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs. The VDDFLASH threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 2.80V with an accuracy of ± 3.5% and is factory calibrated. The brownout detector is low-power, as it consumes less than 28 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash. 26 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 9.2 Clock Generator The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics: • RC Oscillator ranges between 22 KHz and 42 KHz • Main Oscillator frequency ranges between 3 and 20 MHz • Main Oscillator can be bypassed • PLL output ranges between 80 and 200 MHz It provides SLCK, MAINCK and PLLCK. Figure 9-2. Clock Generator Block Diagram Clock Generator Embedded RC Oscillator Slow Clock SLCK XIN XOUT Main Oscillator Main Clock MAINCK PLLRC PLL and Divider PLL Clock PLLCK Status Control Power Management Controller 27 6120DS–ATARM–03-Oct-06 9.3 Power Management Controller The Power Management Controller uses the Clock Generator outputs to provide: • the Processor Clock PCK • the Master Clock MCK • the USB Clock UDPCK • all the peripheral clocks, independently controllable • four programmable clock outputs The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device. The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt. Figure 9-3. Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int periph_clk[2..18] Programmable Clock Controller SLCK MAINCK PLLCK Prescaler /1,/2,/4,...,/64 pck[0..3] USB Clock Controller ON/OFF PLLCK Divider /1,/2,/4 UDPCK 9.4 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor • Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) – Other sources control the peripheral interrupts or external interrupts – Programmable edge-triggered or level-sensitive internal sources – Programmable positive/negative edge-triggered or high/low level-sensitive external sources • 8-level Priority Controller – Drives the normal interrupt nIRQ of the processor – Handles priority of the interrupt sources 28 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes interrupt service routine branch and execution – One 32-bit vector register per interrupt source – Interrupt vector register reads the corresponding current interrupt vector • Protect Mode – Easy debugging by preventing automatic operations • Fast Forcing – Permits redirecting any interrupt source on the fast interrupt • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt 9.5 Debug Unit • Comprises: – One two-pin UART – One Interface for the Debug Communication Channel (DCC) support – One set of Chip ID Registers – One Interface providing ICE Access Prevention • Two-pin UART – USART-compatible User Interface – Programmable Baud Rate Generator – Parity, Framing and Overrun Error – Automatic Echo, Local Loopback and Remote Loopback Channel Modes • Debug Communication Channel Support – Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of peripherals – Chip ID is 0x275C 0A40 (VERSION 0) for AT91SAM7X512 – Chip ID is 0x275B 0940 (VERSION 0) for AT91SAM7X256 – Chip ID is 0x275A 0740 (VERSION 0) for AT91SAM7X128 9.6 Periodic Interval Timer • 20-bit programmable counter plus 12-bit interval counter 9.7 Watchdog Timer • 12-bit key-protected Programmable Counter running on prescaled SLCK • Provides reset or interrupt signals to the system • Counter may be stopped while the processor is in debug state or in idle mode 29 6120DS–ATARM–03-Oct-06 9.8 Real-time Timer • 32-bit free-running counter with alarm running on prescaled SLCK • Programmable 16-bit prescaler for SLCK accuracy compensation 9.9 PIO Controllers • Two PIO Controllers, each controlling 31 I/O lines • Fully programmable through set/clear registers • Multiplexing of two peripheral functions per I/O line • For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) – Input change interrupt – Half a clock period glitch filter – Multi-drive option enables driving in open drain – Programmable pull-up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 9.10 Voltage Regulator Controller The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set). 30 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 10. Peripherals 10.1 User Interface The User Peripherals are mapped in the 256 Mbytes of address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space. A complete memory map is provided in Figure 8-1 on page 18. 10.2 Peripheral Identifiers The AT91SAM7X512/256/128 embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the AT91SAM7X512/256/128. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller. Table 10-1. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 - 29 30 31 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB SPI0 SPI1 US0 US1 SSC TWI PWMC UDP TC0 TC1 TC2 CAN EMAC ADC (1) (1) Peripheral Name Advanced Interrupt Controller System Controller Parallel I/O Controller A Parallel I/O Controller B Serial Peripheral Interface 0 Serial Peripheral Interface 1 USART 0 USART 1 Synchronous Serial Controller Two-wire Interface Pulse Width Modulation Controller USB Device Port Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 CAN Controller Ethernet MAC Analog-to Digital Converter External Interrupt FIQ Reserved AIC AIC Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The System Controller and ADC are continuously clocked. 31 6120DS–ATARM–03-Oct-06 10.3 Peripheral Multiplexing on PIO Lines The AT91SAM7X512/256/128 features two PIO controllers, PIOA and PIOB, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls 31 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller. Table 10-2 on page 33 and Table 10-3 on page 34 defines how the I/O lines of the peripherals A, B or the analog inputs are multiplexed on the PIO Controller A and PIO Controller B. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions that are output only, may be duplicated in the table. At reset, all I/O lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected. 32 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 10.4 PIO Controller A Multiplexing Table 10-2. Multiplexing on PIO Controller A PIO Controller A Application Usage Comments High-Drive High-Drive SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 High-Drive High-Drive Function Comments I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 Peripheral A RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 TWD TWCK SPI_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK CANRX CANTX TF TK TD RD RK RF DRXD DTXD FIQ IRQ0 Peripheral B SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 PCK1 IRQ1 TCLK2 SPI1_NPCS0 SPI1_SPCK SPI1_MOSI SPI1_MISO SPI1_NPCS1 SPI1_NPCS2 PCK3 SPI1_NPCS3 PCK2 33 6120DS–ATARM–03-Oct-06 10.5 PIO Controller B Multiplexing Table 10-3. Multiplexing on PIO Controller B PIO Controller B Application Usage Comments Function Comments I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 Peripheral A ETXCK/EREFCK ETXEN ETX0 ETX1 ECRS ERX0 ERX1 ERXER EMDC EMDIO ETX2 ETX3 ETXER ERX2 ERX3 ERXDV/ECRSDV ECOL ERXCK EF100 PWM0 PWM1 PWM2 PWM3 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 PCK1 PCK2 Peripheral B PCK0 SPI1_NPCS1 SPI1_NPCS2 TCLK0 SPI0_NPCS1 SPI0_NPCS2 SPI1_NPCS3 SPI0_NPCS3 ADTRG TCLK1 PCK0 PCK1 PCK2 DCD1 DSR1 DTR1 RI1 PWM0 PWM1 PWM2 PWM3 AD0 AD1 AD2 AD3 34 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 10.6 Ethernet MAC • DMA Master on Receive and Transmit Channels • Compatible with IEEE Standard 802.3 • 10 and 100 Mbit/s operation • Full- and half-duplex operation • Statistics Counter Registers • MII/RMII interface to the physical layer • Interrupt generation to signal receive and transmit completion • 28-byte transmit FIFO and 28-byte receive FIFO • Automatic pad and CRC generation on transmitted frames • Automatic discard of frames received with errors • Address checking logic supports up to four specific 48-bit addresses • Support Promiscuous Mode where all valid received frames are copied to memory • Hash matching of unicast and multicast destination addresses • Physical layer management through MDIO interface • Half-duplex flow control by forcing collisions on incoming frames • Full-duplex flow control with recognition of incoming pause frames • Support for 802.1Q VLAN tagging with recognition of incoming VLAN and priority tagged frames • Multiple buffers per receive and transmit frame • Jumbo frames up to 10240 bytes supported 10.7 Serial Peripheral Interface • Supports communication with external serial devices – Four chip selects with external decoder allow communication with up to 15 peripherals – Serial memories, such as DataFlash® and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays per chip select, between consecutive transfers and between clock and data – Programmable delay between consecutive transfers – Selectable mode fault detection – Maximum frequency at up to Master Clock 10.8 Two-wire Interface • Master Mode only • Compatibility with standard two-wire serial memories 35 6120DS–ATARM–03-Oct-06 • One, two or three bytes for slave address • Sequential read/write operations 10.9 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode – 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB or LSB first – Optional break generation and detection – By 8 or by 16 over-sampling receiver frequency – Hardware handshaking RTS - CTS – Modem Signals Management DTR-DSR-DCD-RI on USART1 – Receiver time-out and transmitter timeguard – Multi-drop Mode with address generation and detection • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.10 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.11 Timer Counter • Three 16-bit Timer Counter Channels – Three output compare or two input capture • Wide range of functions including: – Frequency measurement – Event counting – Interval measurement – Pulse generation 36 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary – Delay timing – Pulse Width Modulation – Up/down capabilities • Each channel is user-configurable and contains: – Three external clock inputs • Five internal clock inputs, as defined in Table 10-4 Table 10-4. Timer Counter Clocks Assignment Clock MCK/2 MCK/8 MCK/32 MCK/128 MCK/1024 TC Clock input TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 – Two multi-purpose input/output signals – Two global registers that act on all three TC channels 10.12 Pulse Width Modulation Controller • Four channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs • Independent channel programming – Independent enable/disable commands – Independent clock selection – Independent period and duty cycle, with double buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 10.13 USB Device Port • USB V2.0 full-speed compliant,12 Mbits per second • Embedded USB V2.0 full-speed transceiver • Embedded 1352-byte dual-port RAM for endpoints • Six endpoints – Endpoint 0: 8 bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Endpoint 4 and 5: 256 bytes ping-pong – Ping-pong Mode (two memory banks) for bulk endpoints • Suspend/resume logic 37 6120DS–ATARM–03-Oct-06 10.14 CAN Controller • • • Fully compliant with CAN 2.0A and 2.0B Bit rates up to 1Mbit/s Eight object oriented mailboxes each with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B Programmable for each Message – Object configurable to receive (with overwrite or not) or transmit – Local tag and mask filters up to 29-bit identifier/channel – 32-bit access to data registers for each mailbox data object – Uses a 16-bit time stamp on receive and transmit message – Hardware concatenation of ID unmasked bitfields to speedup family ID processing – 16-bit internal timer for time stamping and network synchronization – Programmable reception buffer length up to 8 mailbox objects – Priority management between transmission mailboxes – Autobaud and listening mode – Low power mode and programmable wake-up on bus activity or by the application – Data, remote, error and overload frame handling 10.15 Analog-to-Digital Converter • 8-channel ADC • 10-bit 384 K samples/sec. Successive Approximation Register ADC • -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity • Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs • External voltage reference for better accuracy on low voltage inputs • Individual enable and disable of each channel • Multiple trigger sources – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four of eight analog inputs shared with digital signals 38 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary 11. Package Drawings Figure 11-1. LQFP Package Drawing 39 6120DS–ATARM–03-Oct-06 Table 11-1. Symbol A A1 A2 D D1 E E1 R2 R1 Q θ1 θ2 θ3 c L L1 S b e D2 E2 aaa bbb ccc ddd 100-lead LQFP Package Dimensions Millimeter Min 0.05 1.35 1.40 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.08 0.08 0° 0° 11° 11° 0.09 0.45 0.20 0.17 0.20 0.50 BSC 12.00 12.00 Tolerances of Form and Position 0.20 0.20 0.08 0.08 0.008 0.008 0.003 0.003 0.27 0.60 1.00 REF 0.008 0.007 0.008 0.020 BSC 0.472 0.472 0.011 12° 12° 13° 13° 0.20 0.75 3.5° 7° 0.20 0.003 0.003 0° 0° 11° 11° 0.004 0.018 0.024 0.039 REF 12° 12° 13° 13° 0.008 0.030 3.5° 7° Nom Max 1.60 0.15 1.45 0.002 0.053 0.055 0.630 BSC 0.551 BSC 0.630 BSC 0.551 BSC 0.008 Min Inch Nom Max 0.63 0.006 0.057 40 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary Figure 11-2. 100-TFBGA Package Drawing All dimensions are in mm 41 6120DS–ATARM–03-Oct-06 12. Ordering Information Table 12-1. Ordering Information Package LQFP 100 TFBGA 100 LQFP 100 TFBGA 100 LQFP 100 TFBGA 100 Package Type Green Green Green Temperature Operating Range Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) Industrial (-40°C to 85°C) Ordering Code AT91SAM7X512-AU AT91SAM7X512-CU AT91SAM7X256-AU AT91SAM7X256-CU AT91SAM7X128-AU AT91SAM7X128-CU 42 AT91SAM7X512/256/128 Preliminary Summary 6120DS–ATARM–03-Oct-06 AT91SAM7X512/256/128 Preliminary Summary Revision History Table 12-2. Revision History Change Request Ref. Doc. Rev 6120AS Comments First issue - Unqualified on Intranet Legal page updated.Qualified on Intranet 6120BS Corrections to maintain consistency with full datasheet: In “Features” on page 1, corrected Page Programming Time and Full Erase Time; corrected number of PDC channels, removed Wake-on-LAN support. In Figure 2-1 on page 4, corrected number of PDC channels. In Figure 2-1 on page 4, Table 3-1 on page 5, Table 10-2 on page 33 and Table 10-3 on page 34, changed all SPI pin names. In Section 5.2 ”Power Consumption” on page 11, changed value of static current level and value of dynamic power consumption level on VDDCORE In Section 6.2 ”Test Pin” on page 13, removed reference to SAM-BA boot recovery. In Section 6.6 ”I/O Lines Current Drawing” on page 14, changed value of total current level. In Section 7.4 ”Peripheral DMA Controller” on page 16, corrected number of PDC channels. In Section 8. ”Memories” on page 17, corrected Page Programming Time and Full Erase Time. In Section 8.7 ”SAM-BA Boot Assistant” on page 22, updated section. In Figure 9-1 on page 25, changed range of periph_irq and periph_clk on AIC and for Embedded Peripherals block. In Section 10.6 ”Ethernet MAC” on page 35, updated features. CSR 05-388 Update to product functionalities including changes to “Features” on page 1, Figure 2-1 on page 4, Section 9.5 ”Debug Unit” on page 29 and to Peripheral mapping. 6120CS Updated PLL output range max value in Section 9.2 ”Clock Generator” on page 27. Updated information in Section 5.1 ”Power Supplies” on page 11. Updated ordering information in “Ordering Information” on page 42. Added AT91SAM7X512 to product family.“Features” on page 1 and global Reformatted Memories Section 8. ”Memories” on page 17. Reordered sub sections in Peripherals Section 10. ”Peripherals” on page 31 Consolidated Memory Mapping in Figure 8-1 on page 18. Added TFBGA information Section 4.3 ”100-ball TFBGA Package Outline” on page 10. added LQFP and TFBGA package drawings Section 11. on page 39. System Controller block diagram Figure 9-1 on page 25, “ice_nreset” signals changed to “power_on_reset”. Section 10.1 ”User Interface” User Peripherals are mapped between 0xF000 0000 and 0XFFFF EFFF. Table 10-1 on page 31 SYSIRQ changed to SYSC in “Peripheral Identifiers” 05-457 05-462 05-491 05-471 2723 2728 6120DS rfo review 43 6120DS–ATARM–03-Oct-06 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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