AT91SAM9260-QU

Features • 180 MHz ARM926EJ-S™ ARM® Thumb® Processor – 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU • Memories – 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC – Two 4-kbyte internal SRAM, single-cycle access at system speed – One 32-kbyte internal ROM, embedding bootstrap routine Peripherals – ITU-R BT. 601/656 Image Sensor Interface – USB Device and USB Host with dedicated On-Chip Transceiver – 10/100 Mbps Ethernet MAC Controller – One High Speed Memory Card Host – Two Master/Slave Serial Peripheral Interfaces – Two Three-channel 32-bit Timer/Counters – One Synchronous Serial Controller – One Two-wire Interface – Four USARTs – Two UARTs – 4-channel 10-bit ADC System – 90 MHz six 32-bit layer AHB Bus Matrix – 22 Peripheral DMA Channels – Boot from NAND Flash, SDCard, DataFlash® or serial DataFlash – Reset Controller with On-Chip Power-on Reset – Selectable 32,768 Hz Low-Power and 3-20 MHz Main Oscillator – Internal Low-Power 32 kHz RC Oscillator – One PLL for the system and one PLL optimized for USB – Two Programmable External Clock Signals – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real Time Timer I/O – Three 32-bit Parallel Input/Output Controllers – 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os Package – 217-ball BGA, 0.8 mm pitch – 208-pin QFP, 0.5 mm pitch • AT91 ARM Thumb Microcontrollers AT91SAM9260 • • • 6221I–ATARM–17-Jul-09 1. Description The AT91SAM9260 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM memories and a wide range of peripherals. The AT91SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The AT91SAM9260 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. 2. AT91SAM9260 Block Diagram The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-pin PQFP package and the unavailable pins are highlighted in “Multiplexing on PIO Controller A” on page 27, “Multiplexing on PIO Controller B” on page 28, “Multiplexing on PIO Controller C” on page 29. The USB Host Port B is not available in the 208pin package. Table 2-1 on page 2 defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package. Table 2-1. Unavailable Signals in 208-lead PQFP Package PIO PA30 PA31 PB12 PB13 PC2 PC3 PC12 Peripheral A HDPB HDMB SCK2 SCK0 TXD5 RXD5 AD2 AD3 IRQ0 Peripheral B RXD4 TXD4 ISI_D10 ISI_D11 PCK1 SPI1_NPCS3 NCS7 2 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 2-1. S JT AG NT R TD ST TDI TMO TS C RTK CK ET EX T CK ECXE N ER ERRS -E XC T ERXE -EC XE K RO ET X0 -E L R -R M X0 ER XD D- X M C ETX 3 V D 3 F1 IO 00 TST Transc. In-Circuit Emulator System Controller JTAG Selection and Boundary Scan Transc. FIQ IRQ0-IRQ2 AIC DBGU ICache 8 Kbytes MMU Bus Interface DCache 8 Kbytes ARM926EJ-S Processor USB OHCI FIFO DMA DMA D FIFO DMA BM 10/100 Ethernet MAC DRXD DTXD PCK0-PCK1 I PDC PMC PLLRCA PLLA Filter AT91SAM9260 Block Diagram PLLB XIN XOUT OSC WDT PIT 6-layer Matrix RC 4GPREG OSCSEL XIN32 XOUT32 PIOA PIOB PIOC ROM 32 Kbytes Fast SRAM 4 Kbytes Peripheral Bridge Fast SRAM 4 Kbytes OSC RTT IS I_ M IS CK I_ IS PC I_ K I SI DO _V -I IS SY SI_ D I_ HS NC 7 YN C Image Sensor Interface SHDN WKUP VDDBU SHDWC POR 22-channel Peripheral DMA CompactFlash NAND Flash VDDCORE APB POR RSTC NRST SDRAM Controller PDC TWI SPI0 SPI1 TC0 TC1 TC2 TC3 TC4 TC5 PDC PDC SSC PDC 4-channel 10-bit ADC DPRAM USB Device Static Memory Controller ECC Controller Transceiver PDC USART0 USART1 USART2 USART3 USART4 USART5 MCI HD HD PA M A HD P HD B M B M CD B0 -M CD M MB C DA CC 3 0 -M DB C M DA CC 3 D MA CC K TW CT TW D RTS0- CK C SC S0- TS R3 RX K0- TS S3 TD C XD0-R K3 0- XD TX 5 DSD5 DCR0 D R0 DT I0 R0 NP NPCS NPCS3 NC2 PCS1 SP S0 MC OK T M SI CL IS O TI K0 O -T TI A0- CL O TK TC B0 IOA2 L -T 2 TI K3 IOB OTI A3 TC 2 O -T LK B 3- IO 5 TI A5 O B5 TK TF TD RD RF RK AD 0A AD D3 TR IG AD VR EF VD DA NA G ND AN A SPI0_, SPI1_ D D DDM P 6221I–ATARM–17-Jul-09 SE L MASTER SLAVE EBI D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE D16-D31 NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1-CFCE2 NCS2, NCS6, NCS7 NCS3/NANDCS AT91SAM9260 3 3. Signal Description Table 3-1. Signal Name Signal Description List Function Power Supplies Type Active Level Comments VDDIOM VDDIOP0 VDDIOP1 VDDBU VDDANA VDDPLL VDDCORE GND GNDPLL GNDANA GNDBU EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Peripherals I/O Lines Power Supply Backup I/O Lines Power Supply Analog Power Supply PLL Power Supply Core Chip Power Supply Ground PLL and Oscillator Ground Analog Ground Backup Ground Power Power Power Power Power Power Power Ground Ground Ground Ground 1.65V to 1.95V or 3.0V to3.6V 3.0V to 3.6V 1.65V to 3.6V 1.65V to 1.95V 3.0V to 3.6V 1.65V to 1.95V 1.65V to 1.95V Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 OSCSEL PLLRCA PCK0 - PCK1 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Slow Clock Oscillator Selection PLL A Filter Programmable Clock Output Input Output Input Output Input Input Output Accepts between 0V and VDDBU. Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-up Input ICE and JTAG NTRST TCK TDI TDO TMS JTAGSEL RTCK Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Return Test Clock Input Input Input Output Input Input Output No pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. Low Pull-up resistor No pull-up resistor No pull-up resistor Output Input Driven at 0V only. Do not tie over VDDBU. Accepts between 0V and VDDBU. 4 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 3-1. Signal Name Signal Description List (Continued) Function Reset/Test Type Active Level Comments NRST TST Microcontroller Reset Test Mode Select I/O Input Low Pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP0. BMS Boot Mode Select Input Debug Unit - DBGU DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ0 - IRQ2 FIQ External Interrupt Inputs Fast Interrupt Input Input Input PIO Controller - PIOA - PIOB - PIOC PA0 - PA31 PB0 - PB31 PC0 - PC31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset External Bus Interface - EBI D0 - D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset 0 at reset Static Memory Controller - SMC NCS0 - NCS7 NWR0 - NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output CompactFlash Support CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines Output Output Output Output Output Output Output Low Low Low Low Low Low Low Low Low Low Low 5 6221I–ATARM–17-Jul-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type NAND Flash Support Active Level Comments NANDCS NANDOE NANDWE NANDALE NANDCLE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable NAND Flash Address Latch Enable NAND Flash Command Latch Enable Output Output Output Output Output Low Low Low Low Low SDRAM Controller SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Low Low High Low Multimedia Card Interface MCI MCCK MCCDA MCDA0 - MCDA3 MCCDB MCDB0 - MCDB3 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data Multimedia Card Slot B Command Multimedia Card Slot B Data Output I/O I/O I/O I/O Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx TXDx RXDx RTSx CTSx DTR0 DSR0 DCD0 RI0 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send USART0 Data Terminal Ready USART0 Data Set Ready USART0 Data Carrier Detect USART0 Ring Indicator I/O I/O Input Output Input Output Input Input Input Synchronous Serial Controller - SSC TD RD TK RK TF RF SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O 6 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 3-1. Signal Name Signal Description List (Continued) Function Type Timer/Counter - TCx Active Level Comments TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Serial Peripheral Interface - SPIx_ SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1-SPIx_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low Two-Wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock USB Host Port HDPA HDMA HDPB HDMB USB Host Port A Data + USB Host Port A Data USB Host Port B Data + USB Host Port B Data + Analog Analog Analog Analog USB Device Port DDM DDP USB Device Port Data USB Device Port Data + Ethernet 10/100 ETXCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Transmit Clock or Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. Input Input Output Output Output Input Input Input Input Input Output I/O Output High MII only MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII MII only, REFCK in RMII MII only Analog Analog I/O I/O 7 6221I–ATARM–17-Jul-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Image Sensor Interface Active Level Comments ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data clock Input Output Input Input Input Analog to Digital Converter AD0-AD3 ADVREF ADTRG Analog Inputs Analog Positive Reference ADC Trigger Analog Analog Input Digital pulled-up inputs at reset 8 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 4. Package and Pinout The AT91SAM9260 is available in two packages: • 208-pin PQFP Green package (0.5mm pitch) (Figure 4-1) • 217-ball LFBGA Green package (0.8 mm ball pitch) (Figure 4-2). 4.1 208-pin PQFP Package Outline Figure 4-1 shows the orientation of the 208-pin PQFP package. A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Characteristics” of the product datasheet. Figure 4-1. 208-pin PQFP Package 156 157 105 104 208 1 52 53 9 6221I–ATARM–17-Jul-09 4.2 208-pin PQFP Pinout Pinout for 208-pin PQFP Package Signal Name PA24 PA25 PA26 PA27 VDDIOP0 GND PA28 PA29 PB0 PB1 PB2 PB3 VDDIOP0 GND PB4 PB5 PB6 PB7 PB8 PB9 PB14 PB15 PB16 VDDIOP0 GND PB17 PB18 PB19 TDO TDI TMS VDDIOP0 GND TCK NTRST NRST RTCK VDDCORE GND BMS OSCSEL TST JTAGSEL GNDBU XOUT32 XIN32 VDDBU WKUP Pin 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Signal Name GND DDM DDP PC13 PC11 PC10 PC14 PC9 PC8 PC4 PC6 PC7 VDDIOM GND PC5 NCS0 CFOE/NRD CFWE/NWE/NWR0 NANDOE NANDWE A22 A21 A20 A19 VDDCORE GND A18 BA1/A17 BA0/A16 A15 A14 A13 A12 A11 A10 A9 A8 VDDIOM GND A7 A6 A5 A4 A3 A2 NWR2/NBS2/A1 NBS0/A0 SDA10 Pin 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 Signal Name RAS D0 D1 D2 D3 D4 D5 D6 GND VDDIOM SDCK SDWE SDCKE D7 D8 D9 D10 D11 D12 D13 D14 D15 PC15 PC16 PC17 PC18 PC19 VDDIOM GND PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 GND VDDCORE VDDPLL XIN XOUT GNDPLL NC Pin 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 Signal Name ADVREF PC0 PC1 VDDANA PB10 PB11 PB20 PB21 PB22 PB23 PB24 PB25 VDDIOP1 GND PB26 PB27 GND VDDCORE PB28 PB29 PB30 PB31 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 VDDIOP0 GND PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 VDDIOP0 GND PA18 PA19 VDDCORE GND Table 4-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 10 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 4-1. Pin 49 50 51 52 Pinout for 208-pin PQFP Package (Continued) Signal Name SHDN HDMA HDPA VDDIOP0 Pin 101 102 103 104 Signal Name CFIOW/NBS3/NWR3 CFIOR/NBS1/NWR1 SDCS/NCS1 CAS Pin 153 154 155 156 Signal Name GNDPLL PLLRCA VDDPLL GNDANA Pin 205 206 207 208 Signal Name PA20 PA21 PA22 PA23 4.3 217-ball LFBGA Package Outline Figure 4-2 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in the section “AT91SAM9260 Mechanical Characteristics” of the product datasheet. Figure 4-2. 217-ball LFBGA Package (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGH J K LMNPRTU Ball A1 11 6221I–ATARM–17-Jul-09 4.4 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 217-ball LFBGA Pinout Pinout for 217-ball LFBGA Package Signal Name CFIOW/NBS3/NWR3 NBS0/A0 NWR2/NBS2/A1 A6 A8 A11 A13 BA0/A16 A18 A21 A22 CFWE/NWE/NWR0 CFOE/NRD NCS0 PC5 PC6 PC4 SDCK CFIOR/NBS1/NWR1 SDCS/NCS1 SDA10 A3 A7 A12 A15 A20 NANDWE PC7 PC10 PC13 PC11 PC14 PC8 WKUP D8 D1 CAS A2 A4 A9 A14 BA1/A17 A19 NANDOE PC9 PC12 DDP HDMB NC Table 4-2. Pin D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 Signal Name A5 GND A10 GND VDDCORE GND VDDIOM GND DDM HDPB NC VDDBU XIN32 D10 D5 D3 D4 HDPA HDMA GNDBU XOUT32 D13 SDWE D6 GND OSCSEL BMS JTAGSEL TST PC15 D7 SDCKE VDDIOM GND NRST RTCK TMS PC18 D14 D12 D11 GND GND GND VDDCORE TCK NTRST PB18 PC19 Pin J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 Signal Name TDO PB19 TDI PB16 PC24 PC20 D15 PC21 GND GND GND PB4 PB17 GND PB15 GND PC26 PC25 VDDIOP0 PA28 PB9 PB8 PB14 VDDCORE PC31 GND PC22 PB1 PB2 PB3 PB7 XIN VDDPLL PC23 PC27 PA31 PA30 PB0 PB6 XOUT VDDPLL PC30 PC28 PB11 PB13 PB24 VDDIOP1 PB30 PB31 Pin P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 Signal Name PB5 NC GNDANA PC29 VDDANA PB12 PB23 GND PB26 PB28 PA0 PA4 PA5 PA10 PA21 PA23 PA24 PA29 PLLRCA GNDPLL PC0 PC1 PB10 PB22 GND PB29 PA2 PA6 PA8 PA11 VDDCORE PA20 GND PA22 PA27 GNDPLL ADVREF PC2 PC3 PB20 PB21 PB25 PB27 PA12 PA13 PA14 PA15 PA19 PA17 12 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 4-2. Pin C16 C17 D1 D2 D3 D4 Pinout for 217-ball LFBGA Package (Continued) Signal Name VDDIOP0 SHDN D9 D2 RAS D0 Pin J2 J3 J4 J8 J9 J10 Signal Name PC17 VDDIOM PC16 GND GND GND Pin P11 P12 P13 P14 P15 P16 Signal Name PA1 PA3 PA7 PA9 PA26 PA25 Pin U15 U16 U17 Signal Name PA16 PA18 VDDIOP0 5. Power Considerations 5.1 Power Supplies The AT91SAM9260 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and 1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is selectable by software. • VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 3.0V and 3.6V, 3V or 3.3V nominal. • VDDIOP1 pins: Power the Peripherals I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.65V to 1.95V, 1.8V nominal. • VDDPLL pin: Powers the Main Oscillator and PLL cells; voltage ranges from 1.65V and 1.95V, 1.8V nominal. • VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and 3.6V, 3.3V nominal. The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins power supplies. Separated ground pins are provided for VDDBU, VDDPLL and VDDANA. These ground pins are respectively GNDBU, GNDPLL and GNDANA. 5.2 Power Consumption The AT91SAM9260 consumes about 500 µA of static current on VDDCORE at 25°C. This static current rises up to 5 mA if the temperature increases to 85°C. On VDDBU, the current does not exceed 10 µA in worst case conditions. For dynamic power consumption, the AT91SAM9260 consumes a maximum of 100 mA on VDDCORE at maximum conditions (1.8V, 25°C, processor running full-performance algorithm out of high speed memories). 13 6221I–ATARM–17-Jul-09 5.3 Programmable I/O Lines Power Supplies The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The target maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address and data signals) do not exceed 50 MHz. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal, and power supply pins can accept either 1.8V or 3.3V. Obviously, the device cannot reach its maximum speed if the voltage supplied to the pins is 1.8V only. The user must program the EBI voltage range before getting the device out of its Slow Clock Mode. 6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 6.3. All the JTAG signals are supplied with VDDIOP0. 6.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU. 6.3 Reset Pins NRST is a bidirectional with an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in the table “DC Characteristics” in the section “AT91SAM9260 Electrical Characteristics” in the product datasheet. The NRST signal is inserted in the Boundary Scan. 14 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 6.4 PIO Controllers All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section on DC Characteristics in “AT91SAM9260 Electrical Characteristics” for more information. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals and that must be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 I/O Line Drive Levels The PIO lines are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently except PC4 to PC31 that are VDDIOM powered. 6.6 Shutdown Logic Pins The SHDN pin is a tri-state output pin, which is driven by the Shutdown Controller. There is no internal pull-up. An external pull-up tied to VDDBU is needed and its value must be higher than 1 MΩ. The resistor value is calculated according to the regulator enable implementation and the SHDN level. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 6.7 Slow Clock Selection The AT91SAM9260 slow clock can be generated either by an external 32,768 Hz crystal or the on-chip RC oscillator. Table 6-1 defines the states for OSCSEL signal. Table 6-1. OSCSEL 0 1 Slow Clock Selection Slow Clock Internal RC External 32768 Hz Startup Time 240 µs 1200 ms The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The 32,768 Hz startup delay is 1200 ms whereas it is 240 µs for the internal RC oscillator (refer to Table 6-1). The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the device. 15 6221I–ATARM–17-Jul-09 7. Memories Figure 7-1. AT91SAM9260 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF Internal Memory Mapping 0x0000 0000 Boot Memory (1) Notes : (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP 256M Bytes 0x10 0000 ROM 0x10 8000 Reserved 32K Bytes 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF 256M Bytes 0x20 0000 SRAM0 0x20 1000 Reserved 4K Bytes 0x2000 0000 EBI Chip Select 1/ SDRAMC 256M Bytes 0x30 0000 SRAM1 0x30 1000 Reserved 0x50 0000 4K Bytes 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 256M Bytes UHP 0x50 4000 Reserved 16K Bytes 0x4000 0000 EBI Chip Select 3/ NANDFlash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 EBI Chip Select 6 256M Bytes 0x0FFF FFFF 0x4FFF FFFF 0x5000 0000 256M Bytes 0x5FFF FFFF 0x6000 0000 Peripheral Mapping 256M Bytes 0xF000 0000 0x6FFF FFFF 0x7000 0000 256M Bytes Reserved 0xFFFA 0000 TCO, TC1, TC2 0xFFFA 4000 UDP 0xFFFA 8000 16K Bytes 16K Bytes System Controller Mapping 0xFFFF C000 Reserved 0xFFFF E800 ECC 512 Bytes 0x7FFF FFFF 0x8000 0000 EBI Chip Select 7 0x8FFF FFFF 256M Bytes 0xFFFA C000 MCI TWI 0xFFFB 0000 USART0 0xFFFB 4000 USART1 0xFFFB 8000 USART2 0xFFFB C000 SSC 0xFFFC 0000 ISI 0xFFFC 4000 EMAC 0xFFFC 8000 16K Bytes 16K Bytes 0xFFFF EA00 SDRAMC 0xFFFF EC00 512 Bytes 0x9000 0000 16K Bytes 0xFFFF EE00 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF F600 16K Bytes 16K Bytes 0xFFFF F800 SMC MATRIX 0xFFFF EF10 0xFFFF F000 CCFG AIC 0xFFFF F200 DBGU 0xFFFF F400 PIOA 512 Bytes 512 Bytes 512 Bytes 512 Bytes 512 Bytes Undefined (Abort) 1,518M Bytes 0xFFFC C000 SPI0 PIOB 512 bytes SPI1 0xFFFD 0000 USART3 0xFFFD 4000 USART4 0xFFFD 8000 USART5 0xFFFD C000 TC3, TC4, TC5 0xFFFE 0000 0xEFFF FFFF ADC 0xFFFE 4000 PIOC 16K Bytes 16K Bytes 16K Bytes 0xFFFF FA00 Reserved 0xFFFF FC00 PMC 0xFFFF FD00 RSTC 0xFFFF FD10 16K Bytes 16K Bytes 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 WDTC SHDWC RTTC PITC 0xFFFF FD50 0xFFFF FD60 16K Bytes 0xFFFF FFFF 512 bytes 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 0xF000 0000 Internal Peripherals 0xFFFF FFFF Reserved 256M Bytes 0xFFFF C000 SYSC 0xFFFF FFFF GPBR Reserved 16 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256 Mbytes. The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 7-1, “Internal Memory Mapping,” on page 17 for details. A complete memory map is presented in Figure 7-1 on page 16. 7.1 Embedded Memories • 32 KB ROM – Single Cycle Access at full matrix speed • Two 4 KB Fast SRAM – Single Cycle Access at full matrix speed 7.1.1 Boot Strategies Table 7-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Table 7-1. Internal Memory Mapping REMAP = 0 Address BMS = 1 0x0000 0000 ROM BMS = 0 EBI_NCS0 SRAM0 4K REMAP = 1 The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 7-1 on page 16. 17 6221I–ATARM–17-Jul-09 The AT91SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 7.1.1.1 BMS = 1, Boot on Embedded ROM The system boots using the Boot Program. • Boot on slow clock (On-chip RC or 32,768 Hz) • Auto baudrate detection • Downloads and runs an application from external storage media into internal SRAM • Downloaded code size depends on embedded SRAM size • Automatic detection of valid application • Bootloader on a non-volatile memory – SPI DataFlash® connected on NPCS0 and NPCS1 of the SPI0 – 8-bit and/or 16-bit NAND Flash • SAM-BA® Monitor in case no valid program is detected in external NVM, supporting – Serial communication on a DBGU – USB Device Port 7.1.1.2 BMS = 0, Boot on External Memory • Boot on slow clock (On-chip RC or 32,768 Hz) • Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take the following steps: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock. 4. Switch the main clock to the new value. 7.2 External Memories The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256-Mbyte memory area assigned. Refer to the memory map in Figure 7-1 on page 16. 7.2.1 External Bus Interface • Integrates three External Memory Controllers – Static Memory Controller – SDRAM Controller 18 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 – ECC Controller • Additional logic for NAND Flash • Full 32-bit External Data Bus • Up to 26-bit Address Bus (up to 64MBytes linear) • Up to 8 chip selects, Configurable Assignment: – Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3, Optional NAND Flash support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support – Static Memory Controller on NCS6-NCS7 7.2.2 Static Memory Controller • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability – Compliant with LCD Module – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported 7.2.3 SDRAM Controller • Supported devices – Standard and Low-power SDRAM (Mobile SDRAM) • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Datapath • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported 19 6221I–ATARM–17-Jul-09 • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency of 1, 2 and 3 supported • Auto Precharge Command not used 7.2.4 Error Corrected Code Controller • Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select • Single bit error correction and 2-bit Random detection • Automatic Hamming Code Calculation while writing – ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being detected erroneous – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages 20 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 8. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure EBI chip select assignment and voltage range for external memories The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF E800 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes. Figure 8-1 on page 22 shows the System Controller block diagram. Figure 7-1 on page 16 shows the mapping of the User Interfaces of the System Controller peripherals. 21 6221I–ATARM–17-Jul-09 8.1 Block Diagram AT91SAM9260 System Controller Block Diagram System Controller VDDCORE Powered irq0-irq2 fiq periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE POR por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK rtt_irq rtt_alarm UDPCK periph_clk[10] RC OSC SLOW CLOCK OSC SLCK int MAIN OSC PLLA PLLB MAINCK Power Management Controller Shutdown Controller periph_nreset periph_irq[10] 4 General-purpose Backup Registers USB Device Port UHPCK periph_clk[20] periph_nreset periph_irq[20] USB Host Port Debug Unit Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq Figure 8-1. dbgu_irq dbgu_txd pit_irq proc_nreset PCK debug jtag_nreset wdt_irq MCK periph_nreset Boundary Scan TAP Controller Bus Matrix VDDBU VDDBU POR SLCK backup_nreset SLCK SHDN WKUP backup_nreset rtt0_alarm OSC_SEL XIN32 XOUT32 Real-time Timer periph_clk[2..27] pck[0-1] PCK UDPCK UHPCK MCK XIN XOUT PLLRCA PLLACK PLLBCK periph_nreset pmc_irq idle periph_clk[6..24] periph_nreset periph_nreset periph_clk[2..4] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PIO Controllers periph_irq[2..4] irq0-irq2 fiq dbgu_txd Embedded Peripherals periph_irq[6..24] in out enable 22 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 8.2 Power Management Controller • Provides: – the Processor Clock PCK – the Master Clock MCK, in particular to the Matrix and the memory interfaces – the USB Device Clock UDPCK – independent peripheral clocks, typically at the frequency of MCK – 2 programmable clock outputs: PCK0, PCK1 • Five flexible operating modes: – Normal Mode, processor and peripherals running at a programmable frequency – Idle Mode, processor stopped waiting for an interrupt – Slow Clock Mode, processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt – Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 8-2. AT91SAM9260 Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Divider /1,/2,/4 Peripherals Clock Controller ON/OFF Idle Mode MCK periph_clk[..] PCK int Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] USB Clock Controller ON/OFF PLLBCK Divider /1,/2,/4 UDPCK UHPCK 8.3 General-purpose Back-up Registers • Four 32-bit backup general-purpose registers 8.4 Chip Identification • Chip ID: 0x019803A2 • JTAG ID: 0x05B1303F • ARM926 TAP ID: 0x0792603F 23 6221I–ATARM–17-Jul-09 8.5 Backup Section The AT91SAM9260 features a Backup Section that embeds: • RC Oscillator • Slow Clock Oscillator • SCKR register • RTT • Shutdown Controller • 4 backup registers • A part of RSTC This section is powered by the VDDBU rail. 9. Peripherals 9.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 7-1 on page 16. 9.2 Identifiers Table 9-1 defines the Peripheral Identifiers of the AT91SAM9260. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 9-1. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 AT91SAM9260 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC ADC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC TC0 Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C Analog to Digital Converter USART 0 USART 1 USART 2 Multimedia Card Interface USB Device Port Two-wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller Reserved Reserved Timer/Counter 0 External Interrupt FIQ 24 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 9-1. Peripheral ID 18 19 20 21 22 23 24 25 26 27 28 29 30 31 AT91SAM9260 Peripheral Identifiers (Continued) Peripheral Mnemonic TC1 TC2 UHP EMAC ISI US3 US4 US5 TC3 TC4 TC5 AIC AIC AIC Peripheral Name Timer/Counter 1 Timer/Counter 2 USB Host Port Ethernet MAC Image Sensor Interface USART 3 USART 4 USART 5 Timer/Counter 3 Timer/Counter 4 Timer/Counter 5 Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 External Interrupt Note: Setting AIC, SYSC, UHP and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. 9.2.1 9.2.1.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-time Timer • the Watchdog Timer • the Reset Controller • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 9.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 9.3 Peripheral Signal Multiplexing on I/O Lines The AT91SAM9260 features 3 PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. Table 9-2 on page 27, Table 9-3 on page 28 and Table 9-4 on page 29 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two col- 25 6221I–ATARM–17-Jul-09 umns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only might be duplicated within both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O appears, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name appears in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 26 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 9.3.1 Table 9-2. PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Note: (1) (1) Application Usage Comments Reset State I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function Comments Peripheral A SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 RTS2 CTS2 MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 ETX0 ETX1 ERX0 ERX1 ETXEN ERXDV ERXER ETXCK EMDC EMDIO ADTRG TWD TWCK TCLK0 TIOA0 TIOA1 TIOA2 SCK1 SCK2 SCK0 Peripheral B MCDB0 MCCDB MCDB3 MCDB2 MCDB1 I/O I/O I/O I/O I/O I/O I/O ETX2 ETX3 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ETXER ETX2 ETX3 ERX2 ERX3 ERXCK ECRS ECOL RXD4 TXD4 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 1. Not available in the 208-lead PQFP package. 27 6221I–ATARM–17-Jul-09 9.3.2 Table 9-3. PIO Controller B Multiplexing Multiplexing on PIO Controller B PIO Controller B Application Usage Comments Reset State I/O I/O I/O I/O I/O I/O TCLK1 TCLK2 I/O I/O I/O I/O ISI_D8 ISI_D9 ISI_D10 ISI_D11 I/O I/O I/O I/O I/O I/O TCLK3 TCLK4 TIOB4 TIOB5 ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_VSYNC ISI_HSYNC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 Function Comments I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12(1) PB13(1) PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Note: Peripheral A SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 TXD0 RXD0 TXD1 RXD1 TXD2 RXD2 TXD3 RXD3 TXD5 RXD5 DRXD DTXD TK0 TF0 TD0 RD0 RK0 RF0 DSR0 DCD0 DTR0 RI0 RTS0 CTS0 RTS1 CTS1 PCK0 PCK1 Peripheral B TIOA3 TIOB3 TIOA4 TIOA5 1. Not available in the 208-lead PQFP package. 28 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 9.3.3 Table 9-4. PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2 (1) (1) Application Usage Comments AD0 AD1 AD2 AD3 Reset State I/O I/O I/O I/O A23 A24 I/O I/O I/O I/O A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDANA VDDANA VDDANA VDDANA VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function Comments Peripheral A Peripheral B SCK3 PCK0 PCK1 SPI1_NPCS3 PC3 PC4 PC5 A23 A24 TIOB2 TIOB1 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW NCS2 IRQ0 FIQ NCS3/NANDCS NWAIT D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 SPI1_NPCS2 SPI1_NPCS1 CFCE1 CFCE2 RTS3 TIOB0 CTS3 SPI0_NPCS1 NCS7 NCS6 IRQ2 IRQ1 SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 EF100 TCLK5 PC6 PC7 PC8 PC9 PC10 PC11 PC12(1) PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Note: 1. Not available in the 208-lead PQFP package. 29 6221I–ATARM–17-Jul-09 30 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 10. ARM926EJ-S Processor Overview 10.1 Description The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multitasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Javapowered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S™ integer core • a Memory Management Unit (MMU) • separate instruction and data AMBA™ AHB bus interfaces • separate instruction and data TCM interfaces 10.2 Embedded Characteristics • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • DSP Instruction Extensions • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 8-Kbyte Data Cache, 8-Kbyte Instruction Cache – Virtually-addressed 4-way Associative Cache – Eight words per line – Write-through and Write-back Operation – Pseudo-random or Round-robin Replacement • Write Buffer – Main Write Buffer with 16-word Data Buffer and 4-address Buffer – DCache Write-back Buffer with 8-word Entries and a Single Address Entry 31 6221I–ATARM–17-Jul-09 – Software Control Drain • Standard ARM v4 and v5 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for each quarter of the page – 16 embedded domains • Bus Interface Unit (BIU) – Arbitrates and Schedules AHB Requests – Separate Masters for both instruction and data access providing complete Matrix system flexibility – Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) 32 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 10.3 Block Diagram Figure 10-1. ARM926EJ-S Internal Functional Block Diagram ARM926EJ-S TCM Interface Coprocessor Interface ETM Interface DEXT Droute Data AHB Interface AHB DCACHE Bus Interface Unit WDATA RDATA ARM9EJ-S DA MMU EmbeddedICE -RT Processor IA Instruction AHB Interface AHB INSTR ICE Interface ICACHE Iroute IEXT 10.4 10.4.1 ARM9EJ-S Processor ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: • ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 10.4.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC 33 6221I–ATARM–17-Jul-09 • ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 10.4.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 10.4.4 Memory Access The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data. 10.4.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode appears as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 10.4.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: • User mode is the usual ARM program execution state. It is used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling 34 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 • Supervisor mode is a protected mode for the operating system • Abort mode is entered after a data or instruction prefetch abort • System mode is a privileged user mode for the operating system • Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 10.4.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers. • 31 general-purpose 32-bit registers • 6 32-bit status registers Table 10-1 shows all the registers in all modes. Table 10-1. User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC ARM9TDMI™ Modes and Registers Layout Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC CPSR CPSR SPSR_SVC CPSR SPSR_ABORT CPSR SPSR_UNDEF CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers 35 6221I–ATARM–17-Jul-09 The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines: • constraints on the use of registers • stack conventions • argument passing and result return The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC • CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12). 10.4.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode 36 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 10-2. Status Register Format 31 30 29 28 27 24 765 0 NZCVQ J Reserved I FT Mode Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than Mode bits Thumb state bit FIQ disable IRQ disable Figure 10-2 shows the status register format, where: • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. • The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where: – J = 0: The processor is in ARM or Thumb state, depending on the T bit – J = 1: The processor is in Jazelle state. • Mode: five bits to encode the current processor mode 10.4.7.2 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi- leged mode. The types of exceptions are: • Fast interrupt (FIQ) • Normal interrupt (IRQ) • Data and Prefetched aborts (Abort) • Undefined instruction (Undefined) • Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order: • Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) 37 6221I–ATARM–17-Jul-09 The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: – ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). – THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 10.4.8 ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions 38 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 • Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 10-2 gives the ARM instruction mnemonic list. Table 10-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Coprocessor Data Processing STRH STRB STRBT STRT STM SWPB MRC STC Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor Mnemonic MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR Operation Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word 39 6221I–ATARM–17-Jul-09 10.4.9 New ARM Instruction Set Table 10-3. Mnemonic BXJ BLX (1) New ARM Instruction Mnemonic List Operation Branch and exchange to Java Branch, Link and exchange Signed Multiply Accumulate 16 * 16 bit Signed Multiply Accumulate Long Signed Multiply Accumulate 32 * 16 bit Signed Multiply 16 * 16 bit Signed Multiply 32 * 16 bit Saturated Add Saturated Add with Double Saturated subtract Saturated Subtract with double Mnemonic MRRC MCR2 MCRR CDP2 BKPT PLD STRD STC2 LDRD LDC2 CLZ Operation Move double from coprocessor Alternative move of ARM reg to coprocessor Move double to coprocessor Alternative Coprocessor Data Processing Breakpoint Soft Preload, Memory prepare to load from address Store Double Alternative Store from Coprocessor Load Double Alternative Load to Coprocessor Count Leading Zeroes SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 10.4.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store multiple instructions • Exception-generating instruction Table 10-4 gives the Thumb instruction mnemonic list. Table 10-4. Mnemonic MOV ADD SUB CMP TST AND EOR Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Mnemonic MVN ADC SBC CMN NEG BIC ORR Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR 40 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 10-4. Mnemonic LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC Thumb Instruction Mnemonic List (Continued) Operation Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch Mnemonic LSR ROR BLX BL SWI STR STRH STRB LDRSB STMIA POP BKPT Operation Logical Shift Right Rotate Right Branch, Link, and Exchange Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Breakpoint 10.5 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S • Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 10-5. Table 10-5. Register 0 0 0 1 2 3 4 5 5 6 7 8 9 CP15 Registers Name ID Code(1) Cache type(1) TCM status Control Translation Table Base Domain Access Control Reserved Data fault Status (1) (1) (1) Read/Write Read/Unpredictable Read/Unpredictable Read/Unpredictable Read/write Read/write Read/write None Read/write Read/write Read/write Read/Write Unpredictable/Write Read/write Instruction fault status Fault Address Cache Operations TLB operations Cache lockdown(2) 41 6221I–ATARM–17-Jul-09 Table 10-5. Register 9 10 11 12 13 13 14 15 Notes: CP15 Registers Name TCM region TLB lockdown Reserved Reserved FCSE PID(1) Context ID Reserved Test configuration (1) Read/Write Read/write Read/write None None Read/write Read/Write None Read/Write 1. Register locations 0, 5 and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. 10.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. 42 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 27 26 25 24 cond 23 22 21 20 1 19 1 18 1 17 0 16 opcode_1 15 14 13 L 12 11 10 CRn 9 8 Rd 7 6 5 4 1 3 1 2 1 1 1 0 opcode_2 1 CRm • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. • opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. • Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. 43 6221I–ATARM–17-Jul-09 10.6 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, Windows CE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 10-6 shows the different attributes of each page in the physical memory. Table 10-6. Mapping Details Mapping Size 1M byte 64K bytes 4K bytes 1K byte Access Permission By Section 4 separated subpages 4 separated subpages Tiny Page Subpage Size 16K bytes 1K byte - Mapping Name Section Large Page Small Page Tiny Page The MMU consists of: • Access control logic • Translation Look-aside Buffer (TLB) • Translation table walk hardware 10.6.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 44 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 10.6.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 10.6.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Pagemapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 10.6.4 MMU Faults The MMU generates an abort on the following types of faults: • Alignment faults (for data accesses only) • Translation faults • Domain faults • Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 10.7 Caches and Write Buffer The ARM926EJ-S contains a 8 KB Instruction Cache (ICache), a 8 KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. 45 6221I–ATARM–17-Jul-09 A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 10.7.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 10.7.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA AHB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. 10.7.2.1 46 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 10.7.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and writeback region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 10.8 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: • It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. • Each AHB layer becomes simple because it only has one master, so no arbitration or masterto-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. • The arbitration becomes effective when more than one master wants to access the same slave simultaneously. 10.8.1 Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into 47 6221I–ATARM–17-Jul-09 packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 10-7 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 10-7. HBurst[2:0] Supported Transfers Description Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT, or WB that has missed in DCache) SINGLE Single transfer • data read (NCNB or NCB) • NC instruction fetch (prefetched and non-prefetched) • page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. Cache linefill INCR4 INCR8 WRAP8 Four-word incrementing burst Eight-word incrementing burst Eight-word wrapping burst 10.8.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time. Address Alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. 10.8.3 48 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 11. AT91SAM9260 Debug and Test 11.1 Description The AT91SAM9260 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 11.2 Embedded Characteristics • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 49 6221I–ATARM–17-Jul-09 11.3 Block Diagram Figure 11-1. Debug and Test Block Diagram TMS TCK TDI NTRST Boundary Port ICE/JTAG TAP JTAGSEL TDO RTCK Reset and Test POR TST ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU PIO DTXD DRXD TAP: Test Access Port 50 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 11.4 11.4.1 Application Examples Debug Environment Figure 11-2 on page 51 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 11-2. Application Debug and Trace Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector AT91SAM9260 RS232 Connector Terminal AT91SAM9260-based Application Board 51 6221I–ATARM–17-Jul-09 11.4.2 Test Environment Figure 11-3 on page 52 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 11-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91SAM9260 Chip 1 AT91SAM9260-based Application Board In Test 11.5 Debug and Test Pin Description Table 11-1. Pin Name Debug and Test Pin List Function Reset/Test Type Active Level NRST TST Microcontroller Reset Test Mode Select ICE and JTAG Input/Output Input Low High NTRST TCK TDI TDO TMS RTCK JTAGSEL Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection Debug Unit Input Input Input Output Input Output Input Low DRXD DTXD Debug Receive Data Debug Transmit Data Input Output 52 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 11.6 11.6.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 11.6.2 EmbeddedICE The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the ARM document: ARM9EJ-S Technical Reference Manual (DDI 0222A). 11.6.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 53 6221I–ATARM–17-Jul-09 11.6.4 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9260 Debug Unit Chip ID value is 0x0198 03A0 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 11.6.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 11.6.5.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associated control signals. Each AT91SAM9260 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 11-2. Bit Number 307 A0 306 305 A1 304 303 A10 302 301 A11 300 299 A12 298 IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9260 JTAG Boundary Scan Register Pin Name Pin Type Associated BSR Cells CONTROL 54 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 11-2. 297 A13 296 295 A14 294 293 A15 292 291 A16 290 289 A17 288 287 A18 286 285 A19 284 283 A2 282 281 A20 280 279 A21 278 277 A22 276 275 A3 274 273 A4 272 271 A5 270 269 A6 268 267 A7 266 265 A8 264 263 A9 262 261 BMS INPUT IN/OUT INPUT/OUTPUT INPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9260 JTAG Boundary Scan Register CONTROL 55 6221I–ATARM–17-Jul-09 Table 11-2. 260 AT91SAM9260 JTAG Boundary Scan Register CONTROL CAS IN/OUT INPUT/OUTPUT CONTROL D0 IN/OUT INPUT/OUTPUT CONTROL D1 IN/OUT INPUT/OUTPUT CONTROL D10 IN/OUT INPUT/OUTPUT CONTROL D11 IN/OUT INPUT/OUTPUT CONTROL D12 IN/OUT INPUT/OUTPUT CONTROL D13 IN/OUT INPUT/OUTPUT CONTROL D14 IN/OUT INPUT/OUTPUT CONTROL D15 IN/OUT INPUT/OUTPUT CONTROL D2 IN/OUT INPUT/OUTPUT CONTROL D3 IN/OUT INPUT/OUTPUT CONTROL D4 IN/OUT INPUT/OUTPUT CONTROL D5 IN/OUT INPUT/OUTPUT CONTROL D6 IN/OUT INPUT/OUTPUT CONTROL D7 IN/OUT INPUT/OUTPUT CONTROL D8 IN/OUT INPUT/OUTPUT CONTROL D9 IN/OUT INPUT/OUTPUT CONTROL NANDOE IN/OUT INPUT/OUTPUT 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 56 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 11-2. 224 NANDWE 223 222 NCS0 221 220 NCS1 219 218 NRD 217 216 NRST 215 214 NWR0 213 212 NWR1 211 210 NWR3 209 208 207 PA0 206 205 PA1 204 203 PA10 202 201 PA11 200 199 PA12 198 197 PA13 196 195 PA14 194 193 PA15 192 191 PA16 190 189 PA17 188 IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL OSCSEL INPUT IN/OUT INPUT/OUTPUT INPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9260 JTAG Boundary Scan Register CONTROL 57 6221I–ATARM–17-Jul-09 Table 11-2. 187 AT91SAM9260 JTAG Boundary Scan Register CONTROL PA18 IN/OUT INPUT/OUTPUT CONTROL PA19 IN/OUT INPUT/OUTPUT CONTROL PA2 IN/OUT INPUT/OUTPUT CONTROL PA20 IN/OUT INPUT/OUTPUT CONTROL PA21 IN/OUT INPUT/OUTPUT CONTROL PA22 IN/OUT INPUT/OUTPUT CONTROL PA23 IN/OUT INPUT/OUTPUT CONTROL PA24 IN/OUT INPUT/OUTPUT CONTROL PA25 IN/OUT INPUT/OUTPUT CONTROL PA26 IN/OUT INPUT/OUTPUT CONTROL PA27 IN/OUT INPUT/OUTPUT CONTROL PA28 IN/OUT INPUT/OUTPUT CONTROL PA29 IN/OUT INPUT/OUTPUT CONTROL PA3 IN/OUT INPUT/OUTPUT internal internal internal internal CONTROL PA4 IN/OUT INPUT/OUTPUT CONTROL PA5 IN/OUT INPUT/OUTPUT 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 58 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 11-2. 151 PA6 150 149 PA7 148 147 PA8 146 145 PA9 144 143 PB0 142 141 PB1 140 139 PB10 138 137 PB11 136 135 134 133 132 131 PB14 130 129 PB15 128 127 PB16 126 125 PB17 124 123 PB18 122 121 PB19 120 119 PB2 118 117 PB20 116 IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL internal internal internal internal CONTROL IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9260 JTAG Boundary Scan Register CONTROL 59 6221I–ATARM–17-Jul-09 Table 11-2. 115 AT91SAM9260 JTAG Boundary Scan Register CONTROL PB21 IN/OUT INPUT/OUTPUT CONTROL PB22 IN/OUT INPUT/OUTPUT CONTROL PB23 IN/OUT INPUT/OUTPUT CONTROL PB24 IN/OUT INPUT/OUTPUT CONTROL PB25 IN/OUT INPUT/OUTPUT CONTROL PB26 IN/OUT INPUT/OUTPUT CONTROL PB27 IN/OUT INPUT/OUTPUT CONTROL PB28 IN/OUT INPUT/OUTPUT CONTROL PB29 IN/OUT INPUT/OUTPUT CONTROL PB3 IN/OUT INPUT/OUTPUT CONTROL PB30 IN/OUT INPUT/OUTPUT CONTROL PB31 IN/OUT INPUT/OUTPUT CONTROL PB4 IN/OUT INPUT/OUTPUT CONTROL PB5 IN/OUT INPUT/OUTPUT CONTROL PB6 IN/OUT INPUT/OUTPUT CONTROL PB7 IN/OUT INPUT/OUTPUT CONTROL PB8 IN/OUT INPUT/OUTPUT CONTROL PB9 IN/OUT INPUT/OUTPUT 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 60 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 11-2. 79 PC0 78 77 PC1 76 75 PC10 74 73 PC11 72 71 70 69 PC13 68 67 PC14 66 65 PC15 64 63 PC16 62 61 PC17 60 59 PC18 58 57 PC19 56 55 54 53 PC20 52 51 PC21 50 49 PC22 48 47 PC23 46 45 PC24 44 IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL internal internal CONTROL IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL internal internal CONTROL IN/OUT INPUT/OUTPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9260 JTAG Boundary Scan Register CONTROL 61 6221I–ATARM–17-Jul-09 Table 11-2. 43 AT91SAM9260 JTAG Boundary Scan Register CONTROL PC25 IN/OUT INPUT/OUTPUT CONTROL PC26 IN/OUT INPUT/OUTPUT CONTROL PC27 IN/OUT INPUT/OUTPUT CONTROL PC28 IN/OUT INPUT/OUTPUT CONTROL PC29 IN/OUT INPUT/OUTPUT internal internal CONTROL PC30 IN/OUT INPUT/OUTPUT CONTROL PC31 IN/OUT INPUT/OUTPUT CONTROL PC4 IN/OUT INPUT/OUTPUT CONTROL PC5 IN/OUT INPUT/OUTPUT CONTROL PC6 IN/OUT INPUT/OUTPUT CONTROL PC7 IN/OUT INPUT/OUTPUT CONTROL PC8 IN/OUT INPUT/OUTPUT CONTROL PC9 IN/OUT INPUT/OUTPUT CONTROL RAS IN/OUT INPUT/OUTPUT CONTROL RTCK OUT OUTPUT CONTROL SDA10 IN/OUT INPUT/OUTPUT CONTROL SDCK IN/OUT INPUT/OUTPUT 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 62 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 11-2. 07 SDCKE 06 05 SDWE 04 03 SHDN 02 01 00 TST WKUP INPUT INPUT OUT OUTPUT INPUT INPUT IN/OUT INPUT/OUTPUT CONTROL IN/OUT INPUT/OUTPUT CONTROL AT91SAM9260 JTAG Boundary Scan Register CONTROL 63 6221I–ATARM–17-Jul-09 11.6.6 JID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B13 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B1_303F. 64 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 12. Reset Controller (RSTC) 12.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 12.2 Embedded Characteristics • Based on two Power-on-reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset • Controls the internal resets and the NRST pin output – Allows shaping a reset signal for the external devices 12.3 Block Diagram Figure 12-1. Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR Startup Counter rstc_irq Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager exter_nreset periph_nreset backup_neset WDRPROC wd_fault SLCK 12.4 12.4.1 Functional Description Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: 65 6221I–ATARM–17-Jul-09 • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • backup_nreset: Affects all the peripherals powered by VDDBU. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 12.4.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 12-2 shows the block diagram of the NRST Manager. Figure 12-2. NRST Manager RSTC_MR RSTC_SR URSTIEN rstc_irq RSTC_MR URSTS NRSTL Other interrupt sources user_reset URSTEN NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset 12.4.2.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 66 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 12.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 12.4.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 12-3. BMS Sampling SLCK Core Supply POR output XXX BMS sampling delay = 3 cycles BMS Signal H or L proc_nreset 12.4.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 12.4.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. 67 6221I–ATARM–17-Jul-09 When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 12-4 shows how the General Reset affects the reset signals. Figure 12-4. General Reset State SLCK MCK Backup Supply POR output Any Freq. Startup Time Main Supply POR output backup_nreset Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset XXX 0x0 = General Reset XXX NRST (nrst_out) BMS Sampling EXTERNAL RESET LENGTH = 2 cycles 68 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 12.4.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR. Figure 12-5. Wake-up State SLCK MCK Main Supply POR output Any Freq. backup_nreset Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 12.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 69 6221I–ATARM–17-Jul-09 When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 12-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset NRST (nrst_out) >= EXTERNAL RESET LENGTH 12.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. 70 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 12-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) Any XXX 0x3 = Software Reset SRCMP in RSTC_SR 12.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. 71 6221I–ATARM–17-Jul-09 • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 12-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 12.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup Reset • Wake-up Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. 72 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 12.4.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. • NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. • URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 12-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 12-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 73 6221I–ATARM–17-Jul-09 12.5 Reset Controller (RSTC) User Interface Register Mapping Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read-write Reset 0x0000_0001 0x0000_0000 0x0000_0000 Back-up Reset Table 12-1. Offset 0x00 0x04 0x08 Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 74 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 12.5.1 Name: Reset Controller Control Register RSTC_CR Write-only 30 29 28 KEY 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 – 19 – 11 – 3 EXTRST 18 – 10 – 2 PERRST 17 – 9 16 – 8 – 0 PROCRST 27 26 25 24 Access Type: 31 1 – • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 75 6221I–ATARM–17-Jul-09 12.5.2 Name: Reset Controller Status Register RSTC_SR Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 25 – 17 SRCMP 9 RSTTYP 1 – 24 – 16 NRSTL 8 Access Type: 31 – 23 – 15 – 7 – 2 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Reset Type General Reset Wake Up Reset Watchdog Reset Software Reset User Reset Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 76 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 12.5.3 Name: Reset Controller Mode Register RSTC_MR Read-write 30 29 28 KEY 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 20 – 12 – 4 URSTIEN 19 – 11 18 – 10 ERSTL 3 – 2 – 1 – 0 URSTEN 17 – 9 16 – 8 27 26 25 24 Access Type: 31 • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 77 6221I–ATARM–17-Jul-09 78 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 13. AT91SAM9260 Boot Program 13.1 Description The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. Then the DataFlash Boot program is executed. It looks for a sequence of eight valid ARM exception vectors in a DataFlash connected to the SPI. All these vectors must be B-branch or LDR load register instructions except for the sixth vector. This vector is used to store the size of the image to download. If a valid sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, the DataFlash Boot program is executed on the second chip select. If no valid ARM vector sequence is found, NAND Flash Boot program is then executed. The NAND Flash Boot program looks for a sequence of eight valid ARM exception vectors. If such a sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, SAM-BA Monitor is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 13.2 Flow Diagram The Boot Program implements the algorithm in Figure 13-1. 79 6221I–ATARM–17-Jul-09 Figure 13-1. Boot Program Algorithm Flow Diagram Start Internal RC Oscillator No Large Crystal Table Yes Main Oscillator Bypass No Reduced Crystal Table Yes Input Frequency Table SPI DataFlash Boot Yes Download from DataFlash (NPCS0) Run DataFlash Boot No SPI DataFlash Boot Yes Download from DataFlash (NPCS1) Run DataFlash Boot No NAND Flash Boot Yes Download from NAND Flash Run NandFlash Boot No No USB Enumeration Successful ? No Character(s) received on DBGU ? SAM-BA Monitor Yes Run SAM-BA Monitor Yes Run SAM-BA Monitor 80 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 13.3 Device Initialization Initialization follows the steps described below: 1. FIQ Initialization 2. Stack setup for ARM supervisor mode 3. External Clock Detection 4. Switch Master Clock on Main Oscillator 5. C variable initialization 6. Main oscillator frequency detection if no external clock detected 7. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. a. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is active, Table 13-1 defines the crystals supported by the Boot Program when using the internal RC oscillator. Table 13-1. Reduced Crystal Table (MHz) OSCSEL = 0 3.0 Boot on DBGU Boot on USB Note: Yes Yes 6.0 Yes Yes 18.432 Yes Yes Other Yes No Any other crystal can be used but it prevents using the USB. b. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is bypassed, Table 13-2 defines the frequencies supported by the Boot Program when bypassing main oscillator. Input Frequencies Supported by Software Auto-detection (MHz) OSCSEL = 0 1.0 2.0 Yes Yes 6.0 Yes Yes 12.0 Yes Yes 25.0 Yes Yes 50.0 Yes Yes Other Yes No Table 13-2. Boot on DBGU Boot on USB Note: Yes Yes Any other input frequency can be used but it prevents using the USB. c. If an external 32768 Hz Oscillator is used (OSCSEL = 1), Table 13-3 defines the crystals supported by the Boot Program. Large Crystal Table (MHz) OSCSEL = 1 3.2768 4.9152 6.4 8.0 12.288 16.367667 3.6864 5.0 6.5536 9.8304 13.56 17.734470 3.84 5.24288 7.159090 10.0 14.31818 18.432 4.0 6.0 7.3728 11.05920 14.7456 20.0 Table 13-3. 3.0 4.433619 6.144 7.864320 12.0 16.0 Note: Booting either on USB or on DBGU is possible with any of these crystals. 81 6221I–ATARM–17-Jul-09 AT91SAM9260 d. If an external 32768 Hz Oscillator is used (OSCSEL = 1) and Main Oscillator is bypassed Table 13-4 defines the crystals supported by the Boot Program. Table 13-4. 3.0 4.433619 6.144 7.864320 12.0 16.0 24 40.0 Note: Input Frequencies Supported (OSCSEL = 1) 3.2768 4.9152 6.4 8.0 12.288 16.367667 25 48.0 3.6864 5.0 6.5536 9.8304 13.56 17.734470 28.224 50.0 3.84 5.24288 7.159090 10.0 14.31818 18.432 32 4.0 6.0 7.3728 11.05920 14.7456 20.0 33 Booting either on USB or on DBGU is possible with any of these input frequencies. 8. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) only if OSCSEL = 1 9. Jump to DataFlash Boot sequence through NPCS0. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 10. Jump to DataFlash Boot sequence through NPCS1. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 11. Jump to NAND Flash Boot sequence. If NAND Flash Boot succeeds, perform a remap and jump to 0x0. 12. Activation of the Instruction Cache 13. Jump to SAM-BA Monitor sequence 14. Disable the WatchDog 15. Initialization of the USB Device Port 82 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 13-2. Clocks and DBGU Configurations Start No Internal RC Oscillator? (OSCSEL = 0) Yes Scan Large Crystal Table or Input Frequencies Supported (OSCEL =1 Scan Reduced Cystal Table or Inut Frequencies Supported by Software Auto-detection MCK = PLLB/2 UDPCK = PLLB/2 "ROMBoot>" displayed on DBGU MCK = Mosc UDPCK = PLLB/2 DBGU not configured DataFlash Boot ? NANDFlash Boot ? Yes End DataFlash Boot ? NANDFlash Boot ? Yes End No No No (USB) Autobaudrate ? Yes (DBGU) MCK = Mosc UDPCK = PLLB/2 DBGU not configured MCK = PLLB UDPCK = xxxx DBGU configured End End End 83 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 13-3. Remap Action after Download Completion 0x0000_0000 Internal ROM REMAP 0x0030_0000 Internal SRAM Internal ROM 0x0010_0000 Internal SRAM 0x0000_0000 13.4 DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. After reset, the code in internal ROM is mapped at both addresses 0x0000_0000 and 0x0010_0000: 100000 100004 100008 10000c 100010 100014 100018 10001c ea000006 eafffffe ea00002f eafffffe eafffffe eafffffe eafffffe eafffffe B B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 0x1c 00000 000004 000008 00000c 000010 000014 000018 00001c ea000006 eafffffe ea00002f eafffffe eafffffe eafffffe eafffffe eafffffe B B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 0x1c 13.4.1 Valid Image Detection The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corresponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his own vector (see “Structure of ARM Vector 6” on page 85). Figure 13-4. LDR Opcode 31 1 1 1 28 27 0 0 1 I 24 23 P U 0 W 20 19 1 Rn 16 15 Rd 12 11 Addressing Mode 0 Figure 13-5. B Opcode 31 1 1 1 28 27 0 1 0 1 24 23 0 Offset (24 bits) 0 Unconditional instruction: 0xE for bits 31 to 28 84 6221I–ATARM–17-Jul-09 AT91SAM9260 Load PC with PC relative addressing instruction: – Rn = Rd = PC = 0xF – I==1 – P==1 – U offset added (U==1) or subtracted (U==0) – W==1 13.4.2 Structure of ARM Vector 6 The ARM exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below. Figure 13-6. Structure of the ARM Vector 6 31 Size of the code to download in bytes 0 13.4.2.1 Example An example of valid vectors follows: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B 0x18 B B B B B 0x20 0x04 _main 0x0c 0x10 ’. • Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal following by ‘>’ • Send a file (S): Send a file to a specified address – Address: Address in hexadecimal – Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. • Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal – NbOfBytes: Number of bytes in hexadecimal to receive – Output: ‘>’ • Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA Monitor version – Output: ROM code version, date and time (example: v1.7 Jul 13 2007 14:54:32), followed by the prompt ‘>’ 13.6.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 13.6.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: 89 6221I–ATARM–17-Jul-09 AT91SAM9260 – = 01 hex – = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – = 1’s complement of the blk#. – = 2 bytes CRC16 Figure 13-9 shows a transmission using this protocol. Figure 13-9. Xmodem Transfer Example Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device 13.6.3 USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, from Windows 98SE to Windows XP. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details. 90 6221I–ATARM–17-Jul-09 AT91SAM9260 13.6.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 13-8. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION GET_STATUS SET_FEATURE CLEAR_FEATURE Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature. The device also handles some class requests defined in the CDC class. Table 13-9. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 13.6.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAMBA Monitor commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 13.7 Hardware and Software Constraints • SAM-BA Monitor disposes of two blocks of internal SRAM. The first block is available for user code. Its size is 4K bytes The second block is used for variables and stacks. Table 13-10. User Area Address Start Address 0x200000 End Address 0x201000 Size (bytes) 4096 91 6221I–ATARM–17-Jul-09 AT91SAM9260 • The DataFlash and NAND Flash downloaded code size must be inferior to 4096 bytes. • The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). • The downloaded code must be position-independent or linked at address 0x0000_0000. • The DataFlash must be connected to NPCS0 and/or NPCS1 of the SPI. • USB requirements: – Crystal or Input Frequencies supported by Software Auto-detection. See Table 13-1, Table 13-2 and Table 13-3 on page 81 for more information. The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between SPI output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 13-11 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. For the DataFlash driven by the SPCK signal at 1 MHz, the time to download 4096 bytes is reduced to 200 ms. Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 13-11. Pins Driven during Boot Program Execution Peripheral SPI0 SPI0 SPI0 SPI0 SPI0 PIOC DBGU DBGU Pin MOSI MISO SPCK NPCS0 NPCS1 NANDCS DRXD DTXD PIO Line PIOA1 PIOA0 PIOA2 PIOA3 PIOC11 PIOC14 PIOB14 PIOB15 13.8 ROM Code Change Log Here are the evolutions between ROM Code V1.4 and V1.7: • User Reset is no longer enabled • NAND Flash Ready/Busy pin (PIOC 13) is no longer used • There are no more Timeouts in the NAND Flash Boot sequence Note: To know which ROM Code version is in the chip, use the SAM-BA Monitor command “V#” (see Table 13-8 on page 91) 92 6221I–ATARM–17-Jul-09 AT91SAM9260 14. Real-time Timer (RTT) 14.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 14.2 Embedded Characteristics – Real-time Timer 32-bit free-running back-up Counter – Integrates a 16-bit programmable prescaler running on slow clock – Alarm Register capable of generating a wake-up of the system through the Shutdown Controller 14.3 Block Diagram Figure 14-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm 14.4 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. 93 6221I–ATARM–17-Jul-09 The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). 94 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 14-2. RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 95 6221I–ATARM–17-Jul-09 14.5 Real-time Timer (RTT) User Interface Register Mapping Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read-write Read-write Read-only Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 Table 14-1. Offset 0x00 0x04 0x08 0x0C 96 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 14.5.1 Real-time Timer Mode Register Register Name: RTT_MR Access Type: 31 – 23 – 15 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RTPRES 27 – 19 – 11 26 – 18 RTTRST 10 25 – 17 RTTINCIEN 9 24 – 16 ALMIEN 8 7 6 5 4 RTPRES 3 2 1 0 • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216. RTPRES ≠ 0: The prescaler period is equal to RTPRES. • ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 97 6221I–ATARM–17-Jul-09 14.5.2 Real-time Timer Alarm Register Register Name: RTT_AR Access Type: 31 Read/Write 30 29 28 ALMV 27 26 25 24 23 22 21 20 ALMV 19 18 17 16 15 14 13 12 ALMV 11 10 9 8 7 6 5 4 ALMV 3 2 1 0 • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 14.5.3 Real-time Timer Value Register Register Name: RTT_VR Access Type: 31 Read-only 30 29 28 CRTV 27 26 25 24 23 22 21 20 CRTV 19 18 17 16 15 14 13 12 CRTV 11 10 9 8 7 6 5 4 CRTV 3 2 1 0 • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 98 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 14.5.4 Real-time Timer Status Register Register Name: RTT_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 RTTINC 24 – 16 – 8 – 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 99 6221I–ATARM–17-Jul-09 100 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 15. Watchdog Timer (WDT) 15.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 15.2 Embedded Characteristics • 16-bit key-protected only-once-Programmable Counter • Windowed, prevents the processor being in a dead-lock on the watchdog access 15.3 Block Diagram Figure 15-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WDRSTT reload 1 0 WDV 12-bit Down Counter WDT_MR WDD Current Value reload 1/128 SLCK bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished 394 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 30-15. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished 395 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 30-16. TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Read Status register TWI_THR = data to send TXRDY = 1? Yes Data to send? Yes No Read Status register Yes No TXCOMP = 1? END 396 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 30-17. TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? Yes Read Receive Holding Register No Read Status register No TXCOMP = 1? Yes END 397 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 30-18. TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END 398 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 30-19. TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) No No Last data to read but one? Yes Stop the transfer TWI_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) Read status register TXCOMP = 1? Yes END No 399 AT91SAM9260 6221I–ATARM–17-Jul-09 30.9 30.9.1 Multi-master Mode Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 30-21 on page 401. 30.9.2 Different Multi-master Modes Two multi-master modes may be distinguished: 1. TWI is considered as a Master only and will never be addressed. 2. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported. 30.9.2.1 TWI as Master Only In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 3020 on page 401). Note: The state of the bus (busy or free) is not indicated in the user interface. 30.9.2.2 TWI as Master or Slave The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below. 1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed). 2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. 400 AT91SAM9260 6221I–ATARM–17-Jul-09 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR. Figure 30-20. Programmer Sends Data While the Bus is Busy TWCK STOP sent by the master TWD DATA sent by a master Bus is busy Bus is free TWI DATA transfer Transfer is kept START sent by the TWI DATA sent by the TWI A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 30-21. Arbitration Cases TWCK TWD TWCK Data from a Master Data from TWI TWD S S S 1 1 1 0 0 11 0 1 Arbitration is lost TWI stops sending data P S S 1 1 1 0 1 Arbitration is lost The master stops sending data 0 01 0 01 1 1 Data from the TWI 00 11 Data from the master P S ARBLST Bus is busy Bus is free TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Transfer is stopped Transfer is kept Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 30-22 on page 402 gives an example of read and write operations in Multi-master mode. 401 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 30-22. Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? Yes GACC = 1 ? SVREAD = 0 ? EOSACC = 1 ? Yes TXCOMP = 1 ? Yes Yes TXRDY= 1 ? Yes Write in TWI_THR RXRDY= 0 ? Yes Read TWI_RHR GENERAL CALL TREATMENT Need to perform a master access ? Yes Decoding of the programming sequence Prog seq OK ? Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register Yes ARBLST = 1 ? Yes Yes RXRDY= 0 ? MREAD = 1 ? TXRDY= 0 ? Yes Read TWI_RHR Yes Data to read? Data to send ? Yes Write in TWI_THR Stop transfer Read Status Register Yes TXCOMP = 0 ? 402 AT91SAM9260 6221I–ATARM–17-Jul-09 30.10 Slave Mode 30.10.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 30.10.2 Application Block Diagram Figure 30-23. Slave Mode Typical Application Block Diagram VDD R TWD TWCK R Master Host with TWI Interface Host with TWI Interface Slave 1 Host with TWI Interface Slave 2 LCD Controller Slave 3 30.10.3 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode. 2. MSDIS (TWI_CR): Disable the master mode. 3. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account. 30.10.4 Receiving Data After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set. 30.10.4.1 Read Sequence In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. 403 AT91SAM9260 6221I–ATARM–17-Jul-09 Note that a STOP or a repeated START always follows a NACK. See Figure 30-24 on page 405. 30.10.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 30-25 on page 405. 30.10.4.3 Clock Synchronization Sequence In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 30-27 on page 407 and Figure 30-28 on page 408. 30.10.4.4 General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 30-26 on page 406. 30.10.4.5 30.10.5 30.10.5.1 Data Transfer Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 30-24 on page 405 describes the write operation. 404 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 30-24. Read Access Ordered by a MASTER SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK ACK/NACK from the Master A DATA NA S/Sr TWD TXRDY NACK SVACC SVREAD EOSVACC S ADR R NA DATA NA P/S/Sr SADR R A DATA A Write THR Read RHR SVREAD has to be taken into account only while SVACC is active Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 30.10.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 30-25 on page 405 describes the Write operation. Figure 30-25. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK Read RHR TWD RXRDY SVACC SVREAD EOSVACC Notes: S ADR W NA DATA NA P/S/Sr SADR W A DATA A A DATA NA S/Sr SVREAD has to be taken into account only while SVACC is active 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. 405 AT91SAM9260 6221I–ATARM–17-Jul-09 30.10.5.3 General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 30-26 on page 406 describes the General Call access. Figure 30-26. Master Performs a General Call 0000000 + W RESET command = 00000110X WRITE command = 00000100X TXD S GENERAL CALL A Reset or write DADD A DATA1 A DATA2 A New SADR A P New SADR Programming sequence GCACC Reset after read SVACC Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. 406 AT91SAM9260 6221I–ATARM–17-Jul-09 30.10.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 30-27 on page 407 describes the clock synchronization in Read mode. 30.10.5.5 Figure 30-27. Clock Synchronization in Read Mode TWI_THR DATA0 1 DATA1 DATA2 S SADR R A DATA0 A DATA1 A XXXXXXX 2 DATA2 NA S TWCK Write THR CLOCK is tied low by the TWI as long as THR is empty SCLWS TXRDY SVACC SVREAD TXCOMP As soon as a START is detected TWI_THR is transmitted to the shift register 1 2 The data is memorized in TWI_THR until a new value is written Ack or Nack from the master The clock is stretched after the ACK, the state of TWD is undefined during clock stretching Notes: 1. TXRDY is reset when data has been written in the TWI_TH to the shift register and set when this data has been acknowledged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock synchronization mechanism is started. 407 AT91SAM9260 6221I–ATARM–17-Jul-09 30.10.5.6 Clock Synchronization in Write Mode The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 30-28 on page 408 describes the clock synchronization in Read mode. Figure 30-28. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full TWD S SADR W A DATA0 A DATA1 A DATA2 NA S ADR TWI_RHR SCLWS DATA0 is not read in the RHR DATA1 DATA2 SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 SVACC SVREAD TXCOMP As soon as a START is detected Rd DATA1 Rd DATA2 Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. 408 AT91SAM9260 6221I–ATARM–17-Jul-09 30.10.5.7 30.10.5.8 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 30-29 on page 409 describes the repeated start + reversal from Read to Write mode. Figure 30-29. Repeated Start + Reversal from Read to Write Mode TWI_THR DATA0 DATA1 TWD S SADR R A DATA0 A DATA1 NA Sr SADR W A DATA2 A DATA3 A DATA3 P TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP As soon as a START is detected DATA2 Cleared after read 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 30.10.5.9 Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command.Figure 30-30 on page 409 describes the repeated start + reversal from Write to Read mode. Figure 30-30. Repeated Start + Reversal from Write to Read Mode TWI_THR DATA2 DATA3 TWD TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP S SADR W A DATA0 A DATA1 A Sr SADR R A DATA2 A DATA3 NA P DATA0 DATA1 Read TWI_RHR As soon as a START is detected Cleared after read Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 409 AT91SAM9260 6221I–ATARM–17-Jul-09 30.10.6 Read Write Flowcharts The flowchart shown in Figure 30-31 on page 410 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 30-31. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? GACC = 1 ? SVREAD = 0 ? EOSACC = 1 ? TXRDY= 1 ? Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? END Read TWI_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? Change SADR 410 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11 Two-wire Interface (TWI) User Interface Table 30-4. Offset 0x00 0x04 0x08 0x0C 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 - 0xFC Register Mapping Register Control Register Master Mode Register Slave Mode Register Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Name TWI_CR TWI_MMR TWI_SMR TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR – Access Write-only Read-write Read-write Read-write Read-write Read-only Write-only Write-only Read-only Read-only Write-only – Reset N/A 0x00000000 0x00000000 0x00000000 0x00000000 0x0000F009 N/A N/A 0x00000000 0x00000000 0x00000000 – 411 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.1 Name: Access: TWI Control Register TWI_CR Write-only Reset Value: 0x00000000 31 – 23 – 15 – 7 SWRST 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 SVDIS 28 – 20 – 12 – 4 SVEN 27 – 19 – 11 – 3 MSDIS 26 – 18 – 10 – 2 MSEN 25 – 17 – 9 – 1 STOP 24 – 16 – 8 – 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR). • STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In master read mode, if a NACK bit is received, the STOP is automatically performed. – In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. • MSEN: TWI Master Mode Enabled 0 = No effect. 1 = If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. • MSDIS: TWI Master Mode Disabled 0 = No effect. 1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. 412 AT91SAM9260 6221I–ATARM–17-Jul-09 • SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset. 413 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.2 Name: Access: TWI Master Mode Register TWI_MMR Read-write Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 29 – 21 28 – 20 27 – 19 DADR 11 – 3 – 26 – 18 25 – 17 24 – 16 14 – 6 – 13 – 5 – 12 MREAD 4 – 10 – 2 – 9 IADRSZ 1 – 8 0 – • IADRSZ: Internal Device Address Size IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address One-byte internal device address Two-byte internal device address Three-byte internal device address • MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. • DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode. 414 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.3 Name: Access: TWI Slave Mode Register TWI_SMR Read-write Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 29 – 21 28 – 20 27 – 19 SADR 11 – 3 – 26 – 18 25 – 17 24 – 16 14 – 6 – 13 – 5 – 12 – 4 – 10 – 2 – 9 8 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. 415 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.4 Name: Access: TWI Internal Address Register TWI_IADR Read-write Reset Value: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 IADR 15 14 13 12 IADR 7 6 5 4 IADR 3 2 1 0 11 10 9 8 27 – 19 26 – 18 25 – 17 24 – 16 • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. 416 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.5 Name: Access: TWI Clock Waveform Generator Register TWI_CWGR Read-write Reset Value: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 25 – 17 CKDIV 9 24 – 16 15 14 13 12 CHDIV 11 10 8 7 6 5 4 CLDIV 3 2 1 0 TWI_CWGR is only used in Master mode. • CLDIV: Clock Low Divider The SCL low period is defined as follows: T low = ( ( CLDIV × 2 CKDIV ) + 4 ) × T MCK • CHDIV: Clock High Divider The SCL high period is defined as follows: T high = ( ( CHDIV × 2 CKDIV ) + 4 ) × T MCK • CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. 417 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.6 Name: Access: TWI Status Register TWI_SR Read-only Reset Value: 0x0000F009 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 EOSACC 3 SVREAD 26 – 18 – 10 SCLWS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 7 – 6 OVRE 5 GACC 4 SVACC • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame. 1 = When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 30-8 on page 390 and in Figure 30-10 on page 391. TXCOMP used in Slave mode: 0 = As soon as a Start is detected. 1 = After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 30-27 on page 407, Figure 30-28 on page 408, Figure 30-29 on page 409 and Figure 30-30 on page 409. • RXRDY: Receive Holding Register Ready (automatically set / reset) 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 30-10 on page 391. RXRDY behavior in Slave mode can be seen in Figure 30-25 on page 405, Figure 30-28 on page 408, Figure 30-29 on page 409 and Figure 30-30 on page 409. • TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode: 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 30-8 on page 390. 418 AT91SAM9260 6221I–ATARM–17-Jul-09 TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 30-24 on page 405, Figure 30-27 on page 407, Figure 30-29 on page 409 and Figure 30-30 on page 409. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0 = Indicates that a write access is performed by a Master. 1 = Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 30-24 on page 405, Figure 30-25 on page 405, Figure 30-29 on page 409 and Figure 30-30 on page 409. • SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 30-24 on page 405, Figure 30-25 on page 405, Figure 30-29 on page 409 and Figure 30-30 on page 409. • GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0 = No General Call has been detected. 1 = A General Call has been detected. After the detection of General Call, the programmer decoded the commands that follow and the programming sequence. GACC behavior can be seen in Figure 30-26 on page 406. • OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. • NACK: Not Acknowledged (clear on read) NACK used in Master mode: 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. NACK used in Slave Read mode: 419 AT91SAM9260 6221I–ATARM–17-Jul-09 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 30-27 on page 407 and Figure 30-28 on page 408. • EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0 = A slave access is being performing. 1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 30-29 on page 409 and Figure 30-30 on page 409 420 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.7 Name: Access: TWI Interrupt Enable Register TWI_IER Write-only Reset Value: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 7 – 6 OVRE 5 GACC 4 SVACC • TXCOMP: Transmission Completed Interrupt Enable • RXRDY: Receive Holding Register Ready Interrupt Enable • TXRDY: Transmit Holding Register Ready Interrupt Enable • SVACC: Slave Access Interrupt Enable • GACC: General Call Access Interrupt Enable • OVRE: Overrun Error Interrupt Enable • NACK: Not Acknowledge Interrupt Enable • ARBLST: Arbitration Lost Interrupt Enable • SCL_WS: Clock Wait State Interrupt Enable • EOSACC: End Of Slave Access Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 421 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.8 Name: Access: TWI Interrupt Disable Register TWI_IDR Write-only Reset Value: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 7 – 6 OVRE 5 GACC 4 SVACC • TXCOMP: Transmission Completed Interrupt Disable • RXRDY: Receive Holding Register Ready Interrupt Disable • TXRDY: Transmit Holding Register Ready Interrupt Disable • SVACC: Slave Access Interrupt Disable • GACC: General Call Access Interrupt Disable • OVRE: Overrun Error Interrupt Disable • NACK: Not Acknowledge Interrupt Disable • ARBLST: Arbitration Lost Interrupt Disable • SCL_WS: Clock Wait State Interrupt Disable • EOSACC: End Of Slave Access Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 422 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.9 Name: Access: TWI Interrupt Mask Register TWI_IMR Read-only Reset Value: 0x00000000 31 – 23 – 15 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 7 – 6 OVRE 5 GACC 4 SVACC • TXCOMP: Transmission Completed Interrupt Mask • RXRDY: Receive Holding Register Ready Interrupt Mask • TXRDY: Transmit Holding Register Ready Interrupt Mask • SVACC: Slave Access Interrupt Mask • GACC: General Call Access Interrupt Mask • OVRE: Overrun Error Interrupt Mask • NACK: Not Acknowledge Interrupt Mask • ARBLST: Arbitration Lost Interrupt Mask • SCL_WS: Clock Wait State Interrupt Mask • EOSACC: End Of Slave Access Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 423 AT91SAM9260 6221I–ATARM–17-Jul-09 30.11.10 TWI Receive Holding Register Name: TWI_RHR Access: Read-only Reset Value: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • RXDATA: Master or Slave Receive Holding Data 30.11.11 TWI Transmit Holding Register Name: TWI_THR Access: Read-write Reset Value: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • TXDATA: Master or Slave Transmit Holding Data 424 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 31. Universal Synchronous Asynchronous Receiver Transmitter (USART) 31.1 Description The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 31.2 Embedded Characteristics • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Optional modem signal management DTR-DSR-DCD-RI – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the AT91SAM9260, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. 425 6221I–ATARM–17-Jul-09 The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features. Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated. 31.3 Block Diagram Figure 31-1. USART Block Diagram Peripheral DMA Controller Channel Channel USART PIO Controller RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS DTR PMC MCK MCK/DIV Modem Signals Control DSR DCD RI SLCK Baud Rate Generator SCK DIV User Interface APB 426 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 31.4 Application Block Diagram Figure 31-2. Application Block Diagram PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver USART RS232 Drivers Modem PSTN RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers Serial Port Differential Bus 427 6221I–ATARM–17-Jul-09 AT91SAM9260 31.5 I/O Lines Description I/O Line Description Description Serial Clock Transmit Serial Data Receive Serial Data Ring Indicator Data Set Ready Data Carrier Detect Data Terminal Ready Clear to Send Request to Send Type I/O I/O Input Input Input Input Output Input Output Low Low Low Low Low Low Active Level Table 31-1. Name SCK TXD RXD RI DSR DCD DTR CTS RTS 428 6221I–ATARM–17-Jul-09 AT91SAM9260 31.6 31.6.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled. All the pins of the modems may or may not be implemented on the USART. Only USART0 is fully equipped with all the modem signals. On USARTs not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART. 31.6.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. 31.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. 429 6221I–ATARM–17-Jul-09 AT91SAM9260 31.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.5 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling receiver frequency – Optional hardware handshaking – Optional modem signals management – Optional break management – Optional multidrop serial communication • High-speed 5- to 9-bit full-duplex synchronous serial communication – MSB- or LSB-first – 1 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling frequency – Optional hardware handshaking – Optional modem signals management – Optional break management – Optional multidrop serial communication • RS485 with driver control signal • ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • InfraRed IrDA Modulation and Demodulation • Test modes – Remote loopback, local loopback, automatic echo 430 6221I–ATARM–17-Jul-09 AT91SAM9260 31.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: • the Master Clock MCK • a division of the Master Clock, the divider being product dependent, but generally set to 8 • the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 31-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC SCK 31.7.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over ) CD ) This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. 431 6221I–ATARM–17-Jul-09 AT91SAM9260 31.7.1.2 Baud Rate Calculation Example Table 31-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Baud Rate Example (OVER = 0) Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 6 8 8 12 13 20 20 23 24 30 39 40 40 52 53 54 65 81 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% Error Table 31-2. Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 The baud rate is calculated with the following formula: BaudRate = MCK ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 – ⎛ --------------------------------------------------⎞ ⎝ ActualBaudRate ⎠ 31.7.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the 432 6221I–ATARM–17-Jul-09 AT91SAM9260 clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = ---------------------------------------------------------------⎛ 8 ( 2 – Over ) ⎛ CD + FP⎞ ⎞ ------ ⎠ ⎠ ⎝ ⎝ 8 The modified architecture is presented below: Figure 31-4. Fractional Baud Rate Generator FP USCLKS MCK MCK/DIV SCK Reserved CD Modulus Control FP CD SCK FIDI 0 OVER Sampling Divider 1 1 SYNC USCLKS = 3 Sampling Clock 0 Baud Rate Clock SYNC 0 1 2 3 16-bit Counter glitch-free logic >1 1 0 0 31.7.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. BaudRate = SelectedClock ------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 31.7.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: 433 6221I–ATARM–17-Jul-09 AT91SAM9260 Di B = ----- × f Fi where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 31-3. Table 31-3. DI field Di (decimal) Binary and Decimal Values for Di 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 31-4. Table 31-4. FI field Fi (decimal Binary and Decimal Values for Fi 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 31-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 31-5. Fi/Di 1 2 4 8 16 32 12 20 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 31-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. 434 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 31-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 31.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally. 31.7.3 31.7.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. 435 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 31-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 31-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 31.7.3.2 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the 436 6221I–ATARM–17-Jul-09 AT91SAM9260 transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 31-8 and Figure 31-9 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 31-8. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 31-9. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 31.7.3.3 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 31-10 illustrates a character reception in synchronous mode. 437 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 31-10. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 31.7.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 31-11. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 438 6221I–ATARM–17-Jul-09 AT91SAM9260 31.7.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 440. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 31-6 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 31-6. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 31-12 illustrates the parity bit status setting and clearing. 439 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 31-12. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 31.7.3.6 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. 31.7.3.7 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 31-13, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 440 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 31-13. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write US_THR TXRDY TXEMPTY Table 31-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 31-7. Maximum Timeguard Length Depending on Baud Rate Bit time µs 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 31.7.3.8 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: • Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state 441 6221I–ATARM–17-Jul-09 AT91SAM9260 on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 31-14 shows the block diagram of the Receiver Time-out feature. Figure 31-14. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 31-8 gives the maximum time-out period for some standard baud rates. Table 31-8. Maximum Time-out Period Bit Time µs 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 442 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 31-8. Maximum Time-out Period (Continued) Bit Time 18 17 5 Time-out 1 170 1 138 328 Baud Rate 56000 57600 200000 31.7.3.9 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 31-15. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 31.7.3.10 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 443 6221I–ATARM–17-Jul-09 AT91SAM9260 The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 31-16 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 31-16. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write US_CR TXRDY TXEMPTY 31.7.3.11 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 31.7.3.12 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 31-17. 444 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 31-17. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 31-18 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 31-18. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1 Figure 31-19 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 31-19. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 445 6221I–ATARM–17-Jul-09 AT91SAM9260 31.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 31.7.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 431). The USART connects to a smart card as shown in Figure 31-20. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 31-20. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 458 and “PAR: Parity Type” on page 459. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 31.7.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 31-21. 446 6221I–ATARM–17-Jul-09 AT91SAM9260 If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 31-22. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 31-21. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 31-22. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 31.7.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 31.7.4.4 31.7.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. 447 6221I–ATARM–17-Jul-09 AT91SAM9260 When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. 31.7.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 31-23. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 31-23. Connection to IrDA Transceivers 31.7.4.7 31.7.5 USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. 448 6221I–ATARM–17-Jul-09 AT91SAM9260 31.7.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 31-9. Table 31-9. Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s IrDA Pulse Duration Pulse Duration (3/16) 78.13 µs 19.53 µs 9.77 µs 4.88 µs 3.26 µs 1.63 µs Figure 31-24 shows an example of character transmission. Figure 31-24. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1 TXD Bit Period 3 16 Bit Period 31.7.5.2 IrDA Baud Rate Table 31-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 31-10. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 38 400 38 400 CD 2 11 18 22 4 22 36 43 6 33 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% 0.00% 1.38% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 4.88 4.88 449 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 31-10. IrDA Baud Rate Error (Continued) Peripheral Clock 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 31.7.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 31-25 illustrates the operations of the IrDA demodulator. Figure 31-25. IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 43 Pulse Rejected 5 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 450 6221I–ATARM–17-Jul-09 AT91SAM9260 31.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 31-26. Figure 31-26. Typical Connection to a RS485 Bus USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 31-27 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 31-27. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 451 6221I–ATARM–17-Jul-09 AT91SAM9260 31.7.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 31-11 gives the correspondence of the USART signals with modem connection standards. Table 31-11. Circuit References USART Pin TXD RTS DTR RXD CTS DSR DCD RI V24 2 4 20 3 5 6 8 22 CCITT 103 105 108.2 104 106 107 109 125 Direction From terminal to modem From terminal to modem From terminal to modem From modem to terminal From terminal to modem From terminal to modem From terminal to modem From terminal to modem The control of the DTR output pin is performed by writing the Control Register (US_CR) with the DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. 31.7.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 31.7.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. 452 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 31-28. Normal Mode Configuration RXD Receiver TXD Transmitter 31.7.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 31-29. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 31-29. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 31.7.8.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 31-30. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 31-30. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD 31.7.8.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 31-31. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. 453 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 31-31. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 454 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Register Mapping Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Reserved Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR – US_FIDI US_NER – US_IF – – Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write Read-write Read-write – Read-write Read-only – Read-write – – Reset – – – – 0x0 – 0x0 – 0x0 0x0 0x0 – 0x174 – – 0x0 – – Table 31-13. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x2C - 0x3C 0x0040 0x0044 0x0048 0x004C 0x5C - 0xFC 0x100 - 0x128 455 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.1 Name: USART Control Register US_CR Write-only 30 – 22 – 14 RSTNACK 6 TXEN 29 – 21 – 13 RSTIT 5 RXDIS 28 – 20 – 12 SENDA 4 RXEN 27 – 19 RTSDIS 11 STTTO 3 RSTTX 26 – 18 RTSEN 10 STPBRK 2 RSTRX 25 – 17 DTRDIS 9 STTBRK 1 – 24 – 16 DTREN 8 RSTSTA 0 – Access Type: 31 – 23 – 15 RETTO 7 TXDIS • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE and RXBRK in US_CSR. • STTBRK: Start Break 0: No effect. 456 6221I–ATARM–17-Jul-09 AT91SAM9260 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. • RETTO: Rearm Time-out 0: No effect 1: Restart Time-out • DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. • DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. • RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. 457 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.2 Name: USART Mode Register US_MR Read-write 30 – 22 – 14 CHMODE 7 CHRL 6 5 USCLKS 29 – 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 – 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Access Type: 31 – 23 – 15 18 CLKO 10 PAR 2 16 MSBF 8 SYNC 0 1 USART_MODE • USART_MODE USART_MODE 0 0 0 0 0 0 1 0 0 0 0 1 1 0 Others 0 0 1 1 0 1 0 0 1 0 1 0 0 0 Mode of the USART Normal RS485 Hardware Handshaking Modem IS07816 Protocol: T = 0 IS07816 Protocol: T = 1 IrDA Reserved • USCLKS: Clock Selection USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK/DIV (DIV = 8) Reserved SCK • CHRL: Character Length. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits 458 6221I–ATARM–17-Jul-09 AT91SAM9260 • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • PAR: Parity Type PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode • NBSTOP: Number of Stop Bits NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin. • MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. 459 6221I–ATARM–17-Jul-09 AT91SAM9260 • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. • FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). 460 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.3 Name: USART Interrupt Enable Register US_IER Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITER 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • ENDRX: End of Receive Transfer Interrupt Enable • ENDTX: End of Transmit Interrupt Enable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Enable • RXBUFF: Buffer Full Interrupt Enable • NACK: Non Acknowledge Interrupt Enable • RIIC: Ring Indicator Input Change Enable • DSRIC: Data Set Ready Input Change Enable • DCDIC: Data Carrier Detect Input Change Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable 461 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.4 Name: USART Interrupt Disable Register US_IDR Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITER 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • ENDRX: End of Receive Transfer Interrupt Disable • ENDTX: End of Transmit Interrupt Disable • OVRE: Overrun Error Interrupt Disable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Disable • RXBUFF: Buffer Full Interrupt Disable • NACK: Non Acknowledge Interrupt Disable • RIIC: Ring Indicator Input Change Disable • DSRIC: Data Set Ready Input Change Disable • DCDIC: Data Carrier Detect Input Change Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable 462 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.5 Name: USART Interrupt Mask Register US_IMR Read-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITER 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • ENDRX: End of Receive Transfer Interrupt Mask • ENDTX: End of Transmit Interrupt Mask • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Mask • RXBUFF: Buffer Full Interrupt Mask • NACK: Non Acknowledge Interrupt Mask • RIIC: Ring Indicator Input Change Mask • DSRIC: Data Set Ready Input Change Mask • DCDIC: Data Carrier Detect Input Change Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask 463 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.6 Name: USART Channel Status Register US_CSR Read-only 30 – 22 DCD 14 – 6 FRAME 29 – 21 DSR 13 NACK 5 OVRE 28 – 20 RI 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITER 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 CTS 15 – 7 PARE • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. • ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. • ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. 464 6221I–ATARM–17-Jul-09 AT91SAM9260 • FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITER: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. • TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. • RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. • NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. • RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of US_CSR. 1: At least one input change has been detected on the RI pin since the last read of US_CSR. • DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of US_CSR. 1: At least one input change has been detected on the DSR pin since the last read of US_CSR. • DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of US_CSR. 1: At least one input change has been detected on the DCD pin since the last read of US_CSR. 465 6221I–ATARM–17-Jul-09 AT91SAM9260 • CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. • RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. • DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. • DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. • CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. 466 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.7 Name: USART Receive Holding Register US_RHR Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 RXCHR 0 Access Type: 31 – 23 – 15 RXSYNH 7 • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. 467 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.8 Name: USART Transmit Holding Register US_THR Write-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 TXCHR 0 Access Type: 31 – 23 – 15 TXSYNH 7 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. 468 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.9 Name: USART Baud Rate Generator Register US_BRGR Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CD 7 6 5 4 CD 3 2 1 0 27 – 19 – 11 26 – 18 25 – 17 FP– 9 24 – 16 Access Type: 31 – 23 – 15 10 8 • CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 CD 0 1 to 65535 Baud Rate = Selected Clock/16/CD OVER = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816 • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. 469 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.10 Name: USART Receiver Time-out Register US_RTOR Read-write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 15 – 22 – 14 – 21 – 13 – 20 – 12 TO – 19 – 11 – 18 – 10 – 17 – 9 – 16 – 8 7 6 5 4 TO 3 2 1 0 • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 470 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.11 Name: USART Transmitter Timeguard Register US_TTGR Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TG 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 471 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.12 Name: USART FI DI RATIO Register US_FIDI Read-write 0x174 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FI_DI_RATIO 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 – 9 FI_DI_RATIO 1 24 – 16 – 8 Access Type: Reset Value: 31 – 23 – 15 – 7 2 0 • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 472 6221I–ATARM–17-Jul-09 AT91SAM9260 31.8.13 Name: USART Number of Errors Register US_NER Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 NB_ERRORS 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 473 6221I–ATARM–17-Jul-09 31.8.14 Name: USART IrDA FILTER Register US_IF Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IRDA_FILTER 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 474 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 32. Synchronous Serial Controller (SSC) 32.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: • CODEC’s in master or slave mode • DAC through dedicated serial interface, particularly I2S • Magnetic card reader 32.2 Embedded Characteristics • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 475 6221I–ATARM–17-Jul-09 32.3 Block Diagram Figure 32-1. Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK TD SSC Interface PIO RF RK Interrupt Control RD PMC MCK SSC Interrupt 32.4 Application Block Diagram Figure 32-2. Application Block Diagram OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management Serial AUDIO Codec Line Interface 476 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 32.5 Pin Name List I/O Lines Description Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output Table 32-1. Pin Name RF RK RD TF TK TD 32.6 32.6.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. 32.6.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. 32.6.3 32.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. 477 6221I–ATARM–17-Jul-09 Figure 32-3. SSC Functional Block Diagram Transmitter Clock Output Controller TK MCK Clock Divider TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller TX clock Frame Sync Controller TF Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register TD APB User Interface Load Shift Receiver Clock Output Controller RK RK Input TX Clock RF TF Start Selector Receive Clock RX Clock Controller Frame Sync Controller RF Receive Shift Register Receive Holding Register Receive Sync Holding Register RD RX PDC PDC Interrupt Control Load Shift AIC 32.7.1 Clock Management The transmitter clock can be generated by: • an external clock received on the TK I/O pad • the receiver clock • the internal clock divider The receiver clock can be generated by: • an external clock received on the RK I/O pad • the transmitter clock • the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 478 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 32.7.1.1 Clock Divider Figure 32-4. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 32-5. Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 Table 32-2. Maximum MCK / 2 Minimum MCK / 8190 32.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin 479 6221I–ATARM–17-Jul-09 (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 32-6. Transmitter Clock Management TK (pin) MUX Receiver Clock Tri_state Controller Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Transmitter Clock CKI CKG 32.7.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. Figure 32-7. Receiver Clock Management RK (pin) Tri-state Controller MUX Transmitter Clock Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Receiver Clock CKI CKG 480 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 32.7.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: – Master Clock divided by 2 if Receiver Frame Synchro is input – Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: – Master Clock divided by 6 if Transmit Frame Synchro is input – Master Clock divided by 2 if Transmit Frame Synchro is output 32.7.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 482. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 484. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 32-8. Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock TF SSC_TFMR.MSBF 0 SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD Start Selector Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR 0 1 SSC_TSHR SSC_TFMR.FSLEN 481 6221I–ATARM–17-Jul-09 32.7.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 482. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 484. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. Figure 32-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF SSC_RFMR.MSBF SSC_RFMR.DATNB Start Selector Receive Shift Register RD SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN SSC_RHR SSC_RFMR.DATLEN 32.7.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: • Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. • Synchronously with the transmitter/receiver • On detection of a falling/rising edge on TF/RF • On detection of a low level/high level on TF/RF • On detection of a level change or an edge on TF/RF 482 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). Figure 32-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF TD (Output) TD (Output) X BO B1 STTDLY Start = Falling Edge on TF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on TF TD (Output) TD (Output) TD (Output) TD (Output) X Start = Rising Edge on TF BO B1 STTDLY Start = Level Change on TF X BO B1 BO B1 STTDLY Start = Any Edge on TF X BO B1 BO B1 STTDLY Figure 32-11. Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF RD (Input) RD (Input) X BO B1 STTDLY Start = Falling Edge on RF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on RF RD (Input) RD (Input) RD (Input) RD (Input) X Start = Rising Edge on RF BO B1 STTDLY Start = Level Change on RF X BO B1 BO B1 STTDLY Start = Any Edge on RF X BO B1 BO B1 STTDLY 483 6221I–ATARM–17-Jul-09 32.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 32.7.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out. 32.7.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). Receive Compare Modes Figure 32-12. Receive Compare Modes RK 32.7.6 RD (Input) CMP0 CMP1 CMP2 CMP3 Start Ignored B0 B1 B2 FSLEN Up to 16 Bits (4 in This Example) STDLY DATLEN 484 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 32.7.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: • the event that starts the data transfer (START) • the delay in number of bit periods between the start event and the first data bit (STTDLY) • the length of the data (DATLEN) • the number of data to be transferred for each start event (DATNB). • the length of synchronization transferred for each start event (FSLEN) • the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. 32.7.7 485 6221I–ATARM–17-Jul-09 Table 32-3. Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR Data Frame Registers Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN SSC_RCMR SSC_RCMR PERIOD STTDLY Up to 512 Up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number of words transmitted in frame Most significant bit first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay Figure 32-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start PERIOD TF/RF (1) Start FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored TD (If FSDEN = 0) RD DATNB Note: 1. Example of input on falling edge of TF/RF. 486 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 32-14. Transmit Frame Format in Continuous Mode Start TD Data From SSC_THR DATLEN Data From SSC_THR DATLEN Default Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 32-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Data To SSC_RHR DATLEN Data To SSC_RHR DATLEN Note: 1. STTDLY is set to 0. 32.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 32.7.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. 487 6221I–ATARM–17-Jul-09 Figure 32-16. Interrupt Block Diagram SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear SSC Interrupt 32.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 32-17. Audio Application Block Diagram Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER Clock SCK Word Select WS Data SD MSB Left Channel LSB MSB Right Channel 488 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 32-18. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend Serial Data In Figure 32-19. Time Slot Application Block Diagram SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend Serial Data in 489 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9 Synchronous Serial Controller (SSC) User Interface Register Mapping Register Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Receive Compare 0 Register Receive Compare 1 Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Name SSC_CR SSC_CMR – – SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR – – SSC_RSHR SSC_TSHR SSC_RC0R SSC_RC1R SSC_SR SSC_IER SSC_IDR SSC_IMR – – Access Write-only Read-write – – Read-write Read-write Read-write Read-write Read-only Write-only – – Read-only Read-write Read-write Read-write Read-only Write-only Write-only Read-only – – Reset – 0x0 – – 0x0 0x0 0x0 0x0 0x0 – – – 0x0 0x0 0x0 0x0 0x000000CC – – 0x0 – – Table 32-4. Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100- 0x124 32.9.1 Name: SSC Control Register SSC_CR Write-only 30 – 22 – 14 – 29 – 21 – 13 – 28 – 20 – 12 – 27 – 19 – 11 – 26 – 18 – 10 – 25 – 17 – 9 TXDIS 24 – 16 – 8 TXEN Access Type: 31 – 23 – 15 SWRST 490 6221I–ATARM–17-Jul-09 AT91SAM9260 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive. If a character is currently being received, disables at end of current character reception. • TXEN: Transmit Enable 0 = No effect. 1 = Enables Transmit if TXDIS is not set. • TXDIS: Transmit Disable 0 = No effect. 1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. • SWRST: Software Reset 0 = No effect. 1 = Performs a software reset. Has priority on any other bit in SSC_CR. 491 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.2 Name: SSC Clock Mode Register SSC_CMR Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DIV 27 – 19 – 11 26 – 18 – 10 DIV 3 2 1 0 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 – 7 • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 492 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.3 Name: SSC Receive Clock Mode Register SSC_RCMR Read-write 30 29 28 PERIOD 23 22 21 20 STTDLY 15 – 7 CKG 14 – 6 13 – 5 CKI 12 STOP 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 Access Type: 31 • CKS: Receive Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock signal RK pin Reserved • CKO: Receive Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Receive Clock Output Mode None Continuous Receive Clock Receive Clock only during data transfers Reserved RK pin Input-only Output Output • CKI: Receive Clock Inversion 0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. 493 6221I–ATARM–17-Jul-09 AT91SAM9260 • CKG: Receive Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Receive Clock Gating None, continuous clock Receive Clock enabled only if RF Low Receive Clock enabled only if RF High Reserved • START: Receive Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RF signal Detection of a high level on RF signal Detection of a falling edge on RF signal Detection of a rising edge on RF signal Detection of any level change on RF signal Detection of any edge on RF signal Compare 0 Reserved • STOP: Receive Stop Selection 0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. • STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. 494 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.4 Name: SSC Receive Frame Mode Register SSC_RFMR Read-write 30 – 22 29 – 21 FSOS 13 – 5 LOOP 28 – Access Type: 31 – 23 – 15 – 7 MSBF 27 – 19 26 – 18 FSLEN 25 – 17 24 FSEDGE 16 20 14 – 6 – 12 – 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • LOOP: Loop Mode 0 = Normal operating mode. 1 = RD is driven by TD, RF is driven by TF and TK drives RK. • MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is sampled first in the bit stream. 1 = The most significant bit of the data register is sampled first in the bit stream. • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). • FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + 1 Receive Clock periods. 495 6221I–ATARM–17-Jul-09 AT91SAM9260 • FSOS: Receive Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF Pin Input-only Output Output Output Output Output Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection 496 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.5 Name: SSC Transmit Clock Mode Register SSC_TCMR Read-write 30 29 28 PERIOD 23 22 21 20 STTDLY 15 – 7 CKG 14 – 6 13 – 5 CKI 12 – 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 Access Type: 31 • CKS: Transmit Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved • CKO: Transmit Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Transmit Clock only during data transfers Reserved TK pin Input-only Output Output • CKI: Transmit Clock Inversion 0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. 497 6221I–ATARM–17-Jul-09 AT91SAM9260 • CKG: Transmit Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TF Low Transmit Clock enabled only if TF High Reserved • START: Transmit Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 - 0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. Receive start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved • STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. 498 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.6 Name: SSC Transmit Frame Mode Register SSC_TFMR Read-write 30 – 22 29 – 21 FSOS 13 – 5 DATDEF 28 – Access Type: 31 – 23 FSDEN 15 – 7 MSBF 27 – 19 26 – 18 FSLEN 25 – 17 24 FSEDGE 16 20 14 – 6 – 12 – 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. • MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is shifted out first in the bit stream. 1 = The most significant bit of the data register is shifted out first in the bit stream. • DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1). • FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + 1 Transmit Clock periods. 499 6221I–ATARM–17-Jul-09 AT91SAM9260 • FSOS: Transmit Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF Pin Input-only Output Output Output Output Output Undefined • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection 500 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.7 Name: SSC Receive Holding Register SSC_RHR Read-only 30 29 28 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Access Type: 31 • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 32.9.8 Name: SSC Transmit Holding Register SSC_THR Write-only 30 29 28 TDAT 27 26 25 24 Access Type: 31 23 22 21 20 TDAT 19 18 17 16 15 14 13 12 TDAT 11 10 9 8 7 6 5 4 TDAT 3 2 1 0 • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 501 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.9 Name: SSC Receive Synchronization Holding Register SSC_RSHR Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RSDAT 7 6 5 4 RSDAT 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 • RSDAT: Receive Synchronization Data 32.9.10 Name: SSC Transmit Synchronization Holding Register SSC_TSHR Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 TSDAT 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 7 6 5 4 TSDAT 3 2 1 0 • TSDAT: Transmit Synchronization Data 502 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.11 Name: SSC Receive Compare 0 Register SSC_RC0R Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CP0 7 6 5 4 CP0 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 • CP0: Receive Compare Data 0 503 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.12 Name: SSC Receive Compare 1 Register SSC_RC1R Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CP1 7 6 5 4 CP1 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 • CP1: Receive Compare Data 1 504 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.13 Name: SSC Status Register SSC_SR Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 RXEN 9 CP1 1 TXEMPTY 24 – 16 TXEN 8 CP0 0 TXRDY Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty. • TXEMPTY: Transmit Empty 0 = Data remains in SSC_THR or is currently transmitted from TSR. 1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. • ENDTX: End of Transmission 0 = The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1 = The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. • TXBUFE: Transmit Buffer Empty 0 = SSC_TCR or SSC_TNCR have a value other than 0. 1 = Both SSC_TCR and SSC_TNCR have a value of 0. • RXRDY: Receive Ready 0 = SSC_RHR is empty. 1 = Data has been received and loaded in SSC_RHR. • OVRUN: Receive Overrun 0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. • ENDRX: End of Reception 0 = Data is written on the Receive Counter Register or Receive Next Counter Register. 1 = End of PDC transfer when Receive Counter Register has arrived at zero. • RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. 505 6221I–ATARM–17-Jul-09 AT91SAM9260 • CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register. • TXSYN: Transmit Sync 0 = A Tx Sync has not occurred since the last read of the Status Register. 1 = A Tx Sync has occurred since the last read of the Status Register. • RXSYN: Receive Sync 0 = An Rx Sync has not occurred since the last read of the Status Register. 1 = An Rx Sync has occurred since the last read of the Status Register. • TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled. • RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled. 506 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.14 Name: SSC Interrupt Enable Register SSC_IER Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready Interrupt Enable 0 = 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Enable 0 = No effect. 1 = Enables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Buffer Empty Interrupt • RXRDY: Receive Ready Interrupt Enable 0 = No effect. 1 = Enables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Enable 0 = No effect. 1 = Enables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Enable 0 = No effect. 1 = Enables the End of Reception Interrupt. • RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the Receive Buffer Full Interrupt. 507 6221I–ATARM–17-Jul-09 AT91SAM9260 • CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt. 508 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.15 Name: SSC Interrupt Disable Register SSC_IDR Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Disable 0 = No effect. 1 = Disables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Buffer Empty Interrupt. • RXRDY: Receive Ready Interrupt Disable 0 = No effect. 1 = Disables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Disable 0 = No effect. 1 = Disables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Disable 0 = No effect. 1 = Disables the End of Reception Interrupt. • RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the Receive Buffer Full Interrupt. 509 6221I–ATARM–17-Jul-09 AT91SAM9260 • CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt. 510 6221I–ATARM–17-Jul-09 AT91SAM9260 32.9.16 Name: SSC Interrupt Mask Register SSC_IMR Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Access Type: 31 – 23 – 15 – 7 RXBUF • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled. • TXEMPTY: Transmit Empty Interrupt Mask 0 = The Transmit Empty Interrupt is disabled. 1 = The Transmit Empty Interrupt is enabled. • ENDTX: End of Transmission Interrupt Mask 0 = The End of Transmission Interrupt is disabled. 1 = The End of Transmission Interrupt is enabled. • TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The Transmit Buffer Empty Interrupt is disabled. 1 = The Transmit Buffer Empty Interrupt is enabled. • RXRDY: Receive Ready Interrupt Mask 0 = The Receive Ready Interrupt is disabled. 1 = The Receive Ready Interrupt is enabled. • OVRUN: Receive Overrun Interrupt Mask 0 = The Receive Overrun Interrupt is disabled. 1 = The Receive Overrun Interrupt is enabled. • ENDRX: End of Reception Interrupt Mask 0 = The End of Reception Interrupt is disabled. 1 = The End of Reception Interrupt is enabled. • RXBUFF: Receive Buffer Full Interrupt Mask 0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled. 511 6221I–ATARM–17-Jul-09 AT91SAM9260 • CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled. 1 = The Rx Sync Interrupt is enabled. 512 6221I–ATARM–17-Jul-09 AT91SAM9260 33. Timer Counter (TC) 33.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 33-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2 Table 33-1. Name Timer Counter Clock Assignment Definition MCK/2 MCK/8 MCK/32 MCK/128 SLCK TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 33.2 Embedded Characteristics • Two blocks of three 16-bit Timer Counter channels • Each channel can be individually programmed to perform a wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals 513 6221I–ATARM–17-Jul-09 • Each block contains two global registers that act on all three TC Channels Note: TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See Figure 7-1, “AT91SAM9260 Memory Mapping,” on page 16 for TC Block 0 and TC Block 1 base addresses. 33.3 Block Diagram Figure 33-1. Timer Counter Block Diagram Parallel I/O Controller TCLK0 TIMER_CLOCK2 TIMER_CLOCK1 TIOA1 TIMER_CLOCK3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA2 TCLK1 XC0 XC1 XC2 TC0XC0S Timer/Counter Channel 0 TIOA TIOA0 TIOB TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOB0 SYNC INT0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC Timer/Counter Channel 1 TIOA TIOA1 TIOB TIOB1 INT1 TIOA1 TIOB1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB TIOB2 SYNC TIOA2 TIOB2 INT2 Timer Counter Advanced Interrupt Controller Table 33-2. Signal Name Description Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal Block/Channel Channel Signal TIOB INT SYNC 514 AT91SAM9260 6221I–ATARM–17-Jul-09 33.4 Pin Name List Table 33-3. Pin Name TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2 TC pin list Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O 33.5 33.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 33.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. 33.5.3 515 AT91SAM9260 6221I–ATARM–17-Jul-09 33.6 33.6.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 33-4 on page 529. 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 33.6.2 33.6.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 33-2 on page 517. Each channel can independently select an internal or external clock source for its counter: • • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 33-3 on page 517 Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock 516 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 33-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TIOA1 TIOA2 XC0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 TIOA0 TCLK0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 TIOA0 TIOA2 XC0 = TCLK2 XC1 XC2 = TCLK2 TIOB1 TIOA1 SYNC TC2XC2S Timer/Counter Channel 2 XC0 = TCLK0 TIOA2 TCLK2 TIOA0 TIOA1 XC1 = TCLK1 XC2 TIOB2 SYNC Figure 33-3. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 517 AT91SAM9260 6221I–ATARM–17-Jul-09 33.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 33-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. • Figure 33-4. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 33.6.5 TC Operating Modes Each channel can independently operate in two different modes: • • Capture Mode provides measurement on signals. Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 33.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: 518 AT91SAM9260 6221I–ATARM–17-Jul-09 • • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. • The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 33.6.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 33-5 shows the configuration of the TC channel when programmed in Capture Mode. 33.6.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 33.6.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. 519 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 33-5. Capture Mode 520 TCCLKS CLKI CLKSTA CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 Q Q R S R S TIMER_CLOCK5 XC0 XC1 LDBSTOP BURST LDBDIS AT91SAM9260 Register C 1 16-bit Counter CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LDRA LDRB CPCTRG Capture Register A SWTRG Capture Register B Compare RC = CPCS LOVRS LDRAS LDRBS ETRGS COVFS TC1_SR XC2 SYNC MTIOB TIOB MTIOA If RA is not loaded or RB is Loaded Edge Detector If RA is Loaded Edge Detector TC1_IMR TIOA Timer/Counter Channel 6221I–ATARM–17-Jul-09 INT 33.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 33-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 33.6.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 521 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 33-6. Waveform Mode BURST Register A WAVSEL Register B Register C ASWTRG Compare RA = Compare RB = Compare RC = 1 16-bit Counter CLK RESET OVF SWTRG BCPC Trig BCPB WAVSEL EEVT BEEVT EEVTEDG ENETRG Edge Detector CPCS CPAS CPBS ETRGS COVFS TC1_SR MTIOB SYNC Output Controller TIOB TC1_IMR BSWTRG Timer/Counter Channel INT Output Controller 522 TCCLKS CLKSTA ACPC CLKI CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 CPCDIS Q Q R CPCSTOP AEEVT S R ACPA MTIOA TIMER_CLOCK5 S AT91SAM9260 TIOA TIOB XC0 XC1 XC2 6221I–ATARM–17-Jul-09 33.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 33-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 33-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 33-7. WAVSEL= 00 without trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 523 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 33-8. WAVSEL= 00 with trigger Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 33.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 33-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 33-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 33-9. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 524 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 33-10. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 33.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 33-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 525 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 33-11. WAVSEL = 01 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 33-12. WAVSEL = 01 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 33.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 33-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 526 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 33-13. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 33-14. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 527 AT91SAM9260 6221I–ATARM–17-Jul-09 33.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 33.6.13 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 528 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7 Timer Counter (TC) User Interface Register Mapping Offset(1) Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Block Control Register Block Mode Register Reserved TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR TC_BCR TC_BMR – Read-only Read-write Read-write (2) (2) Table 33-4. Name TC_CCR TC_CMR Access Write-only Read-write Reset – 0 0x00 + channel * 0x40 + 0x00 0x00 + channel * 0x40 + 0x04 0x00 + channel * 0x40 + 0x08 0x00 + channel * 0x40 + 0x0C 0x00 + channel * 0x40 + 0x10 0x00 + channel * 0x40 + 0x14 0x00 + channel * 0x40 + 0x18 0x00 + channel * 0x40 + 0x1C 0x00 + channel * 0x40 + 0x20 0x00 + channel * 0x40 + 0x24 0x00 + channel * 0x40 + 0x28 0x00 + channel * 0x40 + 0x2C 0xC0 0xC4 0xFC Notes: 2. Read-only if WAVE = 0 0 0 0 0 0 – – 0 – 0 – Read-write Read-only Write-only Write-only Read-only Write-only Read-write – 1. Channel index ranges from 0 to 2. 529 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.1 TC Block Control Register Register Name: TC_BCR Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 530 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.2 TC Block Mode Register Register Name: TC_BMR Access Type: 31 – 23 – 15 – 7 – Read-write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 TC2XC2S 28 – 20 – 12 – 4 27 – 19 – 11 – 3 TC1XC1S 26 – 18 – 10 – 2 25 – 17 – 9 – 1 TC0XC0S 24 – 16 – 8 – 0 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 531 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.3 TC Channel Control Register Register Name: TC_CCRx [x=0..2] Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SWTRG 25 – 17 – 9 – 1 CLKDIS 24 – 16 – 8 – 0 CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. • SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started. 532 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.4 TC Channel Mode Register: Capture Mode Register Name: TC_CMRx [x=0..2] (WAVE = 0) Access Type: 31 – 23 – 15 WAVE 7 LDBDIS Read-write 30 – 22 – 14 CPCTRG 6 LDBSTOP 29 – 21 – 13 – 5 BURST 28 – 20 – 12 – 4 11 – 3 CLKI 27 – 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 – 18 25 – 17 LDRA 8 24 – 16 • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. 533 AT91SAM9260 6221I–ATARM–17-Jul-09 • LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • LDRB: RB Loading Selection LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA 534 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.5 TC Channel Mode Register: Waveform Mode Register Name: TC_CMRx [x=0..2] (WAVE = 1) Access Type: 31 BSWTRG 23 ASWTRG 15 WAVE 7 CPCDIS 6 CPCSTOP 14 WAVSEL 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS Read-write 30 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24 • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. 535 AT91SAM9260 6221I–ATARM–17-Jul-09 • CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • EEVT: External Event Selection EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input (1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. • WAVSEL: Waveform Selection WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare • WAVE 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. 536 AT91SAM9260 6221I–ATARM–17-Jul-09 • ACPA: RA Compare Effect on TIOA ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle • ACPC: RC Compare Effect on TIOA ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle • AEEVT: External Event Effect on TIOA AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle • BCPB: RB Compare Effect on TIOB BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle 537 AT91SAM9260 6221I–ATARM–17-Jul-09 • BCPC: RC Compare Effect on TIOB BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle • BEEVT: External Event Effect on TIOB BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle 538 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.6 TC Counter Value Register Register Name: TC_CVx [x=0..2] Access Type: 31 – 23 – 15 Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CV 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 CV 3 2 1 0 • CV: Counter Value CV contains the counter value in real time. 539 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.7 TC Register A Register Name: TC_RAx [x=0..2] Access Type: 31 – 23 – 15 Read-only if WAVE = 0, Read-write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RA 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RA 3 2 1 0 • RA: Register A RA contains the Register A value in real time. 540 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.8 TC Register B Register Name: TC_RBx [x=0..2] Access Type: 31 – 23 – 15 Read-only if WAVE = 0, Read-write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RB 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RB 3 2 1 0 • RB: Register B RB contains the Register B value in real time. 33.7.9 TC Register C Register Name: TC_RCx [x=0..2] Access Type: 31 – 23 – 15 Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RC 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RC 3 2 1 0 • RC: Register C RC contains the Register C value in real time. 541 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.10 TC Status Register Register Name: TC_SRx [x=0..2] Access Type: 31 – 23 – 15 – 7 ETRGS Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 MTIOB 10 – 2 CPAS 25 – 17 MTIOA 9 – 1 LOVRS 24 – 16 CLKSTA 8 – 0 COVFS • COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. • CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. • LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. 542 AT91SAM9260 6221I–ATARM–17-Jul-09 • CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 543 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.11 TC Interrupt Enable Register Register Name: TC_IERx [x=0..2] Access Type: 31 – 23 – 15 – 7 ETRGS Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. • CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. • CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. • CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. • LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. • ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 544 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.12 TC Interrupt Disable Register Register Name: TC_IDRx [x=0..2] Access Type: 31 – 23 – 15 – 7 ETRGS Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). • CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). • CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). • CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). • ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. 545 AT91SAM9260 6221I–ATARM–17-Jul-09 33.7.13 TC Interrupt Mask Register Register Name: TC_IMRx [x=0..2] Access Type: 31 – 23 – 15 – 7 ETRGS Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. • CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. • CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. • CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. • LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. • LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. • ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 546 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 34. MultiMedia Card Interface (MCI) 34.1 Description The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. 34.2 Embedded Characteristics • One double-channel MultiMedia Card Interface • Compatibility with MultiMedia Card Specification Version 3.11 • Compatibility with SD Memory Card Specification Version 1.1 • Compatibility with SDIO Specification Version V1.0. • Card clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used • MCI has two slots, each supporting – One slot for one MultiMediaCard bus (up to 30 cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write 547 6221I–ATARM–17-Jul-09 34.3 Block Diagram Figure 34-1. Block Diagram APB Bridge PDC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCI Interface PIO MCCDB(1) MCDB0(1) MCDB1(1) MCDB2(1) Interrupt Control MCDB3(1) MCI Interrupt Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 548 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 34.4 Application Block Diagram Figure 34-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 MMC 9 SDCard 34.5 Pin Name List I/O Lines Description Pin Description Command/response Clock Data 0..3 of Slot A Data 0..3 of Slot B Type(1) I/O/PP/OD I/O I/O/PP I/O/PP Comments CMD of an MMC or SDCard/SDIO CLK of an MMC or SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO Table 34-1. Pin Name(2) MCCDA/MCCDB MCCK MCDA0 - MCDA3 MCDB0 - MCDB3 Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 34.6 34.6.1 Product Dependencies I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. 549 6221I–ATARM–17-Jul-09 AT91SAM9260 34.6.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock. Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. 34.6.3 34.7 Bus Topology Figure 34-3. Multimedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 34-2. Pin Number 1 2 3 4 5 6 7 Notes: Bus Topology Name RSV CMD VSS1 VDD CLK VSS2 DAT[0] Type(1) NC I/O/PP/OD S S I/O S I/O/PP Description Not connected Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 MCI Pin Name(2) (Slot z) MCCDz VSS VDD MCCK VSS MCDz0 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. Figure 34-4. MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK 1234567 MMC1 1234567 MMC2 1234567 MMC3 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. 550 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 34-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 34-3. Table 34-3. Pin Number 1 2 3 4 5 6 7 8 9 Notes: SD Memory Card Bus Signals Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type (1) Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 or Interrupt Data line Bit 2 MCI Pin Name(2) (Slot z) MCDz3 MCCDz VSS VDD MCCK VSS MCDz0 MCDz1 MCDz2 I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. Figure 34-6. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 SD CARD Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. 9 551 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 34-7. SD Card Bus Connections with Two Slots MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1234567 MMC1 1 2 3 4 5 6 78 SD CARD 1 MCDB0 - MCDB3 MCCDB Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. Figure 34-8. Mixing MultiMedia and SD Memory Cards with Two Slots MCDA0 MCCDA MCCK 1234567 MMC2 9 9 SD CARD 2 1234567 MMC3 MCDB0 - MCDB3 SD CARD MCCDB Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 34.8 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. 9 552 6221I–ATARM–17-Jul-09 AT91SAM9260 • Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. • Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 34-4 on page 554. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined: • Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See “Data Transfer Operation” on page 555.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 34.8.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping the MCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC E Z NID Cycles ****** Z S T CID Content Z Z Z 553 6221I–ATARM–17-Jul-09 AT91SAM9260 The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 34-4 and Table 34-5. Table 34-4. CMD Index ALL_SEND_CID Command Description Type Argument Resp Abbreviation Command Description Asks all cards to send their CID numbers on the CMD line CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Note: bcr means broadcast command with response. Table 34-5. Field Fields and Values for MCI_CMDR Command Register Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) 0 (not a special command) CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) IOSPCMD (SDIO special command) The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • Fill the argument register (MCI_ARGR) with the command argument. • Set the command register (MCI_CMDR) (see Table 34-5). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. 554 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 34-9. Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? Read response if required RETURN ERROR(1) RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). 34.8.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the mode register MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block. Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes. 555 6221I–ATARM–17-Jul-09 AT91SAM9260 Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (MCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 34.8.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 34-10), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. 556 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 34-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) No Read with PDC Yes Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght Data IN transaction • Data OUT transaction > Data OUT transaction Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake. A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. 636 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 36-4. Control Read and Write Sequences Setup Stage Data Stage Status Stage Control Read Setup TX Data OUT TX Data OUT TX Status IN TX Setup Stage Data Stage Status Stage Control Write Setup TX Data IN TX Data IN TX Status OUT TX Setup Stage Status Stage No Data Control Setup TX Status IN TX Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 36.6.2 36.6.2.1 Handling Transactions with USB V2.0 Device Peripheral Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: • The USB device automatically acknowledges the setup packet • RXSETUP is set in the UDP_CSRx register • An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. 637 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 36-5. Setup Transaction Followed by a Data OUT Transaction Setup Received Setup Handled by Firmware Data Out Received USB Bus Packets Setup PID Data Setup ACK PID Data OUT PID Data OUT NAK PID Data OUT PID Data OUT ACK PID RXSETUP Flag Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) FIFO (DPR) Content XX Data Setup XX Data OUT 36.6.2.2 Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes. Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx register (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 7. The application clears the TXCOMP in the endpoint’s UDP_CSRx. After the last packet has been sent, the application must clear TXCOMP once this has been set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer. 36.6.2.3 638 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 36-6. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus USB Bus Packets Data IN PID Data IN 1 ACK PID Data IN PID NAK PID Data IN PID Data IN 2 ACK PID TXPKTRDY Flag (UDP_CSRx) Set by the firmware Cleared by Hw Set by the firmware Cleared by Hw Interrupt Pending Payload in FIFO Cleared by Firmware DPR access by the firmware FIFO (DPR) Content Data IN 1 Load In Progress DPR access by the hardware Data IN 2 Cleared by Firmware Interrupt Pending TXCOMP Flag (UDP_CSRx) 36.6.2.4 Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 36-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints Microcontroller Write Bank 0 Endpoint 1 USB Device Read USB Bus 1st Data Payload Read and Write at the Same Time 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Data IN Packet 1st Data Payload Data IN Packet 2nd Data Payload Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 639 AT91SAM9260 6221I–ATARM–17-Jul-09 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 36-8. Data IN Transfer for Ping-pong Endpoint Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 USB Bus Packets Data IN PID Data IN ACK PID Data IN PID Data IN ACK PID TXPKTRDY Flag (UDP_MCSRx) Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (UDP_CSRx) Cleared by USB Device, Data Payload Fully Transmitted Set by USB Device Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device Interrupt Cleared by Firmware FIFO (DPR) Written by Microcontroller Bank 0 Read by USB Device Written by Microcontroller FIFO (DPR) Bank 1 Written by Microcontroller Read by USB Device Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the bandwidth. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. 640 AT91SAM9260 6221I–ATARM–17-Jul-09 36.6.2.5 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the endpoint’s UDP_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. 36.6.2.6 Figure 36-9. Data OUT Transfer for Non Ping-pong Endpoints Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT2 PID Data OUT2 NAK PID Data OUT PID Data OUT2 ACK PID RX_DATA_BK0 (UDP_CSRx) Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device FIFO (DPR) Content Data OUT 1 Written by USB Device Data OUT 1 Microcontroller Read An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO. 36.6.2.7 Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data pay- 641 AT91SAM9260 6221I–ATARM–17-Jul-09 load sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 36-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Data IN Packet nd Data Payload 2 Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_FDRx register. 642 AT91SAM9260 6221I–ATARM–17-Jul-09 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 36-11. Data OUT Transfer for Ping-pong Endpoint Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT PID Data OUT 2 ACK PID Data OUT PID Data OUT 3 A P RX_DATA_BK0 Flag (UDP_CSRx) Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 Cleared by Firmware RX_DATA_BK1 Flag (UDP_CSRx) Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 Cleared by Firmware Interrupt Pending FIFO (DPR) Bank 0 Data OUT1 Write by USB Device Data OUT 1 Read By Microcontroller Data OUT 3 Write In Progress FIFO (DPR) Bank 1 Data OUT 2 Write by USB Device Data OUT 2 Read By Microcontroller Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 36.6.2.8 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) • A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) • To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register. 2. The host receives the stall packet. 643 AT91SAM9260 6221I–ATARM–17-Jul-09 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. Figure 36-12. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 36-13. Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID FORCESTALL Set by Firmware Interrupt Pending STALLSENT Set by USB Device Cleared by Firmware 644 AT91SAM9260 6221I–ATARM–17-Jul-09 36.6.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 36-14. USB Device State Diagram Attached Hub Reset or Deconfigured Hub Configured Bus Inactive Powered Bus Activity Power Interruption Suspended Reset Bus Inactive Default Reset Address Assigned Bus Inactive Bus Activity Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Suspended Configured Bus Activity Suspended Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake up request to the host, e.g., waking up a PC by moving a USB mouse. The wake up feature is not mandatory for all devices and must be negotiated with the host. 645 AT91SAM9260 6221I–ATARM–17-Jul-09 36.6.3.1 Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors. Entering Attached State When no device is connected, the USB DP and DM signals are tied to GND by 15 KΩ pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub downstream port, the device connects a 1.5 KΩ pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 KΩ resistor to 3.3V and DM is pulled down by the 15 KΩ resistor of the host. To enable integrated pullup, the PUON bit in the UDP_TXVC register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pullup connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled. 36.6.3.2 36.6.3.3 From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmaskable flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP software must: • Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. • Configure the interrupt mask register which has been reset by the USB reset detection • Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register. In this state UDPCK and MCK must be enabled. Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSR registers have been reset. 36.6.3.4 From Default State to Address State After a set address standard device request, the USB host peripheral enters the address state. Warning: Before the device enters in address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new address, and sets the FEN bit in the UDP_FADDR register. 36.6.3.5 From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. 646 AT91SAM9260 6221I–ATARM–17-Jul-09 36.6.3.6 Entering in Suspend State When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks can be switched off. Resume event is asynchronously detected. MCK and UDPCK can be switched off in the Power Management controller and the USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP. 36.6.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the UDP_ICR register and clearing TXVDIS in the UDP_TXVC register. 36.6.3.8 Sending a Device Remote Wakeup In Suspend state it is possible to wake up the host sending an external resume. • The device must wait at least 5 ms after being entered in suspend before sending an external resume. • The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host. • The device must force a K state from 1 to 15 ms to resume the host To force a K state to the bus (DM at 3.3V and DP tied to GND), it is possible to use a transistor to connect a pullup on DM. The K state is obtained by disabling the pullup on DP and enabling the pullup on DM. This should be under the control of the application. 647 AT91SAM9260 6221I–ATARM–17-Jul-09 Figure 36-15. Board Schematic to Drive a K State 3V3 PIO 0: Force Wake UP (K State) 1: Normal Mode 1.5 K DM 648 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register. Table 36-4. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C Register Mapping Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint Control and Status Register Endpoint FIFO Data Register Reserved Transceiver Control Register Reserved Name UDP_FRM_NUM UDP_GLB_STAT UDP_FADDR – UDP_IER UDP_IDR UDP_IMR UDP_ISR UDP_ICR – UDP_RST_EP – UDP_CSR UDP_FDR – UDP_TXVC – (2) Access Read-only Read-write Read-write – Write-only Write-only Read-only Read-only Write-only – Read-write – Read-write Read-write – Read-write – Reset 0x0000_0000 0x0000_0000 0x0000_0100 – 0x0000_1200 –(1) – 0x0000_0000 – 0x0000_0000 0x0000_0000 – 0x0000_0000 – 0x030 + 0x4 * (ept_num - 1) 0x050 + 0x4 * (ept_num - 1) 0x070 0x074 0x078 - 0xFC Notes: 1. Reset values are not defined for UDP_ISR. 2. See Warning above the ”Register Mapping” on this page. 649 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.1 UDP Frame Number Register Register Name: UDP_FRM_NUM Access Type: 31 --23 – 15 – 7 30 --22 – 14 – 6 Read-only 29 --21 – 13 – 5 28 --20 – 12 – 4 FRM_NUM 27 --19 – 11 – 3 26 --18 – 10 25 --17 FRM_OK 9 FRM_NUM 1 24 --16 FRM_ERR 8 2 0 • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). • FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. • FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. 650 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.2 UDP Global State Register Register Name: UDP_GLB_STAT Access Type: 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – Read-write 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 RSMINPR 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 CONFG 24 – 16 – 8 – 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • RSMINPR: Resume Interrupt Request Read: 0 = No effect. 1 = The pin “send_resume” is set to one. A Send Resume request has been detected and the device can send a Remote Wake Up. 651 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.3 UDP Function Address Register Register Name: UDP_FADDR Access Type: 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 Read-write 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 FADD 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 FEN 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. • FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. 652 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.4 UDP Interrupt Enable Register Register Name: UDP_IER Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 Write-only 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT • EP0INT: Enable Endpoint 0 Interrupt • EP1INT: Enable Endpoint 1 Interrupt • EP2INT: Enable Endpoint 2Interrupt • EP3INT: Enable Endpoint 3 Interrupt • EP4INT: Enable Endpoint 4 Interrupt • EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. • RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt. • RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt. • EXTRSM: Enable External Resume Interrupt 0 = No effect. 1 = Enables External Resume Interrupt. • SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. • WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 653 AT91SAM9260 6221I–ATARM–17-Jul-09 1 = Enables USB bus Interrupt. 36.7.5 UDP Interrupt Disable Register Register Name: UDP_IDR Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 Write-only 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT • EP0INT: Disable Endpoint 0 Interrupt • EP1INT: Disable Endpoint 1 Interrupt • EP2INT: Disable Endpoint 2 Interrupt • EP3INT: Disable Endpoint 3 Interrupt • EP4INT: Disable Endpoint 4 Interrupt • EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. • RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt. • RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt. • EXTRSM: Disable External Resume Interrupt 0 = No effect. 1 = Disables External Resume Interrupt. • SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt 654 AT91SAM9260 6221I–ATARM–17-Jul-09 • WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt. 655 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.6 UDP Interrupt Mask Register Register Name: UDP_IMR Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 Read-only 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 BIT12 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT • EP0INT: Mask Endpoint 0 Interrupt • EP1INT: Mask Endpoint 1 Interrupt • EP2INT: Mask Endpoint 2 Interrupt • EP3INT: Mask Endpoint 3 Interrupt • EP4INT: Mask Endpoint 4 Interrupt • EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. • RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled. • RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled. • EXTRSM: Mask External Resume Interrupt 0 = UDP External Resume Interrupt is disabled. 1 = UDP External Resume Interrupt is enabled. • SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. • BIT12: UDP_IMR Bit 12 Bit 12 of UDP_IMR cannot be masked and is always read at 1. 656 AT91SAM9260 6221I–ATARM–17-Jul-09 • WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled. 657 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.7 UDP Interrupt Status Register Register Name: UDP_ISR Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 Read-only 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 ENDBUSRES 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 EXTRSM 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT • EP0INT: Endpoint 0 Interrupt Status • EP1INT: Endpoint 1 Interrupt Status • EP2INT: Endpoint 2 Interrupt Status • EP3INT: Endpoint 3 Interrupt Status • EP4INT: Endpoint 4 Interrupt Status • EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit. • RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. • RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. 658 AT91SAM9260 6221I–ATARM–17-Jul-09 The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR register. • EXTRSM: UDP External Resume Interrupt Status 0 = No UDP External Resume Interrupt pending. 1 = UDP External Resume Interrupt has been raised. • SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. • WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ICR register. 659 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.8 UDP Interrupt Clear Register Register Name: UDP_ICR Access Type: 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – Write-only 29 – 21 – 13 WAKEUP 5 – 28 – 20 – 12 ENDBUSRES 4 – 27 – 19 – 11 SOFINT 3 – 26 – 18 – 10 EXTRSM 2 – 25 – 17 – 9 RXRSM 1 – 24 – 16 – 8 RXSUSP 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt. • EXTRSM: Clear UDP External Resume Interrupt 0 = No effect. 1 = Clears UDP External Resume Interrupt. • SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. • ENDBUSRES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt. • WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt. 660 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.9 UDP Reset Endpoint Register Register Name: UDP_RST_EP Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 Read-write 29 – 21 – 13 – 5 EP5 28 – 20 – 12 – 4 EP4 27 – 19 – 11 – 3 EP3 26 – 18 – 10 – 2 EP2 25 – 17 – 9 – 1 EP1 24 – 16 – 8 – 0 EP0 • EP0: Reset Endpoint 0 • EP1: Reset Endpoint 1 • EP2: Reset Endpoint 2 • EP3: Reset Endpoint 3 • EP4: Reset Endpoint 4 • EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register. 661 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.10 UDP Endpoint Control and Status Register Register Name: UDP_CSRx [x = 0..5] Access Type: 31 – 23 30 – 22 Read-write 29 – 21 28 – 20 RXBYTECNT 27 – 19 26 25 RXBYTECNT 17 24 18 16 15 EPEDS 7 DIR 14 – 6 RX_DATA_ BK1 13 – 5 FORCE STALL 12 – 4 TXPKTRDY 11 DTGLE 3 STALLSENT ISOERROR 10 9 EPTYPE 1 RX_DATA_ BK0 8 2 RXSETUP 0 TXCOMP WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write operation before executing another write by polling the bits which must be set/cleared. //! Clear flags of UDP UDP_CSR register and waits for synchronization #define Udp_ep_clr_flag(pInterface, endpoint, flags) { \ pInterface->UDP_CSR[endpoint] &= ~(flags); \ while ( (pInterface->UDP_CSR[endpoint] & (flags)) == (flags) ); \ } //! Set flags of UDP UDP_CSR register and waits for synchronization #define Udp_ep_set_flag(pInterface, endpoint, flags) { \ pInterface->UDP_CSR[endpoint] |= (flags); \ while ( (pInterface->UDP_CSR[endpoint] & (flags)) != (flags) ); \ } Note: In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. However, RX_DATA_BLK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 3 peripheral clock cycles before accessing DPR. • TXCOMP: Generates an IN Packet with Data Previously Written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. 662 AT91SAM9260 6221I–ATARM–17-Jul-09 • RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0. 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. • RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set. • STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. 663 AT91SAM9260 6221I–ATARM–17-Jul-09 This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = Can be set to one to send the FIFO data. 1 = The data is waiting to be sent upon reception of token IN. Write: 0 = Can be written if old value is zero. 1 = A new data payload is has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. • FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. 664 AT91SAM9260 6221I–ATARM–17-Jul-09 Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. • RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO’s Bank 1. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. • DIR: Transfer Direction (only available for control endpoints) Read-write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. • EPTYPE[2:0]: Endpoint Type Read-write 000 001 101 010 110 011 111 Control Isochronous OUT Isochronous IN Bulk OUT Bulk IN Interrupt OUT Interrupt IN 665 AT91SAM9260 6221I–ATARM–17-Jul-09 • DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. • EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero). • RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register. 666 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.11 UDP FIFO Data Register Register Name: UDP_FDRx [x = 0..5] Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 Read-write 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FIFO_DATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. 667 AT91SAM9260 6221I–ATARM–17-Jul-09 36.7.12 UDP Transceiver Control Register Register Name: UDP_TXVC Access Type: 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – Read-write 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 PUON 1 – 24 – 16 – 8 TXVDIS 0 – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXCV register. • TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared. • PUON: Pullup On 0: The 1.5KΩ integrated pullup on DP is disconnected. 1: The 1.5 KΩ integrated pullup on DP is connected. NOTE: If the USB pullup is not connected on DP, the user should not write in any UDP register other than the UDP_TXVC register. This is because if DP and DM are floating at 0, or pulled down, then SE0 is received by the device with the consequence of a USB Reset. 668 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 37. USB Host Port (UHP) 37.1 Description The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.) and the USB hub can be connected to the USB host in the USB “tiered star” topology. The USB Host Port controller is fully compliant with the OpenHCI specification. The USB Host Port User Interface (registers description) can be found in the Open HCI Rev 1.0 Specification available on http://h18000.www1.hp.com/productinfo/development/openhci.html. The standard OHCI USB stack driver can be easily ported to ATMEL’s architecture in the same way all existing class drivers run without hardware specialization. This means that all standard class devices are automatically detected and available to the user application. As an example, integrating an HID (Human Interface Device) class driver provides a plug & play feature for all USB keyboards and mouses. 37.2 Embedded Characteristics • Compliance with Open HCI Rev 1.0 Specification • Compliance with USB V2.0 Full-speed and Low-speed Specification • Supports both Low-Speed 1.5 Mbps and Full-speed 12 Mbps devices • Root hub integrated with two downstream USB ports in the 217-LFBGA package • Two embedded USB transceivers • Supports power management • Operates as a master on the Matrix 669 6221I–ATARM–17-Jul-09 37.3 Block Diagram Figure 37-1. Block Diagram AHB HCI Slave Block OHCI Registers Control List Processor Block ED & TD Regsisters OHCI Root Hub Registers Embedded USB v2.0 Full-speed Transceiver USB transceiver USB transceiver DP DM DP DM Slave Root Hub and Host SIE PORT S/M PORT S/M AHB HCI Master Block Master Data FIFO 64 x 8 uhp_int MCK UHPCK Access to the USB host operational registers is achieved through the AHB bus slave interface. The OpenHCI host controller initializes master DMA transfers through the ASB bus master interface as follows: • Fetches endpoint descriptors and transfer descriptors • Access to endpoint data from system memory • Access to the HC communication area • Write status and retire transfer Descriptor Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the corresponding flag in the host controller operational registers. The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of downstream ports can be determined by the software driver reading the root hub’s operational registers. Device connection is automatically detected by the USB host port logic. USB physical transceivers are integrated in the product and driven by the root hub’s ports. Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not dedicate pads to external over current protection. 37.4 37.4.1 Product Dependencies I/O Lines DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host controller. 670 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 37.4.2 Power Management The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%. Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master clock MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to interface with the bus USB signals (Recovered 12 MHz domain). 37.4.3 Interrupt The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling USB host interrupts requires programming the AIC before configuring the UHP. 37.5 Functional Description Please refer to the Open Host Controller Interface Specification for USB Release 1.0.a. 37.5.1 Host Controller Interface There are two communication channels between the Host Controller and the Host Controller Driver. The first channel uses a set of operational registers located on the USB Host Controller. The Host Controller is the target for all communications on this channel. The operational registers contain control, status and list pointer registers. They are mapped in the memory mapped area. Within the operational register set there is a pointer to a location in the processor address space named the Host Controller Communication Area (HCCA). The HCCA is the second communication channel. The host controller is the master for all communication on this channel. The HCCA contains the head pointers to the interrupt Endpoint Descriptor lists, the head pointer to the done queue and status information associated with start-of-frame processing. The basic building blocks for communication across the interface are Endpoint Descriptors (ED, 4 double words) and Transfer Descriptors (TD, 4 or 8 double words). The host controller assigns an Endpoint Descriptor to each endpoint in the system. A queue of Transfer Descriptors is linked to the Endpoint Descriptor for the specific endpoint. 671 6221I–ATARM–17-Jul-09 Figure 37-2. USB Host Communication Channels Device Enumeration Open HCI Operational Registers Mode HCCA Status Event Frame Int Ratio Control Bulk Host Controller Communications Area Interrupt 0 Interrupt 1 Interrupt 2 ... Interrupt 31 ... ... Done Device Register in Memory Space Shared RAM = Transfer Descriptor = Endpoint Descriptor 37.5.2 Host Controller Driver Figure 37-3. USB Host Drivers User Application User Space Kernel Drivers Mini Driver Class Driver Class Driver HUB Driver USB Driver Host Controller Driver Hardware Host Controller Hardware USB Handling is done through several layers as follows: • Host controller hardware and serial engine: Transmits and receives USB data on the bus. • Host controller driver: Drives the Host controller hardware and handles the USB protocol. 672 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 • USB Bus driver and hub driver: Handles USB commands and enumeration. Offers a hardware independent interface. • Mini driver: Handles device specific commands. • Class driver: Handles standard devices. This acts as a generic driver for a class of devices, for example the HID driver. 37.6 Typical Connection Figure 37-4. Board Schematic to Interface UHP Device Controller 5V 0.20A Type A Connector 10μF HDMA or HDMB HDPA or HDPB REXT 100nF 10nF REXT A termination serial resistor must be connected to HDP and HDM. The resistor value is defined in the electrical specification of the product (REXT). 673 6221I–ATARM–17-Jul-09 674 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 38. Image Sensor Interface (ISI) 38.1 Description The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller. Internal FIFOs on the preview and codec paths are used to store the incoming data. The RGB output on the preview path is compatible with the LCD controller. This module outputs the data in RGB format (LCD compatible) and has scaling capabilities to make it compliant to the LCD display resolution (See Table 38-3 on page 678). Several input formats such as preprocessed RGB or YCbCr are supported through the data bus interface. It supports two modes of synchronization: 1. The hardware with ISI_VSYNC and ISI_HSYNC signals 2. The International Telecommunication Union Recommendation ITU-R BT.656-4 Start-ofActive-Video (SAV) and End-of-Active-Video (EAV) synchronization sequence. Using EAV/SAV for synchronization reduces the pin count (ISI_VSYNC, ISI_HSYNC not used). The polarity of the synchronization pulse is programmable to comply with the sensor signals. Table 38-1. Signal ISI_VSYNC ISI_HSYNC ISI_DATA[11..0] ISI_MCK ISI_PCK I/O Description Dir IN IN IN OUT IN Description Vertical Synchronization Horizontal Synchronization Sensor Pixel Data Master Clock Provided to the Image Sensor Pixel Clock Provided by the Image Sensor Figure 38-1. ISI Connection Example Image Sensor Image Sensor Interface data[11..0] CLK PCLK VSYNC HSYNC ISI_DATA[11..0] ISI_MCK ISI_PCK ISI_VSYNC ISI_HSYNC 675 6221I–ATARM–17-Jul-09 38.2 Embedded Characteristics • ITU-R BT. 601/656 8-bit mode external interface support • Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image • Programmable frame capture rate 38.3 Block Diagram Figure 38-2. Image Sensor Interface Block Diagram APB bus AHB bus Hsync/Len Vsync/Fen Timing Signals Interface Camera Interrupt Controller From Rx buffers Config Registers Camera Interrupt Request Line APB Interface CCIR-656 Embedded Timing Decoder(SAV/EAV) CMOS sensor Pixel input up to 12 bit YCbCr 4:2:2 8:8:8 RGB 5:6:5 APB Clock Domain AHB Clock Domain Camera AHB Master Interface Scatter Mode Support Pixel Clock Domain Frame Rate Clipping + Color Conversion YCC to RGB 2-D Image Scaler Pixel Formatter Pixel Sampling Module Rx Direct Display FIFO Core Video Arbiter CMOS sensor pixel clock input Clipping + Color Conversion RGB to YCC Packed Formatter Rx Direct Capture FIFO codec_on 38.4 Functional Description The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit data bus. This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video) and EAV (end of active video) delimiters in the data stream. The Image Sensor Interface interrupt line is generally connected to the Advanced Interrupt Controller and can trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV synchronization is used, an interrupt can be triggered on each delimiter event. For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8, RGB 5:6:5 and may be processed before the storage in memory. The data stream may be sent on both preview path and codec path if the bit CODEC_ON in the ISI_CR1 676 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 is one. To optimize the bandwidth, the codec path should be enabled only when a capture is required. In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the GS_MODE bit in the ISI_CR2 register. The codec datapath is not available when grayscale image is selected. A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames. 38.4.1 Data Timing The two data timings using horizontal and vertical synchronization and EAV/SAV sequence synchronization are shown in Figure 38-3 and Figure 38-4. In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK), after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the control register. The ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface. There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one at the end of each video data block EAV(0xFF00009D). Only data sent between EAV and SAV is captured. Horizontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count. In order to retrieve both frame and line synchronization properly, at least one line of vertical blanking is mandatory. Figure 38-3. HSYNC and VSYNC Synchronization Frame ISI_VSYNC 1 line ISI_HSYNC ISI_PCK DATA[7..0] Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr Figure 38-4. SAV and EAV Sequence Synchronization ISII_PCK DATA[7..0] FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cr Y Cb FF 00 00 EAV 9D 677 6221I–ATARM–17-Jul-09 AT91SAM9260 38.4.2 Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table 38-2. Mode Default Mode1 Mode2 Mode3 Data Ordering in YCbCr Mode Byte 0 Cb(i) Cr(i) Y(i) Y(i) Byte 1 Y(i) Y(i) Cb(i) Cr(i) Byte 2 Cr(i) Cb(i) Y(i+1) Y(i+1) Byte 3 Y(i+1) Y(i+1) Cr(i) Cb(i) Table 38-3. Mode RGB Format in Default Mode, RGB_CFG = 00, No Swap Byte Byte 0 Byte 1 D7 R7(i) G7(i) B7(i) R7(i+1) R4(i) G2(i) R4(i+1) G2(i+1) D6 R6(i) G6(i) B6(i) R6(i+1) R3(i) G1(i) R3(i+1) G1(i+1) D5 R5(i) G5(i) B5(i) R5(i+1) R2(i) G0(i) R2(i+1) G0(i+1) D4 R4(i) G4(i) B4(i) R4(i+1) R1(i) B4(i) R1(i+1) B4(i+1) D3 R3(i) G3(i) B3(i) R3(i+1) R0(i) B3(i) R0(i+1) B3(i+1) D2 R2(i) G2(i) B2(i) R2(i+1) G5(i) B2(i) G5(i+1) B2(i+1) D1 R1(i) G1(i) B1(i) R1(i+1) G4(i) B1(i) G4(i+1) B1(i+1) D0 R0(i) G0(i) B0(i) R0(i+1) G3(i) B0(i) G3(i+1) B0(i+1) RGB 8:8:8 Byte 2 Byte 3 Byte 0 Byte 1 RGB 5:6:5 Byte 2 Byte 3 Table 38-4. Mode RGB Format, RGB_CFG = 10 (Mode 2), No Swap Byte Byte 0 Byte 1 D7 G2(i) B4(i) G2(i+1) B4(i+1) D6 G1(i) B3(i) G1(i+1) B3(i+1) D5 G0(i) B2(i) G0(i+1) B2(i+1) D4 R4(i) B1(i) R4(i+1) B1(i+1) D3 R3(i) B0(i) R3(i+1) B0(i+1) D2 R2(i) G5(i) R2(i+1) G5(i+1) D1 R1(i) G4(i) R1(i+1) G4(i+1) D0 R0(i) G3(i) R0(i+1) G3(i+1) RGB 5:6:5 Byte 2 Byte 3 678 6221I–ATARM–17-Jul-09 AT91SAM9260 Table 38-5. Mode RGB Format in Default Mode, RGB_CFG = 00, Swap Activated Byte Byte 0 Byte 1 D7 R0(i) G0(i) B0(i) R0(i+1) G3(i) B0(i) G3(i+1) B0(i+1) D6 R1(i) G1(i) B1(i) R1(i+1) G4(i) B1(i) G4(i+1) B1(i+1) D5 R2(i) G2(i) B2(i) R2(i+1) G5(i) B2(i) G5(i+1) B2(i+1) D4 R3(i) G3(i) B3(i) R3(i+1) R0(i) B3(i) R0(i+1) B3(i+1) D3 R4(i) G4(i) B4(i) R4(i+1) R1(i) B4(i) R1(i+1) B4(i+1) D2 R5(i) G5(i) B5(i) R5(i+1) R2(i) G0(i) R2(i+1) G0(i+1) D1 R6(i) G6(i) B6(i) R6(i+1) R3(i) G1(i) R3(i+1) G1(i+1) D0 R7(i) G7(i) B7(i) R7(i+1) R4(i) G2(i) R4(i+1) G2(i+1) RGB 8:8:8 Byte 2 Byte 3 Byte 0 Byte 1 RGB 5:6:5 Byte 2 Byte 3 The RGB 5:6:5 input format is processed to be displayed as RGB 5:5:5 format, compliant with the 16-bit mode of the LCD controller. 38.4.3 Clocks The sensor master clock (ISI_MCK) can be generated either by the Advanced Power Management Controller (APMC) through a Programmable Clock output or by an external oscillator connected to the sensor. None of the sensors embeds a power management controller, so providing the clock by the APMC is a simple and efficient way to control power consumption of the system. Care must be taken when programming the system clock. The ISI has two clock domains, the system bus clock and the pixel clock provided by sensor. The two clock domains are not synchronized, but the system clock must be faster than pixel clock. 679 6221I–ATARM–17-Jul-09 AT91SAM9260 38.4.4 38.4.4.1 Preview Path Scaling, Decimation (Subsampling) This module resizes captured 8-bit color sensor images to fit the LCD display format. The resize module performs only downscaling. The same ratio is applied for both horizontal and vertical resize, then a fractional decimation algorithm is applied. The decimation factor is a multiple of 1/16 and values 0 to 15 are forbidden. Table 38-6. Dec value Dec Factor Decimation Factor 0->15 X 16 1 17 1.063 18 1.125 19 1.188 ... ... 124 7.750 125 7.813 126 7.875 127 7.938 Table 38-7. OUTPUT VGA 640*480 QVGA 320*240 CIF 352*288 QCIF 176*144 Decimation and Scaler Offset Values INPUT 352*288 NA 16 16 16 640*480 16 32 26 53 800*600 20 40 33 66 1280*1024 32 64 56 113 1600*1200 40 80 66 133 2048*1536 51 102 85 170 F F F F Example: Input 1280*1024 Output=640*480 Hratio = 1280/640 =2 Vratio = 1024/480 =2.1333 The decimation factor is 2 so 32/16. 680 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 38-5. Resize Examples 1280 32/16 decimation 640 1024 480 1280 56/16 decimation 352 1024 288 38.4.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: C0 0 C1 Y – Y off R = C 0 – C 2 – C 3 × C b – C boff G B C0 C4 0 C r – C roff Example of programmable value to convert YCrCb to RGB: ⎧ R = 1.164 ⋅ ( Y – 16 ) + 1.596 ⋅ ( C r – 128 ) ⎪ ⎨ G = 1.164 ⋅ ( Y – 16 ) – 0.813 ⋅ ( C r – 128 ) – 0.392 ⋅ ( C b – 128 ) ⎪ ⎩ B = 1.164 ⋅ ( Y – 16 ) + 2.107 ⋅ ( C b – 128 ) An example of programmable value to convert from YUV to RGB: ⎧ R = Y + 1.596 ⋅ V ⎪ ⎨ G = Y – 0.394 ⋅ U – 0.436 ⋅ V ⎪ B = Y + 2.032 ⋅ U ⎩ 681 6221I–ATARM–17-Jul-09 AT91SAM9260 38.4.4.3 Memory Interface Preview datapath contains a data formatter that converts 8:8:8 pixel to RGB 5:5:5 format compliant with 16-bit format of the LCD controller. In general, when converting from a color channel with more bits to one with fewer bits, formatter module discards the lower-order bits. Example: Converting from RGB 8:8:8 to RGB 5:6:5, it discards the three LSBs from the red and blue channels, and two LSBs from the green channel. When grayscale mode is enabled, two memory format are supported. One mode supports 2 pixels per word, and the other mode supports 1 pixel per word. Table 38-8. GS_MODE 0 1 Grayscale Memory Mapping Configuration for 12-bit Data DATA[31:24] P_0[11:4] P_0[11:4] DATA[23:16] P_0[3:0], 0000 P_0[3:0], 0000 DATA[15:8] P_1[11:4] 0 DATA[7:0] P_1[3:0], 0000 0 38.4.4.4 FIFO and DMA Features Both preview and Codec datapaths contain FIFOs, asynchronous buffers that are used to safely transfer formatted pixels from Pixel clock domain to AHB clock domain. A video arbiter is used to manage FIFO thresholds and triggers a relevant DMA request through the AHB master interface. Thus, depending on FIFO state, a specified length burst is asserted. Regarding AHB master interface, it supports Scatter DMA mode through linked list operation. This mode of operation improves flexibility of image buffer location and allows the user to allocate two or more frame buffers. The destination frame buffers are defined by a series of Frame Buffer Descriptors (FBD). Each FBD controls the transfer of one entire frame and then optionally loads a further FBD to switch the DMA operation at another frame buffer address. The FBD is defined by a series of two words. The first one defines the current frame buffer address, and the second defines the next FBD memory location. This DMA transfer mode is only available for preview datapath and is configured in the ISI_PPFBD register that indicates the memory location of the first FBD. The primary FBD is programmed into the camera interface controller. The data to be transferred described by an FBD requires several burst access. In the example below, the use of 2 pingpong frame buffers is described. Example The first FBD, stored at address 0x30000, defines the location of the first frame buffer. Destination Address: frame buffer ID0 0x02A000 Next FBD address: 0x30010 Second FBD, stored at address 0x30010, defines the location of the second frame buffer. Destination Address: frame buffer ID1 0x3A000 Transfer width: 32 bit Next FBD address: 0x30000, wrapping to first FBD. Using this technique, several frame buffers can be configured through the linked list. Figure 38-6 illustrates a typical three frame buffer application. Frame n is mapped to frame buffer 0, frame n+1 is mapped to frame buffer 1, frame n+2 is mapped to Frame buffer 2, further frames wrap. A codec request occurs, and the full-size 4:2:2 encoded frame is stored in a dedicated memory space. 682 6221I–ATARM–17-Jul-09 AT91SAM9260 Figure 38-6. Three Frame Buffers Application and Memory Mapping Codec Request Codec Done frame n-1 frame n frame n+1 frame n+2 frame n+3 frame n+4 Memory Space Frame Buffer 3 Frame Buffer 0 LCD Frame Buffer 1 ISI config Space 4:2:2 Image Full ROI 38.4.5 38.4.5.1 Codec Path Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: Y Cr = Cb Y off R C 3 – C 4 – C 5 × G + Cr off B –C6 –C7 C8 Cb off C0 C1 C2 An example of coefficients is given below: ⎧ Y = 0.257 ⋅ R + 0.504 ⋅ G + 0.098 ⋅ B + 16 ⎪ C = 0.439 ⋅ R – 0.368 ⋅ G – 0.071 ⋅ B + 128 ⎨r ⎪ C = – 0.148 ⋅ R – 0.291 ⋅ G + 0.439 ⋅ B + 128 ⎩b 683 6221I–ATARM–17-Jul-09 AT91SAM9260 38.4.5.2 Memory Interface Dedicated FIFO are used to support packed memory mapping. YCrCb pixel components are sent in a single 32-bit word in a contiguous space (packed). Data is stored in the order of natural scan lines. Planar mode is not supported. DMA Features Unlike preview datapath, codec datapath DMA mode does not support linked list operation. Only the CODEC_DMA_ADDR register is used to configure the frame buffer base address. 38.4.5.3 684 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5 Image Sensor Interface (ISI) User Interface ISI Memory Mapping Register Name ISI Control 1 Register ISI Control 2 Register ISI Status Register ISI Interrupt Enable Register ISI Interrupt Disable Register ISI Interrupt Mask Register Reserved Reserved ISI Preview Size Register ISI Preview Decimation Factor Register ISI Preview Primary FBD Register ISI Codec DMA Base Address Register ISI CSC YCrCb To RGB Set 0 Register ISI CSC YCrCb To RGB Set 1 Register ISI CSC RGB To YCrCb Set 0 Register ISI CSC RGB To YCrCb Set 1 Register ISI CSC RGB To YCrCb Set 2 Register Reserved Reserved Register ISI_CR1 ISI_CR2 ISI_SR ISI_IER ISI_IDR ISI_IMR ISI_PSIZE ISI_PDECF ISI_PPFBD ISI_CDBA ISI_Y2R_SET0 ISI_Y2R_SET1 ISI_R2Y_SET0 ISI_R2Y_SET1 ISI_R2Y_SET2 – – Access Read/Write Read/Write Read Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write – – Reset Value 0x00000002 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000010 0x00000000 0x00000000 0x6832cc95 0x00007102 0x01324145 0x01245e38 0x01384a4b – – Table 38-9. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44-0xF8 0xFC Note: Several parts of the ISI controller use the pixel clock provided by the image sensor (ISI_PCK). Thus the user must first program the image sensor to provide this clock (ISI_PCK) before programming the Image Sensor Controller. 685 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.1 ISI Control 1 Register Register Name: ISI_CR1 Access Type: Read/Write Reset Value: 0x00000002 31 30 29 28 SFD 23 22 21 20 SLD 15 CODEC_ON 7 CRC_SYNC 14 THMASK 6 EMB_SYNC 5 13 12 FULL 4 PIXCLK_POL 11 3 VSYNC_POL 10 9 FRATE 1 ISI_DIS 8 19 18 17 16 27 26 25 24 2 HSYNC_POL 0 ISI_RST • ISI_RST: Image sensor interface reset Write-only. Refer to bit SOFTRST in Section 38.5.3 ”ISI Status Register” on page 690 for soft reset status. 0: No action. 1: Resets the image sensor interface. • ISI_DIS: Image sensor disable: 0: Enable the image sensor interface. 1: Finish capturing the current frame and then shut down the module. • HSYNC_POL: Horizontal synchronization polarity 0: HSYNC active high. 1: HSYNC active low. • VSYNC_POL: Vertical synchronization polarity 0: VSYNC active high. 1: VSYNC active low. • PIXCLK_POL: Pixel clock polarity 0: Data is sampled on rising edge of pixel clock. 1: Data is sampled on falling edge of pixel clock. • EMB_SYNC: Embedded synchronization 0: Synchronization by HSYNC, VSYNC. 1: Synchronization by embedded synchronization sequence SAV/EAV. 686 6221I–ATARM–17-Jul-09 AT91SAM9260 • CRC_SYNC: Embedded synchronization 0: No CRC correction is performed on embedded synchronization. 1: CRC correction is performed. if the correction is not possible, the current frame is discarded and the CRC_ERR is set in the status register. • FRATE: Frame rate [0..7] 0: All the frames are captured, else one frame every FRATE+1 is captured. • FULL: Full mode is allowed 1: Both codec and preview datapaths are working simultaneously. • THMASK: Threshold mask 0: 4, 8 and 16 AHB bursts are allowed. 1: 8 and 16 AHB bursts are allowed. 2: Only 16 AHB bursts are allowed. • CODEC_ON: Enable the codec path enable bit Write-only. 0: The codec path is disabled. 1: The codec path is enabled and the next frame is captured. Refer to bit CDC_PND in “ISI Status Register” on page 690. • SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. • SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame. 687 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.2 ISI Control 2 Register Register Name: ISI_CR2 Access Type: Read/Write Reset Value: 0x0 31 RGB_CFG 23 22 21 30 29 YCC_SWAP 20 IM_HSIZE 15 COL_SPACE 7 14 RGB_SWAP 6 13 GRAYSCALE 5 12 RGB_MODE 4 IM_VSIZE 11 GS_MODE 3 10 9 IM_VSIZE 1 8 28 27 19 26 25 IM_HSIZE 17 24 18 16 2 0 • IM_VSIZE: Vertical size of the Image sensor [0..2047] Vertical size = IM_VSIZE + 1. • GS_MODE 0: 2 pixels per word. 1: 1 pixel per word. • RGB_MODE: RGB input mode 0: RGB 8:8:8 24 bits 1: RGB 5:6:5 16 bits • GRAYSCALE 0: Grayscale mode is disabled. 1: Input image is assumed to be grayscale coded. • RGB_SWAP 0: D7 -> R7 1: D0 -> R7 The RGB_SWAP has no effect when the grayscale mode is enabled. • COL_SPACE: Color space for the image data 0: YCbCr 1: RGB • IM_HSIZE: Horizontal size of the Image sensor [0..2047] Horizontal size = IM_HSIZE + 1. 688 6221I–ATARM–17-Jul-09 AT91SAM9260 • YCC_SWAP: Defines the YCC image data YCC_SWAP 00: Default 01: Mode1 10: Mode2 11: Mode3 Byte 0 Cb(i) Cr(i) Y(i) Y(i) Byte 1 Y(i) Y(i) Cb(i) Cr(i) Byte 2 Cr(i) Cb(i) Y(i+1) Y(i+1) Byte 3 Y(i+1) Y(i+1) Cr(i) Cb(i) • RGB_CFG: Defines RGB pattern when RGB_MODE is set to 1 RGB_CFG 00: Default 01: Mode1 10: Mode2 11: Mode3 Byte 0 R/G(MSB) B/G(MSB) G(LSB)/R G(LSB)/B Byte 1 G(LSB)/B G(LSB)/R B/G(MSB) R/G(MSB) Byte 2 R/G(MSB) B/G(MSB) G(LSB)/R G(LSB)/B Byte 3 G(LSB)/B G(LSB)/R B/G(MSB) R/G(MSB) If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence. 689 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.3 ISI Status Register Register Name: ISI_SR Access Type: Read Reset Value: 0x0 31 – 23 – 15 – 7 FO_P_EMP 30 – 22 – 14 – 6 FO_P_OVF 29 – 21 – 13 – 5 FO_C_OVF 28 – 20 – 12 – 4 CRC_ERR 27 – 19 – 11 – 3 CDC_PND 26 – 18 – 10 – 2 SOFTRST 25 – 17 – 9 FR_OVR 1 DIS 24 – 16 – 8 FO_C_EMP 0 SOF • SOF: Start of frame 0: No start of frame has been detected. 1: A start of frame has been detected. • DIS: Image Sensor Interface disable 0: The image sensor interface is enabled. 1: The image sensor interface is disabled and stops capturing data. The DMA controller and the core can still read the FIFOs. • SOFTRST: Software reset 0: Software reset not asserted or not completed. 1: Software reset has completed successfully. • CDC_PND: Codec request pending 0: No request asserted. 1: A codec request is pending. If a codec request is asserted during a frame, the CDC_PND bit rises until the start of a new frame. The capture is completed when the flag FO_C_EMP = 1. • CRC_ERR: CRC synchronization error 0: No CRC error in the embedded synchronization frame (SAV/EAV) 1: The CRC_SYNC is enabled in the control register and an error has been detected and not corrected. The frame is discarded and the ISI waits for a new one. • FO_C_OVF: FIFO codec overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the codec path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. 690 6221I–ATARM–17-Jul-09 AT91SAM9260 • FO_P_OVF: FIFO preview overflow 0: No overflow 1: An overrun condition has occurred in input FIFO on the preview path. The overrun happens when the FIFO is full and an attempt is made to write a new sample to the FIFO. • FO_P_EMP 0:The DMA has not finished transferring all the contents of the preview FIFO. 1:The DMA has finished transferring all the contents of the preview FIFO. • FO_C_EMP 0: The DMA has not finished transferring all the contents of the codec FIFO. 1: The DMA has finished transferring all the contents of the codec FIFO. • FR_OVR: Frame rate overrun 0: No frame overrun. 1: Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs. 691 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.4 Interrupt Enable Register Register Name: ISI_IER Access Type: Read/Write Reset Value: 0x0 31 – 23 – 15 – 7 FO_P_EMP 30 – 22 – 14 – 6 FO_P_OVF 29 – 21 – 13 – 5 FO_C_OVF 28 – 20 – 12 – 4 CRC_ERR 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SOFTRST 25 – 17 – 9 FR_OVR 1 DIS 24 – 16 – 8 FO_C_EMP 0 SOF • SOF: Start of Frame 1: Enables the Start of Frame interrupt. • DIS: Image Sensor Interface disable 1: Enables the DIS interrupt. • SOFTRST: Soft Reset 1: Enables the Soft Reset Completion interrupt. • CRC_ERR: CRC synchronization error 1: Enables the CRC_SYNC interrupt. • FO_C_OVF: FIFO codec Overflow 1: Enables the codec FIFO overflow interrupt. • FO_P_OVF: FIFO preview Overflow 1: Enables the preview FIFO overflow interrupt. • FO_P_EMP 1: Enables the preview FIFO empty interrupt. • FO_C_EMP 1: Enables the codec FIFO empty interrupt. • FR_OVR: Frame overrun 1: Enables the Frame overrun interrupt. 692 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.5 ISI Interrupt Disable Register Register Name: ISI_IDR Access Type: Read/Write Reset Value: 0x0 31 – 23 – 15 – 7 FO_P_EMP 30 – 22 – 14 – 6 FO_P_OVF 29 – 21 – 13 – 5 FO_C_OVF 28 – 20 – 12 – 4 CRC_ERR 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SOFTRST 25 – 17 – 9 FR_OVR 1 DIS 24 – 16 – 8 FO_C_EMP 0 SOF • SOF: Start of Frame 1: Disables the Start of Frame interrupt. • DIS: Image Sensor Interface disable 1: Disables the DIS interrupt. • SOFTRST 1: Disables the soft reset completion interrupt. • CRC_ERR: CRC synchronization error 1: Disables the CRC_SYNC interrupt. • FO_C_OVF: FIFO codec overflow 1: Disables the codec FIFO overflow interrupt. • FO_P_OVF: FIFO preview overflow 1: Disables the preview FIFO overflow interrupt. • FO_P_EMP 1: Disables the preview FIFO empty interrupt. • FO_C_EMP 1: Disables the codec FIFO empty interrupt. • FR_OVR 1: Disables frame overrun interrupt. 693 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.6 ISI Interrupt Mask Register Register Name: ISI_IMR Access Type: Read/Write Reset Value: 0x0 31 – 23 – 15 – 7 FO_P_EMP 30 – 22 – 14 – 6 FO_P_OVF 29 – 21 – 13 – 5 FO_C_OVF 28 – 20 – 12 – 4 CRC_ERR 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SOFTRST 25 – 17 – 9 FR_OVR 1 DIS 24 – 16 – 8 FO_C_EMP 0 SOF • SOF: Start of Frame 0: The Start of Frame interrupt is disabled. 1: The Start of Frame interrupt is enabled. • DIS: Image sensor interface disable 0: The DIS interrupt is disabled. 1: The DIS interrupt is enabled. • SOFTRST 0: The soft reset completion interrupt is enabled. 1: The soft reset completion interrupt is disabled. • CRC_ERR: CRC synchronization error 0: The CRC_SYNC interrupt is disabled. 1: The CRC_SYNC interrupt is enabled. • FO_C_OVF: FIFO codec overflow 0: The codec FIFO overflow interrupt is disabled. 1: The codec FIFO overflow interrupt is enabled. • FO_P_OVF: FIFO preview overflow 0: The preview FIFO overflow interrupt is disabled. 1: The preview FIFO overflow interrupt is enabled. • FO_P_EMP 0: The preview FIFO empty interrupt is disabled. 1: The preview FIFO empty interrupt is enabled. 694 6221I–ATARM–17-Jul-09 AT91SAM9260 • FO_C_EMP 0: The codec FIFO empty interrupt is disabled. 1: The codec FIFO empty interrupt is enabled. • FR_OVR: Frame Rate Overrun 0: The frame overrun interrupt is disabled. 1: The frame overrun interrupt is enabled. 695 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.7 ISI Preview Register Register Name: ISI_PSIZE Access Type: Read/Write Reset Value: 0x0 31 – 23 30 – 22 29 – 21 28 – 20 PREV_HSIZE 27 – 19 26 – 18 25 PREV_HSIZE 17 24 16 15 – 7 14 – 6 13 – 5 12 – 4 PREV_VSIZE 11 – 3 10 – 2 9 PREV_VSIZE 1 8 0 • PREV_VSIZE: Vertical size for the preview path Vertical Preview size = PREV_VSIZE + 1 (480 max). • PREV_HSIZE: Horizontal size for the preview path Horizontal Preview size = PREV_HSIZE + 1 (640 max). 696 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.8 ISI Preview Decimation Factor Register Register Name: ISI_PDECF Access Type: Read/Write Reset Value: 0x00000010 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 DEC_FACTOR • DEC_FACTOR: Decimation factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation. 697 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.9 ISI Preview Primary FBD Register Register Name: ISI_PPFBD Access Type: Read/Write Reset Value: 0x0 31 30 29 28 27 PREV_FBD_ADDR 20 19 PREV_FBD_ADDR 12 11 PREV_FBD_ADDR 4 3 PREV_FBD_ADDR 26 25 24 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0 • PREV_FBD_ADDR: Base address for preview frame buffer descriptor Written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used. The frame buffer is forced to word alignment. 698 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.10 ISI Codec DMA Base Address Register Register Name: ISI_CDBA Access Type: Read/Write Reset Value: 0x0 31 30 29 28 27 CODEC_DMA_ADDR 20 19 CODEC_DMA_ADDR 12 11 CODEC_DMA_ADDR 4 3 CODEC_DMA_ADDR 26 25 24 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0 • CODEC_DMA_ADDR: Base address for codec DMA This register contains codec datapath start address of buffer location. 699 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register Register Name: ISI_Y2R_SET0 Access Type: Read/Write Reset Value: 0x6832cc95 31 30 29 28 C3 27 26 25 24 23 22 21 20 C2 19 18 17 16 15 14 13 12 C1 11 10 9 8 7 6 5 4 C0 3 2 1 0 • C0: Color Space Conversion Matrix Coefficient C0 C0 element, default step is 1/128, ranges from 0 to 1.9921875. • C1: Color Space Conversion Matrix Coefficient C1 C1 element, default step is 1/128, ranges from 0 to 1.9921875. • C2: Color Space Conversion Matrix Coefficient C2 C2 element, default step is 1/128, ranges from 0 to 1.9921875. • C3: Color Space Conversion Matrix Coefficient C3 C3 element default step is 1/128, ranges from 0 to 1.9921875. 700 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.12 ISI Color Space Conversion YCrCb to RGB Set 1 Register Register Name: ISI_Y2R_SET1 Access Type: Read/Write Reset Value: 0x00007102 31 – 23 – 15 – 30 – 22 – 14 Cboff 29 – 21 – 13 Croff 28 – 20 – 12 Yoff 27 – 19 – 11 – 26 – 18 – 10 – 25 – 17 – 9 – 24 – 16 – 8 C4 C4 • C4: Color Space Conversion Matrix coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. • Yoff: Color Space Conversion Luminance default offset 0: No offset. 1: Offset = 128. • Croff: Color Space Conversion Red Chrominance default offset 0: No offset. 1: Offset = 16. • Cboff: Color Space Conversion Blue Chrominance default offset 0: No offset. 1: Offset = 16. 701 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register Register Name: ISI_R2Y_SET0 Access Type: Read/Write Reset Value: 0x01324145 31 – 23 30 – 22 29 – 21 28 – 20 C2 27 – 19 26 – 18 25 – 17 24 Roff 16 15 14 13 12 C1 11 10 9 8 7 6 5 4 C0 3 2 1 0 • C0: Color Space Conversion Matrix coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. • C1: Color Space Conversion Matrix coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875. • C2: Color Space Conversion Matrix coefficient C2 C2 element default step is 1/512, from 0 to 0.2480468875. • Roff: Color Space Conversion Red component offset 0: No offset. 1: Offset = 16. 702 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.14 ISI Color Space Conversion RGB to YCrCb Set 1 Register Register Name: ISI_R2Y_SET1 Access Type: Read/Write Reset Value: 0x01245e38 31 – 23 30 – 22 29 – 21 28 – 20 C5 27 – 19 26 – 18 25 – 17 24 Goff 16 15 14 13 12 C4 11 10 9 8 7 6 5 4 C3 3 2 1 0 • C3: Color Space Conversion Matrix coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875. • C4: Color Space Conversion Matrix coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375. • C5: Color Space Conversion Matrix coefficient C5 C1 element default step is 1/512, ranges from 0 to 0.2480468875. • Goff: Color Space Conversion Green component offset. 0: No offset. 1: Offset = 128. 703 6221I–ATARM–17-Jul-09 AT91SAM9260 38.5.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register Register Name: ISI_R2Y_SET2 Access Type: Read/Write Reset Value: 0x01384a4b 31 – 23 30 – 22 29 – 21 28 – 20 C8 27 – 19 26 – 18 25 – 17 24 Boff 16 15 14 13 12 C7 11 10 9 8 7 6 5 4 C6 3 2 1 0 • C6: Color Space Conversion Matrix coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875. • C7: Color Space Conversion Matrix coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375. • C8: Color Space Conversion Matrix coefficient C8 C8 element default step is 1/128, ranges from 0 to 0.9921875. • Boff: Color Space Conversion Blue component offset 0: No offset. 1: Offset = 128. 704 6221I–ATARM–17-Jul-09 AT91SAM9260 39. Analog-to-digital Converter (ADC) 39.1 Description The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates an 4-to-1 analog multiplexer, making possible the analog-todigital conversions of 4 analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are configurable. The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These features reduce both power consumption and processor intervention. Finally, the user can configure ADC timings, such as Startup Time and Sample & Hold Time. 39.2 Embedded Characteristics • 4-channel ADC • 10-bit 312K samples/sec. Successive Approximation Register ADC • -2/+2 LSB Integral Non Linearity, -1/+1 LSB Differential Non Linearity • Individual enable and disable of each channel • External voltage reference for better accuracy on low voltage inputs • Multiple trigger source – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels • Four analog inputs shared with digital signals 705 6221I–ATARM–17-Jul-09 39.3 Block Diagram Figure 39-1. Analog-to-Digital Converter Block Diagram Timer Counter Channels ADC Trigger Selection ADTRG Control Logic ADC Interrupt AIC VDDANA ADVREF ASB ADPDC Dedicated Analog Inputs ADUser Interface ADSuccessive Approximation Register Analog-to-Digital Converter APB Peripheral Bridge AD- Analog Inputs Multiplexed with I/O lines PIO AD- AD- GND 39.4 Signal Description ADC Pin Description Description Analog power supply Reference voltage Analog input channels External trigger Table 39-1. Pin Name VDDANA ADVREF AD0 - AD3 ADTRG 39.5 39.5.1 Product Dependencies Power Management The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the ADC clock is automatically stopped after each conversion. As the logic is small and the ADC cell can be put into Sleep Mode, the Power Management Controller has no effect on the ADC behavior. Interrupt Sources The ADC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the ADC interrupt requires the AIC to be programmed first. 39.5.2 706 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 39.5.3 Analog Inputs The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the ADC input is automatically done as soon as the corresponding channel is enabled by writing the register ADC_CHER. By default, after reset, the PIO line is configured as input with its pull-up enabled and the ADC input is connected to the GND. 39.5.4 I/O Lines The pin ADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin ADTRG to the ADC function. 39.5.5 Timer Triggers Timer Counters may or may not be used as hardware triggers depending on user requirements. Thus, some or all of the timer counters may be non-connected. 39.5.6 Conversion Performances For performance and electrical characteristics of the ADC, see the DC Characteristics section. 707 6221I–ATARM–17-Jul-09 39.6 39.6.1 Functional Description Analog-to-digital Conversion The ADC uses the ADC Clock to perform conversions. Converting a single analog value to a 10bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the “ADC Mode Register” on page 715 and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the Mode Register (ADC_MR). The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency according to the parameters given in the Product definition section. 39.6.2 Conversion Reference The conversion is performed on a full range between 0V and the reference voltage pin ADVREF. Analog inputs between these voltages convert to values based on a linear conversion. Conversion Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding ADC_CDR register and of the LDATA field in the ADC_LCDR register read 0. Moreover, when a PDC channel is connected to the ADC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized. 39.6.3 708 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 39.6.4 Conversion Results When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register (ADC_LCDR). The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR clears the DRDY bit and the EOC bit corresponding to the last converted channel. Figure 39-2. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) Conversion Time Conversion Time DRDY (ADC_SR) 709 6221I–ATARM–17-Jul-09 If the ADC_CDR is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the Status Register (ADC_SR). In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in ADC_SR. The OVRE and GOVRE flags are automatically cleared when ADC_SR is read. Figure 39-3. GOVRE and OVREx Flag Behavior Read ADC_SR ADTRG CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR ADC_CDR0 ADC_CDR1 Undefined Data Undefined Data Undefined Data Data A Data A Data B Data C Data C Data B EOC0 (ADC_SR) Conversion Conversion Read ADC_CDR0 EOC1 (ADC_SR) Conversion Read ADC_CDR1 GOVRE (ADC_SR) DRDY (ADC_SR) OVRE0 (ADC_SR) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. 710 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 39.6.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR). The selected hardware trigger is enabled with the bit TRGEN in the Mode Register (ADC_MR). If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the selected signal. If one of the TIOA outputs is selected, the corresponding Timer Counter channel must be programmed in Waveform Mode. Only one start command is necessary to initiate a conversion sequence on all the channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) Registers enable the analog channels to be enabled or disabled independently. If the ADC is used with a PDC, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly. Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can be initiated either by the hardware or the software trigger. 39.6.6 Sleep Mode and Conversion Sequencer The ADC Sleep Mode maximizes power saving by automatically deactivating the ADC when it is not being used for conversions. Sleep Mode is selected by setting the bit SLEEP in the Mode Register ADC_MR. The SLEEP mode is automatically managed by a conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. When a start conversion request occurs, the ADC is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. Triggers occurring during the sequence are not taken into account. The conversion sequencer allows automatic processing with minimum processor intervention and optimized power consumption. Conversion sequences can be performed periodically using a Timer/Counter output. The periodic acquisition of several samples can be processed automatically without any intervention of the processor thanks to the PDC. Note: The reference voltage pins always remain connected in normal mode as in sleep mode. 711 6221I–ATARM–17-Jul-09 39.6.7 ADC Timings Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register ADC_MR. In the same way, a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to program a precise value in the SHTIM field. See the section, ADC Characteristics in the product datasheet. 712 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7 Analog-to-Digital Converter (ADC) User Interface Register Mapping Register Control Register Mode Register Reserved Reserved Channel Enable Register Channel Disable Register Channel Status Register Status Register Last Converted Data Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Data Register 0 Channel Data Register 1 ... Channel Data Register 3 Reserved Name ADC_CR ADC_MR – – ADC_CHER ADC_CHDR ADC_CHSR ADC_SR ADC_LCDR ADC_IER ADC_IDR ADC_IMR ADC_CDR0 ADC_CDR1 ... ADC_CDR3 – Access Write-only Read-write – – Write-only Write-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only Read-only ... Read-only – Reset – 0x00000000 – – – – 0x00000000 0x000C0000 0x00000000 – – 0x00000000 0x00000000 0x00000000 ... 0x00000000 – Table 39-2. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 ... 0x40 0x44 - 0xFC 713 6221I–ATARM–17-Jul-09 39.7.1 ADC Control Register Register Name: ADC_CR Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 START 24 – 16 – 8 – 0 SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the ADC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion. 714 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7.2 ADC Mode Register Register Name: ADC_MR Access Type: 31 – 23 – 15 Read/Write 30 – 22 29 – 21 28 – 20 27 26 SHTIM 19 STARTUP 11 PRESCAL 18 17 16 25 24 14 13 12 10 9 8 7 – 6 – 5 SLEEP 4 LOWRES 3 2 TRGSEL 1 0 TRGEN • TRGEN: Trigger Enable TRGEN 0 1 Selected TRGEN Hardware triggers are disabled. Starting a conversion is only possible by software. Hardware trigger selected by TRGSEL field is enabled. • TRGSEL: Trigger Selection TRGSEL 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected TRGSEL TIO Output of the Timer Counter Channel 0 TIO Output of the Timer Counter Channel 1 TIO Output of the Timer Counter Channel 2 Reserved Reserved Reserved External trigger Reserved • LOWRES: Resolution LOWRES 0 1 Selected Resolution 10-bit resolution 8-bit resolution • SLEEP: Sleep Mode SLEEP 0 1 Selected Mode Normal Mode Sleep Mode 715 6221I–ATARM–17-Jul-09 AT91SAM9260 • PRESCAL: Prescaler Rate Selection ADCClock = MCK / ( (PRESCAL+1) * 2 ) • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock • SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+1) / ADCClock 716 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7.3 ADC Channel Enable Register Register Name: ADC_CHER Access Type: 31 – 23 – 15 – 7 - Write-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 CH3 26 – 18 – 10 – 2 CH2 25 – 17 – 9 – 1 CH1 24 – 16 – 8 – 0 CH0 • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. 39.7.4 ADC Channel Disable Register Register Name: ADC_CHDR Access Type: 31 – 23 – 15 – 7 - Write-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 CH3 26 – 18 – 10 – 2 CH2 25 – 17 – 9 – 1 CH1 24 – 16 – 8 – 0 CH0 • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in ADC_SR are unpredictable. 717 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7.5 ADC Channel Status Register Register Name: ADC_CHSR Access Type: 31 – 23 – 15 – 7 - Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 CH3 26 – 18 – 10 – 2 CH2 25 – 17 – 9 – 1 CH1 24 – 16 – 8 – 0 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled. 718 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7.6 ADC Status Register Register Name: ADC_SR Access Type: 31 – 23 – 15 7 - Read-only 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 4 27 – 19 RXBUFF 11 OVRE3 3 EOC3 26 – 18 ENDRX 10 OVRE2 2 EOC2 25 – 17 GOVRE 9 OVRE1 1 EOC1 24 – 16 DRDY 8 OVRE0 0 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. 1 = Corresponding analog channel is enabled and conversion is complete. • OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of ADC_SR. 1 = There has been an overrun error on the corresponding channel since the last read of ADC_SR. • DRDY: Data Ready 0 = No data has been converted since the last read of ADC_LCDR. 1 = At least one data has been converted and is available in ADC_LCDR. • GOVRE: General Overrun Error 0 = No General Overrun Error occurred since the last read of ADC_SR. 1 = At least one General Overrun Error has occurred since the last read of ADC_SR. • ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in ADC_RCR or ADC_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in ADC_RCR or ADC_RNCR. • RXBUFF: RX Buffer Full 0 = ADC_RCR or ADC_RNCR have a value other than 0. 1 = Both ADC_RCR and ADC_RNCR have a value of 0. 719 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7.7 ADC Last Converted Data Register Register Name: ADC_LCDR Access Type: 31 – 23 – 15 – 7 Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 LDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 LDATA 1 0 24 – 16 – 8 • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 39.7.8 ADC Interrupt Enable Register Register Name: ADC_IER Access Type: 31 – 23 – 15 7 - Write-only 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 4 27 – 19 RXBUFF 11 OVRE3 3 EOC3 26 – 18 ENDRX 10 OVRE2 2 EOC2 25 – 17 GOVRE 9 OVRE1 1 EOC1 24 – 16 DRDY 8 OVRE0 0 EOC0 • EOCx: End of Conversion Interrupt Enable x • OVREx: Overrun Error Interrupt Enable x • DRDY: Data Ready Interrupt Enable • GOVRE: General Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 720 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7.9 ADC Interrupt Disable Register Register Name: ADC_IDR Access Type: 31 – 23 – 15 7 - Write-only 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 4 27 – 19 RXBUFF 11 OVRE3 3 EOC3 26 – 18 ENDRX 10 OVRE2 2 EOC2 25 – 17 GOVRE 9 OVRE1 1 EOC1 24 – 16 DRDY 8 OVRE0 0 EOC0 • EOCx: End of Conversion Interrupt Disable x • OVREx: Overrun Error Interrupt Disable x • DRDY: Data Ready Interrupt Disable • GOVRE: General Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 721 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7.10 ADC Interrupt Mask Register Register Name: ADC_IMR Access Type: 31 – 23 – 15 7 - Read-only 30 – 22 – 14 6 29 – 21 – 13 5 28 – 20 – 12 4 27 – 19 RXBUFF 11 OVRE3 3 EOC3 26 – 18 ENDRX 10 OVRE2 2 EOC2 25 – 17 GOVRE 9 OVRE1 1 EOC1 24 – 16 DRDY 8 OVRE0 0 EOC0 • EOCx: End of Conversion Interrupt Mask x • OVREx: Overrun Error Interrupt Mask x • DRDY: Data Ready Interrupt Mask • GOVRE: General Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 722 6221I–ATARM–17-Jul-09 AT91SAM9260 39.7.11 ADC Channel Data Register Register Name: ADC_CDRx Access Type: 31 – 23 – 15 – 7 Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 DATA 1 0 24 – 16 – 8 • DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled. 723 6221I–ATARM–17-Jul-09 724 AT91SAM9260 6221I–ATARM–17-Jul-09 AT91SAM9260 40. AT91SAM9260 Electrical Characteristics 40.1 Absolute Maximum Ratings Absolute Maximum Ratings* *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 40-1. Operating Temperature (Industrial)........... -40° C to +85° C Storage Temperature ............................... -60°C to +150°C Voltage on Input Pins with Respect to Ground .. -0.3V to VDDIO+0.3V(+4V max) Maximum Operating Voltage (VDDCORE, VDDPLL and VDDBU)........................... 2.0V Maximum Operating Voltage (VDDIOM and VDDIOP) ............................................. 4.0V Total DC Output Current on all I/O lines ................ 350 mA 40.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified. Table 40-2. Symbol VVDDCORE VVDDBU VVDDPLL VVDDIOM VVDDIOP0 VVDDIOP1 VVDDANA VIL VIH DC Characteristics Parameter DC Supply Core DC Supply Backup DC Supply PLL DC Supply Memory I/Os DC Supply Peripheral I/Os DC Supply Peripheral I/Os DC Supply Analog Input Low-level Voltage VVDDIO from 3.0V to 3.6V VVDDIO from 1.65V to 1.95V VVDDIO from 3.0V to 3.6V VVDDIO from 1.65V to 1.95V IO Max, VVDDIO from 3.0V to 3.6V CMOS (IO