AT91SAM9263B-CU

Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions, Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 220 MIPS at 200 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support – Mid-level Implementation Embedded Trace Macrocell™ Bus Matrix – Nine 32-bit-layer Matrix, Allowing a Total of 28.8 Gbps of On-chip Bus Bandwidth – Boot Mode Select Option, Remap Command Embedded Memories – One 128 Kbyte Internal ROM, Single-cycle Access at Maximum Bus Matrix Speed – One 80 Kbyte Internal SRAM, Single-cycle Access at Maximum Processor or Bus Matrix Speed – One 16 Kbyte Internal SRAM, Single-cycle Access at Maximum Bus Matrix Speed Dual External Bus Interface (EBI0 and EBI1) – EBI0 Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® – EBI1 Supports SDRAM, Static Memory and ECC-enabled NAND Flash DMA Controller (DMAC) – Acts as one Bus Matrix Master – Embeds 2 Unidirectional Channels with Programmable Priority, Address Generation, Channel Buffering and Control Twenty Peripheral DMA Controller Channels (PDC) LCD Controller – Supports Passive or Active Displays – Up to 24 bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Supports Virtual Screen Buffers Two D Graphics Accelerator – Line Draw, Block Transfer, Clipping, Commands Queuing Image Sensor Interface – ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format USB 2.0 Full Speed (12 Mbits per second) Host Double Port – Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels USB 2.0 Full Speed (12 Mbits per second) Device Port – On-chip Transceiver, 2,432-byte Configurable Integrated DPRAM Ethernet MAC 10/100 Base-T – Media Independent Interface or Reduced Media Independent Interface – 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit Fully-featured System Controller, including – Reset Controller, Shutdown Controller – Twenty 32-bit Battery Backup Registers for a Total of 80 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Double Real-time Timer • • AT91 ARM Thumb Microcontrollers AT91SAM9263 Preliminary Summary • • • • • • • • • • NOTE: This is a summary document. The complete document is available on the Atmel website at www.atmel.com. 6249HS–ATARM–27-Jul-09 • Reset Controller (RSTC) – Based on Two Power-on Reset Cells, Reset Source Identification and Reset Output Control • Shutdown Controller (SHDWC) – Programmable Shutdown Pin Control and Wake-up Circuitry • Clock Generator (CKGR) – 32768Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 3 to 20 MHz On-chip Oscillator and Two Up to 240 MHz PLLs Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention – Mode for General Purpose Two-wire UART Serial Communication Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Two Real-time Timers (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Five 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC, PIOD and PIOE) – 160 Programmable I/O Lines Multiplexed with Up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output One Part 2.0A and Part 2.0B-compliant CAN Controller – 16 Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter Two Multimedia Card Interface (MCI) – SDCard/SDIO and MultiMediaCard™ Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC – Two SDCard Slots Support on eAch Controller Two Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One AC97 Controller (AC97C) – 6-channel Single AC97 Analog Front End Interface, Slot Assigner Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects One Three-channel 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) One Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel® EEPROMs Supported • • • • • • • • • • • • • • • • 2 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary • IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins • Required Power Supplies – 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and VDDPLL – 2.7V to 3.6V for VDDIOP0 (Peripheral I/Os) – 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM0/VDDIOM1 (Memory I/Os) • Available in a 324-ball TFBGA Green Package 1. Description The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent bottlenecks, thus guaranteeing maximum performance. The AT91SAM9263 embeds an LCD Controller supported by a Two D Graphics Controller and a 2-channel DMA Controller, and one Image Sensor Interface. It also integrates several standard peripherals, such as USART, SPI, TWI, Timer Counters, PWM Generators, Multimedia Card interface and one CAN Controller. When coupled with an external GPS engine, the AT91SAM9263 provides the ideal solution for navigation systems. 3 6249HS–ATARM–27-Jul-09 Figure 2-1. L N T TDRS T TDI O TM TC S K RT JT CK AG SE TC TS LK TPYN C TPS0 K -TP BM 0-T S2 S PK1 5 LC LCDD 0 LCDV -LC S LCDH YN DD S LCDD YNC 23 O LCDD TCC D EN K C ET C ETXCK ECXEN-ER R-X ER S- ETX CK E ERXE CO ER ERE RL FC ET X0- -ER K XE X EM 0-E RX DV 3 ED T M C X3 EF DIO 10 0 H D H PA D M HA D H PB D M B 2. AT91SAM9263 Block Diagram D B0 -D DA C B3 0- DB DA C3 DA C K TW C TW D T C RTS0- K C SC S0- TS R2 R K0- TS DS2 X TX 0- CK2 DR 0- DX TX 2 D 2 CA C NT AN X R NX P N CS P3 N CS P2 N CS PC 1 SP S0 M CK O M SI PW IS O M 0PW TC M L 3 TK IO 0-T TI A0 CL O -T K2 B 0- IOA T2 AC IOB 2 AC97C AC 97 K F AC97RS 9X TK 7TX TF0-T TD 0-TK1 R 0-T F1 D DD M AR RF0-R 1 Q R 0- D1 0_ K R D 0-R F1 MK AR 1 Q 3 D D DP D M 6249HS–ATARM–27-Jul-09 SPI0_, SPI1_ I MCI0_, MCI_1 SI I _D SI 0 _P IS -IS C I I_ K IS _HS D1 I_ Y 1 VN IS SYNC I_ C M C K 4 JTAG Boundary Scan Transc. Transc. MASTER SLAVE TST System Controller EBI0_ EBI0 In-Circuit Emulator FIQ IRQ0-IRQ1 AIC ARM926EJ-S Processor ETM ICache 16K bytes MMU DCache 16K bytes DBGU TCM Interface LCD Controller 10/100 Ethernet MAC USB OHCI FIFO DMA DMA SDRAM Controller FIFO LUT FIFO DMA CompactFlash NAND Flash DRXD DTXD PCK0-PCK3 ITCM DTCM Bus Interface PDC PMC I D AT91SAM9263 Block Diagram PLLRCA PLLA PLLRCB Fast SRAM 80 Kbytes PLLB XIN XOUT OSC WDT PIT 9-layer Bus Matrix PIOA PIOB DMA Peripheral Bridge PIOC SRAM 16 Kbytes VDDCORE Static Memory Controller ECC Controller VDDBU 20GPREG RTT0 AT91SAM9263 Preliminary 2-channel D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15, A18-A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD NWR0/NWE NWR1/NBS1 NWR3/NBS3 SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE NWAIT A23-A24 NCS4/CFCS0 NCS5/CFCS1 NCS3/NANDCS A25/CFRNW CFCE1-CFCE2 D16-D31 NCS2 PIOD 20-channel Peripheral DMA XIN32 XOUT32 OSC RTT1 SHDN WKUP SHDWC POR PIOE ROM 128 Kbytes APB DMA EBI1_ EBI1 NAND Flash RSTC VDDCORE 2D Graphics Controller POR NRST SDRAM Controller PDC SSC0 SSC1 USB Device Port DMA PDC PDC CAN SPI0 SPI1 PWMC TC0 TC1 TC2 AC97C USART0 USART1 USART2 PDC PDC MCI0 MCI1 TWI Image Sensor Interface Static Memory Controller ECC Controller Transc. D0-D15 A0/NBS0 A1/NWR2 A2-A15/A18-A20 A16/BA0 A17/BA1 NCS0 NRD NWR0/NWE NWR1/NBS1 SDCK A21/NANDALE A22/NANDCLE NWAIT NWR3/NBS3 NCS1/SDCS NCS2/NANDCS D16-D31 SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE AT91SAM9263 Preliminary 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Name Signal Description List Function Power Supplies Type Active Level Comments VDDIOM0 VDDIOM1 VDDIOP0 VDDIOP1 VDDBU VDDPLL VDDOSC VDDCORE GND GNDPLL GNDBU EBI0 I/O Lines Power Supply EBI1 I/O Lines Power Supply Peripherals I/O Lines Power Supply Peripherals I/O Lines Power Supply Backup I/O Lines Power Supply PLL Power Supply Oscillator Power Supply Core Chip Power Supply Ground PLL Ground Backup Ground Power Power Power Power Power Power Power Power Ground Ground Ground 1.65V to 3.6V 1.65V to 3.6V 2.7V to 3.6V 1.65V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V Clocks, Oscillators and PLLs XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output PLL A Filter PLL B Filter Programmable Clock Output Input Output Input Output Input Input Output Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-up Input ICE and JTAG NTRST TCK TDI TDO TMS JTAGSEL RTCK Test Reset Signal Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Return Test Clock Input Input Input Output Input Input Output No pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. Low Pull-up resistor No pull-up resistor No pull-up resistor Output Input Driven at 0V only. Do not tie over VDDBU. Accepts between 0V and VDDBU. 5 6249HS–ATARM–27-Jul-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Embedded Trace Module - ETM Active Level Comments TSYNC TCLK TPS0 - TPS2 TPK0 - TPK15 Trace Synchronization Signal Trace Clock Trace ARM Pipeline Status Trace Packet Port Reset/Test Output Output Output Output NRST TST BMS Microcontroller Reset Test Mode Select Boot Mode Select Debug Unit - DBGU I/O Input Input Low Pull-up resistor Pull-down resistor DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ0 - IRQ1 FIQ External Interrupt Inputs Fast Interrupt Input Input Input PIO Controller - PIOA - PIOB - PIOC - PIOD - PIOE PA0 - PA31 PB0 - PB31 PC0 - PC31 PD0 - PD31 PE0 - PE31 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D Parallel IO Controller E I/O I/O I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Direct Memory Access Controller - DMA DMARQ0-DMARQ3 DMA Requests Input External Bus Interface - EBI0 - EBI1 EBIx_D0 - EBIx_D31 EBIx_A0 - EBIx_A25 EBIx_NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset 0 at reset Static Memory Controller - SMC EBI0_NCS0 - EBI0_NCS5, EBI1_NCS0 - EBI1_NCS2 EBIx_NWR0 -EBIx_NWR3 EBIx_NRD EBIx_NWE EBIx_NBS0 - EBIx_NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output Low Low Low Low Low 6 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function Type CompactFlash Support Active Level Comments EBI0_CFCE1 - EBI0_CFCE2 EBI0_CFOE EBI0_CFWE EBI0_CFIOR EBI0_CFIOW EBI0_CFRNW EBI0_CFCS0 - EBI0_CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines NAND Flash Support Output Output Output Output Output Output Output Low Low Low Low Low Low EBIx_NANDCS EBIx_NANDOE EBIx_NANDWE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable SDRAM Controller Output Output Output Low Low Low EBIx_SDCK EBIx_SDCKE EBIx_SDCS EBIx_BA0 - EBIx_BA1 EBIx_SDWE EBIx_RAS - EBIx_CAS EBIx_SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Low Low High Low Multimedia Card Interface MCIx_CK MCIx_CDA MCIx_CDB MCIx_DA0 - MCIx_DA3 MCIx_DB0 - MCIx_DB3 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot B Command Multimedia Card Slot A Data Multimedia Card Slot B Data Output I/O I/O I/O I/O Universal Synchronous Asynchronous Receiver Transmitter USART SCKx TXDx RXDx RTSx CTSx USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send I/O I/O Input Output Input Synchronous Serial Controller SSC TDx RDx SSCx Transmit Data SSCx Receive Data Output Input 7 6249HS–ATARM–27-Jul-09 Table 3-1. Signal Name TKx RKx TFx RFx Signal Description List (Continued) Function SSCx Transmit Clock SSCx Receive Clock SSCx Transmit Frame Sync SSCx Receive Frame Sync AC97 Controller - AC97C Type I/O I/O I/O I/O Active Level Comments AC97RX AC97TX AC97FS AC97CK AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Timer/Counter - TC Input Output Output Input TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O Pulse Width Modulation Controller- PWMC PWMx Pulse Width Modulation Output Output Serial Peripheral Interface - SPI SPIx_MISO SPIx_MOSI SPIx_SPCK SPIx_NPCS0 SPIx_NPCS1 - SPIx_NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select Two-Wire Interface TWD TWCK Two-wire Serial Data Two-wire Serial Clock CAN Controllers CANRX CANTX CAN Input CAN Output Input Output LCD Controller - LCDC LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control Output Output Output Output Output Output I/O I/O I/O I/O I/O I/O Output Low Low 8 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function Ethernet 10/100 Type Active Level Comments ETXCK ERXCK ETXEN ETX0-ETX3 ETXER ERXDV ERX0-ERX3 ERXER ECRS ECOL EMDC EMDIO EF100 Transmit Clock or Reference Clock Receive Clock Transmit Enable Transmit Data Transmit Coding Error Receive Data Valid Receive Data Receive Error Carrier Sense and Data Valid Collision Detect Management Data Clock Management Data Input/Output Force 100Mbit/sec. USB Device Port Input Input Output Output Output Input Input Input Input Input Output I/O Output High MII only, REFCK in RMII MII only ETX0-ETX1 only in RMII MII only RXDV in MII, CRSDV in RMII ERX0-ERX1 only in RMII MII only MII only RMII only DDM DDP USB Device Port Data USB Device Port Data + USB Host Port Analog Analog HDPA HDMA HDPB HDMB USB Host Port A Data + USB Host Port A Data USB Host Port B Data + USB Host Port B Data - Analog Analog Analog Analog Image Sensor Interface - ISI ISI_D0-ISI_D11 ISI_MCK ISI_HSYNC ISI_VSYNC ISI_PCK Image Sensor Data Image Sensor Reference Clock Image Sensor Horizontal Synchro Image Sensor Vertical Synchro Image Sensor Data Clock Input Output Input Input Input Provided by PCK3 9 6249HS–ATARM–27-Jul-09 4. Package and Pinout The AT91SAM9263 is available in a 324-ball TFBGA Green package, 15 x 15 mm, 0.8mm ball pitch. 4.1 324-ball TFBGA Package Outline Figure 4-1 shows the orientation of the 324-ball TFBGA package. A detailed mechanical description is given in the section “AT91SAM9263 Mechanical Characteristics” in the product datasheet. Figure 4-1. 324-ball TFBGA Pinout (Top View) 10 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 4.2 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 324-ball TFBGA Package Pinout AT91SAM9263 Pinout for 324-ball TFBGA Package Pin E10 E11 E12 E13 E14 E15 E16 E17 E18 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 H1 H2 H3 H4 H5 Signal Name PC31 PC22 PC15 PC11 PC4 PB30 PC0 PB31 HDPA PD7 EBI0_D13 EBI0_D9 EBI0_D11 EBI0_D12 EBI0_NCS0 EBI0_A16_BA0 EBI0_A12 EBI0_A6 PD3 PC27 PC18 PC13 PB26 PB25 PB29 PB27 HDMA PD17 PD12 PD6 EBI0_D14 PD5 PD8 PD10 GND NC(1) GND GND GND PB21 PB20 PB23 PB28 PB22 PB18 PD24 PD13 PD15 PD9 PD11 Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 L15 L16 L17 L18 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 Signal Name PE6 PD28 PE0 PE1 PD27 PD31 PD29 PD25 GND VDDIOM0 GND VDDIOM0 PB3/BMS PA14 PA15 PB1 PB0 PB2 PE10 PE4 PE9 PE7 PE5 PE2 PE3 VDDIOP1 VDDIOM1 VDDIOM0 VDDIOP0 GNDBU PA13 PB4 PA9 PA12 PA10 PA11 PE18 PE14 PE15 PE11 PE13 PE12 PE8 VDDBU EBI1_A21 VDDIOM1 GND GND VDDIOM1 PA6 Pin P10 P11 P12 P13 P14 P15 P16 P17 P18 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 U1 U2 U3 U4 U5 Signal Name EBI1_NCS0 EBI1_NWE_NWR0 EBI1_D4 EBI1_D10 PA3 PA2 PE28 TDI PLLRCB XOUT32 TST PA18 PA25 PA30 EBI1_A2 EBI1_A14 EBI1_A13 EBI1_A17_BA1 EBI1_D1 EBI1_D8 EBI1_D12 EBI1_D15 PE26 EBI1_SDCK PE30 TCK XOUT VDDOSC VDDIOM1 PA19 PA21 PA26 PA31 EBI1_A7 EBI1_A12 EBI1_A18 EBI1_D0 EBI1_D7 EBI1_D14 PE23 PE25 PE29 PE31 GNDPLL XIN PA17 PA20 PA23 PA24 PA28 Signal Name EBI0_D2 EBI0_SDCKE EBI0_NWE_NWR0 EBI0_NCS1_SDCS EBI0_A19 EBI0_A11 EBI0_A10 EBI0_A5 EBI0_A1_NBS2_NWR2 PD4 PC30 PC26 PC24 PC19 PC12 VDDCORE VDDIOP0 DDP EBI0_D4 EBI0_NANDOE EBI0_CAS EBI0_RAS EBI0_NBS3_NWR3 EBI0_A22 EBI0_A15 EBI0_A7 EBI0_A4 PD0 PC28 PC21 PC17 PC9 PC7 PC5 PB16 DDM EBI0_D6 EBI0_D0 EBI0_NANDWE EBI0_SDWE EBI0_SDCK EBI0_A21 EBI0_A13 EBI0_A8 EBI0_A3 PD2 PC29 PC23 PC14 PC8 Table 4-1. 11 6249HS–ATARM–27-Jul-09 Table 4-1. Pin C15 C16 C17 C18 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 E1 E2 E3 E4 E5 E6 E7 E8 E9 PC3 GND AT91SAM9263 Pinout for 324-ball TFBGA Package (Continued) Pin H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 Signal Name PD14 PD16 VDDIOM0 GND VDDCORE GND PB19 PB17 PB15 PB13 PB24 PB14 PB12 PD30 PD26 PD22 PD19 PD18 PD23 PD21 PD20 GND GND GND PB11 PB9 PB10 PB5 PB6 PB7 PB8 Pin M15 M16 M17 M18 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 P1 P2 P3 P4 P5 P6 P7 P8 P9 Signal Name PA4 PA7 PA5 PA8 NC NC PE19 NC(1) PE17 PE16 EBI1_A6 EBI1_A11 EBI1_A22 EBI1_D2 EBI1_D6 EBI1_D9 GND GNDPLL PA1 PA0 TMS TDO XIN32 SHDN PA16 WKUP JTAGSEL PE20 EBI1_A8 EBI1_A4 EBI1_A19 Pin U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 V15 V16 V17 V18 Signal Name EBI1_A0_NBS0 EBI1_A5 EBI1_A10 EBI1_A16_BA0 EBI1_NRD EBI1_D3 EBI1_D13 PE22 PE27 RTCK NTRST VDDPLLA PLLRCA VDDCORE PA22 PA27 PA29 EBI1_A1_NWR2 EBI1_A3 EBI1_A9 EBI1_A15 EBI1_A20 EBI1_NBS1_NWR1 EBI1_D5 EBI1_D11 PE21 PE24 NRST GND GND VDDPLLB Signal Name VDDIOP0 HDPB EBI0_D10 EBI0_D3 NC(1) EBI0_D1 EBI0_A20 EBI0_A17_BA1 EBI0_A18 EBI0_A9 EBI0_A2 PD1 PC25 PC20 PC6 PC16 PC10 PC2 PC1 HDMB EBI0_D15 EBI0_D7 EBI0_D5 EBI0_D8 EBI0_NBS1_NWR1 EBI0_NRD EBI0_A14 EBI0_SDA10 EBI0_A0_NBS0 Note: 1. NC pins must be left unconnected. 12 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 5. Power Considerations 5.1 Power Supplies AT91SAM9263 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V to 1.32V, 1.2V nominal. • VDDIOM0 and VDDIOM1 pins: Power the External Bus Interface 0 I/O lines and the External Bus Interface 1 I/O lines, respectively; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). • VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 2.7V to 3.6V, 3.3V nominal. • VDDIOP1 pins: Power the Peripheral I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V to 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V to 1.32V, 1.2V nominal. • VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V to 3.6V, 3.3V nominal. • VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V to 3.6V, L3.3V nominal. The power supplies VDDIOM0, VDDIOM1 and VDDIOP0, VDDIOP1 are identified in the pinout table and the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDOSC, VDDCORE, VDDIOM0, VDDIOM1, VDDIOP0 and VDDIOP1 pins power supplies. Separated ground pins are provided for VDDBU and VDDPLL. These ground pins are respectively GNDBU and GNDPLL. 5.2 Power Consumption The AT91SAM9263 consumes about 700 µA (worst case) of static current on VDDCORE at 25°C. This static current rises at up to 7 mA if the temperature increases to 85°C. On VDDBU, the current does not exceed 3 µA @25°C, but can rise at up to 20 µA @85°C. An automatic switch to VDDCORE guarantees low power consumption on the battery when the system is on. For dynamic power consumption, the AT91SAM9263 consumes a maximum of 70 mA on VDDCORE at maximum conditions (1.2V, 25°C, processor running full-performance algorithm). 5.3 Programmable I/O Lines Power Supplies The power supply pins VDDIOM0 and VDDIOM1 accept two voltage ranges. This allows the device to reach its maximum speed, either out of 1.8V or 3.0V external memories. The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 10 pF. The other signals (control, address and data signals) do not go over 50 MHz, loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. However, the device cannot reach its maximum speed if the voltage supplied to 13 6249HS–ATARM–27-Jul-09 the pins is only 1.8V without reprogramming the EBI0 voltage range. The user must be sure to program the EBI0 voltage range before getting the device out of its Slow Clock Mode. 6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 6.3. All JTAG signals except JTAGSEL (VDDBU) are supplied with VDDIOP0. 6.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU. 6.3 Reset Pins NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells, which manage the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor of 100 kΩ minimum to VDDIOP0. The NRST signal is inserted in the Boundary Scan. 6.4 PIO Controllers All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor of 100 kΩ typical. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables on page 36 and following. 6.5 Shutdown Logic Pins The SHDN pin is a tri-state output only pin, which is driven by the Shutdown Controller. There is no internal pull-up. An external pull-up to VDDBU is needed and its value must be higher than 1 14 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary MΩ. The resistor value is calculated according to the regulator enable implementation and the SHDN level. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 7. Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor based on ARM v5TEJ Harvard Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • DSP Instruction Extensions • 5-stage Pipeline Architecture – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 16 Kbyte Data Cache, 16 Kbyte Instruction Cache – Virtually-addressed 4-way Associative Cache – Eight words per line – Write-through and Write-back Operation – Pseudo-random or Round-robin Replacement • Write Buffer – Main Write Buffer with 16-word Data Buffer and 4-address Buffer – DCache Write-back Buffer with 8-word Entries and a Single Address Entry – Software Control Drain • Standard ARM v4 and v5 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for each quarter of the page – 16 embedded domains • Bus Interface Unit (BIU) – Arbitrates and Schedules AHB Requests – Separate Masters for both instruction and data access providing complete Matrix system flexibility – Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) 15 6249HS–ATARM–27-Jul-09 7.2 Bus Matrix • 9-layer Matrix, handling requests from 9 masters • Programmable Arbitration strategy – Fixed-priority Arbitration – Round-Robin Arbitration, either with no default master, last accessed default master or fixed default master • Burst Management – Breaking with Slot Cycle Limit Support – Undefined Burst Length Support • One Address Decoder provided per Master – Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap • Boot Mode Select – Non-volatile Boot Memory can be internal or external – Selection is made by BMS pin sampled at reset • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory – Allows Handling of Dynamic Exception Vectors 7.3 Matrix Masters The Bus Matrix of the AT91SAM9263 manages nine masters, thus each master can perform an access concurrently with others to an available slave peripheral or memory. Each master has its own decoder, which is defined specifically for each master. Table 7-1. Master 0 Master 1 Master 2 Master 3 Master 4 Master 5 Master 6 Master 7 Master 8 List of Bus Matrix Masters OHCI USB Host Controller Image Sensor Interface Two D Graphic Controller DMA Controller Ethernet MAC LCD Controller Peripheral DMA Controller ARM926 Data ARM926™ Instruction 7.4 Matrix Slaves The Bus Matrix of the AT91SAM9263 manages eight slaves. Each slave has its own arbiter, thus allowing to program a different arbitration per slave. 16 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary The LCD Controller, the DMA Controller, the USB OTG and the USB Host have a user interface mapped as a slave on the Matrix. They share the same layer, as programming them does not require a high bandwidth. Table 7-2. Slave 0 Slave 1 Slave 2 List of Bus Matrix Slaves Internal ROM Internal 80 Kbyte SRAM Internal 16 Kbyte SRAM LCD Controller User Interface Slave 3 DMA Controller User Interface USB Host User Interface Slave 4 Slave 5 Slave 6 External Bus Interface 0 External Bus Interface 1 Peripheral Bridge 17 6249HS–ATARM–27-Jul-09 7.5 Master to Slave Access In most cases, all the masters can access all the slaves. However, some paths do not make sense, for example, allowing access from the Ethernet MAC to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and are shown as “-” in Table 7-3. Table 7-3. Masters to Slaves Access 0 OHCI USB Host Controller X X X X X 1 Image Sensor Interface X X X X X 2 Two D Graphics Controller X X X X X 3 DMA Controller X X X X X X 4 Ethernet MAC X X X X X 5 LCD Controller X X X X X 6 Peripheral DMA Controller X X X X X X 7&8 ARM926 Data & Instruction X X X X X X X X X Master Slave 0 1 2 Internal ROM Internal 80 Kbyte SRAM Internal 16 Kbyte SRAM Bank LCD Controller User Interface 3 DMA Controller User Interface USB Host User Interface 4 5 6 External Bus Interface 0 External Bus Interface 1 Peripheral Bridge 7.6 Peripheral DMA Controller • Acts as one Matrix Master • Allows data transfers between a peripheral and memory without any intervention of the processor • Next Pointer support, removes heavy real-time constraints on buffer management. • Twenty channels – Two for each USART – Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – Two for the AC97 Controller – One for each Multimedia Card Interface The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (low to high priorities): – DBGU Transmit Channel – USART2 Transmit Channel 18 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary – USART1 Transmit Channel – USART0 Transmit Channel – AC97 Transmit Channel – SPI1 Transmit Channel – SPI0 Transmit Channel – SSC1 Transmit Channel – SSC0 Transmit Channel – DBGU Receive Channel – USART2 Receive Channel – USART1 Receive Channel – USART0 Receive Channel – AC97 Receive Channel – SPI1 Receive Channel – SPI0 Receive Channel – SSC1 Receive Channel – SSC0 Receive Channel – MCI1 Transmit/Receive Channel – MCI0 Transmit/Receive Channel 7.7 DMA Controller • Acts as one Matrix Master • Embeds 2 unidirectional channels with programmable priority • Address Generation – Source/destination address programming – Address increment, decrement or no change – DMA chaining support for multiple non-contiguous data blocks through use of linked lists – Scatter support for placing fields into a system memory area from a contiguous transfer. Writing a stream of data into non-contiguous fields in system memory. – Gather support for extracting fields from a system memory area into a contiguous transfer – User enabled auto-reloading of source, destination and control registers from initially programmed values at the end of a block transfer – Auto-loading of source, destination and control registers from system memory at end of block transfer in block chaining mode – Unaligned system address to data transfer width supported in hardware • Channel Buffering – Two 8-word FIFOs – Automatic packing/unpacking of data to fit FIFO width • Channel Control – Programmable multiple transaction size for each channel – Support for cleanly disabling a channel without data loss 19 6249HS–ATARM–27-Jul-09 – Suspend DMA operation – Programmable DMA lock transfer support. • Transfer Initiation – Supports four external DMA Requests – Support for software handshaking interface. Memory mapped registers can be used to control the flow of a DMA transfer in place of a hardware handshaking interface • Interrupt – Programmable interrupt generation on DMA transfer completion, Block transfer completion, Single/Multiple transaction completion or Error condition 7.8 Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • Embedded Trace Macrocell: ETM9™ – Medium+ Level Implementation – Half-rate Clock Mode – Four Pairs of Address Comparators – Two Data Comparators – Eight Memory Map Decoder Inputs – Two 16-bit Counters – One 3-stage Sequencer – One 45-byte FIFO • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 20 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 8. Memories Figure 8-1. AT91SAM9263 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF Internal Memory Mapping 0x0000 0000 0x0010 0000 0x0020 0000 Boot Memory (1) ITCM (2) DTCM (2) SRAM (2) ROM 16K SRAM0 Notes: (1) Can be ROM, EBI0_NCS0 or SRAM depending on BMS and REMAP (2) Software programmable 256M Bytes 0x1000 0000 EBI0 Chip Select 0 0x1FFF FFFF 0x0030 0000 256M Bytes 0x0040 0000 0x0050 0000 0x2000 0000 EBI0 Chip Select 1/ EBI0 SDRAMC 256M Bytes 0x0060 0000 0x0070 0000 Reserved LCD Controller 0x2FFF FFFF 0x3000 0000 EBI0 Chip Select 2 0x3FFF FFFF 256M Bytes 0x0080 0000 DMAC 0x0090 0000 Reserved USB HOST 0x00B0 0000 Reserved 0x4000 0000 EBI0 Chip Select 3/ NANDFlash EBI0 Chip Select 4/ Compact Flash Slot 0 EBI0 Chip Select 5/ Compact Flash Slot 1 EBI1 Chip Select 0 0x00A0 0000 256M Bytes 0x4FFF FFFF 0x5000 0000 256M Bytes 0xF000 0000 Peripheral Mapping Reserved 0xFFF7 8000 UDP 0xFFF7 C000 TCO, TC1, TC2 0xFFF8 0000 MCI0 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF EE00 AC97C 0xFFFA 4000 SPI0 0xFFFA 8000 SPI1 16K Bytes 16K Bytes 0xFFFA C000 CAN0 0xFFFB 0000 Reserved 0xFFFB 8000 PWMC 0xFFFB C000 EMAC 0xFFFC 0000 Reserved 0xFFFC 4000 ISI 0xFFFC 8000 16K Bytes 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FC00 0xFFFF FD00 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 16K Bytes 0xFFFF FDB0 Reserved 0xFFFF FFFF PMC RSTC SHDWC RTT0 PIT WDT RTT1 GPBR 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 80 Bytes 0xFFFF F800 0xFFFF FA00 0xFFFF F600 PIOC PIOD PIOE 512 bytes 512 bytes 512 bytes 16K Bytes 0xFFFF F200 0xFFFF F400 PIOB 512 Bytes 16K Bytes DBGU 0xFFFF F000 AIC PIOA 512 bytes 512 bytes 0xFFFF E000 0xFFFF E200 0xFFFF E400 0xFFFF E600 0xFFFF E800 SDRAMC1 0xFFFF EA00 0xFFFF EC00 0xFFFF ED10 SSC1 0xFFFA 0000 CCFG 512 Bytes SMC1 MATRIX 512 Bytes 512 Bytes 512 Bytes 16K Bytes 16K Bytes 16K Bytes 0x5FFF FFFF 0x6000 0000 System Controller Mapping 0xFFFF C000 Reserved ECC0 SDRAMC0 SMC0 ECC1 512 Bytes 512 Bytes 512 Bytes 512 bytes 256M Bytes 0x6FFF FFFF 0x7000 0000 256M Bytes 0xFFF8 4000 MCI1 0xFFF8 8000 0x7FFF FFFF 0x8000 0000 EBI1 Chip Select 1/ EBI1 SDRAMC 0x8FFF FFFF TWI 256M Bytes 0xFFF8 C000 USART0 0xFFF9 0000 USART1 0x9000 0000 EBI1 Chip Select 2/ NANDFlash 0x9FFF FFFF 256M Bytes 0xFFF9 4000 USART2 0xFFF9 8000 SSC0 0xFFF9 C000 0xA000 0000 Undefined (Abort) 1,280M Bytes 0xEFFF FFFF 2DGE 0xFFFC C000 Reserved 0xF000 0000 Internal Peripherals 0xFFFF FFFF 256M Bytes 0xFFFF C000 SYSC 0xFFFF FFFF 21 6249HS–ATARM–27-Jul-09 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its master and slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 9 are directed to the EBI0 that associates these banks to the external chip selects EBI0_NCS0 to EBI0_NCS5 and EBI1_NCS0 to EBI1_NCS2. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M bytes of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each master has its own bus and its own decoder, thus allowing a different memory mapping for each master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot and one after remap. Refer to Table 8-1, “Internal Memory Mapping,” on page 22 for details. A complete memory map is presented in Figure 8-1 on page 21. 8.1 Embedded Memories • 128 Kbyte ROM – Single Cycle Access at full matrix speed • One 80 Kbyte Fast SRAM – Single Cycle Access at full matrix speed – Supports ARM926EJ-S TCM interface at full processor speed – Allows internal Frame Buffer for up to 1/4 VGA 8 bpp screen • 16 Kbyte Fast SRAM – Single Cycle Access at full matrix speed 8.1.1 Internal Memory Mapping Table 8-1 summarizes the Internal Memory Mapping, depending on the Remap status and the BMS state at reset. Table 8-1. Internal Memory Mapping REMAP = 0 Address 0x0000 0000 BMS = 1 ROM BMS = 0 EBI0_NCS0 SRAM C REMAP = 1 8.1.1.1 Internal 80 Kbyte Fast SRAM The AT91SAM9263 device embeds a high-speed 80 Kbyte SRAM. This internal SRAM is split into three areas. Its memory mapping is presented in Figure 8-1 on page 21. • Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR 22 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary configuration register located in the Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000. • Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000. • Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 80 Kbytes of SRAM available, the amount of memory assigned to each block is software programmable as a multiple of 16 Kbytes as shown in Table 8-2. This table provides the size of the Internal SRAM C according to the size of the internal SRAM A and the internal SRAM B. Table 8-2. Internal SRAM Block Size Internal SRAM A (ITCM) Size Internal SRAM C Internal SRAM B (DTCM) size 0 16 Kbytes 32 Kbytes 0 80 Kbytes 64 Kbytes 48 Kbytes 16 Kbytes 64 Kbytes 48 Kbytes 32 Kbytes 32 Kbytes 48 Kbytes 32 Kbytes 16 Kbytes Note that among the five 16 Kbyte blocks making up the Internal SRAM, one is permanently assigned to Internal SRAM C. At reset, the whole memory (80 Kbytes) is assigned to Internal SRAM C. The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16 Kbyte block organization may affect the previous configuration from a software point of view. Table 8-3 illustrates different configurations and the related 16 Kbyte blocks assignments (RB0 to RB4). Table 8-3. 16 Kbyte Block Allocation Configuration examples and related 16 Kbyte block assignments Decoded Area Internal SRAM A (ITCM) Internal SRAM B (DTCM) ITCM = 0 Kbyte DTCM = 0 Kbyte AHB = 80 Kbytes (1) ITCM = 32 Kbytes DTCM = 32 Kbytes AHB = 16 Kbytes ITCM = 16 Kbytes DTCM = 32 Kbytes AHB = 32 Kbytes ITCM = 32 Kbytes DTCM = 16 Kbytes AHB = 32 Kbytes ITCM = 16 Kbytes DTCM = 16 Kbytes AHB = 48 Kbytes Address 0x0010 0000 0x0010 4000 0x0020 0000 0x0020 4000 RB1 RB0 RB3 RB2 RB1 RB1 RB0 RB1 RB3 RB2 RB3 RB3 23 6249HS–ATARM–27-Jul-09 Table 8-3. 16 Kbyte Block Allocation (Continued) Configuration examples and related 16 Kbyte block assignments Decoded Area Address 0x0030 0000 ITCM = 0 Kbyte DTCM = 0 Kbyte AHB = 80 Kbytes (1) ITCM = 32 Kbytes DTCM = 32 Kbytes AHB = 16 Kbytes ITCM = 16 Kbytes DTCM = 32 Kbytes AHB = 32 Kbytes ITCM = 32 Kbytes DTCM = 16 Kbytes AHB = 32 Kbytes ITCM = 16 Kbytes DTCM = 16 Kbytes AHB = 48 Kbytes RB4 RB3 RB2 RB1 RB0 RB4 RB4 RB0 RB4 RB2 RB4 RB2 RB0 Internal SRAM C (AHB) 0x0030 4000 0x0030 8000 0x0030 C000 0x0031 0000 Note: 1. Configuration after reset. When accessed from the Bus Matrix, the internal 80 Kbytes of Fast SRAM is single cycle accessible at full matrix speed (MCK). When accessed from the processor’s TCM Interface, they are also single cycle accessible at full processor speed. 8.1.1.2 Internal 16 Kbyte Fast SRAM The AT91SAM9263 integrates a 16 Kbyte SRAM, mapped at address 0x0050 0000. This SRAM is single cycle accessible at full Bus Matrix speed. Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters. REMAP allows the user to layout the internal SRAM bank to 0x0. This is done by software once the system has booted. Refer to the section “AT91SAM9263 Bus Matrix” in the product datasheet for more details. When REMAP = 0, BMS allows the user to layout at address 0x0 either the ROM or an external memory. This is done via hardware at reset. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 21. 8.1.2 The AT91SAM9263 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 8.1.2.1 BMS = 1, Boot on Embedded ROM The system boots on Boot Program. • Boot at slow clock • Auto baudrate detection • Downloads and runs an application from external storage media into internal SRAM • Downloaded code size depends on embedded SRAM size • Automatic detection of valid application • Bootloader on a non-volatile memory 24 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary – SD Card – NAND Flash – SPI DataFlash® and Serial Flash connected on NPCS0 of the SPI0 • Interface with SAM-BA® Graphic User Interface to enable code loading via: – Serial communication on a DBGU – USB Bulk Device Port 8.1.2.2 BMS = 0, Boot on External Memory • Boot at slow clock • Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI0 CS0 (BMS=0) the user must: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and Start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock. 4. Switch the main clock to the new value. 8.2 External Memories The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256 Mbyte memory area assigned. Refer to Figure 8-1 on page 21. 8.2.1 External Bus Interfaces The AT91SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent bottlenecks while accessing external memories. External Bus Interface 0 • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – ECC Controller • Additional logic for NAND Flash and CompactFlash • Optional Full 32-bit External Data Bus • Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select) • Up to 6 Chip Selects, Configurable Assignment: – Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3, Optional NAND Flash support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support • Optimized for Application Memory Space 8.2.1.1 25 6249HS–ATARM–27-Jul-09 8.2.1.2 External Bus Interface 1 • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – ECC Controller • Additional logic for NAND Flash • Optional Full 32-bit External Data Bus • Up to 23-bit Address Bus (up to 8 Mbytes linear) • Up to 3 Chip Selects, Configurable Assignment: – Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2, Optional NAND Flash support • Allows supporting an external Frame Buffer for the embedded LCD Controller without impacting processor performance. 8.2.2 Static Memory Controller • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability – Compliant with LCD Module – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported 8.2.3 SDRAM Controller • Supported devices – Standard and Low-power SDRAM (Mobile SDRAM) • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable 26 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency of 1, 2 and 3 supported • Auto Precharge Command not used 8.2.4 Error Corrected Code Controller • Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select • Single-bit error correction and two-bit random detection • Automatic Hamming Code Calculation while writing – ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being detected erroneous – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages 9. System Controller The System Controller is a set of peripherals that allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds registers that are used to configure the Bus Matrix and a set of registers for the chip configuration. The chip configuration registers can be used to configure: – EBI0 and EBI1 chip select assignment and voltage range for external memories – ARM Processor Tightly Coupled Memories The System Controller peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF C000 and 0xFFFF FFFF. However, all the registers of the System Controller are mapped on the top of the address space. This allows all the registers of the System Controller to be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instructions have an indexing mode of ± 4 Kbytes. Figure 9-1 on page 28 shows the System Controller block diagram. Figure 8-1 on page 21 shows the mapping of the User Interfaces of the System Controller peripherals. 27 6249HS–ATARM–27-Jul-09 9.1 System Controller Block Diagram AT91SAM9263 System Controller Block Diagram System Controller VDDCORE Powered irq0-irq1 fiq periph_irq[2..29] pit_irq rtt0_irq rtt1_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC NRST VDDCORE POR por_ntrst jtag_nreset rstc_irq Reset Controller periph_nreset proc_nreset backup_nreset VDDBU Powered SLCK Real-Time Timer 0 Real-Time Timer 1 rtt0_irq rtt0_alarm rtt1_irq rtt1_alarm UDPCK periph_clk[24] periph_nreset periph_irq[24] Shut-Down Controller backup_nreset XIN32 XOUT32 SLOW CLOCK OSC rtt0_alarm rtt1_alarm SLCK int XIN XOUT PLLRCA PLLRCB MAIN OSC PLLA PLLB MAINCK Power Management Controller 20 General-Purpose Backup Registers Voltage Controller battery_save UHPCK periph_clk[29] periph_nreset periph_irq[29] USB Host Port USB Device Port Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq Figure 9-1. Debug Unit dbgu_irq dbgu_txd proc_nreset PCK debug pit_irq jtag_nreset wdt_irq MCK periph_nreset Bus Matrix Boundary Scan TAP Controller VDDCORE VDDBU VDDBU POR battery_save SLCK backup_nreset SLCK backup_nreset SLCK SHDN WKUP periph_clk[2..29] pck[0-3] PCK OTGCK UDPCK periph_clk[26] periph_nreset periph_irq[26] LCD Controller PLLACK PLLBCK MCK pmc_irq periph_nreset idle periph_clk[7..27] periph_nreset periph_nreset periph_clk[2..6] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD31 PE0-PE31 PIO Controllers periph_irq[2..6] irq0-irq1 fiq dbgu_txd Embedded Peripherals periph_irq[7..27] in out enable 28 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 9.2 Reset Controller • Based on two Power-on-Reset cells – One on VDDBU and one on VDDCORE • Status of the last reset – Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset • Controls the internal resets and the NRST pin output – Allows shaping a reset signal for the external devices 9.3 Shutdown Controller • Shutdown and Wake-up logic – Software programmable assertion of the SHDN pin (SHDN is push-pull) – Deassertion programmable on a WKUP pin level change or on alarm 9.4 Clock Generator • Embeds the low-power 32768 Hz Slow Clock Oscillator – Provides the permanent Slow Clock SLCK to the system • Embeds the Main Oscillator – Oscillator bypass feature – Supports 3 to 20 MHz crystals • Embeds 2 PLLs – Output 80 to 240 MHz clocks – Integrates an input divider to increase output accuracy – 1 MHz Minimum input frequency Figure 9-2. Clock Generator Block Diagram Clock Generator XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK PLLRCA PLL and Divider A PLL and Divider B Status Control PLLA Clock PLLACK PLLB Clock PLLBCK PLLRCB Power Management Controller 29 6249HS–ATARM–27-Jul-09 9.5 Power Management Controller • Provides: – the Processor Clock PCK – the Master Clock MCK, in particular to the Matrix and the memory interfaces – the USB Device Clock UDPCK – the USB Host Clock UHPCK – independent peripheral clocks, typically at the frequency of MCK – four programmable clock outputs: PCK0 to PCK3 • Five flexible operating modes: – Normal Mode with processor and peripherals running at a programmable frequency – Idle Mode with processor stopped while waiting for an interrupt – Slow Clock Mode with processor and peripherals running at low frequency – Standby Mode, mix of Idle and Backup Mode, with peripherals running at low frequency, processor stopped waiting for an interrupt – Backup Mode with Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9263 Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Divider /1,/2,/4 Peripherals Clock Controller ON/OFF Idle Mode MCK PCK int periph_clk[..] Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] USB Clock Controller PLLBCK Divider /1,/2,/4 ON/OFF UDPCK UHPCK 9.6 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real-time OS or Linux®/WindowsCE® compliant tick generator 9.7 Watchdog Timer • 16-bit key-protected Counter, programmable only once 30 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary • Windowed, prevents the processor deadlocking on the watchdog access 9.8 Real-time Timer • Two Real-time Timers, allowing backup of time with different accuracies – 32-bit Free-running back-up counter – Integrates a 16-bit programmable prescaler running on the embedded 32.768Hz oscillator – Alarm Register capable of generating a wake-up of the system through the Shutdown Controller 9.9 General-purpose Backup Registers • Twenty 32-bit general-purpose backup registers 9.10 Backup Power Switch • Automatic switch of VDDBU to VDDCORE guaranteeing very low power consumption on VDDBU while VDDCORE is present 9.11 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive • Four External Sources plus the Fast Interrupt signal • 8-level Priority Controller – Drives the Normal Interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode – Easy debugging by preventing automatic operations when protect models are enabled • Fast Forcing – Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 9.12 Debug Unit • Composed of two functions • Two-pin UART 31 6249HS–ATARM–27-Jul-09 – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter – Mode for general purpose Two-wire UART serial communication • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE Interface 9.13 Chip Identification • Chip ID: 0x019607A0 • JTAG ID: 0x05B0C03F • ARM926 TAP ID: 0x0792603F 9.14 PIO Controllers • Five PIO Controllers, PIOA to PIOE, controlling a total of 160 I/O Lines • Each PIO Controller controls up to 32 programmable I/O Lines – PIOA has 32 I/O Lines – PIOB has 32 I/O Lines – PIOC has 32 I/O Lines – PIOD has 32 I/O Lines – PIOE has 32 I/O Lines • Fully programmable through Set/Clear Registers • Multiplexing of two peripheral functions per I/O Line • For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull-up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 32 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 10. Peripherals 10.1 User Interface The Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 21. 10.2 Identifiers Table 10-1 defines the Peripheral Identifiers. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 AT91SAM9263 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC to PIOE reserved reserved US0 US1 US2 MCI0 MCI1 CAN TWI SPI0 SPI1 SSC0 SSC1 AC97C TC0, TC1, TC2 PWMC EMAC reserved 2DGE UDP ISI LCDC DMA reserved 2D Graphic Engine USB Device Port Image Sensor Interface LCD Controller DMA Controller USART 0 USART 1 USART 2 Multimedia Card Interface 0 Multimedia Card Interface 1 CAN Controller Two-Wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 AC97 Controller Timer/Counter 0, 1 and 2 Pulse Width Modulation Controller Ethernet MAC Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C, D and E External Interrupt FIQ Peripheral ID 33 6249HS–ATARM–27-Jul-09 Table 10-1. 29 30 31 AT91SAM9263 Peripheral Identifiers (Continued) Peripheral Mnemonic UHP AIC AIC Peripheral Name USB Host Port Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 External Interrupt Peripheral ID Note: Setting AIC, SYSC, UHP and IRQ0 - 1 bits in the clock set/clear registers of the PMC has no effect. 10.2.1 10.2.1.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-Time Timer • the Watchdog Timer • the Reset Controller • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ1, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. Timer Counter Interrupts The three Timer Counter channels interrupt signals are OR-wired together to provide the interrupt source 19 of the Advanced Interrupt Controller. This forces the programmer to read all Timer Counter status registers before branching the right Interrupt Service Routine. The Timer Counter channels clocks cannot be deactivated independently. Switching off the clock of the Peripheral 19 disables the clock of the 3 channels. 10.2.1.3 10.3 Peripherals Signals Multiplexing on I/O Lines The AT91SAM9263 device features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only may be duplicated within both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is specified, the PIO Line resets in input with the pull-up enabled, so that the device 34 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is specified in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 35 6249HS–ATARM–27-Jul-09 10.3.1 PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A Application Usage Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PCK0 IRQ0 IRQ1 EBI1_D16 EBI1_D17 EBI1_D18 EBI1_D19 EBI1_D20 EBI1_D21 EBI1_D22 EBI1_D23 EBI1_D24 EBI1_D25 EBI1_D26 EBI1_D27 EBI1_D28 EBI1_D29 EBI1_D30 EBI1_D31 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 Function Comments Table 10-2. I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A MCI0_DA0 MCI0_CDA Peripheral B SPI0_MISO SPI0_MOSI SPI0_SPCK MCI0_DA1 MCI0_DA2 MCI0_DA3 MCI1_CK MCI1_CDA MCI1_DA0 MCI1_DA1 MCI1_DA2 MCI1_DA3 MCI0_CK CANTX CANRX TCLK2 MCI0_CDB MCI0_DB0 MCI0_DB1 MCI0_DB2 MCI0_DB3 MCI1_CDB MCI1_DB0 MCI1_DB1 MCI1_DB2 MCI1_DB3 TXD0 RXD0 RTS0 CTS0 SCK0 DMARQ0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS0 PCK2 36 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 10.3.2 PIO Controller B Multiplexing Multiplexing on PIO Controller B PIO Controller B I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PWM2 TCLK0 PWM3 DMARQ3 Peripheral A AC97FS AC97CK AC97TX AC97RX TWD TWCK TF1 TK1 TD1 RD1 RK1 RF1 SPI1_MISO SPI1_MOSI SPI1_SPCK SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 PCK1 TIOA2 TIOB2 Peripheral B TF0 TK0 TD0 RD0 RK0 RF0 DMARQ1 PWM0 PWM1 LCDCC PCK1 SPI0_NPCS3 Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Application Usage Function Comments Table 10-3. 37 6249HS–ATARM–27-Jul-09 10.3.3 PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C Application Usage Reset State I/O I/O I/O PWM1 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 ETX2 ETX3 ERX2 ERX3 ETXER ERXDV ECOL ERXCK TCLK1 PWM2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 Function Comments Table 10-4. I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Peripheral A LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 PWM0 PCK0 DRXD DTXD Peripheral B 38 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 10.3.4 PIO Controller D Multiplexing Multiplexing on PIO Controller D PIO Controller D I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 PD22 PD23 PD24 PD25 PD26 PD27 PD28 PD29 PD30 PD31 EBI0_NCS2 EBI0_A23 EBI0_A24 EBI0_A25_CFRNW EBI0_NCS3/NANDCS EBI0_D16 EBI0_D17 EBI0_D18 EBI0_D19 EBI0_D20 EBI0_D21 EBI0_D22 EBI0_D23 EBI0_D24 EBI0_D25 EBI0_D26 EBI0_D27 EBI0_D28 EBI0_D29 EBI0_D30 EBI0_D31 Peripheral A TXD1 RXD1 TXD2 RXD2 FIQ EBI0_NWAIT EBI0_NCS4/CFCS0 EBI0_NCS5/CFCS1 EBI0_CFCE1 EBI0_CFCE2 Peripheral B SPI0_NPCS2 SPI0_NPCS3 SPI1_NPCS2 SPI1_NPCS3 DMARQ2 RTS2 CTS2 RTS1 CTS1 SCK2 SCK1 TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A23 A24 A25 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOP0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0 Application Usage Function Comments Table 10-5. 39 6249HS–ATARM–27-Jul-09 10.3.5 PIO Controller E Multiplexing Multiplexing on PIO Controller E PIO Controller E Application Usage Reset State I/O I/O I/O I/O I/O I/O I/O I/O TIOA1 TIOB1 PWM3 PCK3 ISI_D8 ISI_D9 ISI_D10 ISI_D11 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TIOA0 TIOB0 EBI1_NWAIT ETXCK ECRS ETX0 ETX1 ERX0 ERX1 ERXER ETXEN EMDC EMDIO EF100 EBI1_SDCKE EBI1_RAS EBI1_CAS EBI1_SDWE EBI1_SDA10 EBI1_NANDWE EBI1_NCS2/NANDCS EB1_NANDOE EBI1_NWR3/NBS3 EBI1_NCS1/SDCS I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOP1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1 Function Comments Table 10-6. I/O Line PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31 Peripheral A ISI_D0 ISI_D1 ISI_D2 ISI_D3 ISI_D4 ISI_D5 ISI_D6 ISI_D7 ISI_PCK ISI_HSYNC ISI_VSYNC Peripheral B 40 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 10.4 10.4.1 System Resource Multiplexing LCD Controller The LCD Controller can interface with several LCD panels. It supports 4 bits per pixel (bpp), 8 bpp or 16 bpp without limitation. Interfacing 24 bpp TFT panels prevents using the Ethernet MAC. 16 bpp TFT panels are interfaced through peripheral B functions, as color data is output on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on LCDD10. Using the peripheral B does not prevent using MAC lines. 16 bpp STN panels are interfaced through peripheral A and color data is output on LCDD0 to LCDD15, thus MAC lines can be used on peripheral B. Mapping the LCD signals on peripheral A and peripheral B makes is possible to use 24 bpp TFT panels in 24 bits (peripheral A) or 16 bits (peripheral B) by reprogramming the PIO controller and thus without hardware modification. 10.4.2 ETM™ Using the ETM prevents the use of the EBI0 in 32-bit mode. Only 16-bit mode (EBI0_D0 to EBI0_D15) is available, makes EBI0 unable to interface CompactFlash and NAND Flash cards, reduces EBI0’s address bus width which makes it unable to address memory ranges bigger than 0x7FFFFF and finally it makes impossible to use EBI0_NCS2 and EBI0_NCS3. 10.4.3 EBI1 Using the following features prevents using EBI1 in 32-bit mode: • the second slots of MCI0 and/or MCI1 • USART0 • DMA request 0 (DMARQ0) 10.4.4 Ethernet 10/100MAC Using the following features of EBI1 prevents using Ethernet 10/100MAC: • SDRAM • NAND (unless NANDCS, NANDOE and NANDWE are managed by PIO) • SMC 32 bits (SMC 16 bits is still available) • NCS1, NCS2 are not available in SMC mode 10.4.5 SSC Using SSC0 prevents using the AC97 Controller and Two-wire Interface. Using SSC1 prevents using DMA Request 1, PWM0, PWM1, LCDCC and PCK1. 10.4.6 USART Using USART2 prevents using EBI0’s NWAIT signal, Chip Select 4 and CompactFlash Chip Enable 2. Using USART1 prevents using EBI0’s Chip Select 5 and CompactFlash Chip Enable1. 10.4.7 NAND Flash Using the NAND Flash interface on EBI1 prevents using Ethernet MAC. 41 6249HS–ATARM–27-Jul-09 10.4.8 CompactFlash Using the CompactFlash interface prevents using NCS4 and/or NCS5 to access other parallel devices. 10.4.9 SPI0 and MCI Interface SPI0 signals and MCI0 signals are multiplexed, as the DataFlash Card is hardware-compatible with the SDCard. Only one can be used at a time. Interrupts Using IRQ0 prevents using the CAN controller. Using FIQ prevents using DMA Request 2. 10.4.10 10.4.11 Image Sensor Interface Using ISI in 8-bit data mode prevents using timers TIOA1, TIOB1. Timers Using TIOA2 and TIOB2, in this order, prevents using SPI1’s Chip Selects [2-3]. 10.4.12 10.5 10.5.1 Embedded Peripherals Overview Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device 10.5.2 Two-wire Interface • Master Mode only • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations 42 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 10.5.3 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.5.4 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 10.5.5 AC97 Controller • Compatible with AC97 Component Specification V2.2 • Can interface with a single analog front end • Three independent RX Channels and three independent TX Channels – One RX and one TX channel dedicated to the AC97 analog front end control – One RX and one TX channel for data transfers, associated with a PDC – One RX and one TX channel for data transfers with no PDC • Time Slot Assigner that can assign up to 12 time slots to a channel • Channels support mono or stereo up to 20-bit sample length – Variable sampling rate AC97 Codec Interface (48 kHz and below) 43 6249HS–ATARM–27-Jul-09 10.5.6 Timer Counter • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 10.5.7 Pulse Width Modulation Controller • 4 channels, one 16-bit counter per channel • Common clock generator, providing thirteen different clocks – Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter outputs • Independent channel programming – Independent Enable Disable commands – Independent clock selection – Independent period and duty cycle, with double bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 10.5.8 Multimedia Card Interface • Two double-channel Multimedia Card Interfaces, allowing concurrent transfers with 2 cards • Compatibility with MultiMediaCard Specification Version 3.31 • Compatibility with SD Memory Card Specification Version 1.0 • Compatibility with SDIO Specification Version V1.1 • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used • Each MCI has two slots, each supporting – One slot for one MultiMediaCard bus (up to 30 cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write 10.5.9 CAN Controller • Fully compliant with 16-mailbox CAN 2.0A and 2.0B CAN Controllers 44 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary • Bit rates up to 1Mbit/s. • Object-oriented mailboxes, each with the following properties: – CAN Specification 2.0 Part A or 2.0 Part B programmable for each message – Object Configurable as receive (with overwrite or not) or transmit – Local Tag and Mask Filters up to 29-bit Identifier/Channel – 32 bits access to Data registers for each mailbox data object – Uses a 16-bit time stamp on receive and transmit message – Hardware concatenation of ID unmasked bitfields to speedup family ID processing – 16-bit internal timer for Time Stamping and Network synchronization – Programmable reception buffer length up to 16 mailbox object – Priority Management between transmission mailboxes – Autobaud and listening mode – Low power mode and programmable wake-up on bus activity or by the application – Data, Remote, Error and Overload Frame handling 10.5.10 USB Host Port • Compliant with Open HCI Rev 1.0 Specification • Compliant with USB V2.0 full-speed and low-speed specification • Supports both low-speed 1.5 Mbps and full-speed 12 Mbps devices • Root hub integrated with two downstream USB ports • Two embedded USB transceivers • Supports power management • Operates as a master on the matrix 10.5.11 USB Device Port • USB V2.0 full-speed compliant, 12 Mbits per second • Embedded USB V2.0 full-speed transceiver • Embedded 2,432-byte dual-port RAM for endpoints • Suspend/Resume logic • Ping-pong mode (two memory banks) for isochronous and bulk endpoints • Six general-purpose endpoints – Endpoint 0 and 3: 64 bytes, no ping-pong mode – Endpoint 1 and 2: 64 bytes, ping-pong mode – Endpoint 4 and 5: 512 bytes, ping-pong mode 10.5.12 LCD Controller • Single and Dual scan color and monochrome passive STN LCD panels supported • Single scan active TFT LCD panels supported • 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported • Up to 24-bit single scan TFT interfaces supported • Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays • 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN 45 6249HS–ATARM–27-Jul-09 • 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN • 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048x2048 • 2D DMA Controller for management of virtual Frame Buffer – Allows management of frame buffer larger than the screen size and moving the view over this virtual frame buffer • Automatic resynchronization of the frame buffer pointer to prevent flickering 10.5.13 Two D Graphics Controller • Acts as one Matrix Master • Commands are passed through the APB User Interface • Operates directly in the frame buffer of the LCD Controller – Line draw – Block transfer – Clipping • Commands queuing through a FIFO 10.5.14 Ethernet 10/100 MAC • Compatibility with IEEE Standard 802.3 • 10 and 100 Mbits per second data throughput capability • Full- and half-duplex operations • MII or RMII interface to the physical layer • Register Interface to address, data, status and control registers • DMA Interface, operating as a master on the Memory Controller • Interrupt generation to signal receive and transmit completion • 28-byte transmit and 28-byte receive FIFOs • Automatic pad and CRC generation on transmitted frames • Address checking logic to recognize four 48-bit addresses • Support promiscuous mode where all valid frames are copied to memory • Support physical layer management through MDIO interface control of alarm and update time/calendar data in 10.5.15 Image Sensor Interface • ITU-R BT. 601/656 8-bit mode external interface support • Support for ITU-R BT.656-4 SAV and EAV synchronization • Vertical and horizontal resolutions up to 2048 x 2048 • Preview Path up to 640*480 • Support for packed data formatting for YCbCr 4:2:2 formats • Preview scaler to generate smaller size image • Programmable frame capture rate 46 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 11. Package Drawing Figure 11-1. 324-ball TFBGA Package Drawing Table 11-1. Ball Land Soldering Information 0.4 mm +/- 0.05 0.275 mm +/- 0.03 Soldering Mask Opening Table 11-2. 572 Device and 324-ball TFBGA Package Maximum Weight mg Table 11-3. 324-ball TFBGA Package Characteristics 3 Moisture Sensitivity Level Table 11-4. Package Reference MO-210 e1 JEDEC Drawing Reference JESD97 Classification This package respects the recommendations of the NEMI User Group. 47 6249HS–ATARM–27-Jul-09 12. AT91SAM9263 Ordering Information Table 12-1. AT91SAM9263 Ordering Information MLR B Ordering Code AT91SAM9263B-CU Package TFBGA 324 Package Type Green Temperature Operating Range Industrial -40°C to 85°C MLR A Ordering Code AT91SAM9263-CU 48 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 AT91SAM9263 Preliminary 13. Revision History Table 13-1. Document Ref. 6249HS Revision History Change Request Ref. 6053 6395 Comments EBI0_NCS3 restriction added to Section 10.4.2 “ETM™” on page 41 Second paragraph in Section 5.3 “Programmable I/O Lines Power Supplies” on page 13 edited. 6249GS Overview: ”Features” Debug Unit (DBGU) updated. Section 10.4.3 ”EBI1”, updated Section 10.4.4 ”Ethernet 10/100MAC”, added to datasheet Section 6.5 ”Shutdown Logic Pins”, updated, “SHDN pin is tri state output.......” 5846 5903 rfo 6249FS Section 5.1 ”Power Supplies”, VDDCORE and VDDBU updated. Section 5.2, “Power Sequence Requirements removed from datasheet. 6249ES New Ordering Code: AT91SAM9263B-CU added to Table 12-1, ”AT91SAM9263 Ordering Information”. Section 8.1.2.1 ”BMS = 1, Boot on Embedded ROM”, changes to list under “Bootloader on a non-volatile memory” Section 5.2 ”Power Sequence Requirements”, section added to datasheet. Section 10.4.3 ”EBI1”, System Resource Multiplexing, Ethernet 10/100 MAC limitation on EBI1 updated. Section 10.5.8 ”Multimedia Card Interface”, protocol specification compatibilities updated. 5560 5425 5643 5713 5282 5791/5793 Section 10.5.13 ”Two D Graphics Controller”, removed reference to Polygon Fill, removed from Features also. 5206 Table 3-1, ”Signal Description List”, Image Sensor Interface, ISI_MCK is provided by PCK3. Table 10-6, ”Multiplexing on PIO Controller E”, ISI_MCK removed from PE11 line of the table. 6249DS “Features”, SPI: Synchronous Communications feature removed. Section 5.1 ”Power Supplies”, VDDIO and VDDBU slope alignment described. Section 5.2 ”Power Consumption”, paragraph beginning with “On VDDBU...” updated. Section 10.5.8 ”Multimedia Card Interface”, “When REMAP = 1.....” removed from 2nd paragraph. Section 10.5.8 ”Multimedia Card Interface”, MMC and SDMC compatibility updated. Section 8.2.1.1 ”External Bus Interface 0”, feature added. Section 8.2.1.1 ”External Bus Interface 0”, feature added. “Package and Pinout”, references to package are “324-TFBGA. Figure 9-3 ”AT91SAM9263 Power Management Controller Block Diagram” on page 30, /3 divider removed. Figure 11-1 ”324-ball TFBGA Package Drawing” on page 47, updated. 5329 4910 4967 4505 5029 4945 4146 4664 4834 4668 49 6249HS–ATARM–27-Jul-09 Table 13-1. Document Ref. 6249CS Revision History Change Request Ref. Comments In Section 4.1 “324-ball TFBGA Package Outline” on page 10 corrected package top view. 4463 All new information for Table 7-1, “List of Bus Matrix Masters,” on page 16, Table 7-2, “List of Bus Matrix Slaves,” on page 17 and Table 7-3, “Masters to Slaves Access,” on page 18. In Section 9.3 “Shutdown Controller” on page 29, corrected reference to shutdown pin. In Section 5.2 “Power Consumption” on page 13, specified static current consumption as worst case. Corrected Section 10.4.7 “NAND Flash” on page 41, with information on EMAC. 4466 3870 3825 In Section 10.4.3 “EBI1” on page 41, added Ethernet 10/100 MAC to the System Resource Multiplexing list of 4064 EBI1. In Section 10.4.11 “Image Sensor Interface” on page 42 and Section 10.4.12 “Timers” on page 42, removed 4407 mention of keyboard interfaces. Corrected typo to IDE hard disk in Section 1. “Description” on page 3. 6249BS Corrected ordering code in Section 12. “AT91SAM9263 Ordering Information” on page 48. 6249AS First issue. 3805 3804 50 AT91SAM9263 Preliminary 6249HS–ATARM–27-Jul-09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Technical Support AT91SAM Support Atmel techincal support Sales Contacts www.atmel.com/contacts/ Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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