AT91SAM9G10_1

Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 293 MIPS at 266 MHz – Memory Management Unit – EmbeddedICE™, Debug Communication Channel Support Additional Embedded Memories – 32 Kbytes of Internal ROM, Single-cycle Access at Maximum Bus Speed – 16 Kbytes of Internal SRAM, Single-cycle Access at Bus Speed External Bus Interface (EBI) – Supports SDRAM, Static Memory, NAND Flash and CompactFlash® LCD Controller – Supports Passive or Active Displays – Up to 16-bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode (24-bit per Pixel), Resolution up to 1280 x 860 USB – USB 2.0 Full Speed (12 Mbits per second) Host Double Port • OHCI Compliant • Dual On-chip Transceivers • Integrated FIFOs and Dedicated DMA Channels – USB 2.0 Full Speed (12 Mbits per second) Device Port • On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs Bus Matrix – Handles Five Masters and Five Slaves – Boot Mode Select Option – Remap Command Fully Featured System Controller (SYSC) for Efficient System Management, including – Reset Controller, Shutdown Controller, Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer – Three 32-bit PIO Controllers Reset Controller (RSTC) – Based on Power-on Reset Cells, Reset Source Identification and Reset Output Control Shutdown Controller (SHDWC) – Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) – 32,768 Hz Low-power Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 3 to 20 MHz On-chip Oscillator and two PLLs Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Four Programmable External Clock Signals • • • AT91 ARM Thumb-based Microcontrollers AT91SAM9G10 • Preliminary • • • • • • 6462A–ATARM–03-Jun-09 • Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire USART and support for Debug Communication Channel, Programmable ICE Access Prevention – Mode for General Purpose Two-wire UART Serial Communication Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) – Key Protected, Programmable Only Once, Windowed 12-bit Counter, Running at Slow Clock Real-Time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock Three 32-bit Parallel Input/Output Controllers (PIO) PIOA, PIOB and PIOC – 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output – Schmitt Trigger on All Inputs Nineteen Peripheral DMA (PDC) Channels Multimedia Card Interface (MCI) – SDCard/SDIO and MultiMediaCard™ Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC, MMC and SDCard Compliant Three Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer Three Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware and Software Handshaking, RS485 Support Two Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects One Three-channel 16-bit Timer/Counters (TC) – Three External Clock Inputs, Two multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability Two-wire Interface (TWI) – Master Mode Support, All Two-wire Atmel EEPROMs Supported – Compatibility with Standard Two-wire Serial Memories – One, Two or Three Bytes for Slave Address – Sequential Read/Write Operations – Master, Multi-master and Slave Mode Operation – Bit rate: up to 400 Kbits – GEneral Call Supported in Slave Mode IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: – 1.08V to 1.32V for VDDCORE and VDDBU – 3.0V to 3.6V for VDDOSC and for VDDPLL – 2.7V to 3.6V for VDDIOP (Peripheral I/Os) – 1.65V to 3.6V for VDDIOM (Memory I/Os) Available in a 217-ball LFBGA RoHS-compliant Package • • • • • • • • • • • • • • • 2 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 1. Description The AT91SAM9G10 is a complete system-on-chip built around the ARM926EJ-S ARM Thumb processor with an extended DSP instruction set and Jazelle Java accelerator. It achieves 293 MIPS at 266 MHz. The AT91SAM9G10 is an optimized host processor for applications with an LCD display. Its integrated LCD controller supports BW and up to 16M color, active and passive LCD displays. The External Bus Interface incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific interface circuitry for CompactFlash and NAND Flash. The AT91SAM9G10 integrates a ROM-based Boot Loader supporting code shadowing from, for example, external DataFlash® into external SDRAM. The software controlled Power Management Controller (PMC) keeps system power consumption to a minimum by selectively enabling/disabling the processor and various peripherals and adjustment of the operating frequency. The AT91SAM9G10 also benefits from the integration of a wide range of debug features including JTAG-ICE, a dedicated UART debug channel (DBGU). This enables the development and debug of all applications, especially those with real-time constraints. 3 6462A–ATARM–03-Jun-09 2. Block Diagram Figure 2-1. JTAGSEL TDI TDO TMS TCK NTRST RTCK AT91SAM9G10 Block Diagram ARM926EJ-S Core JTAG Boundary Scan ICE Instruction Cache 16K bytes MMU BIU I D Data Cache 16K bytes PIO System Controller TST FIQ IRQ0-IRQ2 DRXD DTXD PCK0-PCK3 PLLRCA PLLRCB XIN XOUT AIC PIO DBGU PDC Fast SRAM 16K bytes EBI CompactFlash NAND Flash PLLA PLLB OSC PMC Fast ROM 32K bytes 5-layer Matrix PIT Peripheral Bridge Peripheral DMA Controller DMA RSTC POR APB PIOA PIOB PIOC FIFO USB Device USB Host FIFO Transceiver WDT SDRAM Controller GPBREG XIN32 XOUT32 SHDN WKUP VDDBU GNDBU VDDCORE NRST POR OSC RTT SHDWC Static Memory Controller BMS D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15/A18-A21 A22/REG A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE RAS-CAS SDWE SDA10 NWAIT A23-A24 A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 NCS6/NANDOE NCS7/NANDWE D16-D31 HDMA HDPA HDMB HDPB Transceiver PIO DDM DDP DMA MCCK MCCDA MCDA0-MCDA3 FIFO MCI PDC RXD0 TXD0 SCK0 RTS0 CTS0 RXD1 TXD1 SCK1 RTS1 CTS1 RXD2 TXD2 SCK2 RTS2 CTS2 SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 SPI0_MISO SPI0_MOSI SPI0_SPCK SPI1_NPCS10 SPI1_NPCS1 SPI1_NPCS12 SPI1_NPCS3 SPI1_MISO SPI1_MOSI SPI1_SPCK LUT LCD Controller LCDD0-LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC TF0 TK0 TD0 RD0 RK0 RF0 TF1 TK1 TD1 RD1 RK1 RF1 TF2 TK2 TD2 RD2 RK2 RF2 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TWD TWCK USART0 PDC PDC SSC0 USART1 PIO PIO SSC1 PDC PDC PIO SSC2 PDC Timer Counter TC0 TC1 TC2 TWI PDC USART2 PDC SPI0 PDC SPI1 4 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 3. Signal Description Table 3-1. Signal Name VDDIOM VDDIOP VDDBU VDDPLL VDDOSC VDDCORE GND GNDPLL GNDOSC GNDBU XIN XOUT XIN32 XOUT32 PLLRCA PLLRCB PCK0 - PCK3 SHDN WKUP TCK RTCK TDI TDO TMS NTRST JTAGSEL Signal Description by Peripheral Function Power EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply Backup I/O Lines Power Supply PLL Power Supply Oscillator Power Supply Core Chip Power Supply Ground PLL Ground Oscillator Ground Backup Ground Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output PLL Filter PLL Filter Programmable Clock Output Shutdown Control Wake-Up Input Test Clock Returned Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal JTAG Selection Power Power Power Power Power Power Ground Ground Ground Ground Clocks, Oscillators and PLLs Input Output Input Output Input Input Output Output Input ICE and JTAG Input Output Input Output Input Input Input Reset/Test Low No pull-up resistor. Pull-up resistor. Pull-down resistor. Accepts between 0V and VDDBU. Low Pull-up resistor Pull-down resistor. No pull-up resistor. No pull-up resistor. No pull-up resistor. Do not tie over VDDBU. Accepts between 0V and VDDBU. Shutdown, Wakeup Logic 1.65 V to 1.95V and 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V Type Active Level Comments NRST TST BMS DRXD DTXD Microcontroller Reset Test Mode Select Boot Mode Select Debug Receive Data Debug Transmit Data I/O Input Input Debug Unit Input Output 5 6462A–ATARM–03-Jun-09 Table 3-1. Signal Name IRQ0 - IRQ2 FIQ PA0 - PA31 PB0 - PB31 PC0 - PC31 D0 - D31 A0 - A25 NWAIT NCS0 - NCS7 Signal Description by Peripheral (Continued) Function AIC External Interrupt Inputs Fast Interrupt Input PIO Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C EBI Data Bus Address Bus External Wait Signal SMC Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines NAND Flash Output Enable NAND Flash Write Enable NAND Flash Chip Select SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Multimedia Card Clock Multimedia Card A Command Multimedia Card A Data Output Output Output Output Output CompactFlash Support Output Output Output Output Output Output Output Output Output Output SDRAM Controller Output Output Output Output Output Output Output Multimedia Card Interface Output I/O I/O Low Low High Low Low Low Low Low Low Low Low Low Low Low Low Low Low Low I/O Output Input Low Pulled-up input at reset 0 at reset I/O I/O I/O Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Input Input Type Active Level Comments NWR0 - NWR3 NRD NWE NBS0 - NBS3 CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 NANDOE NANDWE NANDCS SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 MCCK MCCDA MCDA0 - MCDA3 NAND Flash Support 6 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 3-1. Signal Name SCK0 - SCK2 TXD0 - TXD2 RXD0 - RXD2 RTS0 - RTS2 CTS0 - CTS2 TD0 - TD2 RD0 - RD2 TK0 - TK2 RK0 - RK2 TF0 - TF2 RF0 - RF2 TCLK0 - TCLK2 TIOA0 - TIOA2 TIOB0 - TIOB2 SPI0_MISO SPI1_MISO SPI0_MOSI SPI1_MOSI SPI0_SPCK SPI1_SPCK SPI0_NPCS0, SPI1_NPCS0 SPI0_NPCS1 SPI0_NPCS3 SPI1_NPCS1 SPI1_NPCS3 TWD TWCK LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC DDM DDP Signal Description by Peripheral (Continued) Function USART Serial Clock Transmit Data Receive Data Request To Send Clear To Send Transmit Data Receive Data Transmit Clock Receive Clock Transmit Frame Sync Receive Frame Sync External Clock Input I/O Line A I/O Line B SPI Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 I/O I/O I/O I/O Low I/O Output Input Output Input Synchronous Serial Controller Output Input I/O I/O I/O I/O Timer/Counter Input I/O I/O Type Active Level Comments SPI Peripheral Chip Select Output Low Two-Wire Interface Two-wire Serial Data Two-wire Serial Clock LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control USB Device Port Data USB Device Port Data + I/O I/O LCD Controller Output Output Output Output Output Output USB Device Port Analog Analog 7 6462A–ATARM–03-Jun-09 Table 3-1. Signal Name HDMA HDPA HDMB HDPB Signal Description by Peripheral (Continued) Function USB Host Port A Data USB Host Port A Data + USB Host Port B Data USB Host Port B Data + Type USB Host Port Analog Analog Analog Analog Active Level Comments 8 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 4. Package and Pinout The AT91SAM9G10 is available in a 217-ball LFBGA RoHS-compliant package, 15 x 15 mm, 0.8 mm ball pitch 4.1 217-ball LFBGA Package Outline Figure 4-1 shows the orientation of the 217-ball LFBGA Package. A detailed mechanical description is given in the section “AT91SAM9G10 Mechanical Characteristics” of the product datasheet. Figure 4-1. 217-ball LFBGA Package Outline (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEFGH J K LMNPRTU Ball A1 9 6462A–ATARM–03-Jun-09 4.2 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 Pinout AT91SAM9G10 Pinout for 217-ball LFBGA Package (1) Signal Name A19 A16/BA0 A14 A12 A9 A6 A3 A2 NC XOUT32 XIN32 DDP HDPB HDMB PB27 GND PB24 A20 A18 A15 A13 A11 A7 A4 A1/NBS2/NWR2 VDDBU JTAGSEL WKUP DDM PB31 HDMA PB26 PB25 PB19 A22 A21 VDDIOM A17/BA1 VDDIOM A8 GND VDDIOM GNDBU TST GND HDPA PB30 NC VDDIOP PB21 TMS NCS2 NCS1/SDCS GND VDDIOM Table 4-1. Pin D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J8 J9 J10 Signal Name VDDCORE A10 A5 A0/NBS0 SHDN NC VDDIOP PB29 PB28 PB23 PB20 PB17 TCK NWR1/NBS1/CFIOR NWR0/NWE/CFWE NRD/CFOE SDA10 PB22 PB18 PB15 TDI SDCKE RAS NWR3/NBS3/CFIOW NCS0 PB16 NRST TDO NTRST D0 D1 SDWE NCS3/NANDCS PB14 PB12 PB11 PB8 D2 D3 VDDIOM SDCK GND GND GND PB10 PB13 PB7 PB5 D4 D5 GND CAS GND GND GND Pin J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name VDDIOP PB9 PB6 PB4 D6 D8 D10 D7 GND GND GND VDDCORE PB3/BMS PB1 PB2 D9 D11 D12 VDDIOM PA30 PA27 PA31 PB0 D13 D15 PC18 VDDCORE PA25 PA26 PA28 PA29 D14 PC17 PC31 VDDIOM PA22 PA21 PA23 PA24 PC16 PC30 PC22 PC24 PC28 PC1 PC7 PC11 GNDPLL PA3 VDDIOP VDDCORE PA15 PA16 VDDIOP PA19 Pin P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PA20 PC19 PC21 GND PC27 PC29 PC4 PC8 PC12 PC14 VDDPLL PA0 PA7 PA10 PA13 PA17 GND PA18 PC20 PC23 PC26 PC2 VDDIOP PC5 PC9 PC10 PC15 VDDOSC GNDOSC PA1 PA4 PA6 PA8 PA11 PA14 PC25 PC0 PC3 GND PC6 VDDIOP GND PC13 PLLRCB PLLRCA XIN XOUT PA2 PA5 PA12 PA9 RTCK Note: 1. Shaded cells define the pins powered by VDDIOM. 10 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 5. Power Considerations 5.1 Power Supplies The AT91SAM9G10 has six types of power supply pins: • VDDCORE pins: Power the core, including the processor, the memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges from 1.65V to 1.95V and 3.0V to 3.6V, 1.8V and 3.3V nominal. • VDDIOP pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from 2.7V and 3.6V, 3.3V nominal. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDPLL pin: Powers the PLL cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal. • VDDOSC pin: Powers the Main Oscillator cells; voltage ranges from 3.0V and 3.6V, 3.3V nominal. The double power supplies VDDIOM and VDDIOP are identified in Table 4-1 on page 10. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Separated ground pins are provided for VDDBU, VDDOSC and VDDPLL. The ground pins are GNDBU, GNDOSC and GNDPLL, respectively. 6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. The NTRST pin is used to initialize the embedded ICE TAP Controller when asserted at a low level. It integrates a permanent pull-up resistor of about 15 kΩ to VDDIOP, so that it can be left unconnected for normal operations. 6.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. 6.3 Reset Pin NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. As the product integrates power-on reset cells, the NRST pin can be left unconnected in case no reset from the system needs to be applied to the product. 11 6462A–ATARM–03-Jun-09 The NRST pin integrates a permanent pull-up resistor of 100 kΩ minimum to VDDIOP. The NRST signal is inserted in the Boundary Scan. 6.4 PIO Controller A, B and C Lines All the I/O lines PA0 to PA31, PB0 to PB31, and PC0 to PC31 integrate a programmable pull-up resistor of 100 kΩ. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripherals at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shutdown Logic Pins The SHDN pin is an output only, driven by Shutdown Controller. The pin WKUP is an input only. It can accept voltages only between 0V and VDDBU. 12 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 7. Processor and Architecture 7.1 ARM926EJ-S Processor • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration • Two Instruction Sets – ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set • DSP Instruction Extensions • 5-Stage Pipeline Architecture: – Instruction Fetch (F) – Instruction Decode (D) – Execute (E) – Data Memory (M) – Register Write (W) • 16 Kbyte Data Cache, 16 Kbyte Instruction Cache – Virtually-addressed 4-way Associative Cache – Eight words per line – Write-through and Write-back Operation – Pseudo-random or Round-robin Replacement • Write Buffer – Main Write Buffer with 16-word Data Buffer and 4-address Buffer – DCache Write-back Buffer with 8-word Entries and a Single Address Entry – Software Control Drain • Standard ARM v4 and v5 Memory Management Unit (MMU) – Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for each quarter of the page – 16 embedded domains • Bus Interface Unit (BIU) – Arbitrates and Schedules AHB Requests – Separate Masters for both instruction and data access providing complete AHB system flexibility – Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface – On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) 13 6462A–ATARM–03-Jun-09 7.2 Debug and Test Features • Integrated Embedded In-circuit Emulator Real-Time – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 7.3 Bus Matrix • Five Masters and Five Slaves handled – Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD Controller and USB Host Port. – Round-Robin Arbitration (three modes supported: no default master, last accessed default master, fixed default master) – Burst Breaking with Slot Cycle Limit • One Address Decoder Provided per Master – Three different slaves may be assigned to each decoded memory area: one for internal boot, one for external boot, one after remap. • Boot Mode Select Option – Non-volatile Boot Memory can be Internal or External. – Selection is made by BMS pin sampled at reset. • Remap Command – Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory – Allows Handling of Dynamic Exception Vectors 7.4 Peripheral DMA Controller • Transfers from/to peripheral to/from any memory space without intervention of the processor. • Next Pointer Support, forbids strong real-time constraints on buffer management. • Nineteen channels – Two for each USART – Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – One for the Multimedia Card Interface 14 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 8. Memories Figure 8-1. AT91SAM9G10 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF 0x0000 0000 Internal Memory Mapping Notes : (1) Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP 256M Bytes 0x10 0000 Boot Memory (1) 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF Reserved 256M Bytes 0x20 0000 Reserved 0x30 0000 0x2000 0000 EBI Chip Select 1/ SDRAMC 256M Bytes SRAM 0x40 0000 1M Bytes 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 0x50 0000 ROM 256M Bytes UHP User Interface 0x60 0000 1M Bytes 1M Bytes 0x4000 0000 EBI Chip Select 3/ NAND Flash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 EBI Chip Select 6 256M Bytes 0x70 0000 LCD User Interface 1M Bytes 0x4FFF FFFF 0x5000 0000 Reserved 256M Bytes 0x0FFF FFFF 0x5FFF FFFF 0x6000 0000 256M Bytes System Controller Mapping 0xFFFF C000 0x6FFF FFFF 0x7000 0000 256M Bytes Peripheral Mapping 0xF000 0000 0x7FFF FFFF Reserved 0x8000 0000 EBI Chip Select 7 0x8FFF FFFF 256M Bytes 0xFFFA 0000 Reserved 0xFFFF EA00 SDRAMC TCO, TC1, TC2 16K Bytes 16K Bytes 0xFFFF EE00 16K Bytes 0xFFFF F000 16K Bytes 0xFFFF F200 0xFFFF EC00 512 Bytes 0x9000 0000 0xFFFA 4000 SMC UDP 512 Bytes 0xFFFA 8000 MATRIX 512 Bytes MCI 0xFFFA C000 TWI 0xFFFB 0000 AIC DBGU 0xFFFF F400 512 Bytes USART0 0xFFFB 4000 16K Bytes 16K Bytes 0xFFFF F600 512 Bytes USART1 0xFFFB 8000 PIOA 512 Bytes Undefined (Abort) 1,518M Bytes 0xFFFB C000 USART2 SSC0 0xFFFC 0000 16K Bytes PIOB 0xFFFF F800 16K Bytes 512 bytes PIOC 0xFFFF FA00 16K Bytes 512 bytes SSC1 0xFFFC 4000 Reserved 16K Bytes 0xFFFF FC00 SSC2 0xFFFC 8000 PMC 16K Bytes 16K Bytes 0xFFFF FD00 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes SPI0 0xFFFC C000 RSTC 0xFFFF FD10 0xFFFF FD20 0xFFFF FD30 SHDWC RTT PIT WDT GPBR Reserved SPI1 0xFFFC D000 0xEFFF FFFF 0xF000 0000 Internal Peripherals 0xFFFF FFFF Reserved 256M Bytes 0xFFFF C000 0xFFFF FD40 0xFFFF FD50 0xFFFF FD60 SYSC 0xFFFF FFFF 16K Bytes 0xFFFF FFFF 15 6462A–ATARM–03-Jun-09 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 areas of 256 Mbytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NCS0 to NCS7. The area 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. The area 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. The Bus Matrix manages five Masters and five Slaves. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. Regarding Master 0 and Master 1 (ARM926™ Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 8-3 for details. Table 8-1. Master 0 Master 1 Master 2 Master 3 Master 4 List of Bus Matrix Masters ARM926 Instruction ARM926 Data PDC LCD Controller USB Host Each Slave has its own arbiter, thus allowing a different arbitration per Slave. Table 8-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 List of Bus Matrix Slaves Internal SRAM Internal ROM LCD Controller and USB Host Port Interfaces External Bus Interface Internal Peripherals 8.1 Embedded Memories • 32 KB ROM – Single Cycle Access at full bus speed • 16 KB Fast SRAM – Single Cycle Access at full bus speed 16 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 8.1.1 Internal Memory Mapping Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Internal Memory Mapping Master 0: ARM926 Instruction REMAP(RCB0) = 0 BMS = 1 0x0000 0000 Note: Int. ROM BMS = 0 EBI NCS0(1) Int. RAM C REMAP (RCB0) = 1 Master 1: ARM926 Data REMAP (RCB1) = 0 BMS = 1 Int. ROM BMS = 0 EBI NCS0(1) Int. RAM C REMAP (RCB1) = 1 Table 8-3. Address 1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers. 8.1.1.1 Internal SRAM The AT91SAM9G10 embeds a high-speed 16-Kbyte SRAM. Internal ROM The AT91SAM9G10 integrates a 32-Kbyte Internal ROM mapped at address 0x0040 0000. It is also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset. USB Host Port The AT91SAM9G10 integrates a USB Host Port Open Host Controller Interface (OHCI). The registers of this interface are directly accessible on the AHB Bus and are mapped like a standard internal memory at address 0x0050 0000. LCD Controller The AT91SAM9G10 integrates an LCD Controller. The interface is directly accessible on the AHB Bus and is mapped like a standard internal memory at address 0x0060 0000. Boot Strategies The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted for each Master of the Bus Matrix. Refer to the Bus Matrix Section for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 8-1 on page 15. 8.1.1.2 8.1.1.3 8.1.1.4 8.1.2 The AT91SAM9G10 Bus Matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 17 6462A–ATARM–03-Jun-09 8.1.2.1 BMS = 1, Boot on Embedded ROM The system boots using the Boot Program. • Enable the 32,768 Hz oscillator • Auto baudrate detection • Downloads and runs an application from external storage media into internal SRAM • Automatic detection of valid application • Bootloader on a non-volatile memory – SPI Serial Flash or DataFlash® connected on NPCS0 of the SPI0 – NAND Flash – SDCard (boot ROM does not support high-capacity SDCards) • SAM-BA Boot in case no valid program is detected in external NVM, supporting – Serial communication on a DBGU – USB Device HS Port 8.1.2.2 BMS = 0, Boot on External Memory • Boot on slow clock (32,768 Hz) • Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS=0), the user must take the following steps: 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock 4. Switch the main clock to the new value. 8.2 External Memories The external memories are accessed through the External Bus Interface (Bus Matrix Slave 3). Refer to the memory map in Figure 8-1 on page 15. 18 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 9. System Controller The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset. The System Peripherals are all mapped within the highest 6 Kbytes of address space, between addresses 0xFFFF EA00 and 0xFFFF FFFF. Each peripheral has an address space of 256 or 512 Bytes, representing 64 or 128 registers. Figure 9-1 on page 20 shows the System Controller block diagram. Figure 8-1 on page 15 shows the mapping of the User Interfaces of the System Controller peripherals. 19 6462A–ATARM–03-Jun-09 9.1 Block Diagram System Controller Block Diagram System Controller irq0-irq2 fiq periph_irq[2..21] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset VDDCORE Powered NRST VDDCORE POR ice_nreset jtag_nreset periph_nreset proc_nreset backup_nreset rstc_irq SLCK SLCK backup_nreset SLCK rtt_alarm Real-Time Timer rtt_irq rtt_alarm Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC MCK periph_nreset Bus Matrix Debug Unit nirq nfiq Figure 9-1. Advanced Interrupt Controller int ice_nreset force_ntrst dbgu_irq force_ntrst dbgu_txd pit_irq ntrst ARM926EJ-S proc_nreset PCK debug wdt_irq jtag_nreset Boundary Scan TAP Controller Reset Controller UDPCK periph_clk[10] periph_nreset periph_irq[10] usb_suspend USB Device Port VDDBU POR SHDN WKUP Shutdown Controller UHPCK periph_clk[20] USB Host Port backup_nreset VDDBU Powered 4 General-purpose Backup Registers periph_nreset periph_irq[20] LCDCK periph_clk[21] periph_nreset periph_irq[21] XIN32 XOUT32 XIN XOUT PLLRCA PLLRCB SLOW CLOCK OSC SLCK periph_clk[2..21] pck[0-3] MAINCK Power Management Controller PCK UDPCK UHPCK LCDCK MCK pmc_irq idle MAIN OSC PLLA PLLB int periph_nreset usb_suspend periph_nreset periph_clk[2..4] dbgu_rxd LCD Controller PLLACK PLLBCK periph_clk[6..21] periph_nreset Embedded Peripherals PA0-PA31 PB0-PB31 PC0-PC31 PIO Controllers periph_irq{2..4] irq0-irq2 fiq dbgu_txd periph_irq[6..21] in out enable 20 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 9.2 Reset Controller • Based on two Power-on-Reset cells • Status of the last reset – Either cold reset, first reset, soft reset, user reset, watchdog reset, wake-up reset • Controls the internal resets and the NRST pin output 9.3 Shutdown Controller • Shutdown and Wake-up logic: – Software programmable assertion of the SHDN pin – Deassertion Programmable on a WKUP pin level change or on alarm 9.4 General-purpose Backup Registers • Four 32-bit general-purpose backup registers 9.5 Clock Generator • Embeds the Low-power 32,768 Hz Slow Clock Oscillator – Provides the permanent Slow Clock to the system • Embeds the Main Oscillator – Oscillator bypass feature – Supports 3 to 20 MHz crystals • Embeds Two PLLs – Outputs 80 to 300 MHz clocks – Integrates an input divider to increase output accuracy – 1 MHz minimum input frequency • Provides SLCK, MAINCK, PLLACK and PLLBCK. Figure 9-2. Clock Generator Block Diagram Clock Generator XIN32 XOUT32 XIN XOUT Main Oscillator Main Clock MAINCK Slow Clock Oscillator Slow Clock SLCK PLLRCA PLL and Divider A PLL and Divider B Status Control PLLA Clock PLLACK PLLB Clock PLLBCK PLLRCB Power Management Controller 21 6462A–ATARM–03-Jun-09 9.6 Power Management Controller • The Power Management Controller provides: – the Processor Clock PCK – the Master Clock MCK – the USB Clock USBCK (HCK0) – the LCD Controller Clock LCDCK (HCK1) – up to thirty peripheral clocks – four programmable clock outputs: PCK0 to PCK3 Figure 9-3. Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 Divider /1,/2,/3,/4 APB Peripherals Clock Controller ON/OFF AHB Peripherals Clock Controller ON/OFF Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 pck[0..3] Idle Mode MCK periph_clk[2..21] PCK int HCKx PLLBCK USB Clock Controller ON/OFF Divider /1,/2,/4 usb_suspend UDPCK UHPCK 9.7 Periodic Interval Timer • Includes a 20-bit Periodic Counter with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real time OS or Linux®/WindowsCE® compliant tick generator 9.8 Watchdog Timer • 12-bit key-protected only-once programmable counter • Windowed, prevents the processor to be in a dead-lock on the watchdog access 9.9 Real-time Timer • 32-bit Free-running backup counter • Alarm Register capable to generate a wake-up of the system 22 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 9.10 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Source 2 to Source 31 control up to thirty embedded peripheral interrupts or external interrupts – Programmable edge-triggered or level-sensitive internal sources – Programmable positive/negative edge-triggered or high/low level-sensitive • Four External Sources • 8-level Priority Controller – Drives the normal interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode – Easy debugging by preventing automatic operations when protect mode is enabled • Fast Forcing – Permits redirecting any normal interrupt source on the Fast Interrupt of the processor • General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt 9.11 Debug Unit • Composed of four functions – Two-pin UART – Debug Communication Channel (DCC) support – Chip ID Registers – ICE Access Prevention • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support 23 6462A–ATARM–03-Jun-09 – Offers visibility of COMMRX and COMMTX signals from the ARM Processor • Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of peripherals • ICE Access prevention – Enables software to prevent system access through the ARM Processor’s ICE – Prevention is made by asserting the NTRST line of the ARM Processor’s ICE 9.12 PIO Controllers • Three PIO Controllers, each controlling up to 32 programmable I/O Lines – PIOA has 32 I/O Lines – PIOB has 32 I/O Lines – PIOC has 32 I/O Lines • Fully programmable through Set/Clear Registers • Multiplexing of two peripheral functions per I/O Line • For each I/O Line (whether assigned to a peripheral or used as general-purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 24 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 10. Peripherals 10.1 User Interface The User Peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 8-1 on page 15. 10.2 Peripheral Identifiers Table 10-1 defines the Peripheral Identifiers of the AT91SAM9G10. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 - 28 29 30 31 Peripheral Identifiers Peripheral Mnemonic AIC SYSIRQ PIOA PIOB PIOC US0 US1 US2 MCI UDP TWI SPI0 SPI1 SSC0 SSC1 SSC2 TC0 TC1 TC2 UHP LCDC AIC AIC AIC Peripheral Name Advanced Interrupt Controller System Interrupt Parallel I/O Controller A Parallel I/O Controller B Parallel I/O Controller C Reserved USART 0 USART 1 USART 2 Multimedia Card Interface USB Device Port Two-Wire Interface Serial Peripheral Interface 0 Serial Peripheral Interface 1 Synchronous Serial Controller 0 Synchronous Serial Controller 1 Synchronous Serial Controller 2 Timer/Counter 0 Timer/Counter 1 Timer/Counter 2 USB Host Port LCD Controller Reserved Advanced Interrupt Controller Advanced Interrupt Controller Advanced Interrupt Controller IRQ0 IRQ1 IRQ2 External Interrupt FIQ Note: Setting AIC, SYSIRQ, UHP, LCDC and IRQ0 to IRQ2 bits in the clock set/clear registers of the PMC has no effect. 25 6462A–ATARM–03-Jun-09 10.3 Peripheral Multiplexing on PIO Lines The AT91SAM9G10 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to thirty-two lines. Each line can be assigned to one of two peripheral functions, A or B. Table 10-2 on page 28, Table 10-3 on page 29 and Table 10-4 on page 30 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application. Note that some output only peripheral functions might be duplicated within the tables. The column “Reset State” indicates whether the PIO line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 10.3.1 10.3.1.1 Resource Multiplexing LCD Controller The LCD Controller can interface with several LCD panels. It supports 4, 8 or 16 bit-per-pixel without any limitation. Interfacing 24 bit-per-pixel TFTs panel prevents using the SSC0 and the chip select line 0 of the SPI1. 16 bit-per-pixel TFT panels are interfaced through peripheral B functions, as color data is output on LCDD3 to LCDD7, LCDD11 to LCDD15 and LCDD19 to LCDD23. Intensity bit is output on LCDD2, LCDD10 and LCDD18. Using the peripheral B does not prevent using the SSC0 and the SPI1 lines. 10.3.1.2 EBI If not required, the NWAIT function (external wait request) can be deactivated by software, allowing this pin to be used as a PIO. 10.3.1.3 32-bit Data Bus Using a 32-bit Data Bus prevents: • using the three Timer Counter channels’ outputs and trigger inputs • using the SSC2 10.3.1.4 NAND Flash Interface Using the NAND Flash interface prevents: • using NCS3, NCS6 and NCS7 to access other parallel devices 10.3.1.5 Compact Flash Interface Using the CompactFlash interface prevents: • using NCS4 and/or NCS5 to access other parallel devices 26 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 10.3.1.6 SPI0 and the MultiMedia Card Interface As the DataFlash Card is compatible with the SDCard, it is useful to multiplex SPI and MCI. Here, the SPI0 signal is multiplexed with the MCI. USARTs • Using USART0 with its control signals prevents using some clock outputs and interrupt lines. 10.3.1.8 Clock Outputs • Using the clock outputs multiplexed with the PIO A prevents using the Debug Unit and/or the Two Wire Interface. • Alternatively, using the second implementation of the clock outputs prevents using the LCD Controller Interface and/or USART0. 10.3.1.9 Interrupt Lines • Using FIQ prevents using the USART0 control signals. • Using IRQ0 prevents using the NWAIT EBI signal. • Using the IRQ1 and/or IRQ2 prevents using the SPI1. 10.3.1.7 27 6462A–ATARM–03-Jun-09 10.3.2 PIO Controller A Multiplexing Multiplexing on PIO Controller A PIO Controller A Application Usage Reset State I/O I/O I/O I/O MCDA1 MCDA2 MCDA3 PCK0 PCK1 PCK2 PCK3 SCK1 RTS1 CTS1 SCK2 RTS2 CTS2 TF1 TK1 TD1 RD1 RK1 RF1 RTS0 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS3 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 A23 A24 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O A23 A24 Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOM VDDIOM Function Comments Table 10-2. I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A SPI0_MISO SPI0_MOSI SPI0_SPCK SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS3 TWD TWCK DRXD DTXD TSYNC TCLK TPS0 TPS1 TPS2 TPK0 TPK1 TPK2 TPK3 TPK4 TPK5 TPK6 TPK7 TPK8 TPK9 TPK10 TPK11 TPK12 TPK13 TPK14 TPK15 Peripheral B MCDA0 MCCDA MCCK Comments 28 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 10.3.3 PIO Controller B Multiplexing Multiplexing on PIO Controller B PIO Controller B I/O Line PB0 PB1 PB2 PB3 (1) Table 10-3. Application Usage Reset State I/O I/O Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Function Comments Peripheral A LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 TF0 TK0 TD0 RD0 RK0 RF0 SPI1_NPCS1 SPI1_NPCS0 SPI1_SPCK SPI1_MISO SPI1_MOSI Peripheral B Comments PCK0 See footnote LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 IRQ2 IRQ1 PCK2 (1) I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Note: 1. PB3 is multiplexed with BMS signal. Care should be taken during reset time. 29 6462A–ATARM–03-Jun-09 10.3.4 PIO Controller C Multiplexing Multiplexing on PIO Controller C PIO Controller C Application Usage Reset State I/O I/O I/O A25 I/O I/O I/O I/O PCK2 PCK3 SCK0 FIQ NCS6 NCS7 SPI1_NPCS2 SPI1_NPCS3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2 TF2 TK2 TD2 RD2 RK2 RF2 PCK1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOM VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOM VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function Comments Table 10-4. I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Peripheral A NANDOE NANDWE NWAIT A25/CFRNW NCS4/CFCS0 NCS5/CFCS1 CFCE1 CFCE2 TXD0 RXD0 RTS0 CTS0 TXD1 RXD1 TXD2 RXD2 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Peripheral B NCS6 NCS7 IRQ0 Comments 30 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 10.3.5 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-Time Timer • the Watchdog Timer • the Reset Controller • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.3.6 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.4 External Bus Interface • Integrates two External Memory Controllers: – Static Memory Controller – SDRAM Controller • Additional logic for NAND Flash and CompactFlash support – NAND Flash support: 8-bit as well as 16-bit devices are supported – CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True IDE) are supported but the signals -IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled. • Optimized External Bus – 16- or 32-bit Data Bus – Up to 26-bit Address Bus, up to 64 Mbytes addressable – Eight Chip Selects, each reserved to one of the eight Memory Areas – Optimized pin multiplexing to reduce latencies on External Memories • Configurable Chip Select Assignment Managed by EBI_CSA Register located in the MATRIX user interface – Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3, Optional NAND Flash Support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash Support – Static Memory Controller on NCS6 - NCS7 31 6462A–ATARM–03-Jun-09 10.5 Static Memory Controller • External memory mapping, 256 Mbyte address space per Chip Select Line • Up to Eight Chip Select Lines • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability – Compliant with LCD Module – Control signal programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock Mode Supported 10.6 SDRAM Controller • Supported Devices – Standard and Low Power SDRAM (Mobile SDRAM) • Numerous configurations supported – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming Facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving Capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • CAS Latency of 1, 2 and 3 supported • Auto Precharge Command not used 32 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 10.7 Serial Peripheral Interface • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to fifteen peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device 10.8 Two-wire Interface • Compatibility with standard two-wire serial memories • One, two or three bytes for slave address • Sequential read/write operations • Supports either master or slave modes • Master, multi-master and slave mode operation • Bit rate: up to 400 Kbits • General call supported in slave mode 10.9 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first – Optional break generation and detection – By-8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding 33 6462A–ATARM–03-Jun-09 • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.10 Synchronous Serial Controller • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader and more). • Contains an independent receiver and transmitter and a common clock divider. • Offers a configurable frame sync and data length. • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal. • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal. 10.11 Timer Counter • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 10.12 MultiMediaCard Interface • Two double-channel MultiMediaCard Interfaces, allowing concurrent transfers with 2 cards • Compatibility with MultiMediaCard Specification Version 3.31 • Compatibility with SD Memory Card Specification Version 1.0 • Compatibility with SDIO Specification Version V1.1 • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used 34 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 • Each MCI has two slots, each supporting – One slot for one MultiMediaCard bus (up to 30 cards) or – One SD Memory Card • Support for stream, block and multi-block data read and write 10.13 USB • USB Host Port: – Compliance with Open HCI Rev 1.0 specification – Compliance with USB V2.0 Full-speed and Low-speed Specification – Supports both Low-speed 1.5 Mbps and Full-speed 12 Mbps USB devices – Root hub integrated with two downstream USB ports – Two embedded USB transceivers – No overcurrent detection – Supports power management – Operates as a master on the Bus Matrix • USB Device Port: – USB V2.0 full-speed compliant, 12 Mbits per second – Embedded USB V2.0 full-speed transceiver – Embedded dual-port RAM for endpoints – Suspend/Resume logic – Ping-pong mode (two memory banks) for isochronous and bulk endpoints – Six general-purpose endpoints: Endpoint 0: 8 bytes, no ping-pong mode Endpoint 1, Endpoint 2: 64 bytes, ping-pong mode Endpoint 3: 64 bytes, no ping-pong mode Endpoint 4, Endpoint 5: 256 bytes, ping-pong mode • Embedded pad pull-up configurable via USB_PUCR Register located in the MATRIX user interface 10.14 LCD Controller • Single and Dual scan color and monochrome passive STN LCD panels supported • Single scan active TFT LCD panels supported. • 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported • Up to 24-bit single scan TFT interfaces supported • Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays • 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN • 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN • 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 1280 x 860 35 6462A–ATARM–03-Jun-09 36 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 11. ARM926EJ-S Processor Description 11.1 Overview The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multitasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Javapowered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S™ integer core • a Memory Management Unit (MMU) • separate instruction and data AMBA™ AHB bus interfaces 37 6462A–ATARM–03-Jun-09 11.2 11.2.1 ARM9EJ-S Processor ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: • ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 11.2.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC • ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 11.2.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 11.2.4 Memory Access The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data. 11.2.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode appears as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. 38 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 11.2.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: • User mode is the usual ARM program execution state. It is used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling • Supervisor mode is a protected mode for the operating system • Abort mode is entered after a data or instruction prefetch abort • System mode is a privileged user mode for the operating system • Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 11.2.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers. • 31 general-purpose 32-bit registers • 6 32-bit status registers Table 11-1 shows all the registers in all modes. Table 11-1. User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 ARM9TDMI™ Modes and Registers Layout Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 39 6462A–ATARM–03-Jun-09 Table 11-1. User and System Mode R11 R12 R13 R14 PC ARM9TDMI™ Modes and Registers Layout Supervisor Mode R11 R12 R13_SVC R14_SVC PC Undefined Mode R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC Abort Mode R11 R12 R13_ABORT R14_ABORT PC CPSR CPSR SPSR_SVC CPSR SPSR_ABORT CPSR SPSR_UNDEF CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines: • constraints on the use of registers • stack conventions • argument passing and result return The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC 40 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 • CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12). 11.2.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode Figure 11-1. Status Register Format 31 30 29 28 27 24 765 0 NZCVQ J Reserved I FT Mode Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than Mode bits Thumb state bit FIQ disable IRQ disable Figure 11-1 shows the status register format, where: • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. • The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where: – J = 0: The processor is in ARM or Thumb state, depending on the T bit – J = 1: The processor is in Jazelle state. • Mode: five bits to encode the current processor mode 11.2.7.2 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi- leged mode. The types of exceptions are: • Fast interrupt (FIQ) • Normal interrupt (IRQ) • Data and Prefetched aborts (Abort) • Undefined instruction (Undefined) • Software interrupt and Reset (Supervisor) 41 6462A–ATARM–03-Jun-09 When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order: • Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: – ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). – THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the 42 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 11.2.8 ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions • Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 11-2 gives the ARM instruction mnemonic list. Table 11-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte STRH STRB Store Half Word Store Byte Mnemonic MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR Operation Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word 43 6462A–ATARM–03-Jun-09 Table 11-2. Mnemonic LDRBT LDRT LDM SWP MCR LDC CDP ARM Instruction Mnemonic List (Continued) Operation Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Coprocessor Data Processing Mnemonic STRBT STRT STM SWPB MRC STC Operation Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor 11.2.9 New ARM Instruction Set Table 11-3. Mnemonic BXJ BLX (1) SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB New ARM Instruction Mnemonic List Operation Branch and exchange to Java Branch, Link and exchange Signed Multiply Accumulate 16 * 16 bit Signed Multiply Accumulate Long Signed Multiply Accumulate 32 * 16 bit Signed Multiply 16 * 16 bit Signed Multiply 32 * 16 bit Saturated Add Saturated Add with Double Saturated subtract Saturated Subtract with double Mnemonic MRRC MCR2 MCRR CDP2 BKPT PLD STRD STC2 LDRD LDC2 CLZ Operation Move double from coprocessor Alternative move of ARM reg to coprocessor Move double to coprocessor Alternative Coprocessor Data Processing Breakpoint Soft Preload, Memory prepare to load from address Store Double Alternative Store from Coprocessor Load Double Alternative Load to Coprocessor Count Leading Zeroes Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 11.2.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store multiple instructions • Exception-generating instruction 44 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 11-4 gives the Thumb instruction mnemonic list. Table 11-4. Mnemonic MOV ADD SUB CMP TST AND EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch Mnemonic MVN ADC SBC CMN NEG BIC ORR LSR ROR BLX BL SWI STR STRH STRB LDRSB STMIA POP BKPT Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear Logical (inclusive) OR Logical Shift Right Rotate Right Branch, Link, and Exchange Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Breakpoint 45 6462A–ATARM–03-Jun-09 11.3 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S • Caches (ICache, DCache and write buffer) • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 11-5. Table 11-5. Register 0 0 1 2 3 4 5 5 6 7 8 9 10 11 12 13 13 14 15 Notes: CP15 Registers Name ID Code (1) Read/Write Read/Unpredictable Read/Unpredictable Read/write Read/write Read/write None Read/write (1) Cache type(1) Control Translation Table Base Domain Access Control Reserved Data fault Status(1) Instruction fault status Fault Address Cache Operations TLB operations Cache lockdown TLB lockdown Reserved Reserved FCSE PID (1) (1) (2) Read/write Read/write Read/Write Unpredictable/Write Read/write Read/write None None Read/write Read/Write None Read/Write Context ID Reserved Test configuration 1. Register locations 0, 5 and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. 46 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 11.3.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 27 26 25 24 cond 23 22 21 20 1 19 1 18 1 17 0 16 opcode_1 15 14 13 L 12 11 10 CRn 9 8 Rd 7 6 5 4 1 3 1 2 1 1 1 0 opcode_2 1 CRm • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. • opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. • Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. 47 6462A–ATARM–03-Jun-09 11.4 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, Windows CE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 11-6 shows the different attributes of each page in the physical memory. Table 11-6. Mapping Details Mapping Size 1M byte 64K bytes 4K bytes 1K byte Access Permission By Section 4 separated subpages 4 separated subpages Tiny Page Subpage Size 16K bytes 1K byte - Mapping Name Section Large Page Small Page Tiny Page The MMU consists of: • Access control logic • Translation Look-aside Buffer (TLB) • Translation table walk hardware 11.4.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 48 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 11.4.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 11.4.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Pagemapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 11.4.4 MMU Faults The MMU generates an abort on the following types of faults: • Alignment faults (for data accesses only) • Translation faults • Domain faults • Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 49 6462A–ATARM–03-Jun-09 11.5 Caches and Write Buffer The ARM926EJ-S contains a 16 KB Instruction Cache (ICache), a 16 KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 11.5.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 11.5.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA AHB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the 11.5.2.1 50 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 11.5.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and writeback region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 51 6462A–ATARM–03-Jun-09 11.6 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: • It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. • Each AHB layer becomes simple because it only has one master, so no arbitration or masterto-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. • The arbitration becomes effective when more than one master wants to access the same slave simultaneously. 11.6.1 Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 11-7 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 11-7. HBurst[2:0] Supported Transfers Description Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT, or WB that has missed in DCache) SINGLE Single transfer • data read (NCNB or NCB) • NC instruction fetch (prefetched and non-prefetched) • page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. Cache linefill INCR4 INCR8 WRAP8 Four-word incrementing burst Eight-word incrementing burst Eight-word wrapping burst 11.6.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time. Address Alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. 11.6.3 52 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 12. AT91SAM9G10 Debug and Test 12.1 Overview The AT91SAM9G10 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 12.2 Block Diagram Figure 12-1. Debug and Test Block Diagram TMS TCK TDI NTRST Boundary Port ICE/JTAG TAP JTAGSEL TDO RTCK Reset and Test POR TST ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU PIO DTXD DRXD TAP: Test Access Port 53 6462A–ATARM–03-Jun-09 12.3 12.3.1 Application Examples Debug Environment Figure 12-2 on page 54 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 12-2. Application Debug and Trace Environment Example Host Debugger PC ICE/JTAG Interface ICE/JTAG Connector AT91SAM9G10 RS232 Connector Terminal AT91SAM9G10-based Application Board 54 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 12.3.2 Test Environment Figure 12-3 on page 55 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 12-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91SAM9G10 Chip 1 AT91SAM9G10-based Application Board In Test 12.4 Debug and Test Pin Description Table 12-1. Pin Name Debug and Test Pin List Function Reset/Test Type Active Level NRST TST Microcontroller Reset Test Mode Select ICE and JTAG Input/Output Input Low High TCK TDI TDO TMS NTRST RTCK JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select Test Reset Signal Returned Test Clock JTAG Selection Debug Unit Input Input Output Input Input Output Input Low DRXD DTXD Debug Receive Data Debug Transmit Data Input Output 55 6462A–ATARM–03-Jun-09 12.5 12.5.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 12.5.2 Embedded In-circuit Emulator The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the ARM document ARM9EJ-S Technical Reference Manual (DDI 0222A). 12.5.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 56 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 12.5.4 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two Peripheral DMA Controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9G10 Debug Unit Chip ID value is 0x0199 03A0 on 32-bit width. 12.5.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 12.5.5.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associated control signals. Each AT91SAM9G10 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register Pin Name A18 A[22:16] A19 A20 A21 A22 NCS0 A[7:0] NCS1 NCS0/NCS1/NCS2/NCS3 NRD/NWR0/NWR1/NWR3 OUT OUT OUT OUT OUT OUT Pin Type OUT Associated BSR Cells OUTPUT CONTROL OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CONTROL OUTPUT CONTROL Bit Number 483 482 481 480 479 478 477 476 475 474 57 6462A–ATARM–03-Jun-09 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name NCS2 NCS3 NRD NWR0 Pin Type OUT OUT OUT IN/OUT OUTPUT INPUT NWR1 IN/OUT OUTPUT internal NWR3 SDRAMCKE SDRAMCKE/RAS/CAS SDA10/SDWE OUT OUT OUTPUT OUTPUT CONTROL INPUT SDRAMCLK IN/OUT OUTPUT CONTROL RAS CAS SDWE OUT OUT OUT OUTPUT OUTPUT OUTPUT INPUT D0 IN/OUT OUTPUT CONTROL internal INPUT D1 IN/OUT OUTPUT CONTROL INPUT D2 IN/OUT OUTPUT CONTROL INPUT D3 IN/OUT OUTPUT CONTROL INPUT D4 IN/OUT OUTPUT CONTROL internal Associated BSR Cells OUTPUT OUTPUT OUTPUT INPUT Bit Number 473 472 471 470 469 468 467 466 465 464 463 462 461 460 459 458 457 456 455 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 58 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name NCS2 NCS3 NRD NWR0 469 468 NWR1 467 466 465 464 463 462 461 460 459 458 457 456 455 454 453 452 451 450 449 448 447 446 445 444 443 442 441 440 internal D4 IN/OUT D3 IN/OUT D2 IN/OUT D1 IN/OUT internal INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL INPUT OUTPUT CONTROL D0 IN/OUT RAS CAS SDWE OUT OUT OUT SDRAMCLK IN/OUT NWR3 SDRAMCKE SDRAMCKE/RAS/CAS SDA10/SDWE internal OUT OUT OUTPUT OUTPUT CONTROL INPUT OUTPUT CONTROL OUTPUT OUTPUT OUTPUT INPUT OUTPUT CONTROL IN/OUT OUTPUT Pin Type OUT OUT OUT IN/OUT OUTPUT INPUT Associated BSR Cells OUTPUT OUTPUT OUTPUT INPUT Bit Number 473 472 471 470 59 6462A–ATARM–03-Jun-09 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT D5 IN/OUT OUTPUT CONTROL INPUT D6 IN/OUT OUTPUT CONTROL INPUT D7 IN/OUT OUTPUT CONTROL INPUT D8 IN/OUT OUTPUT CONTROL internal INPUT D9 IN/OUT OUTPUT CONTROL INPUT D10 IN/OUT OUTPUT CONTROL INPUT D11 IN/OUT OUTPUT CONTROL INPUT D12 IN/OUT OUTPUT CONTROL internal INPUT D13 IN/OUT OUTPUT CONTROL INPUT D14 IN/OUT OUTPUT CONTROL INPUT D15 IN/OUT OUTPUT CONTROL Bit Number 439 438 437 436 435 434 433 432 431 430 429 428 427 426 425 424 423 422 421 420 419 418 417 416 415 414 413 412 411 410 409 408 407 406 405 60 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PC16 IN/OUT OUTPUT CONTROL internal INPUT PC17 IN/OUT OUTPUT CONTROL internal INPUT PC18 IN/OUT OUTPUT CONTROL internal INPUT PC19 IN/OUT OUTPUT CONTROL internal INPUT PC30 IN/OUT OUTPUT CONTROL internal INPUT PC31 IN/OUT OUTPUT CONTROL internal INPUT PC20 IN/OUT OUTPUT CONTROL internal INPUT PC21 IN/OUT OUTPUT CONTROL internal INPUT PC22 IN/OUT OUTPUT CONTROL internal Bit Number 404 403 402 401 400 399 398 397 396 395 394 393 392 391 390 389 388 387 386 385 384 383 382 381 380 379 378 377 376 375 374 373 372 371 370 369 61 6462A–ATARM–03-Jun-09 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PC23 IN/OUT OUTPUT CONTROL internal INPUT PC24 IN/OUT OUTPUT CONTROL internal INPUT PC25 IN/OUT OUTPUT CONTROL internal INPUT PC26 IN/OUT OUTPUT CONTROL internal INPUT PC27 IN/OUT OUTPUT CONTROL internal INPUT PC28 IN/OUT OUTPUT CONTROL internal INPUT PC29 IN/OUT OUTPUT CONTROL internal INPUT PC0 IN/OUT OUTPUT CONTROL internal INPUT PC1 IN/OUT OUTPUT CONTROL internal Bit Number 368 367 366 365 364 363 362 361 360 359 358 357 356 355 354 353 352 351 350 349 348 347 346 345 344 343 342 341 340 339 338 337 336 335 334 333 62 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PC2 IN/OUT OUTPUT CONTROL internal INPUT PC3 IN/OUT OUTPUT CONTROL internal INPUT PC4 IN/OUT OUTPUT CONTROL internal INPUT PC5 IN/OUT OUTPUT CONTROL internal INPUT PC6 IN/OUT OUTPUT CONTROL internal INPUT PC7 IN/OUT OUTPUT CONTROL internal INPUT PC8 IN/OUT OUTPUT CONTROL internal INPUT PC9 IN/OUT OUTPUT CONTROL internal INPUT PC10 IN/OUT OUTPUT CONTROL internal Bit Number 332 331 330 329 328 327 326 325 324 323 322 321 320 319 318 317 316 315 314 313 312 311 310 309 308 307 306 305 304 303 302 301 300 299 298 297 63 6462A–ATARM–03-Jun-09 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PC11 IN/OUT OUTPUT CONTROL internal INPUT PC12 IN/OUT OUTPUT CONTROL internal INPUT PC13 IN/OUT OUTPUT CONTROL internal INPUT PC14 IN/OUT OUTPUT CONTROL internal INPUT PC15 IN/OUT OUTPUT CONTROL internal INPUT PA0 IN/OUT OUTPUT CONTROL internal INPUT PA1 IN/OUT OUTPUT CONTROL internal INPUT PA2 IN/OUT OUTPUT CONTROL internal INPUT PA3 IN/OUT OUTPUT CONTROL internal Bit Number 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 64 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PA4 IN/OUT OUTPUT CONTROL internal INPUT PA5 IN/OUT OUTPUT CONTROL internal INPUT PA6 IN/OUT OUTPUT CONTROL internal INPUT PA7 IN/OUT OUTPUT CONTROL internal INPUT PA8 IN/OUT OUTPUT CONTROL internal INPUT PA9 IN/OUT OUTPUT CONTROL internal INPUT PA10 IN/OUT OUTPUT CONTROL internal INPUT PA11 IN/OUT OUTPUT CONTROL internal INPUT PA12 IN/OUT OUTPUT CONTROL internal Bit Number 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 65 6462A–ATARM–03-Jun-09 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PA13 IN/OUT OUTPUT CONTROL internal INPUT PA14 IN/OUT OUTPUT CONTROL internal INPUT PA15 IN/OUT OUTPUT CONTROL internal INPUT PA16 IN/OUT OUTPUT CONTROL internal INPUT PA17 IN/OUT OUTPUT CONTROL internal INPUT PA18 IN/OUT OUTPUT CONTROL internal INPUT PA19 IN/OUT OUTPUT CONTROL internal INPUT PA20 IN/OUT OUTPUT CONTROL internal INPUT PA21 IN/OUT OUTPUT CONTROL internal Bit Number 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 66 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PA22 IN/OUT OUTPUT CONTROL internal INPUT PA23 IN/OUT OUTPUT CONTROL internal INPUT PA24 IN/OUT OUTPUT CONTROL internal INPUT PA25 IN/OUT OUTPUT CONTROL internal INPUT PA26 IN/OUT OUTPUT CONTROL internal INPUT PA27 IN/OUT OUTPUT CONTROL internal INPUT PA28 IN/OUT OUTPUT CONTROL internal INPUT PA29 IN/OUT OUTPUT CONTROL internal INPUT PA30 IN/OUT OUTPUT CONTROL internal Bit Number 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 67 6462A–ATARM–03-Jun-09 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PA31 IN/OUT OUTPUT CONTROL internal INPUT PB0 IN/OUT OUTPUT CONTROL internal INPUT PB1 IN/OUT OUTPUT CONTROL internal INPUT PB2 IN/OUT OUTPUT CONTROL internal INPUT PB3 IN/OUT OUTPUT CONTROL internal INPUT PB4 IN/OUT OUTPUT CONTROL internal INPUT PB5 IN/OUT OUTPUT CONTROL internal INPUT PB6 IN/OUT OUTPUT CONTROL internal INPUT PB7 IN/OUT OUTPUT CONTROL internal Bit Number 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 68 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PB8 IN/OUT OUTPUT CONTROL internal INPUT PB9 IN/OUT OUTPUT CONTROL internal INPUT PB10 IN/OUT OUTPUT CONTROL internal INPUT PB11 IN/OUT OUTPUT CONTROL internal INPUT PB12 IN/OUT OUTPUT CONTROL internal INPUT PB13 IN/OUT OUTPUT CONTROL internal INPUT PB14 IN/OUT OUTPUT CONTROL internal INPUT PB15 IN/OUT OUTPUT CONTROL internal INPUT PB16 IN/OUT OUTPUT CONTROL internal Bit Number 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 69 6462A–ATARM–03-Jun-09 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PB17 IN/OUT OUTPUT CONTROL internal INPUT PB18 IN/OUT OUTPUT CONTROL internal INPUT PB19 IN/OUT OUTPUT CONTROL internal INPUT PB20 IN/OUT OUTPUT CONTROL internal INPUT PB21 IN/OUT OUTPUT CONTROL internal INPUT PB22 IN/OUT OUTPUT CONTROL internal INPUT PB23 IN/OUT OUTPUT CONTROL internal INPUT PB24 IN/OUT OUTPUT CONTROL internal INPUT PB25 IN/OUT OUTPUT CONTROL internal Bit Number 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 70 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name Pin Type Associated BSR Cells INPUT PB26 IN/OUT OUTPUT CONTROL internal INPUT PB27 IN/OUT OUTPUT CONTROL internal INPUT PB28 IN/OUT OUTPUT CONTROL internal INPUT PB29 IN/OUT OUTPUT CONTROL internal INPUT PB30 IN/OUT OUTPUT CONTROL internal INPUT PB31 IN/OUT OUTPUT CONTROL internal A0 OUT internal A1 A2 A3 A4 A5 A6 A7 A8 A[15:8] A9 OUT OUT OUT OUT OUT OUT OUT OUT OUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT CONTROL OUTPUT OUTPUT Bit Number 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 71 6462A–ATARM–03-Jun-09 Table 12-2. AT91SAM9G10 JTAG Boundary Scan Register (Continued) Pin Name A10 SDA10 A11 A12 A13 A14 A15 A16 A17 Pin Type OUT OUT OUT OUT OUT OUT OUT OUT OUT Associated BSR Cells OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT Bit Number 08 07 06 05 04 03 02 01 00 12.5.6 ID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B25 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_503F. 72 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 13. AT91SAM9G10 Boot Program 13.1 Overview The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The Boot program tries to detect SPI flash memories. The Serial flash Boot program and DataFlash® B oot program are executed. It looks for a sequence of seven valid ARM exception vectors in a Serial Flash or DataFlash connected to the SPI. All these vectors must be B-branch or LDR load register instructions except for the sixth vector. This vector is used to store the size of the image to download. If a valid sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, NAND Flash Boot program is then executed. The NAND Flash Boot program looks for a sequence of seven valid ARM exception vectors. If such a sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. Then the SD Card Boot program is executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If the SD Card is not formatted or if boot.bin file is not found, TWI Boot program is then executed. The TWI Boot program searches for a valid application in a EEPROM memory. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, SAM-BA Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 73 6462A–ATARM–03-Jun-09 13.2 Flow Diagram The Boot Program implements the algorithm in Figure 13-1. Figure 13-1. Boot Program Algorithm Flow Diagram Device Setup SPI Serial Flash Boot Yes Download from Serial Flash NPCS0 Run Serial Flash Boot No Timeout < 25 ms SPI DataFlash Boot Yes Download from DataFlash NPCS0 Run DataFlash Boot No Timeout < 25 ms Nand Flash Boot Yes Download from Nand Flash Run Nand Flash Boot No Timeout < 50ms SD Card Boot Yes Download from SDCARD Run SD Card Boot No Timeout < 50ms EEPROMBoot Yes Download from EEPROM Run TWI/EEPROM Boot No Timeout 50ms. Character(s) received on DBGU OR USB Enumeration Successful Run SAM-BA Boot SAM-BA Boot Run SAM-BA Boot 74 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 13.3 Device Initialization Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. Main Oscillator Frequency Detection 3. C variable initialization 4. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. Table 13-1 defines the crystals supported by the Boot Program. Table 13-1. 3.0 4.433619 6.0 7.3728 11.05920 14.7456 Crystals Supported by Software Auto-Detection (MHz) 3.2768 4.608 6.144 7.864320 12.0 16.0 3.6864 4.9152 6.4 8.0 12.288 17.734470 3.84 5.0 6.5536 9.8304 13.56 18.432 4.0 5.24288 7.159090 10.0 14.31818 20.0 5. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) 6. Enable the user reset 7. Jump to SerialFlash Boot sequence through NPCS0. If SerialFlash Boot succeeds, perform a remap and jump to 0x0. 8. Jump to DataFlash Boot sequence through NPCS0. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 9. Jump to NAND Flash Boot sequence. If NAND Flash Boot succeeds, perform a remap and jump to 0x0. 10. Jump to SD Card Boot sequence. If SD Card Boot succeeds, perform a remap and jump to 0x0. 11. Jump to EEPROM Boot sequence. If EEPROM Boot succeeds, perform a remap and jump to 0x0. 12. Activation of the Instruction Cache 13. Jump to SAM-BA Boot sequence 14. Disable the WatchDog 15. Initialization of the USB Device Port 75 6462A–ATARM–03-Jun-09 Figure 13-2. Remap Action after Download Completion 0x0000_0000 Internal ROM REMAP 0x0030_0000 Internal SRAM Internal ROM 0x0010_0000 Internal SRAM 0x0000_0000 13.4 Valid Image Detection The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corresponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his own vector (see “Structure of ARM Vector 6” on page 76). 13.4.1 Valid ARM Exception Vectors Figure 13-3. LDR Opcode 31 1 1 1 28 27 0 0 1 I 24 23 P U 0 W 20 19 1 Rn 16 15 Rd 12 11 0 Figure 13-4. B Opcode 31 1 1 1 28 27 0 1 0 1 24 23 0 Offset (24 bits) 0 Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: – Rn = Rd = PC = 0xF – I==0 – P==1 – U offset added (U==1) or subtracted (U==0) – W==1 13.4.2 Structure of ARM Vector 6 The ARM exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below. 76 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 13-5. Structure of the ARM Vector 6 31 Size of the code to download in bytes 0 13.4.2.1 Example An example of valid vectors follows: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 ’. • Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal following by ‘>’ • Send a file (S): Send a file to a specified address – Address: Address in hexadecimal – Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. • Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal – NbOfBytes: Number of bytes in hexadecimal to receive – Output: ‘>’ • Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ 13.10.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of 81 6462A–ATARM–03-Jun-09 the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 13.10.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: – = 01 hex – = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – = 1’s complement of the blk#. – = 2 bytes CRC16 Figure 13-8 shows a transmission using this protocol. Figure 13-8. Xmodem Transfer Example Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device 13.10.3 USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows®, from Windows 98SE to Windows XP®. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. 82 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details. 13.10.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 13-3. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION GET_STATUS SET_FEATURE CLEAR_FEATURE Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature. The device also handles some class requests defined in the CDC class. Table 13-4. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 13.10.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64-byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAMBA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 83 6462A–ATARM–03-Jun-09 13.11 Hardware and Software Constraints • The DataFlash, SerialFlash, NAND Flash, SDCard(1), and EEPROM downloaded code size must be inferior to 12 Kbytes. • The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). • The downloaded code must be position-independent or linked at address 0x0000_0000. • The DataFlash must be connected to NPCS0 of the SPI. Note: 1. Boot ROM does not support high capactiy SDCards. The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between SPI output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 13-5 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 13-5. Peripheral SPI0 SPI0 SPI0 SPI0 PIOC PIOC PIOC Address Bus Address Bus MCI0 MCI0 MCI0 MCI0 MCI0 MCI0 TWI TWI DBGU DBGU Pins Driven during Boot Program Execution Pin MOSI MISO SPCK NPCS0 NANDCS NAND OE NAND WE NAND CLE NAND ALE MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 TWCK TWD DRXD DTXD PIO Line PIOA1 PIOA0 PIOA2 PIOA3 PIOC14 PIOC0 PIOC1 A21 A22 PIOA0 PIOA1 PIOA2 PIOA4 PIOA5 PIOA6 PIOA8 PIOA7 PIOA9 PIOA10 84 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 14. Reset Controller (RSTC) 14.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 14.2 Block Diagram Figure 14-1. Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR Startup Counter rstc_irq Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager exter_nreset periph_nreset backup_neset WDRPROC wd_fault SLCK 14.3 14.3.1 Functional Description Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • backup_nreset: Affects all the peripherals powered by VDDBU. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. 85 6462A–ATARM–03-Jun-09 The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 14.3.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 14-2 shows the block diagram of the NRST Manager. Figure 14-2. NRST Manager RSTC_MR RSTC_SR URSTIEN rstc_irq RSTC_MR URSTS NRSTL Other interrupt sources user_reset URSTEN NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset 14.3.2.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 14.3.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. 86 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 14.3.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 14-3. BMS Sampling SLCK Core Supply POR output XXX BMS sampling delay = 3 cycles BMS Signal H or L proc_nreset 14.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 14.3.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 2 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 5-5 shows how the General Reset affects the reset signals. 87 6462A–ATARM–03-Jun-09 Figure 14-4. General Reset State SLCK MCK Backup Supply POR output Any Freq. Startup Time Main Supply POR output backup_nreset Processor Startup = 2 cycles proc_nreset RSTTYP periph_nreset XXX 0x0 = General Reset XXX NRST (nrst_out) EXTERNAL RESET LENGTH = 2 cycles BMS Sampling 88 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 14.3.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 2 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR. Figure 14-5. Wake-up State SLCK MCK Main Supply POR output Any Freq. backup_nreset Resynch. 2 cycles Processor Startup = 2 cycles proc_nreset RSTTYP XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 14.3.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 2-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. 89 6462A–ATARM–03-Jun-09 When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 14-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 2 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset NRST (nrst_out) >= EXTERNAL RESET LENGTH 14.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. Except for Debug purposes, PERRST must always be used in conjunction with PROCRST (PERRST and PROCRST set both at 1 simultaneously.) • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 2 Slow Clock cycles. 90 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 14-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. Processor Startup 1 cycle = 2 cycles proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) Any XXX 0x3 = Software Reset SRCMP in RSTC_SR 14.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 2 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. 91 6462A–ATARM–03-Jun-09 • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 14-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 2 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 14.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup Reset • Wake-up Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. 92 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 14.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. • NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. • URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 14-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 14-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 93 6462A–ATARM–03-Jun-09 14.4 Reset Controller (RSTC) User Interface Register Mapping Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read-write Reset 0x0000_0001 0x0000_0000 0x0000_0000 Back-up Reset Table 14-1. Offset 0x00 0x04 0x08 Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 94 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 14.4.1 Name: Address: Access Type: 31 Reset Controller Control Register RSTC_CR 0xFFFFFD00 Write-only 30 29 28 KEY 27 26 25 24 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 – 19 – 11 – 3 EXTRST 18 – 10 – 2 PERRST 17 – 9 16 – 8 – 0 PROCRST 1 – • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 95 6462A–ATARM–03-Jun-09 14.4.2 Name: Address: Reset Controller Status Register RSTC_SR 0xFFFFFD04 Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 25 – 17 SRCMP 9 RSTTYP 1 – 24 – 16 NRSTL 8 Access Type: 31 – 23 – 15 – 7 – 2 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Reset Type General Reset Wake Up Reset Watchdog Reset Software Reset User Reset Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 96 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 14.4.3 Name: Address: Access Type: 31 Reset Controller Mode Register RSTC_MR 0xFFFFFD08 Read-write 30 29 28 KEY 27 26 25 24 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 20 – 12 – 4 URSTIEN 19 – 11 18 – 10 ERSTL 17 – 9 16 8 3 – 2 – 1 – 0 URSTEN • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 97 6462A–ATARM–03-Jun-09 98 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 15. Real-time Timer 15.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 15.2 Block Diagram Figure 15-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm 15.3 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 99 6462A–ATARM–03-Jun-09 The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). Figure 15-2. RTT Counting RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 100 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 15.4 Real-time Timer (RTT) User Interface Register Mapping Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read-write Read-write Read-only Read-only Reset 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 Table 15-1. Offset 0x00 0x04 0x08 0x0C 101 6462A–ATARM–03-Jun-09 15.4.1 Real-time Timer Mode Register Register Name: RTT_MR Address: Access Type: 31 – 23 – 15 0xFFFFFD20 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RTPRES 27 – 19 – 11 26 – 18 RTTRST 10 25 – 17 RTTINCIEN 9 24 – 16 ALMIEN 8 7 6 5 4 RTPRES 3 2 1 0 • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216. RTPRES …0: The prescaler period is equal to RTPRES. • ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 102 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 15.4.2 Real-time Timer Alarm Register Register Name: RTT_AR Address: Access Type: 31 0xFFFFFD24 Read/Write 30 29 28 ALMV 27 26 25 24 23 22 21 20 ALMV 19 18 17 16 15 14 13 12 ALMV 11 10 9 8 7 6 5 4 ALMV 3 2 1 0 • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 15.4.3 Real-time Timer Value Register Register Name: RTT_VR Address: Access Type: 31 0xFFFFFD28 Read-only 30 29 28 CRTV 27 26 25 24 23 22 21 20 CRTV 19 18 17 16 15 14 13 12 CRTV 11 10 9 8 7 6 5 4 CRTV 3 2 1 0 • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 103 6462A–ATARM–03-Jun-09 15.4.4 Real-time Timer Status Register Register Name: RTT_SR Address: Access Type: 31 – 23 – 15 – 7 – 0xFFFFFD2C Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 RTTINC 24 – 16 – 8 – 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occured since the last read of RTT_SR. 1 = The Real-time Alarm occured since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 104 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 16. Periodic Interval Timer (PIT) 16.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time . 16.2 Block Diagram Figure 16-1. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset pit_irq 0 0 1 0 1 12-bit Adder read PIT_PIVR MCK 20-bit Counter Prescaler MCK/16 CPIV PIT_PIVR PICNT CPIV PIT_PIIR PICNT 16.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). 105 6462A–ATARM–03-Jun-09 Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 16-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 16-2. Enabling/Disabling PIT with PITEN APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle CPIV PICNT PITS (PIT_SR) APB Interface 0 1 0 PIV - 1 PIV 1 0 0 1 read PIT_PIVR 106 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 16.4 Periodic Interval Timer (PIT) User Interface Register Mapping Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read-write Read-only Read-only Read-only Reset 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 Table 16-1. Offset 0x00 0x04 0x08 0x0C 107 6462A–ATARM–03-Jun-09 16.4.1 Periodic Interval Timer Mode Register Register Name: PIT_MR Address: Access Type: 31 – 23 – 15 0xFFFFFD30 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 PIV 27 – 19 26 – 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16 7 6 5 4 PIV 3 2 1 0 • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 108 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 16.4.2 Periodic Interval Timer Status Register Register Name: PIT_SR Address: Access Type: 31 – 23 – 15 – 7 – 0xFFFFFD34 Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 16.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR Address: Access Type: 31 0xFFFFFD38 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurences of periodic intervals since the last read of PIT_PIVR. 109 6462A–ATARM–03-Jun-09 AT91SAM9G10 16.4.4 Periodic Interval Timer Image Register Register Name: PIT_PIIR Address: Access Type: 31 0xFFFFFD3C Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurences of periodic intervals since the last read of PIT_PIVR. 110 6462A–ATARM–03-Jun-09 AT91SAM9G10 17. Watchdog Timer (WDT) 17.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 17.2 Block Diagram Figure 17-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WDRSTT reload 1 0 WDV 12-bit Down Counter WDT_MR WDD Current Value reload 1/128 SLCK 1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock 28.4.2 28.4.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 28.4.2.2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. 298 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 28-4. Start Bit Detection Sampling Clock DRXD True Start Detection Baud Rate Clock D0 Figure 28-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 28.4.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 28-6. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 28.4.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 28-7. Receiver Overrun DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 28.4.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity 299 6462A–ATARM–03-Jun-09 AT91SAM9G10 bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 28-8. Parity Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 28.4.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 28-9. Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 RSTSTA 28.4.3 28.4.3.1 Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. 28.4.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field 300 6462A–ATARM–03-Jun-09 AT91SAM9G10 PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 28-10. Character Transmission Example: Parity enabled Baud Rate Clock DTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 28.4.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 28-11. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register Data 0 Data 1 DTXD S Data 0 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 28.4.4 Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. 301 6462A–ATARM–03-Jun-09 AT91SAM9G10 The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR. 28.4.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. Figure 28-12. Test Modes Automatic Echo Receiver RXD Transmitter Disabled TXD Local Loopback Receiver Disabled RXD VDD Transmitter Disabled TXD Remote Loopback Receiver VDD Disabled RXD Transmitter Disabled TXD 28.4.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. 302 6462A–ATARM–03-Jun-09 AT91SAM9G10 The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 28.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: • EXT - shows the use of the extension identifier register • NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size • ARCH - identifies the set of embedded peripherals • SRAMSIZ - indicates the size of the embedded SRAM • EPROC - indicates the embedded ARM processor • VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 28.4.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible. 303 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5 Debug Unit (DBGU)User Interface Register Mapping Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Force NTRST Register PDC Area Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR – DBGU_CIDR DBGU_EXID DBGU_FNR – Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write – Read-only Read-only Read-write – Reset – 0x0 – – 0x0 – 0x0 – 0x0 – – – 0x0 – Table 28-3. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 - 0x003C 0x0040 0x0044 0x0048 0x0100 - 0x0124 304 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.1 Name: Address: Access Type: 31 Debug Unit Control Register DBGU_CR 0xFFFFF200 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 0 – 7 TXDIS – 6 TXEN – 5 RXDIS – 4 RXEN – 3 RSTTX – 2 RSTRX – 1 – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. • RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. • RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. • RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. • TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. • TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. • RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 305 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.2 Name: Address: Access Type: 31 Debug Unit Mode Register DBGU_MR 0xFFFFF204 Read-write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CHMODE 7 – 14 – 13 – 12 – 11 – 10 PAR – 9 – 8 – 6 5 – 4 3 – 1 0 2 – – – – – – – – • PAR: Parity Type PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback 306 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.3 Name: Address: Access Type: 31 COMMRX 23 Debug Unit Interrupt Enable Register DBGU_IER 0xFFFFF208 Write-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Enable RXRDY Interrupt • TXRDY: Enable TXRDY Interrupt • ENDRX: Enable End of Receive Transfer Interrupt • ENDTX: Enable End of Transmit Interrupt • OVRE: Enable Overrun Error Interrupt • FRAME: Enable Framing Error Interrupt • PARE: Enable Parity Error Interrupt • TXEMPTY: Enable TXEMPTY Interrupt • TXBUFE: Enable Buffer Empty Interrupt • RXBUFF: Enable Buffer Full Interrupt • COMMTX: Enable COMMTX (from ARM) Interrupt • COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 307 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.4 Name: Address: Access Type: 31 COMMRX 23 Debug Unit Interrupt Disable Register DBGU_IDR 0xFFFFF20C Write-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Disable RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Disable End of Receive Transfer Interrupt • ENDTX: Disable End of Transmit Interrupt • OVRE: Disable Overrun Error Interrupt • FRAME: Disable Framing Error Interrupt • PARE: Disable Parity Error Interrupt • TXEMPTY: Disable TXEMPTY Interrupt • TXBUFE: Disable Buffer Empty Interrupt • RXBUFF: Disable Buffer Full Interrupt • COMMTX: Disable COMMTX (from ARM) Interrupt • COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 308 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.5 Name: Address: Access Type: 31 COMMRX 23 Debug Unit Interrupt Mask Register DBGU_IMR 0xFFFFF210 Read-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Mask RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Mask End of Receive Transfer Interrupt • ENDTX: Mask End of Transmit Interrupt • OVRE: Mask Overrun Error Interrupt • FRAME: Mask Framing Error Interrupt • PARE: Mask Parity Error Interrupt • TXEMPTY: Mask TXEMPTY Interrupt • TXBUFE: Mask TXBUFE Interrupt • RXBUFF: Mask RXBUFF Interrupt • COMMTX: Mask COMMTX Interrupt • COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 309 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.6 Name: Address: Access Type: 31 COMMRX 23 Debug Unit Status Register DBGU_SR 0xFFFFF214 Read-only 30 COMMTX 22 29 28 27 26 25 24 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. • TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. • ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active. • ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. • OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. • PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. 310 6462A–ATARM–03-Jun-09 AT91SAM9G10 • TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active. 311 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.7 Name: Address: Access Type: 31 Debug Unit Receiver Holding Register DBGU_RHR 0xFFFFF218 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 RXCHR – 3 – 2 – 1 – 0 • RXCHR: Received Character Last received character if RXRDY is set. 28.5.8 Name: Address: Debug Unit Transmit Holding Register DBGU_THR 0xFFFFF21C Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 TXCHR – 3 – 2 – 1 – 0 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 312 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.9 Name: Address: Access Type: 31 Debug Unit Baud Rate Generator Register DBGU_BRGR 0xFFFFF220 Read-write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 CD – 11 – 10 – 9 – 8 7 6 5 4 CD 3 2 1 0 • CD: Clock Divisor CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16) 313 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.10 Name: Address: Access Type: 31 EXT 23 22 ARCH 15 14 NVPSIZ2 7 6 EPROC 5 4 3 2 VERSION 13 12 11 10 NVPSIZ 1 0 Debug Unit Chip ID Register DBGU_CIDR 0xFFFFF240 Read-only 30 29 NVPTYP 21 20 19 18 SRAMSIZ 9 8 28 27 26 ARCH 17 16 25 24 • VERSION: Version of the Device Values depend upon the version of the device. • EPROC: Embedded Processor EPROC 0 0 1 1 0 1 0 0 1 0 0 1 Processor ARM946ES ARM7TDMI ARM920T ARM926EJS • NVPSIZ: Nonvolatile Program Memory Size NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes 314 6462A–ATARM–03-Jun-09 AT91SAM9G10 NVPSIZ 1 1 1 1 1 1 0 1 1 1 0 1 Size Reserved 2048K bytes Reserved • NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved • SRAMSIZ: Internal SRAM Size SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes 6K bytes 112K bytes 4K bytes 80K bytes 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 315 6462A–ATARM–03-Jun-09 AT91SAM9G10 SRAMSIZ 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 Size 128K bytes 256K bytes 96K bytes 512K bytes • ARCH: Architecture Identifier ARCH Hex 0x19 0x29 0x34 0x37 0x39 0x3B 0x40 0x42 0x55 0x60 0x61 0x63 0x70 0x71 0x72 0x73 0x75 0x92 0xF0 Bin 0001 1001 0010 1001 0011 0100 0011 0111 0011 1001 0011 1011 0100 0000 0100 0010 0101 0101 0110 0000 0110 0001 0110 0011 0111 0000 0111 0001 0111 0010 0111 0011 0111 0101 1001 0010 1111 0000 Architecture AT91SAM9xx Series AT91SAM9XExx Series AT91x34 Series CAP7 Series CAP9 Series CAP11 Series AT91x40 Series AT91x42 Series AT91x55 Series AT91SAM7Axx Series AT91SAM7AQxx Series AT91x63 Series AT91SAM7Sxx Series AT91SAM7XCxx Series AT91SAM7SExx Series AT91SAM7Lxx Series AT91SAM7Xxx Series AT91x92 Series AT75Cxx Series • NVPTYP: Nonvolatile Program Memory Type NVPTYP 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 Memory ROM ROMless or on-chip Flash SRAM emulating ROM Embedded Flash Memory ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size 316 6462A–ATARM–03-Jun-09 AT91SAM9G10 • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists. 317 6462A–ATARM–03-Jun-09 AT91SAM9G10 28.5.11 Name: Address: Access Type: 31 Debug Unit Chip ID Extension Register DBGU_EXID 0xFFFFF244 Read-only 30 29 28 EXID 27 26 25 24 23 22 21 20 EXID 19 18 17 16 15 14 13 12 EXID 11 10 9 8 7 6 5 4 EXID 3 2 1 0 • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 28.5.12 Name: Address: Debug Unit Force NTRST Register DBGU_FNR 0xFFFFF248 Read-write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FNTRST – – – – – – – • FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low. 318 6462A–ATARM–03-Jun-09 AT91SAM9G10 29. Parallel Input/Output Controller (PIO) 29.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: • An input change interrupt enabling level change detection on any I/O line. • A glitch filter providing rejection of pulses lower than one-half of clock cycle. • Multi-drive capability similar to an open drain I/O line. • Control of the the pull-up of the I/O line. • Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 319 6462A–ATARM–03-Jun-09 29.2 Block Diagram Figure 29-1. Block Diagram PIO Controller AIC PIO Interrupt PMC PIO Clock Data, Enable Embedded Peripheral Up to 32 peripheral IOs PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 29-2. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver General Purpose I/Os External Devices 320 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.3 29.3.1 Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. 29.3.2 29.3.3 29.3.4 Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled. 321 6462A–ATARM–03-Jun-09 29.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 29-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 29-3. I/O Line Control Logic PIO_OER[0] PIO_OSR[0] PIO_ODR[0] 1 PIO_PUER[0] PIO_PUSR[0] PIO_PUDR[0] Peripheral A Output Enable Peripheral B Output Enable PIO_ASR[0] PIO_ABSR[0] PIO_BSR[0] Peripheral A Output Peripheral B Output 0 0 0 1 PIO_PER[0] PIO_PSR[0] PIO_PDR[0] 0 0 1 PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 0 1 1 PIO_SODR[0] PIO_ODSR[0] PIO_CODR[0] Pad 1 Peripheral A Input Peripheral B Input PIO_PDSR[0] 0 Edge Detector Glitch Filter PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] 1 PIO_ISR[0] (Up to 32 possible inputs) PIO Interrupt PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] 322 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pullup Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. 29.4.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. 29.4.3 Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. 29.4.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). 323 6462A–ATARM–03-Jun-09 The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 29.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 29.4.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 29.4.7 Output Line Timings Figure 29-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 29-4 also shows when the feedback in PIO_PDSR is available. 324 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 29-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0 APB Access APB Access PIO_ODSR 2 cycles PIO_PDSR 2 cycles 29.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 29.4.9 Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 29-5. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled. 325 6462A–ATARM–03-Jun-09 Figure 29-5. Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 up to 2.5 cycles 1 cycle up to 2 cycles 1 cycle 1 cycle 1 cycle 29.4.10 Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. Figure 29-6. Input Change Interrupt Timings MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 326 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.5 I/O Lines Programming Example The programing example as shown in Table 29-1 below is used to define the following configuration. • 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor • Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor • Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts • Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter • I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor • I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor • I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 29-1. Programming Example Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0 327 6462A–ATARM–03-Jun-09 29.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 29-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C Register Mapping Register PIO Enable Register PIO Disable Register PIO Status Register Reserved Output Enable Register Output Disable Register Output Status Register Reserved Glitch Input Filter Enable Register Glitch Input Filter Disable Register Glitch Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register Pin Data Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register(4) Multi-driver Enable Register Multi-driver Disable Register Multi-driver Status Register Reserved Pull-up Disable Register Pull-up Enable Register Pad Pull-up Status Register Reserved PIO_PUDR PIO_PUER PIO_PUSR Write-only Write-only Read-only – – 0x00000000 PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR Write-only Write-only Read-only or(2) Read/Write Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only – (3) Name PIO_PER PIO_PDR PIO_PSR Access Write-only Write-only Read-only Reset – – (1) PIO_OER PIO_ODR PIO_OSR Write-only Write-only Read-only – – 0x0000 0000 PIO_IFER PIO_IFDR PIO_IFSR Write-only Write-only Read-only – – 0x0000 0000 – – – 0x00000000 0x00000000 – – 0x00000000 328 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 29-2. Offset 0x0070 0x0074 0x0078 0x007C to 0x009C 0x00A0 0x00A4 0x00A8 0x00AC Notes: Register Mapping (Continued) Register Peripheral A Select Register Peripheral B Select Register AB Status Register Reserved Output Write Enable Output Write Disable Output Write Status Register Reserved PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only – – 0x00000000 (5) (5) (5) Name PIO_ASR PIO_BSR PIO_ABSR Access Write-only Write-only Read-only Reset – – 0x00000000 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register. 329 6462A–ATARM–03-Jun-09 29.6.1 Name: PIO Controller PIO Enable Register PIO_PER 0xFFFFF400 (PIOA), 0xFFFFF600 (PIOB), 0xFFFFF800 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 29.6.2 Name: PIO Controller PIO Disable Register PIO_PDR 0xFFFFF404 (PIOA), 0xFFFFF604 (PIOB), 0xFFFFF804 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 330 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.3 Name: PIO Controller PIO Status Register PIO_PSR 0xFFFFF408 (PIOA), 0xFFFFF608 (PIOB), 0xFFFFF808 (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive). 29.6.4 Name: PIO Controller Output Enable Register PIO_OER 0xFFFFF410 (PIOA), 0xFFFFF610 (PIOB), 0xFFFFF810 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line. 331 6462A–ATARM–03-Jun-09 29.6.5 Name: PIO Controller Output Disable Register PIO_ODR 0xFFFFF414 (PIOA), 0xFFFFF614 (PIOB), 0xFFFFF814 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. 29.6.6 Name: PIO Controller Output Status Register PIO_OSR 0xFFFFF418 (PIOA), 0xFFFFF618 (PIOB), 0xFFFFF818 (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output. 332 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.7 Name: PIO Controller Input Filter Enable Register PIO_IFER 0xFFFFF420 (PIOA), 0xFFFFF620 (PIOB), 0xFFFFF820 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 29.6.8 Name: PIO Controller Input Filter Disable Register PIO_IFDR 0xFFFFF424 (PIOA), 0xFFFFF624 (PIOB), 0xFFFFF824 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line. 333 6462A–ATARM–03-Jun-09 29.6.9 Name: PIO Controller Input Filter Status Register PIO_IFSR 0xFFFFF428 (PIOA), 0xFFFFF628 (PIOB), 0xFFFFF828 (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 29.6.10 Name: PIO Controller Set Output Data Register PIO_SODR 0xFFFFF430 (PIOA), 0xFFFFF630 (PIOB), 0xFFFFF830 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line. 334 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.11 Name: PIO Controller Clear Output Data Register PIO_CODR 0xFFFFF434 (PIOA), 0xFFFFF634 (PIOB), 0xFFFFF834 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 29.6.12 Name: PIO Controller Output Data Status Register PIO_ODSR 0xFFFFF438 (PIOA), 0xFFFFF638 (PIOB), 0xFFFFF838 (PIOC) Read-only or Read/Write 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1. 335 6462A–ATARM–03-Jun-09 29.6.13 Name: PIO Controller Pin Data Status Register PIO_PDSR 0xFFFFF43C (PIOA), 0xFFFFF63C (PIOB), 0xFFFFF83C (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 29.6.14 Name: PIO Controller Interrupt Enable Register PIO_IER 0xFFFFF440 (PIOA), 0xFFFFF640 (PIOB), 0xFFFFF840 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line. 336 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.15 Name: PIO Controller Interrupt Disable Register PIO_IDR 0xFFFFF444 (PIOA), 0xFFFFF644 (PIOB), 0xFFFFF844 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 29.6.16 Name: PIO Controller Interrupt Mask Register PIO_IMR 0xFFFFF448 (PIOA), 0xFFFFF648 (PIOB), 0xFFFFF848 (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line. 337 6462A–ATARM–03-Jun-09 29.6.17 Name: PIO Controller Interrupt Status Register PIO_ISR 0xFFFFF44C (PIOA), 0xFFFFF64C (PIOB), 0xFFFFF84C (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 29.6.18 Name: PIO Multi-driver Enable Register PIO_MDER 0xFFFFF450 (PIOA), 0xFFFFF650 (PIOB), 0xFFFFF850 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line. 338 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.19 Name: PIO Multi-driver Disable Register PIO_MDDR 0xFFFFF454 (PIOA), 0xFFFFF654 (PIOB), 0xFFFFF854 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line. 29.6.20 Name: PIO Multi-driver Status Register PIO_MDSR 0xFFFFF458 (PIOA), 0xFFFFF658 (PIOB), 0xFFFFF858 (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 339 6462A–ATARM–03-Jun-09 29.6.21 Name: PIO Pull Up Disable Register PIO_PUDR 0xFFFFF460 (PIOA), 0xFFFFF660 (PIOB), 0xFFFFF860 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 29.6.22 Name: PIO Pull Up Enable Register PIO_PUER 0xFFFFF464 (PIOA), 0xFFFFF664 (PIOB), 0xFFFFF864 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line. 340 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.23 Name: PIO Pull Up Status Register PIO_PUSR 0xFFFFF468 (PIOA), 0xFFFFF668 (PIOB), 0xFFFFF868 (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 29.6.24 Name: PIO Peripheral A Select Register PIO_ASR 0xFFFFF470 (PIOA), 0xFFFFF670 (PIOB), 0xFFFFF870 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function. 341 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.25 Name: PIO Peripheral B Select Register PIO_BSR 0xFFFFF474 (PIOA), 0xFFFFF674 (PIOB), 0xFFFFF874 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. 29.6.26 Name: PIO Peripheral A B Status Register PIO_ABSR 0xFFFFF478 (PIOA), 0xFFFFF678 (PIOB), 0xFFFFF878 (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B. 342 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.27 Name: PIO Output Write Enable Register PIO_OWER 0xFFFFF4A0 (PIOA), 0xFFFFF6A0 (PIOB), 0xFFFFF8A0 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 29.6.28 Name: PIO Output Write Disable Register PIO_OWDR 0xFFFFF4A4 (PIOA), 0xFFFFF6A4 (PIOB), 0xFFFFF8A4 (PIOC) Write-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line. 343 6462A–ATARM–03-Jun-09 AT91SAM9G10 29.6.29 Name: PIO Output Write Status Register PIO_OWSR 0xFFFFF4A8 (PIOA), 0xFFFFF6A8 (PIOB), 0xFFFFF8A8 (PIOC) Read-only 30 29 28 27 26 25 24 Addresses: Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line. 344 6462A–ATARM–03-Jun-09 AT91SAM9G10 30. Serial Peripheral Interface (SPI) 30.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. • Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. • Slave Select (NSS): This control line allows slaves to be turned on and off by hardware. 345 6462A–ATARM–03-Jun-09 30.2 Block Diagram Figure 30-1. Block Diagram PDC APB SPCK MISO MCK SPI Interface PIO MOSI NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 PMC SPI Interrupt 30.3 Application Block Diagram Figure 30-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 346 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.4 Signal Description Signal Description Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input Table 30-1. 30.5 30.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. Table 30-2. I/O Lines Signal SPI0_MISO SPI0_MOSI SPI0_NPCS0 SPI0_NPCS1 SPI0_NPCS1 SPI0_NPCS2 SPI0_NPCS2 SPI0_NPCS3 SPI0_NPCS3 SPI0_SPCK SPI1_MISO SPI1_MOSI SPI1_NPCS0 SPI1_NPCS1 SPI1_NPCS1 SPI1_NPCS2 SPI1_NPCS2 SPI1_NPCS3 SPI1_NPCS3 SPI1_SPCK I/O Line PA0 PA1 PA3 PA4 PA27 PA5 PA28 PA6 PA29 PA2 PB30 PB31 PB28 PA24 PB27 PA25 PC14 PA26 PC15 PB29 Peripheral A A A A B A B A B A A A A B A B B B B A Instance SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI0 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 SPI1 347 6462A–ATARM–03-Jun-09 30.5.2 Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).Handling the SPI interrupt requires programming the AICbefore configuring the SPI. Table 30-3. Instance SPI0 SPI1 30.5.3 Peripheral IDs ID 12 13 30.6 30.6.1 Functional Description Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode. 30.6.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. 348 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 30-4 shows the four modes and corresponding parameter settings. Table 30-4. SPI Bus Protocol Mode CPOL 0 0 1 1 NCPHA 1 0 1 0 Shift SPCK Edge Falling Rising Rising Falling Capture SPCK Edge Rising Falling Falling Rising SPCK Inactive Level Low Low High High SPI Mode 0 1 2 3 Figure 30-3 and Figure 30-4 show examples of data transfers. Figure 30-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. 349 6462A–ATARM–03-Jun-09 Figure 30-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) * MSB 6 5 4 3 2 1 LSB NSS (to slave) * Not defined but normally LSB of previous character transmitted. 30.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Receiving data cannot occur without transmitting data. If receiving mode is not needed, for example when communicating with a slave receiver only (such as an LCD), the receive status flags in the status register can be discarded. Before writing the TDR, the PCS field in the SPI_MR register must be set in order to select a slave. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. 350 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 30-5, shows a block diagram of the SPI when operating in Master Mode. Figure 30-6 on page 353 shows a flow chart describing how transfers are handled. 351 6462A–ATARM–03-Jun-09 30.6.3.1 Master Mode Block Diagram Figure 30-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL MISO LSB SPI_RDR RD RDRF OVRES Shift Register MSB MOSI SPI_TDR TD SPI_CSR0..3 SPI_RDR CSAAT PS SPI_MR PCS 0 SPI_TDR PCS 1 NPCS0 PCSDEC Current Peripheral PCS NPCS3 NPCS2 NPCS1 TDRE MSTR NPCS0 MODFDIS MODF 352 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.6.3.2 Master Mode Flow Diagram Figure 30-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ? 0 1 CSAAT ? PS ? Variable peripheral yes 0 Fixed peripheral 0 0 PS ? Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral 1 SPI_TDR(PCS) = NPCS ? no NPCS = 0xF SPI_MR(PCS) = NPCS ? no NPCS = 0xF 1 NPCS = SPI_TDR(PCS) Delay DLYBCS Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS), SPI_TDR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT 0 TDRE ? 1 1 CSAAT ? 0 NPCS = 0xF Delay DLYBCS 353 6462A–ATARM–03-Jun-09 Figure 30-7 shows Transmit Data Register Empty (TDRE), Receive Data Register (RDRF) and Transmission Register Empty (TXEMPTY) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode and no Peripheral Data Controller involved. Figure 30-7. Status Register Flags Behavior 1 SPCK NPCS0 MOSI (from master) TDRE RDR read Write in SPI_TDR RDRF MISO (from slave) TXEMPTY MSB 6 5 4 3 2 1 LSB 2 3 4 5 6 7 8 MSB 6 5 4 3 2 1 LSB shift register empty Figure 30-8 shows Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags behavior within the SPI_SR (Status Register) during an 8-bit data transfer in fixed mode with the Peripheral Data Controller involved. The PDC is programmed to transfer and receive three data. The next pointer and counter are not used. The RDRF and TDRE are not shown because these flags are managed by the PDC when using the PDC. 354 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 30-8. PDC Status Register Flags Behavior 1 SPCK NPCS0 MOSI (from master) MISO (from slave) ENDTX ENDRX TXBUFE RXBUFF TXEMPTY 2 3 MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB MSB 6 5 4 3 2 1 LSB 30.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 30.6.3.4 Transfer Delays Figure 30-9 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: • The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. • The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. • The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select 355 6462A–ATARM–03-Jun-09 These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 30-9. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 30.6.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. • Fixed Peripheral Select: SPI exchanges data with only one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect. • Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to reprogram the NPCS field in the SPI_MR register. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR register as the following format. [xxxxxxx(7-bit) + LASTXFER(1-bit)(1)+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip select to assert as defined in Section 30.7.4 (SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending on CSAAT bit. CSAAT, LASTXFER and CSNAAT bit are discussed in the Peripheral Deselection in Section 30.6.3.10. Note: 1. Optional. 30.6.3.6 SPI Peripheral DMA Controller (PDC) In both fixed and variable mode the Peripheral DMA Controller (PDC) can be used to reduce processor overhead. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, how- 356 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 ever the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 30.6.3.7 Transfer Size Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer's size it has to point to. The PDC will perform the following transfer size depending on the mode and number of bits per data. Fixed Mode: • 8-bit Data: Byte transfer, PDC Pointer Address = Address + 1 byte, PDC Counter = Counter - 1 • 8-bit to 16-bit Data: 2 bytes transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s, PDC Pointer Address = Address + 2 bytes, PDC Counter = Counter - 1 Variable Mode: In variable Mode, PDC Pointer Address = Address +4 bytes and PDC Counter = Counter - 1 for 8 to 16-bit transfer size. When using the PDC, the TDRE and RDRF flags are handled by the PDC, thus the user’s application does not have to check those bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer Full (RXBUFF), TX Buffer Empty (TXBUFE) are significant. For further details about the Peripheral DMA Controller and user interface, refer to the PDC section of the product datasheet. 30.6.3.8 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with 1 of up to 16 decoder/demultiplexer. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e., one NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field on NPCS lines of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. Figure 30-10 below shows such an implementation. 357 6462A–ATARM–03-Jun-09 If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This is not needed for all other chip select lines since Mode Fault Detection is only on NPCS0. Figure 30-10. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPCK MISO MOSI Slave 0 SPI Master NSS NPCS0 NPCS1 NPCS2 NPCS3 SPCK MISO MOSI Slave 1 NSS SPCK MISO MOSI Slave 14 NSS 1-of-n Decoder/Demultiplexer 30.6.3.9 Peripheral Deselection without PDC During a transfer of more than one data on a Chip Select without the PDC, the SPI_TDR is loaded by the processor, the flag TDRE rises as soon as the content of the SPI_TDR is transferred into the internal shift register. When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the Chip Select is not de-asserted between the two transfers. But depending on the application software handling the SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor may not reload the SPI_TDR in time to keep the chip select active (low). A null Delay Between Consecutive Transfer (DLYBCT) value in the SPI_CSR register, will give even less time for the processor to reload the SPI_TDR. With some SPI slave peripherals, requiring the chip select line to remain active (low) during a full set of transfers might lead to communication errors. To facilitate interfacing with such devices, the Chip Select Register [CSR0...CSR3] can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another chip select is required. Even if the SPI_TDR is not reloaded the chip select will remain active. To have the chip select line to raise at the end of the transfer the Last transfer Bit (LASTXFER) in the SPI_MR register must be set at 1 before writing the last data to transmit into the SPI_TDR. 358 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.6.3.10 Peripheral Deselection with PDC When the Peripheral DMA Controller is used, the chip select line will remain low during the whole transfer since the TDRE flag is managed by the PDC itself. The reloading of the SPI_TDR by the PDC is done as soon as TDRE flag is set to one. In this case the use of CSAAT bit might not be needed. However, it may happen that when other PDC channels connected to other peripherals are in use as well, the SPI PDC might be delayed by another (PDC with a higher priority on the bus). Having PDC buffers in slower memories like flash memory or SDRAM compared to fast internal SRAM, may lengthen the reload time of the SPI_TDR by the PDC as well. This means that the SPI_TDR might not be reloaded in time to keep the chip select line low. In this case the chip select line may toggle between data transfer and according to some SPI Slave devices, the communication might get lost. The use of the CSAAT bit might be needed. Figure 30-11 shows different peripheral deselction cases and the effect of the CSAAT bit. Figure 30-11. Peripheral Deselection CSAAT = 0 CSAAT = 1 TDRE DLYBCT A DLYBCS PCS = A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE DLYBCT A DLYBCS PCS=A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] DLYBCT A DLYBCS PCS = B B A DLYBCT B DLYBCS PCS = B Write SPI_TDR 30.6.3.11 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. In this case, multi-master configuration, NPCS0, MOSI, MISO and SPCK pins must be configured in open drain (through the PIO control359 6462A–ATARM–03-Jun-09 ler). When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). 30.6.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. (For more information on BITS field, see also, the “SPI Chip Select Register” on page 373.) (Note:) below the register table; Section 30.7.9 When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 30-12 shows a block diagram of the SPI when operating in Slave Mode. 360 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 30-12. Slave Mode Functional Bloc Diagram SPCK NSS SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RD RDRF OVRES SPI Clock Shift Register MSB MISO SPI_TDR TD TDRE 361 6462A–ATARM–03-Jun-09 30.7 Serial Peripheral Interface (SPI) User Interface Register Mapping Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 – – Read-write Read-write Read-write Read-write – – 0x0 0x0 0x0 0x0 – – Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read-write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0 Table 30-5. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x004C - 0x00F8 0x100 - 0x124 362 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.7.1 Name: SPI Control Register SPI_CR 0xFFFC8000 (0), 0xFFFCC000 (1) Write-only 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 LASTXFER 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. • SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. PDC channels are not affected by software reset. • LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 30.7.2 Name: SPI Mode Register SPI_MR 0xFFFC8004 (0), 0xFFFCC004 (1) Addresses: 363 6462A–ATARM–03-Jun-09 Access: 31 Read/Write 30 29 28 27 26 25 24 DLYBCS 23 22 21 20 19 18 17 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 LLB – – MODFDIS – PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. • PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14. • MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. • LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0 NPCS[3:0] = 1110 364 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay: Delay Between Chip Selects = D LYBCS ---------------------MCK NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 365 6462A–ATARM–03-Jun-09 30.7.3 Name: SPI Receive Data Register SPI_RDR 0xFFFC8008 (0), 0xFFFCC008 (1) Read-only 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 RD 7 6 5 4 3 2 1 0 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. 366 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.7.4 Name: SPI Transmit Data Register SPI_TDR 0xFFFC800C (0), 0xFFFCC00C (1) Write-only 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 LASTXFER 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 TD 7 6 5 4 3 2 1 0 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. • PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS • LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1). NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 367 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.7.5 Name: SPI Status Register SPI_SR 0xFFFC8010 (0), 0xFFFCC010 (1) Read-only 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 SPIENS 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. • TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. • MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. • OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. • ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). • ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). • RXBUFF: RX Buffer Full 0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0. 368 6462A–ATARM–03-Jun-09 AT91SAM9G10 • TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC. 369 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.7.6 Name: SPI Interrupt Enable Register SPI_IER 0xFFFC8014 (0), 0xFFFCC014 (1) Write-only 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = No effect. 1 = Enables the corresponding interrupt. • RDRF: Receive Data Register Full Interrupt Enable • TDRE: SPI Transmit Data Register Empty Interrupt Enable • MODF: Mode Fault Error Interrupt Enable • OVRES: Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable • NSSR: NSS Rising Interrupt Enable • TXEMPTY: Transmission Registers Empty Enable 370 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.7.7 Name: SPI Interrupt Disable Register SPI_IDR 0xFFFC8018 (0), 0xFFFCC018 (1) Write-only 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = No effect. 1 = Disables the corresponding interrupt. • RDRF: Receive Data Register Full Interrupt Disable • TDRE: SPI Transmit Data Register Empty Interrupt Disable • MODF: Mode Fault Error Interrupt Disable • OVRES: Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable • NSSR: NSS Rising Interrupt Disable • TXEMPTY: Transmission Registers Empty Disable 371 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.7.8 Name: SPI Interrupt Mask Register SPI_IMR 0xFFFC801C (0), 0xFFFCC01C (1) Read-only 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. • RDRF: Receive Data Register Full Interrupt Mask • TDRE: SPI Transmit Data Register Empty Interrupt Mask • MODF: Mode Fault Error Interrupt Mask • OVRES: Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask • NSSR: NSS Rising Interrupt Mask • TXEMPTY: Transmission Registers Empty Mask 372 6462A–ATARM–03-Jun-09 AT91SAM9G10 30.7.9 Name: SPI Chip Select Register SPI_CSR0... SPI_CSR3 0xFFFC8030 (0), 0xFFFCC030 (1) Read/Write 30 29 28 27 26 25 24 Addresses: Access: 31 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 7 6 5 4 3 2 1 0 BITS Note: CSAAT – NCPHA CPOL SPI_CSRx registers must be written even if the user wants to use the defaults. The BITS field will not be updated with the translated value unless the register is written. • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. • NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. • BITS: Bits Per Transfer (See the (Note:) below the register table; Section 30.7.9 “SPI Chip Select Register” on page 373.) The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 Bits Per Transfer 8 9 10 11 12 13 14 15 373 6462A–ATARM–03-Jun-09 AT91SAM9G10 BITS 1000 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer 16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = -------------SCBR Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBS Delay Before SPCK = -----------------MCK • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: 32 × DLYBCT Delay Between Consecutive Transfers = -----------------------------------MCK 374 6462A–ATARM–03-Jun-09 AT91SAM9G10 31. Two-wire Interface (TWI) 31.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. 20 Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Below, Table 31-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I2C compatible device. Table 31-1. I2C Standard Standard Mode Speed (100 KHz) Fast Mode Speed (400 KHz) 7 or 10 bits Slave Addressing START BYTE (1) Atmel TWI compatibility with i2C Standard Atmel TWI Supported Supported Supported Not Supported Supported Supported Not Supported Supported Supported Repeated Start (Sr) Condition ACK and NACK Management Slope control and input filtering (Fast mode) Clock stretching Multi Master Capability Note: 1. START + b000000001 + Ack + Sr 31.2 List of Abbreviations Table 31-2. Abbreviation TWI A NA P S Sr SADR Abbreviations Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start Slave Address 375 6462A–ATARM–03-Jun-09 Table 31-2. Abbreviation ADR R W Abbreviations (Continued) Description Any address except SADR Read Write 31.3 Block Diagram Figure 31-1. Block Diagram APB Bridge TWCK PIO Two-wire Interface TWD PMC MCK TWI Interrupt AIC 31.4 Application Block Diagram Figure 31-2. Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 I²C RTC Slave 2 I²C LCD Controller Slave 3 I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard 376 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.4.1 I/O Lines Description I/O Lines Description Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output Table 31-3. Pin Name TWD TWCK 31.5 31.5.1 Product Dependencies I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 31-2 on page 376). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following step: • Program the PIO controller to dedicate TWD and TWCK as peripheral lines. The user must not program TWD and TWCK as open-drain. It is already done by the hardware. Table 31-4. I/O Lines Signal TWCK TWD I/O Line PA8 PA7 Peripheral A A Instance TWI TWI 31.5.2 Power Management • Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 31.5.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. Table 31-5. Instance TWI Peripheral IDs ID 11 31.6 31.6.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 31-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 31-3). 377 AT91SAM9G10 6462A–ATARM–03-Jun-09 • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 31-3. START and STOP Conditions TWD TWCK Start Stop Figure 31-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 31.6.2 Modes of Operation The TWI has six modes of operations: • Master transmitter mode • Master receiver mode • Multi-master transmitter mode • Multi-master receiver mode • Slave transmitter mode • Slave receiver mode These modes are described in the following chapters. 378 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.7 31.7.1 Master Mode Definition The Master is the device that starts a transfer, generates a clock and stops it. 31.7.2 Application Block Diagram Figure 31-5. Master Mode Typical Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 I²C RTC Slave 2 I²C LCD Controller Slave 3 I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard 31.7.3 Programming Master Mode The following registers have to be programmed before entering Master mode: 1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode. 2. CKDIV + CHDIV + CLDIV: Clock Waveform. 3. SVDIS: Disable the slave mode. 4. MSEN: Enable the master mode. 31.7.4 Master Transmitter Mode After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR. While no new data is written in the TWI_THR, the Serial Clock Line is tied low. When new data is written in the TWI_THR, the SCL is released and the data is sent. To generate a STOP event, the STOP command must be performed by writing in the STOP field of TWI_CR. 379 AT91SAM9G10 6462A–ATARM–03-Jun-09 After a Master Write transfer, the Serial Clock line is stretched (tied low) while no new data is written in the TWI_THR or until a STOP command is performed. See Figure 31-6, Figure 31-7, and Figure 31-8. Figure 31-6. Master Write with One Data Byte STOP Command sent (write in TWI_CR) TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) Figure 31-7. Master Write with Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 380 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-8. Master Write with One Byte Internal Address and Multiple Data Bytes STOP command performed (by writing in the TWI_CR) TWD S DADR W A IADR A DATA n A DATA n+1 A DATA n+2 A P TWCK TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+2) Last data sent 31.7.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after the stop condition. See Figure 31-9. When the RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 31-9. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-tolast data received. See Figure 31-10. For Internal Address usage see Section 31.7.6. Figure 31-9. Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR 381 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read 31.7.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 31-12. See Figure 31-11 and Figure 31-13 for Master Write operation with internal address. The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0. In the figures below the following abbreviations are used: •S • Sr •P •W •R •A •N • DADR • IADR Start Repeated Start Stop Write Read Acknowledge Not Acknowledge Device Address Internal Address 31.7.6.1 382 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A DATA A P One byte internal address TWD S DADR W A IADR(7:0) A DATA A P Figure 31-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A Sr DADR R A DATA N P N P One byte internal address TWD S DADR W A IADR(7:0) A Sr DADR R A DATA N P 31.7.6.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) 3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 31-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 31-13. Internal Address Usage S T A R T W R I T E S T O P Device Address 0 M S B FIRST WORD ADDRESS SECOND WORD ADDRESS DATA LRA S/C BW K M S B A C K LA SC BK A C K 383 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.7.7 SMBUS Quick Command (Master Mode Only) The TWI interface can perform a Quick Command: 1. Configure the master mode (DADR, CKDIV, etc.). 2. Write the MREAD bit in the TWI_MMR register at the value of the one-bit command to be sent. 3. Start the transfer by setting the QUICK bit in the TWI_CR. Figure 31-14. SMBUS Quick Command TWD S DADR R/W A P TXCOMP TXRDY Write QUICK command in TWI_CR 31.7.8 Read-write Flowcharts The following flowcharts shown in Figure 31-16 on page 386, Figure 31-17 on page 387, Figure 31-18 on page 388, Figure 31-19 on page 389 and Figure 31-20 on page 390 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. 384 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-15. TWI Write Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Write STOP Command TWI_CR = STOP Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished 385 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-16. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Write STOP command TWI_CR = STOP Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished 386 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-17. TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Read Status register TWI_THR = data to send TXRDY = 1? Yes Data to send? Yes No Write STOP Command TWI_CR = STOP Read Status register Yes No TXCOMP = 1? END 387 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-18. TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? Yes Read Receive Holding Register No Read Status register No TXCOMP = 1? Yes END 388 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-19. TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END 389 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-20. TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) No No Last data to read but one? Yes Stop the transfer TWI_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) Read status register TXCOMP = 1? Yes END No 390 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.8 31.8.1 Multi-master Mode Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 31-22 on page 392. 31.8.2 Different Multi-master Modes Two multi-master modes may be distinguished: 1. TWI is considered as a Master only and will never be addressed. 2. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported. 31.8.2.1 TWI as Master Only In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 3121 on page 392). Note: The state of the bus (busy or free) is not indicated in the user interface. 31.8.2.2 TWI as Master or Slave The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below. 1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed). 2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. 391 AT91SAM9G10 6462A–ATARM–03-Jun-09 Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR. Figure 31-21. Programmer Sends Data While the Bus is Busy TWCK STOP sent by the master TWD DATA sent by a master Bus is busy Bus is free TWI DATA transfer Transfer is kept START sent by the TWI DATA sent by the TWI A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 31-22. Arbitration Cases TWCK TWD TWCK Data from a Master Data from TWI TWD S S S 1 1 1 0 0 11 0 1 Arbitration is lost TWI stops sending data P S S 1 1 1 0 1 Arbitration is lost The master stops sending data 0 01 0 01 1 1 Data from the TWI 00 11 Data from the master P S ARBLST Bus is busy Bus is free TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Transfer is stopped Transfer is kept Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 31-23 on page 393 gives an example of read and write operations in Multi-master mode. 392 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-23. Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? No No EOSACC = 1 ? Yes No TXCOMP = 1 ? Yes No Yes GACC = 1 ? No No No SVREAD = 0 ? Yes TXRDY= 1 ? Yes Write in TWI_THR RXRDY= 0 ? Yes Read TWI_RHR No Need to perform a master access ? GENERAL CALL TREATMENT Yes Decoding of the programming sequence Prog seq OK ? Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W No Read Status Register Yes ARBLST = 1 ? No Yes Yes RXRDY= 0 ? No Read TWI_RHR Yes Data to read? No MREAD = 1 ? No TXRDY= 0 ? No Data to send ? No Yes Write in TWI_THR Yes Stop Transfer TWI_CR = STOP Read Status Register Yes No TXCOMP = 0 ? 393 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.9 31.9.1 Slave Mode Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 31.9.2 Application Block Diagram Figure 31-24. Slave Mode Typical Application Block Diagram VDD R TWD TWCK R Master Host with TWI Interface Host with TWI Interface Slave 1 Host with TWI Interface Slave 2 LCD Controller Slave 3 31.9.3 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode. 2. MSDIS (TWI_CR): Disable the master mode. 3. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account. 31.9.4 Receiving Data After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set. 31.9.4.1 Read Sequence In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. 394 AT91SAM9G10 6462A–ATARM–03-Jun-09 Note that a STOP or a repeated START always follows a NACK. See Figure 31-25 on page 396. 31.9.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 31-26 on page 396. 31.9.4.3 Clock Synchronization Sequence In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 31-28 on page 398 and Figure 31-29 on page 399. 31.9.4.4 General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 31-27 on page 397. 31.9.5 31.9.5.1 Data Transfer Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 31-25 on page 396 describes the write operation. 395 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 31-25. Read Access Ordered by a MASTER SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK ACK/NACK from the Master A DATA NA S/Sr TWD TXRDY NACK SVACC SVREAD EOSVACC S ADR R NA DATA NA P/S/Sr SADR R A DATA A Write THR Read RHR SVREAD has to be taken into account only while SVACC is active Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 31.9.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 31-26 on page 396 describes the Write operation. Figure 31-26. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK Read RHR TWD RXRDY SVACC SVREAD EOSVACC Notes: S ADR W NA DATA NA P/S/Sr SADR W A DATA A A DATA NA S/Sr SVREAD has to be taken into account only while SVACC is active 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. 396 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.9.5.3 General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 31-27 on page 397 describes the General Call access. Figure 31-27. Master Performs a General Call 0000000 + W RESET command = 00000110X WRITE command = 00000100X A TXD S GENERAL CALL A Reset or write DADD A DATA1 A DATA2 A New SADR P New SADR Programming sequence GCACC Reset after read SVACC Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. 397 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.9.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 31-28 on page 398 describes the clock synchronization in Read mode. 31.9.5.5 Figure 31-28. Clock Synchronization in Read Mode TWI_THR DATA0 1 DATA1 DATA2 S SADR R A DATA0 A DATA1 A XXXXXXX 2 DATA2 NA S TWCK Write THR CLOCK is tied low by the TWI as long as THR is empty SCLWS TXRDY SVACC SVREAD TXCOMP As soon as a START is detected TWI_THR is transmitted to the shift register 1 2 The data is memorized in TWI_THR until a new value is written Ack or Nack from the master The clock is stretched after the ACK, the state of TWD is undefined during clock stretching Notes: 1. TXRDY is reset when data has been written in the TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock synchronization mechanism is started. 398 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.9.5.6 Clock Synchronization in Write Mode The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 31-29 on page 399 describes the clock synchronization in Read mode. Figure 31-29. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full TWD S SADR W A DATA0 A DATA1 A DATA2 NA S ADR TWI_RHR SCLWS DATA0 is not read in the RHR DATA1 DATA2 SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 SVACC SVREAD TXCOMP As soon as a START is detected Rd DATA1 Rd DATA2 Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. 399 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.9.5.7 31.9.5.8 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 31-30 on page 400 describes the repeated start + reversal from Read to Write mode. Figure 31-30. Repeated Start + Reversal from Read to Write Mode TWI_THR DATA0 DATA1 TWD S SADR R A DATA0 A DATA1 NA Sr SADR W A DATA2 A DATA3 A DATA3 P TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP As soon as a START is detected DATA2 Cleared after read 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 31.9.5.9 Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command.Figure 31-31 on page 400 describes the repeated start + reversal from Write to Read mode. Figure 31-31. Repeated Start + Reversal from Write to Read Mode TWI_THR DATA2 DATA3 TWD TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP S SADR W A DATA0 A DATA1 A Sr SADR R A DATA2 A DATA3 NA P DATA0 DATA1 Read TWI_RHR As soon as a START is detected Cleared after read Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 400 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.9.6 Read Write Flowcharts The flowchart shown in Figure 31-32 on page 401 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 31-32. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? No No GACC = 1 ? No SVREAD = 0 ? No EOSACC = 1 ? TXRDY= 1 ? No No Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? END Read TWI_RHR No GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? No Change SADR 401 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10 Two-wire Interface (TWI) User Interface Table 31-6. Offset 0x00 0x04 0x08 0x0C 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 - 0xFC Register Mapping Register Control Register Master Mode Register Slave Mode Register Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Name TWI_CR TWI_MMR TWI_SMR TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR – Access Write-only Read-write Read-write Read-write Read-write Read-only Write-only Write-only Read-only Read-only Write-only – Reset N/A 0x00000000 0x00000000 0x00000000 0x00000000 0x0000F009 N/A N/A 0x00000000 0x00000000 0x00000000 – 402 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.1 Name: Address: Access: Reset: 31 – 23 – 15 – TWI Control Register TWI_CR 0xFFFAC000 Write-only 0x00000000 30 – 22 – 14 – 6 QUICK 29 – 21 – 13 – 5 SVDIS 28 – 20 – 12 – 4 SVEN 27 – 19 – 11 – 3 MSDIS 26 – 18 – 10 – 2 MSEN 25 – 17 – 9 – 1 STOP 24 – 16 – 8 – 0 START 7 SWRST • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR). • STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In master read mode, if a NACK bit is received, the STOP is automatically performed. – In master data write operation, a STOP condition will be sent after the transmission of the current data is finished. • MSEN: TWI Master Mode Enabled 0 = No effect. 1 = If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. • MSDIS: TWI Master Mode Disabled 0 = No effect. 1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. 403 AT91SAM9G10 6462A–ATARM–03-Jun-09 • SVEN: TWI Slave Mode Enabled 0 = No effect. 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • QUICK: SMBUS Quick Command 0 = No effect. 1 = If Master mode is enabled, a SMBUS Quick Command is sent. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset. 404 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.2 Name: Address: Access: Reset: 31 – 23 – 15 – 7 – TWI Master Mode Register TWI_MMR 0xFFFAC004 Read-write 0x00000000 30 – 22 29 – 21 28 – 20 27 – 19 DADR 11 – 3 – 26 – 18 25 – 17 24 – 16 14 – 6 – 13 – 5 – 12 MREAD 4 – 10 – 2 – 9 IADRSZ 1 – 8 0 – • IADRSZ: Internal Device Address Size IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address One-byte internal device address Two-byte internal device address Three-byte internal device address • MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. • DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode. 405 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.3 Name: Address: Access: Reset: 31 – 23 – 15 – 7 – TWI Slave Mode Register TWI_SMR 0xFFFAC008 Read-write 0x00000000 30 – 22 29 – 21 28 – 20 27 – 19 SADR 11 – 3 – 26 – 18 25 – 17 24 – 16 14 – 6 – 13 – 5 – 12 – 4 – 10 – 2 – 9 8 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. 406 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.4 Name: Address: Access: Reset: 31 – 23 TWI Internal Address Register TWI_IADR 0xFFFAC00C Read-write 0x00000000 30 – 22 29 – 21 28 – 20 IADR 27 – 19 26 – 18 25 – 17 24 – 16 15 14 13 12 IADR 11 10 9 8 7 6 5 4 IADR 3 2 1 0 • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. 407 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.5 Name: Address: Access: Reset: 31 – 23 TWI Clock Waveform Generator Register TWI_CWGR 0xFFFAC010 Read-write 0x00000000 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 25 – 17 CKDIV 9 24 – 16 15 14 13 12 CHDIV 11 10 8 7 6 5 4 CLDIV 3 2 1 0 TWI_CWGR is only used in Master mode. • CLDIV: Clock Low Divider The SCL low period is defined as follows: T low = ( ( CLDIV × 2 CKDIV ) + 4 ) × T MCK • CHDIV: Clock High Divider The SCL high period is defined as follows: T high = ( ( CHDIV × 2 CKDIV ) + 4 ) × T MCK • CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. 408 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.6 Name: Address: Access: Reset: 31 – 23 – 15 TWI Status Register TWI_SR 0xFFFAC020 Read-only 0x0000F009 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 EOSACC 3 SVREAD 26 – 18 – 10 SCLWS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 7 – 6 OVRE 5 GACC 4 SVACC • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame. 1 = When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 31-8 on page 381 and in Figure 31-10 on page 382. TXCOMP used in Slave mode: 0 = As soon as a Start is detected. 1 = After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 31-28 on page 398, Figure 31-29 on page 399, Figure 31-30 on page 400 and Figure 31-31 on page 400. • RXRDY: Receive Holding Register Ready (automatically set / reset) 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 31-10 on page 382. RXRDY behavior in Slave mode can be seen in Figure 31-26 on page 396, Figure 31-29 on page 399, Figure 31-30 on page 400 and Figure 31-31 on page 400. • TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode: 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 31-8 on page 381. 409 AT91SAM9G10 6462A–ATARM–03-Jun-09 TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 31-25 on page 396, Figure 31-28 on page 398, Figure 31-30 on page 400 and Figure 31-31 on page 400. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0 = Indicates that a write access is performed by a Master. 1 = Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 31-25 on page 396, Figure 31-26 on page 396, Figure 31-30 on page 400 and Figure 31-31 on page 400. • SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 31-25 on page 396, Figure 31-26 on page 396, Figure 31-30 on page 400 and Figure 31-31 on page 400. • GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0 = No General Call has been detected. 1 = A General Call has been detected. After the detection of General Call, if need be, the programmer may acknowledge this access and decode the following bytes and respond according to the value of the bytes. GACC behavior can be seen in Figure 31-27 on page 397. • OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. • NACK: Not Acknowledged (clear on read) NACK used in Master mode: 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. NACK used in Slave Read mode: 410 AT91SAM9G10 6462A–ATARM–03-Jun-09 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 31-28 on page 398 and Figure 31-29 on page 399. • EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0 = A slave access is being performing. 1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 31-30 on page 400 and Figure 31-31 on page 400 411 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.7 Name: Address: Access: Reset: 31 – 23 – 15 TWI Interrupt Enable Register TWI_IER 0xFFFAC024 Write-only 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 7 – 6 OVRE 5 GACC 4 SVACC • TXCOMP: Transmission Completed Interrupt Enable • RXRDY: Receive Holding Register Ready Interrupt Enable • TXRDY: Transmit Holding Register Ready Interrupt Enable • SVACC: Slave Access Interrupt Enable • GACC: General Call Access Interrupt Enable • OVRE: Overrun Error Interrupt Enable • NACK: Not Acknowledge Interrupt Enable • ARBLST: Arbitration Lost Interrupt Enable • SCL_WS: Clock Wait State Interrupt Enable • EOSACC: End Of Slave Access Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 412 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.8 Name: Address: Access: Reset: 31 – 23 – 15 TWI Interrupt Disable Register TWI_IDR 0xFFFAC028 Write-only 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 7 – 6 OVRE 5 GACC 4 SVACC • TXCOMP: Transmission Completed Interrupt Disable • RXRDY: Receive Holding Register Ready Interrupt Disable • TXRDY: Transmit Holding Register Ready Interrupt Disable • SVACC: Slave Access Interrupt Disable • GACC: General Call Access Interrupt Disable • OVRE: Overrun Error Interrupt Disable • NACK: Not Acknowledge Interrupt Disable • ARBLST: Arbitration Lost Interrupt Disable • SCL_WS: Clock Wait State Interrupt Disable • EOSACC: End Of Slave Access Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 413 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.9 Name: Address: Access: Reset: 31 – 23 – 15 TWI Interrupt Mask Register TWI_IMR 0xFFFAC02C Read-only 0x00000000 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP 7 – 6 OVRE 5 GACC 4 SVACC • TXCOMP: Transmission Completed Interrupt Mask • RXRDY: Receive Holding Register Ready Interrupt Mask • TXRDY: Transmit Holding Register Ready Interrupt Mask • SVACC: Slave Access Interrupt Mask • GACC: General Call Access Interrupt Mask • OVRE: Overrun Error Interrupt Mask • NACK: Not Acknowledge Interrupt Mask • ARBLST: Arbitration Lost Interrupt Mask • SCL_WS: Clock Wait State Interrupt Mask • EOSACC: End Of Slave Access Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 414 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.10 TWI Receive Holding Register Name: TWI_RHR Address: Access: Reset: 31 – 23 – 15 – 7 0xFFFAC030 Read-only 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • RXDATA: Master or Slave Receive Holding Data 415 AT91SAM9G10 6462A–ATARM–03-Jun-09 31.10.11 TWI Transmit Holding Register Name: TWI_THR Address: Access: Reset: 31 – 23 – 15 – 7 0xFFFAC034 Read-write 0x00000000 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • TXDATA: Master or Slave Transmit Holding Data 416 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 32. Universal Synchronous Asynchronous Receiver Transmitter (USART) 32.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots and infrared transceivers. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 417 6462A–ATARM–03-Jun-09 32.2 Block Diagram Figure 32-1. USART Block Diagram Peripheral DMA Controller Channel Channel USART PIO Controller RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS PMC MCK MCK/DIV Baud Rate Generator SCK DIV User Interface SLCK APB 418 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.3 Application Block Diagram Figure 32-2. Application Block Diagram PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver USART RS232 Drivers Modem PSTN RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers Serial Port Differential Bus 419 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.4 I/O Lines Description I/O Line Description Description Serial Clock Transmit Serial Data Receive Serial Data Clear to Send Request to Send Type I/O I/O Input Input Output Low Low Active Level Table 32-1. Name SCK TXD RXD CTS RTS 420 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.5 32.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature is used, the internal pull up on TXD must also be enabled. Only USART– fully equipped with all the modem signals. Table 32-2. Instance USART0 USART0 USART0 USART0 USART0 USART0 USART1 USART1 USART1 USART1 USART1 USART2 USART2 USART2 USART2 USART2 I/O Lines Signal CTS0 RTS0 RTS0 RXD0 SCK0 TXD0 CTS1 RTS1 RXD1 SCK1 TXD1 CTS2 RTS2 RXD2 SCK2 TXD2 I/O Line PC11 PA23 PC10 PC9 PC10 PC8 PA13 PA12 PC13 PA11 PC12 PA16 PA15 PC15 PA14 PC14 Peripheral A B A A B A B B A B A B B A B A 32.5.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. 421 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.5.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Inter-rupt Table 32-3. Instance USART0 USART1 USART2 Peripheral IDs ID 6 7 8 Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. 422 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.5 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling receiver frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication • High-speed 5- to 9-bit full-duplex synchronous serial communication – MSB- or LSB-first – 1 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling frequency – Optional hardware handshaking – Optional break management – Optional multidrop serial communication • RS485 with driver control signal • ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • InfraRed IrDA Modulation and Demodulation • Test modes – Remote loopback, local loopback, automatic echo 423 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: • the Master Clock MCK • a division of the Master Clock, the divider being product dependent, but generally set to 8 • the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 32-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC SCK 32.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over ) CD ) This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. 424 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.6.1.2 Baud Rate Calculation Example Table 32-4 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Baud Rate Example (OVER = 0) Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 6 8 8 12 13 20 20 23 24 30 39 40 40 52 53 54 65 81 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 0.00% 0.00% 1.70% 0.00% 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% Error Table 32-4. Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 The baud rate is calculated with the following formula: BaudRate = MCK ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 – ⎛ --------------------------------------------------⎞ ⎝ ActualBaudRate ⎠ 32.6.1.3 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the 425 6462A–ATARM–03-Jun-09 AT91SAM9G10 clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = ---------------------------------------------------------------⎛ 8 ( 2 – Over ) ⎛ CD + FP⎞ ⎞ ------ ⎠ ⎠ ⎝ ⎝ 8 The modified architecture is presented below: Figure 32-4. Fractional Baud Rate Generator FP USCLKS MCK MCK/DIV SCK Reserved CD Modulus Control FP CD SCK FIDI 0 OVER Sampling Divider 1 1 SYNC USCLKS = 3 Sampling Clock 0 Baud Rate Clock SYNC 0 1 2 3 16-bit Counter glitch-free logic >1 1 0 0 32.6.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. BaudRate = SelectedClock ------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the receive part limits the SCK maximum frequency to MCK/4.5, When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 426 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.6.1.5 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- × f Fi where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 32-5. Table 32-5. DI field Di (decimal) Binary and Decimal Values for Di 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 32-6. Table 32-6. FI field Fi (decimal Binary and Decimal Values for Fi 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 32-7 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 32-7. Fi/Di 1 2 4 8 16 32 12 20 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). 427 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 32-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 32.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally. 32.6.3 32.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The num428 6462A–ATARM–03-Jun-09 AT91SAM9G10 ber of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. Figure 32-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 32-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 32.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 32-8 illustrates this coding scheme. 429 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-8. NRZ to Manchester Encoding NRZ encoded data Manchester encoded data 1 0 1 1 0 0 0 1 Txd The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 32-9 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. Figure 32-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 32-10 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition 430 6462A–ATARM–03-Jun-09 AT91SAM9G10 occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information. Figure 32-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data Txd DATA One bit start frame delimiter SFD Manchester encoded data Txd DATA SFD Manchester encoded data Txd Command Sync start frame delimiter DATA Data Sync start frame delimiter 32.6.3.3 Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. 431 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-11. Bit Resynchronization Oversampling 16x Clock RXD Sampling point Expected edge Synchro. Error Synchro. Jump Tolerance Sync Jump Synchro. Error 32.6.3.4 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 32-12 and Figure 32-13 illustrate start detection and character reception when USART operates in asynchronous mode. 432 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-12. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 32-13. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 32.6.3.5 Manchester Decoder When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See Figure 32-9 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 32-14. The sample pulse rejection mechanism applies. 433 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-14. Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 32-15 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. See Figure 32-16 for an example of Manchester error detection during data phase. Figure 32-15. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Preamble Mismatch invalid pattern Manchester encoded data Txd SFD DATA Preamble Length is set to 8 Figure 32-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR 434 6462A–ATARM–03-Jun-09 AT91SAM9G10 field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-toone transition. 32.6.3.6 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 32-17. Figure 32-17. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line ASK/FSK downstream transmitter Manchester decoder USART Receiver Downstream Receiver Manchester encoder PA RF filter Mod VCO USART Emitter control The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 32-18 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 32-19. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver 435 6462A–ATARM–03-Jun-09 AT91SAM9G10 switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 32-18. ASK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output ASK Modulator Output Uptstream Frequency F0 0 0 1 Txd Figure 32-19. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 0 0 1 Txd 32.6.3.7 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 32-20 illustrates a character reception in synchronous mode. Figure 32-20. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 436 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.6.3.8 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 32-21. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 437 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.6.3.9 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 439. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 32-8 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 32-8. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 32-22 illustrates the parity bit status setting and clearing. 438 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-22. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 32.6.3.10 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. 32.6.3.11 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 32-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 439 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-23. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write US_THR TXRDY TXEMPTY Table 32-9 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 32-9. Maximum Timeguard Length Depending on Baud Rate Bit time µs 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 32.6.3.12 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: • Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state 440 6462A–ATARM–03-Jun-09 AT91SAM9G10 on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 32-24 shows the block diagram of the Receiver Time-out feature. Figure 32-24. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 32-10 gives the maximum time-out period for some standard baud rates. Table 32-10. Maximum Time-out Period Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 Bit Time µs 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 441 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 32-10. Maximum Time-out Period (Continued) Baud Rate 56000 57600 200000 Bit Time 18 17 5 Time-out 1 170 1 138 328 32.6.3.13 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 32-25. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 32.6.3.14 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 442 6462A–ATARM–03-Jun-09 AT91SAM9G10 The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 32-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 32-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write US_CR TXRDY TXEMPTY 32.6.3.15 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 32.6.3.16 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 32-27. 443 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-27. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 32-28 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 32-28. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1 Figure 32-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 32-29. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 444 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 32.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 424). The USART connects to a smart card as shown in Figure 32-30. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 32-30. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 457 and “PAR: Parity Type” on page 458. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 32.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 32-31. 445 6462A–ATARM–03-Jun-09 AT91SAM9G10 If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 32-32. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 32-31. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 32-32. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 32.6.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. 32.6.4.4 32.6.4.5 Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. 446 6462A–ATARM–03-Jun-09 AT91SAM9G10 When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. 32.6.4.6 Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 32-33. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 32-33. Connection to IrDA Transceivers 32.6.4.7 32.6.5 USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: • Disable TX and Enable RX 447 6462A–ATARM–03-Jun-09 AT91SAM9G10 • Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption). • Receive data 32.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 32-11. Table 32-11. IrDA Pulse Duration Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s Pulse Duration (3/16) 78.13 µs 19.53 µs 9.77 µs 4.88 µs 3.26 µs 1.63 µs Figure 32-34 shows an example of character transmission. Figure 32-34. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1 TXD Bit Period 3 16 Bit Period 32.6.5.2 IrDA Baud Rate Table 32-12 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 32-12. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 CD 2 11 18 22 4 22 36 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 448 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 32-12. IrDA Baud Rate Error (Continued) Peripheral Clock 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 57 600 38 400 38 400 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 43 6 33 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.93% 0.00% 1.38% 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 3.26 4.88 4.88 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 32.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 32-35 illustrates the operations of the IrDA demodulator. Figure 32-35. IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 43 Pulse Rejected 5 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 449 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 32-36. Figure 32-36. Typical Connection to a RS485 Bus USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 32-37 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 32-37. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 450 6462A–ATARM–03-Jun-09 AT91SAM9G10 451 6462A–ATARM–03-Jun-09 AT91SAM9G10 • • 32.6.7 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 32.6.7.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 32-38. Normal Mode Configuration RXD Receiver TXD Transmitter 32.6.7.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 32-39. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 32-39. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 32.6.7.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 32-40. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. 452 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 32-40. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD 32.6.7.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 32-41. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 32-41. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 453 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Register Mapping Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Manchester Encoder Decoder Register Reserved Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR – US_FIDI US_NER – US_IF US_MAN – – Access Write-only Read-write Write-only Write-only Read-only Read-only Read-only Write-only Read-write Read-write Read-write – Read-write Read-only – Read-write Read-write – – Reset – – – – 0x0 – 0x0 – 0x0 0x0 0x0 – 0x174 – – 0x0 0x30011004 – – Table 32-14. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x2C - 0x3C 0x0040 0x0044 0x0048 0x004C 0x0050 0x5C - 0xFC 0x100 - 0x128 454 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.1 Name: USART Control Register US_CR 0xFFFB0000 (0), 0xFFFB4000 (1), 0xFFFB8000 (2) Write-only 30 – 22 – 14 RSTNACK 6 TXEN 29 – 21 – 13 RSTIT 5 RXDIS 28 – 20 – 12 SENDA 4 RXEN 27 – 19 RTSDIS 11 STTTO 3 RSTTX 26 – 18 RTSEN 10 STPBRK 2 RSTRX 25 – 17 – 9 STTBRK 1 – 24 – 16 – 8 RSTSTA 0 – Addresses: Access: 31 – 23 – 15 RETTO 7 TXDIS • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. 455 6462A–ATARM–03-Jun-09 AT91SAM9G10 • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. • RETTO: Rearm Time-out 0: No effect 1: Restart Time-out • RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. 456 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.2 Name: USART Mode Register US_MR 0xFFFB0004 (0), 0xFFFB4004 (1), 0xFFFB8004 (2) Read-write 30 MODSYNC– 22 VAR_SYNC 14 CHMODE 7 CHRL 6 5 USCLKS 29 MAN 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 – 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Addresses: Access: 31 ONEBIT 23 18 CLKO 10 PAR 2 16 MSBF 8 SYNC 0 15 1 USART_MODE • USART_MODE USART_MODE 0 0 0 0 0 1 0 0 0 1 1 0 Others 0 0 1 0 1 0 0 1 0 0 0 0 Mode of the USART Normal RS485 Hardware Handshaking IS07816 Protocol: T = 0 IS07816 Protocol: T = 1 IrDA Reserved • USCLKS: Clock Selection USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK/DIV (DIV = 8) Reserved SCK • CHRL: Character Length. CHRL 0 0 1 1 0 1 0 1 Character Length 5 bits 6 bits 7 bits 8 bits 457 6462A–ATARM–03-Jun-09 AT91SAM9G10 • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • PAR: Parity Type PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode • NBSTOP: Number of Stop Bits NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin. • MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 458 6462A–ATARM–03-Jun-09 AT91SAM9G10 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on SYNC value. 1: The sync field is updated when a character is written into US_THR register. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. • FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). • MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. • MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit. 459 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.3 Name: USART Interrupt Enable Register US_IER Addresses: 0xFFFB0008 (0), 0xFFFB4008 (1), 0xFFFB8008 (2) Access: 31 – 23 – 15 – 7 PARE Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITER 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 16 – 8 TIMEOUT 0 RXRDY 12 RXBUFF 4 ENDTX • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • ENDRX: End of Receive Transfer Interrupt Enable • ENDTX: End of Transmit Interrupt Enable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Enable • RXBUFF: Buffer Full Interrupt Enable • NACK: Non Acknowledge Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable 460 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.4 Name: USART Interrupt Disable Register US_IDR 0xFFFB000C (0), 0xFFFB400C (1), 0xFFFB800C (2) Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITER 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 Addresses: Access: 31 – 23 – 15 – 7 PARE 16 – 8 TIMEOUT 0 RXRDY 12 RXBUFF 4 ENDTX • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • ENDRX: End of Receive Transfer Interrupt Disable • ENDTX: End of Transmit Interrupt Disable • OVRE: Overrun Error Interrupt Disable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Disable • RXBUFF: Buffer Full Interrupt Disable • NACK: Non Acknowledge Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable 461 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.5 Name: USART Interrupt Mask Register US_IMR 0xFFFB0010 (0), 0xFFFB4010 (1), 0xFFFB8010 (2) Read-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITER 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 Addresses: Access: 31 – 23 – 15 – 7 PARE 16 – 8 TIMEOUT 0 RXRDY 12 RXBUFF 4 ENDTX • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • ENDRX: End of Receive Transfer Interrupt Mask • ENDTX: End of Transmit Interrupt Mask • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Mask • RXBUFF: Buffer Full Interrupt Mask • NACK: Non Acknowledge Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask 462 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.6 Name: USART Channel Status Register US_CSR 0xFFFB0014 (0), 0xFFFB4014 (1), 0xFFFB8014 (2) Read-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 – 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 – 10 ITER 2 RXBRK 25 – 17 – 9 TXEMPTY 1 TXRDY 24 MANERR 16 – 8 TIMEOUT 0 RXRDY Addresses: Access: 31 – 23 CTS 15 – 7 PARE • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. • ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. • ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. 463 6462A–ATARM–03-Jun-09 AT91SAM9G10 • FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITER: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. • TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. • RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. • NACKNon Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. • • CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. • CTS: Image of CTS Input 0: CTS is at 0. 464 6462A–ATARM–03-Jun-09 AT91SAM9G10 1: CTS is at 1. • MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. 465 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.7 Name: USART Receive Holding Register US_RHR 0xFFFB0018 (0), 0xFFFB4018 (1), 0xFFFB8018 (2) Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 RXCHR 0 Addresses: Access: 31 – 23 – 15 RXSYNH 7 • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. 466 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.8 Name: USART Transmit Holding Register US_THR 0xFFFB001C (0), 0xFFFB401C (1), 0xFFFB801C (2) Write-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 TXCHR 0 Addresses: Access: 31 – 23 – 15 TXSYNH 7 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. 467 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.9 Name: USART Baud Rate Generator Register US_BRGR 0xFFFB0020 (0), 0xFFFB4020 (1), 0xFFFB8020 (2) Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CD 7 6 5 4 CD 3 2 1 0 27 – 19 – 11 26 – 18 25 – 17 FP 9 24 – 16 Addresses: Access: 31 – 23 – 15 10 8 • CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 CD 0 1 to 65535 Baud Rate = Selected Clock/16/CD OVER = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816 • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. 468 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.10 Name: USART Receiver Time-out Register US_RTOR 0xFFFB0024 (0), 0xFFFB4024 (1), 0xFFFB8024 (2) Read-write 30 29 28 27 26 25 24 Addresses: Access: 31 – 23 – 15 – 22 – 14 – 21 – 13 – 20 – 12 TO – 19 – 11 – 18 – 10 – 17 – 9 – 16 – 8 7 6 5 4 TO 3 2 1 0 • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 469 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.11 Name: USART Transmitter Timeguard Register US_TTGR 0xFFFB0028 (0), 0xFFFB4028 (1), 0xFFFB8028 (2) Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TG 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Addresses: Access: 31 – 23 – 15 – 7 • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 470 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.12 Name: USART FI DI RATIO Register US_FIDI 0xFFFB0040 (0), 0xFFFB4040 (1), 0xFFFB8040 (2) Read-write 0x174 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FI_DI_RATIO 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 – 9 FI_DI_RATIO 1 24 – 16 – 8 Addresses: Access: Reset Value: 31 – 23 – 15 – 7 2 0 • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 32.7.13 Name: USART Number of Errors Register US_NER 0xFFFB0044 (0), 0xFFFB4044 (1), 0xFFFB8044 (2) Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 NB_ERRORS 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Addresses: Access: 31 – 23 – 15 – 7 • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 471 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.14 Name: USART IrDA FILTER Register US_IF 0xFFFB004C (0), 0xFFFB404C (1), 0xFFFB804C (2) Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IRDA_FILTER 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Addresses: Access: 31 – 23 – 15 – 7 • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 472 6462A–ATARM–03-Jun-09 AT91SAM9G10 32.7.15 Name: USART Manchester Configuration Register US_MAN 0xFFFB0050 (0), 0xFFFB4050 (1), 0xFFFB8050 (2) Read-write 30 DRIFT 22 – 14 – 6 – 29 1 21 – 13 – 5 – 28 RX_MPOL 20 – 12 TX_MPOL 4 – 27 – 19 26 – 18 RX_PL 11 – 3 10 – 2 TX_PL 9 TX_PP 1 0 8 25 RX_PP 17 16 24 Addresses: Access: 31 – 23 – 15 – 7 – • TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1 - 15: The Preamble Length is TX_PL x Bit Period • TX_PP: Transmitter Preamble Pattern TX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (TX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO • TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1 - 15: The detected preamble length is RX_PL x Bit Period • RX_PP: Receiver Preamble Pattern detected RX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (RX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO 473 6462A–ATARM–03-Jun-09 AT91SAM9G10 • RX_MPOL: Receiver Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. 474 6462A–ATARM–03-Jun-09 AT91SAM9G10 33. Synchronous Serial Controller (SSC) 33.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels,the SSC permits interfacing with low processor overhead to the following: • CODEC’s in master or slave mode • DAC through dedicated serial interface, particularly I2S • Magnetic card reader 475 6462A–ATARM–03-Jun-09 33.2 Block Diagram Figure 33-1. Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK TD SSC Interface PIO RF RK Interrupt Control RD PMC MCK SSC Interrupt 33.3 Application Block Diagram Figure 33-2. Application Block Diagram OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management Serial AUDIO Codec Line Interface 476 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.4 Pin Name List I/O Lines Description Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output Table 33-1. Pin Name RF RK RD TF TK TD 33.5 33.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. Table 33-2. I/O Lines Signal RD0 RF0 RK0 TD0 TF0 TK0 RD1 RF1 RK1 TD1 TF1 TK1 RD2 RF2 RK2 TD2 TF2 TK2 I/O Line PB24 PB26 PB25 PB23 PB21 PB22 PA20 PA22 PA21 PA19 PA17 PA18 PC28 PC30 PC29 PC27 PC25 PC26 Peripheral A A A A A A B B B B B B B B B B B B Instance SSC0 SSC0 SSC0 SSC0 SSC0 SSC0 SSC1 SSC1 SSC1 SSC1 SSC1 SSC1 SSC2 SSC2 SSC2 SSC2 SSC2 SSC2 477 6462A–ATARM–03-Jun-09 33.5.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AICbefore configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each Table 33-3. Instance SSC0 SSC1 SSC2 33.5.3 Peripheral IDs ID 14 15 16 pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. 478 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.6 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. Figure 33-3. SSC Functional Block Diagram Transmitter Clock Output Controller TX clock TK MCK Clock Divider TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller Frame Sync Controller TF Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register TD APB User Interface Load Shift Receiver Clock Output Controller RK RK Input TX Clock RF TF Start Selector Receive Clock RX Clock Controller Frame Sync Controller RF Receive Shift Register Receive Holding Register Receive Sync Holding Register RD RX PDC PDC Interrupt Control Load Shift AIC 479 6462A–ATARM–03-Jun-09 Figure 33-4. SSC Functional Block Diagram Transmitter Clock Output Controller TX clock TK MCK Clock Divider TK Input RX clock TF RF Start Selector Transmit Clock Controller Frame Sync Controller TF Transmit Shift Register Transmit Holding Register Load Shift Transmit Sync Holding Register TD APB User Interface Receiver Clock Output Controller RK RK Input TX Clock RF TF Start Selector Receive Clock RX Clock Controller Frame Sync Controller RF Receive Shift Register Receive Holding Register Receive Sync Holding Register RD Interrupt Control Load Shift NVIC 33.6.1 Clock Management The transmitter clock can be generated by: • an external clock received on the TK I/O pad • the receiver clock • the internal clock divider The receiver clock can be generated by: • an external clock received on the RK I/O pad • the transmitter clock • the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 480 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.6.1.1 Clock Divider Figure 33-5. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 33-6. Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 Table 33-4. Maximum MCK / 2 Minimum MCK / 8190 33.6.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin 481 6462A–ATARM–03-Jun-09 (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 33-7. Transmitter Clock Management TK (pin) MUX Receiver Clock Tri_state Controller Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Transmitter Clock CKI CKG 33.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. Figure 33-8. Receiver Clock Management RK (pin) Tri-state Controller MUX Transmitter Clock Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Receiver Clock CKI CKG 482 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.6.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: – Master Clock divided by 2 if Receiver Frame Synchro is input – Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: – Master Clock divided by 6 if Transmit Frame Synchro is input – Master Clock divided by 2 if Transmit Frame Synchro is output 33.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 484. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 486. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 33-9. Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock TF SSC_TFMR.MSBF 0 SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD Start Selector Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR 0 1 SSC_TSHR SSC_TFMR.FSLEN 483 6462A–ATARM–03-Jun-09 33.6.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 484. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 486. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. Figure 33-10. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF SSC_RFMR.MSBF SSC_RFMR.DATNB Start Selector Receive Shift Register RD SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN SSC_RHR SSC_RFMR.DATLEN 33.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: • Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. • Synchronously with the transmitter/receiver • On detection of a falling/rising edge on TF/RF • On detection of a low level/high level on TF/RF • On detection of a level change or an edge on TF/RF 484 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). Figure 33-11. Transmit Start Mode TK TF (Input) Start = Low Level on TF TD (Output) TD (Output) X BO B1 STTDLY Start = Falling Edge on TF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on TF TD (Output) TD (Output) TD (Output) TD (Output) X Start = Rising Edge on TF BO B1 STTDLY Start = Level Change on TF X BO B1 BO B1 STTDLY Start = Any Edge on TF X BO B1 BO B1 STTDLY Figure 33-12. Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF RD (Input) RD (Input) X BO B1 STTDLY Start = Falling Edge on RF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on RF RD (Input) RD (Input) RD (Input) RD (Input) X Start = Rising Edge on RF BO B1 STTDLY Start = Level Change on RF X BO B1 BO B1 STTDLY Start = Any Edge on RF X BO B1 BO B1 STTDLY 485 6462A–ATARM–03-Jun-09 33.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 33.6.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out. 33.6.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). Receive Compare Modes Figure 33-13. Receive Compare Modes RK 33.6.6 RD (Input) CMP0 CMP1 CMP2 CMP3 Start Ignored B0 B1 B2 FSLEN Up to 16 Bits (4 in This Example) STDLY DATLEN 486 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.6.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: • the event that starts the data transfer (START) • the delay in number of bit periods between the start event and the first data bit (STTDLY) • the length of the data (DATLEN) • the number of data to be transferred for each start event (DATNB). • the length of synchronization transferred for each start event (FSLEN) • the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. 33.6.7 487 6462A–ATARM–03-Jun-09 Table 33-5. Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR Data Frame Registers Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN SSC_RCMR SSC_RCMR PERIOD STTDLY Up to 512 Up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number of words transmitted in frame Most significant bit first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay Figure 33-14. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start PERIOD TF/RF (1) Start FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored TD (If FSDEN = 0) RD DATNB Note: 1. Example of input on falling edge of TF/RF. Figure 33-15. Transmit Frame Format in Continuous Mode Start TD Data From SSC_THR DATLEN Data From SSC_THR DATLEN Default Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR 488 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 33-16. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Data To SSC_RHR DATLEN Data To SSC_RHR DATLEN Note: 1. STTDLY is set to 0. 33.6.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 33.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. Figure 33-17. Interrupt Block Diagram SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear SSC Interrupt 489 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 33-18. Interrupt Block Diagram SSC_IMR SSC_IER Set SSC_IDR Clear Transmitter TXRDY TXEMPTY TXSYNC Interrupt Control SSC Interrupt Receiver RXRDY OVRUN RXSYNC 490 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 33-19. Audio Application Block Diagram Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER Clock SCK Word Select WS Data SD MSB Left Channel LSB MSB Right Channel Figure 33-20. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend Serial Data In 491 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 33-21. Time Slot Application Block Diagram SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend Serial Data in 492 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8 Synchronous Serial Controller (SSC) User Interface Register Mapping Register Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Receive Compare 0 Register Receive Compare 1 Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Reserved Name SSC_CR SSC_CMR – – SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR – – SSC_RSHR SSC_TSHR SSC_RC0R SSC_RC1R SSC_SR SSC_IER SSC_IDR SSC_IMR – – – Access Write-only Read-write – – Read-write Read-write Read-write Read-write Read-only Write-only – – Read-only Read-write Read-write Read-write Read-only Write-only Write-only Read-only – – – Reset – 0x0 – – 0x0 0x0 0x0 0x0 0x0 – – – 0x0 0x0 0x0 0x0 0x000000CC – – 0x0 – – – Table 33-6. Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100- 0x124 0x100- 0x124 493 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.1 Name: SSC Control Register SSC_CR: 0xFFFBC000 (0), 0xFFFC0000 (1), 0xFFFC4000 (2) Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 TXDIS 1 RXDIS 24 – 16 – 8 TXEN 0 RXEN Addresses: Access: 31 – 23 – 15 SWRST 7 – • RXEN: Receive Enable 0 = No effect. 1 = Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0 = No effect. 1 = Disables Receive. If a character is currently being received, disables at end of current character reception. • TXEN: Transmit Enable 0 = No effect. 1 = Enables Transmit if TXDIS is not set. • TXDIS: Transmit Disable 0 = No effect. 1 = Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. • SWRST: Software Reset 0 = No effect. 1 = Performs a software reset. Has priority on any other bit in SSC_CR. 494 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.2 Name: SSC Clock Mode Register SSC_CMR 0xFFFBC004 (0), 0xFFFC0004 (1), 0xFFFC4004 (2) Read-write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DIV 27 – 19 – 11 26 – 18 – 10 DIV 3 2 1 0 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 – 7 • DIV: Clock Divider 0 = The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 495 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.3 Name: SSC Receive Clock Mode Register SSC_RCMR 0xFFFBC010 (0), 0xFFFC0010 (1), 0xFFFC4010 (2) Read-write 30 29 28 PERIOD 23 22 21 20 STTDLY 15 – 7 CKG 14 – 6 13 – 5 CKI 12 STOP 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 Addresses: Access: 31 • CKS: Receive Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock signal RK pin Reserved • CKO: Receive Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Receive Clock Output Mode None Continuous Receive Clock Receive Clock only during data transfers Reserved RK pin Input-only Output Output • CKI: Receive Clock Inversion 0 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1 = The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. 496 6462A–ATARM–03-Jun-09 AT91SAM9G10 • CKG: Receive Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Receive Clock Gating None, continuous clock Receive Clock enabled only if RF Low Receive Clock enabled only if RF High Reserved • START: Receive Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RF signal Detection of a high level on RF signal Detection of a falling edge on RF signal Detection of a rising edge on RF signal Detection of any level change on RF signal Detection of any edge on RF signal Compare 0 Reserved • STOP: Receive Stop Selection 0 = After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1 = After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. • STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. 497 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.4 Name: SSC Receive Frame Mode Register SSC_RFMR 0xFFFBC014 (0), 0xFFFC0014 (1), 0xFFFC4014 (2) Read-write 30 – 22 29 – 21 FSOS 13 – 5 LOOP 28 – Addresses: Access: 31 – 23 – 15 – 7 MSBF 27 – 19 26 – 18 FSLEN 25 – 17 24 FSEDGE 16 20 14 – 6 – 12 – 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • LOOP: Loop Mode 0 = Normal operating mode. 1 = RD is driven by TD, RF is driven by TF and TK drives RK. • MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is sampled first in the bit stream. 1 = The most significant bit of the data register is sampled first in the bit stream. • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). • FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. 498 6462A–ATARM–03-Jun-09 AT91SAM9G10 • FSOS: Receive Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF Pin Input-only Output Output Output Output Output Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection 499 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.5 Name: SSC Transmit Clock Mode Register SSC_TCMR 0xFFFBC018 (0), 0xFFFC0018 (1), 0xFFFC4018 (2) Read-write 30 29 28 PERIOD 23 22 21 20 STTDLY 15 – 7 CKG 14 – 6 13 – 5 CKI 12 – 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 Addresses: Access: 31 • CKS: Transmit Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved • CKO: Transmit Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Transmit Clock only during data transfers Reserved TK pin Input-only Output Output • CKI: Transmit Clock Inversion 0 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1 = The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. 500 6462A–ATARM–03-Jun-09 AT91SAM9G10 • CKG: Transmit Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TF Low Transmit Clock enabled only if TF High Reserved • START: Transmit Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 - 0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. Receive start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved • STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. 501 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.6 Name: SSC Transmit Frame Mode Register SSC_TFMR 0xFFFBC01C (0), 0xFFFC001C (1), 0xFFFC401C (2) Read-write 30 – 22 29 – 21 FSOS 13 – 5 DATDEF 28 – Addresses: Access: 31 – 23 FSDEN 15 – 7 MSBF 27 – 19 26 – 18 FSLEN 25 – 17 24 FSEDGE 16 20 14 – 6 – 12 – 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 • DATLEN: Data Length 0 = Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. • MSBF: Most Significant Bit First 0 = The lowest significant bit of the data register is shifted out first in the bit stream. 1 = The most significant bit of the data register is shifted out first in the bit stream. • DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1). • FSLEN: Transmit Frame Syn Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. 502 6462A–ATARM–03-Jun-09 AT91SAM9G10 • FSOS: Transmit Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF Pin Input-only Output Output Output Output Output Undefined • FSDEN: Frame Sync Data Enable 0 = The TD line is driven with the default value during the Transmit Frame Sync signal. 1 = SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection 503 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.7 Name: SSC Receive Holding Register SSC_RHR 0xFFFBC020 (0), 0xFFFC0020 (1), 0xFFFC4020 (2) Read-only 30 29 28 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Addresses: Access: 31 • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 33.8.8 Name: SSC Transmit Holding Register SSC_THR 0xFFFBC024 (0), 0xFFFC0024 (1), 0xFFFC4024 (2) Write-only 30 29 28 TDAT 27 26 25 24 Addresses: Access: 31 23 22 21 20 TDAT 19 18 17 16 15 14 13 12 TDAT 11 10 9 8 7 6 5 4 TDAT 3 2 1 0 • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 504 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.9 Name: SSC Receive Synchronization Holding Register SSC_RSHR 0xFFFBC030 (0), 0xFFFC0030 (1), 0xFFFC4030 (2) Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RSDAT 7 6 5 4 RSDAT 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 • RSDAT: Receive Synchronization Data 33.8.10 Name: SSC Transmit Synchronization Holding Register SSC_TSHR 0xFFFBC034 (0), 0xFFFC0034 (1), 0xFFFC4034 (2) Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 TSDAT 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 7 6 5 4 TSDAT 3 2 1 0 • TSDAT: Transmit Synchronization Data 505 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.11 Name: SSC Receive Compare 0 Register SSC_RC0R 0xFFFBC038 (0), 0xFFFC0038 (1), 0xFFFC4038 (2) Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CP0 7 6 5 4 CP0 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 • CP0: Receive Compare Data 0 33.8.12 Name: SSC Receive Compare 1 Register SSC_RC1R 0xFFFBC03C (0), 0xFFFC003C (1), 0xFFFC403C (2) Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CP1 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 7 6 5 4 CP1 3 2 1 0 • CP1: Receive Compare Data 1 506 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.13 Name: SSC Status Register SSC_SR 0xFFFBC040 (0), 0xFFFC0040 (1), 0xFFFC4040 (2) Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 RXEN 9 CP1 1 TXEMPTY 24 – 16 TXEN 8 CP0 0 TXRDY Addresses: Access: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready 0 = Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1 = SSC_THR is empty. • TXEMPTY: Transmit Empty 0 = Data remains in SSC_THR or is currently transmitted from TSR. 1 = Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. • ENDTX: End of Transmission 0 = The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1 = The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. • TXBUFE: Transmit Buffer Empty 0 = SSC_TCR or SSC_TNCR have a value other than 0. 1 = Both SSC_TCR and SSC_TNCR have a value of 0. • RXRDY: Receive Ready 0 = SSC_RHR is empty. 1 = Data has been received and loaded in SSC_RHR. • OVRUN: Receive Overrun 0 = No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1 = Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. • ENDRX: End of Reception 0 = Data is written on the Receive Counter Register or Receive Next Counter Register. 1 = End of PDCtransfer when Receive Counter Register has arrived at zero. 507 6462A–ATARM–03-Jun-09 AT91SAM9G10 • RXBUFF: Receive Buffer Full 0 = SSC_RCR or SSC_RNCR have a value other than 0. 1 = Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0 = A compare 0 has not occurred since the last read of the Status Register. 1 = A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0 = A compare 1 has not occurred since the last read of the Status Register. 1 = A compare 1 has occurred since the last read of the Status Register. • TXSYN: Transmit Sync 0 = A Tx Sync has not occurred since the last read of the Status Register. 1 = A Tx Sync has occurred since the last read of the Status Register. • RXSYN: Receive Sync 0 = An Rx Sync has not occurred since the last read of the Status Register. 1 = An Rx Sync has occurred since the last read of the Status Register. • TXEN: Transmit Enable 0 = Transmit is disabled. 1 = Transmit is enabled. • RXEN: Receive Enable 0 = Receive is disabled. 1 = Receive is enabled. 508 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.14 Name: SSC Interrupt Enable Register SSC_IER 0xFFFBC044 (0), 0xFFFC0044 (1), 0xFFFC4044 (2) Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Addresses: Access: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready Interrupt Enable 0 = 0 = No effect. 1 = Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Enable 0 = No effect. 1 = Enables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the Transmit Buffer Empty Interrupt • RXRDY: Receive Ready Interrupt Enable 0 = No effect. 1 = Enables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Enable 0 = No effect. 1 = Enables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Enable 0 = No effect. 1 = Enables the End of Reception Interrupt. 509 6462A–ATARM–03-Jun-09 AT91SAM9G10 • RXBUFF: Receive Buffer Full Interrupt Enable 0 = No effect. 1 = Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0 = No effect. 1 = Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0 = No effect. 1 = Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Enables the Rx Sync Interrupt. 510 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.15 Name: SSC Interrupt Disable Register SSC_IDR 0xFFFBC048 (0), 0xFFFC0048 (1), 0xFFFC4048 (2) Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Addresses: Access: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready Interrupt Disable 0 = No effect. 1 = Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Disable 0 = No effect. 1 = Disables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the Transmit Buffer Empty Interrupt. • RXRDY: Receive Ready Interrupt Disable 0 = No effect. 1 = Disables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Disable 0 = No effect. 1 = Disables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Disable 0 = No effect. 1 = Disables the End of Reception Interrupt. 511 6462A–ATARM–03-Jun-09 AT91SAM9G10 • RXBUFF: Receive Buffer Full Interrupt Disable 0 = No effect. 1 = Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0 = No effect. 1 = Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0 = No effect. 1 = Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0 = No effect. 1 = Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0 = No effect. 1 = Disables the Rx Sync Interrupt. 512 6462A–ATARM–03-Jun-09 AT91SAM9G10 33.8.16 Name: SSC Interrupt Mask Register SSC_IMR 0xFFFBC04C (0), 0xFFFC004C (1), 0xFFFC404C (2) Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Addresses: Access: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready Interrupt Mask 0 = The Transmit Ready Interrupt is disabled. 1 = The Transmit Ready Interrupt is enabled. • TXEMPTY: Transmit Empty Interrupt Mask 0 = The Transmit Empty Interrupt is disabled. 1 = The Transmit Empty Interrupt is enabled. • ENDTX: End of Transmission Interrupt Mask 0 = The End of Transmission Interrupt is disabled. 1 = The End of Transmission Interrupt is enabled. • TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The Transmit Buffer Empty Interrupt is disabled. 1 = The Transmit Buffer Empty Interrupt is enabled. • RXRDY: Receive Ready Interrupt Mask 0 = The Receive Ready Interrupt is disabled. 1 = The Receive Ready Interrupt is enabled. • OVRUN: Receive Overrun Interrupt Mask 0 = The Receive Overrun Interrupt is disabled. 1 = The Receive Overrun Interrupt is enabled. • ENDRX: End of Reception Interrupt Mask 0 = The End of Reception Interrupt is disabled. 1 = The End of Reception Interrupt is enabled. 513 6462A–ATARM–03-Jun-09 AT91SAM9G10 • RXBUFF: Receive Buffer Full Interrupt Mask 0 = The Receive Buffer Full Interrupt is disabled. 1 = The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0 = The Compare 0 Interrupt is disabled. 1 = The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0 = The Compare 1 Interrupt is disabled. 1 = The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0 = The Tx Sync Interrupt is disabled. 1 = The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0 = The Rx Sync Interrupt is disabled. 1 = The Rx Sync Interrupt is enabled. 514 6462A–ATARM–03-Jun-09 AT91SAM9G10 34. Timer Counter (TC) 34.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 34-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2. Table 34-1. Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Note: (1) Timer Counter Clock Assignment Definition MCK/2 MCK/8 MCK/32 MCK/128 SLCK 1. When Slow Clock is selected for Master Clock (CSS = 0 in PMC Master CLock Register), TIMER_CLOCK5 input is Master Clock, i.e., Slow CLock modified by PRES and MDIV fields. 515 6462A–ATARM–03-Jun-09 34.2 Block Diagram Figure 34-1. Timer Counter Block Diagram Parallel I/O Controller TCLK0 TIMER_CLOCK2 TIMER_CLOCK1 TIOA1 TIMER_CLOCK3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA2 TCLK1 XC0 XC1 XC2 TC0XC0S Timer/Counter Channel 0 TIOA TIOA0 TIOB TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOB0 SYNC INT0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC Timer/Counter Channel 1 TIOA TIOA1 TIOB TIOB1 INT1 TIOA1 TIOB1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB TIOB2 SYNC TIOA2 TIOB2 INT2 Timer Counter Interrupt Controller Table 34-2. Signal Name Description Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal Block/Channel Channel Signal TIOB INT SYNC 516 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.3 Pin Name List Table 34-3. Pin Name TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2 TC pin list Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O 34.4 34.4.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. Table 34-4. I/O Lines Signal TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 TIOA2 TIOB0 TIOB1 TIOB2 I/O Line PC16 PC17 PC18 PC19 PC21 PC23 PC20 PC22 PC24 Peripheral B B B B B B B B B Instance TC0 TC0 TC0 TC0 TC0 TC0 TC0 TC0 TC0 34.4.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. Interrupt The TC has an interrupt line connected to the Interrupt Controller (IC). Handling the TC interrupt requires programming the IC before configuring the TC. 34.4.3 34.5 34.5.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation . The registers for channel programming are listed in Table 34-5 on page 531. 517 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.5.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 34.5.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 34-2 ”Clock Chaining Selection”. Each channel can independently select an internal or external clock source for its counter: • • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 34-3 ”Clock Selection” Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock 518 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 34-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TIOA1 TIOA2 XC0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 TIOA0 TCLK0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 TIOA0 TIOA2 XC0 = TCLK2 XC1 XC2 = TCLK2 TIOB1 TIOA1 SYNC TC2XC2S Timer/Counter Channel 2 XC0 = TCLK0 TIOA2 TCLK2 TIOA0 TIOA1 XC1 = TCLK1 XC2 TIOB2 SYNC Figure 34-3. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 519 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.5.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 34-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. • Figure 34-4. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 34.5.5 TC Operating Modes Each channel can independently operate in two different modes: • • Capture Mode provides measurement on signals. Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 34.5.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. 520 AT91SAM9G10 6462A–ATARM–03-Jun-09 Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. The following triggers are common to both modes: • • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. • The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. 34.5.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 34-5 shows the configuration of the TC channel when programmed in Capture Mode. 34.5.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 34.5.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. 521 AT91SAM9G10 6462A–ATARM–03-Jun-09 522 TCCLKS CLKI CLKSTA CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 Q Q R S R S Figure 34-5. Capture Mode TIMER_CLOCK5 XC0 XC1 LDBSTOP BURST LDBDIS AT91SAM9G10 Register C 1 16-bit Counter CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LDRA LDRB CPCTRG Capture Register A SWTRG Capture Register B Compare RC = CPCS LOVRS LDRAS LDRBS ETRGS COVFS TC1_SR XC2 SYNC MTIOB TIOB MTIOA If RA is not loaded or RB is Loaded Edge Detector If RA is Loaded Edge Detector TC1_IMR TIOA Timer/Counter Channel 6462A–ATARM–03-Jun-09 INT 34.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 34-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 34.5.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 523 AT91SAM9G10 6462A–ATARM–03-Jun-09 BURST Register A WAVSEL Register B Register C ASWTRG Compare RA = Compare RB = Compare RC = 1 16-bit Counter CLK RESET OVF SWTRG BCPC Trig BCPB WAVSEL EEVT BEEVT EEVTEDG ENETRG Edge Detector CPCS CPAS CPBS ETRGS COVFS TC1_SR MTIOB SYNC Output Controller TIOB TC1_IMR BSWTRG Timer/Counter Channel INT Output Controller 524 TCCLKS CLKSTA ACPC CLKI CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 Figure 34-6. Waveform Mode TIMER_CLOCK3 TIMER_CLOCK4 CPCDIS Q Q R CPCSTOP AEEVT S R ACPA MTIOA TIMER_CLOCK5 S AT91SAM9G10 TIOA TIOB XC0 XC1 XC2 6462A–ATARM–03-Jun-09 34.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 34-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 34-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 34-7. WAVSEL= 00 without trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 525 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 34-8. WAVSEL= 00 with trigger Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 34.5.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 34-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 34-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 34-9. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 526 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 34-10. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 34.5.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 34-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 34-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 527 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 34-11. WAVSEL = 01 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 34-12. WAVSEL = 01 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 34.5.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 34-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 34-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 528 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 34-13. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 34-14. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 529 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.5.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 34.5.13 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 530 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6 Timer Counter (TC) User Interface Register Mapping Offset(1) Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Block Control Register Block Mode Register Reserved Reserved Reserved – – – TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR TC_BCR TC_BMR Read-only Read-write(2) Read-write(2) Read-write Read-only Write-only Write-only Read-only Write-only Read-write 0 0 0 0 0 – – 0 – 0 Name TC_CCR TC_CMR Access Write-only Read-write Reset – 0 Table 34-5. 0x00 + channel * 0x40 + 0x00 0x00 + channel * 0x40 + 0x04 0x00 + channel * 0x40 + 0x08 0x00 + channel * 0x40 + 0x0C 0x00 + channel * 0x40 + 0x10 0x00 + channel * 0x40 + 0x14 0x00 + channel * 0x40 + 0x18 0x00 + channel * 0x40 + 0x1C 0x00 + channel * 0x40 + 0x20 0x00 + channel * 0x40 + 0x24 0x00 + channel * 0x40 + 0x28 0x00 + channel * 0x40 + 0x2C 0xC0 0xC4 0xD8 0xE4 0xFC Notes: 2. Read-only if WAVE = 0 1. Channel index ranges from 0 to 2. 531 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.1 Name: Address: Access: 31 – 23 – 15 – 7 – TC Block Control Register TC_BCR 0xFFFA00C0 Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 SYNC • SYNC: Synchro Command 0 = no effect. 1 = asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 532 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.2 Name: Address: Access: 31 – 23 – 15 – 7 – TC Block Mode Register TC_BMR 0xFFFA00C4 Read-write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 TC2XC2S 28 – 20 – 12 – 4 27 – 19 – 11 – 3 TC1XC1S 26 – 18 – 10 – 2 25 – 17 – 9 – 1 TC0XC0S 24 – 16 – 8 – 0 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 533 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.3 Name: TC Channel Control Register TC_CCRx [x=0..2] 0xFFFA0000 (0)[0], 0xFFFA0040 (0)[1], 0xFFFA0080 (0)[2] Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SWTRG 25 – 17 – 9 – 1 CLKDIS 24 – 16 – 8 – 0 CLKEN Addresses: Access: 31 – 23 – 15 – 7 – • CLKEN: Counter Clock Enable Command 0 = no effect. 1 = enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = no effect. 1 = disables the clock. • SWTRG: Software Trigger Command 0 = no effect. 1 = a software trigger is performed: the counter is reset and the clock is started. 534 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.4 Name: TC Channel Mode Register: Capture Mode TC_CMRx [x=0..2] (WAVE = 0) 0xFFFA0004 (0)[0], 0xFFFA0044 (0)[1], 0xFFFA0084 (0)[2] Read-write 30 – 22 – 14 CPCTRG 6 LDBSTOP 29 – 21 – 13 – 5 BURST 28 – 20 – 12 – 4 11 – 3 CLKI 27 – 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 – 18 25 – 17 LDRA 8 24 – 16 Addresses: Access: 31 – 23 – 15 WAVE 7 LDBDIS • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • LDBSTOP: Counter Clock Stopped with RB Loading 0 = counter clock is not stopped when RB loading occurs. 1 = counter clock is stopped when RB loading occurs. 535 AT91SAM9G10 6462A–ATARM–03-Jun-09 • LDBDIS: Counter Clock Disable with RB Loading 0 = counter clock is not disabled when RB loading occurs. 1 = counter clock is disabled when RB loading occurs. • ETRGEDG: External Trigger Edge Selection ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • LDRB: RB Loading Selection LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA 536 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.5 Name: TC Channel Mode Register: Waveform Mode TC_CMRx [x=0..2] (WAVE = 1) 0xFFFA0004 (0)[0], 0xFFFA0044 (0)[1], 0xFFFA0084 (0)[2] Read-write 30 BSWTRG 29 BEEVT 22 ASWTRG 21 AEEVT 14 WAVSEL 6 CPCSTOP 5 BURST 13 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24 Addresses: Access: 31 23 15 WAVE 7 CPCDIS • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = counter is incremented on rising edge of the clock. 1 = counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • CPCSTOP: Counter Clock Stopped with RC Compare 0 = counter clock is not stopped when counter reaches RC. 1 = counter clock is stopped when counter reaches RC. 537 AT91SAM9G10 6462A–ATARM–03-Jun-09 • CPCDIS: Counter Clock Disable with RC Compare 0 = counter clock is not disabled when counter reaches RC. 1 = counter clock is disabled when counter reaches RC. • EEVTEDG: External Event Edge Selection EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • EEVT: External Event Selection EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input (1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • ENETRG: External Event Trigger Enable 0 = the external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = the external event resets the counter and starts the counter clock. • WAVSEL: Waveform Selection WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare • WAVE 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. 538 AT91SAM9G10 6462A–ATARM–03-Jun-09 • ACPA: RA Compare Effect on TIOA ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle • ACPC: RC Compare Effect on TIOA ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle • AEEVT: External Event Effect on TIOA AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle • BCPB: RB Compare Effect on TIOB BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle 539 AT91SAM9G10 6462A–ATARM–03-Jun-09 • BCPC: RC Compare Effect on TIOB BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle • BEEVT: External Event Effect on TIOB BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle 540 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.6 Name: TC Counter Value Register TC_CVx [x=0..2] 0xFFFA0010 (0)[0], 0xFFFA0050 (0)[1], 0xFFFA0090 (0)[2] Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CV 7 6 5 4 CV 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 • CV: Counter Value CV contains the counter value in real time. 34.6.7 Name: TC Register A TC_RAx [x=0..2] 0xFFFA0014 (0)[0], 0xFFFA0054 (0)[1], 0xFFFA0094 (0)[2] Read-only if WAVE = 0, Read-write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RA 7 6 5 4 RA 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 • RA: Register A RA contains the Register A value in real time. 541 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.8 Name: TC Register B TC_RBx [x=0..2] 0xFFFA0018 (0)[0], 0xFFFA0058 (0)[1], 0xFFFA0098 (0)[2] Read-only if WAVE = 0, Read-write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RB 7 6 5 4 RB 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 • RB: Register B RB contains the Register B value in real time. 34.6.9 Name: TC Register C TC_RCx [x=0..2] 0xFFFA001C (0)[0], 0xFFFA005C (0)[1], 0xFFFA009C (0)[2] Read-write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RC 7 6 5 4 RC 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Addresses: Access: 31 – 23 – 15 • RC: Register C RC contains the Register C value in real time. 542 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.10 Name: TC Status Register TC_SRx [x=0..2] 0xFFFA0020 (0)[0], 0xFFFA0060 (0)[1], 0xFFFA00A0 (0)[2] Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 MTIOB 10 – 2 CPAS 25 – 17 MTIOA 9 – 1 LOVRS 24 – 16 CLKSTA 8 – 0 COVFS Addresses: Access: 31 – 23 – 15 – 7 ETRGS • COVFS: Counter Overflow Status 0 = no counter overflow has occurred since the last read of the Status Register. 1 = a counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. • CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. • LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. 543 AT91SAM9G10 6462A–ATARM–03-Jun-09 • ETRGS: External Trigger Status 0 = external trigger has not occurred since the last read of the Status Register. 1 = external trigger has occurred since the last read of the Status Register. • CLKSTA: Clock Enabling Status 0 = clock is disabled. 1 = clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 544 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.11 Name: TC Interrupt Enable Register TC_IERx [x=0..2] 0xFFFA0024 (0)[0], 0xFFFA0064 (0)[1], 0xFFFA00A4 (0)[2] Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS Addresses: Access: 31 – 23 – 15 – 7 ETRGS • COVFS: Counter Overflow 0 = no effect. 1 = enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = no effect. 1 = enables the Load Overrun Interrupt. • CPAS: RA Compare 0 = no effect. 1 = enables the RA Compare Interrupt. • CPBS: RB Compare 0 = no effect. 1 = enables the RB Compare Interrupt. • CPCS: RC Compare 0 = no effect. 1 = enables the RC Compare Interrupt. • LDRAS: RA Loading 0 = no effect. 1 = enables the RA Load Interrupt. • LDRBS: RB Loading 0 = no effect. 1 = enables the RB Load Interrupt. • ETRGS: External Trigger 0 = no effect. 1 = enables the External Trigger Interrupt. 545 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.12 Name: TC Interrupt Disable Register TC_IDRx [x=0..2] 0xFFFA0028 (0)[0], 0xFFFA0068 (0)[1], 0xFFFA00A8 (0)[2] Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS Addresses: Access: 31 – 23 – 15 – 7 ETRGS • COVFS: Counter Overflow 0 = no effect. 1 = disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = no effect. 1 = disables the Load Overrun Interrupt (if WAVE = 0). • CPAS: RA Compare 0 = no effect. 1 = disables the RA Compare Interrupt (if WAVE = 1). • CPBS: RB Compare 0 = no effect. 1 = disables the RB Compare Interrupt (if WAVE = 1). • CPCS: RC Compare 0 = no effect. 1 = disables the RC Compare Interrupt. • LDRAS: RA Loading 0 = no effect. 1 = disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading 0 = no effect. 1 = disables the RB Load Interrupt (if WAVE = 0). • ETRGS: External Trigger 0 = no effect. 1 = disables the External Trigger Interrupt. 546 AT91SAM9G10 6462A–ATARM–03-Jun-09 34.6.13 Name: TC Interrupt Mask Register TC_IMRx [x=0..2] 0xFFFA002C (0)[0], 0xFFFA006C (0)[1], 0xFFFA00AC (0)[2] Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS Addresses: Access: 31 – 23 – 15 – 7 ETRGS • COVFS: Counter Overflow 0 = the Counter Overflow Interrupt is disabled. 1 = the Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0 = the Load Overrun Interrupt is disabled. 1 = the Load Overrun Interrupt is enabled. • CPAS: RA Compare 0 = the RA Compare Interrupt is disabled. 1 = the RA Compare Interrupt is enabled. • CPBS: RB Compare 0 = the RB Compare Interrupt is disabled. 1 = the RB Compare Interrupt is enabled. • CPCS: RC Compare 0 = the RC Compare Interrupt is disabled. 1 = the RC Compare Interrupt is enabled. • LDRAS: RA Loading 0 = the Load RA Interrupt is disabled. 1 = the Load RA Interrupt is enabled. • LDRBS: RB Loading 0 = the Load RB Interrupt is disabled. 1 = the Load RB Interrupt is enabled. • ETRGS: External Trigger 0 = the External Trigger Interrupt is disabled. 1 = the External Trigger Interrupt is enabled. 547 AT91SAM9G10 6462A–ATARM–03-Jun-09 548 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 35. MultiMediaCard Interface (MCI) 35.1 Description The MultiMediaCard Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. 549 6462A–ATARM–03-Jun-09 35.2 Block Diagram Figure 35-1. Block Diagram APB Bridge HDMA APB MCCK (1) MCCDA MCI Interface PMC MCK PIO (1) MCDA0 (1) MCDA1 MCDA2 MCDA3 (1) (1) (1) MCDA4 (1) MCDA5 (1) MCDA6 (1) Interrupt Control MCDA7 (1) MCI Interrupt Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. 550 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 35.3 Application Block Diagram Figure 35-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1234567 1 2 3 4 5 6 78 9 9 1011 1213 8 SDCard MMC 35.4 Pin Name List I/O Lines Description Pin Description Command/response Clock Data 0..3 of Slot A Type(1) I/O/PP/OD I/O I/O/PP Comments CMD of an MMC or SDCard/SDIO CLK of an MMC or SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO (2) Table 35-1. Pin Name MCCDA MCCK MCDA0 - MCDA3 Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. 551 6462A–ATARM–03-Jun-09 AT91SAM9G10 35.5 35.5.1 Product Dependencies I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. Table 35-2. I/O Lines Signal MCCDA MCCK MCDA0 MCDA1 MCDA2 MCDA3 I/O Line PA1 PA2 PA0 PA4 PA5 PA6 Peripheral B B B B B B Instance MCI MCI MCI MCI MCI MCI 35.5.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock. Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. Table 35-3. Instance MCI 35.5.3 Peripheral IDs ID 9 35.6 Bus Topology Figure 35-3. Multimedia Memory Card Bus Topology 1234567 9 1011 1213 8 The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 35-4. Pin Number 1 2 3 4 Bus Topology Name RSV CMD VSS1 VDD Type NC I/O/PP/OD S S (1) Description Not connected Command/response Supply voltage ground Supply voltage MCI Pin Name(2) (Slot z) MCCDz VSS VDD 552 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 35-4. Pin Number 5 6 7 Notes: Bus Topology Name CLK VSS2 DAT[0] Type I/O S I/O/PP (1) Description Clock Supply voltage ground Data 0 MCI Pin Name(2) (Slot z) MCCK VSS MCDz0 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. Figure 35-4. MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK 1234567 1234567 1234567 9 1011 1213 8 9 1011 1213 8 9 1011 1213 8 MMC1 MMC2 MMC3 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. Figure 35-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 35-5. Table 35-5. Pin Number 1 2 3 4 5 6 SD Memory Card Bus Signals Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 Type (1) Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground MCI Pin Name(2) (Slot z) MCDz3 MCCDz VSS VDD MCCK VSS I/O/PP PP S S I/O S 553 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 35-5. Pin Number 7 8 9 Notes: SD Memory Card Bus Signals Name DAT[0] DAT[1] DAT[2] Type (1) Description Data line Bit 0 Data line Bit 1 or Interrupt Data line Bit 2 MCI Pin Name(2) (Slot z) MCDz0 MCDz1 MCDz2 I/O/PP I/O/PP I/O/PP 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy. Figure 35-6. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 SD CARD Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 35.7 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. • Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. • Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 35-6 on page 555. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present 554 6462A–ATARM–03-Jun-09 9 AT91SAM9G10 in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined: • Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See “Data Transfer Operation” on page 557.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 35.7.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping the MCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC E Z NID Cycles ****** Z S T CID Content Z Z Z The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 35-6 and Table 35-7. Table 35-6. CMD Index CMD2 ALL_SEND_CID Command Description Type bcr Argument [31:0] stuff bits Resp R2 Abbreviation ALL_SEND_CID Command Description Asks all cards to send their CID numbers on the CMD line Note: bcr means broadcast command with response. 555 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 35-7. Field Fields and Values for MCI_CMDR Command Register Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) 0 (not a special command) CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) IOSPCMD (SDIO special command) The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • Fill the argument register (MCI_ARGR) with the command argument. • Set the command register (MCI_CMDR) (see Table 35-7). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. 556 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 35-7. Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? Read response if required RETURN ERROR(1) RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). 35.7.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the mode register MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block. Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes. 557 6462A–ATARM–03-Jun-09 AT91SAM9G10 Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (MCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 35.7.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 35-8), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. 558 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 35-8. Read Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) No Read with HDMA Yes Reset the DMAEN bit MCI_DMA &= ~DMAEN Set the block length (in bytes) MCI_MR |= (BlockLenght Data IN transaction • Data OUT transaction > Data OUT transaction Interrupt IN Transfer (device toward host) Interrupt OUT Transfer (host toward device) Isochronous IN Transfer(2) (device toward host) Isochronous OUT Transfer(2) (host toward device) Bulk IN Transfer (device toward host) Bulk OUT Transfer (host toward device) Notes: 1. Control transfer must use endpoints with no ping-pong attributes. 2. Isochronous transfers must use endpoints with ping-pong attributes. 3. Control transfers can be aborted using a stall handshake. A status transaction is a special type of host-to-device transaction used only in a control transfer. The control transfer must be performed using endpoints with no ping-pong attributes. According to the control sequence (read or write), the USB device sends or receives a status transaction. 596 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 37-4. Control Read and Write Sequences Setup Stage Data Stage Status Stage Control Read Setup TX Data OUT TX Data OUT TX Status IN TX Setup Stage Data Stage Status Stage Control Write Setup TX Data IN TX Data IN TX Status OUT TX Setup Stage Status Stage No Data Control Setup TX Status IN TX Notes: 1. During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0, for more information on the protocol layer. 2. During the Status OUT stage, the host emits a zero length packet to the device (Data OUT transaction with no data). 37.5.2 37.5.2.1 Handling Transactions with USB V2.0 Device Peripheral Setup Transaction Setup is a special type of host-to-device transaction used during control transfers. Control transfers must be performed using endpoints with no ping-pong attributes. A setup transaction needs to be handled as soon as possible by the firmware. It is used to transmit requests from the host to the device. These requests are then handled by the USB device and may require more arguments. The arguments are sent to the device by a Data OUT transaction which follows the setup transaction. These requests may also return data. The data is carried out to the host by the next Data IN transaction which follows the setup transaction. A status transaction ends the control transfer. When a setup transfer is received by the USB endpoint: • The USB device automatically acknowledges the setup packet • RXSETUP is set in the UDP_CSRx register • An endpoint interrupt is generated while the RXSETUP is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. Thus, firmware must detect the RXSETUP polling the UDP_CSRx or catching an interrupt, read the setup packet in the FIFO, then clear the RXSETUP. RXSETUP cannot be cleared before the setup packet has been read in the FIFO. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the setup packet in the FIFO. 597 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 37-5. Setup Transaction Followed by a Data OUT Transaction Setup Received Setup Handled by Firmware Data Out Received USB Bus Packets Setup PID Data Setup ACK PID Data OUT PID Data OUT NAK PID Data OUT PID Data OUT ACK PID RXSETUP Flag Interrupt Pending Set by USB Device Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) FIFO (DPR) Content XX Data Setup XX Data OUT 37.5.2.2 Data IN Transaction Data IN transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the device to the host. Data IN transactions in isochronous transfer must be done using endpoints with ping-pong attributes. Using Endpoints Without Ping-pong Attributes To perform a Data IN transaction using a non ping-pong endpoint: 1. The application checks if it is possible to write in the FIFO by polling TXPKTRDY in the endpoint’s UDP_CSRx register (TXPKTRDY must be cleared). 2. The application writes the first packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 3. The application notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. The application is notified that the endpoint’s FIFO has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register has been set. Then an interrupt for the corresponding endpoint is pending while TXCOMP is set. 5. The microcontroller writes the second packet of data to be sent in the endpoint’s FIFO, writing zero or more byte values in the endpoint’s UDP_FDRx register, 6. The microcontroller notifies the USB peripheral it has finished by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 7. The application clears the TXCOMP in the endpoint’s UDP_CSRx. After the last packet has been sent, the application must clear TXCOMP once this has been set. TXCOMP is set by the USB device when it has received an ACK PID signal for the Data IN packet. An interrupt is pending while TXCOMP is set. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. Note: Refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0, for more information on the Data IN protocol layer. 37.5.2.3 598 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 37-6. Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX Microcontroller Load Data in FIFO Data is Sent on USB Bus USB Bus Packets Data IN PID Data IN 1 ACK PID Data IN PID NAK PID Data IN PID Data IN 2 ACK PID TXPKTRDY Flag (UDP_CSRx) Set by the firmware Cleared by Hw Set by the firmware Cleared by Hw Interrupt Pending Payload in FIFO Cleared by Firmware DPR access by the firmware FIFO (DPR) Content Data IN 1 Load In Progress DPR access by the hardware Data IN 2 Cleared by Firmware Interrupt Pending TXCOMP Flag (UDP_CSRx) 37.5.2.4 Using Endpoints With Ping-pong Attribute The use of an endpoint with ping-pong attributes is necessary during isochronous transfer. This also allows handling the maximum bandwidth defined in the USB specification during bulk transfer. To be able to guarantee a constant or the maximum bandwidth, the microcontroller must prepare the next data payload to be sent while the current one is being sent by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 37-7. Bank Swapping Data IN Transfer for Ping-pong Endpoints Microcontroller Write Bank 0 Endpoint 1 USB Device Read USB Bus 1st Data Payload Read and Write at the Same Time 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Bank 0 Endpoint 1 Data IN Packet 1st Data Payload Data IN Packet 2nd Data Payload Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data IN transactions: 599 AT91SAM9G10 6462A–ATARM–03-Jun-09 1. The microcontroller checks if it is possible to write in the FIFO by polling TXPKTRDY to be cleared in the endpoint’s UDP_CSRx register. 2. The microcontroller writes the first data payload to be sent in the FIFO (Bank 0), writing zero or more byte values in the endpoint’s UDP_FDRx register. 3. The microcontroller notifies the USB peripheral it has finished writing in Bank 0 of the FIFO by setting the TXPKTRDY in the endpoint’s UDP_CSRx register. 4. Without waiting for TXPKTRDY to be cleared, the microcontroller writes the second data payload to be sent in the FIFO (Bank 1), writing zero or more byte values in the endpoint’s UDP_FDRx register. 5. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set. 6. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx register. 7. At this step, Bank 0 is available and the microcontroller can prepare a third data payload to be sent. Figure 37-8. Data IN Transfer for Ping-pong Endpoint Microcontroller Load Data IN Bank 0 Microcontroller Load Data IN Bank 1 USB Device Send Bank 0 Microcontroller Load Data IN Bank 0 USB Device Send Bank 1 USB Bus Packets Data IN PID Data IN ACK PID Data IN PID Data IN ACK PID TXPKTRDY Flag (UDP_MCSRx) Set by Firmware, Data Payload Written in FIFO Bank 0 TXCOMP Flag (UDP_CSRx) Cleared by USB Device, Data Payload Fully Transmitted Set by USB Device Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by USB Device Interrupt Cleared by Firmware FIFO (DPR) Written by Microcontroller Bank 0 Read by USB Device Written by Microcontroller FIFO (DPR) Bank 1 Written by Microcontroller Read by USB Device Warning: There is software critical path due to the fact that once the second bank is filled, the driver has to wait for TX_COMP to set TX_PKTRDY. If the delay between receiving TX_COMP is set and TX_PKTRDY is set too long, some Data IN packets may be NACKed, reducing the bandwidth. Warning: TX_COMP must be cleared after TX_PKTRDY has been set. 600 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.5.2.5 Data OUT Transaction Data OUT transactions are used in control, isochronous, bulk and interrupt transfers and conduct the transfer of data from the host to the device. Data OUT transactions in isochronous transfers must be done using endpoints with ping-pong attributes. Data OUT Transaction Without Ping-pong Attributes To perform a Data OUT transaction, using a non ping-pong endpoint: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. While the FIFO associated to this endpoint is being used by the microcontroller, a NAK PID is returned to the host. Once the FIFO is available, data are written to the FIFO by the USB device and an ACK is automatically carried out to the host. 3. The microcontroller is notified that the USB device has received a data payload polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 4. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 5. The microcontroller carries out data received from the endpoint’s memory to its memory. Data received is available by reading the endpoint’s UDP_FDRx register. 6. The microcontroller notifies the USB device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 7. A new Data OUT packet can be accepted by the USB device. 37.5.2.6 Figure 37-9. Data OUT Transfer for Non Ping-pong Endpoints Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT2 PID Data OUT2 NAK PID Data OUT PID Data OUT2 ACK PID RX_DATA_BK0 (UDP_CSRx) Interrupt Pending Set by USB Device Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by USB Device FIFO (DPR) Content Data OUT 1 Written by USB Device Data OUT 1 Microcontroller Read An interrupt is pending while the flag RX_DATA_BK0 is set. Memory transfer between the USB device, the FIFO and microcontroller memory can not be done after RX_DATA_BK0 has been cleared. Otherwise, the USB device would accept the next Data OUT transfer and overwrite the current Data OUT packet in the FIFO. 37.5.2.7 Using Endpoints With Ping-pong Attributes During isochronous transfer, using an endpoint with ping-pong attributes is obligatory. To be able to guarantee a constant bandwidth, the microcontroller must read the previous data pay- 601 AT91SAM9G10 6462A–ATARM–03-Jun-09 load sent by the host, while the current data payload is received by the USB device. Thus two banks of memory are used. While one is available for the microcontroller, the other one is locked by the USB device. Figure 37-10. Bank Swapping in Data OUT Transfers for Ping-pong Endpoints Microcontroller Write USB Device Read Bank 0 Endpoint 1 Data IN Packet 1st Data Payload USB Bus Write and Read at the Same Time 1st Data Payload Bank 0 Endpoint 1 2nd Data Payload Bank 1 Endpoint 1 3rd Data Payload Bank 0 Endpoint 1 Bank 1 Endpoint 1 Data IN Packet nd Data Payload 2 Bank 0 Endpoint 1 Data IN Packet 3rd Data Payload When using a ping-pong endpoint, the following procedures are required to perform Data OUT transactions: 1. The host generates a Data OUT packet. 2. This packet is received by the USB device endpoint. It is written in the endpoint’s FIFO Bank 0. 3. The USB device sends an ACK PID packet to the host. The host can immediately send a second Data OUT packet. It is accepted by the device and copied to FIFO Bank 1. 4. The microcontroller is notified that the USB device has received a data payload, polling RX_DATA_BK0 in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK0 is set. 5. The number of bytes available in the FIFO is made available by reading RXBYTECNT in the endpoint’s UDP_CSRx register. 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9. If a second Data OUT packet has been received, the microcontroller is notified by the flag RX_DATA_BK1 set in the endpoint’s UDP_CSRx register. An interrupt is pending for this endpoint while RX_DATA_BK1 is set. 10. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is available by reading the endpoint’s UDP_FDRx register. 602 AT91SAM9G10 6462A–ATARM–03-Jun-09 11. The microcontroller notifies the USB device it has finished the transfer by clearing RX_DATA_BK1 in the endpoint’s UDP_CSRx register. 12. A fourth Data OUT packet can be accepted by the USB device and copied in the FIFO Bank 0. Figure 37-11. Data OUT Transfer for Ping-pong Endpoint Host Sends First Data Payload Microcontroller Reads Data 1 in Bank 0, Host Sends Second Data Payload Microcontroller Reads Data2 in Bank 1, Host Sends Third Data Payload USB Bus Packets Data OUT PID Data OUT 1 ACK PID Data OUT PID Data OUT 2 ACK PID Data OUT PID Data OUT 3 A P RX_DATA_BK0 Flag (UDP_CSRx) Interrupt Pending Set by USB Device, Data Payload Written in FIFO Endpoint Bank 0 Cleared by Firmware RX_DATA_BK1 Flag (UDP_CSRx) Set by USB Device, Data Payload Written in FIFO Endpoint Bank 1 Cleared by Firmware Interrupt Pending FIFO (DPR) Bank 0 Data OUT1 Write by USB Device Data OUT 1 Read By Microcontroller Data OUT 3 Write In Progress FIFO (DPR) Bank 1 Data OUT 2 Write by USB Device Data OUT 2 Read By Microcontroller Note: An interrupt is pending while the RX_DATA_BK0 or RX_DATA_BK1 flag is set. Warning: When RX_DATA_BK0 and RX_DATA_BK1 are both set, there is no way to determine which one to clear first. Thus the software must keep an internal counter to be sure to clear alternatively RX_DATA_BK0 then RX_DATA_BK1. This situation may occur when the software application is busy elsewhere and the two banks are filled by the USB host. Once the application comes back to the USB driver, the two flags are set. 37.5.2.8 Stall Handshake A stall handshake can be used in one of two distinct occasions. (For more information on the stall handshake, refer to Chapter 8 of the Universal Serial Bus Specification, Rev 2.0.) • A functional stall is used when the halt feature associated with the endpoint is set. (Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0, for more information on the halt feature.) • To abort the current request, a protocol stall is used, but uniquely with control transfer. The following procedure generates a stall packet: 1. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register. 2. The host receives the stall packet. 603 AT91SAM9G10 6462A–ATARM–03-Jun-09 3. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt. When a setup transaction is received after a stall handshake, STALLSENT must be cleared in order to prevent interrupts due to STALLSENT being set. Figure 37-12. Stall Handshake (Data IN Transfer) USB Bus Packets Data IN PID Stall PID Cleared by Firmware FORCESTALL Set by Firmware Interrupt Pending Cleared by Firmware STALLSENT Set by USB Device Figure 37-13. Stall Handshake (Data OUT Transfer) USB Bus Packets Data OUT PID Data OUT Stall PID FORCESTALL Set by Firmware Interrupt Pending STALLSENT Set by USB Device Cleared by Firmware 604 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.5.2.9 Transmit Data Cancellation Some endpoints have dual-banks whereas some endpoints have only one bank. The procedure to cancel transmission data held in these banks is described below. To see the organization of dual-bank availablity refer to Table 37-1 ”USB Endpoint Description”. 37.5.2.10 Endpoints Without Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set. • TXPKTRDY is not set: – Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 ”UDP Reset Endpoint Register”.) • TXPKTRDY has already been set: – Clear TXPKTRDY so that no packet is ready to be sent – Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 ”UDP Reset Endpoint Register”.) 37.5.2.11 Endpoints With Dual-Banks There are two possibilities: In one case, TXPKTRDY field in UDP_CSR has already been set. In the other instance, TXPKTRDY is not set. • TXPKTRDY is not set: – Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 ”UDP Reset Endpoint Register”.) • TXPKTRDY has already been set: – Clear TXPKTRDY and read it back until actually read at 0. – Set TXPKTRDY and read it back until actually read at 1. – Clear TXPKTRDY so that no packet is ready to be sent. – Reset the endpoint to clear the FIFO (pointers). (See, Section 37.6.9 ”UDP Reset Endpoint Register”.) 605 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0. Figure 37-14. USB Device State Diagram Attached Hub Reset or Deconfigured Hub Configured Bus Inactive Powered Bus Activity Power Interruption Suspended Reset Bus Inactive Default Reset Address Assigned Bus Inactive Bus Activity Suspended Address Bus Activity Device Deconfigured Device Configured Bus Inactive Suspended Configured Bus Activity Suspended Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake up request to the host, e.g., waking up a PC by moving a USB mouse. The wake up feature is not mandatory for all devices and must be negotiated with the host. 606 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.5.3.1 Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors. Entering Attached State When no device is connected, the USB DP and DM signals are tied to GND by 15 KΩ pull-down resistors integrated in the hub downstream ports. When a device is attached to a hub downstream port, the device connects a 1.5 KΩ pull-up resistor on DP. The USB bus line goes into IDLE state, DP is pulled up by the device 1.5 KΩ resistor to 3.3V and DM is pulled down by the 15 KΩ resistor of the host. To enable integrated pullup, the UDP_PUP_ON bit in the USB_PUCR Bus Matrix register must be set. Warning: To write to the UDP_TXVC register, MCK clock must be enabled on the UDP. This is done in the Power Management Controller. After pullup connection, the device enters the powered state. In this state, the UDPCK and MCK must be enabled in the Power Management Controller. The transceiver can remain disabled. 37.5.3.2 37.5.3.3 From Powered State to Default State After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmaskable flag ENDBUSRES is set in the register UDP_ISR and an interrupt is triggered. Once the ENDBUSRES interrupt has been triggered, the device enters Default State. In this state, the UDP software must: • Enable the default endpoint, setting the EPEDS flag in the UDP_CSR[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 to the UDP_IER register. The enumeration then begins by a control transfer. • Configure the interrupt mask register which has been reset by the USB reset detection • Enable the transceiver clearing the TXVDIS flag in the UDP_TXVC register. In this state UDPCK and MCK must be enabled. Warning: Each time an ENDBUSRES interrupt is triggered, the Interrupt Mask Register and UDP_CSR registers have been reset. 37.5.3.4 From Default State to Address State After a set address standard device request, the USB host peripheral enters the address state. Warning: Before the device enters in address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDP device sets its new address once the TXCOMP flag in the UDP_CSR[0] register has been received and cleared. To move to address state, the driver software sets the FADDEN flag in the UDP_GLB_STAT register, sets its new address, and sets the FEN bit in the UDP_FADDR register. 37.5.3.5 From Address State to Configured State Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the EPEDS and EPTYPE fields in the UDP_CSRx registers and, optionally, enabling corresponding interrupts in the UDP_IER register. 607 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.5.3.6 Entering in Suspend State When a Suspend (no bus activity on the USB bus) is detected, the RXSUSP signal in the UDP_ISR register is set. This triggers an interrupt if the corresponding bit is set in the UDP_IMR register.This flag is cleared by writing to the UDP_ICR register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500uA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The USB device peripheral clocks can be switched off. Resume event is asynchronously detected. MCK and UDPCK can be switched off in the Power Management controller and the USB transceiver can be disabled by setting the TXVDIS field in the UDP_TXVC register. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. Switching off MCK for the UDP peripheral must be one of the last operations after writing to the UDP_TXVC and acknowledging the RXSUSP. 37.5.3.7 Receiving a Host Resume In suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks are disabled (however the pullup shall not be removed). Once the resume is detected on the bus, the WAKEUP signal in the UDP_ISR is set. It may generate an interrupt if the corresponding bit in the UDP_IMR register is set. This interrupt may be used to wake up the core, enable PLL and main oscillators and configure clocks. Warning: Read, write operations to the UDP registers are allowed only if MCK is enabled for the UDP peripheral. MCK for the UDP must be enabled before clearing the WAKEUP bit in the UDP_ICR register and clearing TXVDIS in the UDP_TXVC register. 37.5.3.8 Sending a Device Remote Wakeup In Suspend state it is possible to wake up the host sending an external resume. • The device must wait at least 5 ms after being entered in suspend before sending an external resume. • The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host. • The device must force a K state from 1 to 15 ms to resume the host To force a K state to the bus (DM at 3.3V and DP tied to GND), it is possible to use a transistor to connect a pullup on DM. The K state is obtained by disabling the pullup on DP and enabling the pullup on DM. This should be under the control of the application. 608 AT91SAM9G10 6462A–ATARM–03-Jun-09 Figure 37-15. Board Schematic to Drive a K State 3V3 PIO 0: Force Wake UP (K State) 1: Normal Mode 1.5 K DM 609 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6 USB Device Port (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registersincluding the UDP_TXVC register. Table 37-5. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C Register Mapping Register Frame Number Register Global State Register Function Address Register Reserved Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register Interrupt Clear Register Reserved Reset Endpoint Register Reserved Endpoint Control and Status Register Endpoint FIFO Data Register Reserved Transceiver Control Register Reserved Name UDP_FRM_NUM UDP_GLB_STAT UDP_FADDR – UDP_IER UDP_IDR UDP_IMR UDP_ISR UDP_ICR – UDP_RST_EP – UDP_CSR UDP_FDR – UDP_TXVC – (2) Access Read-only Read-write Read-write – Write-only Write-only Read-only Read-only Write-only – Read-write – Read-write Read-write – Read-write – Reset 0x0000_0000 0x0000_0010 0x0000_0100 – 0x0000_1200 –(1) – 0x0000_0000 – 0x0000_0000 0x0000_0000 – 0x0000_0000 – 0x030 + 0x4 * ( ept_num - 1 ) 0x050 + 0x4 * ( ept_num - 1 ) 0x070 0x074 0x078 - 0xFC Notes: 1. Reset values are not defined for UDP_ISR. 2. See Warning above the ”Register Mapping” on this page. 610 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.1 UDP Frame Number Register Register Name: UDP_FRM_NUM Address: Access Type: 31 --23 – 15 – 7 30 --22 – 14 – 6 0xFFFA4000 Read-only 29 --21 – 13 – 5 28 --20 – 12 – 4 FRM_NUM 27 --19 – 11 – 3 26 --18 – 10 25 --17 FRM_OK 9 FRM_NUM 1 24 --16 FRM_ERR 8 2 0 • FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet). • FRM_ERR: Frame Error This bit is set at SOF_EOP when the SOF packet is received containing an error. This bit is reset upon receipt of SOF_PID. • FRM_OK: Frame OK This bit is set at SOF_EOP when the SOF packet is received without any error. This bit is reset upon receipt of SOF_PID (Packet Identification). In the Interrupt Status Register, the SOF interrupt is updated upon receiving SOF_PID. This bit is set without waiting for EOP. Note: In the 8-bit Register Interface, FRM_OK is bit 4 of FRM_NUM_H and FRM_ERR is bit 3 of FRM_NUM_L. 611 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.2 UDP Global State Register Register Name: UDP_GLB_STAT Address: Access Type: 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 0xFFFA4004 Read-write 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 CONFG 24 – 16 – 8 – 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. • FADDEN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = No effect, only a reset can bring back a device to the default state. 1 = Sets device in address state. This occurs after a successful Set Address request. Beforehand, the UDP_FADDR register must have been initialized with Set Address parameters. Set Address must complete the Status Stage before setting FADDEN. Refer to chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. • CONFG: Configured Read: 0 = Device is not in configured state. 1 = Device is in configured state. Write: 0 = Sets device in a non configured state 1 = Sets device in configured state. The device is set in configured state when it is in address state and receives a successful Set Configuration request. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev. 2.0 for more details. 612 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.3 UDP Function Address Register Register Name: UDP_FADDR Address: Access Type: 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 0xFFFA4008 Read-write 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 FADD 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 FEN 0 • FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. After power up or reset, the function address value is set to 0. • FEN: Function Enable Read: 0 = Function endpoint disabled. 1 = Function endpoint enabled. Write: 0 = Disables function endpoint. 1 = Default value. The Function Enable bit (FEN) allows the microcontroller to enable or disable the function endpoints. The microcontroller sets this bit after receipt of a reset from the host. Once this bit is set, the USB device is able to accept and transfer data packets from and to the host. 613 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.4 UDP Interrupt Enable Register Register Name: UDP_IER Address: Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 0xFFFA4010 Write-only 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 – 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT • EP0INT: Enable Endpoint 0 Interrupt • EP1INT: Enable Endpoint 1 Interrupt • EP2INT: Enable Endpoint 2Interrupt • EP3INT: Enable Endpoint 3 Interrupt • EP4INT: Enable Endpoint 4 Interrupt • EP5INT: Enable Endpoint 5 Interrupt 0 = No effect. 1 = Enables corresponding Endpoint Interrupt. • RXSUSP: Enable UDP Suspend Interrupt 0 = No effect. 1 = Enables UDP Suspend Interrupt. • RXRSM: Enable UDP Resume Interrupt 0 = No effect. 1 = Enables UDP Resume Interrupt • SOFINT: Enable Start Of Frame Interrupt 0 = No effect. 1 = Enables Start Of Frame Interrupt. • WAKEUP: Enable UDP bus Wakeup Interrupt 0 = No effect. 1 = Enables USB bus Interrupt. 614 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.5 UDP Interrupt Disable Register Register Name: UDP_IDR Address: Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 0xFFFA4014 Write-only 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 – 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 – 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT • EP0INT: Disable Endpoint 0 Interrupt • EP1INT: Disable Endpoint 1 Interrupt • EP2INT: Disable Endpoint 2 Interrupt • EP3INT: Disable Endpoint 3 Interrupt • EP4INT: Disable Endpoint 4 Interrupt • EP5INT: Disable Endpoint 5 Interrupt 0 = No effect. 1 = Disables corresponding Endpoint Interrupt. • RXSUSP: Disable UDP Suspend Interrupt 0 = No effect. 1 = Disables UDP Suspend Interrupt. • RXRSM: Disable UDP Resume Interrupt 0 = No effect. 1 = Disables UDP Resume Interrupt. • SOFINT: Disable Start Of Frame Interrupt 0 = No effect. 1 = Disables Start Of Frame Interrupt • WAKEUP: Disable USB Bus Interrupt 0 = No effect. 1 = Disables USB Bus Wakeup Interrupt. 615 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.6 UDP Interrupt Mask Register Register Name: UDP_IMR Address: Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 0xFFFA4018 Read-only 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 BIT12 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 – 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT • EP0INT: Mask Endpoint 0 Interrupt • EP1INT: Mask Endpoint 1 Interrupt • EP2INT: Mask Endpoint 2 Interrupt • EP3INT: Mask Endpoint 3 Interrupt • EP4INT: Mask Endpoint 4 Interrupt • EP5INT: Mask Endpoint 5 Interrupt 0 = Corresponding Endpoint Interrupt is disabled. 1 = Corresponding Endpoint Interrupt is enabled. • RXSUSP: Mask UDP Suspend Interrupt 0 = UDP Suspend Interrupt is disabled. 1 = UDP Suspend Interrupt is enabled. • RXRSM: Mask UDP Resume Interrupt. 0 = UDP Resume Interrupt is disabled. 1 = UDP Resume Interrupt is enabled. • SOFINT: Mask Start Of Frame Interrupt 0 = Start of Frame Interrupt is disabled. 1 = Start of Frame Interrupt is enabled. • BIT12: UDP_IMR Bit 12 Bit 12 of UDP_IMR cannot be masked and is always read at 1. 616 AT91SAM9G10 6462A–ATARM–03-Jun-09 • WAKEUP: USB Bus WAKEUP Interrupt 0 = USB Bus Wakeup Interrupt is disabled. 1 = USB Bus Wakeup Interrupt is enabled. Note: When the USB block is in suspend mode, the application may power down the USB logic. In this case, any USB HOST resume request that is made must be taken into account and, thus, the reset value of the RXRSM bit of the register UDP_IMR is enabled. 617 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.7 UDP Interrupt Status Register Register Name: UDP_ISR Address: Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 0xFFFA401C Read-only 29 – 21 – 13 WAKEUP 5 EP5INT 28 – 20 – 12 ENDBUSRES 4 EP4INT 27 – 19 – 11 SOFINT 3 EP3INT 26 – 18 – 10 – 2 EP2INT 25 – 17 – 9 RXRSM 1 EP1INT 24 – 16 – 8 RXSUSP 0 EP0INT • EP0INT: Endpoint 0 Interrupt Status • EP1INT: Endpoint 1 Interrupt Status • EP2INT: Endpoint 2 Interrupt Status • EP3INT: Endpoint 3 Interrupt Status • EP4INT: Endpoint 4 Interrupt Status • EP5INT: Endpoint 5 Interrupt Status 0 = No Endpoint0 Interrupt pending. 1 = Endpoint0 Interrupt has been raised. Several signals can generate this interrupt. The reason can be found by reading UDP_CSR0: RXSETUP set to 1 RX_DATA_BK0 set to 1 RX_DATA_BK1 set to 1 TXCOMP set to 1 STALLSENT set to 1 EP0INT is a sticky bit. Interrupt remains valid until EP0INT is cleared by writing in the corresponding UDP_CSR0 bit. • RXSUSP: UDP Suspend Interrupt Status 0 = No UDP Suspend Interrupt pending. 1 = UDP Suspend Interrupt has been raised. The USB device sets this bit when it detects no activity for 3ms. The USB device enters Suspend mode. 618 AT91SAM9G10 6462A–ATARM–03-Jun-09 • RXRSM: UDP Resume Interrupt Status 0 = No UDP Resume Interrupt pending. 1 =UDP Resume Interrupt has been raised. The USB device sets this bit when a UDP resume signal is detected at its port. After reset, the state of this bit is undefined, the application must clear this bit by setting the RXRSM flag in the UDP_ICR register. • SOFINT: Start of Frame Interrupt Status 0 = No Start of Frame Interrupt pending. 1 = Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. • ENDBUSRES: End of BUS Reset Interrupt Status 0 = No End of Bus Reset Interrupt pending. 1 = End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence. The USB device must prepare to receive requests on the endpoint 0. The host starts the enumeration, then performs the configuration. • WAKEUP: UDP Resume Interrupt Status 0 = No Wakeup Interrupt pending. 1 = A Wakeup Interrupt (USB Host Sent a RESUME or RESET) occurred since the last clear. After reset the state of this bit is undefined, the application must clear this bit by setting the WAKEUP flag in the UDP_ICR register. 619 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.8 UDP Interrupt Clear Register Register Name: UDP_ICR Address: Access Type: 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 0xFFFA4020 Write-only 29 – 21 – 13 WAKEUP 5 – 28 – 20 – 12 ENDBUSRES 4 – 27 – 19 – 11 SOFINT 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 RXRSM 1 – 24 – 16 – 8 RXSUSP 0 – • RXSUSP: Clear UDP Suspend Interrupt 0 = No effect. 1 = Clears UDP Suspend Interrupt. • RXRSM: Clear UDP Resume Interrupt 0 = No effect. 1 = Clears UDP Resume Interrupt. • SOFINT: Clear Start Of Frame Interrupt 0 = No effect. 1 = Clears Start Of Frame Interrupt. • ENDBUSRES: Clear End of Bus Reset Interrupt 0 = No effect. 1 = Clears End of Bus Reset Interrupt. • WAKEUP: Clear Wakeup Interrupt 0 = No effect. 1 = Clears Wakeup Interrupt. 620 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.9 UDP Reset Endpoint Register Register Name: UDP_RST_EP Address: Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 0xFFFA4028 Read-write 29 – 21 – 13 – 5 EP5 28 – 20 – 12 – 4 EP4 27 – 19 – 11 – 3 EP3 26 – 18 – 10 – 2 EP2 25 – 17 – 9 – 1 EP1 24 – 16 – 8 – 0 EP0 • EP0: Reset Endpoint 0 • EP1: Reset Endpoint 1 • EP2: Reset Endpoint 2 • EP3: Reset Endpoint 3 • EP4: Reset Endpoint 4 • EP5: Reset Endpoint 5 This flag is used to reset the FIFO associated with the endpoint and the bit RXBYTECOUNT in the register UDP_CSRx.It also resets the data toggle to DATA0. It is useful after removing a HALT condition on a BULK endpoint. Refer to Chapter 5.8.5 in the USB Serial Bus Specification, Rev.2.0. Warning: This flag must be cleared at the end of the reset. It does not clear UDP_CSRx flags. 0 = No reset. 1 = Forces the corresponding endpoint FIF0 pointers to 0, therefore RXBYTECNT field is read at 0 in UDP_CSRx register. Reseting the endpoint is a two-step operation: 1. Set the corresponding EPx field. 2. Clear the corresponding EPx field. 621 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.10 UDP Endpoint Control and Status Register Register Name: UDP_CSRx [x = 0..5] Address: Access Type: 31 – 23 30 – 22 0xFFFA402C Read-write 29 – 21 28 – 20 RXBYTECNT 27 – 19 26 25 RXBYTECNT 17 24 18 16 15 EPEDS 7 DIR 14 – 6 RX_DATA_ BK1 13 – 5 FORCE STALL 12 – 4 TXPKTRDY 11 DTGLE 3 STALLSENT ISOERROR 10 9 EPTYPE 1 RX_DATA_ BK0 8 2 RXSETUP 0 TXCOMP WARNING: Due to synchronization between MCK and UDPCK, the software application must wait for the end of the write operation before executing another write by polling the bits which must be set/cleared. /// Bitmap for all status bits in CSR that are not effected by a value 1. #define REG_NO_EFFECT_1_ALL AT91C_UDP_RX_DATA_BK0\ | AT91C_UDP_RX_DATA_BK1\ | AT91C_UDP_STALLSENT\ | AT91C_UDP_RXSETUP\ | AT91C_UDP_TXCOMP /// Sets the specified bit(s) in the UDP_CSR register. /// \param endpoint The endpoint number of the CSR to process. /// \param flags The bitmap to set to 1. #define SET_CSR(endpoint, flags) \ {\ volatile unsigned int reg; \ reg = AT91C_BASE_UDP->UDP_CSR[endpoint] ; \ reg |= REG_NO_EFFECT_1_ALL; \ reg |= (flags); \ AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \ while ( (AT91C_BASE_UDP->UDP_CSR[endpoint] & (flags)) != (flags)); \ } /// Clears the specified bit(s) in the UDP_CSR register. /// \param endpoint The endpoint number of the CSR to process. /// \param flags The bitmap to clear to 0. #define CLEAR_CSR(endpoint, flags) \ {\ volatile unsigned int reg; \ reg = AT91C_BASE_UDP->UDP_CSR[endpoint]; \ 622 AT91SAM9G10 6462A–ATARM–03-Jun-09 reg |= REG_NO_EFFECT_1_ALL; \ reg &= ~(flags); \ AT91C_BASE_UDP->UDP_CSR[endpoint] = reg; \ while ( (AT91C_BASE_UDP->UDP_CSR[endpoint] & (flags)) == (flags)); \ } Note: In a preemptive environment, set or clear the flag and wait for a time of 1 UDPCK clock cycle and 1peripheral clock cycle. However, RX_DATA_BK0, TXPKTRDY, RX_DATA_BK1 require wait times of 3 UDPCK clock cycles and 5 peripheral clock cycles before accessing DPR. • TXCOMP: Generates an IN Packet with Data Previously Written in the DPR This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Clear the flag, clear the interrupt. 1 = No effect. Read (Set by the USB peripheral): 0 = Data IN transaction has not been acknowledged by the Host. 1 = Data IN transaction is achieved, acknowledged by the Host. After having issued a Data IN transaction setting TXPKTRDY, the device firmware waits for TXCOMP to be sure that the host has acknowledged the transaction. • RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 0. 1 = A data packet has been received, it has been stored in the FIFO's Bank 0. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to the microcontroller memory. The number of bytes received is available in RXBYTCENT field. Bank 0 FIFO values are read through the UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 0 to the USB peripheral device by clearing RX_DATA_BK0. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. • RXSETUP: Received Setup This flag generates an interrupt while it is set to one. Read: 0 = No setup packet available. 1 = A setup data packet has been sent by the host and is available in the FIFO. 623 AT91SAM9G10 6462A–ATARM–03-Jun-09 Write: 0 = Device firmware notifies the USB peripheral device that it has read the setup data in the FIFO. 1 = No effect. This flag is used to notify the USB device firmware that a valid Setup data packet has been sent by the host and successfully received by the USB device. The USB device firmware may transfer Setup data from the FIFO by reading the UDP_FDRx register to the microcontroller memory. Once a transfer has been done, RXSETUP must be cleared by the device firmware. Ensuing Data OUT transaction is not accepted while RXSETUP is set. • STALLSENT: Stall Sent (Control, Bulk Interrupt Endpoints)/ISOERROR (Isochronous Endpoints) This flag generates an interrupt while it is set to one. STALLSENT: This ends a STALL handshake. Read: 0 = The host has not acknowledged a STALL. 1 = Host has acknowledged the stall. Write: 0 = Resets the STALLSENT flag, clears the interrupt. 1 = No effect. This is mandatory for the device firmware to clear this flag. Otherwise the interrupt remains. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. ISOERROR: A CRC error has been detected in an isochronous transfer. Read: 0 = No error in the previous isochronous transfer. 1 = CRC error has been detected, data available in the FIFO are corrupted. Write: 0 = Resets the ISOERROR flag, clears the interrupt. 1 = No effect. • TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0 = There is no data to send. 1 = The data is waiting to be sent upon reception of token IN. 624 AT91SAM9G10 6462A–ATARM–03-Jun-09 Write: 0 = Can be used in the procedure to cancel transmission data. (See, Section 37.5.2.9 “Transmit Data Cancellation” on page 605) 1 = A new data payload has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host). Device firmware checks that it can write a data payload in the FIFO, checking that TXPKTRDY is cleared. Transfer to the FIFO is done by writing in the UDP_FDRx register. Once the data payload has been transferred to the FIFO, the firmware notifies the USB device setting TXPKTRDY to one. USB bus transactions can start. TXCOMP is set once the data payload has been received by the host. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. • FORCESTALL: Force Stall (used by Control, Bulk and Isochronous Endpoints) Read: 0 = Normal state. 1 = Stall state. Write: 0 = Return to normal state. 1 = Send STALL to the host. Refer to chapters 8.4.5 and 9.4.5 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the STALL handshake. Control endpoints: During the data stage and status stage, this bit indicates that the microcontroller cannot complete the request. Bulk and interrupt endpoints: This bit notifies the host that the endpoint is halted. The host acknowledges the STALL, device firmware is notified by the STALLSENT flag. • RX_DATA_BK1: Receive Data Bank 1 (only used by endpoints with ping-pong attributes) This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0 = Notifies USB device that data have been read in the FIFO’s Bank 1. 1 = To leave the read value unchanged. Read (Set by the USB peripheral): 0 = No data packet has been received in the FIFO's Bank 1. 1 = A data packet has been received, it has been stored in FIFO's Bank 1. When the device firmware has polled this bit or has been interrupted by this signal, it must transfer data from the FIFO to microcontroller memory. The number of bytes received is available in RXBYTECNT field. Bank 1 FIFO values are read through UDP_FDRx register. Once a transfer is done, the device firmware must release Bank 1 to the USB device by clearing RX_DATA_BK1. After setting or clearing this bit, a wait time of 3 UDPCK clock cycles and 3 peripheral clock cycles is required before accessing DPR. 625 AT91SAM9G10 6462A–ATARM–03-Jun-09 • DIR: Transfer Direction (only available for control endpoints) Read-write 0 = Allows Data OUT transactions in the control data stage. 1 = Enables Data IN transactions in the control data stage. Refer to Chapter 8.5.3 of the Universal Serial Bus Specification, Rev. 2.0 for more information on the control data stage. This bit must be set before UDP_CSRx/RXSETUP is cleared at the end of the setup stage. According to the request sent in the setup data packet, the data stage is either a device to host (DIR = 1) or host to device (DIR = 0) data transfer. It is not necessary to check this bit to reverse direction for the status stage. • EPTYPE[2:0]: Endpoint Type Read-write 000 001 101 010 110 011 111 Control Isochronous OUT Isochronous IN Bulk OUT Bulk IN Interrupt OUT Interrupt IN • DTGLE: Data Toggle Read-only 0 = Identifies DATA0 packet. 1 = Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. • EPEDS: Endpoint Enable Disable Read: 0 = Endpoint disabled. 1 = Endpoint enabled. Write: 0 = Disables endpoint. 1 = Enables endpoint. Control endpoints are always enabled. Reading or writing this field has no effect on control endpoints. Note: After reset, all endpoints are configured as control endpoints (zero). • RXBYTECNT[10:0]: Number of Bytes Available in the FIFO Read-only When the host sends a data packet to the device, the USB device stores the data in the FIFO and notifies the microcontroller. The microcontroller can load the data from the FIFO by reading RXBYTECENT bytes in the UDP_FDRx register. 626 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.11 UDP FIFO Data Register Register Name: UDP_FDRx [x = 0..5] Address: Access Type: 31 – 23 – 15 – 7 30 – 22 – 14 – 6 0xFFFA404C Read-write 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FIFO_DATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host). The maximum number of bytes to write is fixed by the Max Packet Size in the Standard Endpoint Descriptor. It can not be more than the physical memory size associated to the endpoint. Refer to the Universal Serial Bus Specification, Rev. 2.0 for more information. 627 AT91SAM9G10 6462A–ATARM–03-Jun-09 37.6.12 UDP Transceiver Control Register Register Name: UDP_TXVC Address: Access Type: 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 0xFFFA4074 Read-write 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 TXVDIS 0 – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register. • TXVDIS: Transceiver Disable When UDP is disabled, power consumption can be reduced significantly by disabling the embedded transceiver. This can be done by setting TXVDIS field. To enable the transceiver, TXVDIS must be cleared. • PUON: Pullup On 0: The 1.5KΩ integrated pullup on DP is disconnected. 1: The 1.5 KΩ integrated pullup on DP is connected. NOTE: If the USB pullup is not connected on DP, the user should not write in any UDP register other than the UDP_TXVC register. This is because if DP and DM are floating at 0, or pulled down, then SE0 is received by the device with the consequence of a USB Reset. 628 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 38. LCD Controller (LCDC) 38.1 Description The LCD Controller (LCDC) consists of logic for transferring LCD image data from an external display buffer to an LCD module with integrated common and segment drivers. The LCD Controller supports single and double scan monochrome and color passive STN LCD modules and single scan active TFT LCD modules. On monochrome STN displays, up to 16 gray shades are supported using a time-based dithering algorithm and Frame Rate Control (FRC) method. This method is also used in color STN displays to generate up to 4096 colors. The LCD Controller has a display input buffer (FIFO) to allow a flexible connection of the external AHB master interface, and a lookup table to allow palletized display configurations. The LCD Controller is programmable in order to support many different requirements such as resolutions up to 2048 x 2048; pixel depth (1, 2, 4, 8, 16, 24 bits per pixel); data line width (4, 8, 16 or 24 bits) and interface timing. The LCD Controller is connected to the ARM Advanced High Performance Bus (AHB) as a master for reading pixel data. However, the LCD Controller interfaces with the AHB as a slave in order to configure its registers. 629 6462A–ATARM–03-Jun-09 38.2 Block Diagram Figure 38-1. LCD Macrocell Block Diagram AHB MASTER AHB SLAVE DMA Controller SPLIT AHB IF CFG AHB SLAVE DMA Data Dvalid Dvalid CH-U Upper Push CH-L Lower Push CTRL Input Interface LCD Controller Core FIFO Configuration IF CFG AHB SLAVE SERIALIZER DATAPATH LUT Mem Interface PALETTE LUT Mem Interface FIFO Mem Interface DITHERING Control Interface FIFO MEM OUTPUT SHIFTER LUT MEM Timegen LCDD DISPLAY IF Control signals Display PWM DISPLAY IF 630 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 38.3 I/O Lines Description I/O Lines Description Description Contrast control signal Line synchronous signal (STN) or Horizontal synchronous signal (TFT) LCD clock signal (STN/TFT) Frame synchronous signal (STN) or Vertical synchronization signal (TFT) Data enable signal LCD Data Bus output Type Output Output Output Output Output Output Table 38-1. Name LCDCC LCDHSYNC LCDDOTCK LCDVSYNC LCDDEN LCDD[23:0] 38.4 38.4.1 Product Dependencies I/O Lines The pins used for interfacing the LCD Controller may be multiplexed with PIO lines. The programmer must first program the PIO Controller to assign the pins to their peripheral function. If I/O lines of the LCD Controller are not used by the application, they can be used for other purposes by the PIO Controller. Table 38-2. I/O Lines Signal LCDCC LCDDEN LCDDOTCK LCDD0 LCDD1 LCDD2 LCDD2 LCDD3 LCDD3 LCDD4 LCDD4 LCDD5 LCDD5 LCDD6 LCDD6 LCDD7 LCDD7 LCDD8 LCDD9 LCDD10 I/O Line PB4 PB3 PB2 PB5 PB6 PB4 PB7 PB5 PB8 PB6 PB9 PB7 PB10 PB8 PB11 PB9 PB12 PB13 PB14 PB10 Peripheral A A A A A B A B A B A B A B A B A A A B Instance LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC 631 6462A–ATARM–03-Jun-09 Table 38-2. LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC LCDC I/O Lines LCDD10 LCDD11 LCDD11 LCDD12 LCDD12 LCDD13 LCDD13 LCDD14 LCDD14 LCDD15 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD19 LCDD20 LCDD20 LCDD21 LCDD21 LCDD22 LCDD22 LCDD23 LCDD23 LCDHSYNC LCDVSYNC PB15 PB11 PB16 PB12 PB17 PB13 PB18 PB14 PB19 PB15 PB20 PB21 PB22 PB23 PB16 PB24 PB17 PB25 PB18 PB26 PB19 PB27 PB20 PB28 PB1 PB0 A B A B A B A B A B A B B B B B B B B B B B B B A A 38.4.2 Power Management The LCD Controller is not continuously clocked. As the LCD Controller is on the AHB bus, the clock is enabled by setting the HCKx bit in the PMC_SCER register. Interrupt Sources The LCD Controller interrupt line is connected to one of the internal sources of the Advanced Interrupt Controller. Using the LCD Controller interrupt requires prior programming of the AIC. Table 38-3. Instance LCDC 38.4.3 Peripheral IDs ID 21 632 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 38.5 Functional Description The LCD Controller consists of two main blocks (Figure 38-1 on page 630), the DMA controller and the LCD controller core (LCDC core). The DMA controller reads the display data from an external memory through a AHB master interface. The LCD controller core formats the display data. The LCD controller core continuously pumps the pixel data into the LCD module via the LCD data bus (LCDD[23:0]); this bus is timed by the LCDDOTCK, LCDDEN, LCDHSYNC, and LCDVSYNC signals. 38.5.1 38.5.1.1 DMA Controller Configuration Block The configuration block is a set of programmable registers that are used to configure the DMA controller operation. These registers are written via the AHB slave interface. Only word access is allowed. For details on the configuration registers, see “LCD Controller (LCDC) User Interface” on page 656. 38.5.1.2 AHB Interface This block generates the AHB transactions. It generates undefined-length incrementing bursts as well as 4- ,8- or 16-beat incrementing bursts. The size of the transfer can be configured in the BRSTLN field of the DMAFRMCFG register. For details on this register, see “DMA Frame Configuration Register” on page 661. Channel-U This block stores the base address and the number of words transferred for this channel (frame in single scan mode and Upper Panel in dual scan mode) since the beginning of the frame. It also generates the end of frame signal. It has two pointers, the base address and the number of words to transfer. When the module receives a new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel. When the module receives the new_frame signal, it also reloads the base address with the base address programmed by the host. The size of the frame/panel can be programmed in the FRMSIZE field of the DMAFRMCFG Register. This size is calculated as follows: Display_size × Bpp Frame_size = -------------------------------------------------32 where: • Display_size = Horizontal_display_size x Vertical_display_size • Bpp is the bits per pixel configuration 38.5.1.4 Channel-L This block has the same functionality as Channel-U, but for the Lower Panel in dual scan mode only. 38.5.1.5 Control This block receives the request signals from the LCDC core and generates the requests for the channels. 38.5.1.3 633 6462A–ATARM–03-Jun-09 38.5.2 38.5.2.1 LCD Controller Core Configuration Block The configuration block is a set of programmable registers that are used to configure the LCDC core operation. These registers are written via the AHB slave interface. Only word access is allowed. The description of the configuration registers can be found in “LCD Controller (LCDC) User Interface” on page 656. 38.5.2.2 Datapath The datapath block contains five submodules: FIFO, Serializer, Palette, Dithering and Shifter. The structure of the datapath is shown in Figure 38-2. Figure 38-2. Datapath Structure Input Interface FIFO Serializer Configuration IF Palette Control Interface Dithering Output Shifter Output Interface This module transforms the data read from the memory into a format according to the LCD module used. It has four different interfaces: the input interface, the output interface, the configuration interface and the control interface. • The input interface connects the datapath with the DMA controller. It is a dual FIFO interface with a data bus and two push lines that are used by the DMA controller to fill the FIFOs. 634 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 • The output interface is a 24-bit data bus. The configuration of this interface depends on the type of LCD used (TFT or STN, Single or Dual Scan, 4-bit, 8-bit, 16-bit or 24-bit interface). • The configuration interface connects the datapath with the configuration block. It is used to select between the different datapath configurations. • The control interface connects the datapath with the timing generation block. The main control signal is the data-request signal, used by the timing generation module to request new data from the datapath. The datapath can be characterized by two parameters: initial_latency and cycles_per_data. The parameter initial_latency is defined as the number of LCDC Core Clock cycles until the first data is available at the output of the datapath. The parameter cycles_per_data is the minimum number of LCDC Core clock cycles between two consecutive data at the output interface. These parameters are different for the different configurations of the LCD Controller and are shown in Table 38-4. Table 38-4. Datapath Parameters Configuration DISTYPE TFT STN Mono STN Mono STN Mono STN Mono STN Color STN Color STN Color STN Color Single Single Dual Dual Single Single Dual Dual 4 8 8 16 4 8 8 16 SCAN IFWIDTH initial_latency 9 13 17 17 25 11 12 14 15 cycles_per_data 1 4 8 8 16 2 3 4 6 38.5.2.3 FIFO The FIFO block buffers the input data read by the DMA module. It contains two input FIFOs to be used in Dual Scan configuration that are configured as a single FIFO when used in single scan configuration. The size of the FIFOs allows a wide range of architectures to be supported. The upper threshold of the FIFOs can be configured in the FIFOTH field of the LCDFIFO register. The LCDC core will request a DMA transfer when the number of words in each FIFO is less than FIFOTH words. To avoid overwriting in the FIFO and to maximize the FIFO utilization, the FIFOTH should be programmed with: FIFOTH = 512 - (2 x DMA_BURST_LENGTH + 3) where: • 512 is the effective size of the FIFO. It is the total FIFO memory size in single scan mode and half that size in dual scan mode. • DMA_burst_length is the burst length of the transfers made by the DMA 635 6462A–ATARM–03-Jun-09 38.5.2.4 Serializer This block serializes the data read from memory. It reads words from the FIFO and outputs pixels (1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide) depending on the format specified in the PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both bigendian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register. The organization of the pixel data in the memory depends on the configuration and is shown in Table 38-5 and Table 38-7. Table 38-5. Mem Addr Little Endian Memory Organization 0x3 0x2 0x1 8 8 4 2 1 0 0 2 3 5 4 1 2 7 7 3 1 0 6 6 5 5 2 4 4 0x0 3 3 1 0 2 2 1 1 0 0 0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 1bpp Pixel 2bpp Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp Pixel 24bpp Pixel 24bpp Pixel 24bpp 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 15 7 3 1 14 13 6 12 11 5 2 10 9 4 8 7 3 6 5 Table 38-7. Mem Addr Big Endian Memory Organization 0x3 0x2 0x1 8 7 6 5 4 0x0 3 2 1 0 Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 Pixel 1bpp Pixel 2bpp Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp 0 0 0 0 0 0 1 2 1 3 4 2 1 5 6 3 7 8 4 2 1 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 5 6 3 7 8 4 2 1 1 9 10 5 11 12 6 3 13 14 7 15 636 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 38-7. Mem Addr Pixel 24bpp Pixel 24bpp Pixel 24bpp 2 4 Big Endian Memory Organization 0x3 1 3 5 0x2 0x1 2 0x0 38.5.2.5 Palette This block is used to generate the pixel gray or color information in palletized configurations. The different modes with the palletized/non-palletized configuration can be found in Table 38-8. In these modes, 1, 2, 4 or 8 input bits index an entry in the lookup table. The corresponding entry in the lookup table contains the color or gray shade information for the pixel. Table 38-8. Palette Configurations Configuration DISTYPE TFT TFT STN Mono STN Mono STN Color STN Color PIXELSIZE 1, 2, 4, 8 16, 24 1, 2 4 1, 2, 4, 8 16 Palette Palletized Non-palletized Palletized Non-palletized Palletized Non-palletized The lookup table can be accessed by the host in R/W mode to allow the host to program and check the values stored in the palette. It is mapped in the LCD controller configuration memory map. The LUT is mapped as 16-bit half-words aligned at word boundaries, only word write access is allowed (the 16 MSB of the bus are not used). For the detailed memory map, see Table 38-15 on page 656. The lookup table contains 256 16-bit wide entries. The 256 entries are chosen by the programmer from the 216 possible combinations. For the structure of each LUT entry, see Table 38-9. Table 38-9. Address 00 01 ... FE FF Intensity_bit_254 Intensity_bit_255 Blue_value_254[4:0] Blue_value_255[4:0] Green_value_254[4:0] Green_value_255[4:0] Red_value_254[4:0] Red_value_255[4:0] Intensity_bit_0 Intensity_bit_1 Blue_value_0[4:0] Blue_value_1[4:0] Lookup Table Structure in the Memory Data Output [15:0] Green_value_0[4:0] Green_value_1[4:0] Red_value_0[4:0] Red_value_1[4:0] 637 6462A–ATARM–03-Jun-09 In STN Monochrome, only the four most significant bits of the red value are used (16 gray shades). In STN Color, only the four most significant bits of the blue, green and red value are used (4096 colors). In TFT mode, all the bits in the blue, green and red values are used (32768 colors). In this mode, there is also a common intensity bit that can be used to double the possible colors. This bit is the least significant bit of each color component in the LCDD interface (LCDD[18], LCDD[10], LCDD[2]). The LCDD unused bits are tied to 0 when TFT palletized configurations are used (LCDD[17:16], LCDD[9:8], LCDD[1:0]). 38.5.2.6 Dithering The dithering block is used to generate the shades of gray or color when the LCD Controller is used with an STN LCD Module. It uses a time-based dithering algorithm and Frame Rate Control method. The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the display an appearance of multiple shades. In order to reduce the flicker noise caused by turning on and off adjacent pixels at the same time, a time-based dithering algorithm is used to vary the pattern of adjacent pixels every frame. This algorithm is expressed in terms of Dithering Pattern registers (DP_i) and considers not only the pixel gray level number, but also its horizontal coordinate. Table 38-10 shows the correspondences between the gray levels and the duty cycle. Table 38-10. Dithering Duty Cycle Gray Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Duty Cycle 1 6/7 4/5 3/4 5/7 2/3 3/5 4/7 1/2 3/7 2/5 1/3 1/4 1/5 1/7 0 Pattern Register DP6_7 DP4_5 DP3_4 DP5_7 DP2_3 DP3_5 DP4_7 ~DP1_2 ~DP4_7 ~DP3_5 ~DP2_3 ~DP3_4 ~DP4_5 ~DP6_7 - The duty cycles for gray levels 0 and 15 are 0 and 1, respectively. 638 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 The same DP_i register can be used for the pairs for which the sum of duty cycles is 1 (e.g., 1/7 and 6/7). The dithering pattern for the first pair member is the inversion of the one for the second. The DP_i registers contain a series of 4-bit patterns. The (3-m)th bit of the pattern determines if a pixel with horizontal coordinate x = 4n + m (n is an integer and m ranges from 0 to 3) should be turned on or off in the current frame. The operation is shown by the examples below. Consider the pixels a, b, c and d with the horizontal coordinates 4*n+0, 4*n+1, 4*n+2 and 4*n+3, respectively. The four pixels should be displayed in gray level 9 (duty cycle 3/5) so the register used is DP3_5 =”1010 0101 1010 0101 1111”. The output sequence obtained in the data output for monochrome mode is shown in Table 3811. Table 38-11. Dithering Algorithm for Monochrome Mode Frame Number N N+1 N+2 N+3 N+4 N+5 N+6 N+7 ... Pattern 1010 0101 1010 0101 1111 1010 0101 1010 ... Pixel a ON OFF ON OFF ON ON OFF ON ... Pixel b OFF ON OFF ON ON OFF ON OFF ... Pixel c ON OFF ON OFF ON ON OFF ON ... Pixel d OFF ON OFF ON ON OFF ON OFF ... Consider now color display mode and two pixels p0 and p1 with the horizontal coordinates 4*n+0, and 4*n+1. A color pixel is composed of three components: {R, G, B}. Pixel p0 will be displayed sending the color components {R0, G0, B0} to the display. Pixel p1 will be displayed sending the color components {R1, G1, B1}. Suppose that the data read from memory and mapped to the lookup tables corresponds to shade level 10 for the three color components of both pixels, with the dithering pattern to apply to all of them being DP2_3 = “1101 1011 0110”. Table 38-12 shows the output sequence in the data output bus for single scan configurations. (In Dual Scan Configuration, each panel data bus acts like in the equivalent single scan configuration.) Table 38-12. Dithering Algorithm for Color Mode Frame N N N N N N Signal red_data_0 green_data_0 blue_data_0 red_data_1 green_data_1 blue_data_1 Shadow Level 1010 1010 1010 1010 1010 1010 Bit used 3 2 1 0 3 2 Dithering Pattern 1101 1101 1101 1101 1101 1101 4-bit LCDD LCDD[3] LCDD[2] LCDD[1] LCDD[0] LCDD[3] LCDD[2] 8-bit LCDD LCDD[7] LCDD[6] LCDD[5] LCDD[4] LCDD[3] LCDD[2] Output R0 G0 b0 R1 G1 B1 639 6462A–ATARM–03-Jun-09 Table 38-12. Dithering Algorithm for Color Mode (Continued) Frame … N+1 N+1 N+1 N+1 N+1 N+1 … N+2 N+2 N+2 N+2 N+2 N+2 … Note: Signal … red_data_0 green_data_0 blue_data_0 red_data_1 green_data_1 blue_data_1 … red_data_0 green_data_0 blue_data_0 red_data_1 green_data_1 blue_data_1 … Shadow Level … 1010 1010 1010 1010 1010 1010 … 1010 1010 1010 1010 1010 1010 … Bit used … 3 2 1 0 3 2 … 3 2 1 0 3 2 … Dithering Pattern … 1011 1011 1011 1011 1011 1011 … 0110 0110 0110 0110 0110 0110 … 4-bit LCDD … LCDD[3] LCDD[2] LCDD[1] LCDD[0] LCDD[3] LCDD[2] … LCDD[3] LCDD[2] LCDD[1] LCDD[0] LCDD[3] LCDD[2] … 8-bit LCDD … LCDD[7] LCDD[6] LCDD[5] LCDD[4] LCDD[3] LCDD[2] … LCDD[7] LCDD[6] LCDD[5] LCDD[4] LCDD[3] LCDD[2] … Output … R0 g0 B0 R1 G1 b1 … r0 G0 B0 r1 g1 B1 … Ri = red pixel component ON. Gi = green pixel component ON. Bi = blue pixel component ON. ri = red pixel component OFF. gi = green pixel component OFF. bi = blue pixel component OFF. 38.5.2.7 Shifter The FIFO, Serializer, Palette and Dithering modules process one pixel at a time in monochrome mode and three sub-pixels at a time in color mode (R,G,B components). This module packs the data according to the output interface. This interface can be programmed in the DISTYPE, SCANMOD, and IFWIDTH fields of the LCDCON2 register. The DISTYPE field selects between TFT, STN monochrome and STN color display. The SCANMODE field selects between single and dual scan modes; in TFT mode, only single scan is supported. The IFWIDTH field configures the width of the interface in STN mode: 4-bit (in single scan mode only), 8-bit and 16-bit (in dual scan mode only). For a more detailed description of the fields, see “LCD Controller (LCDC) User Interface” on page 656. For a more detailed description of the LCD Interface, see “LCD Interface” on page 645. 38.5.2.8 Timegen The time generator block generates the control signals LCDDOTCK, LCDHSYNC, LCDVSYNC, LCDDEN, used by the LCD module. This block is programmable in order to support different types of LCD modules and obtain the output clock signals, which are derived from the LCDC Core clock. The LCDDOTCK signal is used to clock the data into the LCD drivers' shift register. The data is sent through LCDD[23:0] synchronized by default with LCDDOTCK falling edge (rising edge can be selected). The CLKVAL field of LCDCON1 register controls the rate of this signal. The divisor 640 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 can also be bypassed with the BYPASS bit in the LCDCON1 register. In this case, the rate of LCDDOTCK is equal to the frequency of the LCDC Core clock. The minimum period of the LCDDOTCK signal depends on the configuration. This information can be found in Table 38-13. f LCDC_clock f LCDDOTCK = -------------------------------2 × CLKVAL The LCDDOTCK signal has two different timings that are selected with the CLKMOD field of the LCDCON2 register: • Always Active (used with TFT LCD Modules) • Active only when data is available (used with STN LCD Modules) Table 38-13. Minimum LCDDOTCK Period in LCDC Core Clock Cycles Configuration DISTYPE TFT STN Mono STN Mono STN Mono STN Mono STN Color STN Color STN Color STN Color Single Single Dual Dual Single Single Dual Dual 4 8 8 16 4 8 8 16 SCAN IFWIDTH LCDDOTCK Period 1 4 8 8 16 2 2 4 6 The LCDDEN signal indicates valid data in the LCD Interface. After each horizontal line of data has been shifted into the LCD, the LCDHSYNC is asserted to cause the line to be displayed on the panel. The following timing parameters can be configured: • Vertical to Horizontal Delay (VHDLY): The delay between begin_of_line and the generation of LCDHSYNC is configurable in the VHDLY field of the LCDTIM1 register. The delay is equal to (VHDLY+1) LCDDOTCK cycles. • Horizontal Pulse Width (HPW): The LCDHSYNC pulse width is configurable in HPW field of LCDTIM2 register. The width is equal to (HPW + 1) LCDDOTCK cycles. • Horizontal Back Porch (HBP): The delay between the LCDHSYNC falling edge and the first LCDDOTCK rising edge with valid data at the LCD Interface is configurable in the HBP field of the LCDTIM2 register. The delay is equal to (HBP+1) LCDDOTCK cycles. • Horizontal Front Porch (HFP): The delay between end of valid data and the end of the line is configurable in the HFP field of the LCDTIM2 register. The delay is equal to (HFP+2) LCDDOTCK cycles. 641 6462A–ATARM–03-Jun-09 There is a limitation in the minimum values of VHDLY, HPW and HBP parameters imposed by the initial latency of the datapath. The total delay in LCDC clock cycles must be higher than or equal to the latency column in Table 38-4 on page 635. This limitation is given by the following formula: 38.5.2.9 Equation 1 ( VHDLY + HPW + HBP + 3 ) × PCLK_PERIOD ≥ DPATH_LATENCY where: • VHDLY, HPW, HBP are the value of the fields of LCDTIM1 and LCDTIM2 registers • PCLK_PERIOD is the period of LCDDOTCK signal measured in LCDC Clock cycles • DPATH_LATENCY is the datapath latency of the configuration, given in Table 38-4 on page 635 The LCDVSYNC is asserted once per frame. This signal is asserted to cause the LCD's line pointer to start over at the top of the display. The timing of this signal depends on the type of LCD: STN or TFT LCD. In STN mode, the high phase corresponds to the complete first line of the frame. In STN mode, this signal is synchronized with the first active LCDDOTCK rising edge in a line. In TFT mode, the high phase of this signal starts at the beginning of the first line. The following timing parameters can be selected: • Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the LCDTIM1 register. The pulse width is equal to (VPW+1) lines. • Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in VBP field of LCDTIM1 register. The number of inactive lines is equal to VBP. This field should be programmed with 0 in STN Mode. • Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP field of LCDTIM2 register. The number of inactive lines is equal to VFP. This field should be programmed with 0 in STN mode. There are two other parameters to configure in this module, the HOZVAL and the LINEVAL fields of the LCDFRMCFG: • HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of active cycles in each line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1. • LINEVAL configures the number of active lines per frame. This number is equal to (LINEVAL+1) lines. The minimum value of this parameter is 1. Figure 38-3, Figure 38-4 and Figure 38-5 show the timing of LCDDOTCK, LCDDEN, LCDHSYNC and LCDVSYNC signals: 642 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 38-3. STN Panel Timing, CLKMOD 0 Frame Period LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD Line Period VHDLY+ LCDVSYNC HPW+1 HBP+1 HOZVAL+1 HFP+1 LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK 1/2 PCLK 1/2 PCLK Figure 38-4. TFT Panel Timing, CLKMOD = 0, VPW = 2, VBP = 2, VFP = 1 Frame Period (VPW+1) Lines LCDVSYNC Vertical Back Porch = VBP Lines VHDLY+1 LCDHSYNC LCDDEN LCDDOTCK LCDD Vertical Fron t Porch = VFP Lines Line Period VHDLY+1 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK 1/2 PCLK 1/2 PCLK HPW+1 HBP+1 HOZVAL+1 HFP+1 643 6462A–ATARM–03-Jun-09 Figure 38-5. TFT Panel Timing (Line Expanded View), CLKMOD=1 Line Period VHDLY+1 LCDVSYNC LCDHSYNC LCDDEN LCDDOTCK LCDD 1 PCLK 1/2 PCLK 1/2 PCLK HPW+1 HBP+1 HOZVAL+1 HFP+1 Usually the LCD_FRM rate is about 70 Hz to 75 Hz. It is given by the following equation: VHDLY + HPW + HBP + HOZVAL + HFP + 5 1 --------------------------- = ⎛ -------------------------------------------------------------------------------------------------------------------- ⎞ ( VBP + LINEVAL + VFP + 1 ) ⎝ ⎠ f LCDDOTCK f LCDVSYNC where: • HOZVAL determines de number of LCDDOTCK cycles per line • LINEVAL determines the number of LCDHSYNC cycles per frame, according to the expressions shown below: In STN Mode: HOZVAL = Horizontal_display_size – 1 -------------------------------------------------------------Number_data_lines LINEVAL = Vertical_display_size – 1 In monochrome mode, Horizontal_display_size is equal to the number of horizontal pixels. The number_data_lines is equal to the number of bits of the interface in single scan mode; number_data_lines is equal to half the bits of the interface in dual scan mode. In color mode, Horizontal_display_size equals three times the number of horizontal pixels. In TFT Mode: HOZVAL = Horizontal_display_size – 1 LINEVAL = Vertical_display_size – 1 The frame rate equation is used first without considering the clock periods added at the end beginning or at the end of each line to determine, approximately, the LCDDOTCK rate: f lcd_pclk = ( HOZVAL + 5 ) × ( f lcd_vsync × ( LINEVAL + 1 ) ) With this value, the CLKVAL is fixed, as well as the corresponding LCDDOTCK rate. Then select VHDLY, HPW and HBP according to the type of LCD used and “Equation 1” on page 642. 644 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Finally, the frame rate is adjusted to 70 Hz - 75 Hz with the HFP value: 1 HFP = f LCDDOTCK × -------------------------------------------------------------------------------------------------------------- – ( VHDLY + VPW + VBP + HOZVAL + 5 ) f LCDVSYNC × ( LINEVAL + VBP + VFP + 1 ) The line counting is controlled by the read-only field LINECNT of LCDCON1 register. The LINECNT field decreases by one unit at each falling edge of LCDHSYNC. 38.5.2.10 Display This block is used to configure the polarity of the data and control signals. The polarity of all clock signals can be configured by LCDCON2[12:8] register setting. This block also generates the lcd_pwr signal internally used to control the state of the LCD pins and to turn on and off by software the LCD module. This signal is controlled by the PWRCON register and respects the number of frames configured in the GUARD_TIME field of PWRCON register (PWRCON[7:1]) between the write access to LCD_PWR field (PWRCON[0]) and the activation/deactivation of lcd_pwr signal. The minimum value for the GUARD_TIME field is one frame. This gives the DMA Controller enough time to fill the FIFOs before the start of data transfer to the LCD. 38.5.2.11 PWM This block generates the LCD contrast control signal (LCDCC) to make possible the control of the display's contrast by software. This is an 8-bit PWM (Pulse Width Modulation) signal that can be converted to an analog voltage with a simple passive filter. The PWM module has a free-running counter whose value is compared against a compare register (CONTRAST_VAL register). If the value in the counter is less than that in the register, the output brings the value of the polarity (POL) bit in the PWM control register: CONTRAST_CTR. Otherwise, the opposite value is output. Thus, a periodic waveform with a pulse width proportional to the value in the compare register is generated. Due to the comparison mechanism, the output pulse has a width between zero and 255 PWM counter cycles. Thus by adding a simple passive filter outside the chip, an analog voltage between 0 and (255/256) × VDD can be obtained (for the positive polarity case, or between (1/256) × VDD and VDD for the negative polarity case). Other voltage values can be obtained by adding active external circuitry. For PWM mode, the frequency of the counter can be adjusted to four different values using field PS of CONTRAST_CTR register. 38.5.3 LCD Interface The LCD Controller interfaces with the LCD Module through the LCD Interface (Table 38-14 on page 651). The Controller supports the following interface configurations: 24-bit TFT single scan, 16-bit STN Dual Scan Mono (Color), 8-bit STN Dual (Single) Scan Mono (Color), 4-bit single scan Mono (Color). A 4-bit single scan STN display uses 4 parallel data lines to shift data to successive single horizontal lines one at a time until the entire frame has been shifted and transferred. The 4 LSB pins of LCD Data Bus (LCDD [3:0]) can be directly connected to the LCD driver; the 20 MSB pins (LCDD [23:4]) are not used. 645 6462A–ATARM–03-Jun-09 An 8-bit single scan STN display uses 8 parallel data lines to shift data to successive single horizontal lines one at a time until the entire frame has been shifted and transferred. The 8 LSB pins of LCD Data Bus (LCDD [7:0]) can be directly connected to the LCD driver; the 16 MSB pins (LCDD [23:8]) are not used. An 8-bit Dual Scan STN display uses two sets of 4 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. The bus LCDD[3:0] is connected to the upper panel data lines and the bus LCDD[7:4] is connected to the lower panel data lines. The rest of the LCD Data Bus lines (LCDD[23:8]) are not used. A 16-bit Dual Scan STN display uses two sets of 8 parallel data lines to shift data to successive upper and lower panel horizontal lines one at a time until the entire frame has been shifted and transferred. The bus LCDD[7:0] is connected to the upper panel data lines and the bus LCDD[15:8] is connected to the lower panel data lines. The rest of the LCD Data Bus lines (LCDD[23:16]) are not used. STN Mono displays require one bit of image data per pixel. STN Color displays require three bits (Red, Green and Blue) of image data per pixel, resulting in a horizontal shift register of length three times the number of pixels per horizontal line. This RGB or Monochrome data is shifted to the LCD driver as consecutive bits via the parallel data lines. A TFT single scan display uses up to 24 parallel data lines to shift data to successive horizontal lines one at a time until the entire frame has been shifted and transferred. The 24 data lines are divided in three bytes that define the color shade of each color component of each pixel. The LCDD bus is split as LCDD[23:16] for the blue component, LCDD[15:8] for the green component and LCDD[7:0] for the red component. If the LCD Module has lower color resolution (fewer bits per color component), only the most significant bits of each component are used. All these interfaces are shown in Figure 38-6 to Figure 38-10. Figure 38-6 on page 646 shows the 24-bit single scan TFT display timing; Figure 38-7 on page 647 shows the 4-bit single scan STN display timing for monochrome and color modes; Figure 38-8 on page 648 shows the 8-bit single scan STN display timing for monochrome and color modes; Figure 38-9 on page 649 shows the 8-bit Dual Scan STN display timing for monochrome and color modes; Figure 38-10 on page 650 shows the 16-bit Dual Scan STN display timing for monochrome and color modes. Figure 38-6. TFT Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [24:16] LCDD [15:8] LCDD [7:0] B0 G0 R0 B1 G1 R1 646 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 38-7. Single Scan Monochrome and Color 4-bit Panel Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [3] LCDD [2] LCDD [1] LCDD [0] P0 P1 P2 P3 P4 P5 P6 P7 LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [3] LCDD [2] LCDD [1] LCDD [0] R0 G0 B0 R1 G1 B1 R2 G2 647 6462A–ATARM–03-Jun-09 Figure 38-8. Single Scan Monochrome and Color 8-bit Panel Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0] P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK LCDD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0] R0 G0 B0 R1 G1 B1 R2 G2 B2 R3 G3 B3 R4 G4 B4 R5 648 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Figure 38-9. Dual Scan Monochrome and Color 8-bit Panel Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK Lower Pane LCDD [7] LCDD [6] LCDD [5] LCDD [4] Upper Pane LP0 LP1 L2 L3 LP4 LP5 LP6 LP7 LCDD [3] LCDD [2] LCDD [1] LCDD [0] UP0 UP4 UP1 UP5 UP2 UP6 UP3 UP7 LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK Lower Pane LCDD [7] LCDD [6] LCDD [5] LCDD [4] Upper Pane LR0 LG0 LB0 LR1 LG1 LB1 LR2 LG2 LCDD [3] LCDD [2] LCDD [1] LCDD [0] UR0 UG1 UG0 UB1 UB0 UR2 UR1 UG2 649 6462A–ATARM–03-Jun-09 Figure 38-10. Dual Scan Monochrome and Color 16-bit Panel Timing (First Line Expanded View) LCDVSYNC LCDDEN LCDHSYNC LCDDOTCK Lower Panel LCDD [15] LCDD [14] LCDD [13] LCDD [12] LCDD [11] LCDD [10] LCDD [9] LCDD [8] Upper Panel LP0 LP1 LP8 LP9 LP2 LP10 LP3 LP11 LP4 LP12 LP5 LP13 LP6 LP14 LP7 LP15 UP0 UP8 UP1 UP9 UP2 UP10 UP3 UP11 UP4 UP12 UP5 UP13 UP6 UP14 UP7 UP15 LC DD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0] LCDVSYNC LCDDEN LC DHSYNC LCDDOTCK Lower Panel LCDD [15] LCDD [14] LCDD [13] LCDD [12] LCDD [11] LCDD [10] LCDD [9] LCDD [8] Upper Panel LR0 LB2 LG0 LR3 LB0 LR1 LG3 LB3 LG1 LR4 LB1 LR2 LG4 LB4 LG2 LR5 UR0 UB2 UG0 UR3 UB0 UG3 UR1 UB3 UG1 UR4 UB1 UG4 UR2 UB4 UG2 UR5 LCDD [7] LCDD [6] LCDD [5] LCDD [4] LCDD [3] LCDD [2] LCDD [1] LCDD [0] 650 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 Table 38-14. LCD Signal Multiplexing LCD Data Bus LCDD[23] LCDD[22] LCDD[21] LCDD[20] LCDD[19] LCDD[18] LCDD[17] LCDD[16] LCDD[15] LCDD[14] LCDD[13] LCDD[12] LCDD[11] LCDD[10] LCDD[9] LCDD[8] LCDD[7] LCDD[6] LCDD[5] LCDD[4] LCDD[3] LCDD[2] LCDD[1] LCDD[0] LCD3 LCD2 LCD1 LCD0 LCD7 LCD6 LCD5 LCD4 LCD3 LCD2 LCD1 LCD0 LCDLP3 LCDLP2 LCDLP1 LCDLP0 LCDUP3 LCDUP2 LCDUP1 LCDUP0 LCDLP7 LCDLP6 LCDLP5 LCDLP4 LCDLP3 LCDLP2 LCDLP1 LCDLP0 LCDUP7 LCDUP6 LCDUP5 LCDUP4 LCDUP3 LCDUP2 LCDUP1 LCDUP0 4-bit STN Single Scan (mono, color) 8-bit STN Single Scan (mono, color) 8-bit STN Dual Scan (mono, color) 16-bit STN Dual Scan (mono, color) 24-bit TFT LCD_BLUE7 LCD_BLUE6 LCD_BLUE5 LCD_BLUE4 LCD_BLUE3 LCD_BLUE2 LCD_BLUE1 LCD_BLUE0 LCD_GREEN7 LCD_GREEN6 LCD_GREEN5 LCD_GREEN4 LCD_GREEN3 LCD_GREEN2 LCD_GREEN1 LCD_GREEN0 LCD_RED7 LCD_RED6 LCD_RED5 LCD_RED4 LCD_RED3 LCD_RED2 LCD_RED1 LCD_RED0 16-bit TFT LCD_BLUE4 LCD_BLUE3 LCD_BLUE2 LCD_BLUE1 LCD_BLUE0 Intensity Bit LCD_GREEN4 LCD_GREEN3 LCD_GREEN2 LCD_GREEN1 LCD_GREEN0 Intensity Bit LCD_RED4 LCD_RED3 LCD_RED2 LCD_RED1 LCD_RED0 Intensity Bit 651 6462A–ATARM–03-Jun-09 38.6 Interrupts The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal LCD Core Clock. The IRQs are: • DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB slave while it is doing a data transfer. • FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when the FIFO is empty. • FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO while the FIFO is full. • DMA end of frame IRQ. Generated when the DMA controller updates the Frame Base Address pointers. This IRQ can be used to implement a double-buffer technique. For more information, see “Double-buffer Technique” on page 653. • End of Line IRQ. This IRQ is generated when the LINEBLANK period of each line is reached and the DMA Controller is in inactive state. • End of Last Line IRQ. This IRQ is generated when the LINEBLANK period of the last line of the current frame is reached and the DMA Controller is in inactive state. Each IRQ can be individually enabled, disabled or cleared, in the LCD_IER (Interrupt Enable Register), LCD_IDR (Interrupt Disable Register) and LCD_ICR (Interrupt Clear Register) registers. The LCD_IMR register contains the mask value for each IRQ source and the LDC_ISR contains the status of each IRQ source. A more detailed description of these registers can be found in “LCD Controller (LCDC) User Interface” on page 656. 38.7 Configuration Sequence The DMA Controller starts to transfer image data when the LCDC Core is activated (Write to LCD_PWR field of PWRCON register). Thus, the user should configure the LCDC Core and configure and enable the DMA Controller prior to activation of the LCD Controller. In addition, the image data to be shows should be available when the LCDC Core is activated, regardless of the value programmed in the GUARD_TIME field of the PWRCON register. To disable the LCD Controller, the user should disable the LCDC Core and then disable the DMA Controller. The user should not enable LIP again until the LCDC Core is in IDLE state. This is checked by reading the LCD_BUSY bit in the PWRCON register. The initialization sequence that the user should follow to make the LCDC work is: • Create or copy the first image to show in the display buffer memory. • If a palletized mode is used, create and store a palette in the internal LCD Palette memory(See “Palette” on page 637. • Configure the LCD Controller Core without enabling it: – LCDCON1 register: Program the CLKVAL and BYPASS fields: these fields control the pixel clock divisor that is used to generate the pixel clock LCDDOTCK. The value to program depends on the LCD Core clock and on the type and size of the LCD Module used. There is a minimum value of the LCDDOTCK clock period that depends on the LCD Controller Configuration, this minimum value can be found in Table 38-13 on page 641. The equations that are used to calculate the value of the pixel clock divisor can be found at the end of the section “Timegen” on page 640 652 AT91SAM9G10 6462A–ATARM–03-Jun-09 AT91SAM9G10 – LCDCON2 register: Program its fields following their descriptions in the LCD Controller User Interface section below and considering the type of LCD module used and the desired working mode. Consider that not all combinations are possible. – LCDTIM1 and LCDTIM2 registers: Program their fields according to the datasheet of the LCD module used and with the help of the Timegen section in page 10. Note that some fields are not applicable to STN modules and must be programmed with 0 values. Note also that there is a limitation on the minimum value of VHDLY, HPW, HBP that depends on the configuration of the LCDC. – LCDFRMCFG register: program the dimensions of the LCD module used. – LCDFIFO register: To program it, use the formula in section “FIFO” on page 635 – DP1_2 to DP6_7 registers: they are only used for STN displays. They contain the dithering patterns used to generate gray shades or colors in these modules. They are loaded with recommended patterns at reset, so it is not necessary to write anything on them. They can be used to improve the image quality in the display by tuning the patterns in each application. – PWRCON Register: this register controls the power-up sequence of the LCD, so take care to use it properly. Do not enable the LCD (writing a 1 in LCD_PWR field) until the previous steps and the configuration of the DMA have been finished. – CONTRAST_CTR and CONTRAST_VAL: use this registers to adjust the contrast of the display, when the LCDCC line is used. • Configure the DMA Controller. The user should configure the base address of the display buffer memory, the size of the AHB transaction and the size of the display image in memory. When the DMA is configured the user should enable the DMA. To do so the user should configure the following registers: – DMABADDR1 and DMABADDR2 registers: In single scan mode only DMABADDR1 register must be configured with the base address of the display buffer in memory. In dual scan mode DMABADDR1 should be configured with the base address of the Upper Panel display buffer and DMABADDR2 should be configured with the base address of the Lower Panel display buffer. – DMAFRMCFG register: Program the FRMSIZE field. Note that in dual scan mode the vertical size to use in the calculation is that of each panel. Respect to the BRSTLN field, a recommended value is a 4-word burst. – DMACON register: Once both the LCD Controller Core and the DMA Controller have been configured, enable the DMA Controller by writing a “1” to the DMAEN field of this register. • Finally, enable the LCD Controller Core by writing a “1” in the LCD_PWR field of the PWRCON register and do any other action that may be required to turn the LCD module on. 38.8 Double-buffer Technique The double-buffer technique is used to avoid flickering while the frame being displayed is updated. Instead of using a single buffer, there are two different buffers, the backbuffer (background buffer) and the primary buffer (the buffer being displayed). The host updates the backbuffer while the LCD Controller is displaying the primary buffer. When the backbuffer has been updated the host updates the DMA Base Address registers. When using a Dual Panel LCD Module, both base address pointers should be updated in the same frame. There are two possibilities: 653 6462A–ATARM–03-Jun-09 • Check the DMAFRMPTx register to ensure that there is enough time to update the DMA Base Address registers before the end of frame. • Update the Frame Base Address Registers when the End Of Frame IRQ is generated. Once the host has updated the Frame Base Address Registers and the next DMA end of frame IRQ arrives, the backbuffer and the primary buffer are swapped and the host can work with the new backbuffer. 38.9 Register Configuration Guide Program the PIO Controller to enable LCD signals. Enable the LCD controller clock in the Power Management Controller. PMC_SCER = 1