AT91SAM9R64_09

Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer – 265 MIPS at 240 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Multi-layer AHB Bus Matrix for Large Bandwidth Transfers – Six 32-bit-layer Matrix – Boot Mode Select Option, Remap Command One 32-KByte internal ROM, Single-cycle Access at Maximum Speed One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed – 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB Bus Matrix – Single-cycle Accessible on AHB Bus at Bus Speed – Single-cycle Accessible on TCM Interface at Processor Speed 2-channel DMA – Memory to Memory Transfer – 16 Bytes FIFO – LInked List External Bus Interface (EBI) – EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® LCD Controller (for AT91SAM9RL64 only) – Supports Passive or Active Displays – Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Virtual Screen Support High Speed (480 Mbit/s) USB 2.0 Device Controller – On-Chip High Speed Transceiver, UTMI+ Physical Interface – Integrated FIFOs and Dedicated DMA – 4 Kbyte Configurable Integrated DPRAM Fully-featured System Controller, including – Reset Controller, Shutdown Controller – Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock Reset Controller (RSTC) – Based on Two Power-on Reset Cells – Reset Source Identification and Reset Output Control Shutdown Controller (SHDC) – Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) – Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 12 MHz On-chip Oscillator for Main System Clock and USB Clock – One PLL up to 240 MHz • • • AT91 ARM Thumb Microcontrollers AT91SAM9R64 AT91SAM9RL64 Preliminary Summary • • • • • • • • 6289CS–ATARM–28-May-09 – One PLL 480 MHz Optimized for USB HS • Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – One External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention – Mode for General Purpose 2-wire UART Serial Communication Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Real-time Clock (RTC) – Time, Date and Alarm 32-bit Parallel Load – Low Power Consumption – Programmable Periodic Interrupt One 6-channel 10-Bit Analog-to-Digital Converter – Touch Screen Interface Compatible with Industry Standard 4-wire Sensitive Touch Panels Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD) – 118 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os for 217-ball BGA Package – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output 22-channel Peripheral DMA Controller (PDC) One MultiMedia Card Interface (MCI) – SDCard/SDIO 1.0 and MultiMediaCard™ 4.3 Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC Two Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One AC97 Controller (AC97C) – 6-channel Single AC97 Analog Front End Interface, Slot Assigner Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support One Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects – High-speed Synchronous Communications One Three-channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) Two Two-wire Interfaces (TWI) – Compatible with Standard Two-wire Serial Memories – One, Two or Three Bytes for Slave Address – Sequential Read/Write Operations • • • • • • • • • • • • • • • • • 2 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Master, Multi-master and Slave Mode Operation Bit Rate: Up to 400 Kbits General Call Supported in Slave Mode Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only (TWI0 only) SAM-BA® Boot Assistant – Default Boot Program – Interface with SAM-BA Graphic User Interface IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: – 1.08 to 1.32V for VDDCORE, VDDUTMIC, VDDPLLB and VDDBU – 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMII and VDDIOP – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package – – – – • • • • 1. Description The AT91SAM9R64/RL64 device is based on the integration of an ARM926EJ-S processor with a large fast SRAM and a wide range of peripherals. The AT91SAM9R64/RL64 embeds one USB Device High Speed Controller, one LCD Controller (for AT91SAM9RL64 only), one AC97 controller, a 2-channel DMA Controller, four USARTs, two SSCs, one SPI, two TWIs, three Timer Counter channels, a 4-channel PWM generator, one Multimedia Card interface and a 6-channel Analog-to-digital converter that also provides resistive touch screen management. The AT91SAM9R64/RL64 is architectured on a 6-layer bus matrix. It also features an External Bus Interface capable of interfacing with a wide range of memory and peripheral devices. Some features are not available for AT91SAM9R64 in the 144-ball BGA package. Separate block diagrams and PIO multiplexing are provided in this document. Table 1-1 lists the features and signals of AT91SAM9RL64 that are not available or partially available for AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified. Table 1-1. Feature Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Signal AC97FS AC97CK AC97TX AC97RX D16-D31 NCS2 NCS5/CFCS1 LCDMOD LCDCC LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0-LCDD23 Peripheral A PD1 PD2 PD3 PD4 PB16-PB31 PD0 PD13 PC2 PC3 PC4 PC5 PC6 PC7 PC8-PC31 Peripheral B AC97 Full - EBI Partial - LCDC Full - 3 6289CS–ATARM–28-May-09 Table 1-1. Feature PWM SPI Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Partial Partial Signal PWM2 NPCS2 NPCS3 RF1 RK1 TD1 RD1 TK1 TF1 AD3YM GPAD4 GPAD5 TIOA1 TIOB1 TCLK1 TIOA2 TIOB2 TWD1 TWCK1 SCK0 RTS0 CTS0 DSR0 DTR0 DCD0 RI0 SCK1 SCK2 RTS2 CTS2 SCK3 RTS3 CTS3 Peripheral A PD5 and PD12 PD8 PD9 and PD13 PA8 PA9 PA13 PA14 PA29 PA30 PC29 PC30 PC31 PD10 PD11 Peripheral B - SSC1 Full - Touchscreen ADC Partial PA20 PD6 PD7 TC Partial - TWI Full PD10 PD11 PA8 PA9 PA10 PD14 PD15 PD16 PD17 PD9 PA29 PA30 - USART0 Partial - USART1 USART2 Partial Partial PD2 PA20 PD3 PD4 USART3 Partial 4 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 Figure 2-1. TD TI DO TM S T C RTK CK NT RS T J TA G SE L 2. Block Diagrams MASTER SLAVE TST System Controller JTAG Selection and Boundary Scan HS UTMI Transceiver FIQ In-Circuit Emulator BM G N I II IC TM TM TM PMPM UU D D SD SD D D VDD VBG DFS DFS DH DH V S 6289CS–ATARM–28-May-09 D U AIC ARM926EJ-S Processor TCM Interface ITCM DTCM ICache DCache 4 Kbytes 4 Kbytes CompactFlash NAND Flash & ECC EBI USB Device HS IRQ DRXD DTXD DBGU PDC AT91SAM9R64 Block Diagram PCK0-PCK1 PLLRCA PLLA I D DMA XIN XOUT 12 MHz OSC PMC UPLL 5-layer AHB Bus Matrix SDRAM Controller D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NWAIT A23-A24, A18-A20 WDT PIT RC SRAM 64K Bytes ROM 32K Bytes APB Peripheral Bridge 2-channel DMA Peripheral DMA Controller XIN32 XOUT32 32 kHz OSC 4 GPBREG A21/NANDALE A22/NANDCLE A25/CFRNW RTT SHDN WKUP SHDC PDC PDC TWI0 RTC PDC PDC SPI PWM Static Memory Controller PDC SSC0 PDC NCS4/CFCS0 VDDBU POR NCS3/NANDCS VDDCORE POR RSTC MCI NRST USART0 USART1 USART2 USART3 TC0 TC1 TC2 3-channel 10-bit ADC CFCE1-CFCE2 NANDOE, NANDWE PIOA PIOB PIOC PIOD 0 DA A3 A K D0 K0 -D CD C W C T TW C 0 0 0 0 0 K0 TK TF TD RD RF R A TS 1 S1 33 013 0 2 A0 B0 S1 CK SI ISO MMM TS RT XD XD LK LK IO IO W PC SP MO M RT PW PW P 0- D0TC TC T T -N S0 XD TX R PC N D G0 12 TR AD AD AD EF A N R AN DA DV DD GN SA V T AT91SAM9R64/RL64 Preliminary 5 Figure 2-2. TD TDI O TM S T C RTK CK NT RS T J TA G SE L BM S MASTER SLAVE I II IC TM M M PMPM UTT D DU DU G SD SD SD SD N FFHH G VD VD VB D D D D TST System Controller JTAG Selection and Boundary Scan HS UTMI Transceiver FIQ LC LCDD 0 LCDV -LC S LD Y D CDHS NC D2 3 Y LD DO NC T LCDE CK N LCDC C LCDP DMWR O D 6 AIC In-Circuit Emulator EBI ARM926EJ-S Processor LCDC ICache DCache 4 Kbytes 4 Kbytes IRQ DRXD DTXD PDC DBGU USB Device HS AT91SAM9RL64 Block Diagram PCK0-PCK1 CompactFlash NAND Flash & ECC PLLRCA PLLA PMC I D TCM Interface ITCM DTCM DMA DMA XIN XOUT OSC 12M UPLL 6-layer AHB Bus Matrix PIT SDRAM Controller D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NWAIT A23-A24 A18-A20 WDT RC 4 GPBREG XIN32 XOUT32 OSC 32K SRAM 64K Bytes ROM 32K Bytes APB Peripheral Bridge Peripheral DMA Controller 2-channel DMA A21/NANDALE A22/NANDCLE A25/CFRNW D16-D31 NCS4/CFCS0 RTT RTC PDC PDC RSTC MCI TWI0 TWI1 AT91SAM9R64/RL64 Preliminary Static Memory Controller PDC PDC PDC PDC SPI PWM SHDN WKUP SHDC PDC AC97 VDDBU POR NCS5/CFCS1 NCS3/NANDCS NCS2 Touch Screen Controller SSC0 SSC1 6-channel 10-bit ADC VDDCORE POR NRST USART0 USART1 USART2 USART3 TC0 TC1 TC2 CFCE1-CFCE2 NANDOE, NANDWE PIOA PIOB PIOD PIOC 0 DA 3 3 222 K S X X 1 1 1 1 1 K1 G A3 A K 0 0 D1 1 S3 S K3 D3 3 D0 I0 0 0 S3 K I O FAN 45 LK A B C F R T K TF D D F R TR 0X P 1X M 2Y P 3Y M AD AD RE AN DA -D CD C WD CK W CK CT -RT SC RX TXD C R SR TR PC PC OSMIS WM C IO IO 97 97 97 97 0-T 0- -T -R -R 0D D -N S M T W T TW 0- S0 0- 0- 0- D -P -T 0-T 0-T AC AC AC AC TK TF TD0 D0RF0RK AD AD AD AD AD GP GP DV DD GN T 0 0 AV S R TS RT CK XD XD M LK0 OA OB S T C SR T TS I PC PW TC T TI N 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Name Signal Description List Function Type Power Supplies Active Level Comments VDDIOM VDDIOP VDDUTMII VDDUTMIC GNDUTMI VDDBU GNDBU VDDPLLA GNDPLLA VDDPLLB GNDPLLB VDDANA GNDANA VDDCORE GNDCORE GND EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply USB UTMI+ Interface Power Supply USB UTMI+ Core Power Supply USB UTMI Ground Backup I/O Lines Power Supply Backup Ground PLL Power Supply PLL Ground UTMI PLL and OSC 12M Power Supply UTMI PLL and OSC 12M Ground ADC Analog Power Supply ADC Analog Ground Core Chip Power Supply Ground Ground Power Power Power Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Ground Clocks, Oscillators and PLLs 1.65V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 1.08V to 1.32V 3.0V to 3.6V 1.08 V to 1.32V 3.0V to 3.6V 1.08V to 1.32V XIN XOUT XIN32 XOUT32 VBG PLLRCA PCK0 - PCK1 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Bias Voltage Reference PLL A Filter Programmable Clock Output Input Output Input Output Analog Input Output Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-Up Input Output Input ICE and JTAG Driven at 0V only. 0: The device is in backup mode. 1: The device is running (not in backup mode.) Accept between 0V and VDDBU TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Input Input Output Input Input No pull-up resistor No pull-up resistor No pull-up resistor Pull-down resistor 7 6289CS–ATARM–28-May-09 Table 3-1. Signal Name NTRST Signal Description List (Continued) Function Test Reset Signal Type Input Reset/Test Active Level Low Comments Pull-up resistor. NRST TST Microcontroller Reset Test Mode Select I/O Input Low Pull-up resistor Pull-down resistor Must be connected to GND or VDDIOP. No pullup resistor BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP BMS Boot Mode Select Input Debug Unit - DBGU DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ FIQ External Interrupt Input Fast Interrupt Input Input Input PIO Controller - PIOA - PIOB - PIOC-PIOD PA0 - PA31 PB0 - PB31 PC0 - PC31 PD0 - PD21 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D I/O I/O I/O I/O External Bus Interface - EBI D0 - D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset. D16-D31 not present on AT91SAM9R64. 0 at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Static Memory Controller - SMC NCS0 - NCS5 NWR0 - NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output Low Low Low Low Low NCS2, NCS5 not present on AT91SAM9R64. CompactFlash Support CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines Output Output Output Output Output Output Output Low CFCS1 not present on AT91SAM9R64. Low Low Low Low Low 8 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Comments NAND Flash Support NANDCS NANDOE NANDWE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable Output Output Output SDRAM Controller SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Multimedia Card Interface MCI CK CDA DA0 - DA3 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data I/O I/O I/O Low Low High Low Low Low Low Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx TXDx RXDx RTSx CTSx DTR0 DSR0 DCD0 RI0 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send USART0 Data Terminal Ready USART0 Data Set Ready USART0 Data Carrier Detect USART0 Ring Indicator I/O I/O Input Output Input I/O Input Output Input RTS0, RTS2, RTS3 not present on AT91SAM9R64. CTS0, CTS2, CTS3 not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. SCKx not present on AT91SAM9R64. Synchronous Serial Controller - SSCx TD0 - TD1 RD0 - RD1 TK0 - TK1 RK0 - RK1 TF0 - TF1 RF0 - RF1 SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O TD1 not present on AT91SAM9R64. RD1 not present on AT91SAM9R64. TK1 not present on AT91SAM9R64. RK1 not present on AT91SAM9R64. TF1 not present on AT91SAM9R64. RF1 not present on AT91SAM9R64. 9 6289CS–ATARM–28-May-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Comments AC97 Controller - AC97C AC97RX AC97TX AC97FS AC97CK AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Input Output Output Input Timer/Counter - TC TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O TCLK1 not present on AT91SAM9R64. TIOA1, TIOA2 not present on AT91SAM9R64. TIOB1, TIOB2 not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Pulse Width Modulation Controller- PWMC PMWx Pulse Width Modulation Output Output PWM2 not present on AT91SAM9R64. Serial Peripheral Interface - SPI MISO MOSI SPCK NPCS0 NPCS1 - NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low NPCS2, NPCS3 not present on AT91SAM9R64. Two-Wire Interface - TWIx TWDx TWCKx TWIx Two-wire Serial Data TWIx Two-wire Serial Clock I/O I/O TWD1 not present on AT91SAM9R64. TWCK1 not present on AT91SAM9R64. Touch Screen Analog-to-Digital Converter GPAD0-GPAD5 AD0XP AD1XM AD2YP AD3YM TSADTRG TSADVREF Analog Inputs Touch Panel Right side Touch Panel Left side Touch Panel Top side Touch Panel Bottom side ADC Trigger ADC Reference Analog Analog Analog Analog Analog Input Analog LCD Controller - LCDC LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCDPWR LCDMOD LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control LCD panel Power enable control LCD Modulation signal Output Output Output Output Output Output Output Output Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. GPAD4, GPAD5 not present on AT91SAM9R64. Multiplexed with AD0 Multiplexed with AD1 Multiplexed with AD2 Multiplexed with AD3. Not present on AT91SAM9R64. 10 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Comments USB High Speed Device DFSDM DFSDP DHSDM DHSDP USB Device Full Speed Data USB Device Full Speed Data + USB Device High Speed Data USB Device High Speed Data + Analog Analog Analog Analog 11 6289CS–ATARM–28-May-09 4. Package and Pinout The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available in a 217-ball LFBGA package. 4.1 144-ball BGA Package Outline Figure 4-1 shows the orientation of the 144-ball BGA package. Figure 4-1. 144-ball BGA Pinout (Top View) 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEF GHJ BALL A1 KLM 12 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 4.2 Pinout AT91SAM9R64 Pinout for 144-ball BGA Package Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 Signal Name PLLRCA VDDUTMII NWR3/NBS3/CFIOW NWR1/NBS1/CFIOR JTAGSEL GNDBU TCK PA[26] PA[24] PA[13] PA[6] PD[20] GNDPLLA NWR0/NWE/CFWE NRD/CFOE NCS0 NCS1/SDCS PB[2] NRST BMS PA[25] PA[15] PA[5] PA[4] PB[5] PB[6] PB[7] PB[8] PB[3] PB[4] TST VDDUTMIC PA[3] PA[2] PA[0] PA[1] Pin G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 Signal Name PB[10] PB[11] PB[12] PB[9] PB[13] GND GND GND GNDUTMI VDDCORE VDDIOP VDDIOP PB[14] PB[15] A[0] A[2] SDA10 D[1] GND GND VDDIOM SDCKE VDDCORE VDDIOP A[4] A[1] A[3] A[14] CAS D[2] D[5] D[12] D[14] VDDIOM D[10] D[9] Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Signal Name A[5] A[6] A[13] A[15] RAS D[3] D[6] D[13] VDDIOM VDDIOM D[11] PB[1] A[7] A[8] A[11] A[16] SDWE D[4] D[7] D[15] PC[1] PC[0] PB[0] GNDANA A[9] A[10] A[12] A[17] D[0] SDCK D[8] ADVREF VDDANA PA[17] PA[18] PA[19] Table 4-1. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 DFSDM DHSDM XIN XOUT XIN32 Signal Name XOUT32 TDO PA[31] PA[22] PA[16] PA[14] PA[11] DFSDP DHSDP NC VDDPLLB GNDPLLB TMS RTCK PA[27] PA[21] PA[12] PD[21] PA[10] VDDPLLA VBG VDDBU SHDN WKUP NTRST TDI PA[28] PA[23] PA[7] PD[19] PD[18] 13 6289CS–ATARM–28-May-09 4.3 217-ball LFBGA Package Outline Figure 4-2 shows the orientation of the 217-ball LFBGA package. Figure 4-2. 217-ball LFBGA Pinout (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEF GHJ KL M NPRT U BALL A1 14 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 4.4 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 Pinout AT91SAM9RL64 Pinout for 217-ball LFBGA Package (1) Signal Name DFSDM DHSDP VDDPLLB XIN XOUT GNDPLLB XOUT32 GND NRST RTCK PA[29] PA[26] PA[22] PA[14] PA[10] PD[20] PD[17] DFSDP DHSDM VBG NC NC XIN32 TST GND TMS VDDCORE PA[28] PA[25] PA[21] PA[13] PD[21] PD[19] PA[9] VDDPLLA VDDUTMII GND GNDUTMI VDDBU WKUP GNDBU TCK TDI PA[31] PA[27] PA[24] PA[16] PA[11] PD[18] PA[7] PA[6] PLLRCA NWR1/NBS1/CFIOR GND GND Pin D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J8 J9 J10 Signal Name SHDN JTAGSEL NTRST BMS TDO PA[30] GND PA[23] PA[15] PA[12] PA[8] PD[13] PD[16] GNDPLLA NCS1/SDCS NCS0 NWR3/NBS3/CFIOW PD[15] PD[14] PA[5] PA[4] NRD/CFOE PB[2] NWR0/NWE/CFWE PB[3] PA[1] PA[0] PA[2] PA[3] GND VDDIOM PB[5] PB[4] PD[12] PD[11] PD[10] PD[9] PB[8] PB[9] PB[7] PB[6] VDDCORE VDDIOP PD[4] PD[8] PD[5] PD[2] PD[3] PB[12] PB[13] PB[11] PB[10] VDDCORE VDDIOP PC[29] Pin J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name PD[1] PD[0] PC[30] PC[31] PB[14] PB[15] PB[17] PB[16] VDDUTMIC VDDIOP PC[28] PC[25] PC[24] PC[26] PC[27] PB[18] PB[19] PB[21] PB[20] PC[21] PC[20] PC[22] PC[23] PB[22] PB[23] PB[25] PB[24] PC[17] PC[16] PC[18] PC[19] PB[26] PB[27] PB[29] PB[28] PC[13] PC[12] PC[14] PC[15] PB[30] PB[31] A[1] A[11] A[15] CAS D[1] SDCKE D[5] D[8] D[15] PC[0] PB[0] PC[8] PC[9] PC[10] Pin P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PC[11] A[0] A[2] A[7] A[10] A[14] SDA10 D[0] VDDIOM D[6] D[9] NC VDDIOM PC[1] PB[1] PC[5] PC[6] PC[7] A[3] A[5] A[8] A[12] A[16] RAS D[2] D[4] D[7] D[10] D[14] VDDANA PA[17] PA[19] PC[2] PC[3] PC[4] A[4] A[6] A[9] A[13] A[17] SDWE D[3] SDCK D[11] D[12] D[13] TSADVREF PA[18] PA[20] PD[6] PD[7] GNDANA Table 4-2. Note: 1. Shaded cells define the pins powered by VDDIOM. 15 6289CS–ATARM–28-May-09 5. Power Considerations 5.1 Power Supplies The AT91SAM9R64/RL64 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). • VDDIOP pins: Power the Peripherals I/O lines; voltage ranges from 3.0V and 3.6V, 3.3V nominal. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDPLLA pin: Powers the PLL cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal. • VDDPLLB pin: Powers the UTMI PLL (480MHz) and OSC 12M cells; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V and 3.6V, 3.3V nominal. • VDDUTMIC pin: Powers the UTMI+ core; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDANA pin: Powers the ADC cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal. The power supplies VDDIOM and VDDIOP are identified in the pinout table and the PIO multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Separated ground pins are provided for VDDBU, VDDPLLA, VDDPLLB and VDDANA. These ground pins are respectively GNDBU, GNDPLLA, GNDPLLB and GNDANA. A common ground pin is provided for VDDUTMII and VDDUTMIC. This ground pin is GNDUTMI. Caution: VDDCORE and VDDIO constraints at startup to be checked in the Core Power Supply POR Characteristics in the Electical Characteristics section of the datasheet. 5.1.1 USB Power Supply Considerations To achieve the best performances on the UDPHS, care must be taken in the power supplies choice and especially on VDDPLLB,VDDUTMIC and VDDUTMII. The USB High speed requires power supplies with a ripple voltage < 20 mV on VDDPLLB and VDDUTMIC. The VDDUTMII powering the UTMI transceiver must also be filtered. It is highly recommended to use an LDO linear regulator to generate the 1.2 volts for both VDDPLLB and VDDUTMIC. VDDUTMII can be connected on the 3.3 volts of the system via an LC filter. The figure below gives an example of VDDPLLB, VDDUTMIC and VDDUTMII. 16 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 5-1. Example of PLL and USB Power Supplies VIN VIN CE 10µF VSS VOUT 10µF 1K ADJ 100K MIC5235YM5 0.1µF 1V2_USB 2.2µH 1V2_USB 0.1µF VDDPLLB 2.2µH 1V2_USB 0.1µF VDDUTMIC 2.2µH 3V3 0.1µF VDDUTMII 5.2 Programmable I/O Lines Power Supplies The power supplies pins VDDIOM support two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The maximum speed is MCK on the pin SDCK (SDRAM Clock) loaded with 30pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The maximum speed on the other signals of the External Bus Interface (control, address and data signals) is 50 MHz. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode. The PIO lines are supplied through VDDIOP and the speed of the signal that can be driven on them can reach 50 MHz with 50 pF load. 17 6289CS–ATARM–28-May-09 6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO is an output, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. All the JTAG signals are supplied with VDDIOP except JTAGSEL supplied by VDDBU. 6.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU. 6.3 Reset Pins NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and NTRST pin can be left unconnected. The NRST and NTRST pins integrates a permanent pull-up resistor of 100 k Ω t ypical to VDDIOP. The NRST signal is inserted in the Boundary Scan. 6.4 PIO Controllers All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product datasheet for more details. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shutdown Logic Pins The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 7. Processor and Architecture 7.1 ARM926EJ-S Processor • • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration Two Instruction Sets 18 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – – • • ARM High-performance 32-bit Instruction Set Thumb High Code Density 16-bit Instruction Set DSP Instruction Extensions 5-Stage Pipeline Architecture: – – – – – Instruction Fetch (F) Instruction Decode (D) Execute (E) Data Memory (M) Register Write (W) Virtually-addressed 4-way Associative Cache Eight words per line Write-through and Write-back Operation Pseudo-random or Round-robin Replacement Main Write Buffer with 16-word Data Buffer and 4-address Buffer DCache Write-back Buffer with 8-word Entries and a Single Address Entry Software Control Drain Access Permission for Sections Access Permission for large pages and small pages can be specified separately for each quarter of the page 16 embedded domains Arbitrates and Schedules AHB Requests Separate Masters for both instruction and data access providing complete Matrix system flexibility Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) • 4-Kbyte Data Cache, 4-Kbyte Instruction Cache – – – – • Write Buffer – – – • Standard ARM v4 and v5 Memory Management Unit (MMU) – – – • Bus Interface Unit (BIU) – – – – 7.2 Matrix Masters The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 7-1. Master 0 Master 1 Master 2 List of Bus Matrix Masters DMA Controller USB Device High Speed DMA LCD Controller DMA 19 6289CS–ATARM–28-May-09 Table 7-1. Master 3 Master 4 Master 5 List of Bus Matrix Masters Peripheral DMA Controller ARM926™ Instruction ARM926 Data 7.3 Matrix Slaves The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 List of Bus Matrix Slaves Internal ROM Internal SRAM LCD Controller User Interface UDP High Speed RAM External Bus Interface (EBI) Peripheral Bridge 7.4 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 7-3. AT91SAM9R64/RL64 Master to Slave Access Masters Slaves 0 DMA Controller 1 USB HS Device DMA 2 LCD Controller DMA 3 Peripheral DMA 4 ARM926 Instruction 5 ARM926 Data 0 1 2 3 4 5 Internal ROM Internal SRAM LCD Controller User Interface UDP High Speed RAM External Bus Interface Peripheral Bridge X X X X X X X X X X X X X X - X X X X X - X X X X X - 7.5 Peripheral DMA Controller (PDC) • Acting as one AHB Bus Matrix Master • Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. • Next Pointer support, prevents strong real-time constraints on buffer management. The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): 20 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary a. TWI0 Transmit Channel b. DBGU Transmit Channel c. USART3 Transmit Channel d. USART2 Transmit Channel e. USART1 Transmit Channel f. USART0 Transmit Channel g. AC97 Transmit Channel h. SPI Transmit Channel i. j. k. l. SSC1 Transmit Channel SSC0 Transmit Channel TWI0 Receive Channel DBGU Receive Channel m. ADC Receive Channel n. USART3 Receive Channel o. USART2 Receive Channel p. USART1 Receive Channel q. USART0 Receive Channel r. s. t. v. AC97 Receive Channel SPI Receive Channel SSC1 Receive Channel MCI Receive/Transmit Channel u. SSC0 Transmit Channel 7.6 DMA Controller • Acting as one Matrix Master • Embeds 2 channels • 16 bytes/FIFO for Channel Buffering • Linked List support with Status Write Back operation at End of Transfer • Word, Half-word, Byte transfer support 7.7 Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 21 6289CS–ATARM–28-May-09 8. Memories Figure 8-1. AT91SAM9R64/RL64 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF Internal Memory Mapping 0x0000 0000 Boot Memory (1) 1 MBytes 1 MBytes Notes : (1) Can be SRAM, ROM depending on BMS and the REMAP Command (2) Software programmable 256M Bytes 0x0010 0000 ITCM(2) 0x0020 0000 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF DTCM(2) 1 MBytes 256M Bytes 0x0030 0000 SRAM(2) 1 MBytes 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x0040 0000 256M Bytes 0x0050 0000 ROM LCD Controller User Interface 1 MBytes 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 1 MBytes 256M Bytes 0x0060 0000 UDPHS RAM 0x0070 0000 1 MBytes 0x4000 0000 EBI Chip Select 3/ NANDFlash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 256M Bytes 0x0FFF FFFF Undefined (Abort) System Controller Mapping 0xFFFF C000 0x4FFF FFFF 0x5000 0000 256M Bytes Peripheral Mapping 0xF000 0000 0x5FFF FFFF 0x6000 0000 Reserved Reserved 0xFFFF E600 256M Bytes 0xFFFA 0000 0x6FFF FFFF 0x7000 0000 0xFFFA 4000 DMAC TCO, TC1, TC2 16K Bytes 0xFFFF E800 512 Bytes ECC MCI 16K Bytes 0xFFFF EA00 512 Bytes 0xFFFA 8000 TWI0 0xFFFA C000 TWI1 0xFFFB 0000 USART0 0xFFFB 4000 USART1 0xFFFB 8000 USART2 16K Bytes 0xFFFF F400 16K Bytes 0xFFFF F200 16K Bytes 16K Bytes 0xFFFF EE00 0xFFFF EF10 0xFFFF F000 16K Bytes 0xFFFF EC00 SDRAMC SMC MATRIX AIC DBGU PIOA UART3 16K Bytes 0xFFFF F600 512 Bytes 512 bytes 512 Bytes 512 Bytes 512 Bytes Undefined (Abort) 0xFFFB C000 512 Bytes 0xFFFC 0000 SSC0 0xFFFC 4000 16K Bytes 0xFFFF F800 PIOB PIOC SSC1 16K Bytes 0xFFFF FA00 512 Bytes 512 bytes 2,048M Bytes 0xFFFC 8000 PIOD PWMC 16K Bytes 0xFFFF FC00 512 bytes 0xFFFC C000 SPI 0xFFFD 0000 ADC TouchScreen 0xFFFD 4000 UDPHS 0xFFFD 8000 AC97 0xFFFD C000 0xEFFF FFFF 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FD00 PMC RSTC 0xFFFF FD10 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes SHDC 0xFFFF FD20 RTTC 0xFFFF FD30 PITC 0xFFFF FD40 WDTC 0xFFFF FD50 0xFFFF FD60 SCKCR GPBR Reserved RTCC 0xF000 0000 0xFFFF C000 Reserved Internal Peripherals 256M Bytes 0xFFFF FFFF SYSC 16K Bytes 0xFFFF FD70 0xFFFF FE00 128 Bytes 0xFFFF FFFF 0xFFFF FFFF Reserved 22 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 8 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M byte of internal memory area. The bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. 8.1 Embedded Memories • 32 KB ROM – Single Cycle Access at full bus speed • 64 KB Fast SRAM – Single Cycle Access at full bus speed – Supports ARM926EJ-S TCM interface at full processor speed 8.1.1 Internal Memory Mapping Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap status (RCBx bit) and the BMS state at reset. Table 8-1. Address BMS = 1 0x0000 0000 Notes: ROM BMS =0 EBI_NCS0(2) SRAM Internal Memory Mapping RCBx(1) = 0 RCBx(1) = 1 1. x = 0 to maximum Master number. 2. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers. 8.1.1.1 Internal SRAM The AT91SAM9R64/RL64 product embeds a total of 64Kbyte high-speed SRAM split in 4 blocks of 16KBytes. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. This Internal SRAM can be allocated to threes areas. Its Memory Mapping is detailed in Table 82. • Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR configuration register located in the Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000. 23 6289CS–ATARM–28-May-09 • Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000. • Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 64Kbyte SRAM size available, the amount of memory assigned to each block is software programmable as a multiple of 16K Bytes according to Table 8-2. This Table provides the size of the Internal SRAM C according to the size of the Internal SRAM A and the Internal SRAM B. Table 8-2. Internal SRAM Block Size Internal SRAM A (ITCM) Size Remaining Internal SRAM C 0 0 Internal SRAM B (DTCM) size 16K Bytes 32K Bytes 64K Bytes 48K Bytes 32K Bytes 16K Bytes 48K Bytes 32K Bytes 16K Bytes 32K Bytes 32K Bytes 16K Bytes 0K Bytes At reset, the whole memory is assigned to Internal SRAM C. The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16-Kbyte block organization may affect the previous configuration from a software point of view. Table 8-3 illustrates different configurations and the related 16-Kbyte blocks (RB0 to RB3) assignments. Table 8-3. Decoded Area 16-Kbyte Block Allocation example Configuration examples and related 16-Kbyte block assignments Address I = 0K D = 0K A = 64K(1) I = 16K D = 0K A = 48K RB1 I =32K D = 0K A = 32K RB1 RB0 RB3 RB3 I = 0K D = 16K A = 48K I = 16K D = 16K A = 32K RB1 I = 32K D = 16K A = 16K RB1 RB0 RB3 RB3 RB2 RB3 RB2 RB1 RB0 RB3 RB2 RB0 RB3 RB2 RB2 RB1 RB0 RB2 RB0 RB2 RB1 RB0 RB3 RB2 RB0 I = 0K D = 32K A = 32K I = 16K D = 32K A = 16K RB1 I = 32K D = 32K A = 0K RB1 RB0 RB3 RB2 Internal SRAM A (ITCM) Internal SRAM B (DTCM) 0x0010 0000 0x0010 4000 0x0020 0000 0x0020 4000 0x0030 0000 Internal SRAM C (AHB) Note: 0x0030 4000 0x0030 8000 0x0030 C000 1. Configuration after reset. 24 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary When accessed from the AHB, the internal Fast SRAM is single cycle accessible at full matrix speed (MCK). When accessed from the processor’s TCM Interface, they are also single cycle accessible at full processor speed. 8.1.1.2 Internal ROM The AT91SAM9R64/RL64 embeds an Internal ROM, which contains the SAM-BA program. At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset and before the Remap Command. 8.1.2 Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters. REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This is done by software once the system has boot. Refer to the Bus Matrix Section for more details. When REMAP = 0 BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done by a hardware way at reset. Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The AT91SAM9R64/RL64 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 8.1.2.1 BMS = 1, boot on embedded ROM The system boots on Boot Program. • Boot on on-chip RC • Enable the 32768 Hz oscillator • Auto baudrate detection • Downloads and runs an application from external storage media into internal SRAM • Downloaded code size depends on embedded SRAM size • Automatic detection of valid application • Bootloader on a non-volatile memory – SDCard (boot ROM does not support high-capacity SDCards) – NAND Flash – SPI DataFlash® connected on NPCS0 of the SPI0 • SAM-BA Boot in case no valid program is detected in external NVM, supporting – Serial communication on a DBGU – USB Device HS Port 8.1.2.2 BMS = 0, boot on external memory • Boot on on-chip RC 25 6289CS–ATARM–28-May-09 • Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. For optimization purposes, nothing else is done. To speed up the boot sequence user programmed software should perform a complete configuration: • Enable the 32768 Hz oscillator if best accuracy needed • Program the PMC (main oscillator enable or bypass mode) • Program and Start the PLL • Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock • Switch the main clock to the new value 8.2 External Memories The AT91SAM9R64/RL64 features one External Bus Interface to offer interface to a wide range of external memories and to any parallel peripheral. 8.2.1 External Bus Interface • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – SLC Nand Flash ECC Controller • Additional logic for NAND Flash and CompactFlashTM • Optional Full 32-bit External Data Bus • Up to 26-bit Address Bus (up to 64MBytes linear per chip select) • Up to 6 chips selects, Configurable Assignment: – Static Memory Controller on NCS0 – SDRAM Controller (SDCS) or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3, Optional NAND Flash support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlashM support 8.2.2 Static Memory Controller • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported 26 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 8.2.3 SDRAM Controller • Supported devices: – Standard and Low Power SDRAM (Mobile SDRAM) – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • SDRAM CAS Latency of 1, 2 and 3 supported • Auto Precharge Command not used 8.2.4 NAND Flash Error Corrected Code Controller • Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select • Single bit error correction and 2-bit Random detection. • Automatic Hamming Code Calculation while writing – ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being detected erroneous – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages 27 6289CS–ATARM–28-May-09 9. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface embeds also the registers allowing to configure the Matrix and a set of registers configuring the EBI chip select assignment and the voltage range for external memories. 9.1 System Controller Mapping As shown in Figure 8-1, the System Controller’s peripherals are all mapped within the highest 16K bytes of the 4 Gbyte address space, between addresses 0xFFFF C000 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. This allows addressing all the registers of the System Controller from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of +/4kbytes. 28 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 9.2 Block Diagram System Controller Block Diagram System Controller VDDCORE Powered irq0-irq2 fiq periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC rtt_alarm VDDCORE POR por_ntrst jtag_nreset Debug Unit Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq Figure 9-1. dbgu_irq dbgu_txd pit_irq proc_nreset PCK debug jtag_nreset wdt_irq MCK periph_nreset rstc_irq periph_nreset proc_nreset backup_nreset VDDBU Powered Boundary Scan TAP Controller Bus Matrix NRST Reset Controller VDDBU VDDBU POR SLCK Real-Time Clock Real-Time Timer rtc_irq rtc_alarm rtt_irq rtt_alarm HSCK periph_clk[22] Shutdown Controller 4 General-purpose Backup Registers SCKCR SLCK XIN XOUT int 12MHz MAIN OSC UPLL HSCK PLLRCA PLLA periph_nreset periph_nreset periph_nreset periph_clk[2..4] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD21 periph_irq[2..4] irq fiq dbgu_txd Embedded Peripherals periph_irq[6..24] in out enable PLLACK MAINCK PCK Power Management Controller MCK pmc_irq idle periph_clk[6..24] periph_nreset periph_irq[22] USB High Speed Device Port SLCK backup_nreset SLCK backup_nreset SLCK SHDN WKUP backup_nreset rtc_alarm rtt_alarm RC OSC XIN32 XOUT32 SLOW CLOCK OSC periph_clk[2..24] pck[0-1] PIO Controllers 29 6289CS–ATARM–28-May-09 9.3 Reset Controller The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin output. It is capable to shape a reset signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a manual reset. The configuration of the Reset Controller is saved as supplied on VDDBU. 9.4 Shutdown Controller The Shutdown Controller is supplied on VDDBU and allows a software-controllable shut down of the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the SHDN pin, and thus wakes up the system power supply. 9.5 Clock Generator The Clock Generator is made up of: • One low-power 32768 Hz Slow Clock Oscillator with bypass mode • One low-power RC oscillator • One 12 MHz Main Oscillator, which can be bypassed • One 480 MHz PLL (UPLL or PLLB) providing a clock for the USB High Speed Device Controller • One 80 to 240 MHz programmable PLL, providing the PLL Clock (PLLCK). This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 1 MHz. 30 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 9-2. Clock Generator Block Diagram Clock Generator RCEN On Chip RC OSC XIN32 XOUT32 Slow Clock Oscillator Slow Clock SLCK OSCSEL OSC32EN OSC32BYP XIN XOUT 12M Main Oscillator Main Clock MAINCK UPLL (PLLB) PLL and Divider HSCK PLLRCA PLL Clock PLLCK Status Control Power Management Controller 9.6 9.6.1 Slow Clock Selection Description The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external slow clock on XIN32. Configuration is located in the slow clock control register (SCKCR) located at address 0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is present. Refer to the “Clock Generator” section for more details. 9.7 Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock PCK • the Master Clock MCK, in particular to the Matrix and the memory interfaces • the USB Device HS Clock HSCK • independent peripheral clocks, typically at the frequency of MCK • two programmable clock outputs: PCK0 and PCK1 This allows the software control of five flexible operating modes: • Normal Mode, processor and peripherals running at a programmable frequency • Idle Mode, processor stopped waiting for an interrupt • Slow Clock Mode, processor and peripherals running at low frequency 31 6289CS–ATARM–28-May-09 • Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9R64/RL64 Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK PCK int Idle Mode MCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF periph_clk[..] Programmable Clock Controller ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] SLCK MAINCK PLLCK 9.8 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux®/WindowsCE® compliant tick generator 9.9 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • Windowed, prevents the processor to be in a dead-lock on the watchdog access 9.10 Real-Time Timer • Real-Time Timer, allowing backup of time with different accuracies – 32-bit Free-running back-up Counter – Integrates a 16-bit programmable prescaler running on slow clock – Alarm Register capable to generate a wake-up of the system through the Shut Down Controller 9.11 Real-Time Clock • Low power consumption • Full asynchronous design 32 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 9.12 General-Purpose Backed-up Registers • Four 32-bit backup general-purpose registers 9.13 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive • One External Sources plus the Fast Interrupt signal • 8-level Priority Controller – Drives the Normal Interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode – Easy debugging by preventing automatic operations when protect modeIs are enabled • Fast Forcing – Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 9.14 Debug Unit • Composed of two functions – Two-pin UART – Debug Communication Channel (DCC) support • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes 33 6289CS–ATARM–28-May-09 – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE Interface 9.15 Chip Identification • Chip ID: 0x019B03A0 • JTAG ID: 0x05B2003F • ARM926 TAP ID: 0x0792603F 9.16 PIO Controllers • 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, controlling a maximum of 118 I/O Lines • Each PIO Controller controls up to 32 programmable I/O Lines – PIOA has 32 I/O Lines – PIOB has 32 I/O Lines – PIOC has 32 I/O Lines – PIOD has 22 I/O Lines • Fully programmable through Set/Clear Registers • Multiplexing of two peripheral functions per I/O Line • For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 10. Peripherals 10.1 Peripheral Mapping As shown in Figure 8-1, the Peripherals are mapped in the upper 256M bytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. 34 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.2 Peripheral Identifiers The Table 10-1 defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. AT91SAM9R64/RL64 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC PIOD US0 US1 US2 US3 MCI TWI0 TWI1 SPI SSC0 SSC1 TC0 TC1 TC2 PWMC TSADCC DMAC UDPHS LCDC AC97 AIC Note: Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D USART 0 USART 1 USART 2 USART 3 Multimedia Card Interface Two-Wire Interface 0 Two-Wire Interface 1 Serial Peripheral Interface Synchronous Serial Controller 0 Synchronous Serial Controller 1 Timer Counter 0 Timer Counter 1 Timer Counter 2 Pulse Width Modulation Controller Touch Screen ADC Controller DMA Controller USB Device High Speed LCD Controller (AT91SAM9RL64 only) AC97 Controller Reserved Advanced Interrupt Controller IRQ External Interrupt FIQ Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25-30 31 Setting AIC, SYSIRQ, LCDC and IRQ bits in the clock set/clear registers of the PMC has no effect. 35 6289CS–ATARM–28-May-09 10.3 10.3.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-time Timer • the Real-time Clock • the Watchdog Timer • the Reset Controller • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.3.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.4 Peripherals Signals Multiplexing on I/O Lines The AT91SAM9R64/RL64 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplexes the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only, might be duplicated within the both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case for pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. The AT91SAM9RL64 and AT91SAM9R64 do not have the same peripheral signal multiplexing, each one follows. 36 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.4.1 10.4.1.1 Table 10-2. AT91SAM9RL64 PIO Multiplexing AT91SAM9RL64 PIO Controller A Multiplexing AT91SAM9RL64 Multiplexing on PIO Controller A PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A MC_DA0 MC_CDA MC_CK MC_DA1 MC_DA2 MC_DA3 TXD0 RXD0 SCK0 RTS0 CTS0 TXD1 RXD1 TXD2 RXD2 TD0 RD0 AD0 AD1 AD2 AD3 DRXD DTXD TWD0 TWCK0 MISO MOSI SPCK NPCS0 RTS2 CTS2 NWAIT TF1 TK1 IRQ RF0 RTS1 CTS1 SCK3 TD1 RD1 RF1 RK1 RK0 TCLK0 TIOA0 TIOB0 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDANA VDDANA VDDANA VDDANA VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Application Usage Function Comments 37 6289CS–ATARM–28-May-09 10.4.1.2 Table 10-3. AT91SAM9RL64 PIO Controller B Multiplexing AT91SAM9RL64 Multiplexing on PIO Controller B PIO Controller B Application Usage Reset State I/O I/O A21 A22 I/O I/O I/O NPCS1 PWM0 PWM1 FIQ I/O I/O I/O A25 A18 A19 A20 PCK0 ADTRG A23 A24 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function Comments I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Peripheral A TXD3 RXD3 A21/NANDALE A22/NANDCLE NANDOE NANDWE NCS3/NANDCS NCS4/CFCS0 CFCE1 CFCE2 A25/CFRNW A18 A19 A20 A23 A24 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Peripheral B 38 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.4.1.3 Table 10-4. AT91SAM9RL64 PIO Controller C Multiplexing AT91SAM9RL64 Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Peripheral A TF0 TK0 LCDMOD LCDCC LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 TIOA1 TIOB1 TCLK1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 LCDPWR PWM0 PWM1 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Application Usage Function Comments 39 6289CS–ATARM–28-May-09 10.4.1.4 Table 10-5. AT91SAM9RL64 PIO Controller D Multiplexing AT91SAM9RL64 Multiplexing on PIO Controller D PIO Controller D Application Usage Reset State I/O I/O SCK1 CTS3 RTS3 PWM2 I/O I/O I/O I/O I/O I/O PWM3 NPCS3 TIOA2 TIOB2 PCK1 NPCS3 PWM0 PWM1 PWM2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDANA VDDANA VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Function Comments I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 Peripheral A NCS2 AC97_FS AC97_CK AC97_TX AC97_RX DTXD AD4 AD5 NPCS2 SCK2 TWD1 TWCK1 PWM2 NCS5/CFCS1 DSR0 DTR0 DCD0 RI0 PWM3 PCK0 PCK1 TCLK2 Peripheral B Comments 40 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.4.2 Note: AT91SAM9R64 PIO Multiplexing In Table 10-6, Table 10-7, Table 10-8 and Table 10-9, shaded cells indicate I/O lines that are NOT available on the AT91SAM9R64. 10.4.2.1 Table 10-6. AT91SAM9R64 PIO Controller A Multiplexing AT91SAM9R64 Multiplexing on PIO Controller A PIO Controller A Application Usage Reset State I/O I/O I/O TCLK0 TIOA0 TIOB0 I/O I/O I/O I/O I/O NA NA RK0 I/O I/O I/O I/O I/O I/O I/O I/O RTS1 CTS1 NA I/O RF0 I/O I/O I/O I/O I/O I/O I/O NA NA IRQ I/O VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Reserved Reserved I/O I/O VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Reserved Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Reserved Reserved Function Comments I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A MC_DA0 MC_CDA MC_CK MC_DA1 MC_DA2 MC_DA3 TXD0 RXD0 NA NA CTS0 TXD1 RXD1 TXD2 RXD2 TD0 RD0 AD0 AD1 AD2 NA DRXD DTXD TWD0 TWCK0 MISO MOSI SPCK NPCS0 NA NA NWAIT Peripheral B 41 6289CS–ATARM–28-May-09 10.4.2.2 Table 10-7. AT91SAM9R64 PIO Controller B Multiplexing AT91SAM9R64 Multiplexing on PIO Controller B PIO Controller B Application Usage Reset State I/O I/O A21 A22 I/O I/O I/O NPCS1 PWM0 PWM1 FIQ I/O I/O I/O A25 A18 A19 A20 PCK0 ADTRG NA A23 A24 Power Supply VDDIOP VDDIOP VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Reserved Function Comments I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16PB31 Peripheral A TXD3 RXD3 A21/NANDALE A22/NANDCLE NANDOE NANDWE NCS3/NANDCS NCS4/CFCS0 CFCE1 CFCE2 A25/CFRNW A18 A19 A20 A23 A24 NA Peripheral B 42 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.4.2.3 Table 10-8. AT91SAM9R64 PIO Controller C Multiplexing AT91SAM9R64 Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2PC31 Peripheral A TF0 TK0 NA NA Peripheral B Reset State I/O I/O Power Supply VDDIOP VDDIOP Reserved Application Usage Function Comments 10.4.2.4 Table 10-9. AT91SAM9R64 PIO Controller D Multiplexing AT91SAM9R64 Multiplexing on PIO Controller D PIO Controller D Application Usage Comments Reset State Power Supply Function Comments Reserved I/O I/O I/O I/O VDDIOP VDDIOP VDDIOP VDDIOP I/O Line PD0PD17 PD18 PD19 PD20 PD21 Peripheral A NA PWM3 PCK0 PCK1 TCLK2 Peripheral B NA 43 6289CS–ATARM–28-May-09 11. Embedded Peripherals Overview 11.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device 11.2 Two-wire Interface (TWI) • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations • Supports either master or slave modes • Compatible with Standard Two-wire Serial Memories • Master, Multi-master and Slave Mode Operation • Bit Rate: Up to 400 Kbits • General Call Supported in Slave mode • Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only – One Channel for the Receiver, One Channel for the Transmitter – Next Buffer Support 11.3 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first 44 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 11.4 Serial Synchronous Controller (SSC) • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 11.5 AC97 Controller • Compatible with AC97 Component Specification V2.2 • Capable to Interface with a Single Analog Front end • Three independent RX Channels and three independent TX Channels – One RX and one TX channel dedicated to the AC97 Analog Front end control – One RX and one TX channel for data transfers, associated with a PDC – One RX and one TX channel for data transfers with no PDC • Time Slot Assigner allowing to assign up to 12 time slots to a channel • Channels support mono or stereo up to 20 bit sample length – Variable sampling rate AC97 Codec Interface (48KHz and below) 11.6 Timer Counter (TC) • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation 45 6289CS–ATARM–28-May-09 – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 11.7 Pulse Width Modulation Controller (PWM) • 4 channels, one 16-bit counter per channel • Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter outputs • Independent channel programming – Independent Enable Disable Commands – Independent Clock Selection – Independent Period and Duty Cycle, with Double Bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 11.8 Multimedia Card Interface (MCI) • Compatibility with MultiMedia Card Specification Version 3.31 • Compatibility with SD Memory Card Specification Version 1.0 • Compatibility with SDIO Specification Version V1.1 • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used • MCI has one slot supporting – One MultiMediaCard bus (up to 30 cards) or – One SD Memory Card – One SDIO Card • Support for stream, block and multi-block data read and write 11.9 USB High Speed Device Port (UDPHS) • USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver • Embedded 4K-byte dual-port RAM for endpoints • Embedded 6 channels DMA controller • Suspend/Resume logic • Up to 3 banks for isochronous and bulk endpoints • Seven endpoints: 46 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – Endpoint 0: 64 bytes, 1 bank mode – Endpoint 1 & 2: 1024 bytes, 2 banks mode, HS isochronous capable, DMA – Endpoint 3 & 4: 1024bytes, 3 banks mode, DMA – Endpoint 5 & 6: 1024 bytes, 3 banks mode, HS isochronous capable, DMA 11.10 LCD Controller (LCDC) • Single and Dual scan color and monochrome passive STN LCD panels supported • Single scan active TFT LCD panels supported. • 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported • Up to 24-bit single scan TFT interfaces supported • Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays • 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN • 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN • 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048x2048 11.11 Touch Screen Analog-to-digital Converter (TSADCC) • 6-channel ADC • Support 4-wire resistive Touch Screen • 10-bit 384 Ksamples/sec. Successive Approximation Register ADC • -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity • Integrated 6-to-1 multiplexer, offering eight independent 3.3V analog inputs • External voltage reference for better accuracy on low voltage inputs • Individual enable and disable of each channel • Multiple trigger sources – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 47 6289CS–ATARM–28-May-09 12. Package Drawings Figure 12-1. 144-ball BGA Package Drawing 48 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 12-2. 217-ball LFBGA Package Drawing 49 6289CS–ATARM–28-May-09 13. AT91SAM9R64/RL64 Ordering Information Table 13-1. AT91SAM9R64/RL64 Ordering Information MRL A A Package LFBGA144 LFBGA217 Package Type Green Green Temperature Operating Range Industrial -40°C to 85°C Ordering Code AT91SAM9R64-CU AT91SAM9RL64-CU 50 AT91SAM9R64/RL64 Preliminary 6289CS–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 14. Revision History Change Request Ref. 6142 RFO 6345 6345 6345 5935 5846 5276 Doc. Rev Comments Product Overview: “Features” on page 1, removed mid-level Embedded Trace Macrocell feature “Features” on page 1, updated figures on CPU speed “Features” on page 1, updated SDIO and MMC version Removed paragraph Section 5.2 “Power Consumption”. Section 6.5 “Shutdown Logic Pins”, removed information on the shutdown pin Section 8.1.2.1 “BMS = 1, boot on embedded ROM”, – SDCard, (boot ROM does not support high capacity SDCards) clarification added. “Features” “Debug Unit (DBGU)” on page 2, updated Figure 8-1 “AT91SAM9R64/RL64 Memory Mapping”, Internal Memory Mapping updated. Table 7-2, “List of Bus Matrix Slaves”, Table 7-3, “AT91SAM9R64/RL64 Master to Slave Access”, Slave 3 updated. Section 5.1 “Power Supplies”, updated with caution on VDDCORE and VDDIO constraints Section 5.1.1 “USB Power Supply Considerations” and Figure 5-1 added to datasheet. Section 5.2 “Power Consumption”, first two sentences updated. Table 3-1, “Signal Description List”, additional comments on BMS. SHDN comments updated. Table 10-3 and Table 10-7 PB8, PB9 Peripheral A column: typos corrected, “CFCE1”, “CFCE2”. First issue 6289CS 6289BS 5291 5420 5388 5423 rfo 5788 6289AS 51 6289CS–ATARM–28-May-09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com www.atmel.com/AT91SAM Technical Support AT91SAM Support Sales Contacts www.atmel.com/contacts/ Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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