AT91SAM9R64_1

Features • Incorporates the ARM926EJ-S™ ARM® Thumb® Processor – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer – 265 MIPS at 240 MHz – Memory Management Unit – EmbeddedICE™ In-circuit Emulation, Debug Communication Channel Support Multi-layer AHB Bus Matrix for Large Bandwidth Transfers – Six 32-bit-layer Matrix – Boot Mode Select Option, Remap Command One 32-KByte internal ROM, Single-cycle Access at Maximum Speed One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed – 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB Bus Matrix – Single-cycle Accessible on AHB Bus at Bus Speed – Single-cycle Accessible on TCM Interface at Processor Speed 2-channel DMA – Memory to Memory Transfer – 16 Bytes FIFO – LInked List External Bus Interface (EBI) – EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash® LCD Controller (for AT91SAM9RL64 only) – Supports Passive or Active Displays – Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode – Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Virtual Screen Support High Speed (480 Mbit/s) USB 2.0 Device Controller – On-Chip High Speed Transceiver, UTMI+ Physical Interface – Integrated FIFOs and Dedicated DMA – 4 Kbyte Configurable Integrated DPRAM Fully-featured System Controller, including – Reset Controller, Shutdown Controller – Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock Reset Controller (RSTC) – Based on Two Power-on Reset Cells – Reset Source Identification and Reset Output Control Shutdown Controller (SHDC) – Programmable Shutdown Pin Control and Wake-up Circuitry Clock Generator (CKGR) – Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock – 12 MHz On-chip Oscillator for Main System Clock and USB Clock – One PLL up to 240 MHz • • • AT91 ARM Thumb Microcontrollers AT91SAM9R64 AT91SAM9RL64 Preliminary • • • • • • • • 6289C–ATARM–28-May-09 – One PLL 480 MHz Optimized for USB HS • Power Management Controller (PMC) – Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals Advanced Interrupt Controller (AIC) – Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – One External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected Debug Unit (DBGU) – 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention – Mode for General Purpose 2-wire UART Serial Communication Periodic Interval Timer (PIT) – 20-bit Interval Timer plus 12-bit Interval Counter Watchdog Timer (WDT) – Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock Real-time Timer (RTT) – 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler Real-time Clock (RTC) – Time, Date and Alarm 32-bit Parallel Load – Low Power Consumption – Programmable Periodic Interrupt One 6-channel 10-Bit Analog-to-Digital Converter – Touch Screen Interface Compatible with Industry Standard 4-wire Sensitive Touch Panels Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD) – 118 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os for 217-ball BGA Package – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output 22-channel Peripheral DMA Controller (PDC) One MultiMedia Card Interface (MCI) – SDCard/SDIO 1.0 and MultiMediaCard™ 4.3 Compliant – Automatic Protocol Control and Fast Automatic Data Transfers with PDC Two Synchronous Serial Controllers (SSC) – Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer One AC97 Controller (AC97C) – 6-channel Single AC97 Analog Front End Interface, Slot Assigner Four Universal Synchronous/Asynchronous Receiver Transmitters (USART) – Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation, Manchester Encoding/Decoding – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support One Master/Slave Serial Peripheral Interface (SPI) – 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects – High-speed Synchronous Communications One Three-channel 16-bit Timer/Counter (TC) – Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability One Four-channel 16-bit PWM Controller (PWMC) Two Two-wire Interfaces (TWI) – Compatible with Standard Two-wire Serial Memories – One, Two or Three Bytes for Slave Address – Sequential Read/Write Operations • • • • • • • • • • • • • • • • • 2 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Master, Multi-master and Slave Mode Operation Bit Rate: Up to 400 Kbits General Call Supported in Slave Mode Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only (TWI0 only) SAM-BA® Boot Assistant – Default Boot Program – Interface with SAM-BA Graphic User Interface IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins Required Power Supplies: – 1.08 to 1.32V for VDDCORE, VDDUTMIC, VDDPLLB and VDDBU – 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMII and VDDIOP – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package – – – – • • • • 1. Description The AT91SAM9R64/RL64 device is based on the integration of an ARM926EJ-S processor with a large fast SRAM and a wide range of peripherals. The AT91SAM9R64/RL64 embeds one USB Device High Speed Controller, one LCD Controller (for AT91SAM9RL64 only), one AC97 controller, a 2-channel DMA Controller, four USARTs, two SSCs, one SPI, two TWIs, three Timer Counter channels, a 4-channel PWM generator, one Multimedia Card interface and a 6-channel Analog-to-digital converter that also provides resistive touch screen management. The AT91SAM9R64/RL64 is architectured on a 6-layer bus matrix. It also features an External Bus Interface capable of interfacing with a wide range of memory and peripheral devices. Some features are not available for AT91SAM9R64 in the 144-ball BGA package. Separate block diagrams and PIO multiplexing are provided in this document. Table 1-1 lists the features and signals of AT91SAM9RL64 that are not available or partially available for AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified. Table 1-1. Feature Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Signal AC97FS AC97CK AC97TX AC97RX D16-D31 NCS2 NCS5/CFCS1 LCDMOD LCDCC LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0-LCDD23 Peripheral A PD1 PD2 PD3 PD4 PB16-PB31 PD0 PD13 PC2 PC3 PC4 PC5 PC6 PC7 PC8-PC31 Peripheral B AC97 Full - EBI Partial - LCDC Full - 3 6289C–ATARM–28-May-09 Table 1-1. Feature PWM SPI Unavailable or Partially Available Features and Signals in AT91SAM9R64 Full/Partial Partial Partial Signal PWM2 NPCS2 NPCS3 RF1 RK1 TD1 RD1 TK1 TF1 AD3YM GPAD4 GPAD5 TIOA1 TIOB1 TCLK1 TIOA2 TIOB2 TWD1 TWCK1 SCK0 RTS0 CTS0 DSR0 DTR0 DCD0 RI0 SCK1 SCK2 RTS2 CTS2 SCK3 RTS3 CTS3 Peripheral A PD5 and PD12 PD8 PD9 and PD13 PA8 PA9 PA13 PA14 PA29 PA30 PC29 PC30 PC31 PD10 PD11 Peripheral B - SSC1 Full - Touchscreen ADC Partial PA20 PD6 PD7 TC Partial - TWI Full PD10 PD11 PA8 PA9 PA10 PD14 PD15 PD16 PD17 PD9 PA29 PA30 - USART0 Partial - USART1 USART2 Partial Partial PD2 PA20 PD3 PD4 USART3 Partial 4 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Figure 2-1. TD TI DO TM S T C RTK CK NT RS T J TA G SE L 2. Block Diagrams MASTER SLAVE TST System Controller JTAG Selection and Boundary Scan HS UTMI Transceiver FIQ In-Circuit Emulator BM G N I II IC TM TM TM PMPM UU D D SD SD D D VDD VBG DFS DFS DH DH V S 6289C–ATARM–28-May-09 D U AIC ARM926EJ-S Processor TCM Interface ITCM DTCM ICache DCache 4 Kbytes 4 Kbytes CompactFlash NAND Flash & ECC EBI USB Device HS IRQ DRXD DTXD DBGU PDC AT91SAM9R64 Block Diagram PCK0-PCK1 PLLRCA PLLA I D DMA XIN XOUT 12 MHz OSC PMC UPLL 5-layer AHB Bus Matrix SDRAM Controller D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NWAIT A23-A24, A18-A20 WDT PIT RC SRAM 64K Bytes ROM 32K Bytes APB Peripheral Bridge 2-channel DMA Peripheral DMA Controller XIN32 XOUT32 32 kHz OSC 4 GPBREG A21/NANDALE A22/NANDCLE A25/CFRNW RTT SHDN WKUP SHDC PDC PDC TWI0 RTC PDC PDC SPI PWM Static Memory Controller PDC SSC0 PDC NCS4/CFCS0 VDDBU POR NCS3/NANDCS VDDCORE POR RSTC MCI NRST USART0 USART1 USART2 USART3 TC0 TC1 TC2 3-channel 10-bit ADC CFCE1-CFCE2 NANDOE, NANDWE PIOA PIOB PIOC PIOD 0 DA A3 A K D0 K0 -D CD C W C T TW C 0 0 0 0 0 K0 TK TF TD RD RF R A TS 1 S1 33 013 0 2 A0 B0 S1 CK SI ISO MMM TS RT XD XD LK LK IO IO W PC SP MO M RT PW PW P 0- D0TC TC T T -N S0 XD TX R PC N D G0 12 TR AD AD AD EF A N R AN DA DV DD GN SA V T AT91SAM9R64/RL64 Preliminary 5 Figure 2-2. TD TDI O TM S T C RTK CK NT RS T J TA G SE L BM S MASTER SLAVE I II IC TM M M PMPM UTT D DU DU G SD SD SD SD N FFHH G VD VD VB D D D D TST System Controller JTAG Selection and Boundary Scan HS UTMI Transceiver FIQ LC LCDD 0 LCDV -LC S LD Y D CDHS NC D2 3 Y LD DO NC T LCDE CK N LCDC C LCDP DMWR O D 6 AIC In-Circuit Emulator EBI ARM926EJ-S Processor LCDC ICache DCache 4 Kbytes 4 Kbytes IRQ DRXD DTXD PDC DBGU USB Device HS AT91SAM9RL64 Block Diagram PCK0-PCK1 CompactFlash NAND Flash & ECC PLLRCA PLLA PMC I D TCM Interface ITCM DTCM DMA DMA XIN XOUT OSC 12M UPLL 6-layer AHB Bus Matrix PIT SDRAM Controller D0-D15 A0/NBS0 A1/NBS2/NWR2 A2-A15 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NWAIT A23-A24 A18-A20 WDT RC 4 GPBREG XIN32 XOUT32 OSC 32K SRAM 64K Bytes ROM 32K Bytes APB Peripheral Bridge Peripheral DMA Controller 2-channel DMA A21/NANDALE A22/NANDCLE A25/CFRNW D16-D31 NCS4/CFCS0 RTT RTC PDC PDC RSTC MCI TWI0 TWI1 AT91SAM9R64/RL64 Preliminary Static Memory Controller PDC PDC PDC PDC SPI PWM SHDN WKUP SHDC PDC AC97 VDDBU POR NCS5/CFCS1 NCS3/NANDCS NCS2 Touch Screen Controller SSC0 SSC1 6-channel 10-bit ADC VDDCORE POR NRST USART0 USART1 USART2 USART3 TC0 TC1 TC2 CFCE1-CFCE2 NANDOE, NANDWE PIOA PIOB PIOD PIOC 0 DA 3 3 222 K S X X 1 1 1 1 1 K1 G A3 A K 0 0 D1 1 S3 S K3 D3 3 D0 I0 0 0 S3 K I O FAN 45 LK A B C F R T K TF D D F R TR 0X P 1X M 2Y P 3Y M AD AD RE AN DA -D CD C WD CK W CK CT -RT SC RX TXD C R SR TR PC PC OSMIS WM C IO IO 97 97 97 97 0-T 0- -T -R -R 0D D -N S M T W T TW 0- S0 0- 0- 0- D -P -T 0-T 0-T AC AC AC AC TK TF TD0 D0RF0RK AD AD AD AD AD GP GP DV DD GN T 0 0 AV S R TS RT CK XD XD M LK0 OA OB S T C SR T TS I PC PW TC T TI N 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 3. Signal Description Table 3-1 gives details on the signal name classified by peripheral. Table 3-1. Signal Name Signal Description List Function Type Power Supplies Active Level Comments VDDIOM VDDIOP VDDUTMII VDDUTMIC GNDUTMI VDDBU GNDBU VDDPLLA GNDPLLA VDDPLLB GNDPLLB VDDANA GNDANA VDDCORE GNDCORE GND EBI I/O Lines Power Supply Peripherals I/O Lines Power Supply USB UTMI+ Interface Power Supply USB UTMI+ Core Power Supply USB UTMI Ground Backup I/O Lines Power Supply Backup Ground PLL Power Supply PLL Ground UTMI PLL and OSC 12M Power Supply UTMI PLL and OSC 12M Ground ADC Analog Power Supply ADC Analog Ground Core Chip Power Supply Ground Ground Power Power Power Power Ground Power Ground Power Ground Power Ground Power Ground Power Ground Ground Clocks, Oscillators and PLLs 1.65V to 3.6V 3.0V to 3.6V 3.0V to 3.6V 1.08V to 1.32V 1.08V to 1.32V 3.0V to 3.6V 1.08 V to 1.32V 3.0V to 3.6V 1.08V to 1.32V XIN XOUT XIN32 XOUT32 VBG PLLRCA PCK0 - PCK1 Main Oscillator Input Main Oscillator Output Slow Clock Oscillator Input Slow Clock Oscillator Output Bias Voltage Reference PLL A Filter Programmable Clock Output Input Output Input Output Analog Input Output Shutdown, Wakeup Logic SHDN WKUP Shutdown Control Wake-Up Input Output Input ICE and JTAG Driven at 0V only. 0: The device is in backup mode. 1: The device is running (not in backup mode.) Accept between 0V and VDDBU TCK TDI TDO TMS JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select JTAG Selection Input Input Output Input Input No pull-up resistor No pull-up resistor No pull-up resistor Pull-down resistor 7 6289C–ATARM–28-May-09 Table 3-1. Signal Name NTRST Signal Description List (Continued) Function Test Reset Signal Type Input Reset/Test Active Level Low Comments Pull-up resistor. NRST TST Microcontroller Reset Test Mode Select I/O Input Low Pull-up resistor Pull-down resistor Must be connected to GND or VDDIOP. No pullup resistor BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP BMS Boot Mode Select Input Debug Unit - DBGU DRXD DTXD Debug Receive Data Debug Transmit Data Input Output Advanced Interrupt Controller - AIC IRQ FIQ External Interrupt Input Fast Interrupt Input Input Input PIO Controller - PIOA - PIOB - PIOC-PIOD PA0 - PA31 PB0 - PB31 PC0 - PC31 PD0 - PD21 Parallel IO Controller A Parallel IO Controller B Parallel IO Controller C Parallel IO Controller D I/O I/O I/O I/O External Bus Interface - EBI D0 - D31 A0 - A25 NWAIT Data Bus Address Bus External Wait Signal I/O Output Input Low Pulled-up input at reset. D16-D31 not present on AT91SAM9R64. 0 at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Pulled-up input at reset Static Memory Controller - SMC NCS0 - NCS5 NWR0 - NWR3 NRD NWE NBS0 - NBS3 Chip Select Lines Write Signal Read Signal Write Enable Byte Mask Signal Output Output Output Output Output Low Low Low Low Low NCS2, NCS5 not present on AT91SAM9R64. CompactFlash Support CFCE1 - CFCE2 CFOE CFWE CFIOR CFIOW CFRNW CFCS0 - CFCS1 CompactFlash Chip Enable CompactFlash Output Enable CompactFlash Write Enable CompactFlash IO Read CompactFlash IO Write CompactFlash Read Not Write CompactFlash Chip Select Lines Output Output Output Output Output Output Output Low CFCS1 not present on AT91SAM9R64. Low Low Low Low Low 8 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Comments NAND Flash Support NANDCS NANDOE NANDWE NAND Flash Chip Select NAND Flash Output Enable NAND Flash Write Enable Output Output Output SDRAM Controller SDCK SDCKE SDCS BA0 - BA1 SDWE RAS - CAS SDA10 SDRAM Clock SDRAM Clock Enable SDRAM Controller Chip Select Bank Select SDRAM Write Enable Row and Column Signal SDRAM Address 10 Line Output Output Output Output Output Output Output Multimedia Card Interface MCI CK CDA DA0 - DA3 Multimedia Card Clock Multimedia Card Slot A Command Multimedia Card Slot A Data I/O I/O I/O Low Low High Low Low Low Low Universal Synchronous Asynchronous Receiver Transmitter USARTx SCKx TXDx RXDx RTSx CTSx DTR0 DSR0 DCD0 RI0 USARTx Serial Clock USARTx Transmit Data USARTx Receive Data USARTx Request To Send USARTx Clear To Send USART0 Data Terminal Ready USART0 Data Set Ready USART0 Data Carrier Detect USART0 Ring Indicator I/O I/O Input Output Input I/O Input Output Input RTS0, RTS2, RTS3 not present on AT91SAM9R64. CTS0, CTS2, CTS3 not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. SCKx not present on AT91SAM9R64. Synchronous Serial Controller - SSCx TD0 - TD1 RD0 - RD1 TK0 - TK1 RK0 - RK1 TF0 - TF1 RF0 - RF1 SSC Transmit Data SSC Receive Data SSC Transmit Clock SSC Receive Clock SSC Transmit Frame Sync SSC Receive Frame Sync Output Input I/O I/O I/O I/O TD1 not present on AT91SAM9R64. RD1 not present on AT91SAM9R64. TK1 not present on AT91SAM9R64. RK1 not present on AT91SAM9R64. TF1 not present on AT91SAM9R64. RF1 not present on AT91SAM9R64. 9 6289C–ATARM–28-May-09 Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Comments AC97 Controller - AC97C AC97RX AC97TX AC97FS AC97CK AC97 Receive Signal AC97 Transmit Signal AC97 Frame Synchronization Signal AC97 Clock signal Input Output Output Input Timer/Counter - TC TCLKx TIOAx TIOBx TC Channel x External Clock Input TC Channel x I/O Line A TC Channel x I/O Line B Input I/O I/O TCLK1 not present on AT91SAM9R64. TIOA1, TIOA2 not present on AT91SAM9R64. TIOB1, TIOB2 not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Pulse Width Modulation Controller- PWMC PMWx Pulse Width Modulation Output Output PWM2 not present on AT91SAM9R64. Serial Peripheral Interface - SPI MISO MOSI SPCK NPCS0 NPCS1 - NPCS3 Master In Slave Out Master Out Slave In SPI Serial Clock SPI Peripheral Chip Select 0 SPI Peripheral Chip Select I/O I/O I/O I/O Output Low Low NPCS2, NPCS3 not present on AT91SAM9R64. Two-Wire Interface - TWIx TWDx TWCKx TWIx Two-wire Serial Data TWIx Two-wire Serial Clock I/O I/O TWD1 not present on AT91SAM9R64. TWCK1 not present on AT91SAM9R64. Touch Screen Analog-to-Digital Converter GPAD0-GPAD5 AD0XP AD1XM AD2YP AD3YM TSADTRG TSADVREF Analog Inputs Touch Panel Right side Touch Panel Left side Touch Panel Top side Touch Panel Bottom side ADC Trigger ADC Reference Analog Analog Analog Analog Analog Input Analog LCD Controller - LCDC LCDD0 - LCDD23 LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDCC LCDPWR LCDMOD LCD Data Bus LCD Vertical Synchronization LCD Horizontal Synchronization LCD Dot Clock LCD Data Enable LCD Contrast Control LCD panel Power enable control LCD Modulation signal Output Output Output Output Output Output Output Output Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. Not present on AT91SAM9R64. GPAD4, GPAD5 not present on AT91SAM9R64. Multiplexed with AD0 Multiplexed with AD1 Multiplexed with AD2 Multiplexed with AD3. Not present on AT91SAM9R64. 10 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 3-1. Signal Name Signal Description List (Continued) Function Type Active Level Comments USB High Speed Device DFSDM DFSDP DHSDM DHSDP USB Device Full Speed Data USB Device Full Speed Data + USB Device High Speed Data USB Device High Speed Data + Analog Analog Analog Analog 11 6289C–ATARM–28-May-09 4. Package and Pinout The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available in a 217-ball LFBGA package. 4.1 144-ball BGA Package Outline Figure 4-1 shows the orientation of the 144-ball BGA package. Figure 4-1. 144-ball BGA Pinout (Top View) 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEF GHJ BALL A1 KLM 12 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 4.2 Pinout AT91SAM9R64 Pinout for 144-ball BGA Package Pin D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 Signal Name PLLRCA VDDUTMII NWR3/NBS3/CFIOW NWR1/NBS1/CFIOR JTAGSEL GNDBU TCK PA[26] PA[24] PA[13] PA[6] PD[20] GNDPLLA NWR0/NWE/CFWE NRD/CFOE NCS0 NCS1/SDCS PB[2] NRST BMS PA[25] PA[15] PA[5] PA[4] PB[5] PB[6] PB[7] PB[8] PB[3] PB[4] TST VDDUTMIC PA[3] PA[2] PA[0] PA[1] Pin G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 Signal Name PB[10] PB[11] PB[12] PB[9] PB[13] GND GND GND GNDUTMI VDDCORE VDDIOP VDDIOP PB[14] PB[15] A[0] A[2] SDA10 D[1] GND GND VDDIOM SDCKE VDDCORE VDDIOP A[4] A[1] A[3] A[14] CAS D[2] D[5] D[12] D[14] VDDIOM D[10] D[9] Pin K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 Signal Name A[5] A[6] A[13] A[15] RAS D[3] D[6] D[13] VDDIOM VDDIOM D[11] PB[1] A[7] A[8] A[11] A[16] SDWE D[4] D[7] D[15] PC[1] PC[0] PB[0] GNDANA A[9] A[10] A[12] A[17] D[0] SDCK D[8] ADVREF VDDANA PA[17] PA[18] PA[19] Table 4-1. Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 DFSDM DHSDM XIN XOUT XIN32 Signal Name XOUT32 TDO PA[31] PA[22] PA[16] PA[14] PA[11] DFSDP DHSDP NC VDDPLLB GNDPLLB TMS RTCK PA[27] PA[21] PA[12] PD[21] PA[10] VDDPLLA VBG VDDBU SHDN WKUP NTRST TDI PA[28] PA[23] PA[7] PD[19] PD[18] 13 6289C–ATARM–28-May-09 4.3 217-ball LFBGA Package Outline Figure 4-2 shows the orientation of the 217-ball LFBGA package. Figure 4-2. 217-ball LFBGA Pinout (Top View) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 ABCDEF GHJ KL M NPRT U BALL A1 14 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 4.4 Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D4 Pinout AT91SAM9RL64 Pinout for 217-ball LFBGA Package (1) Signal Name DFSDM DHSDP VDDPLLB XIN XOUT GNDPLLB XOUT32 GND NRST RTCK PA[29] PA[26] PA[22] PA[14] PA[10] PD[20] PD[17] DFSDP DHSDM VBG NC NC XIN32 TST GND TMS VDDCORE PA[28] PA[25] PA[21] PA[13] PD[21] PD[19] PA[9] VDDPLLA VDDUTMII GND GNDUTMI VDDBU WKUP GNDBU TCK TDI PA[31] PA[27] PA[24] PA[16] PA[11] PD[18] PA[7] PA[6] PLLRCA NWR1/NBS1/CFIOR GND GND Pin D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 E1 E2 E3 E4 E14 E15 E16 E17 F1 F2 F3 F4 F14 F15 F16 F17 G1 G2 G3 G4 G14 G15 G16 G17 H1 H2 H3 H4 H8 H9 H10 H14 H15 H16 H17 J1 J2 J3 J4 J8 J9 J10 Signal Name SHDN JTAGSEL NTRST BMS TDO PA[30] GND PA[23] PA[15] PA[12] PA[8] PD[13] PD[16] GNDPLLA NCS1/SDCS NCS0 NWR3/NBS3/CFIOW PD[15] PD[14] PA[5] PA[4] NRD/CFOE PB[2] NWR0/NWE/CFWE PB[3] PA[1] PA[0] PA[2] PA[3] GND VDDIOM PB[5] PB[4] PD[12] PD[11] PD[10] PD[9] PB[8] PB[9] PB[7] PB[6] VDDCORE VDDIOP PD[4] PD[8] PD[5] PD[2] PD[3] PB[12] PB[13] PB[11] PB[10] VDDCORE VDDIOP PC[29] Pin J14 J15 J16 J17 K1 K2 K3 K4 K8 K9 K10 K14 K15 K16 K17 L1 L2 L3 L4 L14 L15 L16 L17 M1 M2 M3 M4 M14 M15 M16 M17 N1 N2 N3 N4 N14 N15 N16 N17 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 Signal Name PD[1] PD[0] PC[30] PC[31] PB[14] PB[15] PB[17] PB[16] VDDUTMIC VDDIOP PC[28] PC[25] PC[24] PC[26] PC[27] PB[18] PB[19] PB[21] PB[20] PC[21] PC[20] PC[22] PC[23] PB[22] PB[23] PB[25] PB[24] PC[17] PC[16] PC[18] PC[19] PB[26] PB[27] PB[29] PB[28] PC[13] PC[12] PC[14] PC[15] PB[30] PB[31] A[1] A[11] A[15] CAS D[1] SDCKE D[5] D[8] D[15] PC[0] PB[0] PC[8] PC[9] PC[10] Pin P17 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 Signal Name PC[11] A[0] A[2] A[7] A[10] A[14] SDA10 D[0] VDDIOM D[6] D[9] NC VDDIOM PC[1] PB[1] PC[5] PC[6] PC[7] A[3] A[5] A[8] A[12] A[16] RAS D[2] D[4] D[7] D[10] D[14] VDDANA PA[17] PA[19] PC[2] PC[3] PC[4] A[4] A[6] A[9] A[13] A[17] SDWE D[3] SDCK D[11] D[12] D[13] TSADVREF PA[18] PA[20] PD[6] PD[7] GNDANA Table 4-2. Note: 1. Shaded cells define the pins powered by VDDIOM. 15 6289C–ATARM–28-May-09 5. Power Considerations 5.1 Power Supplies The AT91SAM9R64/RL64 has several types of power supply pins: • VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V (1.8V nominal) or between 3.0V and 3.6V (3.3V nominal). • VDDIOP pins: Power the Peripherals I/O lines; voltage ranges from 3.0V and 3.6V, 3.3V nominal. • VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDPLLA pin: Powers the PLL cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal. • VDDPLLB pin: Powers the UTMI PLL (480MHz) and OSC 12M cells; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V and 3.6V, 3.3V nominal. • VDDUTMIC pin: Powers the UTMI+ core; voltage ranges from 1.08V and 1.32V, 1.2V nominal. • VDDANA pin: Powers the ADC cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal. The power supplies VDDIOM and VDDIOP are identified in the pinout table and the PIO multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies. Separated ground pins are provided for VDDBU, VDDPLLA, VDDPLLB and VDDANA. These ground pins are respectively GNDBU, GNDPLLA, GNDPLLB and GNDANA. A common ground pin is provided for VDDUTMII and VDDUTMIC. This ground pin is GNDUTMI. Caution: VDDCORE and VDDIO constraints at startup to be checked in the Core Power Supply POR Characteristics in the Electical Characteristics section of the datasheet. 5.1.1 USB Power Supply Considerations To achieve the best performances on the UDPHS, care must be taken in the power supplies choice and especially on VDDPLLB,VDDUTMIC and VDDUTMII. The USB High speed requires power supplies with a ripple voltage < 20 mV on VDDPLLB and VDDUTMIC. The VDDUTMII powering the UTMI transceiver must also be filtered. It is highly recommended to use an LDO linear regulator to generate the 1.2 volts for both VDDPLLB and VDDUTMIC. VDDUTMII can be connected on the 3.3 volts of the system via an LC filter. The figure below gives an example of VDDPLLB, VDDUTMIC and VDDUTMII. 16 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 5-1. Example of PLL and USB Power Supplies VIN VIN CE 10µF VSS VOUT 10µF 1K ADJ 100K MIC5235YM5 0.1µF 1V2_USB 2.2µH 1V2_USB 0.1µF VDDPLLB 2.2µH 1V2_USB 0.1µF VDDUTMIC 2.2µH 3V3 0.1µF VDDUTMII 5.2 Programmable I/O Lines Power Supplies The power supplies pins VDDIOM support two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The maximum speed is MCK on the pin SDCK (SDRAM Clock) loaded with 30pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The maximum speed on the other signals of the External Bus Interface (control, address and data signals) is 50 MHz. The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface. At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either 1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the device out of its Slow Clock Mode. The PIO lines are supplied through VDDIOP and the speed of the signal that can be driven on them can reach 50 MHz with 50 pF load. 17 6289C–ATARM–28-May-09 6. I/O Line Considerations 6.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO is an output, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. All the JTAG signals are supplied with VDDIOP except JTAGSEL supplied by VDDBU. 6.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU. 6.3 Reset Pins NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP. As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and NTRST pin can be left unconnected. The NRST and NTRST pins integrates a permanent pull-up resistor of 100 k Ω t ypical to VDDIOP. The NRST signal is inserted in the Boundary Scan. 6.4 PIO Controllers All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product datasheet for more details. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 6.5 Shutdown Logic Pins The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. 7. Processor and Architecture 7.1 ARM926EJ-S Processor • • RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration Two Instruction Sets 18 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – – • • ARM High-performance 32-bit Instruction Set Thumb High Code Density 16-bit Instruction Set DSP Instruction Extensions 5-Stage Pipeline Architecture: – – – – – Instruction Fetch (F) Instruction Decode (D) Execute (E) Data Memory (M) Register Write (W) Virtually-addressed 4-way Associative Cache Eight words per line Write-through and Write-back Operation Pseudo-random or Round-robin Replacement Main Write Buffer with 16-word Data Buffer and 4-address Buffer DCache Write-back Buffer with 8-word Entries and a Single Address Entry Software Control Drain Access Permission for Sections Access Permission for large pages and small pages can be specified separately for each quarter of the page 16 embedded domains Arbitrates and Schedules AHB Requests Separate Masters for both instruction and data access providing complete Matrix system flexibility Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) • 4-Kbyte Data Cache, 4-Kbyte Instruction Cache – – – – • Write Buffer – – – • Standard ARM v4 and v5 Memory Management Unit (MMU) – – – • Bus Interface Unit (BIU) – – – – 7.2 Matrix Masters The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 masters, which means that each master can perform an access concurrently with others, to an available slave. Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings. Table 7-1. Master 0 Master 1 Master 2 List of Bus Matrix Masters DMA Controller USB Device High Speed DMA LCD Controller DMA 19 6289C–ATARM–28-May-09 Table 7-1. Master 3 Master 4 Master 5 List of Bus Matrix Masters Peripheral DMA Controller ARM926™ Instruction ARM926 Data 7.3 Matrix Slaves The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. Table 7-2. Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5 List of Bus Matrix Slaves Internal ROM Internal SRAM LCD Controller User Interface UDP High Speed RAM External Bus Interface (EBI) Peripheral Bridge 7.4 Master to Slave Access All the Masters can normally access all the Slaves. However, some paths do not make sense, for example allowing access from the USB Device High speed DMA to the Internal Peripherals. Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table. Table 7-3. AT91SAM9R64/RL64 Master to Slave Access Masters Slaves 0 DMA Controller 1 USB HS Device DMA 2 LCD Controller DMA 3 Peripheral DMA 4 ARM926 Instruction 5 ARM926 Data 0 1 2 3 4 5 Internal ROM Internal SRAM LCD Controller User Interface UDP High Speed RAM External Bus Interface Peripheral Bridge X X X X X X X X X X X X X X - X X X X X - X X X X X - 7.5 Peripheral DMA Controller (PDC) • Acting as one AHB Bus Matrix Master • Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. • Next Pointer support, prevents strong real-time constraints on buffer management. The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities): 20 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary a. TWI0 Transmit Channel b. DBGU Transmit Channel c. USART3 Transmit Channel d. USART2 Transmit Channel e. USART1 Transmit Channel f. USART0 Transmit Channel g. AC97 Transmit Channel h. SPI Transmit Channel i. j. k. l. SSC1 Transmit Channel SSC0 Transmit Channel TWI0 Receive Channel DBGU Receive Channel m. ADC Receive Channel n. USART3 Receive Channel o. USART2 Receive Channel p. USART1 Receive Channel q. USART0 Receive Channel r. s. t. v. AC97 Receive Channel SPI Receive Channel SSC1 Receive Channel MCI Receive/Transmit Channel u. SSC0 Transmit Channel 7.6 DMA Controller • Acting as one Matrix Master • Embeds 2 channels • 16 bytes/FIFO for Channel Buffering • Linked List support with Status Write Back operation at End of Transfer • Word, Half-word, Byte transfer support 7.7 Debug and Test Features • ARM926 Real-time In-circuit Emulator – Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel • Debug Unit – Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register • IEEE1149.1 JTAG Boundary-scan on All Digital Pins 21 6289C–ATARM–28-May-09 8. Memories Figure 8-1. AT91SAM9R64/RL64 Memory Mapping Address Memory Space 0x0000 0000 Internal Memories 0x0FFF FFFF Internal Memory Mapping 0x0000 0000 Boot Memory (1) 1 MBytes 1 MBytes Notes : (1) Can be SRAM, ROM depending on BMS and the REMAP Command (2) Software programmable 256M Bytes 0x0010 0000 ITCM(2) 0x0020 0000 0x1000 0000 EBI Chip Select 0 0x1FFF FFFF DTCM(2) 1 MBytes 256M Bytes 0x0030 0000 SRAM(2) 1 MBytes 0x2000 0000 EBI Chip Select 1/ SDRAMC 0x0040 0000 256M Bytes 0x0050 0000 ROM LCD Controller User Interface 1 MBytes 0x2FFF FFFF 0x3000 0000 EBI Chip Select 2 0x3FFF FFFF 1 MBytes 256M Bytes 0x0060 0000 UDPHS RAM 0x0070 0000 1 MBytes 0x4000 0000 EBI Chip Select 3/ NANDFlash EBI Chip Select 4/ Compact Flash Slot 0 EBI Chip Select 5/ Compact Flash Slot 1 256M Bytes 0x0FFF FFFF Undefined (Abort) System Controller Mapping 0xFFFF C000 0x4FFF FFFF 0x5000 0000 256M Bytes Peripheral Mapping 0xF000 0000 0x5FFF FFFF 0x6000 0000 Reserved Reserved 0xFFFF E600 256M Bytes 0xFFFA 0000 0x6FFF FFFF 0x7000 0000 0xFFFA 4000 DMAC TCO, TC1, TC2 16K Bytes 0xFFFF E800 512 Bytes ECC MCI 16K Bytes 0xFFFF EA00 512 Bytes 0xFFFA 8000 TWI0 0xFFFA C000 TWI1 0xFFFB 0000 USART0 0xFFFB 4000 USART1 0xFFFB 8000 USART2 16K Bytes 0xFFFF F400 16K Bytes 0xFFFF F200 16K Bytes 16K Bytes 0xFFFF EE00 0xFFFF EF10 0xFFFF F000 16K Bytes 0xFFFF EC00 SDRAMC SMC MATRIX AIC DBGU PIOA UART3 16K Bytes 0xFFFF F600 512 Bytes 512 bytes 512 Bytes 512 Bytes 512 Bytes Undefined (Abort) 0xFFFB C000 512 Bytes 0xFFFC 0000 SSC0 0xFFFC 4000 16K Bytes 0xFFFF F800 PIOB PIOC SSC1 16K Bytes 0xFFFF FA00 512 Bytes 512 bytes 2,048M Bytes 0xFFFC 8000 PIOD PWMC 16K Bytes 0xFFFF FC00 512 bytes 0xFFFC C000 SPI 0xFFFD 0000 ADC TouchScreen 0xFFFD 4000 UDPHS 0xFFFD 8000 AC97 0xFFFD C000 0xEFFF FFFF 16K Bytes 16K Bytes 16K Bytes 16K Bytes 0xFFFF FD00 PMC RSTC 0xFFFF FD10 256 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes 16 Bytes SHDC 0xFFFF FD20 RTTC 0xFFFF FD30 PITC 0xFFFF FD40 WDTC 0xFFFF FD50 0xFFFF FD60 SCKCR GPBR Reserved RTCC 0xF000 0000 0xFFFF C000 Reserved Internal Peripherals 256M Bytes 0xFFFF FFFF SYSC 16K Bytes 0xFFFF FD70 0xFFFF FE00 128 Bytes 0xFFFF FFFF 0xFFFF FFFF Reserved 22 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to 8 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS5. The bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M byte of internal memory area. The bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. 8.1 Embedded Memories • 32 KB ROM – Single Cycle Access at full bus speed • 64 KB Fast SRAM – Single Cycle Access at full bus speed – Supports ARM926EJ-S TCM interface at full processor speed 8.1.1 Internal Memory Mapping Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap status (RCBx bit) and the BMS state at reset. Table 8-1. Address BMS = 1 0x0000 0000 Notes: ROM BMS =0 EBI_NCS0(2) SRAM Internal Memory Mapping RCBx(1) = 0 RCBx(1) = 1 1. x = 0 to maximum Master number. 2. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers. 8.1.1.1 Internal SRAM The AT91SAM9R64/RL64 product embeds a total of 64Kbyte high-speed SRAM split in 4 blocks of 16KBytes. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. After Remap, the SRAM also becomes available at address 0x0. This Internal SRAM can be allocated to threes areas. Its Memory Mapping is detailed in Table 82. • Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR configuration register located in the Chip Configuration User Interface. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0010 0000. 23 6289C–ATARM–28-May-09 • Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus at address 0x0020 0000. • Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap Command is performed, this SRAM block is accessible through the AHB bus at address 0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926 Data Masters. Within the 64Kbyte SRAM size available, the amount of memory assigned to each block is software programmable as a multiple of 16K Bytes according to Table 8-2. This Table provides the size of the Internal SRAM C according to the size of the Internal SRAM A and the Internal SRAM B. Table 8-2. Internal SRAM Block Size Internal SRAM A (ITCM) Size Remaining Internal SRAM C 0 0 Internal SRAM B (DTCM) size 16K Bytes 32K Bytes 64K Bytes 48K Bytes 32K Bytes 16K Bytes 48K Bytes 32K Bytes 16K Bytes 32K Bytes 32K Bytes 16K Bytes 0K Bytes At reset, the whole memory is assigned to Internal SRAM C. The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and when the user dynamically changes the Internal SRAM configuration, the new 16-Kbyte block organization may affect the previous configuration from a software point of view. Table 8-3 illustrates different configurations and the related 16-Kbyte blocks (RB0 to RB3) assignments. Table 8-3. Decoded Area 16-Kbyte Block Allocation example Configuration examples and related 16-Kbyte block assignments Address I = 0K D = 0K A = 64K(1) I = 16K D = 0K A = 48K RB1 I =32K D = 0K A = 32K RB1 RB0 RB3 RB3 I = 0K D = 16K A = 48K I = 16K D = 16K A = 32K RB1 I = 32K D = 16K A = 16K RB1 RB0 RB3 RB3 RB2 RB3 RB2 RB1 RB0 RB3 RB2 RB0 RB3 RB2 RB2 RB1 RB0 RB2 RB0 RB2 RB1 RB0 RB3 RB2 RB0 I = 0K D = 32K A = 32K I = 16K D = 32K A = 16K RB1 I = 32K D = 32K A = 0K RB1 RB0 RB3 RB2 Internal SRAM A (ITCM) Internal SRAM B (DTCM) 0x0010 0000 0x0010 4000 0x0020 0000 0x0020 4000 0x0030 0000 Internal SRAM C (AHB) Note: 0x0030 4000 0x0030 8000 0x0030 C000 1. Configuration after reset. 24 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary When accessed from the AHB, the internal Fast SRAM is single cycle accessible at full matrix speed (MCK). When accessed from the processor’s TCM Interface, they are also single cycle accessible at full processor speed. 8.1.1.2 Internal ROM The AT91SAM9R64/RL64 embeds an Internal ROM, which contains the SAM-BA program. At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0 (BMS =1) after the reset and before the Remap Command. 8.1.2 Boot Strategies The system always boots at address 0x0. To ensure maximum boot possibilities, the memory layout can be changed with two parameters. REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This is done by software once the system has boot. Refer to the Bus Matrix Section for more details. When REMAP = 0 BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done by a hardware way at reset. Note: All the memory blocks can always be seen at their specified base addresses that are not concerned by these parameters. The AT91SAM9R64/RL64 Bus Matrix manages a boot memory that depends on the level on the pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved to this effect. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 8.1.2.1 BMS = 1, boot on embedded ROM The system boots on Boot Program. • Boot on on-chip RC • Enable the 32768 Hz oscillator • Auto baudrate detection • Downloads and runs an application from external storage media into internal SRAM • Downloaded code size depends on embedded SRAM size • Automatic detection of valid application • Bootloader on a non-volatile memory – SDCard (boot ROM does not support high-capacity SDCards) – NAND Flash – SPI DataFlash® connected on NPCS0 of the SPI0 • SAM-BA Boot in case no valid program is detected in external NVM, supporting – Serial communication on a DBGU – USB Device HS Port 8.1.2.2 BMS = 0, boot on external memory • Boot on on-chip RC 25 6289C–ATARM–28-May-09 • Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. For optimization purposes, nothing else is done. To speed up the boot sequence user programmed software should perform a complete configuration: • Enable the 32768 Hz oscillator if best accuracy needed • Program the PMC (main oscillator enable or bypass mode) • Program and Start the PLL • Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock • Switch the main clock to the new value 8.2 External Memories The AT91SAM9R64/RL64 features one External Bus Interface to offer interface to a wide range of external memories and to any parallel peripheral. 8.2.1 External Bus Interface • Integrates three External Memory Controllers: – Static Memory Controller – SDRAM Controller – SLC Nand Flash ECC Controller • Additional logic for NAND Flash and CompactFlashTM • Optional Full 32-bit External Data Bus • Up to 26-bit Address Bus (up to 64MBytes linear per chip select) • Up to 6 chips selects, Configurable Assignment: – Static Memory Controller on NCS0 – SDRAM Controller (SDCS) or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3, Optional NAND Flash support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlashM support 8.2.2 Static Memory Controller • 8-, 16- or 32-bit Data Bus • Multiple Access Modes supported – Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size) • Multiple device adaptability – Control signals programmable setup, pulse and hold time for each Memory Bank • Multiple Wait State Management – Programmable Wait State Generation – External Wait Request – Programmable Data Float Time • Slow Clock mode supported 26 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 8.2.3 SDRAM Controller • Supported devices: – Standard and Low Power SDRAM (Mobile SDRAM) – 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path • Programming facilities – Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable • Energy-saving capabilities – Self-refresh, power down and deep power down modes supported • Error detection – Refresh Error Interrupt • SDRAM Power-up Initialization by software • SDRAM CAS Latency of 1, 2 and 3 supported • Auto Precharge Command not used 8.2.4 NAND Flash Error Corrected Code Controller • Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select • Single bit error correction and 2-bit Random detection. • Automatic Hamming Code Calculation while writing – ECC value available in a register • Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being detected erroneous – Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages 27 6289C–ATARM–28-May-09 9. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface embeds also the registers allowing to configure the Matrix and a set of registers configuring the EBI chip select assignment and the voltage range for external memories. 9.1 System Controller Mapping As shown in Figure 8-1, the System Controller’s peripherals are all mapped within the highest 16K bytes of the 4 Gbyte address space, between addresses 0xFFFF C000 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. This allows addressing all the registers of the System Controller from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of +/4kbytes. 28 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 9.2 Block Diagram System Controller Block Diagram System Controller VDDCORE Powered irq0-irq2 fiq periph_irq[2..24] pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq MCK periph_nreset dbgu_rxd MCK debug periph_nreset SLCK debug idle proc_nreset Periodic Interval Timer Watchdog Timer wdt_fault WDRPROC rtt_alarm VDDCORE POR por_ntrst jtag_nreset Debug Unit Advanced Interrupt Controller int por_ntrst ntrst ARM926EJ-S nirq nfiq Figure 9-1. dbgu_irq dbgu_txd pit_irq proc_nreset PCK debug jtag_nreset wdt_irq MCK periph_nreset rstc_irq periph_nreset proc_nreset backup_nreset VDDBU Powered Boundary Scan TAP Controller Bus Matrix NRST Reset Controller VDDBU VDDBU POR SLCK Real-Time Clock Real-Time Timer rtc_irq rtc_alarm rtt_irq rtt_alarm HSCK periph_clk[22] Shutdown Controller 4 General-purpose Backup Registers SCKCR SLCK XIN XOUT int 12MHz MAIN OSC UPLL HSCK PLLRCA PLLA periph_nreset periph_nreset periph_nreset periph_clk[2..4] dbgu_rxd PA0-PA31 PB0-PB31 PC0-PC31 PD0-PD21 periph_irq[2..4] irq fiq dbgu_txd Embedded Peripherals periph_irq[6..24] in out enable PLLACK MAINCK PCK Power Management Controller MCK pmc_irq idle periph_clk[6..24] periph_nreset periph_irq[22] USB High Speed Device Port SLCK backup_nreset SLCK backup_nreset SLCK SHDN WKUP backup_nreset rtc_alarm rtt_alarm RC OSC XIN32 XOUT32 SLOW CLOCK OSC periph_clk[2..24] pck[0-1] PIO Controllers 29 6289C–ATARM–28-May-09 9.3 Reset Controller The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on VDDCORE. The Reset Controller is capable to return to the software the source of the last reset, either a general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user reset or a watchdog reset. The Reset Controller controls the internal resets of the system and the NRST pin output. It is capable to shape a reset signal for the external devices, simplifying to a minimum connection of a push-button on the NRST pin to implement a manual reset. The configuration of the Reset Controller is saved as supplied on VDDBU. 9.4 Shutdown Controller The Shutdown Controller is supplied on VDDBU and allows a software-controllable shut down of the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the SHDN pin, and thus wakes up the system power supply. 9.5 Clock Generator The Clock Generator is made up of: • One low-power 32768 Hz Slow Clock Oscillator with bypass mode • One low-power RC oscillator • One 12 MHz Main Oscillator, which can be bypassed • One 480 MHz PLL (UPLL or PLLB) providing a clock for the USB High Speed Device Controller • One 80 to 240 MHz programmable PLL, providing the PLL Clock (PLLCK). This PLL has an input divider to offer a wider range of output frequencies from the 12 MHz input, the only limitation being the lowest input frequency shall be higher or equal to 1 MHz. 30 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 9-2. Clock Generator Block Diagram Clock Generator RCEN On Chip RC OSC XIN32 XOUT32 Slow Clock Oscillator Slow Clock SLCK OSCSEL OSC32EN OSC32BYP XIN XOUT 12M Main Oscillator Main Clock MAINCK UPLL (PLLB) PLL and Divider HSCK PLLRCA PLL Clock PLLCK Status Control Power Management Controller 9.6 9.6.1 Slow Clock Selection Description The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external slow clock on XIN32. Configuration is located in the slow clock control register (SCKCR) located at address 0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is present. Refer to the “Clock Generator” section for more details. 9.7 Power Management Controller The Power Management Controller provides all the clock signals to the system. It provides: • the Processor Clock PCK • the Master Clock MCK, in particular to the Matrix and the memory interfaces • the USB Device HS Clock HSCK • independent peripheral clocks, typically at the frequency of MCK • two programmable clock outputs: PCK0 and PCK1 This allows the software control of five flexible operating modes: • Normal Mode, processor and peripherals running at a programmable frequency • Idle Mode, processor stopped waiting for an interrupt • Slow Clock Mode, processor and peripherals running at low frequency 31 6289C–ATARM–28-May-09 • Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt • Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 9-3. AT91SAM9R64/RL64 Power Management Controller Block Diagram Processor Clock Controller Master Clock Controller SLCK MAINCK PLLCK PCK int Idle Mode MCK Prescaler /1,/2,/4,...,/64 Peripherals Clock Controller ON/OFF periph_clk[..] Programmable Clock Controller ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] SLCK MAINCK PLLCK 9.8 Periodic Interval Timer • Includes a 20-bit Periodic Counter, with less than 1 µs accuracy • Includes a 12-bit Interval Overlay Counter • Real Time OS or Linux®/WindowsCE® compliant tick generator 9.9 Watchdog Timer • 16-bit key-protected only-once-Programmable Counter • Windowed, prevents the processor to be in a dead-lock on the watchdog access 9.10 Real-Time Timer • Real-Time Timer, allowing backup of time with different accuracies – 32-bit Free-running back-up Counter – Integrates a 16-bit programmable prescaler running on slow clock – Alarm Register capable to generate a wake-up of the system through the Shut Down Controller 9.11 Real-Time Clock • Low power consumption • Full asynchronous design 32 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • Two hundred year calendar • Programmable Periodic Interrupt • Alarm and update parallel load • Control of alarm and update Time/Calendar Data In 9.12 General-Purpose Backed-up Registers • Four 32-bit backup general-purpose registers 9.13 Advanced Interrupt Controller • Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor • Thirty-two individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.) – Programmable Edge-triggered or Level-sensitive Internal Sources – Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive • One External Sources plus the Fast Interrupt signal • 8-level Priority Controller – Drives the Normal Interrupt of the processor – Handles priority of the interrupt sources 1 to 31 – Higher priority interrupts can be served during service of lower priority interrupt • Vectoring – Optimizes Interrupt Service Routine Branch and Execution – One 32-bit Vector Register per interrupt source – Interrupt Vector Register reads the corresponding current Interrupt Vector • Protect Mode – Easy debugging by preventing automatic operations when protect modeIs are enabled • Fast Forcing – Permits redirecting any normal interrupt source on the Fast Interrupt of the processor 9.14 Debug Unit • Composed of two functions – Two-pin UART – Debug Communication Channel (DCC) support • Two-pin UART – Implemented features are 100% compatible with the standard Atmel USART – Independent receiver and transmitter with a common programmable Baud Rate Generator – Even, Odd, Mark or Space Parity Generation – Parity, Framing and Overrun Error Detection – Automatic Echo, Local Loopback and Remote Loopback Channel Modes 33 6289C–ATARM–28-May-09 – Support for two PDC channels with connection to receiver and transmitter • Debug Communication Channel Support – Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from the ARM Processor’s ICE Interface 9.15 Chip Identification • Chip ID: 0x019B03A0 • JTAG ID: 0x05B2003F • ARM926 TAP ID: 0x0792603F 9.16 PIO Controllers • 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, controlling a maximum of 118 I/O Lines • Each PIO Controller controls up to 32 programmable I/O Lines – PIOA has 32 I/O Lines – PIOB has 32 I/O Lines – PIOC has 32 I/O Lines – PIOD has 22 I/O Lines • Fully programmable through Set/Clear Registers • Multiplexing of two peripheral functions per I/O Line • For each I/O Line (whether assigned to a peripheral or used as general purpose I/O) – Input change interrupt – Glitch filter – Multi-drive option enables driving in open drain – Programmable pull up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time • Synchronous output, provides Set and Clear of several I/O lines in a single write 10. Peripherals 10.1 Peripheral Mapping As shown in Figure 8-1, the Peripherals are mapped in the upper 256M bytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16K bytes of address space. 34 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.2 Peripheral Identifiers The Table 10-1 defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 10-1. AT91SAM9R64/RL64 Peripheral Identifiers Peripheral Mnemonic AIC SYSC PIOA PIOB PIOC PIOD US0 US1 US2 US3 MCI TWI0 TWI1 SPI SSC0 SSC1 TC0 TC1 TC2 PWMC TSADCC DMAC UDPHS LCDC AC97 AIC Note: Peripheral Name Advanced Interrupt Controller System Controller Interrupt Parallel I/O Controller A, Parallel I/O Controller B Parallel I/O Controller C Parallel I/O Controller D USART 0 USART 1 USART 2 USART 3 Multimedia Card Interface Two-Wire Interface 0 Two-Wire Interface 1 Serial Peripheral Interface Synchronous Serial Controller 0 Synchronous Serial Controller 1 Timer Counter 0 Timer Counter 1 Timer Counter 2 Pulse Width Modulation Controller Touch Screen ADC Controller DMA Controller USB Device High Speed LCD Controller (AT91SAM9RL64 only) AC97 Controller Reserved Advanced Interrupt Controller IRQ External Interrupt FIQ Peripheral ID 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25-30 31 Setting AIC, SYSIRQ, LCDC and IRQ bits in the clock set/clear registers of the PMC has no effect. 35 6289C–ATARM–28-May-09 10.3 10.3.1 Peripheral Interrupts and Clock Control System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from: • the SDRAM Controller • the Debug Unit • the Periodic Interval Timer • the Real-time Timer • the Real-time Clock • the Watchdog Timer • the Reset Controller • the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 10.3.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 10.4 Peripherals Signals Multiplexing on I/O Lines The AT91SAM9R64/RL64 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplexes the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only, might be duplicated within the both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case for pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. The AT91SAM9RL64 and AT91SAM9R64 do not have the same peripheral signal multiplexing, each one follows. 36 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.4.1 10.4.1.1 Table 10-2. AT91SAM9RL64 PIO Multiplexing AT91SAM9RL64 PIO Controller A Multiplexing AT91SAM9RL64 Multiplexing on PIO Controller A PIO Controller A I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A MC_DA0 MC_CDA MC_CK MC_DA1 MC_DA2 MC_DA3 TXD0 RXD0 SCK0 RTS0 CTS0 TXD1 RXD1 TXD2 RXD2 TD0 RD0 AD0 AD1 AD2 AD3 DRXD DTXD TWD0 TWCK0 MISO MOSI SPCK NPCS0 RTS2 CTS2 NWAIT TF1 TK1 IRQ RF0 RTS1 CTS1 SCK3 TD1 RD1 RF1 RK1 RK0 TCLK0 TIOA0 TIOB0 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDANA VDDANA VDDANA VDDANA VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Application Usage Function Comments 37 6289C–ATARM–28-May-09 10.4.1.2 Table 10-3. AT91SAM9RL64 PIO Controller B Multiplexing AT91SAM9RL64 Multiplexing on PIO Controller B PIO Controller B Application Usage Reset State I/O I/O A21 A22 I/O I/O I/O NPCS1 PWM0 PWM1 FIQ I/O I/O I/O A25 A18 A19 A20 PCK0 ADTRG A23 A24 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Function Comments I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 Peripheral A TXD3 RXD3 A21/NANDALE A22/NANDCLE NANDOE NANDWE NCS3/NANDCS NCS4/CFCS0 CFCE1 CFCE2 A25/CFRNW A18 A19 A20 A23 A24 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 Peripheral B 38 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.4.1.3 Table 10-4. AT91SAM9RL64 PIO Controller C Multiplexing AT91SAM9RL64 Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PC9 PC10 PC11 PC12 PC13 PC14 PC15 PC16 PC17 PC18 PC19 PC20 PC21 PC22 PC23 PC24 PC25 PC26 PC27 PC28 PC29 PC30 PC31 Peripheral A TF0 TK0 LCDMOD LCDCC LCDVSYNC LCDHSYNC LCDDOTCK LCDDEN LCDD0 LCDD1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD8 LCDD9 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD16 LCDD17 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 TIOA1 TIOB1 TCLK1 LCDD2 LCDD3 LCDD4 LCDD5 LCDD6 LCDD7 LCDD10 LCDD11 LCDD12 LCDD13 LCDD14 LCDD15 LCDD18 LCDD19 LCDD20 LCDD21 LCDD22 LCDD23 LCDPWR PWM0 PWM1 Peripheral B Reset State I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Application Usage Function Comments 39 6289C–ATARM–28-May-09 10.4.1.4 Table 10-5. AT91SAM9RL64 PIO Controller D Multiplexing AT91SAM9RL64 Multiplexing on PIO Controller D PIO Controller D Application Usage Reset State I/O I/O SCK1 CTS3 RTS3 PWM2 I/O I/O I/O I/O I/O I/O PWM3 NPCS3 TIOA2 TIOB2 PCK1 NPCS3 PWM0 PWM1 PWM2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDANA VDDANA VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Function Comments I/O Line PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 PD9 PD10 PD11 PD12 PD13 PD14 PD15 PD16 PD17 PD18 PD19 PD20 PD21 Peripheral A NCS2 AC97_FS AC97_CK AC97_TX AC97_RX DTXD AD4 AD5 NPCS2 SCK2 TWD1 TWCK1 PWM2 NCS5/CFCS1 DSR0 DTR0 DCD0 RI0 PWM3 PCK0 PCK1 TCLK2 Peripheral B Comments 40 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.4.2 Note: AT91SAM9R64 PIO Multiplexing In Table 10-6, Table 10-7, Table 10-8 and Table 10-9, shaded cells indicate I/O lines that are NOT available on the AT91SAM9R64. 10.4.2.1 Table 10-6. AT91SAM9R64 PIO Controller A Multiplexing AT91SAM9R64 Multiplexing on PIO Controller A PIO Controller A Application Usage Reset State I/O I/O I/O TCLK0 TIOA0 TIOB0 I/O I/O I/O I/O I/O NA NA RK0 I/O I/O I/O I/O I/O I/O I/O I/O RTS1 CTS1 NA I/O RF0 I/O I/O I/O I/O I/O I/O I/O NA NA IRQ I/O VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Reserved Reserved I/O I/O VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Reserved Power Supply VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP VDDIOP Reserved Reserved Function Comments I/O Line PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31 Peripheral A MC_DA0 MC_CDA MC_CK MC_DA1 MC_DA2 MC_DA3 TXD0 RXD0 NA NA CTS0 TXD1 RXD1 TXD2 RXD2 TD0 RD0 AD0 AD1 AD2 NA DRXD DTXD TWD0 TWCK0 MISO MOSI SPCK NPCS0 NA NA NWAIT Peripheral B 41 6289C–ATARM–28-May-09 10.4.2.2 Table 10-7. AT91SAM9R64 PIO Controller B Multiplexing AT91SAM9R64 Multiplexing on PIO Controller B PIO Controller B Application Usage Reset State I/O I/O A21 A22 I/O I/O I/O NPCS1 PWM0 PWM1 FIQ I/O I/O I/O A25 A18 A19 A20 PCK0 ADTRG NA A23 A24 Power Supply VDDIOP VDDIOP VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM VDDIOM Reserved Function Comments I/O Line PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16PB31 Peripheral A TXD3 RXD3 A21/NANDALE A22/NANDCLE NANDOE NANDWE NCS3/NANDCS NCS4/CFCS0 CFCE1 CFCE2 A25/CFRNW A18 A19 A20 A23 A24 NA Peripheral B 42 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 10.4.2.3 Table 10-8. AT91SAM9R64 PIO Controller C Multiplexing AT91SAM9R64 Multiplexing on PIO Controller C PIO Controller C I/O Line PC0 PC1 PC2PC31 Peripheral A TF0 TK0 NA NA Peripheral B Reset State I/O I/O Power Supply VDDIOP VDDIOP Reserved Application Usage Function Comments 10.4.2.4 Table 10-9. AT91SAM9R64 PIO Controller D Multiplexing AT91SAM9R64 Multiplexing on PIO Controller D PIO Controller D Application Usage Comments Reset State Power Supply Function Comments Reserved I/O I/O I/O I/O VDDIOP VDDIOP VDDIOP VDDIOP I/O Line PD0PD17 PD18 PD19 PD20 PD21 Peripheral A NA PWM3 PCK0 PCK1 TCLK2 Peripheral B NA 43 6289C–ATARM–28-May-09 11. Embedded Peripherals Overview 11.1 Serial Peripheral Interface (SPI) • Supports communication with serial external devices – Four chip selects with external decoder support allow communication with up to 15 peripherals – Serial memories, such as DataFlash and 3-wire EEPROMs – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors – External co-processors • Master or slave serial peripheral bus interface – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays between consecutive transfers and between clock and data per chip select – Programmable delay between consecutive transfers – Selectable mode fault detection • Very fast transfers supported – Transfers with baud rates up to MCK – The chip select line may be left active to speed up transfers on the same device 11.2 Two-wire Interface (TWI) • Compatibility with standard two-wire serial memory • One, two or three bytes for slave address • Sequential read/write operations • Supports either master or slave modes • Compatible with Standard Two-wire Serial Memories • Master, Multi-master and Slave Mode Operation • Bit Rate: Up to 400 Kbits • General Call Supported in Slave mode • Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only – One Channel for the Receiver, One Channel for the Transmitter – Next Buffer Support 11.3 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB- or LSB-first 44 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – Optional break generation and detection – By 8 or by-16 over-sampling receiver frequency – Hardware handshaking RTS-CTS – Receiver time-out and transmitter timeguard – Optional Multi-drop Mode with address generation and detection – Optional Manchester Encoding • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • IrDA modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 11.4 Serial Synchronous Controller (SSC) • Provides serial synchronous communication links used in audio and telecom applications (with CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.) • Contains an independent receiver and transmitter and a common clock divider • Offers a configurable frame sync and data length • Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal • Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal 11.5 AC97 Controller • Compatible with AC97 Component Specification V2.2 • Capable to Interface with a Single Analog Front end • Three independent RX Channels and three independent TX Channels – One RX and one TX channel dedicated to the AC97 Analog Front end control – One RX and one TX channel for data transfers, associated with a PDC – One RX and one TX channel for data transfers with no PDC • Time Slot Assigner allowing to assign up to 12 time slots to a channel • Channels support mono or stereo up to 20 bit sample length – Variable sampling rate AC97 Codec Interface (48KHz and below) 11.6 Timer Counter (TC) • Three 16-bit Timer Counter Channels • Wide range of functions including: – Frequency Measurement – Event Counting – Interval Measurement – Pulse Generation 45 6289C–ATARM–28-May-09 – Delay Timing – Pulse Width Modulation – Up/down Capabilities • Each channel is user-configurable and contains: – Three external clock inputs – Five internal clock inputs – Two multi-purpose input/output signals • Two global registers that act on all three TC Channels 11.7 Pulse Width Modulation Controller (PWM) • 4 channels, one 16-bit counter per channel • Common clock generator, providing Thirteen Different Clocks – A Modulo n counter providing eleven clocks – Two independent Linear Dividers working on modulo n counter outputs • Independent channel programming – Independent Enable Disable Commands – Independent Clock Selection – Independent Period and Duty Cycle, with Double Bufferization – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform 11.8 Multimedia Card Interface (MCI) • Compatibility with MultiMedia Card Specification Version 3.31 • Compatibility with SD Memory Card Specification Version 1.0 • Compatibility with SDIO Specification Version V1.1 • Cards clock rate up to Master Clock divided by 2 • Embedded power management to slow down clock rate when not used • MCI has one slot supporting – One MultiMediaCard bus (up to 30 cards) or – One SD Memory Card – One SDIO Card • Support for stream, block and multi-block data read and write 11.9 USB High Speed Device Port (UDPHS) • USB V2.0 high-speed compliant, 480 MBits per second • Embedded USB V2.0 UTMI+ high-speed transceiver • Embedded 4K-byte dual-port RAM for endpoints • Embedded 6 channels DMA controller • Suspend/Resume logic • Up to 3 banks for isochronous and bulk endpoints • Seven endpoints: 46 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – Endpoint 0: 64 bytes, 1 bank mode – Endpoint 1 & 2: 1024 bytes, 2 banks mode, HS isochronous capable, DMA – Endpoint 3 & 4: 1024bytes, 3 banks mode, DMA – Endpoint 5 & 6: 1024 bytes, 3 banks mode, HS isochronous capable, DMA 11.10 LCD Controller (LCDC) • Single and Dual scan color and monochrome passive STN LCD panels supported • Single scan active TFT LCD panels supported. • 4-bit single scan, 8-bit single or dual scan, 16-bit dual scan STN interfaces supported • Up to 24-bit single scan TFT interfaces supported • Up to 16 gray levels for mono STN and up to 4096 colors for color STN displays • 1, 2 bits per pixel (palletized), 4 bits per pixel (non-palletized) for mono STN • 1, 2, 4, 8 bits per pixel (palletized), 16 bits per pixel (non-palletized) for color STN • 1, 2, 4, 8 bits per pixel (palletized), 16, 24 bits per pixel (non-palletized) for TFT • Single clock domain architecture • Resolution supported up to 2048x2048 11.11 Touch Screen Analog-to-digital Converter (TSADCC) • 6-channel ADC • Support 4-wire resistive Touch Screen • 10-bit 384 Ksamples/sec. Successive Approximation Register ADC • -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity • Integrated 6-to-1 multiplexer, offering eight independent 3.3V analog inputs • External voltage reference for better accuracy on low voltage inputs • Individual enable and disable of each channel • Multiple trigger sources – Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger • Sleep Mode and conversion sequencer – Automatic wakeup on trigger and back to sleep mode after conversions of all enabled channels 47 6289C–ATARM–28-May-09 48 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 12. ARM926EJ-S Processor Overview 12.1 Overview The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multitasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Javapowered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including: • an ARM9EJ-S™ integer core • a Memory Management Unit (MMU) • separate instruction and data AMBA® AHB bus interfaces • separate instruction and data TCM interfaces 49 6289C–ATARM–28-May-09 12.2 Block Diagram Figure 12-1. ARM926EJ-S Internal Functional Block Diagram ARM926EJ-S TCM Interface Coprocessor Interface ETM Interface DEXT Droute Data AHB Interface AHB DCACHE Bus Interface Unit WDATA RDATA ARM9EJ-S DA MMU EmbeddedICE -RT Processor IA Instruction AHB Interface AHB INSTR ICE Interface ICACHE Iroute IEXT 12.3 12.3.1 ARM9EJ-S Processor ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set: • ARM state: 32-bit, word-aligned ARM instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 12.3.2 Switching State The operating state of the ARM9EJ-S core can be switched between: • ARM state and THUMB state using the BX and BLX instructions, and loads to the PC 50 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 12.3.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 12.3.4 Memory Access The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data. 12.3.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode will appear as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. 12.3.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes: • User mode is the usual ARM program execution state. It is used for executing most application programs • Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process • Interrupt (IRQ) mode is used for general-purpose interrupt handling 51 6289C–ATARM–28-May-09 • Supervisor mode is a protected mode for the operating system • Abort mode is entered after a data or instruction prefetch abort • System mode is a privileged user mode for the operating system • Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 12.3.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers: • 31 general-purpose 32-bit registers • 6 32-bit status registers Table 12-1 shows all the registers in all modes. Table 12-1. User and System Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 PC ARM9TDMI™ Modes and Registers Layout Supervisor Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_SVC R14_SVC PC Abort Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_ABORT R14_ABORT PC Undefined Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_UNDEF R14_UNDEF PC Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13_IRQ R14_IRQ PC Fast Interrupt Mode R0 R1 R2 R3 R4 R5 R6 R7 R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ PC CPSR CPSR SPSR_SVC CPSR SPSR_ABORT CPSR SPSR_UNDEF CPSR SPSR_IRQ CPSR SPSR_FIQ Mode-specific banked registers The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose 52 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines: • constraints on the use of registers • stack conventions • argument passing and result return The Thumb state register set is a subset of the ARM state set. The programmer has direct access to: • Eight general-purpose registers r0-r7 • Stack pointer, SP • Link register, LR (ARM r14) • PC • CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12). 12.3.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers: • hold information about the most recently performed ALU operation • control the enabling and disabling of interrupts • set the processor operation mode 53 6289C–ATARM–28-May-09 Figure 12-2. Status Register Format 31 30 29 28 27 24 765 0 NZCVQ J Reserved I FT Mode Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than Mode bits Thumb state bit FIQ disable IRQ disable Figure 12-2 shows the status register format, where: • N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags • The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag. • The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where: – J = 0: The processor is in ARM or Thumb state, depending on the T bit – J = 1: The processor is in Jazelle state. • Mode: five bits to encode the current processor mode 12.3.7.2 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privi- leged mode. The types of exceptions are: • Fast interrupt (FIQ) • Normal interrupt (IRQ) • Data and Prefetched aborts (Abort) • Undefined instruction (Undefined) • Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order: • Reset (highest priority) • Data Abort • FIQ • IRQ • Prefetch Abort • BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) 54 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: – ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). – THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 12.3.8 ARM Instruction Set Overview The ARM instruction set is divided into: • Branch instructions 55 6289C–ATARM–28-May-09 • Data processing instructions • Status register transfer instructions • Load and Store instructions • Coprocessor instructions • Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 12-2 gives the ARM instruction mnemonic list. Table 12-2. Mnemonic MOV ADD SUB RSB CMP TST AND EOR MUL SMULL SMLAL MSR B BX LDR LDRSH LDRSB LDRH LDRB LDRBT LDRT LDM SWP MCR LDC CDP ARM Instruction Mnemonic List Operation Move Add Subtract Reverse Subtract Compare Test Logical AND Logical Exclusive OR Multiply Sign Long Multiply Signed Long Multiply Accumulate Move to Status Register Branch Branch and Exchange Load Word Load Signed Halfword Load Signed Byte Load Half Word Load Byte Load Register Byte with Translation Load Register with Translation Load Multiple Swap Word Move To Coprocessor Load To Coprocessor Coprocessor Data Processing STRH STRB STRBT STRT STM SWPB MRC STC Store Half Word Store Byte Store Register Byte with Translation Store Register with Translation Store Multiple Swap Byte Move From Coprocessor Store From Coprocessor Mnemonic MVN ADC SBC RSC CMN TEQ BIC ORR MLA UMULL UMLAL MRS BL SWI STR Operation Move Not Add with Carry Subtract with Carry Reverse Subtract with Carry Compare Negated Test Equivalence Bit Clear Logical (inclusive) OR Multiply Accumulate Unsigned Long Multiply Unsigned Long Multiply Accumulate Move From Status Register Branch and Link Software Interrupt Store Word 56 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 12.3.9 New ARM Instruction Set . Table 12-3. Mnemonic BXJ BLX (1) SMLAxy SMLAL SMLAWy SMULxy SMULWy QADD QDADD QSUB QDSUB New ARM Instruction Mnemonic List Operation Branch and exchange to Java Branch, Link and exchange Signed Multiply Accumulate 16 * 16 bit Signed Multiply Accumulate Long Signed Multiply Accumulate 32 * 16 bit Signed Multiply 16 * 16 bit Signed Multiply 32 * 16 bit Saturated Add Saturated Add with Double Saturated subtract Saturated Subtract with double Mnemonic MRRC MCR2 MCRR CDP2 BKPT PLD STRD STC2 LDRD LDC2 CLZ Operation Move double from coprocessor Alternative move of ARM reg to coprocessor Move double to coprocessor Alternative Coprocessor Data Processing Breakpoint Soft Preload, Memory prepare to load from address Store Double Alternative Store from Coprocessor Load Double Alternative Load to Coprocessor Count Leading Zeroes Notes: 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. 12.3.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into: • Branch instructions • Data processing instructions • Load and Store instructions • Load and Store multiple instructions • Exception-generating instruction Table 5 shows the Thumb instruction set. Table 12-4 gives the Thumb instruction mnemonic list. Table 12-4. Mnemonic MOV ADD SUB CMP TST AND Thumb Instruction Mnemonic List Operation Move Add Subtract Compare Test Logical AND Mnemonic MVN ADC SBC CMN NEG BIC Operation Move Not Add with Carry Subtract with Carry Compare Negated Negate Bit Clear 57 6289C–ATARM–28-May-09 Table 12-4. Mnemonic EOR LSL ASR MUL B BX LDR LDRH LDRB LDRSH LDMIA PUSH BCC Thumb Instruction Mnemonic List (Continued) Operation Logical Exclusive OR Logical Shift Left Arithmetic Shift Right Multiply Branch Branch and Exchange Load Word Load Half Word Load Byte Load Signed Halfword Load Multiple Push Register to stack Conditional Branch Mnemonic ORR LSR ROR BLX BL SWI STR STRH STRB LDRSB STMIA POP BKPT Operation Logical (inclusive) OR Logical Shift Right Rotate Right Branch, Link, and Exchange Branch and Link Software Interrupt Store Word Store Half Word Store Byte Load Signed Byte Store Multiple Pop Register from stack Breakpoint 12.4 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below: • ARM9EJ-S • Caches (ICache, DCache and write buffer) • TCM • MMU • Other system options To control these features, CP15 provides 16 additional registers. See Table 12-5. Table 12-5. Register 0 0 0 1 2 3 4 5 5 6 7 CP15 Registers Name ID Code (1) Read/Write Read/Unpredictable Read/Unpredictable Read/Unpredictable Read/write Read/write Read/write None (1) (1) Cache type(1) TCM status Control Translation Table Base Domain Access Control Reserved Data fault Status (1) Read/write Read/write Read/write Read/Write Instruction fault status Fault Address Cache Operations 58 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 12-5. Register 8 9 9 10 11 12 13 13 14 15 Notes: CP15 Registers Name TLB operations cache lockdown TCM region TLB lockdown Reserved Reserved FCSE PID (1) (2) Read/Write Unpredictable/Write Read/write Read/write Read/write None None Read/write Read/Write None Read/Write Context ID(1) Reserved Test configuration 1. Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. 59 6289C–ATARM–28-May-09 12.4.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by: • MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15. • MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 27 26 25 24 cond 23 22 21 20 1 19 1 18 1 17 0 16 opcode_1 15 14 13 L 12 11 10 CRn 9 8 Rd 7 6 5 4 1 3 1 2 1 1 1 0 opcode_2 1 CRm • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. • opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. • Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. 60 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 12.5 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, WindowsCE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 7 shows the different attributes of each page in the physical memory. Table 12-6. Mapping Details Mapping Size 1M byte 64K bytes 4K bytes 1K byte Access Permission By Section 4 separated subpages 4 separated subpages Tiny Page Subpage Size 16K bytes 1K byte - Mapping Name Section Large Page Small Page Tiny Page The MMU consists of: • Access control logic • Translation Look-aside Buffer (TLB) • Translation table walk hardware 12.5.1 Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 61 6289C–ATARM–28-May-09 12.5.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 12.5.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Pagemapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 12.5.4 MMU Faults The MMU generates an abort on the following types of faults: • Alignment faults (for data accesses only) • Translation faults • Domain faults • Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core.The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 12.6 Caches and Write Buffer The ARM926EJ-S contains a 4 KB Instruction Cache (ICache), a 4 KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. 62 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 12.6.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat-mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 12.6.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA ASB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. 12.6.2.1 63 6289C–ATARM–28-May-09 The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 12.6.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and writeback region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not up-to-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 12.7 12.7.1 Tightly-Coupled Memory Interface TCM Description The ARM926EJ-S processor features a Tightly-Coupled Memory (TCM) interface, which enables separate instruction and data TCMs (ITCM and DTCM) to be directly reached by the processor. TCMs are used to store real-time and performance critical code, they also provide a DMA support mechanism. Unlike AHB accesses to external memories, accesses to TCMs are fast and deterministic and do not incur bus penalties. The user has the possibility to independently configure each TCM size with values within the following ranges, [0KB, 32 KB] for ITCM size and [0KB, 32 KB] for DTCM size. TCMs can be configured by two means: HMATRIX TCM register and TCM region register (register 9) in CP15 and both steps should be performed. HMATRIX TCM register sets TCM size whereas TCM region register (register 9) in CP15 maps TCMs and enables them. The data side of the ARM9EJ-S core is able to access the ITCM. This is necessary to enable code to be loaded into the ITCM, for SWI and emulated instruction handlers, and for accesses to PC-relative literal pools. 64 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 12.7.2 Enabling and Disabling TCMs Prior to any enabling step, the user should configure the TCM sizes in HMATRIX TCM register. Then enabling TCMs is performed by using TCM region register (register 9) in CP15. The user should use the same sizes as those put in HMATRIX TCM register. For further details and programming tips, please refer to chapter 2.3 in ARM926EJ-S TRM, ref. DDI0222B. TCM Mapping The TCMs can be located anywhere in the memory map, with a single region available for ITCM and a separate region available for DTCM. The TCMs are physically addressed and can be placed anywhere in physical address space. However, the base address of a TCM must be aligned to its size, and the DTCM and ITCM regions must not overlap. TCM mapping is performed by using TCM region register (register 9) in CP15. The user should input the right mapping address for TCMs. 12.7.3 12.8 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: • It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture. • Each AHB layer becomes simple because it only has one master, so no arbitration or masterto-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions. • The arbitration becomes effective when more than one master wants to access the same slave simultaneously. 12.8.1 Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. 65 6289C–ATARM–28-May-09 Table 8 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 12-7. HBurst[2:0] Supported Transfers Description Single transfer of word, half word, or byte: • data write (NCNB, NCB, WT, or WB that has missed in DCache) SINGLE Single transfer • data read (NCNB or NCB) • NC instruction fetch (prefetched and non-prefetched) • page table walk read Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write. Cache linefill INCR4 INCR8 WRAP8 Four-word incrementing burst Eight-word incrementing burst Eight-word wrapping burst 12.8.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time. Address Alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. 12.8.3 66 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 13. AT91SAM9R64/RL64 Debug and Test 13.1 Description The AT91SAM9R64/RL64 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 67 6289C–ATARM–28-May-09 13.2 Block Diagram Figure 13-1. Debug and Test Block Diagram TMS TCK TDI NTRST Boundary Port ICE/JTAG TAP JTAGSEL TDO RTCK Reset and Test POR TST ARM9EJ-S ICE-RT ARM926EJ-S PDC DBGU PIO DTXD DRXD TAP: Test Access Port 68 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 13.3 13.3.1 Application Examples Debug Environment Figure 13-2 on page 69 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. The Trace Port interface is used for tracing information. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 13-2. Application Debug and Trace Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector AT91SAM9RL RS232 Connector Terminal AT91SAM9RLbased Application 13.3.2 Test Environment Figure 13-3 on page 69 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAGcompliant devices. These devices can be connected to form a single scan chain. Figure 13-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector Chip n Chip 2 AT91SAM9RL Chip 1 AT91SAM9RL-based Application Board In Test 69 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 13.4 Debug and Test Pin Description Table 13-1. Pin Name Debug and Test Pin List Function Reset/Test Type Active Level NTRST NRST TST Test Reset Signal Microcontroller Reset Test Mode Select ICE and JTAG Input Input/Output Input Low Low High TCK TDI TDO TMS RTCK JTAGSEL Test Clock Test Data In Test Data Out Test Mode Select Returned Test Clock JTAG Selection Debug Unit Input Input Output Input Output Input DRXD DTXD Debug Receive Data Debug Transmit Data Input Output 13.5 13.5.1 Functional Description Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 13.5.2 Embedded In-circuit Emulator The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a storemultiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the Embedded ICE-RT™. The scan chains are controlled by the ICE/JTAG port. Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document: ARM9EJ-S Technical Reference Manual (DDI 0222A). 70 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 13.5.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 13.5.4 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The AT91SAM9R64/RL64 Debug Unit Chip ID value is 0x0196 07A0 on 32-bit width. For further details on the Debug Unit, see the Debug Unit section. 13.5.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. 71 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 13.5.6 ID Code Register Access: Read-only 31 30 29 28 27 26 25 24 VERSION 23 22 21 20 19 PART NUMBER 18 17 16 PART NUMBER 15 14 13 12 11 10 9 8 PART NUMBER 7 6 5 4 3 MANUFACTURER IDENTITY 2 1 0 MANUFACTURER IDENTITY 1 • MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] Required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_003F. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B20. • VERSION[31:28]: Product Version Number Set to 0x0. 72 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 14. AT91SAM9R64/RL64 Boot Program 14.1 Description The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. Then the SD Card Boot program is executed. It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SD Card. If such a file is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If the SD Card is not formatted or if boot.bin file is not found, NAND Flash Boot program is then executed. The NAND Flash Boot program searches for a valid application in the NAND Flash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See “DataFlash Boot” on page 75 for more information on Valid Image Detection. If no valid ARM vector sequence is found, the DataFlash Boot program is then executed. It looks for a sequence of seven valid ARM exception vectors in a DataFlash connected to the SPI. All these vectors must be B-branch or LDR load register instructions except for the sixth vector. This vector is used to store the size of the image to download. If a valid sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, SAM-BA Boot is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 14.2 Flow Diagram The Boot Program implements the algorithm in Figure 14-1. 73 6289C–ATARM–28-May-09 Figure 14-1. Boot Program Algorithm Flow Diagram Device Setup SD Card Boot Yes Download from SD Card (MCI) Run SD Card Boot No Timeout < 1 s NandFlash Boot Yes Download from NandFlash Run NandFlash Boot No Timeout < 1 s SPI DataFlash Boot Yes Download from DataFlash (NPCS0) Run DataFlash Boot No Timeout < 1 s No USB Enumeration Successful ? No Character(s) received on DBGU ? SAM-BA Boot Yes Run SAM-BA Boot Yes Run SAM-BA Boot 14.3 Device Initialization Initialization follows the steps described below: 1. Stack setup for ARM supervisor mode 2. Main Oscillator Frequency Detection 3. C variable initialization 4. UTMI PLL is enabled to generate a 480MHz clock necessary to use the USB High Speed Device. 5. PLL setup: PLL is initialized to generate a 96 MHz clock. Note: A 12 MHz Crystal is mandatory in order to generate these clocks correctly. 6. MCK is configured to generate a 48MHz clock (PLL/2). 7. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) 8. Enable the user reset 74 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 9. Jump to SD Card Boot sequence. If SD Card Boot succeeds, perform a remap and jump to 0x0. 10. Jump to NAND Flash Boot sequence. If NAND Flash Boot succeeds, perform a remap and jump to 0x0. 11. Jump to DataFlash Boot sequence through NPCS0. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 12. Activation of the Instruction Cache 13. Jump to SAM-BA Boot sequence 14. Disable the WatchDog 15. Initialization of the USB Device Port Figure 14-2. Remap Action after Download Completion 0x0000_0000 Internal ROM REMAP 0x0030_0000 Internal SRAM Internal ROM 0x0010_0000 Internal SRAM 0x0000_0000 14.4 DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. After reset, the code in internal ROM is mapped at both addresses 0x0000_0000 and 0x0040_0000: 400000 400004 400008 40000c 400010 400014 400018 ea000006 eafffffe ea00002f eafffffe eafffffe eafffffe eafffffe B B B B B B B 0x20 0x04 _main 0x0c 0x10 0x14 0x18 00ea000006B0x20 04eafffffeB0x04 08ea00002fB_main 0ceafffffeB0x0c 10eafffffeB0x10 14eafffffeB0x14 18eafffffeB0x18 14.4.1 Valid Image Detection The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corresponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his own vector (see “Structure of ARM Vector 6” on page 76). 75 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 14-3. LDR Opcode 31 1 1 1 28 27 0 1 1 I 24 23 P U 1 W 20 19 0 Rn 16 15 Rd 12 11 0 Figure 14-4. B Opcode 31 1 1 1 28 27 0 1 0 1 24 23 0 Offset (24 bits) 0 Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: – Rn = Rd = PC = 0xF – I==1 – P==1 – U offset added (U==1) or subtracted (U==0) – W==1 14.4.2 Structure of ARM Vector 6 The ARM exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below. Figure 14-5. Structure of the ARM Vector 6 31 Size of the code to download in bytes 0 14.4.2.1 Example An example of valid vectors follows: 00 04 08 0c 10 14 18 ea000006 eafffffe ea00002f eafffffe eafffffe 00001234 eafffffe B 0x18 B B B B B 0x20 0x04 _main 0x0c 0x10 ’. • Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. – Address: Address in hexadecimal – Output: The byte, halfword or word read in hexadecimal following by ‘>’ • Send a file (S): Send a file to a specified address – Address: Address in hexadecimal – Output: ‘>’. Note: There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. • Receive a file (R): Receive data into a file from a specified address – Address: Address in hexadecimal 79 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – NbOfBytes: Number of bytes in hexadecimal to receive – Output: ‘>’ • Go (G): Jump to a specified address and execute the code – Address: Address to jump in hexadecimal – Output: ‘>’ • Get Version (V): Return the SAM-BA boot version – Output: ‘>’ 14.7.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. 14.7.2 Xmodem Protocol The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: – = 01 hex – = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) – = 1’s complement of the blk#. – = 2 bytes CRC16 Figure 14-7 shows a transmission using this protocol. 80 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 14-7. Xmodem Transfer Example Host C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK Device 14.7.3 USB High Speed Device Port A 480 MHz USB clock is necessary to use the USB High Speed Device port. It has been programmed earlier in the device initialization procedure with UTMI PLL configuration. The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details. 14.7.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 14-3. Request GET_DESCRIPTOR SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION GET_STATUS SET_FEATURE CLEAR_FEATURE Handled Standard Requests Definition Returns the current device configuration value. Sets the device address for all future device access. Sets the device configuration. Returns the current device configuration value. Returns status for the specified recipient. Used to set or enable a specific feature. Used to clear or disable a specific feature. 81 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary The device also handles some class requests defined in the CDC class. Table 14-4. Request SET_LINE_CODING GET_LINE_CODING SET_CONTROL_LINE_STATE Handled Class Requests Definition Configures DTE rate, stop bits, parity and number of character bits. Requests current DTE rate, stop bits, parity and number of character bits. RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 14.7.3.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 512-byte Bulk OUT endpoint and endpoint 2 is a 512-byte Bulk IN endpoint. SAM-BA Boot commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 14.8 Hardware and Software Constraints • A 12 MHz Crystal is mandatory in order to generate correctly 480 MHz clock necessary for the USB High Speed Device and to generate the 48 MHz System clock. • No Bypass Mode. • The SD Card, NAND Flash and DataFlash downloaded code size must be inferior to 56 K bytes. • The code is always downloaded from the DataFlash or NAND Flash device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). • The downloaded code must be position-independent or linked at address 0x0000_0000. • The DataFlash must be connected to NPCS0 of the SPI. The MCI, the SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between peripherals output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 14-5 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. For the DataFlash driven by the SPCK signal at 8 MHz, the time to download 60 K bytes is reduced to 200 ms. 82 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 14-5. Peripheral MCI MCI MCI MCI MCI MCI SPI SPI SPI SPI PIO Controller B PIO Controller B PIO Controller B Address Bus Address Bus DBGU DBGU Pins Driven during Boot Program Execution Pin MCDA0 MCCDA MCCK MCDA1 MCDA2 MCDA3 MISO MOSI SPCK NPCS0 NAND OE NAND WE NANDCS NAND ALE NAND CLE DRXD DTXD PIO Line PIOA0 PIOA1 PIOA2 PIOA3 PIOA4 PIOA5 PIOA25 PIOA26 PIOA27 PIOA28 PIOB4 PIOB5 PIOB6 A21 A22 PIOA21 PIOA22 83 6289C–ATARM–28-May-09 84 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 15. Reset Controller (RSTC) 15.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 15.2 Block Diagram Figure 15-1. Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR Startup Counter rstc_irq Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager exter_nreset periph_nreset backup_neset WDRPROC wd_fault SLCK 85 6289C–ATARM–28-May-09 15.3 15.3.1 Functional Description Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals: • proc_nreset: Processor reset line. It also resets the Watchdog Timer. • backup_nreset: Affects all the peripherals powered by VDDBU. • periph_nreset: Affects the whole set of embedded peripherals. • nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 15.3.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 15-2 shows the block diagram of the NRST Manager. Figure 15-2. NRST Manager RSTC_MR RSTC_SR URSTIEN rstc_irq RSTC_MR URSTS NRSTL Other interrupt sources user_reset URSTEN NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset 15.3.2.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. 86 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. 15.3.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 15.3.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On-Reset output rising edge. Figure 15-3. BMS Sampling SLCK Core Supply POR output XXX BMS sampling delay = 3 cycles BMS Signal H or L proc_nreset 87 6289C–ATARM–28-May-09 15.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 15.3.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for 3 cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises 2 cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 15-4 shows how the General Reset affects the reset signals. Figure 15-4. General Reset State SLCK MCK Backup Supply POR output Any Freq. Startup Time Main Supply POR output backup_nreset Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset XXX 0x0 = General Reset XXX NRST (nrst_out) BMS Sampling EXTERNAL RESET LENGTH = 2 cycles 88 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 15.3.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during 3 Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR. Figure 15-5. Wake-up State SLCK MCK Main Supply POR output Any Freq. backup_nreset Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 89 6289C–ATARM–28-May-09 15.3.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a 3-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 15-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Any XXX 0x4 = User Reset NRST (nrst_out) >= EXTERNAL RESET LENGTH 90 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 15.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1: • PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer. • PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes. • EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. 91 6289C–ATARM–28-May-09 Figure 15-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) Any XXX 0x3 = Software Reset SRCMP in RSTC_SR 15.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR: • If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state. • If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. 92 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 15-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP periph_nreset Only if WDRPROC = 0 Any XXX 0x2 = Watchdog Reset NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 15.3.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order: • Backup Reset • Wake-up Reset • Watchdog Reset • Software Reset • User Reset Particular cases are listed below: • When in User Reset: – A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal. – A software reset is impossible, since the processor reset is being activated. • When in Software Reset: – A watchdog event has priority over the current state. – The NRST has no effect. • When in Watchdog Reset: – The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered. 15.3.6 Reset Controller Status Register The Reset Controller status register (RSTC_SR) provides several status fields: • RSTTYP field: This field gives the type of the last reset, as explained in previous sections. 93 6289C–ATARM–28-May-09 • SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset. • NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge. • URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 15-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt. Figure 15-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization NRST NRSTL 2 cycle resynchronization URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 94 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 15.4 Reset Controller (RSTC) User Interface Reset Controller (RSTC) Register Mapping Register Control Register Status Register Mode Register Name RSTC_CR RSTC_SR RSTC_MR Access Write-only Read-only Read/Write Reset Value 0x0000_0001 0x0000_0000 0x0000_0000 Back-up Reset Value Table 15-1. Offset 0x00 0x04 0x08 Note: 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. 95 6289C–ATARM–28-May-09 15.4.1 Reset Controller Control Register Register Name: RSTC_CR Access Type: 31 Write-only 30 29 28 KEY 27 26 25 24 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 – 20 – 12 – 4 – 19 – 11 – 3 EXTRST 18 – 10 – 2 PERRST 17 – 9 16 – 8 – 0 PROCRST 1 – • PROCRST: Processor Reset 0 = No effect. 1 = If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0 = No effect. 1 = If KEY is correct, resets the peripherals. • EXTRST: External Reset 0 = No effect. 1 = If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 96 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 15.4.2 Reset Controller Status Register Register Name: RSTC_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 25 – 17 SRCMP 9 RSTTYP 1 – 24 – 16 NRSTL 8 2 – 0 URSTS • URSTS: User Reset Status 0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP 0 0 0 0 1 0 0 1 1 0 0 1 0 1 0 Reset Type General Reset Wake Up Reset Watchdog Reset Software Reset User Reset Comments Both VDDCORE and VDDBU rising VDDCORE rising Watchdog fault occurred Processor reset required by the software NRST pin detected low • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy. 97 6289C–ATARM–28-May-09 15.4.3 Reset Controller Mode Register Register Name: RSTC_MR Access Type: 31 Read/Write 30 29 28 KEY 27 26 25 24 23 – 15 – 7 – 22 – 14 – 6 – 21 – 13 – 5 20 – 12 – 4 URSTIEN 19 – 11 18 – 10 ERSTL 17 – 9 16 8 3 – 2 – 1 – 0 URSTEN • URSTEN: User Reset Enable 0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 98 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 16. Real-time Timer (RTT) 16.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 16.2 Block Diagram Figure 16-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK reload 16-bit Divider RTT_MR RTTRST 1 0 RTTINCIEN 0 RTT_SR set RTTINC reset rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR CRTV RTT_SR reset ALMS set = RTT_AR ALMV rtt_alarm 16.3 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. 99 6289C–ATARM–28-May-09 The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). Figure 16-2. RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 ALMV+2 ALMV+3 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 100 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 16.4 16.4.1 Real-time Timer (RTT) User Interface Register Mapping Real-time Timer Register Mapping Register Mode Register Alarm Register Value Register Status Register Name RTT_MR RTT_AR RTT_VR RTT_SR Access Read/Write Read/Write Read-only Read-only Reset Value 0x0000_8000 0xFFFF_FFFF 0x0000_0000 0x0000_0000 Table 16-1. Offset 0x00 0x04 0x08 0x0C 101 6289C–ATARM–28-May-09 16.4.2 Real-time Timer Mode Register Register Name: RTT_MR Access Type: 31 – 23 – 15 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RTPRES 27 – 19 – 11 26 – 18 RTTRST 10 25 – 17 RTTINCIEN 9 24 – 16 ALMIEN 8 7 6 5 4 RTPRES 3 2 1 0 • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216 RTPRES ≠ 0: The prescaler period is equal to RTPRES. • ALMIEN: Alarm Interrupt Enable 0 = The bit ALMS in RTT_SR has no effect on interrupt. 1 = The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0 = The bit RTTINC in RTT_SR has no effect on interrupt. 1 = The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 102 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 16.4.3 Real-time Timer Alarm Register Register Name: RTT_AR Access Type: 31 Read/Write 30 29 28 ALMV 27 26 25 24 23 22 21 20 ALMV 19 18 17 16 15 14 13 12 ALMV 11 10 9 8 7 6 5 4 ALMV 3 2 1 0 • ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. 16.4.4 Real-time Timer Value Register Register Name: RTT_VR Access Type: 31 Read-only 30 29 28 CRTV 27 26 25 24 23 22 21 20 CRTV 19 18 17 16 15 14 13 12 CRTV 11 10 9 8 7 6 5 4 CRTV 3 2 1 0 • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 103 6289C–ATARM–28-May-09 16.4.5 Real-time Timer Status Register Register Name: RTT_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 RTTINC 24 – 16 – 8 – 0 ALMS • ALMS: Real-time Alarm Status 0 = The Real-time Alarm has not occurred since the last read of RTT_SR. 1 = The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0 = The Real-time Timer has not been incremented since the last read of the RTT_SR. 1 = The Real-time Timer has been incremented since the last read of the RTT_SR. 104 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 17. Periodic Interval Timer (PIT) 17.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 17.2 Block Diagram Figure 17-1. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset pit_irq 0 0 1 0 1 12-bit Adder read PIT_PIVR MCK 20-bit Counter Prescaler MCK/16 CPIV PIT_PIVR PICNT CPIV PIT_PIIR PICNT 105 6289C–ATARM–28-May-09 17.3 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 17-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. 106 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 17-2. Enabling/Disabling PIT with PITEN APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN APB cycle CPIV PICNT PITS (PIT_SR) APB Interface 0 1 0 PIV - 1 PIV 1 0 0 1 read PIT_PIVR 107 6289C–ATARM–28-May-09 17.4 Periodic Interval Timer (PIT) User Interface Periodic Interval Timer (PIT) Register Mapping Register Mode Register Status Register Periodic Interval Value Register Periodic Interval Image Register Name PIT_MR PIT_SR PIT_PIVR PIT_PIIR Access Read/Write Read-only Read-only Read-only Reset Value 0x000F_FFFF 0x0000_0000 0x0000_0000 0x0000_0000 Table 17-1. Offset 0x00 0x04 0x08 0x0C 108 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 17.4.1 Periodic Interval Timer Mode Register Register Name: PIT_MR Access Type: 31 – 23 – 15 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 PIV 27 – 19 26 – 18 PIV 11 10 9 8 25 PITIEN 17 24 PITEN 16 7 6 5 4 PIV 3 2 1 0 • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0 = The Periodic Interval Timer is disabled when the PIV value is reached. 1 = The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0 = The bit PITS in PIT_SR has no effect on interrupt. 1 = The bit PITS in PIT_SR asserts interrupt. 17.4.2 Periodic Interval Timer Status Register Register Name: PIT_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 PITS • PITS: Periodic Interval Timer Status 0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 109 6289C–ATARM–28-May-09 17.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR Access Type: 31 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 17.4.4 Periodic Interval Timer Image Register Register Name: PIT_PIIR Access Type: 31 Read-only 30 29 28 PICNT 27 26 25 24 23 22 PICNT 21 20 19 18 CPIV 17 16 15 14 13 12 CPIV 11 10 9 8 7 6 5 4 CPIV 3 2 1 0 • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 110 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 18. Watchdog Timer (WDT) 18.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 18.2 Block Diagram Figure 18-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDT_CR WDRSTT reload 1 0 WDV 12-bit Down Counter WDT_MR WDD Current Value reload 1/128 SLCK 1 1 0 0 Receiver Sampling Clock Divide by 16 Baud Rate Clock 30.4.2 30.4.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit. The programmer can disable the receiver by writing DBGU_CR with the bit RXDIS at 1. If the receiver is waiting for a start bit, it is immediately stopped. However, if the receiver has already detected a start bit and is receiving the data, it waits for the stop bit before actually stopping its operation. The programmer can also put the receiver in its reset state by writing DBGU_CR with the bit RSTRX at 1. In doing so, the receiver immediately stops its current operations and is disabled, whatever its current state. If RSTRX is applied when data is being processed, this data is lost. 30.4.2.2 Start Detection and Data Sampling The Debug Unit only supports asynchronous operations, and this affects only its receiver. The Debug Unit receiver detects the start of a received character by sampling the DRXD signal until it detects a valid start bit. A low level (space) on DRXD is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Hence, a space that is longer than 7/16 of the bit period is detected as a valid start bit. A space which is 7/16 of a bit period or shorter is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the DRXD at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1-bit period) so the bit sampling point is eight cycles (0.5-bit period) after the start of the bit. The first sampling point is therefore 24 cycles (1.5-bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1-bit period) after the previous one. 326 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 30-4. Start Bit Detection Sampling Clock DRXD True Start Detection Baud Rate Clock D0 Figure 30-5. Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling D0 D1 True Start Detection D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 30.4.2.3 Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read. Figure 30-6. Receiver Ready DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P S D0 D1 D2 D3 D4 D5 D6 D7 P RXRDY Read DBGU_RHR 30.4.2.4 Receiver Overrun If DBGU_RHR has not been read by the software (or the Peripheral Data Controller) since the last transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1. Figure 30-7. Receiver Overrun DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY OVRE RSTSTA 30.4.2.5 Parity Error Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field PAR in DBGU_MR. It then compares the result with the received parity 327 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary bit. If different, the parity error bit PARE in DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is written, the PARE bit remains at 1. Figure 30-8. Parity Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY PARE Wrong Parity Bit RSTSTA 30.4.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1. Figure 30-9. Receiver Framing Error DRXD S D0 D1 D2 D3 D4 D5 D6 D7 P stop RXRDY FRAME Stop Bit Detected at 0 RSTSTA 30.4.3 30.4.3.1 Transmitter Transmitter Reset, Enable and Disable After device reset, the Debug Unit transmitter is disabled and it must be enabled before being used. The transmitter is enabled by writing the control register DBGU_CR with the bit TXEN at 1. From this command, the transmitter waits for a character to be written in the Transmit Holding Register DBGU_THR before actually starting the transmission. The programmer can disable the transmitter by writing DBGU_CR with the bit TXDIS at 1. If the transmitter is not operating, it is immediately stopped. However, if a character is being processed into the Shift Register and/or a character has been written in the Transmit Holding Register, the characters are completed before the transmitter is actually stopped. The programmer can also put the transmitter in its reset state by writing the DBGU_CR with the bit RSTTX at 1. This immediately stops the transmitter, whether or not it is processing characters. 30.4.3.2 Transmit Format The Debug Unit transmitter drives the pin DTXD at the baud rate clock speed. The line is driven depending on the format defined in the Mode Register and the data stored in the Shift Register. One start bit at level 0, then the 8 data bits, from the lowest to the highest bit, one optional parity bit and one stop bit at 1 are consecutively shifted out as shown on the following figure. The field 328 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary PARE in the mode register DBGU_MR defines whether or not a parity bit is shifted out. When a parity bit is enabled, it can be selected between an odd parity, an even parity, or a fixed space or mark bit. Figure 30-10. Character Transmission Example: Parity enabled Baud Rate Clock DTXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 30.4.3.3 Transmitter Control When the transmitter is enabled, the bit TXRDY (Transmitter Ready) is set in the status register DBGU_SR. The transmission starts when the programmer writes in the Transmit Holding Register DBGU_THR, and after the written character is transferred from DBGU_THR to the Shift Register. The bit TXRDY remains high until a second character is written in DBGU_THR. As soon as the first character is completed, the last character written in DBGU_THR is transferred into the shift register and TXRDY rises again, showing that the holding register is empty. When both the Shift Register and the DBGU_THR are empty, i.e., all the characters written in DBGU_THR have been processed, the bit TXEMPTY rises after the last stop bit has been completed. Figure 30-11. Transmitter Control DBGU_THR Data 0 Data 1 Shift Register Data 0 Data 1 DTXD S Data 0 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR Write Data 1 in DBGU_THR 30.4.4 Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel. The peripheral data controller channels are programmed via registers that are mapped within the Debug Unit user interface from the offset 0x100. The status bits are reported in the Debug Unit status register DBGU_SR and can generate an interrupt. 329 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary The RXRDY bit triggers the PDC channel data transfer of the receiver. This results in a read of the data in DBGU_RHR. The TXRDY bit triggers the PDC channel data transfer of the transmitter. This results in a write of a data in DBGU_THR. 30.4.5 Test Modes The Debug Unit supports three tests modes. These modes of operation are programmed by using the field CHMODE (Channel Mode) in the mode register DBGU_MR. The Automatic Echo mode allows bit-by-bit retransmission. When a bit is received on the DRXD line, it is sent to the DTXD line. The transmitter operates normally, but has no effect on the DTXD line. The Local Loopback mode allows the transmitted characters to be received. DTXD and DRXD pins are not used and the output of the transmitter is internally connected to the input of the receiver. The DRXD pin level has no effect and the DTXD line is held high, as in idle state. The Remote Loopback mode directly connects the DRXD pin to the DTXD line. The transmitter and the receiver are disabled and have no effect. This mode allows a bit-by-bit retransmission. Figure 30-12. Test Modes Automatic Echo Receiver RXD Transmitter Disabled TXD Local Loopback Receiver Disabled RXD VDD Transmitter Disabled TXD Remote Loopback Receiver VDD Disabled RXD Transmitter Disabled TXD 30.4.6 Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the ARM Processor and are driven by the In-circuit Emulator. 330 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary The Debug Communication Channel contains two registers that are accessible through the ICE Breaker on the JTAG side and through the coprocessor 0 on the ARM Processor side. As a reminder, the following instructions are used to read and write the Debug Communication Channel: MRC p14, 0, Rd, c1, c0, 0 Returns the debug communication data read register into Rd MCR p14, 0, Rd, c1, c0, 0 Writes the value in Rd to the debug communication data write register. The bits COMMRX and COMMTX, which indicate, respectively, that the read register has been written by the debugger but not yet read by the processor, and that the write register has been written by the processor and not yet read by the debugger, are wired on the two highest bits of the status register DBGU_SR. These bits can generate an interrupt. This feature permits handling under interrupt a debug link between a debug monitor running on the target system and a debugger. 30.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only. The first register contains the following fields: • EXT - shows the use of the extension identifier register • NVPTYP and NVPSIZ - identifies the type of embedded non-volatile memory and its size • ARCH - identifies the set of embedded peripherals • SRAMSIZ - indicates the size of the embedded SRAM • EPROC - indicates the embedded ARM processor • VERSION - gives the revision of the silicon The second register is device-dependent and reads 0 if the bit EXT is 0. 30.4.8 ICE Access Prevention The Debug Unit allows blockage of access to the system through the ARM processor's ICE interface. This feature is implemented via the register Force NTRST (DBGU_FNR), that allows assertion of the NTRST signal of the ICE Interface. Writing the bit FNTRST (Force NTRST) to 1 in this register prevents any activity on the TAP controller. On standard devices, the bit FNTRST resets to 0 and thus does not prevent ICE access. This feature is especially useful on custom ROM devices for customers who do not want their on-chip code to be visible. 331 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5 Debug Unit User Interface Debug Unit Memory Map Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Status Register Receive Holding Register Transmit Holding Register Baud Rate Generator Register Reserved Chip ID Register Chip ID Extension Register Force NTRST Register Reserved PDC Area Name DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR DBGU_SR DBGU_RHR DBGU_THR DBGU_BRGR – DBGU_CIDR DBGU_EXID DBGU_FNR – – Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write – Read-only Read-only Read/Write – – Reset Value – 0x0 – – 0x0 – 0x0 – 0x0 – – – 0x0 – – Table 30-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 - 0x003C 0x0040 0x0044 0x0048 0x004C - 0x00FC 0x0100 - 0x0124 332 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.1 Name: Debug Unit Control Register DBGU_CR Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RSTSTA 0 – 7 TXDIS – 6 TXEN – 5 RXDIS – 4 RXEN – 3 RSTTX – 2 RSTRX – 1 – – • RSTRX: Reset Receiver 0 = No effect. 1 = The receiver logic is reset and disabled. If a character is being received, the reception is aborted. • RSTTX: Reset Transmitter 0 = No effect. 1 = The transmitter logic is reset and disabled. If a character is being transmitted, the transmission is aborted. • RXEN: Receiver Enable 0 = No effect. 1 = The receiver is enabled if RXDIS is 0. • RXDIS: Receiver Disable 0 = No effect. 1 = The receiver is disabled. If a character is being processed and RSTRX is not set, the character is completed before the receiver is stopped. • TXEN: Transmitter Enable 0 = No effect. 1 = The transmitter is enabled if TXDIS is 0. • TXDIS: Transmitter Disable 0 = No effect. 1 = The transmitter is disabled. If a character is being processed and a character has been written the DBGU_THR and RSTTX is not set, both characters are completed before the transmitter is stopped. • RSTSTA: Reset Status Bits 0 = No effect. 1 = Resets the status bits PARE, FRAME and OVRE in the DBGU_SR. 333 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.2 Name: Debug Unit Mode Register DBGU_MR Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 CHMODE 7 – 14 – 13 – 12 – 11 – 10 PAR – 9 – 8 – 6 5 – 4 3 – 1 0 2 – – – – – – – – • PAR: Parity Type PAR 0 0 0 0 1 0 0 1 1 x 0 1 0 1 x Parity Type Even parity Odd parity Space: parity forced to 0 Mark: parity forced to 1 No parity • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo Local Loopback Remote Loopback 334 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.3 Name: Debug Unit Interrupt Enable Register DBGU_IER Write-only 30 COMMTX 22 29 28 27 26 25 24 Access Type: 31 COMMRX 23 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Enable RXRDY Interrupt • TXRDY: Enable TXRDY Interrupt • ENDRX: Enable End of Receive Transfer Interrupt • ENDTX: Enable End of Transmit Interrupt • OVRE: Enable Overrun Error Interrupt • FRAME: Enable Framing Error Interrupt • PARE: Enable Parity Error Interrupt • TXEMPTY: Enable TXEMPTY Interrupt • TXBUFE: Enable Buffer Empty Interrupt • RXBUFF: Enable Buffer Full Interrupt • COMMTX: Enable COMMTX (from ARM) Interrupt • COMMRX: Enable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Enables the corresponding interrupt. 335 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.4 Name: Debug Unit Interrupt Disable Register DBGU_IDR Write-only 30 COMMTX 22 29 28 27 26 25 24 Access Type: 31 COMMRX 23 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Disable RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Disable End of Receive Transfer Interrupt • ENDTX: Disable End of Transmit Interrupt • OVRE: Disable Overrun Error Interrupt • FRAME: Disable Framing Error Interrupt • PARE: Disable Parity Error Interrupt • TXEMPTY: Disable TXEMPTY Interrupt • TXBUFE: Disable Buffer Empty Interrupt • RXBUFF: Disable Buffer Full Interrupt • COMMTX: Disable COMMTX (from ARM) Interrupt • COMMRX: Disable COMMRX (from ARM) Interrupt 0 = No effect. 1 = Disables the corresponding interrupt. 336 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.5 Name: Debug Unit Interrupt Mask Register DBGU_IMR Read-only 30 COMMTX 22 29 28 27 26 25 24 Access Type: 31 COMMRX 23 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Mask RXRDY Interrupt • TXRDY: Disable TXRDY Interrupt • ENDRX: Mask End of Receive Transfer Interrupt • ENDTX: Mask End of Transmit Interrupt • OVRE: Mask Overrun Error Interrupt • FRAME: Mask Framing Error Interrupt • PARE: Mask Parity Error Interrupt • TXEMPTY: Mask TXEMPTY Interrupt • TXBUFE: Mask TXBUFE Interrupt • RXBUFF: Mask RXBUFF Interrupt • COMMTX: Mask COMMTX Interrupt • COMMRX: Mask COMMRX Interrupt 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 337 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.6 Name: Debug Unit Status Register DBGU_SR Read-only 30 COMMTX 22 29 28 27 26 25 24 Access Type: 31 COMMRX 23 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 RXBUFF 4 ENDTX – 11 TXBUFE 3 ENDRX – 10 – 9 TXEMPTY 1 TXRDY – 8 – 7 PARE – 6 FRAME – 5 OVRE – 2 – 0 RXRDY – • RXRDY: Receiver Ready 0 = No character has been received since the last read of the DBGU_RHR or the receiver is disabled. 1 = At least one complete character has been received, transferred to DBGU_RHR and not yet read. • TXRDY: Transmitter Ready 0 = A character has been written to DBGU_THR and not yet transferred to the Shift Register, or the transmitter is disabled. 1 = There is no character written to DBGU_THR not yet transferred to the Shift Register. • ENDRX: End of Receiver Transfer 0 = The End of Transfer signal from the receiver Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the receiver Peripheral Data Controller channel is active. • ENDTX: End of Transmitter Transfer 0 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is inactive. 1 = The End of Transfer signal from the transmitter Peripheral Data Controller channel is active. • OVRE: Overrun Error 0 = No overrun error has occurred since the last RSTSTA. 1 = At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0 = No framing error has occurred since the last RSTSTA. 1 = At least one framing error has occurred since the last RSTSTA. • PARE: Parity Error 0 = No parity error has occurred since the last RSTSTA. 1 = At least one parity error has occurred since the last RSTSTA. • TXEMPTY: Transmitter Empty 0 = There are characters in DBGU_THR, or characters being processed by the transmitter, or the transmitter is disabled. 1 = There are no characters in DBGU_THR and there are no characters being processed by the transmitter. 338 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • TXBUFE: Transmission Buffer Empty 0 = The buffer empty signal from the transmitter PDC channel is inactive. 1 = The buffer empty signal from the transmitter PDC channel is active. • RXBUFF: Receive Buffer Full 0 = The buffer full signal from the receiver PDC channel is inactive. 1 = The buffer full signal from the receiver PDC channel is active. • COMMTX: Debug Communication Channel Write Status 0 = COMMTX from the ARM processor is inactive. 1 = COMMTX from the ARM processor is active. • COMMRX: Debug Communication Channel Read Status 0 = COMMRX from the ARM processor is inactive. 1 = COMMRX from the ARM processor is active. 339 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.7 Name: Debug Unit Receiver Holding Register DBGU_RHR Read-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 RXCHR – 3 – 2 – 1 – 0 • RXCHR: Received Character Last received character if RXRDY is set. 30.5.8 Name: Debug Unit Transmit Holding Register DBGU_THR Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 TXCHR – 3 – 2 – 1 – 0 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 340 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.9 Name: Debug Unit Baud Rate Generator Register DBGU_BRGR Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 CD – 11 – 10 – 9 – 8 7 6 5 4 CD 3 2 1 0 • CD: Clock Divisor CD 0 1 2 to 65535 Baud Rate Clock Disabled MCK MCK / (CD x 16) 341 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.10 Name: Debug Unit Chip ID Register DBGU_CIDR Read-only 30 29 NVPTYP 22 ARCH 15 14 NVPSIZ2 7 6 EPROC 5 4 3 2 VERSION 13 12 11 10 NVPSIZ 1 0 21 20 19 18 SRAMSIZ 9 8 28 27 26 ARCH 17 16 25 24 Access Type: 31 EXT 23 • VERSION: Version of the Device • EPROC: Embedded Processor EPROC 0 0 1 1 0 1 0 0 1 0 0 1 Processor ARM946E-S™ ARM7TDMI® ARM920T™ ARM926EJ-S • NVPSIZ: Nonvolatile Program Memory Size NVPSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved 342 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size None 8K bytes 16K bytes 32K bytes Reserved 64K bytes Reserved 128K bytes Reserved 256K bytes 512K bytes Reserved 1024K bytes Reserved 2048K bytes Reserved • SRAMSIZ: Internal SRAM Size SRAMSIZ 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Size Reserved 1K bytes 2K bytes 6K bytes 112K bytes 4K bytes 80K bytes 160K bytes 8K bytes 16K bytes 32K bytes 64K bytes 128K bytes 256K bytes 96K bytes 512K bytes 343 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • ARCH: Architecture Identifier ARCH Hex 0x19 0x29 0x34 0x37 0x39 0x3B 0x40 0x42 0x55 0x60 0x61 0x63 0x70 0x71 0x72 0x73 0x75 0x92 0xF0 Bin 0001 1001 0010 1001 0011 0100 0011 0111 0011 1001 0011 1011 0100 0000 0100 0010 0101 0101 0110 0000 0110 0001 0110 0011 0111 0000 0111 0001 0111 0010 0111 0011 0111 0101 1001 0010 1111 0000 Architecture AT91SAM9xx Series AT91SAM9XExx Series AT91x34 Series CAP7 Series CAP9 Series CAP11 Series AT91x40 Series AT91x42 Series AT91x55 Series AT91SAM7Axx Series AT91SAM7AQxx Series AT91x63 Series AT91SAM7Sxx Series AT91SAM7XCxx Series AT91SAM7SExx Series AT91SAM7Lxx Series AT91SAM7Xxx Series AT91x92 Series AT75Cxx Series • NVPTYP: Nonvolatile Program Memory Type NVPTYP 0 0 1 0 0 0 0 0 1 1 0 1 0 0 1 Memory ROM ROMless or on-chip Flash SRAM emulating ROM Embedded Flash Memory ROM and Embedded Flash Memory NVPSIZ is ROM size NVPSIZ2 is Flash size • EXT: Extension Flag 0 = Chip ID has a single register definition without extension 1 = An extended Chip ID exists. 344 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 30.5.11 Name: Debug Unit Chip ID Extension Register DBGU_EXID Read-only 30 29 28 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Access Type: 31 • EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. 345 6289C–ATARM–28-May-09 30.5.12 Name: Debug Unit Force NTRST Register DBGU_FNR Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 FNTRST – – – – – – – • FNTRST: Force NTRST 0 = NTRST of the ARM processor’s TAP controller is driven by the power_on_reset signal. 1 = NTRST of the ARM processor’s TAP controller is held low. 346 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31. Parallel Input/Output Controller (PIO) 31.1 Description The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface. Each I/O line of the PIO Controller features: • An input change interrupt enabling level change detection on any I/O line. • A glitch filter providing rejection of pulses lower than one-half of clock cycle. • Multi-drive capability similar to an open drain I/O line. • Control of the pull-up of the I/O line. • Input visibility and output control. The PIO Controller also features a synchronous output providing up to 32 bits of data output in a single write operation. 347 6289C–ATARM–28-May-09 31.2 Block Diagram Figure 31-1. Block Diagram PIO Controller AIC PIO Interrupt PMC PIO Clock Data, Enable Embedded Peripheral Up to 32 peripheral IOs PIN 0 Data, Enable PIN 1 Up to 32 pins Embedded Peripheral Up to 32 peripheral IOs PIN 31 APB Figure 31-2. Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver General Purpose I/Os External Devices 348 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.3 31.3.1 Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware-defined and thus product-dependent, the hardware designer and programmer must carefully determine the configuration of the PIO controllers required by their application. When an I/O line is general-purpose only, i.e. not multiplexed with any peripheral I/O, programming of the PIO Controller regarding the assignment to a peripheral has no effect and only the PIO Controller can control how the pin is driven by the product. External Interrupt Lines The interrupt signals FIQ and IRQ0 to IRQn are most generally multiplexed through the PIO Controllers. However, it is not necessary to assign the I/O line to the interrupt function as the PIO Controller has no effect on inputs and the interrupt lines (FIQ or IRQs) are used only as inputs. Power Management The Power Management Controller controls the PIO Controller clock in order to save power. Writing any of the registers of the user interface does not require the PIO Controller clock to be enabled. This means that the configuration of the I/O lines does not require the PIO Controller clock to be enabled. However, when the clock is disabled, not all of the features of the PIO Controller are available. Note that the Input Change Interrupt and the read of the pin level require the clock to be validated. After a hardware reset, the PIO clock is disabled by default. The user must configure the Power Management Controller before any access to the input line information. 31.3.2 31.3.3 31.3.4 Interrupt Generation For interrupt handling, the PIO Controllers are considered as user peripherals. This means that the PIO Controller interrupt lines are connected among the interrupt sources 2 to 31. Refer to the PIO Controller peripheral identifier in the product description to identify the interrupt sources dedicated to the PIO Controllers. The PIO Controller interrupt can be generated only if the PIO Controller clock is enabled. 349 6289C–ATARM–28-May-09 31.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 31-3. In this description each signal shown represents but one of up to 32 possible indexes. Figure 31-3. I/O Line Control Logic PIO_OER[0] PIO_OSR[0] PIO_ODR[0] 1 PIO_PUER[0] PIO_PUSR[0] PIO_PUDR[0] Peripheral A Output Enable Peripheral B Output Enable PIO_ASR[0] PIO_ABSR[0] PIO_BSR[0] Peripheral A Output Peripheral B Output 0 0 0 1 PIO_PER[0] PIO_PSR[0] PIO_PDR[0] 0 0 1 PIO_MDER[0] PIO_MDSR[0] PIO_MDDR[0] 0 1 1 PIO_SODR[0] PIO_ODSR[0] PIO_CODR[0] Pad 1 Peripheral A Input Peripheral B Input PIO_PDSR[0] 0 Edge Detector Glitch Filter PIO_IFER[0] PIO_IFSR[0] PIO_IFDR[0] PIO_IER[0] 1 PIO_ISR[0] (Up to 32 possible inputs) PIO Interrupt PIO_IMR[0] PIO_IDR[0] PIO_ISR[31] PIO_IER[31] PIO_IMR[31] PIO_IDR[31] 350 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pullup Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled. Control of the pull-up resistor is possible regardless of the configuration of the I/O line. After reset, all of the pull-ups are enabled, i.e. PIO_PUSR resets at the value 0x0. 31.4.2 I/O Line or Peripheral Function Selection When a pin is multiplexed with one or two peripheral functions, the selection is controlled with the registers PIO_PER (PIO Enable Register) and PIO_PDR (PIO Disable Register). The register PIO_PSR (PIO Status Register) is the result of the set and clear registers and indicates whether the pin is controlled by the corresponding peripheral or by the PIO Controller. A value of 0 indicates that the pin is controlled by the corresponding on-chip peripheral selected in the PIO_ABSR (AB Select Status Register). A value of 1 indicates the pin is controlled by the PIO controller. If a pin is used as a general purpose I/O line (not multiplexed with an on-chip peripheral), PIO_PER and PIO_PDR have no effect and PIO_PSR returns 1 for the corresponding bit. After reset, most generally, the I/O lines are controlled by the PIO controller, i.e. PIO_PSR resets at 1. However, in some events, it is important that PIO lines are controlled by the peripheral (as in the case of memory chip select lines that must be driven inactive after reset or for address lines that must be driven low for booting out of an external memory). Thus, the reset value of PIO_PSR is defined at the product level, depending on the multiplexing of the device. 31.4.3 Peripheral A or B Selection The PIO Controller provides multiplexing of up to two peripheral functions on a single pin. The selection is performed by writing PIO_ASR (A Select Register) and PIO_BSR (Select B Register). PIO_ABSR (AB Select Status Register) indicates which peripheral line is currently selected. For each pin, the corresponding bit at level 0 means peripheral A is selected whereas the corresponding bit at level 1 indicates that peripheral B is selected. Note that multiplexing of peripheral lines A and B only affects the output line. The peripheral input lines are always connected to the pin input. After reset, PIO_ABSR is 0, thus indicating that all the PIO lines are configured on peripheral A. However, peripheral A generally does not drive the pin as the PIO Controller resets in I/O line mode. Writing in PIO_ASR and PIO_BSR manages PIO_ABSR regardless of the configuration of the pin. However, assignment of a pin to a peripheral function requires a write in the corresponding peripheral selection register (PIO_ASR or PIO_BSR) in addition to a write in PIO_PDR. 31.4.4 Output Control When the I/0 line is assigned to a peripheral function, i.e. the corresponding bit in PIO_PSR is at 0, the drive of the I/O line is controlled by the peripheral. Peripheral A or B, depending on the value in PIO_ABSR, determines whether the pin is driven or not. When the I/O line is controlled by the PIO controller, the pin can be configured to be driven. This is done by writing PIO_OER (Output Enable Register) and PIO_ODR (Output Disable Register). 351 6289C–ATARM–28-May-09 The results of these write operations are detected in PIO_OSR (Output Status Register). When a bit in this register is at 0, the corresponding I/O line is used as an input only. When the bit is at 1, the corresponding I/O line is driven by the PIO controller. The level driven on an I/O line can be determined by writing in PIO_SODR (Set Output Data Register) and PIO_CODR (Clear Output Data Register). These write operations respectively set and clear PIO_ODSR (Output Data Status Register), which represents the data driven on the I/O lines. Writing in PIO_OER and PIO_ODR manages PIO_OSR whether the pin is configured to be controlled by the PIO controller or assigned to a peripheral function. This enables configuration of the I/O line prior to setting it to be managed by the PIO Controller. Similarly, writing in PIO_SODR and PIO_CODR effects PIO_ODSR. This is important as it defines the first level driven on the I/O line. 31.4.5 Synchronous Data Output Controlling all parallel busses using several PIOs requires two successive write operations in the PIO_SODR and PIO_CODR registers. This may lead to unexpected transient values. The PIO controller offers a direct control of PIO outputs by single write access to PIO_ODSR (Output Data Status Register). Only bits unmasked by PIO_OWSR (Output Write Status Register) are written. The mask bits in the PIO_OWSR are set by writing to PIO_OWER (Output Write Enable Register) and cleared by writing to PIO_OWDR (Output Write Disable Register). After reset, the synchronous data output is disabled on all the I/O lines as PIO_OWSR resets at 0x0. 31.4.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register). The Multi Drive can be selected whether the I/O line is controlled by the PIO controller or assigned to a peripheral function. PIO_MDSR (Multi-driver Status Register) indicates the pins that are configured to support external drivers. After reset, the Multi Drive feature is disabled on all pins, i.e. PIO_MDSR resets at value 0x0. 31.4.7 Output Line Timings Figure 31-4 shows how the outputs are driven either by writing PIO_SODR or PIO_CODR, or by directly writing PIO_ODSR. This last case is valid only if the corresponding bit in PIO_OWSR is set. Figure 31-4 also shows when the feedback in PIO_PDSR is available. 352 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 31-4. Output Line Timings MCK Write PIO_SODR Write PIO_ODSR at 1 Write PIO_CODR Write PIO_ODSR at 0 APB Access APB Access PIO_ODSR 2 cycles PIO_PDSR 2 cycles 31.4.8 Inputs The level on each I/O line can be read through PIO_PDSR (Pin Data Status Register). This register indicates the level of the I/O lines regardless of their configuration, whether uniquely as an input or driven by the PIO controller or driven by a peripheral. Reading the I/O line levels requires the clock of the PIO controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 31.4.9 Input Glitch Filtering Optional input glitch filters are independently programmable on each I/O line. When the glitch filter is enabled, a glitch with a duration of less than 1/2 Master Clock (MCK) cycle is automatically rejected, while a pulse with a duration of 1 Master Clock cycle or more is accepted. For pulse durations between 1/2 Master Clock cycle and 1 Master Clock cycle the pulse may or may not be taken into account, depending on the precise timing of its occurrence. Thus for a pulse to be visible it must exceed 1 Master Clock cycle, whereas for a glitch to be reliably filtered out, its duration must not exceed 1/2 Master Clock cycle. The filter introduces one Master Clock cycle latency if the pin level change occurs before a rising edge. However, this latency does not appear if the pin level change occurs before a falling edge. This is illustrated in Figure 31-5. The glitch filters are controlled by the register set; PIO_IFER (Input Filter Enable Register), PIO_IFDR (Input Filter Disable Register) and PIO_IFSR (Input Filter Status Register). Writing PIO_IFER and PIO_IFDR respectively sets and clears bits in PIO_IFSR. This last register enables the glitch filter on the I/O lines. When the glitch filter is enabled, it does not modify the behavior of the inputs on the peripherals. It acts only on the value read in PIO_PDSR and on the input change interrupt detection. The glitch filters require that the PIO Controller clock is enabled. 353 6289C–ATARM–28-May-09 Figure 31-5. Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles PIO_PDSR if PIO_IFSR = 1 up to 2.5 cycles 1 cycle up to 2 cycles 1 cycle 1 cycle 1 cycle 31.4.10 Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line. The Input Change Interrupt is controlled by writing PIO_IER (Interrupt Enable Register) and PIO_IDR (Interrupt Disable Register), which respectively enable and disable the input change interrupt by setting and clearing the corresponding bit in PIO_IMR (Interrupt Mask Register). As Input change detection is possible only by comparing two successive samplings of the input of the I/O line, the PIO Controller clock must be enabled. The Input Change Interrupt is available, regardless of the configuration of the I/O line, i.e. configured as an input only, controlled by the PIO Controller or assigned to a peripheral function. When an input change is detected on an I/O line, the corresponding bit in PIO_ISR (Interrupt Status Register) is set. If the corresponding bit in PIO_IMR is set, the PIO Controller interrupt line is asserted. The interrupt signals of the thirty-two channels are ORed-wired together to generate a single interrupt signal to the Advanced Interrupt Controller. When the software reads PIO_ISR, all the interrupts are automatically cleared. This signifies that all the interrupts that are pending when PIO_ISR is read must be handled. Figure 31-6. Input Change Interrupt Timings MCK Pin Level PIO_ISR Read PIO_ISR APB Access APB Access 31.5 I/O Lines Programming Example The programing example as shown in Table 31-1 below is used to define the following configuration. • 4-bit output port on I/O lines 0 to 3, (should be written in a single write operation), open-drain, with pull-up resistor 354 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • Four output signals on I/O lines 4 to 7 (to drive LEDs for example), driven high and low, no pull-up resistor • Four input signals on I/O lines 8 to 11 (to read push-button states for example), with pull-up resistors, glitch filters and input change interrupts • Four input signals on I/O line 12 to 15 to read an external device status (polled, thus no input change interrupt), no pull-up resistor, no glitch filter • I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor • I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor • I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 31-1. Programming Example Register PIO_PER PIO_PDR PIO_OER PIO_ODR PIO_IFER PIO_IFDR PIO_SODR PIO_CODR PIO_IER PIO_IDR PIO_MDER PIO_MDDR PIO_PUDR PIO_PUER PIO_ASR PIO_BSR PIO_OWER PIO_OWDR Value to be Written 0x0000 FFFF 0x0FFF 0000 0x0000 00FF 0x0FFF FF00 0x0000 0F00 0x0FFF F0FF 0x0000 0000 0x0FFF FFFF 0x0F00 0F00 0x00FF F0FF 0x0000 000F 0x0FFF FFF0 0x00F0 00F0 0x0F0F FF0F 0x0F0F 0000 0x00F0 0000 0x0000 000F 0x0FFF FFF0 355 6289C–ATARM–28-May-09 31.6 Parallel Input/Output (PIO) Controller User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically. Table 31-2. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 0x006C Register Mapping Register PIO Enable Register PIO Disable Register PIO Status Register Reserved Output Enable Register Output Disable Register Output Status Register Reserved Glitch Input Filter Enable Register Glitch Input Filter Disable Register Glitch Input Filter Status Register Reserved Set Output Data Register Clear Output Data Register Output Data Status Register Pin Data Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Interrupt Status Register(4) Multi-driver Enable Register Multi-driver Disable Register Multi-driver Status Register Reserved Pull-up Disable Register Pull-up Enable Register Pad Pull-up Status Register Reserved PIO_PUDR PIO_PUER PIO_PUSR Write-only Write-only Read-only – – 0x00000000 PIO_SODR PIO_CODR PIO_ODSR PIO_PDSR PIO_IER PIO_IDR PIO_IMR PIO_ISR PIO_MDER PIO_MDDR PIO_MDSR Write-only Write-only Read-only or(2) Read/Write Read-only Write-only Write-only Read-only Read-only Write-only Write-only Read-only – (3) Name PIO_PER PIO_PDR PIO_PSR Access Write-only Write-only Read-only Reset Value – – (1) PIO_OER PIO_ODR PIO_OSR Write-only Write-only Read-only – – 0x0000 0000 PIO_IFER PIO_IFDR PIO_IFSR Write-only Write-only Read-only – – 0x0000 0000 – – – 0x00000000 0x00000000 – – 0x00000000 356 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 31-2. Offset 0x0070 0x0074 0x0078 0x007C to 0x009C 0x00A0 0x00A4 0x00A8 0x00AC Notes: Register Mapping (Continued) Register Peripheral A Select Register Peripheral B Select Register AB Status Register Reserved Output Write Enable Output Write Disable Output Write Status Register Reserved PIO_OWER PIO_OWDR PIO_OWSR Write-only Write-only Read-only – – 0x00000000 (5) (5) (5) Name PIO_ASR PIO_BSR PIO_ABSR Access Write-only Write-only Read-only Reset Value – – 0x00000000 1. Reset value of PIO_PSR depends on the product implementation. 2. PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines. 3. Reset value of PIO_PDSR depends on the level of the I/O lines. Reading the I/O line levels requires the clock of the PIO Controller to be enabled, otherwise PIO_PDSR reads the levels present on the I/O line at the time the clock was disabled. 4. PIO_ISR is reset at 0x0. However, the first read of the register may read a different value as input changes may have occurred. 5. Only this set of registers clears the status by writing 1 in the first register and sets the status by writing 1 in the second register. 357 6289C–ATARM–28-May-09 31.6.1 Name: PIO Controller PIO Enable Register PIO_PER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Enable 0 = No effect. 1 = Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 31.6.2 Name: PIO Controller PIO Disable Register PIO_PDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Disable 0 = No effect. 1 = Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin). 358 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.6.3 Name: PIO Controller PIO Status Register PIO_PSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: PIO Status 0 = PIO is inactive on the corresponding I/O line (peripheral is active). 1 = PIO is active on the corresponding I/O line (peripheral is inactive). 31.6.4 Name: PIO Controller Output Enable Register PIO_OER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Enable 0 = No effect. 1 = Enables the output on the I/O line. 359 6289C–ATARM–28-May-09 31.6.5 Name: PIO Controller Output Disable Register PIO_ODR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Disable 0 = No effect. 1 = Disables the output on the I/O line. 31.6.6 Name: PIO Controller Output Status Register PIO_OSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Status 0 = The I/O line is a pure input. 1 = The I/O line is enabled in output. 360 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.6.7 Name: PIO Controller Input Filter Enable Register PIO_IFER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Enable 0 = No effect. 1 = Enables the input glitch filter on the I/O line. 31.6.8 Name: PIO Controller Input Filter Disable Register PIO_IFDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filter Disable 0 = No effect. 1 = Disables the input glitch filter on the I/O line. 361 6289C–ATARM–28-May-09 31.6.9 Name: PIO Controller Input Filter Status Register PIO_IFSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Filer Status 0 = The input glitch filter is disabled on the I/O line. 1 = The input glitch filter is enabled on the I/O line. 31.6.10 Name: PIO Controller Set Output Data Register PIO_SODR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Sets the data to be driven on the I/O line. 362 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.6.11 Name: PIO Controller Clear Output Data Register PIO_CODR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Set Output Data 0 = No effect. 1 = Clears the data to be driven on the I/O line. 31.6.12 Name: PIO Controller Output Data Status Register PIO_ODSR Read-only or Read/Write 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The data to be driven on the I/O line is 0. 1 = The data to be driven on the I/O line is 1. 363 6289C–ATARM–28-May-09 31.6.13 Name: PIO Controller Pin Data Status Register PIO_PDSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Data Status 0 = The I/O line is at level 0. 1 = The I/O line is at level 1. 31.6.14 Name: PIO Controller Interrupt Enable Register PIO_IER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Enable 0 = No effect. 1 = Enables the Input Change Interrupt on the I/O line. 364 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.6.15 Name: PIO Controller Interrupt Disable Register PIO_IDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Disable 0 = No effect. 1 = Disables the Input Change Interrupt on the I/O line. 31.6.16 Name: PIO Controller Interrupt Mask Register PIO_IMR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Mask 0 = Input Change Interrupt is disabled on the I/O line. 1 = Input Change Interrupt is enabled on the I/O line. 365 6289C–ATARM–28-May-09 31.6.17 Name: PIO Controller Interrupt Status Register PIO_ISR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Input Change Interrupt Status 0 = No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 1 = At least one Input Change has been detected on the I/O line since PIO_ISR was last read or since reset. 31.6.18 Name: PIO Multi-driver Enable Register PIO_MDER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Enable. 0 = No effect. 1 = Enables Multi Drive on the I/O line. 366 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.6.19 Name: PIO Multi-driver Disable Register PIO_MDDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Disable. 0 = No effect. 1 = Disables Multi Drive on the I/O line. 31.6.20 Name: PIO Multi-driver Status Register PIO_MDSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Multi Drive Status. 0 = The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1 = The Multi Drive is enabled on the I/O line. The pin is driven at low level only. 367 6289C–ATARM–28-May-09 31.6.21 Name: PIO Pull Up Disable Register PIO_PUDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Disable. 0 = No effect. 1 = Disables the pull up resistor on the I/O line. 31.6.22 Name: PIO Pull Up Enable Register PIO_PUER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Enable. 0 = No effect. 1 = Enables the pull up resistor on the I/O line. 368 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.6.23 Name: PIO Pull Up Status Register PIO_PUSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Pull Up Status. 0 = Pull Up resistor is enabled on the I/O line. 1 = Pull Up resistor is disabled on the I/O line. 31.6.24 Name: PIO Peripheral A Select Register PIO_ASR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral A Select. 0 = No effect. 1 = Assigns the I/O line to the Peripheral A function. 369 6289C–ATARM–28-May-09 31.6.25 Name: PIO Peripheral B Select Register PIO_BSR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral B Select. 0 = No effect. 1 = Assigns the I/O line to the peripheral B function. 31.6.26 Name: PIO Peripheral A B Status Register PIO_ABSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Peripheral A B Status. 0 = The I/O line is assigned to the Peripheral A. 1 = The I/O line is assigned to the Peripheral B. 370 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 31.6.27 Name: PIO Output Write Enable Register PIO_OWER Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Enable. 0 = No effect. 1 = Enables writing PIO_ODSR for the I/O line. 31.6.28 Name: PIO Output Write Disable Register PIO_OWDR Write-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Disable. 0 = No effect. 1 = Disables writing PIO_ODSR for the I/O line. 371 6289C–ATARM–28-May-09 31.6.29 Name: PIO Output Write Status Register PIO_OWSR Read-only 30 29 28 27 26 25 24 Access Type: 31 P31 23 P30 22 P29 21 P28 20 P27 19 P26 18 P25 17 P24 16 P23 15 P22 14 P21 13 P20 12 P19 11 P18 10 P17 9 P16 8 P15 7 P14 6 P13 5 P12 4 P11 3 P10 2 P9 1 P8 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: Output Write Status. 0 = Writing PIO_ODSR does not affect the I/O line. 1 = Writing PIO_ODSR affects the I/O line. 372 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32. Serial Peripheral Interface (SPI) 32.1 Description The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data flow, while the other devices act as “slaves'' which have data shifted into and out by the master. Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master Protocol where one CPU is always the master while all of the others are always slaves) and one master may simultaneously shift data into multiple slaves. However, only one slave may drive its output to write data back to the master at any given time. A slave device is selected when the master asserts its NSS signal. If multiple slave devices exist, the master generates a separate slave select signal for each slave (NPCS). The SPI system consists of two data lines and two control lines: • Master Out Slave In (MOSI): This data line supplies the output data from the master shifted into the input(s) of the slave(s). • Master In Slave Out (MISO): This data line supplies the output data from a slave to the input of the master. There may be no more than one slave transmitting data during any particular transfer. • Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once for each bit that is transmitted. • Slave Select (NSS): This control line allows slaves to be turned on and off by hardware. 373 6289C–ATARM–28-May-09 32.2 Block Diagram Figure 32-1. Block Diagram PDC APB SPCK MISO MCK SPI Interface PIO MOSI NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 PMC SPI Interrupt 32.3 Application Block Diagram Figure 32-2. Application Block Diagram: Single Master/Multiple Slave Implementation SPCK MISO MOSI SPI Master NPCS0 NPCS1 NPCS2 NPCS3 NC SPCK MISO Slave 0 MOSI NSS SPCK MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 374 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.4 Signal Description Signal Description Type Pin Name MISO MOSI SPCK NPCS1-NPCS3 NPCS0/NSS Pin Description Master In Slave Out Master Out Slave In Serial Clock Peripheral Chip Selects Peripheral Chip Select/Slave Select Master Input Output Output Output Output Slave Output Input Input Unused Input Table 32-1. 32.5 32.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the SPI pins to their peripheral functions. 32.5.2 Power Management The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the SPI clock. Interrupt The SPI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the SPI interrupt requires programming the AIC before configuring the SPI. 32.5.3 375 6289C–ATARM–28-May-09 32.6 32.6.1 Functional Description Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode. The MISO line is driven by the transmitter output, the MOSI line is wired on the receiver input, the SPCK pin is driven by the transmitter to synchronize the receiver. The NPCS0 pin becomes an input, and is used as a Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other purposes. The data transfers are identically programmable for both modes of operations. The baud rate generator is activated only in Master Mode. 32.6.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is programmed with the CPOL bit in the Chip Select Register. The clock phase is programmed with the NCPHA bit. These two parameters determine the edges of the clock signal on which data is driven and sampled. Each of the two parameters has two possible states, resulting in four possible combinations that are incompatible with one another. Thus, a master/slave pair must use the same parameter pair values to communicate. If multiple slaves are used and fixed in different configurations, the master must reconfigure itself each time it needs to communicate with a different slave. Table 32-2 shows the four modes and corresponding parameter settings. Table 32-2. SPI Bus Protocol Mode SPI Mode 0 1 2 3 CPOL 0 0 1 1 NCPHA 1 0 1 0 Figure 32-3 and Figure 32-4 show examples of data transfers. 376 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 32-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) MSB 6 5 4 3 2 1 LSB * NSS (to slave) * Not defined, but normally MSB of previous character received. Figure 32-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) SPCK (CPOL = 0) 1 2 3 4 5 6 7 8 SPCK (CPOL = 1) MOSI (from master) MSB 6 5 4 3 2 1 LSB MISO (from slave) * MSB 6 5 4 3 2 1 LSB NSS (to slave) * Not defined but normally LSB of previous character transmitted. 377 6289C–ATARM–28-May-09 32.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator. It fully controls the data transfers to and from the slave(s) connected to the SPI bus. The SPI drives the chip select line to the slave and the serial clock signal (SPCK). The SPI features two holding registers, the Transmit Data Register and the Receive Data Register, and a single Shift Register. The holding registers maintain the data flow at a constant rate. After enabling the SPI, a data transfer begins when the processor writes to the SPI_TDR (Transmit Data Register). The written data is immediately transferred in the Shift Register and transfer on the SPI bus starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled and shifted in the Shift Register. Transmission cannot occur without reception. Before writing the TDR, the PCS field must be set in order to select a slave. If new data is written in SPI_TDR during the transfer, it stays in it until the current transfer is completed. Then, the received data is transferred from the Shift Register to SPI_RDR, the data in SPI_TDR is loaded in the Shift Register and a new transfer starts. The transfer of a data written in SPI_TDR in the Shift Register is indicated by the TDRE bit (Transmit Data Register Empty) in the Status Register (SPI_SR). When new data is written in SPI_TDR, this bit is cleared. The TDRE bit is used to trigger the Transmit PDC channel. The end of transfer is indicated by the TXEMPTY flag in the SPI_SR register. If a transfer delay (DLYBCT) is greater than 0 for the last transfer, TXEMPTY is set after the completion of said delay. The master clock (MCK) can be switched off at this time. The transfer of received data from the Shift Register in SPI_RDR is indicated by the RDRF bit (Receive Data Register Full) in the Status Register (SPI_SR). When the received data is read, the RDRF bit is cleared. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. Figure 32-6 on page 380 shows a block diagram of the SPI when operating in Master Mode. Figure 32-6 on page 380 shows a flow chart describing how transfers are handled. 378 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.6.3.1 Master Mode Block Diagram Figure 32-5. Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL MISO LSB SPI_RDR RD RDRF OVRES Shift Register MSB MOSI SPI_TDR TD SPI_CSR0..3 CSAAT PS SPI_MR PCS 0 SPI_TDR PCS 1 NPCS0 PCSDEC Current Peripheral SPI_RDR PCS NPCS3 NPCS2 NPCS1 TDRE MSTR NPCS0 MODFDIS MODF 379 6289C–ATARM–28-May-09 32.6.3.2 Master Mode Flow Diagram Figure 32-6. Master Mode Flow Diagram S SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0. 1 TDRE ? 0 1 CSAAT ? PS ? Variable peripheral yes 0 Fixed peripheral 0 0 PS ? Variable peripheral NPCS = SPI_MR(PCS) Fixed peripheral 1 SPI_TDR(PCS) = NPCS ? no NPCS = 0xF SPI_MR(PCS) = NPCS ? no NPCS = 0xF 1 NPCS = SPI_TDR(PCS) Delay DLYBCS Delay DLYBCS NPCS = SPI_TDR(PCS) NPCS = SPI_MR(PCS), SPI_TDR(PCS) Delay DLYBS Serializer = SPI_TDR(TD) TDRE = 1 Data Transfer SPI_RDR(RD) = Serializer RDRF = 1 Delay DLYBCT 0 TDRE ? 1 1 CSAAT ? 0 NPCS = 0xF Delay DLYBCS 380 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK) by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field of the Chip Select Registers. This allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 32.6.3.4 Transfer Delays Figure 32-7 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays can be programmed to modify the transfer waveforms: • The delay between chip selects, programmable only once for all the chip selects by writing the DLYBCS field in the Mode Register. Allows insertion of a delay between release of one chip select and before assertion of a new one. • The delay before SPCK, independently programmable for each chip select by writing the field DLYBS. Allows the start of SPCK to be delayed after the chip select has been asserted. • The delay between consecutive transfers, independently programmable for each chip select by writing the DLYBCT field. Allows insertion of a delay between two transfers occurring on the same chip select These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus release time. Figure 32-7. Programmable Delays Chip Select 1 Chip Select 2 SPCK DLYBCS DLYBS DLYBCT DLYBCT 32.6.3.5 Peripheral Selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer. The peripheral selection can be performed in two different ways: • Fixed Peripheral Select: SPI exchanges data with only one peripheral 381 6289C–ATARM–28-May-09 • Variable Peripheral Select: Data can be exchanged with more than one peripheral Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect. Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current peripheral. This means that the peripheral selection can be defined for each new data. The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the PDC is an optimal means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral selection requires the Mode Register to be reprogrammed. The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is destined to. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the processor. 32.6.3.6 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low. When operating with decoding, the SPI directly outputs the value defined by the PCS field of either the Mode Register or the Transmit Data Register (depending on PS). As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at 1) when not processing any transfer, only 15 peripherals can be decoded. The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated, each chip select defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14. 32.6.3.7 Peripheral Deselection When operating normally, as soon as the transfer of the last data written in SPI_TDR is completed, the NPCS lines all rise. This might lead to runtime error if the processor is too long in responding to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the Chip Select Register can be programmed with the CSAAT bit (Chip Select Active After Transfer) at 1. This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. 382 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 32-8 shows different peripheral deselection cases and the effect of the CSAAT bit. Figure 32-8. Peripheral Deselection CSAAT = 0 CSAAT = 1 TDRE DLYBCT A DLYBCS PCS = A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE DLYBCT A DLYBCS PCS=A A A DLYBCT A DLYBCS PCS = A A NPCS[0..3] Write SPI_TDR TDRE NPCS[0..3] DLYBCT A DLYBCS PCS = B B A DLYBCT B DLYBCS PCS = B Write SPI_TDR 32.6.3.8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the PIO controller, so that external pull up resistors are needed to guarantee high level. When a mode fault is detected, the MODF bit in the SPI_SR is set until the SPI_SR is read and the SPI is automatically disabled until re-enabled by writing the SPIEN bit in the SPI_CR (Control Register) at 1. By default, the Mode Fault detection circuitry is enabled. The user can disable Mode Fault detection by setting the MODFDIS bit in the SPI Mode Register (SPI_MR). 32.6.4 SPI Slave Mode When operating in Slave Mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK). The SPI waits for NSS to go active before receiving the serial clock from an external master. When NSS falls, the clock is validated on the serializer, which processes the number of bits 383 6289C–ATARM–28-May-09 defined by the BITS field of the Chip Select Register 0 (SPI_CSR0). These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits of the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select Registers have no effect when the SPI is programmed in Slave Mode. The bits are shifted out on the MISO line and sampled on the MOSI line. When all the bits are processed, the received data is transferred in the Receive Data Register and the RDRF bit rises. If the SPI_RDR (Receive Data Register) has not been read before new data is received, the Overrun Error bit (OVRES) in SPI_SR is set. As long as this flag is set, data is loaded in SPI_RDR. The user has to read the status register to clear the OVRES bit. When a transfer starts, the data shifted out is the data present in the Shift Register. If no data has been written in the Transmit Data Register (SPI_TDR), the last data received is transferred. If no data has been received since the last reset, all bits are transmitted low, as the Shift Register resets at 0. When a first data is written in SPI_TDR, it is transferred immediately in the Shift Register and the TDRE bit rises. If new data is written, it remains in SPI_TDR until a transfer occurs, i.e. NSS falls and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in SPI_TDR is transferred in the Shift Register and the TDRE bit rises. This enables frequent updates of critical variables with single transfers. Then, a new data is loaded in the Shift Register from the Transmit Data Register. In case no character is ready to be transmitted, i.e. no character has been written in SPI_TDR since the last load from SPI_TDR to the Shift Register, the Shift Register is not modified and the last received character is retransmitted. Figure 32-9 shows a block diagram of the SPI when operating in Slave Mode. Figure 32-9. Slave Mode Functional Block Diagram SPCK NSS SPIEN SPIENS SPIDIS SPI_CSR0 BITS NCPHA CPOL MOSI LSB SPI_RDR RD RDRF OVRES SPI Clock Shift Register MSB MISO SPI_TDR TD TDRE 384 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.7 Serial Peripheral Interface (SPI) User Interface SPI Register Mapping Register Control Register Mode Register Receive Data Register Transmit Data Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Chip Select Register 0 Chip Select Register 1 Chip Select Register 2 Chip Select Register 3 Reserved Reserved Reserved for the PDC SPI_CSR0 SPI_CSR1 SPI_CSR2 SPI_CSR3 – – Read/Write Read/Write Read/Write Read/Write – – 0x0 0x0 0x0 0x0 – – Register Name SPI_CR SPI_MR SPI_RDR SPI_TDR SPI_SR SPI_IER SPI_IDR SPI_IMR Access Write-only Read/Write Read-only Write-only Read-only Write-only Write-only Read-only Reset --0x0 0x0 --0x000000F0 ----0x0 Table 32-3. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0x2C 0x30 0x34 0x38 0x3C 0x004C - 0x00F8 0x004C - 0x00FC 0x100 - 0x124 385 6289C–ATARM–28-May-09 32.7.1 Name: SPI Control Register SPI_CR Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 LASTXFER 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SWRST – – – – – SPIDIS SPIEN • SPIEN: SPI Enable 0 = No effect. 1 = Enables the SPI to transfer and receive data. • SPIDIS: SPI Disable 0 = No effect. 1 = Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer. All pins are set in input mode and no data is received or transmitted. If a transfer is in progress, the transfer is finished before the SPI is disabled. If both SPIEN and SPIDIS are equal to one when the control register is written, the SPI is disabled. • SWRST: SPI Software Reset 0 = No effect. 1 = Reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in slave mode after software reset. PDC channels are not affected by software reset. • LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. 386 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.7.2 Name: SPI Mode Register SPI_MR Read/Write 30 29 28 27 26 25 24 Access Type: 31 DLYBCS 23 22 21 20 19 18 17 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 LLB – – MODFDIS PCSDEC PS MSTR • MSTR: Master/Slave Mode 0 = SPI is in Slave mode. 1 = SPI is in Master mode. • PS: Peripheral Select 0 = Fixed Peripheral Select. 1 = Variable Peripheral Select. • PCSDEC: Chip Select Decode 0 = The chip selects are directly connected to a peripheral device. 1 = The four chip select lines are connected to a 4- to 16-bit decoder. When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit decoder. The Chip Select Registers define the characteristics of the 15 chip selects according to the following rules: SPI_CSR0 defines peripheral chip select signals 0 to 3. SPI_CSR1 defines peripheral chip select signals 4 to 7. SPI_CSR2 defines peripheral chip select signals 8 to 11. SPI_CSR3 defines peripheral chip select signals 12 to 14. • MODFDIS: Mode Fault Detection 0 = Mode fault detection is enabled. 1 = Mode fault detection is disabled. • LLB: Local Loopback Enable 0 = Local loopback path disabled. 1 = Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in Master Mode only. (MISO is internally connected on MOSI.) • PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). 387 6289C–ATARM–28-May-09 If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-overlapping chip selects and solves bus contentions in case of peripherals having long data float times. If DLYBCS is less than or equal to six, six MCK periods will be inserted by default. Otherwise, the following equation determines the delay: D LYBCS Delay Between Chip Selects = ---------------------MCK NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 388 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.7.3 Name: SPI Receive Data Register SPI_RDR Read-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 RD 7 6 5 4 3 2 1 0 RD • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. • PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero. 389 6289C–ATARM–28-May-09 32.7.4 Name: SPI Transmit Data Register SPI_TDR Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 LASTXFER 16 – 15 – 14 – 13 – 12 11 10 PCS 9 8 TD 7 6 5 4 3 2 1 0 TD • TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format. PCS: Peripheral Chip Select This field is only used if Variable Peripheral Select is active (PS = 1). If PCSDEC = 0: PCS = xxx0 PCS = xx01 PCS = x011 PCS = 0111 PCS = 1111 (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS • LASTXFER: Last Transfer 0 = No effect. 1 = The current NPCS will be deasserted after the character written in TD has been transferred. When CSAAT is set, this allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD transfer has completed. This field is only used if Variable Peripheral Select is active (PS = 1). NPCS[3:0] = 1110 NPCS[3:0] = 1101 NPCS[3:0] = 1011 NPCS[3:0] = 0111 forbidden (no peripheral is selected) 390 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.7.5 Name: SPI Status Register SPI_SR Read-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 SPIENS 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full 0 = No data has been received since the last read of SPI_RDR 1 = Data has been received and the received data has been transferred from the serializer to SPI_RDR since the last read of SPI_RDR. • TDRE: Transmit Data Register Empty 0 = Data has been written to SPI_TDR and not yet transferred to the serializer. 1 = The last data written in the Transmit Data Register has been transferred to the serializer. TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one. • MODF: Mode Fault Error 0 = No Mode Fault has been detected since the last read of SPI_SR. 1 = A Mode Fault occurred since the last read of the SPI_SR. • OVRES: Overrun Error Status 0 = No overrun has been detected since the last read of SPI_SR. 1 = An overrun has occurred since the last read of SPI_SR. An overrun occurs when SPI_RDR is loaded at least twice from the serializer since the last read of the SPI_RDR. • ENDRX: End of RX buffer 0 = The Receive Counter Register has not reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). 1 = The Receive Counter Register has reached 0 since the last write in SPI_RCR(1) or SPI_RNCR(1). • ENDTX: End of TX buffer 0 = The Transmit Counter Register has not reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). 1 = The Transmit Counter Register has reached 0 since the last write in SPI_TCR(1) or SPI_TNCR(1). • RXBUFF: RX Buffer Full 0 = SPI_RCR(1) or SPI_RNCR(1) has a value other than 0. 1 = Both SPI_RCR(1) and SPI_RNCR(1) have a value of 0. 391 6289C–ATARM–28-May-09 • TXBUFE: TX Buffer Empty 0 = SPI_TCR(1) or SPI_TNCR(1) has a value other than 0. 1 = Both SPI_TCR(1) and SPI_TNCR(1) have a value of 0. • NSSR: NSS Rising 0 = No rising edge detected on NSS pin since last read. 1 = A rising edge occurred on NSS pin since last read. • TXEMPTY: Transmission Registers Empty 0 = As soon as data is written in SPI_TDR. 1 = SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. • SPIENS: SPI Enable Status 0 = SPI is disabled. 1 = SPI is enabled. Note: 1. SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC. 392 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.7.6 Name: SPI Interrupt Enable Register SPI_IER Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full Interrupt Enable • TDRE: SPI Transmit Data Register Empty Interrupt Enable • MODF: Mode Fault Error Interrupt Enable • OVRES: Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable • TXEMPTY: Transmission Registers Empty Enable • NSSR: NSS Rising Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 393 6289C–ATARM–28-May-09 32.7.7 Name: SPI Interrupt Disable Register SPI_IDR Write-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full Interrupt Disable • TDRE: SPI Transmit Data Register Empty Interrupt Disable • MODF: Mode Fault Error Interrupt Disable • OVRES: Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable • TXEMPTY: Transmission Registers Empty Disable • NSSR: NSS Rising Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 394 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.7.8 Name: SPI Interrupt Mask Register SPI_IMR Read-only 30 29 28 27 26 25 24 Access Type: 31 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 TXEMPTY 1 NSSR 0 TXBUFE RXBUFF ENDTX ENDRX OVRES MODF TDRE RDRF • RDRF: Receive Data Register Full Interrupt Mask • TDRE: SPI Transmit Data Register Empty Interrupt Mask • MODF: Mode Fault Error Interrupt Mask • OVRES: Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask • TXEMPTY: Transmission Registers Empty Mask • NSSR: NSS Rising Interrupt Mask 0 = The corresponding interrupt is not enabled. 1 = The corresponding interrupt is enabled. 395 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 32.7.9 Name: SPI Chip Select Register SPI_CSR0... SPI_CSR3 Read/Write 30 29 28 27 26 25 24 Access Type: 31 DLYBCT 23 22 21 20 19 18 17 16 DLYBS 15 14 13 12 11 10 9 8 SCBR 7 6 5 4 3 2 1 0 BITS CSAAT – NCPHA CPOL • CPOL: Clock Polarity 0 = The inactive state value of SPCK is logic level zero. 1 = The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices. • NCPHA: Clock Phase 0 = Data is changed on the leading edge of SPCK and captured on the following edge of SPCK. 1 = Data is captured on the leading edge of SPCK and changed on the following edge of SPCK. NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used with CPOL to produce the required clock/data relationship between master and slave devices. • CSAAT: Chip Select Active After Transfer 0 = The Peripheral Chip Select Line rises as soon as the last transfer is achieved. 1 = The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested on a different chip select. • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS 0000 0001 0010 0011 0100 0101 0110 0111 1000 Bits Per Transfer 8 9 10 11 12 13 14 15 16 396 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary BITS 1001 1010 1011 1100 1101 1110 1111 Bits Per Transfer Reserved Reserved Reserved Reserved Reserved Reserved Reserved • SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = -------------SCBR Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer. • DLYBS: Delay Before SPCK This field defines the delay from NPCS valid to the first valid SPCK transition. When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period. Otherwise, the following equations determine the delay: DLYBS Delay Before SPCK = -----------------MCK • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The delay is always inserted after each transfer and before removing the chip select if needed. When DLYBCT equals zero, no delay between consecutive transfers is inserted and the clock keeps its duty cycle over the character transfers. Otherwise, the following equation determines the delay: Delay Between Consecutive Transfers = 32 × DLYBCT -----------------------------------MCK 397 6289C–ATARM–28-May-09 398 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 33. Two-wire Interface (TWI) 33.1 Description The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as a master or a slave with sequential or single-byte access. Multiple master capability is supported. Arbitration of the bus is performed internally and puts the TWI in slave mode automatically if the bus arbitration is lost. A configurable baud rate generator permits the output data rate to be adapted to a wide range of core clock frequencies. Below, Table 33-1 lists the compatibility level of the Atmel Two-wire Interface in Master Mode and a full I2C compatible device. Table 33-1. I2C Standard Standard Mode Speed (100 KHz) Fast Mode Speed (400 KHz) 7 or 10 bits Slave Addressing START BYTE(1) Repeated Start (Sr) Condition ACK and NACK Management Slope control and input filtering (Fast mode) Clock stretching Note: 1. START + b000000001 + Ack + Sr Atmel TWI Compatibility with i2C Standard Atmel TWI Supported Supported Supported Not Supported Supported Supported Not Supported Supported 399 6289C–ATARM–28-May-09 33.2 List of Abbreviations Table 33-2. Abbreviation TWI A NA P S RS SADR ADR R W Abbreviations Description Two-wire Interface Acknowledge Non Acknowledge Stop Start Repeated Start Slave Address Any address except SADR Read Write 33.3 Block Diagram Figure 33-1. Block Diagram APB Bridge TWCK PIO Two-wire Interface TWD PMC MCK TWI Interrupt AIC 400 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.4 Application Block Diagram Figure 33-2. Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 I2C RTC Slave 2 I2C LCD Controller Slave 3 I2C Temp. Sensor Slave 4 Rp: Pull up value as given by the I2C Standard 33.4.1 I/O Lines Description I/O Lines Description Pin Description Two-wire Serial Data Two-wire Serial Clock Type Input/Output Input/Output Table 33-3. Pin Name TWD TWCK 33.5 33.5.1 Product Dependencies I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 33-2 on page 401). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines. To enable the TWI, the programmer must perform the following steps: • Program the PIO controller to: – Dedicate TWD and TWCK as peripheral lines. – Define TWD and TWCK as open-drain. 33.5.2 Power Management • Enable the peripheral clock. The TWI interface may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the TWI clock. 33.5.3 Interrupt The TWI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). In order to handle interrupts, the AIC must be programmed before configuring the TWI. 401 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.6 33.6.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 33-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 33-3). • A high-to-low transition on the TWD line while TWCK is high defines the START condition. • A low-to-high transition on the TWD line while TWCK is high defines a STOP condition. Figure 33-3. START and STOP Conditions TWD TWCK Start Stop Figure 33-4. Transfer Format TWD TWCK Start Address R/W Ack Data Ack Data Ack Stop 33.6.2 Modes of Operation The TWI has six modes of operations: • Master transmitter mode • Master receiver mode • Multi-master transmitter mode • Multi-master receiver mode • Slave transmitter mode • Slave receiver mode These modes are described in the following chapters. 402 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.7 33.7.1 Master Mode Definition The Master is the device which starts a transfer, generates a clock and stops it. 33.7.2 Application Block Diagram Figure 33-5. Master Mode Typical Application Block Diagram VDD Rp TWD TWCK Rp Host with TWI Interface Atmel TWI Serial EEPROM Slave 1 I²C RTC Slave 2 I²C LCD Controller Slave 3 I²C Temp. Sensor Slave 4 Rp: Pull up value as given by the I²C Standard 33.7.3 Programming Master Mode The following registers have to be programmed before entering Master mode: 1. DADR (+ IADRSZ + IADR if a 10 bit device is addressed): The device address is used to access slave devices in read or write mode. 2. CKDIV + CHDIV + CLDIV: Clock Waveform. 3. SVDIS: Disable the slave mode. 4. MSEN: Enable the master mode. 33.7.4 Master Transmitter Mode After the master initiates a Start condition when writing into the Transmit Holding Register, TWI_THR, it sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in TWI_MMR). The TWI transfers require the slave to acknowledge each received byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Not Acknowledge bit (NACK) in the status register if the slave does not acknowledge the byte. As with the other status bits, an interrupt can be generated if enabled in the interrupt enable register (TWI_IER). If the slave acknowledges the byte, the data written in the TWI_THR, is then shifted in the internal shifter and transferred. When an acknowledge is detected, the TXRDY bit is set until a new write in the TWI_THR. When no more data is written into the TWI_THR, the master generates a stop condition to end the transfer. The end of the complete transfer is marked by the TWI_TXCOMP bit set to one. See Figure 33-6, Figure 33-7, and Figure 33-8. 403 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 TXRDY is used as Transmit Ready for the PDC transmit channel. Figure 33-6. Master Write with One Data Byte TWD S DADR W A DATA A P TXCOMP TXRDY Write THR (DATA) STOP sent automaticaly (ACK received and TXRDY = 1) Figure 33-7. Master Write with Multiple Data Byte TWD S DADR W A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) Figure 33-8. Master Write with One Byte Internal Address and Multiple Data Bytes TWD S DADR W A IADR(7:0) A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Write THR (Data n+1) Write THR (Data n+x) STOP sent automaticaly Last data sent (ACK received and TXRDY = 1) 33.7.5 Master Receiver Mode The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction, 1 in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the NACK bit in the status register if the slave does not acknowledge the byte. If an acknowledge is received, the master is then ready to receive data from the slave. After data has been received, the master sends an acknowledge condition to notify the slave that the data has been received except for the last data, after the stop condition. See Figure 33-9. When the 404 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 RXRDY bit is set in the status register, a character has been received in the receive-holding register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR. When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits must be set at the same time. See Figure 33-9. When a multiple data byte read is performed, with or without internal address (IADR), the STOP bit must be set after the next-tolast data received. See Figure 33-10. For Internal Address usage see Section 33.7.6. Figure 33-9. Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 33-10. Master Read with Multiple Data Bytes TWD S DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel. 33.7.6 Internal Address The TWI interface can perform various transfer formats: Transfers with 7-bit slave address devices and 10-bit slave address devices. 7-bit Slave Addressing When Addressing 7-bit slave devices, the internal address bytes are used to perform random address (read or write) accesses to reach one or more data bytes, within a memory page location in a serial memory, for example. When performing read operations with an internal address, the TWI performs a write operation to set the internal address into the slave device, and then switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See Figure 33-12. See Figure 33-11 and Figure 33-13 for Master Write operation with internal address. 33.7.6.1 405 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 The three internal address bytes are configurable through the Master Mode register (TWI_MMR). If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to 0. In the figures below the following abbreviations are used: Table 33-4. •S •P •W •R •A •N • DADR • IADR Start Stop Write Read Acknowledge Not Acknowledge Device Address Internal Address Figure 33-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A DATA A P Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A DATA A P One byte internal address TWD S DADR W A IADR(7:0) A DATA A P Figure 33-12. Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address TWD S DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A S DADR R A DATA Two bytes internal address TWD S DADR W A IADR(15:8) A IADR(7:0) A S DADR R A DATA N P N P One byte internal address TWD S DADR W A IADR(7:0) A S DADR R A DATA N P 33.7.6.2 10-bit Slave Addressing For a slave address higher than 7 bits, the user must configure the address size (IADRSZ) and set the other slave address bits in the internal address register (TWI_IADR). The two remaining Internal address bytes, IADR[15:8] and IADR[23:16] can be used the same as in 7-bit Slave Addressing. 406 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Example: Address a 10-bit device (10-bit device address is b1 b2 b3 b4 b5 b6 b7 b8 b9 b10) 1. Program IADRSZ = 1, 2. Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.) 3. Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address) Figure 33-13 below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal addresses to access the device. Figure 33-13. Internal Address Usage S T A R T W R I T E S T O P Device Address 0 M S B FIRST WORD ADDRESS SECOND WORD ADDRESS DATA LRA S/C BW K M S B A C K LA SC BK A C K 407 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.7.7 Using the Peripheral DMA Controller (PDC) The use of the PDC significantly reduces the CPU load. To assure correct implementation, respect the following programming sequences: 33.7.7.1 Data Transmit with the PDC 1. Initialize the transmit PDC (memory pointers, size, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC TXTEN bit. 4. Wait for the PDC end TX flag. 5. Disable the PDC by setting the PDC TXDIS bit. 33.7.7.2 Data Receive with the PDC 1. Initialize the receive PDC (memory pointers, size - 1, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC RXTEN bit. 4. Wait for the PDC end RX flag. 5. Disable the PDC by setting the PDC RXDIS bit. 408 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.7.8 Read/Write Flowcharts The following flowcharts shown in Figure 33-14, Figure 33-15 on page 410, Figure 33-16 on page 411, Figure 33-17 on page 412, Figure 33-18 on page 413 and Figure on page 413 give examples for read and write operations. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 33-14. TWI Write Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Transfer direction bit Write ==> bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished 409 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Figure 33-15. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished 410 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Figure 33-16. TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Read Status register TWI_THR = data to send TXRDY = 1? Yes Data to send? Yes No Read Status register Yes No TXCOMP = 1? END 411 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Figure 33-17. TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? Yes Read Receive Holding Register No Read Status register No TXCOMP = 1? Yes END 412 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Figure 33-18. TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END 413 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Figure 33-19. TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) No No Last data to read but one? Yes Stop the transfer TWI_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) Read status register TXCOMP = 1? Yes END No 414 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.8 33.8.1 Multi-master Mode Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 33-21 on page 416. 33.8.2 Different Multi-master Modes Two multi-master modes may be distinguished: 1. TWI is considered as a Master only and will never be addressed. 2. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported. 33.8.2.1 TWI as Master Only In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 3320 on page 416). Note: The state of the bus (busy or free) is not indicated in the user interface. 33.8.2.2 TWI as Master or Slave The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multi-master mode described in the steps below. 1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed). 2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. 415 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR. Figure 33-20. Programmer Sends Data While the Bus is Busy TWCK STOP sent by the master TWD DATA sent by a master Bus is busy Bus is free TWI DATA transfer Transfer is kept START sent by the TWI DATA sent by the TWI A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 33-21. Arbitration Cases TWCK TWD TWCK Data from a Master Data from TWI TWD S S S 1 1 1 0 0 11 0 1 Arbitration is lost TWI stops sending data P S S 1 1 1 0 1 Arbitration is lost The master stops sending data 0 01 0 01 1 1 Data from the TWI 00 11 Data from the master P S ARBLST Bus is busy Bus is free TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Transfer is stopped Transfer is kept Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 33-22 on page 417 gives an example of read and write operations in Multi-master mode. 416 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Figure 33-22. Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? Yes GACC = 1 ? SVREAD = 0 ? EOSACC = 1 ? Yes TXCOMP = 1 ? Yes Yes TXRDY= 1 ? Yes Write in TWI_THR RXRDY= 0 ? Yes Read TWI_RHR GENERAL CALL TREATMENT Need to perform a master access ? Yes Decoding of the programming sequence Prog seq OK ? Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register Yes ARBLST = 1 ? Yes Yes RXRDY= 0 ? MREAD = 1 ? TXRDY= 0 ? Yes Read TWI_RHR Yes Data to read? Data to send ? Yes Write in TWI_THR Stop transfer Read Status Register Yes TXCOMP = 0 ? 417 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.9 33.9.1 Slave Mode Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 33.9.2 Application Block Diagram Figure 33-23. Slave Mode Typical Application Block Diagram VDD R TWD TWCK R Master Host with TWI Interface Host with TWI Interface Slave 1 Host with TWI Interface Slave 2 LCD Controller Slave 3 33.9.3 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode. 2. MSDIS (TWI_CR): Disable the master mode. 3. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account. 33.9.4 Receiving Data After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set. 33.9.4.1 Read Sequence In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. 418 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Note that a STOP or a repeated START always follows a NACK. See Figure 33-24 on page 420. 33.9.4.2 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 33-25 on page 420. 33.9.4.3 Clock Synchronization Sequence In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 33-27 on page 422 and Figure 33-28 on page 423. 33.9.4.4 General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 33-26 on page 421. 33.9.4.5 PDC As it is impossible to know the exact number of data to receive/send, the use of PDC is NOT recommended in SLAVE mode. 33.9.5 33.9.5.1 Data Transfer Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 33-24 on page 420 describes the write operation. 419 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 Figure 33-24. Read Access Ordered by a MASTER SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK ACK/NACK from the Master A DATA NA S/RS TWD TXRDY NACK SVACC SVREAD EOSVACC S ADR R NA DATA NA P/S/RS SADR R A DATA A Write THR Read RHR SVREAD has to be taken into account only while SVACC is active Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. 33.9.5.2 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR register. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 33-25 on page 420 describes the Write operation. Figure 33-25. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK SADR matches, TWI answers with an ACK Read RHR TWD RXRDY SVACC SVREAD EOSVACC Notes: S ADR W NA DATA NA P/S/RS SADR W A DATA A A DATA NA S/RS SVREAD has to be taken into account only while SVACC is active 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. 420 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.9.5.3 General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 33-26 on page 421 describes the General Call access. Figure 33-26. Master Performs a General Call 0000000 + W RESET command = 00000110X WRITE command = 00000100X TXD S GENERAL CALL A Reset or write DADD A DATA1 A DATA2 A New SADR A P New SADR Programming sequence GCACC Reset after read SVACC Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. 421 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.9.5.4 Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 33-27 on page 422 describes the clock synchronization in Read mode. 33.9.5.5 Figure 33-27. Clock Synchronization in Read Mode TWI_THR DATA0 1 DATA1 DATA2 S SADR R A DATA0 A DATA1 A XXXXXXX 2 DATA2 NA S TWCK Write THR CLOCK is tied low by the TWI as long as THR is empty SCLWS TXRDY SVACC SVREAD TXCOMP As soon as a START is detected TWI_THR is transmitted to the shift register 1 2 The data is memorized in TWI_THR until a new value is written Ack or Nack from the master The clock is stretched after the ACK, the state of TWD is undefined during clock stretching Notes: 1. TXRDY is reset when data has been written in the TWI_TH to the shift register and set when this data has been acknowledged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock synchronization mechanism is started. 422 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.9.5.6 Clock Synchronization in Write Mode The c lock is tied lo w if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 33-28 on page 423 describes the clock synchronization in Read mode. Figure 33-28. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full TWD S SADR W A DATA0 A DATA1 A DATA2 NA S ADR TWI_RHR SCLWS DATA0 is not read in the RHR DATA1 DATA2 SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 SVACC SVREAD TXCOMP As soon as a START is detected Rd DATA1 Rd DATA2 Notes: 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. 423 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.9.5.7 33.9.5.8 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 33-29 on page 424 describes the repeated start + reversal from Read to Write mode. Figure 33-29. Repeated Start + Reversal from Read to Write Mode TWI_THR DATA0 DATA1 TWD S SADR R A DATA0 A DATA1 NA RS SADR W A DATA2 A DATA3 A DATA3 P TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP As soon as a START is detected DATA2 Cleared after read 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 33.9.5.9 Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command.Figure 33-30 on page 424 describes the repeated start + reversal from Write to Read mode. Figure 33-30. Repeated Start + Reversal from Write to Read Mode TWI_THR DATA2 DATA3 TWD TWI_RHR SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP S SADR W A DATA0 A DATA1 A RS SADR R A DATA2 A DATA3 NA P DATA0 DATA1 Read TWI_RHR As soon as a START is detected Cleared after read Notes: 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. 424 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.9.6 Read Write Flowcharts The flowchart shown in Figure 33-31 on page 425 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 33-31. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? GACC = 1 ? SVREAD = 0 ? EOSACC = 1 ? TXRDY= 1 ? Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? END Read TWI_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? Change SADR 425 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10 Two-wire Interface (TWI) User Interface Table 33-5. Offset 0x00 0x04 0x08 0x0C 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 - 0xFC 0x100 - 0x124 Two-wire Interface (TWI) User Interface Register Control Register Master Mode Register Slave Mode Register Internal Address Register Clock Waveform Generator Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Receive Holding Register Transmit Holding Register Reserved Reserved for the PDC Name TWI_CR TWI_MMR TWI_SMR TWI_IADR TWI_CWGR TWI_SR TWI_IER TWI_IDR TWI_IMR TWI_RHR TWI_THR – – Access Write-only Read/Write Read/Write Read/Write Read/Write Read-only Write-only Write-only Read-only Read-only Write-only – – Reset State N/A 0x00000000 0x00000000 0x00000000 0x00000000 0x0000F009 N/A N/A 0x00000000 0x00000000 0x00000000 – – 426 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.1 Name: Access: TWI Control Register TWI_CR Write-only Reset Value: 0x00000000 31 – 23 – 15 – 7 SWRST 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 SVDIS 28 – 20 – 12 – 4 SVEN 27 – 19 – 11 – 3 MSDIS 26 – 18 – 10 – 2 MSEN 25 – 17 – 9 – 1 STOP 24 – 16 – 8 – 0 START • START: Send a START Condition 0 = No effect. 1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR). • STOP: Send a STOP Condition 0 = No effect. 1 = STOP Condition is sent just after completing the current byte transmission in master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In master read mode, if a NACK bit is received, the STOP is automatically performed. – In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. • MSEN: TWI Master Mode Enabled 0 = No effect. 1 = If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. • MSDIS: TWI Master Mode Disabled 0 = No effect. 1 = The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. • SVEN: TWI Slave Mode Enabled 0 = No effect. 427 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 1 = If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. • SVDIS: TWI Slave Mode Disabled 0 = No effect. 1 = The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • SWRST: Software Reset 0 = No effect. 1 = Equivalent to a system reset. 428 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.2 Name: Access: TWI Master Mode Register TWI_MMR Read/Write Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 29 – 21 28 – 20 27 – 19 DADR 11 – 3 – 26 – 18 25 – 17 24 – 16 14 – 6 – 13 – 5 – 12 MREAD 4 – 10 – 2 – 9 IADRSZ 1 – 8 0 – • IADRSZ: Internal Device Address Size IADRSZ[9:8] 0 0 1 1 0 1 0 1 No internal device address One-byte internal device address Two-byte internal device address Three-byte internal device address • MREAD: Master Read Direction 0 = Master write direction. 1 = Master read direction. • DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode. 429 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.3 Name: Access: TWI Slave Mode Register TWI_SMR Read/Write Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 29 – 21 28 – 20 27 – 19 SADR 11 – 3 – 26 – 18 25 – 17 24 – 16 14 – 6 – 13 – 5 – 12 – 4 – 10 – 2 – 9 8 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. 430 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.4 Name: Access: TWI Internal Address Register TWI_IADR Read/Write Reset Value: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 IADR 15 14 13 12 IADR 7 6 5 4 IADR 3 2 1 0 11 10 9 8 27 – 19 26 – 18 25 – 17 24 – 16 • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. 431 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.5 Name: Access: TWI Clock Waveform Generator Register TWI_CWGR Read/Write Reset Value: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 20 27 – 19 26 – 18 25 – 17 CKDIV 9 24 – 16 15 14 13 12 CHDIV 11 10 8 7 6 5 4 CLDIV 3 2 1 0 TWI_CWGR is only used in Master mode. • CLDIV: Clock Low Divider The SCL low period is defined as follows: T low = ( ( CLDIV × 2 CKDIV ) + 4 ) × T MCK • CHDIV: Clock High Divider The SCL high period is defined as follows: T high = ( ( CHDIV × 2 CKDIV ) + 4 ) × T MCK • CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. 432 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.6 Name: Access: TWI Status Register TWI_SR Read-only Reset Value: 0x0000F009 31 – 23 – 15 TXBUFE 7 – 30 – 22 – 14 RXBUFF 6 OVRE 29 – 21 – 13 ENDTX 5 GACC 28 – 20 – 12 ENDRX 4 SVACC 27 – 19 – 11 EOSACC 3 SVREAD 26 – 18 – 10 SCLWS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0 = During the length of the current frame. 1 = When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 33-8 on page 404 and in Figure 33-10 on page 405. TXCOMP used in Slave mode: 0 = As soon as a Start is detected. 1 = After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 33-27 on page 422, Figure 33-28 on page 423, Figure 33-29 on page 424 and Figure 33-30 on page 424. • RXRDY: Receive Holding Register Ready (automatically set / reset) 0 = No character has been received since the last TWI_RHR read operation. 1 = A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 33-10 on page 405. RXRDY behavior in Slave mode can be seen in Figure 33-25 on page 420, Figure 33-28 on page 423, Figure 33-29 on page 424 and Figure 33-30 on page 424. • TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode: 0 = The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR register. 1 = As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 33-8 on page 404. 433 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 TXRDY used in Slave mode: 0 = As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1 = It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 33-24 on page 420, Figure 33-27 on page 422, Figure 33-29 on page 424 and Figure 33-30 on page 424. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0 = Indicates that a write access is performed by a Master. 1 = Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 33-24 on page 420, Figure 33-25 on page 420, Figure 33-29 on page 424 and Figure 33-30 on page 424. • SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0 = TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1 = Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 33-24 on page 420, Figure 33-25 on page 420, Figure 33-29 on page 424 and Figure 33-30 on page 424. • GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0 = No General Call has been detected. 1 = A General Call has been detected. After the detection of General Call, the programmer decoded the commands that follow and the programming sequence. GACC behavior can be seen in Figure 33-26 on page 421. • OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0 = TWI_RHR has not been loaded while RXRDY was set 1 = TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. • NACK: Not Acknowledged (clear on read) NACK used in Master mode: 0 = Each data byte has been correctly received by the far-end side TWI slave component. 1 = A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. 434 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 NACK used in Slave Read mode: 0 = Each data byte has been correctly received by the Master. 1 = In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0 = The clock is not stretched. 1 = The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 33-27 on page 422 and Figure 33-28 on page 423. • EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0 = A slave access is being performing. 1 = The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 33-29 on page 424 and Figure 33-30 on page 424 • ENDRX: End of RX buffer This bit is only used in Master mode. 0 = The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TWI_RCR or TWI_RNCR. • ENDTX: End of TX buffer This bit is only used in Master mode. 0 = The Transmit Counter Register has not reached 0 since the last write in TWI_TCR or TWI_TNCR. 1 = The Transmit Counter Register has reached 0 since the last write in TWI_TCR or TWI_TNCR. • RXBUFF: RX Buffer Full This bit is only used in Master mode. 0 = TWI_RCR or TWI_RNCR have a value other than 0. 1 = Both TWI_RCR and TWI_RNCR have a value of 0. 435 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 • TXBUFE: TX Buffer Empty This bit is only used in Master mode. 0 = TWI_TCR or TWI_TNCR have a value other than 0. 1 = Both TWI_TCR and TWI_TNCR have a value of 0. 436 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.7 Name: Access: TWI Interrupt Enable Register TWI_IER Write-only Reset Value: 0x00000000 31 – 23 – 15 TXBUFE 7 – 30 – 22 – 14 RXBUFF 6 OVRE 29 – 21 – 13 ENDTX 5 GACC 28 – 20 – 12 ENDRX 4 SVACC 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP • TXCOMP: Transmission Completed Interrupt Enable • RXRDY: Receive Holding Register Ready Interrupt Enable • TXRDY: Transmit Holding Register Ready Interrupt Enable • SVACC: Slave Access Interrupt Enable • GACC: General Call Access Interrupt Enable • OVRE: Overrun Error Interrupt Enable • NACK: Not Acknowledge Interrupt Enable • ABRLST: Arbitration Lost Interrupt Enable • SCL_WS: Clock Wait State Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • ENDTX: End of Transmit Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • TXBUFE: Transmit Buffer Empty Interrupt Enable 0 = No effect. 1 = Enables the corresponding interrupt. 437 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.8 Name: Access: TWI Interrupt Disable Register TWI_IDR Write-only Reset Value: 0x00000000 31 – 23 – 15 TXBUFE 7 – 30 – 22 – 14 RXBUFF 6 OVRE 29 – 21 – 13 ENDTX 5 GACC 28 – 20 – 12 ENDRX 4 SVACC 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP • TXCOMP: Transmission Completed Interrupt Disable • RXRDY: Receive Holding Register Ready Interrupt Disable • TXRDY: Transmit Holding Register Ready Interrupt Disable • SVACC: Slave Access Interrupt Disable • GACC: General Call Access Interrupt Disable • OVRE: Overrun Error Interrupt Disable • NACK: Not Acknowledge Interrupt Disable • ABRLST: Arbitration Lost Interrupt Disable • SCL_WS: Clock Wait State Interrupt Disable • EOSACC: End Of Slave Access Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • ENDTX: End of Transmit Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • TXBUFE: Transmit Buffer Empty Interrupt Disable 0 = No effect. 1 = Disables the corresponding interrupt. 438 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.9 Name: Access: TWI Interrupt Mask Register TWI_IMR Read-only Reset Value: 0x00000000 31 – 23 – 15 TXBUFE 7 – 30 – 22 – 14 RXBUFF 6 OVRE 29 – 21 – 13 ENDTX 5 GACC 28 – 20 – 12 ENDRX 4 SVACC 27 – 19 – 11 EOSACC 3 – 26 – 18 – 10 SCL_WS 2 TXRDY 25 – 17 – 9 ARBLST 1 RXRDY 24 – 16 – 8 NACK 0 TXCOMP • TXCOMP: Transmission Completed Interrupt Mask • RXRDY: Receive Holding Register Ready Interrupt Mask • TXRDY: Transmit Holding Register Ready Interrupt Mask • SVACC: Slave Access Interrupt Mask • GACC: General Call Access Interrupt Mask • OVRE: Overrun Error Interrupt Mask • NACK: Not Acknowledge Interrupt Mask • ABRLST: Arbitration Lost Interrupt Mask • SCL_WS: Clock Wait State Interrupt Mask • EOSACC: End Of Slave Access Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • ENDTX: End of Transmit Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • TXBUFE: Transmit Buffer Empty Interrupt Mask 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 439 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 33.10.10 TWI Receive Holding Register Name: TWI_RHR Access: Read-only Reset Value: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • RXDATA: Master or Slave Receive Holding Data 33.10.11 TWI Transmit Holding Register Name: TWI_THR Access: Read/Write Reset Value: 0x00000000 31 – 23 – 15 – 7 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXDATA 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 • TXDATA: Master or Slave Transmit Holding Data 440 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34. Universal Synchronous/Asynchronous Receiver/Transceiver (USART) 34.1 Description The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 441 6289C–ATARM–28-May-09 34.2 Block Diagram Figure 34-1. USART Block Diagram Peripheral DMA Controller Channel Channel USART PIO Controller RXD Receiver RTS AIC USART Interrupt TXD Transmitter CTS DTR PMC MCK MCK/DIV Modem Signals Control DSR DCD RI SLCK Baud Rate Generator SCK DIV User Interface APB 442 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.3 Application Block Diagram Figure 34-2. Application Block Diagram PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrLAP IrDA Driver USART RS232 Drivers Modem PSTN RS232 Drivers RS485 Drivers Smart Card Slot IrDA Transceivers Serial Port Differential Bus 34.4 I/O Lines Description I/O Line Description Description Serial Clock Transmit Serial Data Receive Serial Data Ring Indicator Data Set Ready Data Carrier Detect Data Terminal Ready Clear to Send Request to Send Type I/O I/O Input Input Input Input Output Input Output Low Low Low Low Low Low Active Level Table 34-1. Name SCK TXD RXD RI DSR DCD DTR CTS RTS 443 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.5 34.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled. All the pins of the modems may or may not be implemented on the USART. Only USART0 is fully equipped with all the modem signals. On USARTs not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART. 34.5.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. 34.5.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. 444 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication – MSB- or LSB-first – 1, 1.5 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling receiver frequency – Optional hardware handshaking – Optional modem signals management – Optional break management – Optional multidrop serial communication • High-speed 5- to 9-bit full-duplex synchronous serial communication – MSB- or LSB-first – 1 or 2 stop bits – Parity even, odd, marked, space or none – By 8 or by 16 over-sampling frequency – Optional hardware handshaking – Optional modem signals management – Optional break management – Optional multidrop serial communication • RS485 with driver control signal • ISO7816, T0 or T1 protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit • InfraRed IrDA Modulation and Demodulation • Test modes – Remote loopback, local loopback, automatic echo 34.6.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between: • the Master Clock MCK • a division of the Master Clock, the divider being product dependent, but generally set to 8 • the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. 445 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 34-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD 0 1 2 3 0 16-bit Counter >1 1 0 1 1 SYNC USCLKS = 3 Sampling Clock 0 OVER Sampling Divider 0 Baud Rate Clock FIDI SYNC SCK 34.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the Baud Rate. SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over ) CD ) This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. Baud Rate Calculation Example Table 34-2 shows calculations of CD to obtain a baud rate at 38400 bauds for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 34-2. Baud Rate Example (OVER = 0) Expected Baud Rate Bit/s 38 400 38 400 38 400 38 400 6.00 8.00 8.14 12.00 6 8 8 12 Calculation Result CD Actual Baud Rate Bit/s 38 400.00 38 400.00 39 062.50 38 400.00 0.00% 0.00% 1.70% 0.00% Error Source Clock MHz 3 686 400 4 915 200 5 000 000 7 372 800 446 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 34-2. Baud Rate Example (OVER = 0) (Continued) Expected Baud Rate 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 38 400 Calculation Result 13.02 19.53 20.00 23.30 24.00 30.00 39.06 40.00 40.69 52.08 53.33 53.71 65.10 81.38 CD 13 20 20 23 24 30 39 40 40 52 53 54 65 81 Actual Baud Rate 38 461.54 37 500.00 38 400.00 38 908.10 38 400.00 38 400.00 38 461.54 38 400.00 38 109.76 38 461.54 38 641.51 38 194.44 38 461.54 38 580.25 Error 0.16% 2.40% 0.00% 1.31% 0.00% 0.00% 0.16% 0.00% 0.76% 0.16% 0.63% 0.54% 0.16% 0.47% Source Clock 8 000 000 12 000 000 12 288 000 14 318 180 14 745 600 18 432 000 24 000 000 24 576 000 25 000 000 32 000 000 32 768 000 33 000 000 40 000 000 50 000 000 The baud rate is calculated with the following formula: BaudRate = MCK ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 – ⎛ --------------------------------------------------⎞ ⎝ ActualBaudRate ⎠ 34.6.1.2 Fractional Baud Rate in Asynchronous Mode The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula: SelectedClock Baudrate = ---------------------------------------------------------------⎛ 8 ( 2 – Over ) ⎛ CD + FP⎞ ⎞ -----⎝ ⎝ 8 ⎠⎠ The modified architecture is presented below: 447 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-4. Fractional Baud Rate Generator FP USCLKS MCK MCK/DIV SCK Reserved CD Modulus Control FP CD SCK FIDI 0 OVER Sampling Divider 1 1 SYNC USCLKS = 3 Sampling Clock 0 Baud Rate Clock SYNC 0 1 2 3 16-bit Counter glitch-free logic >1 1 0 0 34.6.1.3 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. BaudRate = SelectedClock ------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. 34.6.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ----- × f Fi where: • B is the bit rate • Di is the bit-rate adjustment factor • Fi is the clock frequency division factor • f is the ISO7816 clock frequency (Hz) 448 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 34-3. Table 34-3. DI field Di (decimal) Binary and Decimal Values for Di 0001 1 0010 2 0011 4 0100 8 0101 16 0110 32 1000 12 1001 20 Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 34-4. Table 34-4. FI field Fi (decimal Binary and Decimal Values for Fi 0000 372 0001 372 0010 558 0011 744 0100 1116 0101 1488 0110 1860 1001 512 1010 768 1011 1024 1100 1536 1101 2048 Table 34-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 34-5. Fi/Di 1 2 4 8 16 32 12 20 Possible Values for the Fi/Di Ratio 372 372 186 93 46.5 23.25 11.62 31 18.6 558 558 279 139.5 69.75 34.87 17.43 46.5 27.9 774 744 372 186 93 46.5 23.25 62 37.2 1116 1116 558 279 139.5 69.75 34.87 93 55.8 1488 1488 744 372 186 93 46.5 124 74.4 1806 1860 930 465 232.5 116.2 58.13 155 93 512 512 256 128 64 32 16 42.66 25.6 768 768 384 192 96 48 24 64 38.4 1024 1024 512 256 128 64 32 85.33 51.2 1536 1536 768 384 192 96 48 128 76.8 2048 2048 1024 512 256 128 64 170.6 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). Figure 34-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. 449 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 34.6.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally. 34.6.3 34.6.3.1 Synchronous and Asynchronous Modes Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. 450 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY raises. Both TXRDY and TXEMPTY bits are low since the transmitter is disabled. Writing a character in US_THR while TXRDY is active has no effect and the written character is lost. Figure 34-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY 34.6.3.2 Manchester Encoder When the Manchester encoder is in use, characters transmitted through the USART are encoded based on biphase Manchester II format. To enable this mode, set the MAN field in the US_MR register to 1. Depending on polarity configuration, a logic level (zero or one), is transmitted as a coded signal one-to-zero or zero-to-one. Thus, a transition always occurs at the midpoint of each bit time. It consumes more bandwidth than the original NRZ signal (2x) but the receiver has more error control since the expected input must show a change at the center of a bit cell. An example of Manchester encoded sequence is: the byte 0xB1 or 10110001 encodes to 10 01 10 10 01 01 01 10, assuming the default polarity of the encoder. Figure 34-8 illustrates this coding scheme. 451 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-8. NRZ to Manchester Encoding NRZ encoded data Manchester encoded data 1 0 1 1 0 0 0 1 Txd The Manchester encoded character can also be encapsulated by adding both a configurable preamble and a start frame delimiter pattern. Depending on the configuration, the preamble is a training sequence, composed of a pre-defined pattern with a programmable length from 1 to 15 bit times. If the preamble length is set to 0, the preamble waveform is not generated prior to any character. The preamble pattern is chosen among the following sequences: ALL_ONE, ALL_ZERO, ONE_ZERO or ZERO_ONE, writing the field TX_PP in the US_MAN register, the field TX_PL is used to configure the preamble length. Figure 34-9 illustrates and defines the valid patterns. To improve flexibility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition. Figure 34-9. Preamble Patterns, Default Polarity Assumed Manchester encoded data Txd SFD DATA 8 bit width "ALL_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ALL_ZERO" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ZERO_ONE" Preamble Manchester encoded data Txd SFD DATA 8 bit width "ONE_ZERO" Preamble A start frame delimiter is to be configured using the ONEBIT field in the US_MR register. It consists of a user-defined pattern that indicates the beginning of a valid data. Figure 34-10 illustrates these patterns. If the start frame delimiter, also known as start bit, is one bit, (ONEBIT at 1), a logic zero is Manchester encoded and indicates that a new character is being sent serially on the line. If the start frame delimiter is a synchronization pattern also referred to as sync (ONEBIT at 0), a sequence of 3 bit times is sent serially on the line to indicate the start of a new character. The sync waveform is in itself an invalid Manchester waveform as the transition 452 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary occurs at the middle of the second bit time. Two distinct sync patterns are used: the command sync and the data sync. The command sync has a logic one level for one and a half bit times, then a transition to logic zero for the second one and a half bit times. If the MODSYNC field in the US_MR register is set to 1, the next character is a command. If it is set to 0, the next character is a data. When direct memory access is used, the MODSYNC field can be immediately updated with a modified character located in memory. To enable this mode, VAR_SYNC field in US_MR register must be set to 1. In this case, the MODSYNC field in US_MR is bypassed and the sync configuration is held in the TXSYNH in the US_THR register. The USART character format is modified and includes sync information. Figure 34-10. Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data Txd DATA One bit start frame delimiter SFD Manchester encoded data Txd DATA SFD Manchester encoded data Txd Command Sync start frame delimiter DATA Data Sync start frame delimiter Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift. To enable the hardware system, the bit in the USART_MAN register must be set. If the RXD edge is one 16X clock cycle from the expected edge, this is considered as normal jitter and no corrective actions is taken. If the RXD event is between 4 and 2 clock cycles before the expected edge, then the current period is shortened by one clock cycle. If the RXD event is between 2 and 3 clock cycles after the expected edge, then the current period is lengthened by one clock cycle. These intervals are considered to be drift and so corrective actions are automatically taken. 453 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-11. Bit Resynchronization Oversampling 16x Clock RXD Sampling point Expected edge Synchro. Error Synchro. Jump Tolerance Sync Jump Synchro. Error 34.6.3.3 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 34-12 and Figure 34-13 illustrate start detection and character reception when USART operates in asynchronous mode. 454 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-12. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 2 3 4 5 6 01 Start Rejection 7 2 3 4 Figure 34-13. Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 34.6.3.4 Manchester Decoder When the MAN field in US_MR register is set to 1, the Manchester decoder is enabled. The decoder performs both preamble and start frame delimiter detection. One input line is dedicated to Manchester encoded input data. An optional preamble sequence can be defined, its length is user-defined and totally independent of the emitter side. Use RX_PL in US_MAN register to configure the length of the preamble sequence. If the length is set to 0, no preamble is detected and the function is disabled. In addition, the polarity of the input stream is programmable with RX_MPOL field in US_MAN register. Depending on the desired application the preamble pattern matching is to be defined via the RX_PP field in US_MAN. See Figure 34-9 for available preamble patterns. Unlike preamble, the start frame delimiter is shared between Manchester Encoder and Decoder. So, if ONEBIT field is set to 1, only a zero encoded Manchester can be detected as a valid start frame delimiter. If ONEBIT is set to 0, only a sync pattern is detected as a valid start frame delimiter. Decoder operates by detecting transition on incoming stream. If RXD is sampled during one quarter of a bit time at zero, a start bit is detected. See Figure 34-14.. The sample pulse rejection mechanism applies. 455 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-14. Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization. If the stream does not match a valid pattern or a valid start frame delimiter, the receiver re-synchronizes on the next valid edge.The minimum time threshold to estimate the bit value is three quarters of a bit time. If a valid preamble (if used) followed with a valid start frame delimiter is detected, the incoming stream is decoded into NRZ data and passed to USART for processing. Figure 34-15 illustrates Manchester pattern mismatch. When incoming data stream is passed to the USART, the receiver is also able to detect Manchester code violation. A code violation is a lack of transition in the middle of a bit cell. In this case, MANE flag in US_CSR register is raised. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. See Figure 34-16 for an example of Manchester error detection during data phase. Figure 34-15. Preamble Pattern Mismatch Preamble Mismatch Manchester coding error Preamble Mismatch invalid pattern Manchester encoded data Txd SFD DATA Preamble Length is set to 8 Figure 34-16. Manchester Error Flag Preamble Length is set to 4 Elementary character bit time SFD Manchester encoded data Txd Entering USART character area sampling points Preamble subpacket and Start Frame Delimiter were successfully decoded Manchester Coding Error detected When the start frame delimiter is a sync pattern (ONEBIT field at 0), both command and data delimiter are supported. If a valid sync is detected, the received character is written as RXCHR 456 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary field in the US_RHR register and the RXSYNH is updated. RXCHR is set to 1 when the received character is a command, and it is set to 0 if the received character is a data. This mechanism alleviates and simplifies the direct memory access as the character contains its own sync field in the same register. As the decoder is setup to be used in unipolar mode, the first bit of the frame has to be a zero-toone transition. 34.6.3.5 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 34-17. Figure 34-17. Manchester Encoded Characters RF Transmission Fup frequency Carrier ASK/FSK Upstream Receiver Upstream Emitter LNA VCO RF filter Demod Serial Configuration Interface control Fdown frequency Carrier bi-dir line ASK/FSK downstream transmitter Manchester decoder USART Receiver Downstream Receiver Manchester encoder PA RF filter Mod VCO USART Emitter control The USART module is configured as a Manchester encoder/decoder. Looking at the downstream communication channel, Manchester encoded characters are serially sent to the RF emitter. This may also include a user defined preamble and a start frame delimiter. Mostly, preamble is used in the RF receiver to distinguish between a valid data from a transmitter and signals due to noise. The Manchester stream is then modulated. See Figure 34-18 for an example of ASK modulation scheme. When a logic one is sent to the ASK modulator, the power amplifier, referred to as PA, is enabled and transmits an RF signal at downstream frequency. When a logic zero is transmitted, the RF signal is turned off. If the FSK modulator is activated, two different frequencies are used to transmit data. When a logic 1 is sent, the modulator outputs an RF signal at frequency F0 and switches to F1 if the data sent is a 0. See Figure 34-19. From the receiver side, another carrier frequency is used. The RF receiver performs a bit check operation examining demodulated data stream. If a valid pattern is detected, the receiver 457 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary switches to receiving mode. The demodulated stream is sent to the Manchester decoder. Because of bit checking inside RF IC, the data transferred to the microcontroller is reduced by a user-defined number of bits. The Manchester preamble length is to be defined in accordance with the RF IC configuration. Figure 34-18. ASK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output ASK Modulator Output Uptstream Frequency F0 0 0 1 Txd Figure 34-19. FSK Modulator Output 1 NRZ stream Manchester encoded data default polarity unipolar output FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 0 0 1 Txd 34.6.3.6 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 34-20 illustrates a character reception in synchronous mode. Figure 34-20. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit 458 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.6.3.7 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 34-21. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 459 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.6.3.8 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 461. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 34-6 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 34-6. Character A A A A A Parity Bit Examples Hexa 0x41 0x41 0x41 0x41 0x41 Binary 0100 0001 0100 0001 0100 0001 0100 0001 0100 0001 Parity Bit 1 0 1 0 None Parity Mode Odd Even Mark Space None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 34-22 illustrates the parity bit status setting and clearing. 460 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-22. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 34.6.3.9 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. 34.6.3.10 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 34-23, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. 461 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-23. Timeguard Operations TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit TG = 4 Write US_THR TXRDY TXEMPTY Table 34-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the Baud Rate. Table 34-7. Maximum Timeguard Length Depending on Baud Rate Bit time µs 833 104 69.4 52.1 34.7 29.9 17.9 17.4 8.7 Timeguard ms 212.50 26.56 17.71 13.28 8.85 7.63 4.55 4.43 2.21 Baud Rate Bit/sec 1 200 9 600 14400 19200 28800 33400 56000 57600 115200 34.6.3.11 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either: • Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state 462 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received. • Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 34-24 shows the block diagram of the Receiver Time-out feature. Figure 34-24. Receiver Time-out Block Diagram Baud Rate Clock TO 1 STTTO D Q Clock 16-bit Time-out Counter Load 16-bit Value = TIMEOUT Character Received RETTO Clear 0 Table 34-8 gives the maximum time-out period for some standard baud rates. Table 34-8. Maximum Time-out Period Bit Time µs 1 667 833 417 208 104 69 52 35 30 Time-out ms 109 225 54 613 27 306 13 653 6 827 4 551 3 413 2 276 1 962 Baud Rate bit/sec 600 1 200 2 400 4 800 9 600 14400 19200 28800 33400 463 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 34-8. Maximum Time-out Period (Continued) Bit Time 18 17 5 Time-out 1 170 1 138 328 Baud Rate 56000 57600 200000 34.6.3.12 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 34-25. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 34.6.3.13 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. 464 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. Figure 34-26 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 34-26. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STPBRK = 1 End of Break STTBRK = 1 Write US_CR TXRDY TXEMPTY 34.6.3.14 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 34.6.3.15 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 34-27. 465 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-27. Connection with a Remote Device for Hardware Handshaking USART TXD RXD CTS RTS Remote Device RXD TXD RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. Figure 34-28 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 34-28. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 Write US_CR RTS RXBUFF RXDIS = 1 Figure 34-29 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 34-29. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 466 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 34.6.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 445). The USART connects to a smart card as shown in Figure 34-30. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 34-30. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 479 and “PAR: Parity Type” on page 480. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 34.6.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 34-31. 467 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 34-32. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 34-31. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 34-32. T = 0 Protocol with Parity Error Baud Rate Clock I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Error Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. 468 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. 34.6.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 34-33. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to 115.2 Kb/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 34-33. Connection to IrDA Transceivers 34.6.5 USART Receiver Demodulator RXD RX TX Transmitter Modulator TXD IrDA Transceivers The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. 469 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.6.5.1 IrDA Modulation For baud rates up to and including 115.2 Kbits/sec, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 34-9. Table 34-9. Baud Rate 2.4 Kb/s 9.6 Kb/s 19.2 Kb/s 38.4 Kb/s 57.6 Kb/s 115.2 Kb/s IrDA Pulse Duration Pulse Duration (3/16) 78.13 µs 19.53 µs 9.77 µs 4.88 µs 3.26 µs 1.63 µs Figure 34-34 shows an example of character transmission. Figure 34-34. IrDA Modulation Start Bit Transmitter Output 0 1 0 1 Data Bits 0 0 1 1 0 Stop Bit 1 TXD Bit Period 3 16 Bit Period 34.6.5.2 IrDA Baud Rate Table 34-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 34-10. IrDA Baud Rate Error Peripheral Clock 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 Baud Rate 115 200 115 200 115 200 115 200 57 600 57 600 57 600 57 600 38 400 38 400 CD 2 11 18 22 4 22 36 43 6 33 Baud Rate Error 0.00% 1.38% 1.25% 1.38% 0.00% 1.38% 1.25% 0.93% 0.00% 1.38% Pulse Time 1.63 1.63 1.63 1.63 3.26 3.26 3.26 3.26 4.88 4.88 470 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 34-10. IrDA Baud Rate Error (Continued) Peripheral Clock 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 40 000 000 3 686 400 20 000 000 32 768 000 Baud Rate 38 400 38 400 19 200 19 200 19 200 19 200 9 600 9 600 9 600 9 600 2 400 2 400 2 400 CD 53 65 12 65 107 130 24 130 213 260 96 521 853 Baud Rate Error 0.63% 0.16% 0.00% 0.16% 0.31% 0.16% 0.00% 0.16% 0.16% 0.16% 0.00% 0.03% 0.04% Pulse Time 4.88 4.88 9.77 9.77 9.77 9.77 19.53 19.53 19.53 19.53 78.13 78.13 78.13 34.6.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 34-35 illustrates the operations of the IrDA demodulator. Figure 34-35. IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 43 Pulse Rejected 5 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 471 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 34-36. Figure 34-36. Typical Connection to a RS485 Bus USART RXD TXD RTS Differential Bus The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 34-37 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 34-37. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 472 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 34-11 gives the correspondence of the USART signals with modem connection standards. Table 34-11. Circuit References USART Pin TXD RTS DTR RXD CTS DSR DCD RI V24 2 4 20 3 5 6 8 22 CCITT 103 105 108.2 104 106 107 109 125 Direction From terminal to modem From terminal to modem From terminal to modem From modem to terminal From terminal to modem From terminal to modem From terminal to modem From terminal to modem The control of the DTR output pin is performed by writing the Control Register (US_CR) with the DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. 34.6.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 34.6.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. 473 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-38. Normal Mode Configuration RXD Receiver TXD Transmitter 34.6.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 34-39. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 34-39. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 34.6.8.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 34-40. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 34-40. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD 34.6.8.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 34-41. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. 474 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 34-41. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 475 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7 USART User Interface USART Memory Map Register Control Register Mode Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Status Register Receiver Holding Register Transmitter Holding Register Baud Rate Generator Register Receiver Time-out Register Transmitter Timeguard Register Reserved FI DI Ratio Register Number of Errors Register Reserved IrDA Filter Register Manchester Encoder Decoder Register Reserved Reserved for PDC Registers Name US_CR US_MR US_IER US_IDR US_IMR US_CSR US_RHR US_THR US_BRGR US_RTOR US_TTGR – US_FIDI US_NER – US_IF US_MAN – – Access Write-only Read/Write Write-only Write-only Read-only Read-only Read-only Write-only Read/Write Read/Write Read/Write – Read/Write Read-only – Read/Write Read/Write – – Reset State – – – – 0x0 – 0x0 – 0x0 0x0 0x0 – 0x174 – – 0x0 0x30011004 – – Table 34-12. Offset 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x2C - 0x3C 0x0040 0x0044 0x0048 0x004C 0x0050 0x5C - 0xFC 0x100 - 0x128 476 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.1 Name: USART Control Register US_CR Write-only 30 – 22 – 14 RSTNACK 6 TXEN 29 – 21 – 13 RSTIT 5 RXDIS 28 – 20 – 12 SENDA 4 RXEN 27 – 19 RTSDIS 11 STTTO 3 RSTTX 26 – 18 RTSEN 10 STPBRK 2 RSTRX 25 – 17 DTRDIS 9 STTBRK 1 – 24 – 16 DTREN 8 RSTSTA 0 – Access Type: 31 – 23 – 15 RETTO 7 TXDIS • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE, MANERR and RXBRK in US_CSR. • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. 477 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. • RETTO: Rearm Time-out 0: No effect 1: Restart Time-out • DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. • DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. • RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. 478 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.2 Name: USART Mode Register US_MR Read/Write 30 MODSYNC– 22 VAR_SYNC 14 CHMODE 7 CHRL 6 5 USCLKS 29 MAN 21 DSNACK 13 NBSTOP 4 3 28 FILTER 20 INACK 12 27 – 19 OVER 11 26 25 MAX_ITERATION 17 MODE9 9 24 Access Type: 31 ONEBIT 23 – 15 18 CLKO 10 PAR 2 16 MSBF 8 SYNC 0 1 USART_MODE • USART_MODE USART_MODE 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 1 1 0 0 1 1 0 x 0 1 0 1 0 1 0 1 0 x Mode of the USART Normal RS485 Hardware Handshaking Modem IS07816 Protocol: T = 0 Reserved IS07816 Protocol: T = 1 Reserved IrDA Reserved • USCLKS: Clock Selection USCLKS 0 0 1 1 0 1 0 1 Selected Clock MCK MCK/DIV (DIV = 8) Reserved SCK • CHRL: Character Length. CHRL 0 0 Character Length 5 bits 479 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 0 1 1 1 0 1 6 bits 7 bits 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. • PAR: Parity Type PAR 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 x x Parity Type Even parity Odd parity Parity forced to 0 (Space) Parity forced to 1 (Mark) No parity Multidrop mode • NBSTOP: Number of Stop Bits NBSTOP 0 0 1 1 0 1 0 1 Asynchronous (SYNC = 0) 1 stop bit 1.5 stop bits 2 stop bits Reserved Synchronous (SYNC = 1) 1 stop bit Reserved 2 stop bits Reserved • CHMODE: Channel Mode CHMODE 0 0 1 1 0 1 0 1 Mode Description Normal Mode Automatic Echo. Receiver input is connected to the TXD pin. Local Loopback. Transmitter output is connected to the Receiver Input.. Remote Loopback. RXD pin is internally connected to the TXD pin. • MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. 480 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter 0: User defined configuration of command or data sync field depending on SYNC value. 1: The sync field is updated when a character is written into US_THR register. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T= 0. • FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). • MAN: Manchester Encoder/Decoder Enable 0: Manchester Encoder/Decoder are disabled. 1: Manchester Encoder/Decoder are enabled. • MODSYNC: Manchester Synchronization Mode 0:The Manchester Start bit is a 0 to 1 transition 1: The Manchester Start bit is a 1 to 0 transition. • ONEBIT: Start Frame Delimiter Selector 0: Start Frame delimiter is COMMAND or DATA SYNC. 1: Start Frame delimiter is One Bit. 481 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.3 Name: USART Interrupt Enable Register US_IER Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 MANE 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITERATION 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • ENDRX: End of Receive Transfer Interrupt Enable • ENDTX: End of Transmit Interrupt Enable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITERATION: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Enable • RXBUFF: Buffer Full Interrupt Enable • NACK: Non Acknowledge Interrupt Enable • RIIC: Ring Indicator Input Change Enable • DSRIC: Data Set Ready Input Change Enable • DCDIC: Data Carrier Detect Input Change Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable • MANE: Manchester Error Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. 482 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.4 Name: USART Interrupt Disable Register US_IDR Write-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 MANE 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITERATION 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • ENDRX: End of Receive Transfer Interrupt Disable • ENDTX: End of Transmit Interrupt Disable • OVRE: Overrun Error Interrupt Disable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITERATION: Iteration Interrupt Disable • TXBUFE: Buffer Empty Interrupt Disable • RXBUFF: Buffer Full Interrupt Disable • NACK: Non Acknowledge Interrupt Disable • RIIC: Ring Indicator Input Change Disable • DSRIC: Data Set Ready Input Change Disable • DCDIC: Data Carrier Detect Input Change Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable • MANE: Manchester Error Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. 483 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.5 Name: USART Interrupt Mask Register US_IMR Read-only 30 – 22 – 14 – 6 FRAME 29 – 21 – 13 NACK 5 OVRE 28 – 20 MANE 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITERATION 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 – 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 – 15 – 7 PARE • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • ENDRX: End of Receive Transfer Interrupt Mask • ENDTX: End of Transmit Interrupt Mask • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITERATION: Iteration Interrupt Mask • TXBUFE: Buffer Empty Interrupt Mask • RXBUFF: Buffer Full Interrupt Mask • NACK: Non Acknowledge Interrupt Mask • RIIC: Ring Indicator Input Change Mask • DSRIC: Data Set Ready Input Change Mask • DCDIC: Data Carrier Detect Input Change Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask • MANE: Manchester Error Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. 484 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.6 Name: USART Channel Status Register US_CSR Read-only 30 – 22 DCD 14 – 6 FRAME 29 – 21 DSR 13 NACK 5 OVRE 28 – 20 RI 12 RXBUFF 4 ENDTX 27 – 19 CTSIC 11 TXBUFE 3 ENDRX 26 – 18 DCDIC 10 ITERATION 2 RXBRK 25 – 17 DSRIC 9 TXEMPTY 1 TXRDY 24 MANERR 16 RIIC 8 TIMEOUT 0 RXRDY Access Type: 31 – 23 CTS 15 – 7 PARE • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. • ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. • ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. 485 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITERATION: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSIT. 1: Maximum number of repetitions has been reached since the last RSIT. • TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. • RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. • NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. • RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of US_CSR. 1: At least one input change has been detected on the RI pin since the last read of US_CSR. • DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of US_CSR. 1: At least one input change has been detected on the DSR pin since the last read of US_CSR. • DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of US_CSR. 1: At least one input change has been detected on the DCD pin since the last read of US_CSR. • CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. • RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. 486 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. • DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. • CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. • MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. 487 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.7 Name: USART Receive Holding Register US_RHR Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 RXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 RXCHR 0 Access Type: 31 – 23 – 15 RXSYNH 7 • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. 488 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.8 Name: USART Transmit Holding Register US_THR Write-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TXCHR 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 TXCHR 0 Access Type: 31 – 23 – 15 TXSYNH 7 • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. 489 6289C–ATARM–28-May-09 34.7.9 Name: USART Baud Rate Generator Register US_BRGR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CD 7 6 5 4 CD 3 2 1 0 27 – 19 – 11 26 – 18 25 – 17 FP 9 24 – 16 Access Type: 31 – 23 – 15 10 8 • CD: Clock Divider USART_MODE ≠ ISO7816 CD OVER = 0 0 1 to 65535 Baud Rate = Selected Clock/16/CD SYNC = 0 OVER = 1 Baud Rate Clock Disabled Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO SYNC = 1 USART_MODE = ISO7816 • FP: Fractional Part 0: Fractional divider is disabled. 1 - 7: Baudrate resolution, defined by FP x 1/8. 490 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.10 Name: USART Receiver Time-out Register US_RTOR Read/Write 30 29 28 27 26 25 24 Access Type: 31 – 23 – 15 – 22 – 14 – 21 – 13 – 20 – 12 TO – 19 – 11 – 18 – 10 – 17 – 9 – 16 – 8 7 6 5 4 TO 3 2 1 0 • TO: Time-out Value 0: The Receiver Time-out is disabled. 1 - 65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 491 6289C–ATARM–28-May-09 34.7.11 Name: USART Transmitter Timeguard Register US_TTGR Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 TG 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1 - 255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. 492 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 34.7.12 Name: USART FI DI RATIO Register US_FIDI Read/Write 0x174 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 FI_DI_RATIO 27 – 19 – 11 – 3 26 – 18 – 10 25 – 17 – 9 FI_DI_RATIO 1 24 – 16 – 8 Access Type: Reset Value : 31 – 23 – 15 – 7 2 0 • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1 - 2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 34.7.13 Name: USART Number of Errors Register US_NER Read-only 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 NB_ERRORS 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. 493 6289C–ATARM–28-May-09 34.7.14 Name: USART Manchester Configuration Register US_MAN Read/Write 30 DRIFT 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 RX_MPOL 20 – 12 TX_MPOL 4 – 27 – 19 26 – 18 RX_PL 11 – 3 10 – 2 TX_PL 9 TX_PP 1 0 8 25 RX_PP 17 16 24 Access Type: 31 – 23 – 15 – 7 – • TX_PL: Transmitter Preamble Length 0: The Transmitter Preamble pattern generation is disabled 1 - 15: The Preamble Length is TX_PL x Bit Period • TX_PP: Transmitter Preamble Pattern TX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (TX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO • TX_MPOL: Transmitter Manchester Polarity 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • RX_PL: Receiver Preamble Length 0: The receiver preamble pattern detection is disabled 1 - 15: The detected preamble length is RX_PL x Bit Period • RX_PP: Receiver Preamble Pattern detected RX_PP 0 0 1 1 0 1 0 1 Preamble Pattern default polarity assumed (RX_MPOL field not set) ALL_ONE ALL_ZERO ZERO_ONE ONE_ZERO • RX_MPOL: Receiver Manchester Polarity 494 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 0: Logic Zero is coded as a zero-to-one transition, Logic One is coded as a one-to-zero transition. 1: Logic Zero is coded as a one-to-zero transition, Logic One is coded as a zero-to-one transition. • DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. 495 6289C–ATARM–28-May-09 34.7.15 Name: USART IrDA FILTER Register US_IF Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 IRDA_FILTER 27 – 19 – 11 – 3 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 496 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35. Serial Synchronous Controller (SSC) 35.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: • CODEC’s in master or slave mode • DAC through dedicated serial interface, particularly I2S • Magnetic card reader 497 6289C–ATARM–28-May-09 35.2 Block Diagram Figure 35-1. Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK TD SSC Interface PIO RF RK Interrupt Control RD PMC MCK SSC Interrupt 35.3 Application Block Diagram Figure 35-2. Application Block Diagram OS or RTOS Driver Power Management SSC Time Slot Management Frame Management Interrupt Management Test Management Serial AUDIO Codec Line Interface 498 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.4 Pin Name List I/O Lines Description Pin Description Receiver Frame Synchro Receiver Clock Receiver Data Transmitter Frame Synchro Transmitter Clock Transmitter Data Type Input/Output Input/Output Input Input/Output Input/Output Output Table 35-1. Pin Name RF RK RD TF TK TD 35.5 35.5.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. 35.5.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. 35.5.3 35.6 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. 499 6289C–ATARM–28-May-09 Figure 35-3. SSC Functional Block Diagram Transmitter Clock Output Controller TK MCK Clock Divider TK Input RX clock TF RF Start Selector TX PDC Transmit Clock Controller TX clock Frame Sync Controller TF Transmit Shift Register Transmit Holding Register Transmit Sync Holding Register TD APB User Interface Load Shift Receiver Clock Output Controller RK RK Input TX Clock RF TF Start Selector Receive Clock RX Clock Controller Frame Sync Controller RF Receive Shift Register Receive Holding Register Receive Sync Holding Register RD RX PDC PDC Interrupt Control Load Shift AIC 35.6.1 Clock Management The transmitter clock can be generated by: • an external clock received on the TK I/O pad • the receiver clock • the internal clock divider The receiver clock can be generated by: • an external clock received on the RK I/O pad • the transmitter clock • the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 500 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.6.1.1 Clock Divider Figure 35-4. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 35-5. Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 Table 35-2. Maximum MCK / 2 Minimum MCK / 8190 35.6.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR register. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR register to select TK pin 501 6289C–ATARM–28-May-09 (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 35-6. Transmitter Clock Management TK (pin) MUX Receiver Clock Tri_state Controller Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Transmitter Clock CKI CKG 35.6.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR register. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. Figure 35-7. Receiver Clock Management RK (pin) Tri-state Controller MUX Transmitter Clock Clock Output Divider Clock CKO Data Transfer CKS INV MUX Tri-state Controller Receiver Clock CKI CKG 502 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.6.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: – Master Clock divided by 2 if Receiver Frame Synchro is input – Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: – Master Clock divided by 6 if Transmit Frame Synchro is input – Master Clock divided by 2 if Transmit Frame Synchro is output 35.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 504. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 506. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR register then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 35-8. Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock TF SSC_TFMR.MSBF 0 SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB TD Start Selector Transmit Shift Register SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN SSC_THR 0 1 SSC_TSHR SSC_TFMR.FSLEN 503 6289C–ATARM–28-May-09 35.6.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See “Start” on page 504. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 506. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. Figure 35-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF SSC_RFMR.MSBF SSC_RFMR.DATNB Start Selector Receive Shift Register RD SSC_RSHR SSC_RCMR.STTDLY SSC_RFMR.FSLEN SSC_RHR SSC_RFMR.DATLEN 35.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable: • Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled. • Synchronously with the transmitter/receiver • On detection of a falling/rising edge on TF/RF • On detection of a low level/high level on TF/RF • On detection of a level change or an edge on TF/RF 504 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). Figure 35-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF TD (Output) TD (Output) X BO B1 STTDLY Start = Falling Edge on TF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on TF TD (Output) TD (Output) TD (Output) TD (Output) X Start = Rising Edge on TF BO B1 STTDLY Start = Level Change on TF X BO B1 BO B1 STTDLY Start = Any Edge on TF X BO B1 BO B1 STTDLY Figure 35-11. Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF RD (Input) RD (Input) X BO B1 STTDLY Start = Falling Edge on RF X BO B1 STTDLY X BO B1 STTDLY Start = High Level on RF RD (Input) RD (Input) RD (Input) RD (Input) X Start = Rising Edge on RF BO B1 STTDLY Start = Level Change on RF X BO B1 BO B1 STTDLY Start = Any Edge on RF X BO B1 BO B1 STTDLY 505 6289C–ATARM–28-May-09 35.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 256 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 35.6.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out. 35.6.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). Receive Compare Modes Figure 35-12. Receive Compare Modes RK 35.6.6 RD (Input) CMP0 CMP1 CMP2 CMP3 Start Ignored B0 B1 B2 FSLEN Up to 16 Bits (4 in This Example) STDLY DATLEN 506 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.6.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select: • the event that starts the data transfer (START) • the delay in number of bit periods between the start event and the first data bit (STTDLY) • the length of the data (DATLEN) • the number of data to be transferred for each start event (DATNB). • the length of synchronization transferred for each start event (FSLEN) • the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. 35.6.7 507 6289C–ATARM–28-May-09 Table 35-3. Transmitter SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TFMR SSC_TCMR SSC_TCMR Data Frame Registers Receiver SSC_RFMR SSC_RFMR SSC_RFMR SSC_RFMR Field DATLEN DATNB MSBF FSLEN DATDEF FSDEN SSC_RCMR SSC_RCMR PERIOD STTDLY Up to 512 Up to 255 Up to 16 0 or 1 Length Up to 32 Up to 16 Comment Size of word Number of words transmitted in frame Most significant bit first Size of Synchro data register Data default value ended Enable send SSC_TSHR Frame size Size of transmit start delay Figure 35-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start PERIOD TF/RF (1) Start FSLEN TD (If FSDEN = 1) Sync Data Default Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Data From SSC_THR Data From SSC_THR Data To SSC_RHR DATLEN Default FromDATDEF Default From DATDEF Ignored Sync Data Sync Data From SSC_TSHR FromDATDEF Default From DATDEF Sync Data To SSC_RSHR STTDLY Ignored TD (If FSDEN = 0) RD DATNB Note: 1. Example of input on falling edge of TF/RF. 508 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 35-14. Transmit Frame Format in Continuous Mode Start TD Data From SSC_THR DATLEN Data From SSC_THR DATLEN Default Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 35-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Data To SSC_RHR DATLEN Data To SSC_RHR DATLEN Note: 1. STTDLY is set to 0. 35.6.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 35.6.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. 509 6289C–ATARM–28-May-09 Figure 35-16. Interrupt Block Diagram SSC_IMR SSC_IER PDC TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC Interrupt Control Set SSC_IDR Clear SSC Interrupt 35.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 35-17. Audio Application Block Diagram Clock SCK TK Word Select WS TF Data SD SSC TD RD RF RK I2S RECEIVER Clock SCK Word Select WS Data SD MSB Left Channel LSB MSB Right Channel 510 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 35-18. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC TD Serial Data In RD RF RK CODEC Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Dend Serial Data In Figure 35-19. Time Slot Application Block Diagram SCLK TK FSYNC TF Data Out TD SSC RD RF RK Data in CODEC First Time Slot CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) Serial Data Out First Time Slot Dstart Second Time Slot Dend Serial Data in 511 6289C–ATARM–28-May-09 35.8 Synchronous Serial Controller (SSC) User Interface Register Mapping Register Control Register Clock Mode Register Reserved Reserved Receive Clock Mode Register Receive Frame Mode Register Transmit Clock Mode Register Transmit Frame Mode Register Receive Holding Register Transmit Holding Register Reserved Reserved Receive Sync. Holding Register Transmit Sync. Holding Register Receive Compare 0 Register Receive Compare 1 Register Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved Reserved for Peripheral Data Controller (PDC) Register Name SSC_CR SSC_CMR – – SSC_RCMR SSC_RFMR SSC_TCMR SSC_TFMR SSC_RHR SSC_THR – – SSC_RSHR SSC_TSHR SSC_RC0R SSC_RC1R SSC_SR SSC_IER SSC_IDR SSC_IMR – – Access Write Read/Write – – Read/Write Read/Write Read/Write Read/Write Read Write – – Read Read/Write Read/Write Read/Write Read Write Write Read – – Reset – 0x0 – – 0x0 0x0 0x0 0x0 0x0 – – – 0x0 0x0 0x0 0x0 0x000000CC – – 0x0 – – Table 35-4. Offset 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 0x4C 0x50-0xFC 0x100- 0x124 512 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.1 Name: SSC Control Register SSC_CR Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 TXDIS 1 RXDIS 24 – 16 – 8 TXEN 0 RXEN Access Type: 31 – 23 – 15 SWRST 7 – • RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0: No effect. 1: Disables Receive. If a character is currently being received, disables at end of current character reception. • TXEN: Transmit Enable 0: No effect. 1: Enables Transmit if TXDIS is not set. • TXDIS: Transmit Disable 0: No effect. 1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. • SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR. 513 6289C–ATARM–28-May-09 35.8.2 Name: SSC Clock Mode Register SSC_CMR Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 DIV 27 – 19 – 11 26 – 18 – 10 DIV 3 2 1 0 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 – 7 • DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 514 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.3 Name: SSC Receive Clock Mode Register SSC_RCMR Read/Write 30 29 28 PERIOD 23 22 21 20 STDDLY 15 – 7 CKG 14 – 6 13 – 5 CKI 12 STOP 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 Access Type: 31 • CKS: Receive Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Receive Clock Divided Clock TK Clock signal RK pin Reserved • CKO: Receive Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Receive Clock Output Mode None Continuous Receive Clock Receive Clock only during data transfers Reserved RK Pin Input-only Output Output • CKI: Receive Clock Inversion 0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. 515 6289C–ATARM–28-May-09 • CKG: Receive Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Receive Clock Gating None, continuous clock Receive Clock enabled only if RF Low Receive Clock enabled only if RF High Reserved • START: Receive Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9-0xF Receive Start Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. Transmit start Detection of a low level on RF signal Detection of a high level on RF signal Detection of a falling edge on RF signal Detection of a rising edge on RF signal Detection of any level change on RF signal Detection of any edge on RF signal Compare 0 Reserved • STOP: Receive Stop Selection 0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. • STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 x (PERIOD+1) Receive Clock. 516 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.4 Name: SSC Receive Frame Mode Register SSC_RFMR Read/Write 30 FSLEN_EXT 22 29 FSLEN_EXT 21 FSOS 13 – 5 LOOP 28 FSLEN_EXT Access Type: 31 FSLEN_EXT 23 – 15 – 7 MSBF 27 – 19 26 – 18 FSLEN 25 – 17 24 FSEDGE 16 20 14 – 6 – 12 – 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). • FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Receive Clock periods. 517 6289C–ATARM–28-May-09 • FSOS: Receive Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Receive Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved RF Pin Input-only Output Output Output Output Output Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection • FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description on page 517. 518 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.5 Name: SSC Transmit Clock Mode Register SSC_TCMR Read/Write 30 29 28 PERIOD 23 22 21 20 STTDLY 15 – 7 CKG 14 – 6 13 – 5 CKI 12 – 4 11 10 START 3 CKO 2 1 CKS 0 9 8 19 18 17 16 27 26 25 24 Access Type: 31 • CKS: Transmit Clock Selection CKS 0x0 0x1 0x2 0x3 Selected Transmit Clock Divided Clock RK Clock signal TK Pin Reserved • CKO: Transmit Clock Output Mode Selection CKO 0x0 0x1 0x2 0x3-0x7 Transmit Clock Output Mode None Continuous Transmit Clock Transmit Clock only during data transfers Reserved TK pin Input-only Output Output • CKI: Transmit Clock Inversion 0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. 519 6289C–ATARM–28-May-09 • CKG: Transmit Clock Gating Selection CKG 0x0 0x1 0x2 0x3 Transmit Clock Gating None, continuous clock Transmit Clock enabled only if TF Low Transmit Clock enabled only if TF High Reserved • START: Transmit Start Selection START 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 - 0xF Transmit Start Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. Receive start Detection of a low level on TF signal Detection of a high level on TF signal Detection of a falling edge on TF signal Detection of a rising edge on TF signal Detection of any level change on TF signal Detection of any edge on TF signal Reserved • STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 x (PERIOD+1) Transmit Clock. 520 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.6 Name: SSC Transmit Frame Mode Register SSC_TFMR Read/Write 30 FSLEN_EXT 22 29 FSLEN_EXT 21 FSOS 13 – 5 DATDEF 28 FSLEN_EXT Access Type: 31 FSLEN_EXT 23 FSDEN 15 – 7 MSBF 27 – 19 26 – 18 FSLEN 25 – 17 24 FSEDGE 16 20 14 – 6 – 12 – 4 11 10 DATNB 9 8 3 2 DATLEN 1 0 • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. • DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB +1). • FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + (FSLEN_EXT * 16) + 1 Transmit Clock periods. 521 6289C–ATARM–28-May-09 • FSOS: Transmit Frame Sync Output Selection FSOS 0x0 0x1 0x2 0x3 0x4 0x5 0x6-0x7 Selected Transmit Frame Sync Signal None Negative Pulse Positive Pulse Driven Low during data transfer Driven High during data transfer Toggling at each start of data transfer Reserved TF Pin Input-only Output Output Output Output Output Undefined • FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). FSEDGE 0x0 0x1 Frame Sync Edge Detection Positive Edge Detection Negative Edge Detection • FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description on page 521. 522 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.7 Name: SSC Receive Holding Register SSC_RHR Read-only 30 29 28 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 Access Type: 31 • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 35.8.8 Name: SSC Transmit Holding Register SSC_THR Write-only 30 29 28 TDAT 27 26 25 24 Access Type: 31 23 22 21 20 TDAT 19 18 17 16 15 14 13 12 TDAT 11 10 9 8 7 6 5 4 TDAT 3 2 1 0 • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 523 6289C–ATARM–28-May-09 35.8.9 Name: SSC Receive Synchronization Holding Register SSC_RSHR Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RSDAT 7 6 5 4 RSDAT 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 • RSDAT: Receive Synchronization Data 35.8.10 Name: SSC Transmit Synchronization Holding Register SSC_TSHR Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 TSDAT 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 7 6 5 4 TSDAT 3 2 1 0 • TSDAT: Transmit Synchronization Data 524 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.11 Name: SSC Receive Compare 0 Register SSC_RC0R Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CP0 7 6 5 4 CP0 3 2 1 0 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 • CP0: Receive Compare Data 0 525 6289C–ATARM–28-May-09 35.8.12 Name: SSC Receive Compare 1 Register SSC_RC1R Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CP1 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 7 6 5 4 CP1 3 2 1 0 • CP1: Receive Compare Data 1 526 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.13 Name: SSC Status Register SSC_SR Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 RXEN 9 CP1 1 TXEMPTY 24 – 16 TXEN 8 CP0 0 TXRDY Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty. • TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from TSR. 1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. • ENDTX: End of Transmission 0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. • TXBUFE: Transmit Buffer Empty 0: SSC_TCR or SSC_TNCR have a value other than 0. 1: Both SSC_TCR and SSC_TNCR have a value of 0. • RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. • OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. • ENDRX: End of Reception 0: Data is written on the Receive Counter Register or Receive Next Counter Register. 1: End of PDC transfer when Receive Counter Register has arrived at zero. • RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 527 6289C–ATARM–28-May-09 1: Both SSC_RCR and SSC_RNCR have a value of 0. • CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register. • TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. • RXSYN: Receive Sync 0: An Rx Sync has not occurred since the last read of the Status Register. 1: An Rx Sync has occurred since the last read of the Status Register. • TXEN: Transmit Enable 0: Transmit is disabled. 1: Transmit is enabled. • RXEN: Receive Enable 0: Receive is disabled. 1: Receive is enabled. 528 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.14 Name: SSC Interrupt Enable Register SSC_IER Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Enable 0: No effect. 1: Enables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Buffer Empty Interrupt • RXRDY: Receive Ready Interrupt Enable 0: No effect. 1: Enables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Enable 0: No effect. 1: Enables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Enable 0: No effect. 1: Enables the End of Reception Interrupt. • RXBUFF: Receive Buffer Full Interrupt Enable 0: No effect. 529 6289C–ATARM–28-May-09 1: Enables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt. 530 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.15 Name: SSC Interrupt Disable Register SSC_IDR Write-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Access Type: 31 – 23 – 15 – 7 RXBUFF • TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Disable 0: No effect. 1: Disables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Buffer Empty Interrupt. • RXRDY: Receive Ready Interrupt Disable 0: No effect. 1: Disables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Disable 0: No effect. 1: Disables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Disable 0: No effect. 1: Disables the End of Reception Interrupt. • RXBUFF: Receive Buffer Full Interrupt Disable 0: No effect. 531 6289C–ATARM–28-May-09 1: Disables the Receive Buffer Full Interrupt. • CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt. 532 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 35.8.16 Name: SSC Interrupt Mask Register SSC_IMR Read-only 30 – 22 – 14 – 6 ENDRX 29 – 21 – 13 – 5 OVRUN 28 – 20 – 12 – 4 RXRDY 27 – 19 – 11 RXSYN 3 TXBUFE 26 – 18 – 10 TXSYN 2 ENDTX 25 – 17 – 9 CP1 1 TXEMPTY 24 – 16 – 8 CP0 0 TXRDY Access Type: 31 – 23 – 15 – 7 RXBUF • TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled. • TXEMPTY: Transmit Empty Interrupt Mask 0: The Transmit Empty Interrupt is disabled. 1: The Transmit Empty Interrupt is enabled. • ENDTX: End of Transmission Interrupt Mask 0: The End of Transmission Interrupt is disabled. 1: The End of Transmission Interrupt is enabled. • TXBUFE: Transmit Buffer Empty Interrupt Mask 0: The Transmit Buffer Empty Interrupt is disabled. 1: The Transmit Buffer Empty Interrupt is enabled. • RXRDY: Receive Ready Interrupt Mask 0: The Receive Ready Interrupt is disabled. 1: The Receive Ready Interrupt is enabled. • OVRUN: Receive Overrun Interrupt Mask 0: The Receive Overrun Interrupt is disabled. 1: The Receive Overrun Interrupt is enabled. • ENDRX: End of Reception Interrupt Mask 0: The End of Reception Interrupt is disabled. 1: The End of Reception Interrupt is enabled. • RXBUFF: Receive Buffer Full Interrupt Mask 0: The Receive Buffer Full Interrupt is disabled. 533 6289C–ATARM–28-May-09 1: The Receive Buffer Full Interrupt is enabled. • CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled. 534 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36. Timer Counter (TC) 36.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 36-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2 Table 36-1. Name Timer Counter Clock Assignment Definition MCK/2 MCK/8 MCK/32 MCK/128 SLCK TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 535 6289C–ATARM–28-May-09 36.2 Block Diagram Figure 36-1. Timer Counter Block Diagram Parallel I/O Controller TCLK0 TIMER_CLOCK2 TIMER_CLOCK1 TIOA1 TIMER_CLOCK3 TCLK0 TCLK1 TCLK2 TIOA0 TIOB0 TIOA2 TCLK1 XC0 XC1 XC2 TC0XC0S Timer/Counter Channel 0 TIOA TIOA0 TIOB TIMER_CLOCK4 TIMER_CLOCK5 TCLK2 TIOB0 SYNC INT0 TCLK0 TCLK1 TIOA0 TIOA2 TCLK2 XC0 XC1 XC2 TC1XC1S SYNC Timer/Counter Channel 1 TIOA TIOA1 TIOB TIOB1 INT1 TIOA1 TIOB1 TCLK0 TCLK1 TCLK2 TIOA0 TIOA1 XC0 XC1 XC2 TC2XC2S Timer/Counter Channel 2 TIOA TIOA2 TIOB TIOB2 SYNC TIOA2 TIOB2 INT2 Timer Counter Advanced Interrupt Controller Table 36-2. Signal Name Description Signal Name XC0, XC1, XC2 TIOA Description External Clock Inputs Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output Interrupt Signal Output Synchronization Input Signal Block/Channel Channel Signal TIOB INT SYNC 536 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.3 Pin Name List Table 36-3. Pin Name TCLK0-TCLK2 TIOA0-TIOA2 TIOB0-TIOB2 TC Pin List Description External Clock Input I/O Line A I/O Line B Type Input I/O I/O 36.4 36.4.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 36.4.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. 36.4.3 537 6289C–ATARM–28-May-09 36.5 36.5.1 Functional Description TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 36-5 on page 551. 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register, TC_CV. The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 36.5.2 36.5.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 36-2 on page 539. Each channel can independently select an internal or external clock source for its counter: • Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5 • External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 36-3 on page 539 Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock 538 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 36-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TIOA1 TIOA2 XC0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 TIOA0 TCLK0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 TIOA0 TIOA2 XC0 = TCLK2 XC1 XC2 = TCLK2 TIOB1 TIOA1 SYNC TC2XC2S Timer/Counter Channel 2 XC0 = TCLK0 TIOA2 TCLK2 TIOA0 TIOA1 XC1 = TCLK1 XC2 TIOB2 SYNC Figure 36-3. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 CLKI Selected Clock BURST 1 539 6289C–ATARM–28-May-09 36.5.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 36-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can re-enable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register. • The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. Figure 36-4. Clock Control Selected Clock Trigger CLKSTA CLKEN CLKDIS Q Q S R S R Counter Clock Stop Event Disable Event 36.5.5 TC Operating Modes Each channel can independently operate in two different modes: • Capture Mode provides measurement on signals. • Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 36.5.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes: 540 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR. • SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. • Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 36.5.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 36-5 shows the configuration of the TC channel when programmed in Capture Mode. 36.5.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 36.5.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. 541 6289C–ATARM–28-May-09 Figure 36-5. Capture Mode 542 TCCLKS CLKI CLKSTA CLKEN CLKDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 Q Q R S R S TIMER_CLOCK5 XC0 XC1 LDBSTOP BURST LDBDIS XC2 Register C 1 16-bit Counter CLK OVF RESET Trig ABETRG ETRGEDG Edge Detector LDRA LDRB CPCTRG Capture Register A SWTRG Capture Register B Compare RC = AT91SAM9R64/RL64 Preliminary CPCS LOVRS LDRAS LDRBS ETRGS COVFS TC1_SR SYNC MTIOB TIOB MTIOA If RA is not loaded or RB is Loaded Edge Detector If RA is Loaded Edge Detector TC1_IMR TIOA Timer/Counter Channel 6289C–ATARM–28-May-09 INT AT91SAM9R64/RL64 Preliminary 36.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 36-6 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 36.5.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. 543 6289C–ATARM–28-May-09 Figure 36-6. Waveform Mode BURST Register A WAVSEL Register B Register C ASWTRG Compare RA = Compare RB = Compare RC = 1 16-bit Counter CLK RESET OVF SWTRG BCPC Trig BCPB WAVSEL EEVT BEEVT EEVTEDG TC1_SR ENETRG Edge Detector CPCS CPAS CPBS ETRGS COVFS MTIOB TIOB TC1_IMR BSWTRG Timer/Counter Channel INT Output Controller AT91SAM9R64/RL64 Preliminary TCCLKS CLKSTA ACPC CLKI CLKEN CLKDIS SYNC Output Controller 544 Q CPCDIS TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 S R ACPA MTIOA TIMER_CLOCK5 Q R CPCSTOP S XC0 XC1 XC2 AEEVT TIOA TIOB 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 36-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 36-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 36-7. WAVSEL= 00 without trigger Counter Value 0xFFFF Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 545 6289C–ATARM–28-May-09 Figure 36-8. WAVSEL= 00 with trigger Counter Value 0xFFFF Counter cleared by trigger Counter cleared by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA 36.5.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 36-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 36-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 36-9. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA 546 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 36-10. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB Counter cleared by trigger RA Waveform Examples TIOB Time TIOA 36.5.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 36-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 547 6289C–ATARM–28-May-09 Figure 36-11. WAVSEL = 01 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with 0xFFFF RC RB RA Waveform Examples TIOB Time TIOA Figure 36-12. WAVSEL = 01 With Trigger Counter Value 0xFFFF Counter decremented by trigger RC RB Counter decremented by compare match with 0xFFFF Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 36.5.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 36-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 36-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). 548 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 36-13. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Waveform Examples TIOB Time TIOA Figure 36-14. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 549 6289C–ATARM–28-May-09 36.5.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 36.5.13 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. 550 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.6 Timer Counter (TC) User Interface TC Global Memory Map Channel/Register TC Channel 0 TC Channel 1 TC Channel 2 TC Block Control Register TC Block Mode Register TC_BCR TC_BMR Name Access See Table 36-5 See Table 36-5 See Table 36-5 Write-only Read/Write – 0 Reset Value Table 36-4. Offset 0x00 0x40 0x80 0xC0 0xC4 TC_BCR (Block Control Register) and TC_BMR (Block Mode Register) control the whole TC block. TC channels are controlled by the registers listed in Table 36-5. The offset of each of the channel registers in Table 36-5 is in relation to the offset of the corresponding channel as mentioned in Table 36-5. Table 36-5. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0xFC Notes: TC Channel Memory Map Register Channel Control Register Channel Mode Register Reserved Reserved Counter Value Register A Register B Register C Status Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Reserved TC_CV TC_RA TC_RB TC_RC TC_SR TC_IER TC_IDR TC_IMR – Read-only Read/Write(1) Read/Write (1) Name TC_CCR TC_CMR Access Write-only Read/Write Reset Value – 0 – – 0 0 0 0 0 – – 0 – Read/Write Read-only Write-only Write-only Read-only – 1. Read-only if WAVE = 0 551 6289C–ATARM–28-May-09 36.6.1 TC Block Control Register Register Name: TC_BCR Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 SYNC • SYNC: Synchro Command 0 = No effect. 1 = Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 552 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.6.2 TC Block Mode Register Register Name: TC_BMR Access Type: 31 – 23 – 15 – 7 – Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 TC2XC2S 28 – 20 – 12 – 4 27 – 19 – 11 – 3 TCXC1S 26 – 18 – 10 – 2 25 – 17 – 9 – 1 TC0XC0S 24 – 16 – 8 – 0 • TC0XC0S: External Clock Signal 0 Selection TC0XC0S 0 0 1 1 0 1 0 1 Signal Connected to XC0 TCLK0 none TIOA1 TIOA2 • TC1XC1S: External Clock Signal 1 Selection TC1XC1S 0 0 1 1 0 1 0 1 Signal Connected to XC1 TCLK1 none TIOA0 TIOA2 • TC2XC2S: External Clock Signal 2 Selection TC2XC2S 0 0 1 1 0 1 0 1 Signal Connected to XC2 TCLK2 none TIOA0 TIOA1 553 6289C–ATARM–28-May-09 36.6.3 TC Channel Control Register Register Name: TC_CCR Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 SWTRG 25 – 17 – 9 – 1 CLKDIS 24 – 16 – 8 – 0 CLKEN • CLKEN: Counter Clock Enable Command 0 = No effect. 1 = Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0 = No effect. 1 = Disables the clock. • SWTRG: Software Trigger Command 0 = No effect. 1 = A software trigger is performed: the counter is reset and the clock is started. 554 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.6.4 TC Channel Mode Register: Capture Mode Register Name: TC_CMR Access Type: 31 – 23 – 15 WAVE = 0 7 LDBDIS Read/Write 30 – 22 – 14 CPCTRG 6 LDBSTOP 29 – 21 – 13 – 5 BURST 28 – 20 – 12 – 4 11 – 3 CLKI 27 – 19 LDRB 10 ABETRG 2 1 TCCLKS 9 ETRGEDG 0 26 – 18 25 – 17 LDRA 8 24 – 16 • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • LDBSTOP: Counter Clock Stopped with RB Loading 0 = Counter clock is not stopped when RB loading occurs. 1 = Counter clock is stopped when RB loading occurs. • LDBDIS: Counter Clock Disable with RB Loading 0 = Counter clock is not disabled when RB loading occurs. 1 = Counter clock is disabled when RB loading occurs. 555 6289C–ATARM–28-May-09 • ETRGEDG: External Trigger Edge Selection ETRGEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • ABETRG: TIOA or TIOB External Trigger Selection 0 = TIOB is used as an external trigger. 1 = TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0 = RC Compare has no effect on the counter and its clock. 1 = RC Compare resets the counter and starts the counter clock. • WAVE 0 = Capture Mode is enabled. 1 = Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection LDRA 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA • LDRB: RB Loading Selection LDRB 0 0 1 1 0 1 0 1 Edge none rising edge of TIOA falling edge of TIOA each edge of TIOA 556 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.6.5 TC Channel Mode Register: Waveform Mode Register Name: TC_CMR Access Type: 31 BSWTRG 23 ASWTRG 15 WAVE = 1 7 CPCDIS 6 CPCSTOP 14 WAVSEL 5 BURST 13 22 21 AEEVT 12 ENETRG 4 3 CLKI 11 EEVT 2 1 TCCLKS Read/Write 30 29 BEEVT 20 19 ACPC 10 9 EEVTEDG 0 28 27 BCPC 18 17 ACPA 8 26 25 BCPB 16 24 • TCCLKS: Clock Selection TCCLKS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Clock Selected TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 • CLKI: Clock Invert 0 = Counter is incremented on rising edge of the clock. 1 = Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection BURST 0 0 1 1 0 1 0 1 The clock is not gated by an external signal. XC0 is ANDed with the selected clock. XC1 is ANDed with the selected clock. XC2 is ANDed with the selected clock. • CPCSTOP: Counter Clock Stopped with RC Compare 0 = Counter clock is not stopped when counter reaches RC. 1 = Counter clock is stopped when counter reaches RC. • CPCDIS: Counter Clock Disable with RC Compare 0 = Counter clock is not disabled when counter reaches RC. 1 = Counter clock is disabled when counter reaches RC. 557 6289C–ATARM–28-May-09 • EEVTEDG: External Event Edge Selection EEVTEDG 0 0 1 1 0 1 0 1 Edge none rising edge falling edge each edge • EEVT: External Event Selection EEVT 0 0 1 1 Note: 0 1 0 1 Signal selected as external event TIOB XC0 XC1 XC2 TIOB Direction input (1) output output output 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • ENETRG: External Event Trigger Enable 0 = The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1 = The external event resets the counter and starts the counter clock. • WAVSEL: Waveform Selection WAVSEL 0 1 0 1 0 0 1 1 Effect UP mode without automatic trigger on RC Compare UP mode with automatic trigger on RC Compare UPDOWN mode without automatic trigger on RC Compare UPDOWN mode with automatic trigger on RC Compare • WAVE = 1 0 = Waveform Mode is disabled (Capture Mode is enabled). 1 = Waveform Mode is enabled. • ACPA: RA Compare Effect on TIOA ACPA 0 0 1 1 0 1 0 1 Effect none set clear toggle 558 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • ACPC: RC Compare Effect on TIOA ACPC 0 0 1 1 0 1 0 1 Effect none set clear toggle • AEEVT: External Event Effect on TIOA AEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle • BCPB: RB Compare Effect on TIOB BCPB 0 0 1 1 0 1 0 1 Effect none set clear toggle • BCPC: RC Compare Effect on TIOB BCPC 0 0 1 1 0 1 0 1 Effect none set clear toggle 559 6289C–ATARM–28-May-09 • BEEVT: External Event Effect on TIOB BEEVT 0 0 1 1 0 1 0 1 Effect none set clear toggle • BSWTRG: Software Trigger Effect on TIOB BSWTRG 0 0 1 1 0 1 0 1 Effect none set clear toggle 560 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.6.6 TC Counter Value Register Register Name: TC_CV Access Type: 31 – 23 – 15 Read-only 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 CV 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 CV 3 2 1 0 • CV: Counter Value CV contains the counter value in real time. 561 6289C–ATARM–28-May-09 36.6.7 TC Register A Register Name: TC_RA Access Type: 31 – 23 – 15 Read-only if WAVE = 0, Read/Write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RA 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RA 3 2 1 0 • RA: Register A RA contains the Register A value in real time. 36.6.8 TC Register B Register Name: TC_RB Access Type: 31 – 23 – 15 Read-only if WAVE = 0, Read/Write if WAVE = 1 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RB 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RB 3 2 1 0 • RB: Register B RB contains the Register B value in real time. 562 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.6.9 TC Register C Register Name: TC_RC Access Type: 31 – 23 – 15 Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 RC 27 – 19 – 11 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 7 6 5 4 RC 3 2 1 0 • RC: Register C RC contains the Register C value in real time. 563 6289C–ATARM–28-May-09 36.6.10 TC Status Register Register Name: TC_SR Access Type: 31 – 23 – 15 – 7 ETRGS Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 MTIOB 10 – 2 CPAS 25 – 17 MTIOA 9 – 1 LOVRS 24 – 16 CLKSTA 8 – 0 COVFS • COVFS: Counter Overflow Status 0 = No counter overflow has occurred since the last read of the Status Register. 1 = A counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status 0 = Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. • CPAS: RA Compare Status 0 = RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RA Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPBS: RB Compare Status 0 = RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1 = RB Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPCS: RC Compare Status 0 = RC Compare has not occurred since the last read of the Status Register. 1 = RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status 0 = RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RA Load has occurred since the last read of the Status Register, if WAVE = 0. • LDRBS: RB Loading Status 0 = RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1 = RB Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status 0 = External trigger has not occurred since the last read of the Status Register. 1 = External trigger has occurred since the last read of the Status Register. 564 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • CLKSTA: Clock Enabling Status 0 = Clock is disabled. 1 = Clock is enabled. • MTIOA: TIOA Mirror 0 = TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1 = TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0 = TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1 = TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. 565 6289C–ATARM–28-May-09 36.6.11 TC Interrupt Enable Register Register Name: TC_IER Access Type: 31 – 23 – 15 – 7 ETRGS Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Enables the Load Overrun Interrupt. • CPAS: RA Compare 0 = No effect. 1 = Enables the RA Compare Interrupt. • CPBS: RB Compare 0 = No effect. 1 = Enables the RB Compare Interrupt. • CPCS: RC Compare 0 = No effect. 1 = Enables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Enables the RA Load Interrupt. • LDRBS: RB Loading 0 = No effect. 1 = Enables the RB Load Interrupt. • ETRGS: External Trigger 0 = No effect. 1 = Enables the External Trigger Interrupt. 566 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 36.6.12 TC Interrupt Disable Register Register Name: TC_IDR Access Type: 31 – 23 – 15 – 7 ETRGS Write-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = No effect. 1 = Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0 = No effect. 1 = Disables the Load Overrun Interrupt (if WAVE = 0). • CPAS: RA Compare 0 = No effect. 1 = Disables the RA Compare Interrupt (if WAVE = 1). • CPBS: RB Compare 0 = No effect. 1 = Disables the RB Compare Interrupt (if WAVE = 1). • CPCS: RC Compare 0 = No effect. 1 = Disables the RC Compare Interrupt. • LDRAS: RA Loading 0 = No effect. 1 = Disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading 0 = No effect. 1 = Disables the RB Load Interrupt (if WAVE = 0). • ETRGS: External Trigger 0 = No effect. 1 = Disables the External Trigger Interrupt. 567 6289C–ATARM–28-May-09 36.6.13 TC Interrupt Mask Register Register Name: TC_IMR Access Type: 31 – 23 – 15 – 7 ETRGS Read-only 30 – 22 – 14 – 6 LDRBS 29 – 21 – 13 – 5 LDRAS 28 – 20 – 12 – 4 CPCS 27 – 19 – 11 – 3 CPBS 26 – 18 – 10 – 2 CPAS 25 – 17 – 9 – 1 LOVRS 24 – 16 – 8 – 0 COVFS • COVFS: Counter Overflow 0 = The Counter Overflow Interrupt is disabled. 1 = The Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0 = The Load Overrun Interrupt is disabled. 1 = The Load Overrun Interrupt is enabled. • CPAS: RA Compare 0 = The RA Compare Interrupt is disabled. 1 = The RA Compare Interrupt is enabled. • CPBS: RB Compare 0 = The RB Compare Interrupt is disabled. 1 = The RB Compare Interrupt is enabled. • CPCS: RC Compare 0 = The RC Compare Interrupt is disabled. 1 = The RC Compare Interrupt is enabled. • LDRAS: RA Loading 0 = The Load RA Interrupt is disabled. 1 = The Load RA Interrupt is enabled. • LDRBS: RB Loading 0 = The Load RB Interrupt is disabled. 1 = The Load RB Interrupt is enabled. • ETRGS: External Trigger 0 = The External Trigger Interrupt is disabled. 1 = The External Trigger Interrupt is enabled. 568 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37. DMA Controller (DMAC) 37.1 Description The DMA Controller (DMAC) is an AHB-central DMA controller core that transfers data from a source peripheral to a destination peripheral over one or more AMBA buses. One channel is required for each source/destination pair. In the most basic configuration, the DMAC has one master interface and one channel. The master interface reads the data from a source and writes it to a destination. Two AMBA transfers are required for each DMAC data transfer. This is also known as a dual-access transfer. The DMAC is programmed via the APB interface. 569 6289C–ATARM–28-May-09 37.2 Block Diagram Figure 37-1. DMA Controller (DMAC) Block Diagram AMBA AHB Layer 1 DMA AHB Lite Master Interface 1 DMA Global Control and Data Mux DMA Global Request Arbiter DMA Destination Requests Pool DMA Write Datapath Bundles DMA Channel n DMA Destination DMA Channel 2 DMA Channel 1 DMA Channel 0 DMA Channel 0 Write data path to destination Atmel APB rev2 Interface Status Registers Configuration Registers DMA Atmel APB Interface DMA Destination Control State Machine Destination Pointer Management DMA Interrupt Controller DMA Interrupt DMA FIFO Controller DMA FIFO Up to 64 bytes DMA Channel 0 Read data path from source DMA Source Control State Machine Source Pointer Management DMA Read Datapath Bundles DMA Global Control and Data Mux DMA Source Requests Pool DMA Global Request Arbiter DMA AHB Lite Master Interface 0 AMBA AHB Layer 0 570 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.3 37.3.1 Functional Description Basic Definitions Source peripheral: Device on an AMBA layer from where the DMAC reads data, which is then stored in the channel FIFO. The source peripheral teams up with a destination peripheral to form a channel. Destination peripheral: Device to which the DMAC writes the stored data from the FIFO (previously read from the source peripheral). Memory: Source or destination that is always “ready” for a DMAC transfer and does not require a handshaking interface to interact with the DMAC. Channel: Read/write datapath between a source peripheral on one configured AMBA layer and a destination peripheral on the same or different AMBA layer that occurs through the channel FIFO. Master interface: DMAC is a master on the AHB bus reading data from the source and writing it to the destination over the AHB bus. Slave interface: The APB interface over which the DMAC is programmed. The slave interface in practice could be on the same layer as any of the master interfaces or on a separate layer. Figure 37-2. DMAC Transfer Hierarchy for Memory HDMA Transfer DMA Transfer Level Buffer Buffer Buffer Buffer Transfer Level AMBA Burst Transfer AMBA Burst Transfer AMBA Burst Transfer AMBA Single Transfer AMBA Transfer Level Buffer: A buffer of DMAC data. The amount of data (length) is determined by the flow controller. For transfers between the DMAC and memory, a buffer is broken directly into a sequence of AMBA bursts and AMBA single transfers. DMAC transfer: Software controls the number of buffers in a DMAC transfer. Once the DMAC transfer has completed, then hardware within the DMAC disables the channel and can generate an interrupt to signal the completion of the DMAC transfer. You can then re-program the channel for a new DMAC transfer. Single-buffer DMAC transfer: Consists of a single buffer. Multi-buffer DMAC transfer: A DMAC transfer may consist of multiple DMAC buffers. Multi-buffer DMAC transfers are supported through buffer chaining (linked list pointers), auto-reloading of channel registers, and contiguous buffers. The source and destination can independently select which method to use. 571 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – Linked lists (buffer chaining) – A descriptor pointer (DSCR) points to the location in system memory where the next linked list item (LLI) exists. The LLI is a set of registers that describe the next buffer (buffer descriptor) and a descriptor pointer register. The DMAC fetches the LLI at the beginning of every buffer when buffer chaining is enabled. – Replay – The DMAC automatically reloads the channel registers at the end of each buffers to the value when the channel was first enabled. – Contiguous buffers – Where the address of the next buffer is selected to be a continuation from the end of the previous buffer. Picture-in-Picture Mode: DMAC contains a picture-in-picture mode support. When this mode is enabled, addresses are automatically incremented by a programmable value when the DMAC channel transfer count reaches a user defined boundary. Figure 37-3 on page 572 illustrates a memory mapped image 4:2:2 encoded located at image_base_address in memory. A user defined start address is defined at Picture_start_address. The incremented value is set to memory_hole_size = image_width picture_width, and the boundary is set to picture_width. Figure 37-3. Picture-In-Picture Mode Support Bus locking: Software can program a channel to maintain control of the AMBA bus by asserting hmastlock for the duration of a DMAC transfer. Channel locking is asserted for the duration of bus locking at a minimum. 37.3.2 Memory Peripherals Figure 37-2 on page 571 shows the DMAC transfer hierarchy of the DMAC for a memory peripheral. There is no handshaking interface with the DMAC, and therefore the memory peripheral can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately without waiting for a transaction request. The alternative to not having a transaction-level hand- 572 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary shaking interface is to allow the DMAC to attempt AMBA transfers to the peripheral once the channel is enabled. If the peripheral slave cannot accept these AMBA transfers, it inserts wait states onto the bus until it is ready; it is not recommended that more than 16 wait states be inserted onto the bus. 37.3.3 DMAC Transfer Types A DMAC transfer may consist of single or multi-buffers transfers. On successive buffers of a multi-buffer transfer, the DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are reprogrammed using either of the following methods: • Buffer chaining using linked lists • Replay mode • Contiguous address between buffers On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx registers in the DMAC are re-programmed using either of the following methods: • Buffer chaining using linked lists • Replay mode When buffer chaining, using linked lists is the multi-buffer method of choice, and on successive buffers, the DMAC_DSCRx register in the DMAC is re-programmed using the following method: • Buffer chaining using linked lists A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the DMAC_CFGx register, are used by the DMAC to set up and describe the buffer transfer. 37.3.3.1 37.3.3.2 Multi-buffer Transfers Buffer Chaining Using Linked Lists In this case, the DMAC re-programs the channel registers prior to the start of each buffer by fetching the buffer descriptor for that buffer from system memory. This is known as an LLI update. DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that stores the address in memory of the next buffer descriptor. Each buffer descriptor contains the corresponding buffer descriptor (DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx DMAC_CTRLBx). To set up buffer chaining, a sequence of linked lists must be programmed in memory. The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx registers are fetched from system memory on an LLI update. The updated content of the DMAC_CTRLAx register is written back to memory on buffer completion. Figure 37-4 on page 574 shows how to use chained linked lists in memory to define multi-buffer transfers using buffer chaining. The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0) (LLI(0) base address) and DMAC_CTRLBx register with both SRC_DSCR and DST_DSCR set to 0. Other fields and registers are ignored and overwritten when the descriptor is retrieved from memory. The last transfer descriptor must be written to memory with its next descriptor address set to 0. 573 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 37-4. Multi Buffer Transfer Using Linked List System Memory LLI(0) DSCRx(1)= DSCRx(0) + 0x10 CTRLBx= DSCRx(0) + 0xC CTRLAx= DSCRx(0) + 0x8 DADDRx= DSCRx(0) + 0x4 SADDRx= DSCRx(0) + 0x0 DSCRx(1) LLI(1) DSCRx(2)= DSCRx(1) + 0x10 CTRLBx= DSCRx(1) + 0xC CTRLBx= DSCRx(1) + 0x8 DADDRx= DSCRx(1) + 0x4 SADDRx= DSCRx(1) + 0x0 DSCRx(2) (points to 0 if LLI(1) is the last transfer descriptor DSCRx(0) 574 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.3.3.3 Table 37-1. Programming DMAC for Multiple Buffer Transfers Multiple Buffers Transfer Management Table AUTO 0 SRC_REP – DST_REP – SRC_DSCR 1 DST_DSCR 1 BTSIZE USR SADDR USR DADDR USR Other Fields USR Transfer Type 1) Single Buffer or Last buffer of a multiple buffer transfer 2) Multi Buffer transfer with contiguous DADDR 3) Multi Buffer transfer with contiguous SADDR 4) Multi Buffer transfer with LLI support 5) Multi Buffer transfer with DADDR reloaded 6) Multi Buffer transfer with SADDR reloaded 7) Multi Buffer transfer with BTSIZE reloaded and contiguous DADDR 8) Multi Buffer transfer with BTSIZE reloaded and contiguous SADDR 9) Automatic mode channel is stalling BTsize is reloaded 10) Automatic mode BTSIZE, SADDR and DADDR reloaded 11) Automatic mode BTSIZE, SADDR reloaded and DADDR contiguous 0 0 0 0 0 – 0 – – 1 0 – – 1 – 0 1 0 0 1 1 0 0 1 0 LLI LLI LLI LLI LLI LLI CONT LLI LLI REP CONT LLI LLI REP LLI LLI LLI LLI LLI LLI 1 – 0 0 1 REP LLI CONT LLI 1 0 – 1 0 REP CONT LLI LLI 1 0 0 1 1 REP CONT CONT REP 1 1 1 1 1 REP REP REP REP 1 1 0 1 1 REP REP CONT REP Notes: 1. USR means that the register field is manually programmed by the user. 2. CONT means that address are contiguous. 3. REP means that the register field is updated with its previous value. If the transfer is the first one, then the user must manually program the value. 4. Channel stalled is true if the relevant BTC interrupt is not masked. 5. LLI means that the register field is updated with the content of the linked list item. 37.3.3.4 Replay Mode of Channel Registers During automatic replay mode, the channel registers are reloaded with their initial values at the completion of each buffer and the new values used for the new buffer. Depending on the row number in Table 37-1 on page 575, some or all of the DMAC_SADDRx, DMAC_DADDRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers are reloaded from their initial value at the start of a buffer transfer. Contiguous Address Between Buffers In this case, the address between successive buffers is selected to be a continuation from the end of the previous buffer. Enabling the source or destination address to be contiguous between 37.3.3.5 575 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary buffers is a function of DMAC_CTRLAx.SRC_DSCR, DMAC_CFGx.SRC_REP, DMAC_CTRLAx.DST_DSCR and DMAC_CFGx.DST_REP registers. 37.3.3.6 Suspension of Transfers Between buffers At the end of every buffer transfer, an end of buffer interrupt is asserted if: • the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the channel number. Note: The buffer complete interrupt is generated at the completion of the buffer transfer to the destination. At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if: • the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’, when n is the channel number. 37.3.3.7 Ending Multi-buffer Transfers All multi-buffer transfers must end as shown in Row 1 of Table 37-1 on page 575. At the end of every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last buffer and the DMAC transfer is terminated. For rows 9, 10 and 11 of Table 37-1 on page 575, (DMAC_DSCRx = 0 and DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts the DMAC into Row 1 state. For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared) the user must setup the last buffer descriptor in memory such that both LLI.DMAC_CTRLBx.SRC_DSCR and LLI.DMAC_CTRLBx.DST_DSCR are one and LLI.DMAC_DSCRx is set to 0. 576 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.3.4 Programming a Channel Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is used. The different transfer types are shown in Table 37-1 on page 575. The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are enabled. 37.3.4.1 37.3.4.2 Programming Examples Single-buffer Transfer (Row 1) 1. Read the Channel Handler Status Register DMAC_CHSR.ENABLE Field to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register, DMAC_EBCISR. 3. Program the following channel registers: a. Write the starting source address in the DMAC_SADDRx register for channel x. b. c. Write the starting destination address in the DMAC_DADDRx register for channel x. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1 as shown in Table 37-1 on page 575. Program the DMAC_CTRLBx register with both DST_DSCR and SRC_DSCR fields set to one and AUTO field set to 0. d. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers for channel x. For example, in the register, you can program the following: – Set up the transfer characteristics, such as: – Transfer width for the source in the SRC_WIDTH field. – Transfer width for the destination in the DST_WIDTH field. – Source AHB Master interface layer in the SIF field where source resides. – Destination AHB Master Interface layer in the DIF field where destination resides. – Incrementing/decrementing or fixed address for source in SRC_INC field. – Incrementing/decrementing or fixed address for destination in DST_INC field. e. Write the channel configuration information into the DMAC_CFGx register for channel x. f. If source picture-in-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x. g. If destination picture-in-picture mode is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x. 4. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE register is enabled. 5. Once the transfer completes, hardware sets the interrupts and disables the channel. At this time you can either respond to the buffer Complete or Transfer Complete interrupts, or poll for the Channel Handler Status Register (DMAC_CHSR.ENABLE[n]) bit until it is cleared by hardware, to detect when the transfer is complete. 577 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.3.4.3 Multi-buffer Transfer with Linked List for Source and Linked List for Destination (Row 4) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the chain of Linked List Items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory (see Figure 37-5 on page 579) for channel x. For example, in the register, you can program the following: h. Set up the transfer characteristics, such as: – i. Transfer width for the source in the SRC_WIDTH field. – ii. Transfer width for the destination in the DST_WIDTH field. – iii. Source AHB master interface layer in the SIF field where source resides. – iv. Destination AHB master interface layer in the DIF field where destination resides. – v. Incrementing/decrementing or fixed address for source in SRC_INCR field. – vi. Incrementing/decrementing or fixed address for destination DST_INCR field. 3. Write the channel configuration information into the DMAC_CFGx register for channel x. 4. Make sure that the LLI.DMAC_CTRLBx register locations of all LLI entries in memory (except the last) are set as shown in Row 4 of Table 37-1 on page 575. The LLI.DMAC_CTRLBx register of the last Linked List Item must be set as described in Row 1 of Table 37-1. Figure 37-4 on page 574 shows a Linked List example with two list items. 5. Make sure that the LLI.DMAC_DSCRx register locations of all LLI entries in memory (except the last) are non-zero and point to the base address of the next Linked List Item. 6. Make sure that the LLI.DMAC_SADDRx/LLI.DMAC_DADDRx register locations of all LLI entries in memory point to the start source/destination buffer address preceding that LLI fetch. 7. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLI entries in memory are cleared. 8. If source picture-picture mode is enabled (DMAC_CTRLBx.SRC_PIP is enabled), program the DMAC_SPIPx register for channel x. 9. If destination picture-in-picture is enabled (DMAC_CTRLBx.DST_PIP is enabled), program the DMAC_DPIPx register for channel x. 10. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the status register: DMAC_EBCISR. 11. Program the DMAC_CTRLBx, DMAC_CFGx registers according to Row 4 as shown in Table 37-1 on page 575. 12. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 13. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit, where n is the channel number. The transfer is performed. 14. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI. DMAC_DADDRx, LLI.DMAC_DSCRx, LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The DMAC automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLBx and DMAC_CTRLAx channel registers from the DMAC_DSCRx(0). 15. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of the DMAC_CTRLAx register of 578 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE bits have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 16. The DMAC does not wait for the buffer interrupt to be cleared, but continues fetching the next LLI from the memory location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx channel registers. The DMAC transfer continues until the DMAC determines that the DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match described in Row 1 of Table 37-1 on page 575. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. The DMAC transfer might look like that shown in Figure 37-5 on page 579. Figure 37-5. Multi-buffer with Linked List Address for Source and Destination Address of Source Layer Address of Destination Layer Buffer 2 SADDR(2) DADDR(2) Buffer 2 Buffer 1 SADDR(1) DADDR(1) Buffer 1 Buffer 0 SADDR(0) Source Buffers DADDR(0) Buffer 0 Destination Buffers If the user needs to execute a DMAC transfer where the source and destination address are contiguous but the amount of data to be transferred is greater than the maximum buffer size DMAC_CTRLAx.BTSIZE, then this can be achieved using the type of multi-buffer transfer as shown in Figure 37-6 on page 580. 579 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 37-6. Multi-buffer with Linked Address for Source and Destination Buffers are Contiguous Address of Source Layer Address of Destination Layer Buffer 2 DADDR(3) Buffer 2 SADDR(3) Buffer 2 SADDR(2) Buffer 1 SADDR(1) Buffer 0 SADDR(0) Source Buffers Destination Buffers Buffer 0 DADDR(0) Buffer 1 DADDR(1) Buffer 2 DADDR(2) The DMAC transfer flow is shown in Figure 37-7 on page 581. 580 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 37-7. DMAC Transfer Flow for Source and Destination Linked List Address Channel enabled by software LLI Fetch Hardware reprograms SADDRx, DADDRx, CTRLA/Bx, DSCRx DMAC buffer transfer Writeback of HDMA_CTRLAx register in system memory Buffer Complete interrupt generated here Is HDMA in Row1 of HDMA State Machine Table? no HDMA Transfer Complete interrupt generated here yes Channel Disabled by hardware 37.3.4.4 Multi-buffer Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 10) 1. Read the Channel Enable register to choose an available (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. Program the following channel registers: 581 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary a. Write the starting source address in the DMAC_SADDRx register for channel x. b. c. Write the starting destination address in the DMAC_DADDRx register for channel x. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 10 as shown in Table 37-1 on page 575. Program the DMAC_DSCRx register with ‘0’. d. Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx register for channel x. For example, in the register, you can program the following: – Set up the transfer characteristics, such as: – Transfer width for the source in the SRC_WIDTH field. – Transfer width for the destination in the DST_WIDTH field. – Source AHB master interface layer in the SIF field where source resides. – Destination AHB master interface layer in the DIF field where destination resides. – Incrementing/decrementing or fixed address for source in SRC_INCR field. – Incrementing/decrementing or fixed address for destination in DST_INCR field. e. If source picture-in-picture mode is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. f. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. g. Write the channel configuration information into the DMAC_CFGx register for channel x. Ensure that the reload bits, DMAC_CFGx.SRC_REP, DMAC_CFGx.DST_REP and DMAC_CTRLBx.AUTO are enabled. 3. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where is the channel number. Make sure that bit 0 of the DMAC_EN register is enabled. 4. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx, DMAC_DADDRx and DMAC_CTRLAx registers. Hardware sets the buffer Complete interrupt. The DMAC then samples the row number as shown in Table 37-1 on page 575. If the DMAC is in Row 1, then the DMAC transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either respond to the Buffer Complete or Chained buffer transfer Complete interrupts, or poll for the Channel Enable in the Channel Status Register (DMAC_CHSR.ENABLE[n]) until it is disabled, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed. 5. The DMAC transfer proceeds as follows: a. If interrupts is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel number) hardware sets the buffer complete interrupt when the buffer transfer has completed. It then stalls until the STALLED[n] bit of DMAC_CHSR register is cleared by software, writing ‘1’ to DMAC_CHER.KEEPON[n] bit where n is the channel number. If the next buffer is to be the last buffer in the DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit in the DMAC_CTRLBx.AUTO bit. This put the DMAC into Row 1 as shown in Table 37-1 on page 575. If the next buffer is not the last buffer in the DMAC transfer, then the reload bits should remain enabled to keep the DMAC in Row 4. b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel number), then hardware does not stall until it detects a write to the buffer complete interrupt enable register DMAC_EBCIER register but starts the next buffer transfer immediately. In this case software must clear the automatic mode bit 582 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary in the DMAC_CTRLB to put the DMAC into ROW 1 of Table 37-1 on page 575 before the last buffer of the DMAC transfer has completed. The transfer is similar to that shown in Figure 37-8 on page 583. The DMAC transfer flow is shown in Figure 37-9 on page 584. Figure 37-8. Multi-buffer DMAC Transfer with Source and Destination Address Auto-reloaded Address of Source Layer Address of Destination Layer Block0 Block1 Block2 SADDR DADDR BlockN Source Buffers Destination Buffers 583 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 37-9. DMAC Transfer Flow for Source and Destination Address Auto-reloaded Channel Enabled by software Buffer Transfer Replay mode for SADDRx, DADDRx, CTRLAx, CTRLBx Buffer Complete interrupt generated here HDMA Transfer Complete Interrupt generated here yes Is HDMA in Row1 of HDMA State Machine table? Channel Disabled by hardware no EBCIMR[x]=1? no yes Stall until STALLED is cleared by writing to KEEPON field 37.3.4.5 Multi-buffer Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 6) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the chain of linked list items (otherwise known as buffer descriptors) in memory. Write the control information in the LLI.DMAC_CTRLAx and DMAC_CTRLBx registers location of the buffer descriptor for each LLI in memory for channel x. For example, in the register you can program the following: c. Set up the transfer characteristics, such as: – i. Transfer width for the source in the SRC_WIDTH field. – ii. Transfer width for the destination in the DST_WIDTH field. – iii. Source AHB master interface layer in the SIF field where source resides. – iv. Destination AHB master interface layer in the DIF field where destination resides. – v. Incrementing/decrementing or fixed address for source in SRC_INCR field. – vi. Incrementing/decrementing or fixed address for destination DST_INCR field. 3. Write the starting source address in the DMAC_SADDRx register for channel x. Note: The values in the LLI.DMAC_SADDRx register locations of each of the Linked List Items (LLIs) setup up in memory, although fetched during a LLI fetch, are not used. 584 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 4. Write the channel configuration information into the DMAC_CFGx register for channel x. 5. Make sure that the LLI.DMAC_CTRLBx register locations of all LLIs in memory (except the last) are set as shown in Row 6 of Table 37-1 on page 575 while the LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in Row 1 of Table 37-1. Figure 37-4 on page 574 shows a Linked List example with two list items. 6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_DADDRx register location of all LLIs in memory point to the start destination buffer address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTRLA register locations of all LLIs in memory is cleared. 9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register for channel x. 11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the DMAC_EBCISR register. 12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 6 as shown in Table 37-1 on page 575. 13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where n is the channel number. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled. 15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI. DMAC_LLPx LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx registers are fetched. The LLI.DMAC_SADDRx register although fetched is not used. 16. The DMAC_CTRLAx register is written out to system memory. The DMAC_CTRLAx register is written out to the same location on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out, because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAx.DONE fields have been updated by hardware within the DMAC. The LLI.DMAC_CTRLAx.DONE bit is asserted to indicate buffer completion Therefore, software can poll the LLI.DMAC_CTRLAx.DONE field of the DMAC_CTRLAx register in the LLi to ascertain when a buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead poll the LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the polled LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLA.DONE bit was cleared at the start of the transfer. 17. The DMAC reloads the DMAC_SADDRx register from the initial value. Hardware sets the buffer complete interrupt. The DMAC samples the row number as shown in Table 37-1 on page 575. If the DMAC is in Row 1, then the DMAC transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. You can either respond to the Buffer Complete or Chained buffer Transfer Complete interrupts, or poll for the Channel Enable (DMAC_CHSR.ENABLE) bit until it is cleared by hardware, to 585 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary detect when the transfer is complete. If the DMAC is not in Row 1 as shown in Table 371 on page 575, the following step is performed. 18. The DMAC fetches the next LLI from memory location pointed to by the current DMAC_DSCRx register, and automatically reprograms the DMAC_DADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. Note that the DMAC_SADDRx is not re-programmed as the reloaded value is used for the next DMAC buffer transfer. If the next buffer is the last buffer of the DMAC transfer then the DMAC_CTRLBx and DMAC_DSCRx registers just fetched from the LLI should match Row 1 of Table 37-1 on page 575. The DMAC transfer might look like that shown in Figure 37-10 on page 586. Figure 37-10. Multi-buffer DMAC Transfer with Source Address Auto-reloaded and Linked List Destination Address Address of Source Layer Address of Destination Layer Buffer0 DADDR(0) Buffer1 DADDR(1) SADDR Buffer2 DADDR(2) BufferN DADDR(N) Source Buffers Destination Buffers The DMAC Transfer flow is shown in Figure 37-11 on page 587. 586 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 37-11. DMAC Transfer Flow for Replay Mode at Source and Linked List Destination Address Channel Enabled by software LLI Fetch Hardware reprograms DADDRx, CTRLAx, CTRLBx, DSCRx DMA buffer transfer Writeback of control status information in LLI Reload SADDRx Buffer Complete interrupt generated here yes Is HDMA in Row1 of HDMA State Machine Table? HDMA Transfer Complete interrupt generated here Channel Disabled by hardware no 37.3.4.6 Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 11) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Clear any pending interrupts on the channel from the previous DMAC transfer by reading to the Interrupt Status Register. 3. Program the following channel registers: a. Write the starting source address in the DMAC_SADDRx register for channel x. b. c. Write the starting destination address in the DMAC_DADDRx register for channel x. Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 11 as shown in Table 37-1 on page 575. Program the DMAC_DSCRx register with ‘0’. DMAC_CTRLBx.AUTO field is set to ‘1’ to enable automatic mode support. d. Write the control information for the DMAC transfer in the DMAC_CTRLBx and DMAC_CTRLAx register for channel x. For example, in this register, you can program the following: – Set up the transfer characteristics, such as: – Transfer width for the source in the SRC_WIDTH field. – Transfer width for the destination in the DST_WIDTH field. 587 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary – Source AHB master interface layer in the SIF field where source resides. – Destination AHB master interface master layer in the DIF field where destination resides. – Incrementing/decrementing or fixed address for source in SRC_INCR field. – Incrementing/decrementing or fixed address for destination in DST_INCR field. e. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. f. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP), program the DMAC_DPIPx register for channel x. g. Write the channel configuration information into the DMAC_CFGx register for channel x. 4. After the DMAC channel has been programmed, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit where n is the channel number. Make sure that bit 0 of the DMAC_EN.ENABLE register is enabled. 5. When the buffer transfer has completed, the DMAC reloads the DMAC_SADDRx register. The DMAC_DADDRx register remains unchanged. Hardware sets the buffer complete interrupt. The DMAC then samples the row number as shown in Table 37-1 on page 575. If the DMAC is in Row 1, then the DMAC transfer has completed. Hardware sets the transfer complete interrupt and disables the channel. So you can either respond to the Buffer Complete or Transfer Complete interrupts, or poll for ENABLE field in the Channel Status Register (DMAC_CHSR.ENABLE[n] bit) until it is cleared by hardware, to detect when the transfer is complete. If the DMAC is not in Row 1, the next step is performed. 6. The DMAC transfer proceeds as follows: a. If the buffer complete interrupt is un-masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel number) hardware sets the buffer complete interrupt when the buffer transfer has completed. It then stalls until STALLED[n] bit of DMAC_CHSR is cleared by writing in the KEEPON[n] field of DMAC_CHER register where n is the channel number. If the next buffer is to be the last buffer in the DMAC transfer, then the buffer complete ISR (interrupt service routine) should clear the automatic mode bit, DMAC_CTRLBx.AUTO. This puts the DMAC into Row 1 as shown in Table 371 on page 575. If the next buffer is not the last buffer in the DMAC transfer then the automatic transfer mode bit should remain enabled to keep the DMAC in Row 11 as shown in Table 37-1 on page 575. b. If the buffer complete interrupt is masked (DMAC_EBCIMR.BTC[x] = ‘1’, where x is the channel number) then hardware does not stall until it detects a write to the buffer transfer completed interrupt enable register but starts the next buffer transfer immediately. In this case software must clear the automatic mode bit, DMAC_CTRLBx.AUTO, to put the device into ROW 1 of Table 37-1 on page 575 before the last buffer of the DMAC transfer has completed. The transfer is similar to that shown in Figure 37-12 on page 589. The DMAC Transfer flow is shown in Figure 37-13 on page 590. 588 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 37-12. Multi-buffer Transfer with Source Address Auto-reloaded and Contiguous Destination Address Address of Source Layer Address of Destination Layer Buffer2 DADDR(2) Buffer1 DADDR(1) Buffer0 SADDR DADDR(0) Source Buffers Destination Buffers 589 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 37-13. DMAC Transfer Replay Mode is Enabled for the Source and Contiguous Destination Address Channel Enabled by software Buffer Transfer Replay mode for SADDRx, Contiguous mode for DADDRx CTRLAx, CTRLBx Buffer Complete interrupt generated here Buffer Transfer Complete interrupt generated here Is HDMA in Row1of HDMA State Machine Table? yes Channel Disabled by hardware no no DMA_EBCIMR[x]=1? yes Stall until STALLED field is cleared by software writing KEEPON Field 37.3.4.7 Multi-buffer DMAC Transfer with Linked List for Source and Contiguous Destination Address (Row 2) 1. Read the Channel Enable register to choose a free (disabled) channel. 2. Set up the linked list in memory. Write the control information in the LLI.DMAC_CTRLAx and LLI.DMAC_CTRLBx register location of the buffer descriptor for each LLI in memory for channel x. For example, in the register, you can program the following: c. Set up the transfer characteristics, such as: – i. Transfer width for the source in the SRC_WIDTH field. – ii. Transfer width for the destination in the DST_WIDTH field. – iii. Source AHB master interface layer in the SIF field where source resides. – iv. Destination AHB master interface layer in the DIF field where destination resides. – v. Incrementing/decrementing or fixed address for source in SRC_INCR field. – vi. Incrementing/decrementing or fixed address for destination DST_INCR field. 590 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 3. Write the starting destination address in the DMAC_DADDRx register for channel x. Note: The values in the LLI.DMAC_DADDRx register location of each Linked List Item (LLI) in memory, although fetched during an LLI fetch, are not used. 4. Write the channel configuration information into the DMAC_CFGx register for channel x. 5. Make sure that all LLI.DMAC_CTRLBx register locations of the LLI (except the last) are set as shown in Row 2 of Table 37-1 on page 575, while the LLI.DMAC_CTRLBx register of the last Linked List item must be set as described in Row 1 of Table 37-1. Figure 37-4 on page 574 shows a Linked List example with two list items. 6. Make sure that the LLI.DMAC_DSCRx register locations of all LLIs in memory (except the last) are non-zero and point to the next Linked List Item. 7. Make sure that the LLI.DMAC_SADDRx register location of all LLIs in memory point to the start source buffer address proceeding that LLI fetch. 8. Make sure that the LLI.DMAC_CTRLAx.DONE field of the LLI.DMAC_CTRLAx register locations of all LLIs in memory is cleared. 9. If source picture-in-picture is enabled (DMAC_CTRLBx.SPIP is enabled), program the DMAC_SPIPx register for channel x. 10. If destination picture-in-picture is enabled (DMAC_CTRLBx.DPIP is enabled), program the DMAC_DPIPx register for channel x. 11. Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status register. 12. Program the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx registers according to Row 2 as shown in Table 37-1 on page 575 13. Program the DMAC_DSCRx register with DMAC_DSCRx(0), the pointer to the first Linked List item. 14. Finally, enable the channel by writing a ‘1’ to the DMAC_CHER.ENABLE[n] bit. The transfer is performed. Make sure that bit 0 of the DMAC_EN register is enabled. 15. The DMAC fetches the first LLI from the location pointed to by DMAC_DSCRx(0). Note: The LLI.DMAC_SADDRx, LLI.DMAC_DADDRx, LLI.DMAC_DSCRx and LLI.DMAC_CTRLA/Bx registers are fetched. The LLI.DMAC_DADDRx register location of the LLI although fetched is not used. The DMAC_DADDRx register in the DMAC remains unchanged. 16. Once the buffer of data is transferred, the DMAC_CTRLAx register is written out to system memory at the same location and on the same layer (DMAC_DSCRx.DSCR_IF) where it was originally fetched, that is, the location of the DMAC_CTRLAx register of the linked list item fetched prior to the start of the buffer transfer. Only DMAC_CTRLAx register is written out because only the DMAC_CTRLAx.BTSIZE and DMAC_CTRLAX.DONE fields have been updated by DMAC hardware. Additionally, the DMAC_CTRLAx.DONE bit is asserted when the buffer transfer has completed. Note: Do not poll the DMAC_CTRLAx.DONE bit in the DMAC memory map. Instead, poll the LLI.DMAC_CTRLAx.DONE bit in the LLI for that buffer. If the poll LLI.DMAC_CTRLAx.DONE bit is asserted, then this buffer transfer has completed. This LLI.DMAC_CTRLAx.DONE bit was cleared at the start of the transfer. 17. The DMAC does not wait for the buffer interrupt to be cleared, but continues and fetches the next LLI from the memory location pointed to by current DMAC_DSCRx register and automatically reprograms the DMAC_SADDRx, DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx channel registers. The DMAC_DADDRx register is left unchanged. The DMAC transfer continues until the DMAC samples the DMAC_CTRLAx, DMAC_CTRLBx and DMAC_DSCRx registers at the end of a buffer transfer match that described in Row 1 of Table 37-1 on page 575. The DMAC then knows that the previous buffer transferred was the last buffer in the DMAC transfer. 591 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary The DMAC transfer might look like that shown in Figure 37-14 on page 592 Note that the destination address is decrementing. Figure 37-14. DMAC Transfer with Linked List Source Address and Contiguous Destination Address Address of Source Layer Address of Destination Layer Buffer 2 SADDR(2) Buffer 2 DADDR(2) Buffer 1 SADDR(1) Buffer 1 DADDR(1) Buffer 0 Buffer 0 SADDR(0) DADDR(0) Source Buffers Destination Buffers The DMAC transfer flow is shown in Figure 37-15 on page 593. 592 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 37-15. DMAC Transfer Flow for Linked List Source Address and Contiguous Destination Address Channel Enabled by software LLI Fetch Hardware reprograms SADDRx, CTRLAx,CTRLBx, DSCRx HDMA buffer transfer Writeback of control information of LLI Buffer Complete interrupt generated here Is HDMA in Row 1 ? no HDMA Transfer Complete interrupt generated here yes Channel Disabled by hardware 37.3.5 Disabling a Channel Prior to Transfer Completion Under normal operation, software enables a channel by writing a ‘1’ to the Channel Handler Enable Register, DMAC_CHER.ENABLE[n], and hardware disables a channel on transfer completion by clearing the DMAC_CHSR.ENABLE[n] register bit. The recommended way for software to disable a channel without losing data is to use the SUSPEND[n] bit in conjunction with the EMPTY[n] bit in the Channel Handler Status Register. 593 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 1. If software wishes to disable a channel n prior to the DMAC transfer completion, then it can set the DMAC_CHER.SUSPEND[n] bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the channel FIFO receives no new data. 2. Software can now poll the DMAC_CHSR.EMPTY[n] bit until it indicates that the channel n FIFO is empty, where n is the channel number. 3. The DMAC_CHER.ENABLE[n] bit can then be cleared by software once the channel n FIFO is empty, where n is the channel number. When DMAC_CTRLAx.SRC_WIDTH is less than DMAC_CTRLAx.DST_WIDTH and the DMAC_CHSRx.SUSPEND[n] bit is high, the DMAC_CHSRx.EMPTY[n] is asserted once the contents of the FIFO do not permit a single word of DMAC_CTRLAx.DST_WIDTH to be formed. However, there may still be data in the channel FIFO but not enough to form a single transfer of DMAC_CTLx.DST_WIDTH width. In this configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the destination peripheral. It is permitted to remove the channel from the suspension state by writing a ‘1’ to the DMAC_CHER.RESUME[n] field register. The DMAC transfer completes in the normal manner. n defines the channel number. 37.3.5.1 Abnormal Transfer Termination A DMAC transfer may be terminated abruptly by software by clearing the channel enable bit, DMAC_CHDR.ENABLE[n] where n is the channel number. This does not mean that the channel is disabled immediately after the DMAC_CHSR.ENABLE[n] bit is cleared over the APB interface. Consider this as a request to disable the channel. The DMAC_CHSR.ENABLE[n] must be polled and then it must be confirmed that the channel is disabled by reading back 0. Software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register (DMAC_EN.ENABLE bit). Again, this does not mean that all channels are disabled immediately after the DMAC_EN.ENABLE is cleared over the APB slave interface. Consider this as a request to disable all channels. The DMAC_CHSR.ENABLE must be polled and then it must be confirmed that all channels are disabled by reading back ‘0’. Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals, such as a source FIFO, this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral upon request and is not lost. 37.4 DMAC Software Requirements • There must not be any write operation to Channel registers in an active channel after the channel enable is made HIGH. If any channel parameters must be reprogrammed, this can only be done after disabling the DMAC channel. • You must program the DMAC_SADDRx and DMAC_DADDRx channel registers with a byte, half-word and word aligned address depending on the source width and destination width. • After the software disables a channel by writing into the channel disable register, it must reenable the channel only after it has polled a 0 in the corresponding channel enable status register. This is because the current AHB Burst must terminate properly. • If you program the BTSIZE field in the DMAC_CTRLA, as zero, and the DMAC is defined as the flow controller, then the channel is automatically disabled. • When AUTO Field is set to TRUE, then the BTSIZE Field is automatically reloaded from its previous value. BTSIZE must be initialized to a non zero value if the first transfer is initiated 594 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary with AUTO field set to TRUE even if LLI mode is enabled because the LLI fetch operation will not update this field. 595 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5 DMA Controller (DMAC) User Interface Register Mapping Register DMAC Global Configuration Register DMAC Enable Register Reserved Reserved Reserved Reserved DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Enable register. DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Interrupt Disable register. DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Mask Register. DMAC Error, Chained Buffer transfer completed and Buffer transfer completed Status Register. DMAC Channel Handler Enable Register DMAC Channel Handler Disable Register DMAC Channel Handler Status Register Reserved Reserved DMAC Channel 0 Source Address Register DMAC Channel 0 Destination Address Register DMAC Channel 0 Descriptor Address Register DMAC Channel 0 Control A Register DMAC Channel 0 Control B Register DMAC Channel 0 Configuration Register DMAC Channel 0 Source Picture in Picture Configuration Register DMAC Channel 0 Destination Picture in Picture Configuration Register Reserved Reserved DMAC Channel 1 Source Address Register DMAC Channel 1 Destination Address Register DMAC Channel 1 Descriptor Address Register DMAC Channel 1 Control A Register DMAC Channel 1 Control B Register Name DMAC_GCFG DMAC_EN – – – – DMAC_EBCIER DMAC_EBCIDR DMAC_EBCIMR DMAC_EBCISR DMAC_CHER DMAC_CHDR DMAC_CHSR – – DMAC_SADDR0 DMAC_DADDR0 DMAC_DSCR0 DMAC_CTRLA0 DMAC_CTRLB0 DMAC_CFG0 DMAC_SPIP0 DMAC_DPIP0 – – DMAC_SADDR1 DMAC_DADDR1 DMAC_DSCR1 DMAC_CTRLA1 DMAC_CTRLB1 Access Read/Write Read/Write – – – – Write-only Write-only Read-only Read-only Write-only Write-only Read-only – – Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write Read/Write – – Read/Write Read/Write Read/Write Read/Write Read/Write 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x01000000 0x0 0x0 – – 0x0 0x0 – – 0x00FF0000 – – Reset State 0x10 0x0 – – – – – – Table 37-2. Offset 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C 0x020 0x024 0x028 0x02C 0x030 0x034 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 0x054 0x058 0x05C 0x060 0x064 0x068 0x06C 0x070 0x074 596 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Table 37-2. Offset 0x078 0x07C 0x080 Register Mapping Register DMAC Channel 1 Configuration Register DMAC Channel 1 Source Picture in Picture Configuration Register DMAC Channel 1 Destination Picture in Picture Configuration Register Name DMAC_CFG1 DMAC_SPIP1 DMAC_DPIP1 Access Read/Write Read/Write Read/Write Reset State 0x01000000 0x0 0x0 597 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.1 DMAC Global Configuration Register Name: DMAC_GCFG Access: Read/Write Reset Value: 0x00000010 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 ARB_CFG 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 IF0_BIGEND • IF0_BIGEND 0: AHB-Lite Interface 0 is little endian. 1: AHB-Lite Interface 0 is big endian. • ARB_CFG 0: Fixed priority arbiter. 1: Modified round robin arbiter. 598 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.2 DMAC Enable Register Name: DMAC_EN Access: Read/Write Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 – 8 – 0 ENABLE • ENABLE 0: DMA Controller is disabled. 1: DMA Controller is enabled. 599 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.3 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register Name: DMAC_EBCIER Access: Write-only Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 ERR1 9 CBTC1 1 BTC1 24 – 16 ERR0 8 CBTC0 0 BTC0 • BTC[1:0] Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the BTC field to enable the interrupt for channel i. • CBTC[1:0] Chained Buffer Transfer Completed Interrupt Enable Register. Set the relevant bit in the CBTC field to enable the interrupt for channel i. • ERR[1:0] Access Error Interrupt Enable Register. Set the relevant bit in the ERR field to enable the interrupt for channel i. 600 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.4 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register Name: DMAC_EBCIDR Access: Write-only Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 ERR1 9 CBTC1 1 BTC1 24 – 16 ERR0 8 CBTC0 0 BTC0 • BTC[1:0] Buffer transfer completed Disable Interrupt Register. When set, a bit of the BTC field disables the interrupt from the relevant DMAC channel. • CBTC[1:0] Chained Buffer transfer completed Disable Register. When set, a bit of the CBTC field disables the interrupt from the relevant DMAC channel. • ERR[1:0] Access Error Interrupt Disable Register. When set, a bit of the ERR field disables the interrupt from the relevant DMAC channel. 601 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.5 DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register Name: DMAC_EBCIMR Access: Read-only Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 ERR1 9 CBTC1 1 BTC1 24 – 16 ERR0 8 CBTC0 0 BTC0 • BTC[1:0] 0: Buffer Transfer completed interrupt is disabled for channel i. 1: Buffer Transfer completed interrupt is enabled for channel i. • CBTC[1:0] 0: Chained Buffer Transfer interrupt is disabled for channel i. 1: Chained Buffer Transfer interrupt is enabled for channel i. • ERR[1:0] 0: Transfer Error Interrupt is disabled for channel i. 1: Transfer Error Interrupt is enabled for channel i. 602 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.6 DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register Name: DMAC_EBCISR Access: Read-only Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 ERR1 9 CBTC1 1 BTC1 24 – 16 ERR0 8 CBTC0 0 BTC0 • BTC[1:0] When BTC[i] is set, Channel i buffer transfer has terminated. • CBTC[1:0] When CBTC[i] is set, Channel i Chained buffer has terminated. LLI Fetch operation is disabled. • ERR[1:0] When ERR[i] is set, Channel i has detected an AHB Read or Write Error Access. 603 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.7 DMAC Channel Handler Enable Register Name: DMAC_CHER Access: Write-only Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 KEEP1 17 – 9 SUSP1 1 ENA1 24 KEEP0 16 – 8 SUSP0 0 ENA0 • ENA[1:0] When set, a bit of the ENA field enables the relevant channel. • SUSP[1:0] When set, a bit of the SUSP field freezes the relevant channel and its current context. • KEEP[1:0] When set, a bit of the KEEP field resumes the current channel from an automatic stall state. 604 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.8 DMAC Channel Handler Disable Register Name: DMAC_CHDR Access: Write-only Reset Value: 0x00000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 RES1 1 DIS1 24 – 16 – 8 RES0 0 DIS0 • DIS[1:0] Write one to this field to disable the relevant DMAC Channel. The content of the FIFO is lost and the current AHB access is terminated. Software must poll DIS[1:0] field in the DMAC_CHSR register to be sure that the channel is disabled. • RES[1:0] Write one to this field to resume the channel transfer restoring its context. 605 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.9 DMAC Channel Handler Status Register Name: DMAC_CHSR Access: Read-only Reset Value: 0x00FF0000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 STAL1 17 EMPT1 9 SUSP1 1 ENA1 24 STAL0 16 EMPT0 8 SUSP0 0 ENA0 • ENA[1:0] A one in any position of this field indicates that the relevant channel is enabled. • SUSP[1:0] A one in any position of this field indicates that the channel transfer is suspended. • EMPT[1:0] A one in any position of this field indicates that the relevant channel is empty. • STAL[1:0] A one in any position of this field indicates that the relevant channel is stalling. 606 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.10 DMAC Channel x [x = 0..1] Source Address Register Name: DMAC_SADDRx [x = 0..1] Access: Read/Write Reset Value: 0x00000000 31 30 29 28 SADDRx 23 22 21 20 SADDRx 15 14 13 12 SADDRx 7 6 5 4 SADDRx 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 • SADDRx Channel x source address. This register must be aligned with the source transfer width. 37.5.11 DMAC Channel x [x = 0..1] Destination Address Register Name: DMAC_DADDRx [x = 0..1] Access: Read/Write Reset Value: 0x00000000 31 30 29 28 DADDRx 23 22 21 20 DADDRx 15 14 13 12 DADDRx 7 6 5 4 DADDRx 3 2 1 0 11 10 9 8 19 18 17 16 27 26 25 24 • DADDRx Channel x destination address. This register must be aligned with the destination transfer width. 607 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.12 DMAC Channel x [x = 0..1] Descriptor Address Register Name: DMAC_DSCRx [x = 0..1] Access: Read/Write Reset Value: 0x00000000 31 30 29 28 DSCRx 23 22 21 20 DSCRx 15 14 13 12 DSCRx 7 6 5 DSCRx 4 3 2 1 DSCRx_IF 0 11 10 9 8 19 18 17 16 27 26 25 24 • DSCRx_IF 00: The Buffer Transfer descriptor is fetched via AHB-Lite Interface 0. 01: Reserved. 10: Reserved. 11: Reserved. • DSCRx Buffer Transfer descriptor address. This address is word aligned. 608 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.13 DMAC Channel x [x = 0..1] Control A Register Name: DMAC_CTRLAx [x = 0..1] Access: Read/Write Reset Value: 0x00000000 31 DONE 23 – 15 30 – 22 – 14 29 DST_WIDTH 21 – 13 20 – 12 BTSIZE 7 6 5 4 BTSIZE 3 2 1 0 28 27 – 19 – 11 26 – 18 – 10 25 SRC_WIDTH 17 – 9 16 – 8 24 • BTSIZE Buffer Transfer Size. The transfer size relates to the number of transfers to be performed, that is, for writes it refers to the number of source width transfers to perform when DMAC is flow controller. For Reads, BTSIZE refers to the number of transfers completed on the Source Interface. When this field is set to 0, the DMAC module is automatically disabled when the relevant channel is enabled. • SRC_WIDTH SRC_WIDTH 00 01 1X Single Transfer Size BYTE HALF-WORD WORD • DST_WIDTH DST_WIDTH 00 01 1X Single Transfer Size BYTE HALF-WORD WORD • DONE 0: The transfer is performed. 1: If SOD field of DMAC_CFG register is set to true, then the DMAC is automatically disabled when an LLI updates the content of this register. The DONE field is written back to memory at the end of the transfer. 609 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.14 DMAC Channel x [x = 0..1] Control B Register Name: DMAC_CTRLBx [x = 0..1] Access: Read/Write Reset Value: 0x00000000 31 AUTO 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 DST_INCR 21 – 13 20 DST_DSCR 12 DST_PIP 4 DIF 28 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 SRC_INCR 17 – 9 – 1 SIF 16 SRC_DSCR 8 SRC_PIP 0 24 5 • SIF Source Interface Selection Field. 00: The source transfer is done via AHB-Lite Interface 0. 01: Reserved. 10: Reserved. 11: Reserved. • DIF Destination Interface Selection Field. 00: The destination transfer is done via AHB-Lite Interface 0. 01: Reserved. 10: Reserved. 11: Reserved. • SRC_PIP 0: Picture-in-Picture mode is disabled. The source data area is contiguous. 1: Picture-in-Picture mode is enabled. When the source PIP counter reaches the programmable boundary, the address is automatically increment of a user defined amount. • DST_PIP 0: Picture-in-Picture mode is disabled. The Destination data area is contiguous. 1: Picture-in-Picture mode is enabled. When the Destination PIP counter reaches the programmable boundary the address is automatically incremented by a user-defined amount. • SRC_DSCR 0: Source address is updated when the descriptor is fetched from the memory. 1: Buffer Descriptor Fetch operation is disabled for the source. 610 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • DST_DSCR 0: Destination address is updated when the descriptor is fetched from the memory. 1: Buffer Descriptor Fetch operation is disabled for the destination. • SRC_INCR SRC_INCR 00 01 10 Type of addressing mode INCREMENTING DECREMENTING FIXED • DST_INCR DST_INCR 00 01 10 Type of addressing scheme INCREMENTING DECREMENTING FIXED • AUTO Automatic multiple buffer transfer is enabled. When set, this bit enables replay mode or contiguous mode when several buffers are transferred. 611 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.15 DMAC Channel x [x = 0..1] Configuration Register Name: DMAC_CFGx [x = 0..1] Access: Read/Write Reset Value: 0x0100000000 31 – 23 – 15 – 7 – 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 DST_REP 4 – 27 – 19 – 11 – 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 – 1 – 24 – 16 SOD 8 SRC_REP 0 – • SRC_REP 0: When automatic mode is activated, source address is contiguous between two buffers. 1: When automatic mode is activated, the source address and the control register are reloaded from previous transfer. • DST_REP 0: When automatic mode is activated, destination address is contiguous between two buffers. 1: When automatic mode is activated, the destination and the control register are reloaded from the previous transfer. • SOD 0: STOP ON DONE disabled, the descriptor fetch operation ignores DONE Field of CTRLA register. 1: STOP ON DONE activated, the DMAC module is automatically disabled if DONE FIELD is set to 1. 612 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.16 DMAC Channel x [x = 0..1] Source Picture in Picture Configuration Register Name: DMAC_SPIPx [x = 0..1] Access: Read/Write Reset Value: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 27 – 26 – 18 25 24 SPIP_BOUNDARY 17 16 20 19 SPIP_BOUNDARY 12 SPIP_HOLE 11 15 14 13 10 9 8 7 6 5 4 SPIP_HOLE 3 2 1 0 • SPIP_HOLE This field indicates the value to add to the address when the programmable boundary has been reached. • SPIP_BOUNDARY This field indicates the number of source transfers to perform before the automatic address increment operation. 613 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 37.5.17 DMAC Channel x [x = 0..1] Destination Picture in Picture Configuration Register Name: DMAC_DPIPx [x = 0..1] Access: Read/Write Reset Value: 0x00000000 31 – 23 30 – 22 29 – 21 28 – 27 – 26 – 18 25 24 DPIP_BOUNDARY 17 16 20 19 DPIP_BOUNDARY 12 DPIPE_HOLE 11 15 14 13 10 9 8 7 6 5 4 DPIPE_HOLE 3 2 1 0 • DPIP_HOLE This field indicates the value to add to the address when the programmable boundary has been reached. • DPIP_BOUNDARY This field indicates the number of source transfers to perform before the automatic address increment operation. 614 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 38. MultiMedia Card Interface (MCI) 38.1 Description The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. 615 6289C–ATARM–28-May-09 38.2 Block Diagram Figure 38-1. Block Diagram APB Bridge PDC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCI Interface PIO MCCDB(1) MCDB0(1) MCDB1(1) MCDB2(1) Interrupt Control MCDB3(1) MCI Interrupt Note: 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 616 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 38.3 Application Block Diagram Figure 38-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 MMC 9 SDCard 38.4 Pin Name List I/O Lines Description Pin Description Command/response Clock Data 0..3 of Slot A Data 0..3 of Slot B Type(1) I/O/PP/OD I/O I/O/PP I/O/PP Comments CMD of an MMC or SDCard/SDIO CLK of an MMC or SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO DAT0 of an MMC DAT[0..3] of an SD Card/SDIO Table 38-1. Pin Name(2) MCCDA/MCCDB MCCK MCDA0 - MCDA3 MCDB0 - MCDB3 Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. 38.5 38.5.1 Product Dependencies I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. 38.5.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock. 617 6289C–ATARM–28-May-09 38.5.3 Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. 38.6 Bus Topology Figure 38-3. Multimedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 38-2. Pin Number 1 2 3 4 5 6 7 Notes: Bus Topology Name RSV CMD VSS1 VDD CLK VSS2 DAT[0] Type(1) NC I/O/PP/OD S S I/O S I/O/PP Description Not connected Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data 0 MCI Pin Name(2) (Slot z) MCCDz VSS VDD MCCK VSS MCDz0 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. Figure 38-4. MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK 1234567 MMC1 1234567 MMC2 1234567 MMC3 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. 618 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 38-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 38-3. Table 38-3. Pin Number 1 2 3 4 5 6 7 8 9 Notes: SD Memory Card Bus Signals Name CD/DAT[3] CMD VSS1 VDD CLK VSS2 DAT[0] DAT[1] DAT[2] Type (1) Description Card detect/ Data line Bit 3 Command/response Supply voltage ground Supply voltage Clock Supply voltage ground Data line Bit 0 Data line Bit 1 or Interrupt Data line Bit 2 MCI Pin Name(2) (Slot z) MCDz3 MCCDz VSS VDD MCCK VSS MCDz0 MCDz1 MCDz2 I/O/PP PP S S I/O S I/O/PP I/O/PP I/O/PP 1. I: input, O: output, PP: Push Pull, OD: Open Drain. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. Figure 38-6. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 SD CARD Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. 9 619 6289C–ATARM–28-May-09 Figure 38-7. SD Card Bus Connections with Two Slots MCDA0 - MCDA3 MCCK MCCDA 1 2 3 4 5 6 78 1 2 3 4 5 6 78 1234567 MMC1 1 2 3 4 5 6 78 SD CARD 1 MCDB0 - MCDB3 MCCDB Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. Figure 38-8. Mixing MultiMedia and SD Memory Cards with Two Slots MCDA0 MCCDA MCCK 1234567 MMC2 9 9 SD CARD 2 1234567 MMC3 MCDB0 - MCDB3 SD CARD MCCDB Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR register. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 620 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 9 AT91SAM9R64/RL64 Preliminary 38.7 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line. • Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line. • Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 38-4 on page 622. MultiMediaCard bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined: • Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum. • Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See “Data Transfer Operation” on page 623.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 38.7.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping the MCI Clock during read or write access if the internal FIFO is full. This guarantees data integrity, not bandwidth. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification. 621 6289C–ATARM–28-May-09 The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC E Z NID Cycles ****** Z S T CID Content Z Z Z The command ALL_SEND_CID and the fields and values for the MCI_CMDR Control Register are described in Table 38-4 and Table 38-5. Table 38-4. CMD Index ALL_SEND_CID Command Description Type Argument Resp Abbreviation Command Description Asks all cards to send their CID numbers on the CMD line CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Note: bcr means broadcast command with response. Table 38-5. Field Fields and Values for MCI_CMDR Command Register Value 2 (CMD2) 2 (R2: 136 bits response) 0 (not a special command) 1 0 (NID cycles ==> 5 cycles) 0 (No transfer) X (available only in transfer command) X (available only in transfer command) 0 (not a special command) CMDNB (command number) RSPTYP (response type) SPCMD (special command) OPCMD (open drain command) MAXLAT (max latency for command to response) TRCMD (transfer command) TRDIR (transfer direction) TRTYP (transfer type) IOSPCMD (SDIO special command) The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps: • Fill the argument register (MCI_ARGR) with the command argument. • Set the command register (MCI_CMDR) (see Table 38-5). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. 622 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 38-9. Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? Read response if required RETURN ERROR(1) RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). 38.7.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the mode register MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block. Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes. 623 6289C–ATARM–28-May-09 Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time): • Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card continuously transfers (or programs) data blocks until a stop transmission command is received. • Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card transfers (or programs) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (MCI_BLKR). Otherwise the card starts an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 38.7.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 38-10), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. 624 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 38-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card (1) Send SET_BLOCKLEN command No Read with PDC Yes Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght UDPHS_DMA[i].UDPHS_DMASTATUS = AT91C_BASE_UDPHS->UDPHS_DMA[i].UDPHS_DMASTATUS; } // STOP // NON // STOP 41.4.8 41.4.8.1 Handling Transactions with USB V2.0 Device Peripheral Setup Transaction The setup packet is valid in the DPR while RX_SETUP is set. Once RX_SETUP is cleared by the application, the UDPHS accepts the next packets sent over the device endpoint. When a valid setup packet is accepted by the UDPHS: • the UDPHS device automatically acknowledges the setup packet (sends an ACK response) • payload data is written in the endpoint • sets the RX_SETUP interrupt • the BYTE_COUNT field in the UDPHS_EPTSTAx register is updated An endpoint interrupt is generated while RX_SETUP in the UDPHS_EPTSTAx register is not cleared. This interrupt is carried out to the microcontroller if interrupts are enabled for this endpoint. 741 6289C–ATARM–28-May-09 Thus, firmware must detect RX_SETUP polling UDPHS_EPTSTAx or catching an interrupt, read the setup packet in the FIFO, then clear the RX_SETUP bit in the UDPHS_EPTCLRSTA register to acknowledge the setup stage. If STALL_SNT was set to 1, then this bit is automatically reset when a setup token is detected by the device. Then, the device still accepts the setup stage. (See Section 41.4.8.15 “STALL” on page 753). 41.4.8.2 NYET NYET is a High Speed only handshake. It is returned by a High Speed endpoint as part of the PING protocol. High Speed devices must support an improved NAK mechanism for Bulk OUT and control endpoints (except setup stage). This mechanism allows the device to tell the host whether it has sufficient endpoint space for the next OUT transfer (see USB 2.0 spec 8.5.1 NAK Limiting via Ping Flow Control). The NYET/ACK response to a High Speed Bulk OUT transfer and the PING response are automatically handled by hardware in the UDPHS_EPTCTLx register (except when the user wants to force a NAK response by using the NYET_DIS bit). If the endpoint responds instead to the OUT/DATA transaction with an NYET handshake, this means that the endpoint accepted the data but does not have room for another data payload. The host controller must return to using a PING token until the endpoint indicates it has space available. Figure 41-6. NYET Example with Two Endpoint Banks data 0 ACK data 1 NYET PING ACK data 0 NYET PING NACK PING ACK t=0 t = 125 µs t = 250 µs t = 375 µs t = 500 µs t = 625 µs E: empty E': begin to empty F: full Bank 1 E Bank 0 F Bank 1 F Bank 1 F Bank 0 E' Bank 0 E Bank 1 F Bank 0 E Bank 1 F Bank 0 F Bank 1 E' Bank 0 F Bank 1 E Bank 0 F 41.4.8.3 41.4.8.4 Data IN Bulk IN or Interrupt IN Data IN packets are sent by the device during the data or the status stage of a control transfer or during an (interrupt/bulk/isochronous) IN transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. There are three ways for an application to transfer a buffer in several packets over the USB: • packet by packet (see 41.4.8.5 below) • 64 KB (see 41.4.8.5 below) • DMA (see 41.4.8.6 below) 41.4.8.5 Bulk IN or Interrupt IN: Sending a Packet Under Application Control (Device to Host) The application can write one or several banks. 742 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary A simple algorithm can be used by the application to send packets regardless of the number of banks associated to the endpoint. Algorithm Description for Each Packet: • The application waits for TX_PK_RDY flag to be cleared in the UDPHS_EPTSTAx register before it can perform a write access to the DPR. • The application writes one USB packet of data in the DPR through the 64 KB endpoint logical memory window. • The application sets TX_PK_RDY flag in the UDPHS_EPTSETSTAx register. The application is notified that it is possible to write a new packet to the DPR by the TX_PK_RDY interrupt. This interrupt can be enabled or masked by setting the TX_PK_RDY bit in the UDPHS_EPTCTLENB/UDPHS_EPTCTLDIS register. Algorithm Description to Fill Several Packets: Using the previous algorithm, the application is interrupted for each packet. It is possible to reduce the application overhead by writing linearly several banks at the same time. The AUTO_VALID bit in the UDPHS_EPTCTLx must be set by writing the AUTO_VALID bit in the UDPHS_EPTCTLENBx register. The auto-valid-bank mechanism allows the transfer of data (IN and OUT) without the intervention of the CPU. This means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit) is done by hardware. • The application checks the BUSY_BANK_STA field in the UDPHS_EPTSTAx register. The application must wait that at least one bank is free. • The application writes a number of bytes inferior to the number of free DPR banks for the endpoint. Each time the application writes the last byte of a bank, the TX_PK_RDY signal is automatically set by the UDPHS. • If the last packet is incomplete (i.e., the last byte of the bank has not been written) the application must set the TX_PK_RDY bit in the UDPHS_EPTSETSTAx register. The application is notified that all banks are free, so that it is possible to write another burst of packets by the BUSY_BANK interrupt. This interrupt can be enabled or masked by setting the BUSY_BANK flag in the UDPHS_EPTCTLENB and UDPHS_EPTCTLDIS registers. This algorithm must not be used for isochronous transfer. In this case, the ping-pong mechanism does not operate. A Zero Length Packet can be sent by setting just the TX_PKTRDY flag in the UDPHS_EPTSETSTAx register. 41.4.8.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) The UDPHS integrates a DMA host controller. This DMA controller can be used to transfer a buffer from the memory to the DPR or from the DPR to the processor memory under the UDPHS control. The DMA can be used for all transfer types except control transfer. Example DMA configuration: 1. Program UDPHS_DMAADDRESS x with the address of the buffer that should be transferred. 2. Enable the interrupt of the DMA in UDPHS_IEN 3. Program UDPHS_ DMACONTROLx: 743 6289C–ATARM–28-May-09 – Size of buffer to send: size of the buffer to be sent to the host. – END_B_EN: The endpoint can validate the packet (according to the values programmed in the AUTO_VALID and SHRT_PCKT fields of UDPHS_EPTCTLx.) (See “UDPHS Endpoint Control Register” on page 787 and Figure 41-11. Autovalid with DMA) – END_BUFFIT: generate an interrupt when the BUFF_COUNT in UDPHS_DMASTATUSx reaches 0. – CHANN_ENB: Run and stop at end of buffer The auto-valid-bank mechanism allows the transfer of data (IN & OUT) without the intervention of the CPU. This means that bank validation (set TX_PK_RDY or clear the RX_BK_RDY bit) is done by hardware. A transfer descriptor can be used. Instead of programming the register directly, a descriptor should be programmed and the address of this descriptor is then given to UDPHS_DMANXTDSC to be processed after setting the LDNXT_DSC field (Load Next Descriptor Now) in UDPHS_DMACONTROLx register. The structure that defines this transfer descriptor must be aligned. Each buffer to be transferred must be described by a DMA Transfer descriptor (see “UDPHS DMA Channel Transfer Descriptor” on page 798). Transfer descriptors are chained. Before executing transfer of the buffer, the UDPHS may fetch a new transfer descriptor from the memory address pointed by the UDPHS_DMANXTDSCx register. Once the transfer is complete, the transfer status is updated in the UDPHS_DMASTATUSx register. To chain a new transfer descriptor with the current DMA transfer, the DMA channel must be stopped. To do so, INTDIS_DMA and TX_BK_RDY may be set in the UDPHS_EPTCTLENBx register. It is also possible for the application to wait for the completion of all transfers. In this case the LDNXT_DSC field in the last transfer descriptor UDPHS_DMACONTROLx register must be set to 0 and CHANN_ENB set to 1. Then the application can chain a new transfer descriptor. The INTDIS_DMA can be used to stop the current DMA transfer if an enabled interrupt is triggered. This can be used to stop DMA transfers in case of errors. The application can be notified at the end of any buffer transfer (ENB_BUFFIT bit in the UDPHS_DMACONTROLx register). 744 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 41-7. Data IN Transfer for Endpoint with One Bank Prevous Data IN TX Microcontroller Loads Data in FIFO Data is Sent on USB Bus USB Bus Packets Token IN Data IN 1 ACK Token IN NAK Token IN Data IN 2 ACK TX_PK_RDY Flag (UDPHS_EPTSTAx) Set by firmware Cleared by hardware Set by the firmware Interrupt Pending Cleared by hardware Interrupt Pending Payload in FIFO TX_COMPLT Flag (UDPHS_EPTSTAx) Set by hardware DPR access by firmware Cleared by firmware DPR access by hardware Data IN 2 Cleared by firmware FIFO Content Data IN 1 Load in progress Figure 41-8. Data IN Transfer for Endpoint with Two Banks Microcontroller Load Data IN Bank 0 USB Bus Packets Microcontroller Load Data IN Bank 1 UDPHS Device Send Bank 0 Microcontroller Load Data IN Bank 0 UDPHS Device Send Bank 1 Token IN Data IN ACK Token IN Data IN ACK Set by Firmware, Cleared by Hardware Data Payload Written switch to next bank in FIFO Bank 0 Virtual TX_PK_RDY bank 0 (UDPHS_EPTSTAx) Virtual TX_PK_RDY bank 1 (UDPHS_EPTSTAx) Cleared by Hardware Data Payload Fully Transmitted Set by Firmware, Data Payload Written in FIFO Bank 1 Interrupt Pending Set by Hardware Interrupt Cleared by Firmware Set by Hardware TX_COMPLT Flag (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Written by Microcontroller Read by USB Device Written by Microcontroller FIFO (DPR) Bank1 Written by Microcontroller Read by UDPHS Device 745 6289C–ATARM–28-May-09 Figure 41-9. Data IN Followed By Status OUT Transfer at the End of a Control Transfer Device Sends the Last Data Payload to Host USB Bus Packets Device Sends a Status OUT to Host ACK ACK Token IN Data IN ACK Token OUT Data OUT (ZLP) Token OUT Data OUT (ZLP) Interrupt Pending RX_BK_RDY (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware TX_COMPLT (UDPHS_EPTSTAx) Set by Hardware Cleared by Firmware Note: A NAK handshake is always generated at the first status stage token. Figure 41-10. Data OUT Followed by Status IN Transfer Host Sends the Last Data Payload to the Device Device Sends a Status IN to the Host USB Bus Packets Token OUT Data OUT ACK Token IN Data IN ACK Interrupt Pending RX_BK_RDY (UDPHS_EPTSTAx) Set by Hardware TX_PK_RDY (UDPHS_EPTSTAx) Set by Firmware Clear by Hardware Cleared by Firmware Note: Before proceeding to the status stage, the software should determine that there is no risk of extra data from the host (data stage). If not certain (non-predictable data stage length), then the software should wait for a NAK-IN interrupt before proceeding to the status stage. This precaution should be taken to avoid collision in the FIFO. 746 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 41-11. Autovalid with DMA Bank (system) Bank 0 Bank 1 Bank 0 Bank 1 Write write bank 0 write bank 1 bank 1 is full write bank 0 bank 0 is full bank 0 is full Bank 1 Bank 0 IN data 0 IN data 1 IN data 0 Bank (usb) Bank 0 Bank 1 Bank 0 Bank 1 Virtual TX_PK_RDY Bank 0 Virtual TX_PK_RDY Bank 1 TX_PK_RDY (Virtual 0 & Virtual 1) Note: In the illustration above Autovalid validates a bank as full, although this might not be the case, in order to continue processing data and to send to DMA. 41.4.8.7 Isochronous IN Isochronous-IN is used to transmit a stream of data whose timing is implied by the delivery rate. Isochronous transfer provides periodic, continuous communication between host and device. It guarantees bandwidth and low latencies appropriate for telephony, audio, video, etc. If the endpoint is not available (TX_PK_RDY = 0), then the device does not answer to the host. An ERR_FL_ISO interrupt is generated in the UDPHS_EPTSTAx register and once enabled, then sent to the CPU. The STALL_SNT command bit is not used for an ISO-IN endpoint. 41.4.8.8 High Bandwidth Isochronous Endpoint Handling: IN Example For high bandwidth isochronous endpoints, the DMA can be programmed with the number of transactions (BUFF_LENGTH field in UDPHS_DMACONTROLx) and the system should provide 747 6289C–ATARM–28-May-09 the required number of packets per microframe, otherwise, the host will notice a sequencing problem. A response should be made to the first token IN recognized inside a microframe under the following conditions: • If at least one bank has been validated, the correct DATAx corresponding to the programmed Number Of Transactions per Microframe (NB_TRANS) should be answered. In case of a subsequent missed or corrupted token IN inside the microframe, the USB 2.0 Core available data bank(s) that should normally have been transmitted during that microframe shall be flushed at its end. If this flush occurs, an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). • If no bank is validated yet, the default DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). Then, no data bank is flushed at microframe end. • If no data bank has been validated at the time when a response should be made for the second transaction of NB_TRANS = 3 transactions microframe, a DATA1 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if remaining untransmitted banks for that microframe are available at its end, they are flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). • If no data bank has been validated at the time when a response should be made for the last programmed transaction of a microframe, a DATA0 ZLP is answered and underflow is flagged (ERR_FL_ISO is set in UDPHS_EPTSTAx). If and only if the remaining untransmitted data bank for that microframe is available at its end, it is flushed and an error condition is flagged (ERR_FLUSH is set in UDPHS_EPTSTAx). • If at the end of a microframe no valid token IN has been recognized, no data bank is flushed and no error condition is reported. At the end of a microframe in which at least one data bank has been transmitted, if less than NB_TRANS banks have been validated for that microframe, an error condition is flagged (ERR_TRANS is set in UDPHS_EPTSTAx). Cases of Error (in UDPHS_EPTSTAx) • ERR_FL_ISO: There was no data to transmit inside a microframe, so a ZLP is answered by default. • ERR_FLUSH: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of transactions actually validated (TX_BK_RDY) and likewise with the NB_TRANS programmed. • ERR_TRANS: At least one packet has been sent inside the microframe, but the number of token IN received is lesser than the number of programmed NB_TRANS transactions and the packets not requested were not validated. • ERR_FL_ISO + ERR_FLUSH: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN. • ERR_FL_ISO + ERR_TRANS: At least one packet has been sent inside the microframe, but the data has not been validated in time to answer one of the following token IN and the data can be discarded at the microframe end. • ERR_FLUSH + ERR_TRANS: The first token IN has been answered and it was the only one received, a second bank has been validated but not the third, whereas NB_TRANS was waiting for three transactions. 748 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • ERR_FL_ISO + ERR_FLUSH + ERR_TRANS: The first token IN has been treated, the data for the second Token IN was not available in time, but the second bank has been validated before the end of the microframe. The third bank has not been validated, but three transactions have been set in NB_TRANS. 41.4.8.9 41.4.8.10 Data OUT Bulk OUT or Interrupt OUT Like data IN, data OUT packets are sent by the host during the data or the status stage of control transfer or during an interrupt/bulk/isochronous OUT transfer. Data buffers are sent packet by packet under the control of the application or under the control of the DMA channel. Bulk OUT or Interrupt OUT: Receiving a Packet Under Application Control (Host to Device) Algorithm Description for Each Packet: • The application enables an interrupt on RX_BK_RDY. • When an interrupt on RX_BK_RDY is received, the application knows that UDPHS_EPTSTAx register BYTE_COUNT bytes have been received. • The application reads the BYTE_COUNT bytes from the endpoint. • The application clears RX_BK_RDY. Note: If the application does not know the size of the transfer, it may not be a good option to use AUTO_VALID. Because if a zero-length-packet is received, the RX_BK_RDY is automatically cleared by the AUTO_VALID hardware and if the endpoint interrupt is triggered, the software will not find its originating flag when reading the UDPHS_EPTSTAx register. Algorithm to Fill Several Packets: • The application enables the interrupts of BUSY_BANK and AUTO_VALID. • When a BUSY_BANK interrupt is received, the application knows that all banks available for the endpoint have been filled. Thus, the application can read all banks available. If the application doesn’t know the size of the receive buffer, instead of using the BUSY_BANK interrupt, the application must use RX_BK_RDY. 41.4.8.12 Bulk OUT or Interrupt OUT: Sending a Buffer Using DMA (Host To Device) To use the DMA setting, the AUTO_VALID field is mandatory. See 41.4.8.6 Bulk IN or Interrupt IN: Sending a Buffer Using DMA (Device to Host) for more information. DMA Configuration Example: 1. First program UDPHS_DMAADDRESSx with the address of the buffer that should be transferred. 2. Enable the interrupt of the DMA in UDPHS_IEN 3. Program the DMA Channelx Control Register: – Size of buffer to be sent. – END_B_EN: Can be used for OUT packet truncation (discarding of unbuffered packet data) at the end of DMA buffer. 41.4.8.11 749 6289C–ATARM–28-May-09 – END_BUFFIT: Generate an interrupt when BUFF_COUNT in the UDPHS_DMASTATUSx register reaches 0. – END_TR_EN: End of transfer enable, the UDPHS device can put an end to the current DMA transfer, in case of a short packet. – END_TR_IT: End of transfer interrupt enable, an interrupt is sent after the last USB packet has been transferred by the DMA, if the USB transfer ended with a short packet. (Beneficial when the receive size is unknown.) – CHANN_ENB: Run and stop at end of buffer. For OUT transfer, the bank will be automatically cleared by hardware when the application has read all the bytes in the bank (the bank is empty). Note: When a zero-length-packet is received, RX_BK_RDY bit in UDPHS_EPTSTAx is cleared automatically by AUTO_VALID, and the application knows of the end of buffer by the presence of the END_TR_IT. Note: If the host sends a zero-length packet, and the endpoint is free, then the device sends an ACK. No data is written in the endpoint, the RX_BY_RDY interrupt is generated, and the BYTE_COUNT field in UDPHS_EPTSTAx is null. Figure 41-12. Data OUT Transfer for Endpoint with One Bank Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Host Resends the Next Data Payload USB Bus Packets Token OUT Data OUT 1 ACK Token OUT Data OUT 2 NAK Token OUT Data OUT 2 ACK RX_BK_RDY (UDPHS_EPTSTAx) Interrupt Pending Set by Hardware Cleared by Firmware, Data Payload Written in FIFO Data OUT 2 Written by UDPHS Device FIFO (DPR) Content Data OUT 1 Written by UDPHS Device Data OUT 1 Microcontroller Read 750 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 41-13. Data OUT Transfer for an Endpoint with Two Banks Host sends first data payload Microcontroller reads Data 1 in bank 0, Host sends second data payload Microcontroller reads Data 2 in bank 1, Host sends third data payload USB Bus Packets Token OUT Data OUT 1 ACK Token OUT Data OUT 2 ACK Token OUT Data OUT 3 Virtual RX_BK_RDY Bank 0 Interrupt pending Set by Hardware, Data payload written in FIFO endpoint bank 0 Set by Hardware Data Payload written in FIFO endpoint bank 1 Cleared by Firmware Cleared by Firmware Interrupt pending Virtual RX_BK_RDY Bank 1 RX_BK_RDY = (virtual bank 0 | virtual bank 1) (UDPHS_EPTSTAx) FIFO (DPR) Bank 0 Data OUT 1 Write by UDPHS Device FIFO (DPR) Bank 1 Data OUT 1 Read by Microcontroller Data OUT 3 Write in progress Data OUT 2 Write by Hardware Data OUT 2 Read by Microcontroller 41.4.8.13 High Bandwidth Isochronous Endpoint OUT Figure 41-14. Bank Management, Example of Three Transactions per Microframe USB bus Transactions MDATA0 MDATA1 DATA2 MDATA0 MDATA1 DATA2 t=0 RX_BK_RDY Microcontroller FIFO (DPR) Access t = 52.5 µs (40% of 125 µs) t = 125 µs RX_BK_RDY USB line Read Bank 1 Read Bank 2 Read Bank 3 Read Bank 1 USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024 data bytes per microframe. To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The microcontroller (or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average). NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe. If NB_TRANS > 1 then it is High Bandwidth. 751 6289C–ATARM–28-May-09 Example: • If NB_TRANS = 3, the sequence should be either – MData0 – MData0/Data1 – MData0/Data1/Data2 • If NB_TRANS = 2, the sequence should be either – MData0 – MData0/Data1 • If NB_TRANS = 1, the sequence should be – Data0 41.4.8.14 Isochronous Endpoint Handling: OUT Example The user can ascertain the bank status (free or busy), and the toggle sequencing of the data packet for each bank with the UDPHS_EPTSTAx register in the three bit fields as follows: • TOGGLESQ_STA: PID of the data stored in the current bank • CURRENT_BANK: Number of the bank currently being accessed by the microcontroller. • BUSY_BANK_STA: Number of busy bank This is particularly useful in case of a missing data packet. If the inter-packet delay between the OUT token and the Data is greater than the USB standard, then the ISO-OUT transaction is ignored. (Payload data is not written, no interrupt is generated to the CPU.) If there is a data CRC (Cyclic Redundancy Check) error, the payload is, none the less, written in the endpoint. The ERR_CRISO flag is set in UDPHS_EPTSTAx register. If the endpoint is already full, the packet is not written in the DPRAM. The ERR_FL_ISO flag is set in UDPHS_EPTSTAx. If the payload data is greater than the maximum size of the endpoint, then the ERR_OVFLW flag is set. It is the task of the CPU to manage this error. The data packet is written in the endpoint (except the extra data). If the host sends a Zero Length Packet, and the endpoint is free, no data is written in the endpoint, the RX_BK_RDY flag is set, and the BYTE_COUNT field in UDPHS_EPTSTAx register is null. The FRCESTALL command bit is unused for an isochronous endpoint. Otherwise, payload data is written in the endpoint, the RX_BK_RDY interrupt is generated and the BYTE_COUNT in UDPHS_EPTSTAx register is updated. 752 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.4.8.15 STALL STALL is returned by a function in response to an IN token or after the data phase of an OUT or in response to a PING transaction. STALL indicates that a function is unable to transmit or receive data, or that a control pipe request is not supported. • OUT To stall an endpoint, set the FRCESTALL bit in UDPHS_EPTSETSTAx register and after the STALL_SNT flag has been set, set the TOGGLE_SEG bit in the UDPHS_EPTCLRSTAx register. • IN Set the FRCESTALL bit in UDPHS_EPTSETSTAx register. Figure 41-15. Stall Handshake Data OUT Transfer USB Bus Packets Token OUT Data OUT Stall PID FRCESTALL Set by Firmware Cleared by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware Figure 41-16. Stall Handshake Data IN Transfer USB Bus Packets Token IN Stall PID FRCESTALL Set by Firmware Cleared by Firmware Interrupt Pending STALL_SNT Set by Hardware Cleared by Firmware 753 6289C–ATARM–28-May-09 41.4.9 Speed Identification The high speed reset is managed by the hardware. At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset. At the end of the reset process (full or high), the ENDRESET interrupt is generated. Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device. 41.4.10 USB V2.0 High Speed Global Interrupt Interrupts are defined in Section 41.5.3 ”UDPHS Interrupt Enable Register” (UDPHS_IEN) and in Section 41.5.4 ”UDPHS Interrupt Status Register” (UDPHS_INTSTA). Endpoint Interrupts Interrupts are enabled in UDPHS_IEN (see Section 41.5.3 ”UDPHS Interrupt Enable Register”) and individually masked in UDPHS_EPTCTLENBx (see Section 41.5.17 ”UDPHS Endpoint Control Enable Register”). . Table 41-4. SHRT_PCKT BUSY_BANK NAK_OUT NAK_IN/ERR_FLUSH STALL_SNT/ERR_CRISO/ERR_NB_TRA RX_SETUP/ERR_FL_ISO TX_PK_RD /ERR_TRANS TX_COMPLT RX_BK_RDY ERR_OVFLW MDATA_RX DATAX_RX 41.4.11 Endpoint Interrupt Source Masks Short Packet Interrupt Busy Bank Interrupt NAKOUT Interrupt NAKIN/Error Flush Interrupt Stall Sent/CRC error/Number of Transaction Error Interrupt Received SETUP/Error Flow Interrupt TX Packet Read/Transaction Error Interrupt Transmitted IN Data Complete Interrupt Received OUT Data Interrupt Overflow Error Interrupt MDATA Interrupt DATAx Interrupt 754 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 41-17. UDPHS Interrupt Control Interface (UDPHS_IEN) DET_SUSPD MICRO_SOF USB Global IT Sources IEN_SOF ENDRESET WAKE_UP ENDOFRSM UPSTR_RES Global IT mask Global IT sources (UDPHS_EPTCTLENBx) SHRT_PCKT BUSY_BANK NAK_OUT NAK_IN/ERR_FLUSH STALL_SNT/ERR_CRISO/ERR_NB_TRA EPT0 IT Sources RX_SETUP/ERR_FL_ISO TX_BK_RDY/ERR_TRANS TX_COMPLT RX_BK_RDY ERR_OVFLW MDATA_RX DATAX_RX EP mask EP sources (UDPHS_IEN) EPT_INT_x EP sources EP mask (UDPHS_IEN) EPT_INT_0 husb2dev interrupt EPT1-6 IT Sources (UDPHS_EPTCTLx) INT_DIS_DMA disable DMA channelx request (UDPHS_DMACONTROLx) EN_BUFFIT mask (UDPHS_IEN) DMA_INT_x mask DMA CH x END_TR_IT mask DESC_LD_IT 755 6289C–ATARM–28-May-09 41.4.12 41.4.12.1 Power Modes Controlling Device States A USB device has several possible states. Refer to Chapter 9 (USB Device Framework) of the Universal Serial Bus Specification, Rev 2.0. Figure 41-18. UDPHS Device State Diagram Attached Hub Reset Hub or Configured Deconfigured Bus Inactive Powered Bus Activity Power Interruption Reset Bus Inactive Default Reset Address Assigned Bus Inactive Address Bus Activity Device Deconfigured Device Configured Bus Inactive Configured Bus Activity Suspended Suspended Bus Activity Suspended Suspended Movement from one state to another depends on the USB bus state or on standard requests sent through control transactions via the default endpoint (endpoint 0). After a period of bus inactivity, the USB device enters Suspend Mode. Accepting Suspend/Resume requests from the USB host is mandatory. Constraints in Suspend Mode are very strict for bus-powered applications; devices may not consume more than 500 µA on the USB bus. While in Suspend Mode, the host may wake up a device by sending a resume signal (bus activity) or a USB device may send a wake-up request to the host, e.g., waking up a PC by moving a USB mouse. The wake-up feature is not mandatory for all devices and must be negotiated with the host. 756 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.4.12.2 Not Powered State Self powered devices can detect 5V VBUS using a PIO. When the device is not connected to a host, device power consumption can be reduced by the DETACH bit in UDPHS_CTRL. Disabling the transceiver is automatically done. HSDM, HSDP, FSDP and FSDP lines are tied to GND pull-downs integrated in the hub downstream ports. Entering Attached State When no device is connected, the USB FSDP and FSDM signals are tied to GND by 15 KΩ pulldowns integrated in the hub downstream ports. When a device is attached to an hub downstream port, the device connects a 1.5 KΩ pull-up on FSDP. The USB bus line goes into IDLE state, FSDP is pulled-up by the device 1.5 KΩ resistor to 3.3V and FSDM is pulled-down by the 15 KΩ resistor to GND of the host. After pull-up connection, the device enters the powered state. The transceiver remains disabled until bus activity is detected. In case of low power consumption need, the device can be stopped. When the device detects the VBUS, the software must enable the USB transceiver by enabling the EN_UDPHS bit in UDPHS_CTRL register. The software can detach the pull-up by setting DETACH bit in UDPHS_CTRL register. 41.4.12.4 From Powered State to Default State (Reset) After its connection to a USB host, the USB device waits for an end-of-bus reset. The unmasked flag ENDRESET is set in the UDPHS_IEN register and an interrupt is triggered. Once the ENDRESET interrupt has been triggered, the device enters Default State. In this state, the UDPHS software must: • Enable the default endpoint, setting the EPT_ENABL flag in the UDPHS_EPTCTLENB[0] register and, optionally, enabling the interrupt for endpoint 0 by writing 1 in EPT_INT_0 of the UDPHS_IEN register. The enumeration then begins by a control transfer. • Configure the Interrupt Mask Register which has been reset by the USB reset detection • Enable the transceiver. In this state, the EN_UDPHS bit in UDPHS_CTRL register must be enabled. 41.4.12.5 From Default State to Address State (Address Assigned) After a Set Address standard device request, the USB host peripheral enters the address state. Warning: before the device enters address state, it must achieve the Status IN transaction of the control transfer, i.e., the UDPHS device sets its new address once the TX_COMPLT flag in the UDPHS_EPTCTL[0] register has been received and cleared. To move to address state, the driver software sets the DEV_ADDR field and the FADDR_EN flag in the UDPHS_CTRL register. 41.4.12.6 From Address State to Configured State (Device Configured) Once a valid Set Configuration standard request has been received and acknowledged, the device enables endpoints corresponding to the current configuration. This is done by setting the BK_NUMBER, EPT_TYPE, EPT_DIR and EPT_SIZE fields in the UDPHS_EPTCFGx registers and enabling them by setting the EPT_ENABL flag in the UDPHS_EPTCTLENBx registers, and, optionally, enabling corresponding interrupts in the UDPHS_IEN register. 41.4.12.3 757 6289C–ATARM–28-May-09 41.4.12.7 Entering Suspend State (Bus Activity) When a Suspend (no bus activity on the USB bus) is detected, the DET_SUSPD signal in the UDPHS_STA register is set. This triggers an interrupt if the corresponding bit is set in the UDPHS_IEN register. This flag is cleared by writing to the UDPHS_CLRINT register. Then the device enters Suspend Mode. In this state bus powered devices must drain less than 500 µA from the 5V VBUS. As an example, the microcontroller switches to slow clock, disables the PLL and main oscillator, and goes into Idle Mode. It may also switch off other devices on the board. The UDPHS device peripheral clocks can be switched off. Resume event is asynchronously detected. 41.4.12.8 Receiving a Host Resume In Suspend mode, a resume event on the USB bus line is detected asynchronously, transceiver and clocks disabled (however the pull-up should not be removed). Once the resume is detected on the bus, the signal WAKE_UP in the UDPHS_INTSTA is set. It may generate an interrupt if the corresponding bit in the UDPHS_IEN register is set. This interrupt may be used to wake-up the core, enable PLL and main oscillators and configure clocks. 41.4.12.9 Sending an External Resume In Suspend State it is possible to wake-up the host by sending an external resume. The device waits at least 5 ms after being entered in Suspend State before sending an external resume. The device must force a K state from 1 to 15 ms to resume the host. 758 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.4.13 Test Mode A device must support the TEST_MODE feature when in the Default, Address or Configured High Speed device states. TEST_MODE can be: • Test_J • Test_K • Test_Packet • Test_SEO_NAK (See Section 41.5.11 “UDPHS Test Register” on page 775 for definitions of each test mode.) const char test_packet_buffer[] = { 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, 9 0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA,0xAA, 8 0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE, 8 0xFE,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF, // JJJJJJJKKKKKKK * 8 0x7F,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD, 0xFC,0x7E,0xBF,0xDF,0xEF,0xF7,0xFB,0xFD,0x7E * 10}, JK }; // JJJJJJJK * 8 // {JKKKKKKK // JJKKJJKK * // JJKKJJKK * // JKJKJKJK * 759 6289C–ATARM–28-May-09 41.5 USB High Speed Device Port (UDPHS) User Interface Register Mapping Register UDPHS Control Register UDPHS Frame Number Register Reserved UDPHS Interrupt Enable Register UDPHS Interrupt Status Register UDPHS Clear Interrupt Register UDPHS Endpoints Reset Register Reserved UDPHS Test Register Reserved UDPHS PADDRSIZE Register UDPHS Name1 Register UDPHS Name2 Register UDPHS Features Register UDPHS Endpoint0 Configuration Register UDPHS Endpoint0 Control Enable Register UDPHS Endpoint0 Control Disable Register UDPHS Endpoint0 Control Register Reserved (for endpoint 0) UDPHS Endpoint0 Set Status Register UDPHS Endpoint0 Clear Status Register UDPHS Endpoint0 Status Register UDPHS Endpoint1 to 6 Reserved UDPHS DMA Next Descriptor1 Address Register UDPHS DMA Channel1 Address Register UDPHS DMA Channel1 Control Register UDPHS DMA Channel1 Status Register DMA Channel2 to 5 (3) (2) Table 41-5. Offset 0x00 0x04 0x08 - 0x0C 0x10 0x14 0x18 0x1C 0x20 - 0xCC 0xE0 0xE4 - 0xE8 0xEC 0xF0 0xF4 0xF8 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 - 0x1DC 0x300 - 0x30C 0x310 0x314 0x318 0x31C 0x320 - 0x370 Name UDPHS_CTRL UDPHS_FNUM – UDPHS_IEN UDPHS_INTSTA UDPHS_CLRINT UDPHS_EPTRST – UDPHS_TST – UDPHS_IPPADDRSIZE UDPHS_IPNAME1 UDPHS_IPNAME2 UDPHS_IPFEATURES UDPHS_EPTCFG0 UDPHS_EPTCTLENB0 UDPHS_EPTCTLDIS0 UDPHS_EPTCTL0 – UDPHS_EPTSETSTA0 UDPHS_EPTCLRSTA0 UDPHS_EPTSTA0 Access Read/Write Read – Read/Write Read Write Write – Read/Write – Read Read Read Read Read/Write Write Write Read – Write Write Read Reset 0x0000_0200 0x0000_0000 – 0x0000_0010 0x0000_0000 – – – 0x0000_0000 – 0x0000_4000 0x4855_5342 0x3244_4556 0x0000_0000 – – 0x0000_0000(1) – – – 0x0000_0040 Registers – UDPHS_DMANXTDSC1 UDPHS_DMAADDRESS1 UDPHS_DMACONTROL1 UDPHS_DMASTATUS1 – Read/Write Read/Write Read/Write Read/Write – 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 Registers Notes: 1. The reset value for UDPHS_EPTCTL0 is 0x0000_0001. 2. The addresses for the UDPHS Endpoint registers shown here are for UDPHS Endpoint0. The structure of this group of registers is repeated successively for each endpoint according to the consecution of endpoint registers located between 0x120 and 0x1DC. 3. The addresses for the UDPHS DMA registers shown here are for UDPHS DMA Channel1. (There is no Channel0) The structure of this group of registers is repeated successively for each DMA channel according to the consecution of DMA registers located between 0x320 and 0x370. 760 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.1 Name: UDPHS Control Register UDPHS_CTRL Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 PULLD_DIS 3 DEV_ADDR 26 – 18 – 10 REWAKEUP 2 25 – 17 – 9 DETACH 1 24 – 16 – 8 EN_UDPHS 0 Access Type: 31 – 23 – 15 – 7 FADDR_EN • DEV_ADDR: UDPHS Address Read: This field contains the default address (0) after power-up or UDPHS bus reset. Write: This field is written with the value set by a SET_ADDRESS request received by the device firmware. • FADDR_EN: Function Address Enable Read: 0 = Device is not in address state. 1 = Device is in address state. Write: 0 = only the default function address is used (0). 1 = this bit is set by the device firmware after a successful status phase of a SET_ADDRESS transaction. When set, the only address accepted by the UDPHS controller is the one stored in the UDPHS Address field. It will not be cleared afterwards by the device firmware. It is cleared by hardware on hardware reset, or when UDPHS bus reset is received (see above). • EN_UDPHS: UDPHS Enable Read: 0 = UDPHS is disabled. 1 = UDPHS is enabled. Write: 0 = disable and reset the UDPHS controller, disable the UDPHS transceiver. 1 = enables the UDPHS controller. 761 6289C–ATARM–28-May-09 • DETACH: Detach Command Read: 0 = UDPHS is attached. 1 = UDPHS is detached, UTMI transceiver is suspended. Write: 0 = pull up the DP line (attach command). 1 = simulate a detach on the UDPHS line and force the UTMI transceiver into suspend state (Suspend M = 0). • REWAKEUP: Send Remote Wake Up Read: 0 = Remote Wake Up is disabled. 1 = Remote Wake Up is enabled. Write: 0 = no effect. 1 = force an external interrupt on the UDPHS controller for Remote Wake UP purposes. An Upstream Resume is sent only after the UDPHS bus has been in SUSPEND state for at least 5 ms. This bit is automatically cleared by hardware at the end of the Upstream Resume. • PULLD_DIS: Pull-Down Disable When set, there is no pull-down on DP & DM. (DM Pull-Down = DP Pull-Down = 0). Note: If the DETACH bit is also set, device DP & DM are left in high impedance state. 762 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.2 Name: UDPHS Frame Number Register UDPHS_FNUM Read 30 – 22 – 14 – 6 29 – 21 – 13 28 – 20 – 12 27 – 19 – 26 – 18 – 25 – 17 – 9 24 – 16 – 8 Access Type: 31 FNUM_ERR 23 – 15 – 7 11 10 FRAME_NUMBER 3 2 5 FRAME_NUMBER 4 1 MICRO_FRAME_NUM 0 • MICRO_FRAME_NUM: Microframe Number Number of the received microframe (0 to 7) in one frame.This field is reset at the beginning of each new frame (1 ms). One microframe is received each 125 microseconds (1 ms/8). • FRAME_NUMBER: Frame Number as defined in the Packet Field Formats This field is provided in the last received SOF packet (see INT_SOF in the UDPHS Interrupt Status Register). • FNUM_ERR: Frame Number CRC Error This bit is set by hardware when a corrupted Frame Number in Start of Frame packet (or Micro SOF) is received. This bit and the INT_SOF (or MICRO_SOF) interrupt are updated at the same time. 763 6289C–ATARM–28-May-09 41.5.3 Name: UDPHS Interrupt Enable Register UDPHS_IEN Read/Write 30 DMA_6 22 – 14 EPT_6 6 ENDOFRSM 29 DMA_5 21 – 13 EPT_5 5 WAKE_UP 28 DMA_4 20 – 12 EPT_4 4 ENDRESET 27 DMA_3 19 – 11 EPT_3 3 INT_SOF 26 DMA_2 18 – 10 EPT_2 2 MICRO_SOF 25 DMA_1 17 – 9 EPT_1 1 DET_SUSPD 24 – 16 – 8 EPT_0 0 – Access Type: 31 – 23 – 15 – 7 UPSTR_RES • DET_SUSPD: Suspend Interrupt Enable Read: 0 = Suspend Interrupt is disabled. 1 = Suspend Interrupt is enabled. Write 0 = disable Suspend Interrupt. 1 = enable Suspend Interrupt. • MICRO_SOF: Micro-SOF Interrupt Enable Read: 0 = Micro-SOF Interrupt is disabled. 1 = Micro-SOF Interrupt is enabled. Write 0 = disable Micro-SOF Interrupt. 1 = enable Micro-SOF Interrupt. • INT_SOF: SOF Interrupt Enable Read: 0 = SOF Interrupt is disabled. 1 = SOF Interrupt is enabled. Write 0 = disable SOF Interrupt. 1 = enable SOF Interrupt. 764 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • ENDRESET: End Of Reset Interrupt Enable Read: 0 = End Of Reset Interrupt is disabled. 1 = End Of Reset Interrupt is enabled. Write 0 = disable End Of Reset Interrupt. 1 = enable End Of Reset Interrupt. Automatically enabled after USB reset. • WAKE_UP: Wake Up CPU Interrupt Enable Read: 0 = Wake Up CPU Interrupt is disabled. 1 = Wake Up CPU Interrupt is enabled. Write 0 = disable Wake Up CPU Interrupt. 1 = enable Wake Up CPU Interrupt. • ENDOFRSM: End Of Resume Interrupt Enable Read: 0 = Resume Interrupt is disabled. 1 = Resume Interrupt is enabled. Write 0 = disable Resume Interrupt. 1 = enable Resume Interrupt. • UPSTR_RES: Upstream Resume Interrupt Enable Read: 0 = Upstream Resume Interrupt is disabled. 1 = Upstream Resume Interrupt is enabled. Write 0 = disable Upstream Resume Interrupt. 1 = enable Upstream Resume Interrupt. • EPT_x: Endpoint x Interrupt Enable Read: 0 = the interrupts for this endpoint are disabled. 1 = the interrupts for this endpoint are enabled. Write 0 = disable the interrupts for this endpoint. 765 6289C–ATARM–28-May-09 1 = enable the interrupts for this endpoint. • DMA_INT_x: DMA Channel x Interrupt Enable Read: 0 = the interrupts for this channel are disabled. 1 = the interrupts for this channel are enabled. Write 0 = disable the interrupts for this channel. 1 = enable the interrupts for this channel. 766 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.4 Name: UDPHS Interrupt Status Register UDPHS_INTSTA Read-only 30 DMA_6 22 – 14 EPT_6 6 ENDOFRSM 29 DMA_5 21 – 13 EPT_5 5 WAKE_UP 28 DMA_4 20 – 12 EPT_4 4 ENDRESET 27 DMA_3 19 – 11 EPT_3 3 INT_SOF 26 DMA_2 18 – 10 EPT_2 2 MICRO_SOF 25 DMA_1 17 – 9 EPT_1 1 DET_SUSPD 24 – 16 – 8 EPT_0 0 SPEED Access Type: 31 – 23 – 15 – 7 UPSTR_RES • SPEED: Speed Status 0 = reset by hardware when the hardware is in Full Speed mode. 1 = set by hardware when the hardware is in High Speed mode • DET_SUSPD: Suspend Interrupt 0 = cleared by setting the DET_SUSPD bit in UDPHS_CLRINT register 1 = set by hardware when a UDPHS Suspend (Idle bus for three frame periods, a J state for 3 ms) is detected. This triggers a UDPHS interrupt when the DET_SUSPD bit is set in UDPHS_IEN register. • MICRO_SOF: Micro Start Of Frame Interrupt 0 = cleared by setting the MICRO_SOF bit in UDPHS_CLRINT register. 1 = set by hardware when an UDPHS micro start of frame PID (SOF) has been detected (every 125 us) or synthesized by the macro. This triggers a UDPHS interrupt when the MICRO_SOF bit is set in UDPHS_IEN. In case of detected SOF, the MICRO_FRAME_NUM field in UDPHS_FNUM register is incremented and the FRAME_NUMBER field doesn’t change. Note: The Micro Start Of Frame Interrupt (MICRO_SOF), and the Start Of Frame Interrupt (INT_SOF) are not generated at the same time. • INT_SOF: Start Of Frame Interrupt 0 = cleared by setting the INT_SOF bit in UDPHS_CLRINT. 1 = set by hardware when an UDPHS Start Of Frame PID (SOF) has been detected (every 1 ms) or synthesized by the macro. This triggers a UDPHS interrupt when the INT_SOF bit is set in UDPHS_IEN register. In case of detected SOF, in High Speed mode, the MICRO_FRAME_NUMBER field is cleared in UDPHS_FNUM register and the FRAME_NUMBER field is updated. • ENDRESET: End Of Reset Interrupt 0 = cleared by setting the ENDRESET bit in UDPHS_CLRINT. 1 = set by hardware when an End Of Reset has been detected by the UDPHS controller. This triggers a UDPHS interrupt when the ENDRESET bit is set in UDPHS_IEN. 767 6289C–ATARM–28-May-09 • WAKE_UP: Wake Up CPU Interrupt 0 = cleared by setting the WAKE_UP bit in UDPHS_CLRINT. 1 = set by hardware when the UDPHS controller is in SUSPEND state and is re-activated by a filtered non-idle signal from the UDPHS line (not by an upstream resume). This triggers a UDPHS interrupt when the WAKE_UP bit is set in UDPHS_IEN register. When receiving this interrupt, the user has to enable the device controller clock prior to operation. Note: this interrupt is generated even if the device controller clock is disabled. • ENDOFRSM: End Of Resume Interrupt 0 = cleared by setting the ENDOFRSM bit in UDPHS_CLRINT. 1 = set by hardware when the UDPHS controller detects a good end of resume signal initiated by the host. This triggers a UDPHS interrupt when the ENDOFRSM bit is set in UDPHS_IEN. • UPSTR_RES: Upstream Resume Interrupt 0 = cleared by setting the UPSTR_RES bit in UDPHS_CLRINT. 1 = set by hardware when the UDPHS controller is sending a resume signal called “upstream resume”. This triggers a UDPHS interrupt when the UPSTR_RES bit is set in UDPHS_IEN. • EPT_x: Endpoint x Interrupt 0 = reset when the UDPHS_EPTSTAx interrupt source is cleared. 1 = set by hardware when an interrupt is triggered by the UDPHS_EPTSTAx register and this endpoint interrupt is enabled by the EPT_INT_x bit in UDPHS_IEN. • DMA_INT_x: DMA Channel x Interrupt 0 = reset when the UDPHS_DMASTATUSx interrupt source is cleared. 1 = set by hardware when an interrupt is triggered by the DMA Channelx and this endpoint interrupt is enabled by the DMA_INT_x bit in UDPHS_IEN. 768 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.5 Name: UDPHS Clear Interrupt Register UDPHS_CLRINT Write only 30 – 22 – 14 – 6 ENDOFRSM 29 – 21 – 13 – 5 WAKE_UP 28 – 20 – 12 – 4 ENDRESET 27 – 19 – 11 – 3 INT_SOF 26 – 18 – 10 – 2 MICRO_SOF 25 – 17 – 9 – 1 DET_SUSPD 24 – 16 – 8 – 0 – Access Type: 31 – 23 – 15 – 7 UPSTR_RES • DET_SUSPD: Suspend Interrupt Clear 0 = no effect. 1 = clear the DET_SUSPD bit in UDPHS_INTSTA. • MICRO_SOF: Micro Start Of Frame Interrupt Clear 0 = no effect. 1 = clear the MICRO_SOF bit in UDPHS_INTSTA. • INT_SOF: Start Of Frame Interrupt Clear 0 = no effect. 1 = clear the INT_SOF bit in UDPHS_INTSTA. • ENDRESET: End Of Reset Interrupt Clear 0 = no effect. 1 = clear the ENDRESET bit in UDPHS_INTSTA. • WAKE_UP: Wake Up CPU Interrupt Clear 0 = no effect. 1 = clear the WAKE_UP bit in UDPHS_INTSTA. • ENDOFRSM: End Of Resume Interrupt Clear 0 = no effect. 1 = clear the ENDOFRSM bit in UDPHS_INTSTA. • UPSTR_RES: Upstream Resume Interrupt Clear 0 = no effect. 1 = clear the UPSTR_RES bit in UDPHS_INTSTA. 769 6289C–ATARM–28-May-09 41.5.6 Name: UDPHS Endpoints Reset Register UDPHS_EPTRST Write only 30 – 22 – 14 – 6 EPT_6 29 – 21 – 13 – 5 EPT_5 28 – 20 – 12 – 4 EPT_4 27 – 19 – 11 – 3 EPT_3 26 – 18 – 10 – 2 EPT_2 25 – 17 – 9 – 1 EPT_1 24 – 16 – 8 – 0 EPT_0 Access Type: 31 – 23 – 15 – 7 – • EPT_x: Endpoint x Reset 0 = no effect. 1 = reset the Endpointx state. Setting this bit clears the Endpoint status UDPHS_EPTSTAx register, except for the TOGGLESQ_STA field. 770 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.7 Name: UDPHS Test SOF Counter Register UDPHS_TSTSOFCNT Read/Write 30 – 22 – 14 – 6 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 SOFCNTMAX 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 SOFCTLOAD • SOFCNTMAX: SOF Counter Max Value • SOFCTLOAD: SOF Counter Load 771 6289C–ATARM–28-May-09 41.5.8 Name: UDPHS Test A Counter Register UDPHS_TSTCNTA Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 CNTAMAX 3 CNTAMAX 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 CNTALOAD 7 6 5 4 2 1 0 • CNTALOAD: A Counter Load • CNTAMAX: A Counter Max Value 772 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.9 Name: UDPHS Test B Counter Register UDPHS_TSTCNTB Read/Write 30 – 22 – 14 29 – 21 – 13 28 – 20 – 12 27 – 19 – 11 CNTBMAX 3 CNTBMAX 26 – 18 – 10 25 – 17 – 9 24 – 16 – 8 Access Type: 31 – 23 – 15 CNTBLOAD 7 6 5 4 2 1 0 • CNTBLOAD: B Counter Load • CNTBMAX: B Counter Max Value 773 6289C–ATARM–28-May-09 41.5.10 Name: UDPHS Test Mode Register UDPHS_TSTMODEREG Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 28 – 20 – 12 – 4 27 – 19 – 11 – 3 TSTMODE 26 – 18 – 10 – 2 25 – 17 – 9 – 1 24 – 16 – 8 – 0 – Access Type: 31 – 23 – 15 – 7 – • TSTMODE: UDPHS Core TestModeReg 774 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.11 Name: UDPHS Test Register UDPHS_TST Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 OPMODE2 28 – 20 – 12 – 4 TST_PKT 27 – 19 – 11 – 3 TST_K 26 – 18 – 10 – 2 TST_J 25 – 17 – 9 – 1 SPEED_CFG 24 – 16 – 8 – 0 Access Type: 31 – 23 – 15 – 7 – • SPEED_CFG: Speed Configuration Read/Write: Speed Configuration: 00 01 10 11 Normal Mode: The macro is in Full Speed mode, ready to make a High Speed identification, if the host supports it and then to automatically switch to High Speed mode Reserved Force High Speed: Set this value to force the hardware to work in High Speed mode. Only for debug or test purpose. Force Full Speed: Set this value to force the hardware to work only in Full Speed mode. In this configuration, the macro will not respond to a High Speed reset handshake • TST_J: Test J Mode Read and write: 0 = no effect. 1 = set to send the J state on the UDPHS line. This enables the testing of the high output drive level on the D+ line. • TST_K: Test K Mode Read and write: 0 = no effect. 1 = set to send the K state on the UDPHS line. This enables the testing of the high output drive level on the D- line. • TST_PKT: Test Packet Mode Read and write: 0 = no effect. 1 = set to repetitively transmit the packet stored in the current bank. This enables the testing of rise and fall times, eye patterns, jitter, and any other dynamic waveform specifications. • OPMODE2: OpMode2 Read and write: 775 6289C–ATARM–28-May-09 0 = no effect. 1 = set to force the OpMode signal (UTMI interface) to “10”, to disable the bit-stuffing and the NRZI encoding. Note: For the Test mode, Test_SE0_NAK (see Universal Serial Bus Specification, Revision 2.0: 7.1.20, Test Mode Support). Force the device in High Speed mode, and configure a bulk-type endpoint. Do not fill this endpoint for sending NAK to the host. Upon command, a port’s transceiver must enter the High Speed receive mode and remain in that mode until the exit action is taken. This enables the testing of output impedance, low level output voltage and loading characteristics. In addition, while in this mode, upstream facing ports (and only upstream facing ports) must respond to any IN token packet with a NAK handshake (only if the packet CRC is determined to be correct) within the normal allowed device response time. This enables testing of the device squelch level circuitry and, additionally, provides a general purpose stimulus/response test for basic functional testing. 776 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.12 Name: UDPHS PADDRSIZE Register UDPHS_IPPADDRSIZE Read-only 30 29 28 27 IP_PADDRSIZE 20 19 IP_PADDRSIZE 12 11 IP_PADDRSIZE 4 3 IP_PADDRSIZE 26 25 24 Access Type: 31 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0 • IP_PADDRSIZE 2^UDPHS_PADDR_SIZE APB address bus aperture of the UDPHS 777 6289C–ATARM–28-May-09 41.5.13 Name: UDPHS Name1 Register UDPHS_IPNAME1 Read-only 30 29 28 IP_NAME1 27 26 25 24 Access Type: 31 23 22 21 20 IP_NAME1 19 18 17 16 15 14 13 12 IP_NAME1 11 10 9 8 7 6 5 4 IP_NAME1 3 2 1 0 • IP_NAME1 ASCII string “HUSB” 41.5.14 Name: UDPHS Name2 Register UDPHS_IPNAME2 Read-only 30 29 28 IP_NAME2 27 26 25 24 Access Type: 31 23 22 21 20 IP_NAME2 19 18 17 16 15 14 13 12 IP_NAME2 11 10 9 8 7 6 5 4 IP_NAME2 3 2 1 0 • IP_NAME2 ASCII string “2DEV” 778 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.15 Name: UDPHS Features Register UDPHS_IPFEATURES Read-only 30 ISO_EPT_14 22 ISO_EPT_6 14 29 ISO_EPT_13 21 ISO_EPT_5 13 FIFO_MAX_SIZE 5 DMA_CHANNEL_NBR 28 ISO_EPT_12 20 ISO_EPT_4 12 27 ISO_EPT_11 19 ISO_EPT_3 11 26 ISO_EPT_10 18 ISO_EPT_2 25 ISO_EPT_9 17 ISO_EPT_1 24 ISO_EPT_8 16 DATAB16_8 8 Access Type: 31 ISO_EPT_15 23 ISO_EPT_7 15 BW_DPRAM 7 DMA_B_SIZ 10 9 DMA_FIFO_WORD_DEPTH 2 1 EPT_NBR_MAX 6 4 3 0 • EPT_NBR_MAX: Max Number of Endpoints Give the max number of endpoints. 0 = if 16 endpoints are hardware implemented. 1 = if 1 endpoint is hardware implemented. 2 = if 2 endpoints are hardware implemented. ... 15 = if 15 endpoints are hardware implemented. • DMA_CHANNEL_NBR: Number of DMA Channels Give the number of DMA channels. 1 = if 1 DMA channel is hardware implemented. 2 = if 2 DMA channels are hardware implemented. ... 7 = if 7 DMA channels are hardware implemented. • DMA_B_SIZ: DMA Buffer Size 0 = if the DMA Buffer size is 16 bits. 1 = if the DMA Buffer size is 24 bits. • DMA_FIFO_WORD_DEPTH: DMA FIFO Depth in Words 0 = if FIFO is 16 words deep. 1 = if FIFO is 1 word deep. 2 = if FIFO is 2 words deep. ... 15 = if FIFO is 15 words deep. 779 6289C–ATARM–28-May-09 • FIFO_MAX_SIZE: DPRAM Size 0 = if DPRAM is 128 bytes deep. 1 = if DPRAM is 256 bytes deep. 2 = if DPRAM is 512 bytes deep. 3 = if DPRAM is 1024 bytes deep. 4 = if DPRAM is 2048 bytes deep. 5 = if DPRAM is 4096 bytes deep. 6 = if DPRAM is 8192 bytes deep. 7 = if DPRAM is 16384 bytes deep. • BW_DPRAM: DPRAM Byte Write Capability 0 = if DPRAM Write Data Shadow logic is implemented. 1 = if DPRAM is byte write capable. • DATAB16_8: UTMI DataBus16_8 0 = if the UTMI uses an 8-bit parallel data interface (60 MHz, unidirectional). 1 = if the UTMI uses a 16-bit parallel data interface (30 MHz, bidirectional). • ISO_EPT_x: Endpointx High Bandwidth Isochronous Capability 0 = if the endpoint does not have isochronous High Bandwidth Capability. 1 = if the endpoint has isochronous High Bandwidth Capability. 780 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.16 Name: UDPHS Endpoint Configuration Register UDPHS_EPTCFGx [x=0..6] Read/Write 30 – 22 – 14 – 6 BK_NUMBER 29 – 21 – 13 – 5 EPT_TYPE 28 – 20 – 12 – 4 27 – 19 – 11 – 3 EPT_DIR 26 – 18 – 10 – 2 25 – 17 – 9 NB_TRANS 1 EPT_SIZE 0 24 – 16 – 8 Access Type: 31 EPT_MAPD 23 – 15 – 7 • EPT_SIZE: Endpoint Size Read and write: Set this field according to the endpoint size in bytes (see Section 41.4.5 ”Endpoint Configuration”). Endpoint Size 000 001 010 011 100 101 110 111 Note: 8 bytes 16 bytes 32 bytes 64 bytes 128 bytes 256 bytes 512 bytes 1024 bytes(1) 1. 1024 bytes is only for isochronous endpoint. • EPT_DIR: Endpoint Direction Read and write: 0 = Clear this bit to configure OUT direction for Bulk, Interrupt and Isochronous endpoints. 1 = set this bit to configure IN direction for Bulk, Interrupt and Isochronous endpoints. For Control endpoints this bit has no effect and should be left at zero. • EPT_TYPE: Endpoint Type Read and write: Set this field according to the endpoint type (see Section 41.4.5 ”Endpoint Configuration”). (Endpoint 0 should always be configured as control) 781 6289C–ATARM–28-May-09 :Endpoint Type 00 01 10 11 Control endpoint Isochronous endpoint Bulk endpoint Interrupt endpoint • BK_NUMBER: Number of Banks Read and write: Set this field according to the endpoint’s number of banks (see Section 41.4.5 ”Endpoint Configuration”). Number of Banks 00 01 10 11 Zero bank, the endpoint is not mapped in memory One bank (bank 0) Double bank (Ping-Pong: bank 0/bank 1) Triple bank (bank 0/bank 1/bank 2) • NB_TRANS: Number Of Transaction per Microframe Read and Write: The Number of transactions per microframe is set by software. Note: Meaningful for high bandwidth isochronous endpoint only. • EPT_MAPD: Endpoint Mapped Read-only: 0 = the user should reprogram the register with correct values. 1 = set by hardware when the endpoint size (EPT_SIZE) and the number of banks (BK_NUMBER) are correct regarding: – the fifo max capacity (FIFO_MAX_SIZE in UDPHS_IPFEATURES register) – the number of endpoints/banks already allocated – the number of allowed banks for this endpoint 782 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.17 Name: UDPHS Endpoint Control Enable Register UDPHS_EPTCTLENBx [x=0..6] Write-only 30 – 22 – 14 NAK_IN/ ERR_FLUSH 29 – 21 – 13 STALL_SNT/ ERR_CRISO/ ERR_NBTRA 5 – 28 – 20 – 12 RX_SETUP/ ERR_FL_ISO 27 – 19 – 11 TX_PK_RDY/ ERR_TRANS 26 – 18 BUSY_BANK 10 TX_COMPLT 25 – 17 – 9 RX_BK_RDY 24 – 16 – 8 ERR_OVFLW Access Type: 31 SHRT_PCKT 23 – 15 NAK_OUT 7 MDATA_RX 6 DATAX_RX 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL For additional Information, see “UDPHS Endpoint Control Register” on page 787. • EPT_ENABL: Endpoint Enable 0 = no effect. 1 = enable endpoint according to the device configuration. • AUTO_VALID: Packet Auto-Valid Enable 0 = no effect. 1 = enable this bit to automatically validate the current packet and switch to the next bank for both IN and OUT transfers. • INTDIS_DMA: Interrupts Disable DMA 0 = no effect. 1 = If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled. • NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints) 0 = no effect. 1 = forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. • DATAX_RX: DATAx Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 0 = no effect. 1 = enable DATAx Interrupt. • MDATA_RX: MDATA Interrupt Enable (Only for high bandwidth Isochronous OUT endpoints) 0 = no effect. 1 = enable MDATA Interrupt. • ERR_OVFLW: Overflow Error Interrupt Enable 0 = no effect. 1 = enable Overflow Error Interrupt. 783 6289C–ATARM–28-May-09 • RX_BK_RDY: Received OUT Data Interrupt Enable 0 = no effect. 1 = enable Received OUT Data Interrupt. • TX_COMPLT: Transmitted IN Data Complete Interrupt Enable 0 = no effect. 1 = enable Transmitted IN Data Complete Interrupt. • TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enable 0 = no effect. 1 = enable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enable 0 = no effect. 1 = enable RX_SETUP/Error Flow ISO Interrupt. • STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent /ISO CRC Error/Number of Transaction Error Interrupt Enable 0 = no effect. 1 = enable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. • NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enable 0 = no effect. 1 = enable NAKIN/Bank Flush Error Interrupt. • NAK_OUT: NAKOUT Interrupt Enable 0 = no effect. 1 = enable NAKOUT Interrupt. • BUSY_BANK: Busy Bank Interrupt Enable 0 = no effect. 1 = enable Busy Bank Interrupt. • SHRT_PCKT: Short Packet Send/Short Packet Interrupt Enable For OUT endpoints: 0 = no effect. 1 = enable Short Packet Interrupt. For IN endpoints: Guarantees short packet at end of DMA Transfer if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTOVALID bits are also set. 784 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.18 Name: UDPHS Endpoint Control Disable Register UDPHS_EPTCTLDISx [x=0..6] Write-only 30 – 22 – 14 NAK_IN/ ERR_FLUSH 29 – 21 – 13 STALL_SNT/ ERR_CRISO/ ERR_NBTRA 5 – 28 – 20 – 12 RX_SETUP/ ERR_FL_ISO 27 – 19 – 11 TX_PK_RDY/ ERR_TRANS 26 – 18 BUSY_BANK 10 TX_COMPLT 25 – 17 – 9 RX_BK_RDY 24 – 16 – 8 ERR_OVFLW Access Type: 31 SHRT_PCKT 23 – 15 NAK_OUT 7 MDATA_RX 6 DATAX_RX 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_DISABL For additional Information, see “UDPHS Endpoint Control Register” on page 787. • EPT_DISABL: Endpoint Disable 0 = no effect. 1 = disable endpoint. • AUTO_VALID: Packet Auto-Valid Disable 0 = no effect. 1 = disable this bit to not automatically validate the current packet. • INTDIS_DMA: Interrupts Disable DMA 0 = no effect. 1 = disable the “Interrupts Disable DMA”. • NYET_DIS: NYET Enable (Only for High Speed Bulk OUT endpoints) 0 = no effect. 1 = let the hardware handle the handshake response for the High Speed Bulk OUT transfer. • DATAX_RX: DATAx Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 0 = no effect. 1 = disable DATAx Interrupt. • MDATA_RX: MDATA Interrupt Disable (Only for High Bandwidth Isochronous OUT endpoints) 0 = no effect. 1 = disable MDATA Interrupt. • ERR_OVFLW: Overflow Error Interrupt Disable 0 = no effect. 1 = disable Overflow Error Interrupt. 785 6289C–ATARM–28-May-09 • RX_BK_RDY: Received OUT Data Interrupt Disable 0 = no effect. 1 = disable Received OUT Data Interrupt. • TX_COMPLT: Transmitted IN Data Complete Interrupt Disable 0 = no effect. 1 = disable Transmitted IN Data Complete Interrupt. • TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Disable 0 = no effect. 1 = disable TX Packet Ready/Transaction Error Interrupt. • RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow Interrupt Disable 0 = no effect. 1 = disable RX_SETUP/Error Flow ISO Interrupt. • STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Disable 0 = no effect. 1 = disable Stall Sent/Error CRC ISO/Error Number of Transaction Interrupt. • NAK_IN/ERR_FLUSH: NAKIN/bank flush error Interrupt Disable 0 = no effect. 1 = disable NAKIN/ Bank Flush Error Interrupt. • NAK_OUT: NAKOUT Interrupt Disable 0 = no effect. 1 = disable NAKOUT Interrupt. • BUSY_BANK: Busy Bank Interrupt Disable 0 = no effect. 1 = disable Busy Bank Interrupt. • SHRT_PCKT: Short Packet Interrupt Disable For OUT endpoints: 0 = no effect. 1 = disable Short Packet Interrupt. For IN endpoints: Never automatically add a zero length packet at end of DMA transfer. 786 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.19 Name: UDPHS Endpoint Control Register UDPHS_EPTCTLx [x=0..6] Read-only 30 – 22 – 14 NAK_IN/ ERR_FLUSH 29 – 21 – 13 STALL_SNT/ ERR_CRISO/ ERR_NBTRA 5 – 28 – 20 – 12 RX_SETUP/ ERR_FL_ISO 27 – 19 – 11 TX_PK_RDY/ ERR_TRANS 26 – 18 BUSY_BANK 10 TX_COMPLT 25 – 17 – 9 RX_BK_RDY 24 – 16 – 8 ERR_OVFLW Access Type: 31 SHRT_PCKT 23 – 15 NAK_OUT 7 MDATA_RX 6 DATAX_RX 4 NYET_DIS 3 INTDIS_DMA 2 – 1 AUTO_VALID 0 EPT_ENABL • EPT_ENABL: Endpoint Enable 0 = If cleared, the endpoint is disabled according to the device configuration. Endpoint 0 should always be enabled after a hardware or UDPHS bus reset and participate in the device configuration. 1 = If set, the endpoint is enabled according to the device configuration. • AUTO_VALID: Packet Auto-Valid Enabled (Not for CONTROL Endpoints) Set this bit to automatically validate the current packet and switch to the next bank for both IN and OUT endpoints. For IN Transfer: If this bit is set, then the UDPHS_EPTSTAx register TX_PK_RDY bit is set automatically when the current bank is full and at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. The user may still set the UDPHS_EPTSTAx register TX_PK_RDY bit if the current bank is not full, unless the user wants to send a Zero Length Packet by software. For OUT Transfer: If this bit is set, then the UDPHS_EPTSTAx register RX_BK_RDY bit is automatically reset for the current bank when the last packet byte has been read from the bank FIFO or at the end of DMA buffer if the UDPHS_DMACONTROLx register END_B_EN bit is set. For example, to truncate a padded data packet when the actual data transfer size is reached. The user may still clear the UDPHS_EPTSTAx register RX_BK_RDY bit, for example, after completing a DMA buffer by software if UDPHS_DMACONTROLx register END_B_EN bit was disabled or in order to cancel the read of the remaining data bank(s). • INTDIS_DMA: Interrupt Disables DMA If set, when an enabled endpoint-originated interrupt is triggered, the DMA request is disabled regardless of the UDPHS_IEN register EPT_INT_x bit for this endpoint. Then, the firmware will have to clear or disable the interrupt source or clear this bit if transfer completion is needed. If the exception raised is associated with the new system bank packet, then the previous DMA packet transfer is normally completed, but the new DMA packet transfer is not started (not requested). 787 6289C–ATARM–28-May-09 If the exception raised is not associated to a new system bank packet (NAK_IN, NAK_OUT, ERR_FL_ISO...), then the request cancellation may happen at any time and may immediately stop the current DMA transfer. This may be used, for example, to identify or prevent an erroneous packet to be transferred into a buffer or to complete a DMA buffer by software after reception of a short packet, or to perform buffer truncation on ERR_FL_ISO interrupt for adaptive rate. • NYET_DIS: NYET Disable (Only for High Speed Bulk OUT endpoints) 0 = If clear, this bit lets the hardware handle the handshake response for the High Speed Bulk OUT transfer. 1 = If set, this bit forces an ACK response to the next High Speed Bulk OUT transfer instead of a NYET response. Note: According to the Universal Serial Bus Specification, Rev 2.0 (8.5.1.1 NAK Responses to OUT/DATA During PING Protocol), a NAK response to an HS Bulk OUT transfer is expected to be an unusual occurrence. • DATAX_RX: DATAx Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 0 = no effect. 1 = send an interrupt when a DATA2, DATA1 or DATA0 packet has been received meaning the whole microframe data payload has been received. • MDATA_RX: MDATA Interrupt Enabled (Only for High Bandwidth Isochronous OUT endpoints) 0 = no effect. 1 = send an interrupt when an MDATA packet has been received and so at least one packet of the microframe data payload has been received. • ERR_OVFLW: Overflow Error Interrupt Enabled 0 = Overflow Error Interrupt is masked. 1 = Overflow Error Interrupt is enabled. • RX_BK_RDY: Received OUT Data Interrupt Enabled 0 = Received OUT Data Interrupt is masked. 1 = Received OUT Data Interrupt is enabled. • TX_COMPLT: Transmitted IN Data Complete Interrupt Enabled 0 = Transmitted IN Data Complete Interrupt is masked. 1 = Transmitted IN Data Complete Interrupt is enabled. • TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error Interrupt Enabled 0 = TX Packet Ready/Transaction Error Interrupt is masked. 1 = TX Packet Ready/Transaction Error Interrupt is enabled. Caution: Interrupt source is active as long as the corresponding UDPHS_EPTSTAx register TX_PK_RDY flag remains low. If there are no more banks available for transmitting after the software has set UDPHS_EPTSTAx/TX_PK_RDY for the last transmit packet, then the interrupt source remains inactive until the first bank becomes free again to transmit at UDPHS_EPTSTAx/TX_PK_RDY hardware clear. • RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow Interrupt Enabled 0 = Received SETUP/Error Flow Interrupt is masked. 1 = Received SETUP/Error Flow Interrupt is enabled. 788 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary • STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent/ISO CRC Error/Number of Transaction Error Interrupt Enabled 0 = Stall Sent/ISO CRC error/number of Transaction Error Interrupt is masked. 1 = Stall Sent /ISO CRC error/number of Transaction Error Interrupt is enabled. • NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Interrupt Enabled 0 = NAKIN Interrupt is masked. 1 = NAKIN/Bank Flush Error Interrupt is enabled. • NAK_OUT: NAKOUT Interrupt Enabled 0 = NAKOUT Interrupt is masked. 1 = NAKOUT Interrupt is enabled. • BUSY_BANK: Busy Bank Interrupt Enabled 0 = BUSY_BANK Interrupt is masked. 1 = BUSY_BANK Interrupt is enabled. For OUT endpoints: an interrupt is sent when all banks are busy. For IN endpoints: an interrupt is sent when all banks are free. • SHRT_PCKT: Short Packet Interrupt Enabled For OUT endpoints: send an Interrupt when a Short Packet has been received. 0 = Short Packet Interrupt is masked. 1 = Short Packet Interrupt is enabled. For IN endpoints: a Short Packet transmission is guaranteed upon end of the DMA Transfer, thus signaling a BULK or INTERRUPT end of transfer or an end of isochronous (micro-)frame data, but only if the UDPHS_DMACONTROLx register END_B_EN and UDPHS_EPTCTLx register AUTO_VALID bits are also set. 789 6289C–ATARM–28-May-09 41.5.20 Name: UDPHS Endpoint Set Status Register UDPHS_EPTSETSTAx [x=0..6] Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 FRCESTALL 28 – 20 – 12 – 4 – 27 – 19 – 11 TX_PK_RDY 3 – 26 – 18 – 10 – 2 – 25 – 17 – 9 KILL_BANK 1 – 24 – 16 – 8 – 0 – Access Type: 31 – 23 – 15 – 7 – • FRCESTALL: Stall Handshake Request Set 0 = no effect. 1 = set this bit to request a STALL answer to the host for the next handshake Refer to chapters 8.4.5 (Handshake Packets) and 9.4.5 (Get Status) of the Universal Serial Bus Specification, Rev 2.0 for more information on the STALL handshake. • KILL_BANK: KILL Bank Set (for IN Endpoint) 0 = no effect. 1 = kill the last written bank. • TX_PK_RDY: TX Packet Ready Set 0 = no effect. 1 = set this bit after a packet has been written into the endpoint FIFO for IN data transfers – This flag is used to generate a Data IN transaction (device to host). – Device firmware checks that it can write a data payload in the FIFO, checking that TX_PK_RDY is cleared. – Transfer to the FIFO is done by writing in the “Buffer Address” register. – Once the data payload has been transferred to the FIFO, the firmware notifies the UDPHS device setting TX_PK_RDY to one. – UDPHS bus transactions can start. – TXCOMP is set once the data payload has been received by the host. – Data should be written into the endpoint FIFO only after this bit has been cleared. – Set this bit without writing data to the endpoint FIFO to send a Zero Length Packet. 790 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.21 Name: UDPHS Endpoint Clear Status Register UDPHS_EPTCLRSTAx [x=0..6] Write-only 30 – 22 – 14 NAK_IN/ ERR_FLUSH 6 TOGGLESQ 29 – 21 – 13 STALL_SNT/ ERR_NBTRA 5 FRCESTALL 28 – 20 – 12 RX_SETUP/ ERR_FL_ISO 4 – 27 – 19 – 11 – 26 – 18 – 10 TX_COMPLT 25 – 17 – 9 RX_BK_RDY 24 – 16 – 8 – Access Type: 31 – 23 – 15 NAK_OUT 7 – 3 – 2 – 1 – 0 – • FRCESTALL: Stall Handshake Request Clear 0 = no effect. 1 = clear the STALL request. The next packets from host will not be STALLed. • TOGGLESQ: Data Toggle Clear 0 = no effect. 1 = clear the PID data of the current bank For OUT endpoints, the next received packet should be a DATA0. For IN endpoints, the next packet will be sent with a DATA0 PID. • RX_BK_RDY: Received OUT Data Clear 0 = no effect. 1 = clear the RX_BK_RDY flag of UDPHS_EPTSTAx. • TX_COMPLT: Transmitted IN Data Complete Clear 0 = no effect. 1 = clear the TX_COMPLT flag of UDPHS_EPTSTAx. • RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow Clear 0 = no effect. 1 = clear the RX_SETUP/ERR_FL_ISO flags of UDPHS_EPTSTAx. • STALL_SNT/ERR_NBTRA: Stall Sent/Number of Transaction Error Clear 0 = no effect. 1 = clear the STALL_SNT/ERR_NBTRA flags of UDPHS_EPTSTAx. • NAK_IN/ERR_FLUSH: NAKIN/Bank Flush Error Clear 0 = no effect. 1 = clear the NAK_IN/ERR_FLUSH flags of UDPHS_EPTSTAx. 791 6289C–ATARM–28-May-09 • NAK_OUT: NAKOUT Clear 0 = no effect. 1 = clear the NAK_OUT flag of UDPHS_EPTSTAx. 792 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.22 Name: UDPHS Endpoint Status Register UDPHS_EPTSTAx [x=0..6] Read-only 30 29 28 27 BYTE_COUNT 19 26 25 24 Access Type: 31 SHRT_PCKT 23 22 21 20 18 BYTE_COUNT BUSY_BANK_STA 17 16 CURRENT_BANK/ CONTROL_DIR 9 RX_BK_RDY/ KILL_BANK 8 ERR_OVFLW 15 NAK_OUT 14 NAK_IN/ ERR_FLUSH 13 STALL_SNT/ ERR_CRISO/ ERR_NBTRA 5 FRCESTALL 12 RX_SETUP/ ERR_FL_ISO 11 TX_PK_RDY/ ERR_TRANS 10 TX_COMPLT 7 6 TOGGLESQ_STA 4 – 3 – 2 – 1 – 0 – • FRCESTALL: Stall Handshake Request 0 = no effect. 1= If set a STALL answer will be done to the host for the next handshake. This bit is reset by hardware upon received SETUP. • TOGGLESQ_STA: Toggle Sequencing Toggle Sequencing: IN endpoint: it indicates the PID Data Toggle that will be used for the next packet sent. This is not relative to the current bank. CONTROL and OUT endpoint: These bits are set by hardware to indicate the PID data of the current bank: 00 01 10 11 Data0 Data1 Data2 (only for High Bandwidth Isochronous Endpoint) MData (only for High Bandwidth Isochronous Endpoint) Note 1: I n OUT transfer, the Toggle information is meaningful only when the current bank is busy (Received OUT Data = 1). Note 2:These bits are updated for OUT transfer: – a new data has been written into the current bank. – the user has just cleared the Received OUT Data bit to switch to the next bank. Note 3: For High Bandwidth Isochronous Out endpoint, it is recommended to check the UDPHS_EPTSTAx/ERR_TRANS bit to know if the toggle sequencing is correct or not. Note 4: This field is reset to DATA1 by the UDPHS_EPTCLRSTAx register TOGGLESQ bit, and by UDPHS_EPTCTLDISx (disable endpoint). 793 6289C–ATARM–28-May-09 • ERR_OVFLW: Overflow Error This bit is set by hardware when a new too-long packet is received. Example: If the user programs an endpoint 64 bytes wide and the host sends 128 bytes in an OUT transfer, then the Overflow Error bit is set. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). • RX_BK_RDY/KILL_BANK: Received OUT Data/KILL Bank – Received OUT Data: (For OUT endpoint or Control endpoint) This bit is set by hardware after a new packet has been stored in the endpoint FIFO. This bit is cleared by the device firmware after reading the OUT data from the endpoint. For multi-bank endpoints, this bit may remain active even when cleared by the device firmware, this if an other packet has been received meanwhile. Hardware assertion of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register RX_BK_RDY bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – KILL Bank: (For IN endpoint) – the bank is really cleared or the bank is sent, BUSY_BANK_STA is decremented. – the bank is not cleared but sent on the IN transfer, TX_COMPLT – the bank is not cleared because it was empty. The user should wait that this bit is cleared before trying to clear another packet. Note: “Kill a packet” may be refused if at the same time, an IN token is coming and the current packet is sent on the UDPHS line. In this case, the TX_COMPLT bit is set. Take notice however, that if at least two banks are ready to be sent, there is no problem to kill a packet even if an IN token is coming. In fact, in that case, the current bank is sent (IN transfer) and the last bank is killed. • TX_COMPLT: Transmitted IN Data Complete This bit is set by hardware after an IN packet has been transmitted for isochronous endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk and Interrupt endpoints. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). • TX_PK_RDY/ERR_TRANS: TX Packet Ready/Transaction Error – TX Packet Ready: This bit is cleared by hardware, as soon as the packet has been sent for isochronous endpoints, or after the host has acknowledged the packet for Control, Bulk and Interrupt endpoints. For Multi-bank endpoints, this bit may remain clear even after software is set if another bank is available to transmit. Hardware clear of this bit may generate an interrupt if enabled by the UDPHS_EPTCTLx register TX_PK_RDY bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). – Transaction Error : (For high bandwidth isochronous OUT endpoints) (Read-Only) This bit is set by hardware when a transaction error occurs inside one microframe. 794 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary If one toggle sequencing problem occurs among the n-transactions (n = 1, 2 or 3) inside a microframe, then this bit is still set as long as the current bank contains one “bad” n-transaction. (see “CURRENT_BANK/CONTROL_DIR: Current Bank/Control Direction” on page 796) As soon as the current bank is relative to a new “good” n-transactions, then this bit is reset. Note1: A transaction error occurs when the toggle sequencing does not respect the Universal Serial Bus Specification, Rev 2.0 (5.9.2 High Bandwidth Isochronous endpoints) (Bad PID, missing data....) Note2: When a transaction error occurs, the user may empty all the “bad” transactions by clearing the Received OUT Data flag (RX_BK_RDY). If this bit is reset, then the user should consider that a new n-transaction is coming. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). • RX_SETUP/ERR_FL_ISO: Received SETUP/Error Flow – Received SETUP: (for Control endpoint only) This bit is set by hardware when a valid SETUP packet has been received from the host. It is cleared by the device firmware after reading the SETUP data from the endpoint FIFO. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint), and by UDPHS_EPTCTLDISx (disable endpoint). – Error Flow: (for isochronous endpoint only) This bit is set by hardware when a transaction error occurs. – Isochronous IN transaction is missed, the micro has no time to fill the endpoint (underflow). – Isochronous OUT data is dropped because the bank is busy (overflow). This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). • STALL_SNT/ERR_CRISO/ERR_NBTRA: Stall Sent/CRC ISO Error/Number of Transaction Error – STALL_SNT: (for Control, Bulk and Interrupt endpoints) This bit is set by hardware after a STALL handshake has been sent as requested by the UDPHS_EPTSTAx register FRCESTALL bit. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – ERR_CRISO: (for Isochronous OUT endpoints) (Read-only) This bit is set by hardware if the last received data is corrupted (CRC error on data). This bit is updated by hardware when new data is received (Received OUT Data bit). – ERR_NBTRA: (for High Bandwidth Isochronous IN endpoints) This bit is set at the end of a microframe in which at least one data bank has been transmitted, if less than the number of transactions per micro-frame banks (UDPHS_EPTCFGx register NB_TRANS) have been validated for transmission inside this microframe. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). • NAK_IN/ERR_FLUSH: NAK IN/Bank Flush Error – NAK_IN: This bit is set by hardware when a NAK handshake has been sent in response to an IN request from the Host. This bit is cleared by software. 795 6289C–ATARM–28-May-09 – ERR_FLUSH: (for High Bandwidth Isochronous IN endpoints) This bit is set when flushing unsent banks at the end of a microframe. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint). • NAK_OUT: NAK OUT This bit is set by hardware when a NAK handshake has been sent in response to an OUT or PING request from the Host. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by EPT_CTL_DISx (disable endpoint). • CURRENT_BANK/CONTROL_DIR: Current Bank/Control Direction – Current Bank: (all endpoints except Control endpoint) These bits are set by hardware to indicate the number of the current bank. 00 01 10 11 Bank 0 (or single bank) Bank 1 Bank 2 Invalid Note: the current bank is updated each time the user: – Sets the TX Packet Ready bit to prepare the next IN transfer and to switch to the next bank. – Clears the received OUT data bit to access the next bank. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). – Control Direction: (for Control endpoint only) 0 = a Control Write is requested by the Host. 1 = a Control Read is requested by the Host. Note1: This bit corresponds with the 7th bit of the bmRequestType (Byte 0 of the Setup Data). Note2: This bit is updated after receiving new setup data. • BUSY_BANK_STA: Busy Bank Number These bits are set by hardware to indicate the number of busy banks. IN endpoint: it indicates the number of busy banks filled by the user, ready for IN transfer. OUT endpoint: it indicates the number of busy banks filled by OUT transaction from the Host. 00 01 10 11 All banks are free 1 busy bank 2 busy banks 3 busy banks • BYTE_COUNT: UDPHS Byte Count Byte count of a received data packet. This field is incremented after each write into the endpoint (to prepare an IN transfer). This field is decremented after each reading into the endpoint (OUT transfer). 796 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary This field is also updated at RX_BK_RDY flag clear with the next bank. This field is also updated at TX_PK_RDY flag set with the next bank. This field is reset by EPT_x of UDPHS_EPTRST register. • SHRT_PCKT: Short Packet An OUT Short Packet is detected when the receive byte count is less than the configured UDPHS_EPTCFGx register EPT_Size. This bit is updated at the same time as the BYTE_COUNT field. This bit is reset by UDPHS_EPTRST register EPT_x (reset endpoint) and by UDPHS_EPTCTLDISx (disable endpoint). 797 6289C–ATARM–28-May-09 41.5.23 UDPHS DMA Channel Transfer Descriptor The DMA channel transfer descriptor is loaded from the memory. Be careful with the alignment of this buffer. The structure of the DMA channel transfer descriptor is defined by three parameters as described below: Offset 0: The address must be aligned: 0xXXXX0 Next Descriptor Address Register: UDPHS_DMANXTDSCx Offset 4: The address must be aligned: 0xXXXX4 DMA Channelx Address Register: UDPHS_DMAADDRESSx Offset 8: The address must be aligned: 0xXXXX8 DMA Channelx Control Register: UDPHS_DMACONTROLx To use the DMA channel transfer descriptor, fill the structures with the correct value (as described in the following pages). Then write directly in UDPHS_DMANXTDSCx the address of the descriptor to be used first. Then write 1 in the LDNXT_DSC bit of UDPHS_DMACONTROLx (load next channel transfer descriptor). The descriptor is automatically loaded upon Endpointx request for packet transfer. 798 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.24 Name: UDPHS DMA Next Descriptor Address Register UDPHS_DMANXTDSCx [x = 1..5] Read/Write 30 29 28 27 NXT_DSC_ADD 20 19 NXT_DSC_ADD 12 11 NXT_DSC_ADD 4 3 NXT_DSC_ADD 26 25 24 Access Type: 31 23 22 21 18 17 16 15 14 13 10 9 8 7 6 5 2 1 0 • NXT_DSC_ADD This field points to the next channel descriptor to be processed. This channel descriptor must be aligned, so bits 0 to 3 of the address must be equal to zero. 799 6289C–ATARM–28-May-09 41.5.25 Name: UDPHS DMA Channel Address Register UDPHS_DMAADDRESSx [x = 1..5] Read/Write 30 29 28 BUFF_ADD 27 26 25 24 Access Type: 31 23 22 21 20 BUFF_ADD 19 18 17 16 15 14 13 12 BUFF_ADD 11 10 9 8 7 6 5 4 BUFF_ADD 3 2 1 0 • BUFF_ADD This field determines the AHB bus starting address of a DMA channel transfer. Channel start and end addresses may be aligned on any byte boundary. The firmware may write this field only when the UDPHS_DMASTATUS register CHANN_ENB bit is clear. This field is updated at the end of the address phase of the current access to the AHB bus. It is incrementing of the access byte width. The access width is 4 bytes (or less) at packet start or end, if the start or end address is not aligned on a word boundary. The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer. The packet end address is either the channel end address or the latest channel address accessed in the channel buffer. The channel start address is written by software or loaded from the descriptor, whereas the channel end address is either determined by the end of buffer or the UDPHS device, USB end of transfer if the UDPHS_DMACONTROLx register END_TR_EN bit is set. 800 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.26 Name: UDPHS DMA Channel Control Register UDPHS_DMACONTROLx [x = 1..5] Read/Write 30 29 28 27 BUFF_LENGTH 20 19 BUFF_LENGTH 12 – 4 END_TR_IT 11 – 3 END_B_EN 26 25 24 Access Type: 31 23 22 21 18 17 16 15 – 7 BURST_LCK 14 – 6 DESC_LD_IT 13 – 5 END_BUFFIT 10 – 2 END_TR_EN 9 – 1 LDNXT_DSC 8 – 0 CHANN_ENB • CHANN_ENB (Channel Enable Command) 0 = DMA channel is disabled at and no transfer will occur upon request. This bit is also cleared by hardware when the channel source bus is disabled at end of buffer. If the UDPHS_DMACONTROL register LDNXT_DSC bit has been cleared by descriptor loading, the firmware will have to set the corresponding CHANN_ENB bit to start the described transfer, if needed. If the UDPHS_DMACONTROL register LDNXT_DSC bit is cleared, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both UDPHS_DMASTATUS register CHANN_ENB and CHANN_ACT flags read as 0. If a channel request is currently serviced when this bit is cleared, the DMA FIFO buffer is drained until it is empty, then the UDPHS_DMASTATUS register CHANN_ENB bit is cleared. If the LDNXT_DSC bit is set at or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer occurs) and the next descriptor is immediately loaded. 1 = UDPHS_DMASTATUS register CHANN_ENB bit will be set, thus enabling DMA channel data transfer. Then any pending request will start the transfer. This may be used to start or resume any requested transfer. • LDNXT_DSC: Load Next Channel Transfer Descriptor Enable (Command) 0 = no channel register is loaded after the end of the channel transfer. 1 = the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDPHS_DMASTATUS/CHANN_ENB bit is reset. If the UDPHS_DMA CONTROL/CHANN_ENB bit is cleared, the next descriptor is immediately loaded upon transfer request. LDNXT_DSC 0 0 1 1 CHANN_ENB 0 1 0 1 Stop now Run and stop at end of buffer Load next descriptor now Run and link at end of buffer Description 801 6289C–ATARM–28-May-09 • END_TR_EN: End of Transfer Enable (Control) Used for OUT transfers only. 0 = USB end of transfer is ignored. 1 = UDPHS device can put an end to the current buffer transfer. When set, a BULK or INTERRUPT short packet or the last packet of an ISOCHRONOUS (micro) frame (DATAX) will close the current buffer and the UDPHS_DMASTATUSx register END_TR_ST flag will be raised. This is intended for UDPHS non-prenegotiated end of transfer (BULK or INTERRUPT) or ISOCHRONOUS microframe data buffer closure. • END_B_EN: End of Buffer Enable (Control) 0 = DMA Buffer End has no impact on USB packet transfer. 1 = endpoint can validate the packet (according to the values programmed in the UDPHS_EPTCTLx register AUTO_VALID and SHRT_PCKT fields) at DMA Buffer End, i.e. when the UDPHS_DMASTATUS register BUFF_COUNT reaches 0. This is mainly for short packet IN validation initiated by the DMA reaching end of buffer, but could be used for OUT packet truncation (discarding of unwanted packet data) at the end of DMA buffer. • END_TR_IT: End of Transfer Interrupt Enable 0 = UDPHS device initiated buffer transfer completion will not trigger any interrupt at UDPHS_STATUSx/END_TR_ST rising. 1 = an interrupt is sent after the buffer transfer is complete, if the UDPHS device has ended the buffer transfer. Use when the receive size is unknown. • END_BUFFIT: End of Buffer Interrupt Enable 0 = UDPHS_DMA_STATUSx/END_BF_ST rising will not trigger any interrupt. 1 = an interrupt is generated when the UDPHS_DMASTATUSx register BUFF_COUNT reaches zero. • DESC_LD_IT: Descriptor Loaded Interrupt Enable 0 = UDPHS_DMASTATUSx/DESC_LDST rising will not trigger any interrupt. 1 = an interrupt is generated when a descriptor has been loaded from the bus. • BURST_LCK: Burst Lock Enable 0 = the DMA never locks bus access. 1 = USB packets AHB data bursts are locked for maximum optimization of the bus bandwidth usage and maximization of fly-by AHB burst duration. • BUFF_LENGTH: Buffer Byte Length (Write-only) This field determines the number of bytes to be transferred until end of buffer. The maximum channel transfer size (64 KBytes) is reached when this field is 0 (default value). If the transfer size is unknown, this field should be set to 0, but the transfer end may occur earlier under UDPHS device control. When this field is written, The UDPHS_DMASTATUSx register BUFF_COUNT field is updated with the write value. Note: Note: Bits [31:2] are only writable when issuing a channel Control Command other than “Stop Now”. For reliability it is highly recommended to wait for both UDPHS_DMASTATUSx register CHAN_ACT and CHAN_ENB flags are at 0, thus ensuring the channel has been stopped before issuing a command other than “Stop Now”. 802 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 41.5.27 Name: UDPHS DMA Channel Status Register UDPHS_DMASTATUSx [x = 1..5] Read/Write 30 29 28 27 BUFF_COUNT 20 19 BUFF_COUNT 12 – 4 END_TR_ST 11 – 3 – 26 25 24 Access Type: 31 23 22 21 18 17 16 15 – 7 – 14 – 6 DESC_LDST 13 – 5 END_BF_ST 10 – 2 – 9 – 1 CHANN_ACT 8 – 0 CHANN_ENB • CHANN_ENB: Channel Enable Status 0 = if cleared, the DMA channel no longer transfers data, and may load the next descriptor if the UDPHS_DMACONTROLx register LDNXT_DSC bit is set. When any transfer is ended either due to an elapsed byte count or a UDPHS device initiated transfer end, this bit is automatically reset. 1 = if set, the DMA channel is currently enabled and transfers data upon request. This bit is normally set or cleared by writing into the UDPHS_DMACONTROLx register CHANN_ENB bit field either by software or descriptor loading. If a channel request is currently serviced when the UDPHS_DMACONTROLx register CHANN_ENB bit is cleared, the DMA FIFO buffer is drained until it is empty, then this status bit is cleared. • CHANN_ACT: Channel Active Status 0 = the DMA channel is no longer trying to source the packet data. When a packet transfer is ended this bit is automatically reset. 1 = the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a packet transfer cannot be completed due to an END_BF_ST, this flag stays set during the next channel descriptor load (if any) and potentially until UDPHS packet transfer completion, if allowed by the new descriptor. • END_TR_ST: End of Channel Transfer Status 0 = cleared automatically when read by software. 1 = set by hardware when the last packet transfer is complete, if the UDPHS device has ended the transfer. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • END_BF_ST: End of Channel Buffer Status 0 = cleared automatically when read by software. 1 = set by hardware when the BUFF_COUNT downcount reach zero. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. 803 6289C–ATARM–28-May-09 • DESC_LDST: Descriptor Loaded Status 0 = cleared automatically when read by software. 1 = set by hardware when a descriptor has been loaded from the system bus. Valid until the CHANN_ENB flag is cleared at the end of the next buffer transfer. • BUFF_COUNT: Buffer Byte Count This field determines the current number of bytes still to be transferred for this buffer. This field is decremented from the AHB source bus access byte width at the end of this bus address phase. The access byte width is 4 by default, or less, at DMA start or end, if the start or end address is not aligned on a word boundary. At the end of buffer, the DMA accesses the UDPHS device only for the number of bytes needed to complete it. This field value is reliable (stable) only if the channel has been stopped or frozen (UDPHS_EPTCTLx register NT_DIS_DMA bit is used to disable the channel request) and the channel is no longer active CHANN_ACT flag is 0. Note: For OUT endpoints, if the receive buffer byte length (BUFF_LENGTH) has been defaulted to zero because the USB transfer length is unknown, the actual buffer byte length received will be 0x10000-BUFF_COUNT. 804 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 42. Pulse Width Modulation (PWM) Controller 42.1 Description The PWM macrocell controls several channels independently. Each channel controls one square output waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock generator provides several clocks resulting from the division of the PWM macrocell master clock. All PWM macrocell accesses are made through APB mapped registers. Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle. 42.2 Block Diagram Figure 42-1. Pulse Width Modulation Controller Block Diagram PWM Controller PWMx Channel Period Update Duty Cycle Comparator PWMx PWMx Clock Selector Counter PIO PWM0 Channel Period Update Duty Cycle Comparator PWM0 PWM0 Clock Selector MCK Counter PMC Clock Generator APB Interface Interrupt Generator AIC APB 805 6289C–ATARM–28-May-09 42.3 I/O Lines Description Each channel outputs one waveform on one external I/O line. Table 42-1. Name PWMx I/O Line Description Description PWM Waveform Output for Channel x Type Output 42.4 42.4.1 Product Dependencies I/O Lines The pins used for interfacing the PWM may be multiplexed with PIO lines. The programmer must first program the PIO controller to assign the desired PWM pins to their peripheral function. If I/O lines of the PWM are not used by the application, they can be used for other purposes by the PIO controller. All of the PWM outputs may or may not be enabled. If an application requires only four channels, then only four PIO lines will be assigned to PWM outputs. 42.4.2 Power Management The PWM is not continuously clocked. The programmer must first enable the PWM clock in the Power Management Controller (PMC) before using the PWM. However, if the application does not require PWM operations, the PWM clock can be stopped when not needed and be restarted later. In this case, the PWM will resume its operations where it left off. Configuring the PWM does not require the PWM clock to be enabled. 42.4.3 Interrupt Sources The PWM interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the PWM interrupt requires the AIC to be programmed first. Note that it is not recommended to use the PWM interrupt line in edge sensitive mode. 42.5 Functional Description The PWM macrocell is primarily composed of a clock generator module and 4 channels. – Clocked by the system clock, MCK, the clock generator module provides 13 clocks. – Each channel can independently choose one of the clock generator outputs. – Each channel generates an output waveform with attributes that can be defined independently for each channel through the user interface registers. 806 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 42.5.1 PWM Clock Generator Figure 42-2. Functional View of the Clock Generator Block Diagram MCK modulo n counter MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Divider A clkA PREA DIVA PWM_MR Divider B clkB PREB DIVB PWM_MR Caution: Before using the PWM macrocell, the programmer must first enable the PWM clock in the Power Management Controller (PMC). The PWM macrocell master clock, MCK, is divided in the clock generator module to provide different clocks available for all channels. Each channel can independently select one of the divided clocks. The clock generator is divided in three blocks: – a modulo n counter which provides 11 clocks: FMCK, FMCK/2, FMCK/4, FMCK/8, FMCK/16, FMCK/32, FMCK/64, FMCK/128, FMCK/256, FMCK/512, FMCK/1024 – two linear dividers (1, 1/2, 1/3, ... 1/255) that provide two separate clocks: clkA and clkB Each linear divider can independently divide one of the clocks of the modulo n counter. The selection of the clock to be divided is made according to the PREA (PREB) field of the PWM Mode register (PWM_MR). The resulting clock clkA (clkB) is the clock selected divided by DIVA (DIVB) field value in the PWM Mode register (PWM_MR). 807 6289C–ATARM–28-May-09 After a reset of the PWM controller, DIVA (DIVB) and PREA (PREB) in the PWM Mode register are set to 0. This implies that after reset clkA (clkB) are turned off. At reset, all clocks provided by the modulo n counter are turned off except clock “clk”. This situation is also true when the PWM master clock is turned off through the Power Management Controller. 42.5.2 42.5.2.1 PWM Channel Block Diagram Figure 42-3. Functional View of the Channel Block Diagram inputs from clock generator Channel Clock Selector Internal Counter Comparator PWMx output waveform inputs from APB bus Each of the 4 channels is composed of three blocks: • A clock selector which selects one of the clocks provided by the clock generator described in Section 42.5.1 “PWM Clock Generator” on page 807. • An internal counter clocked by the output of the clock selector. This internal counter is incremented or decremented according to the channel configuration and comparators events. The size of the internal counter is 16 bits. • A comparator used to generate events according to the internal counter value. It also computes the PWMx output waveform according to the configuration. 42.5.2.2 Waveform Properties The different properties of output waveforms are: • the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the clock generator described in the previous section. This channel parameter is defined in the CPRE field of the PWM_CMRx register. This field is reset at 0. • the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register. - If the waveform is left aligned, then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be: ( X × CPRD ) ------------------------------MCK By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: 808 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary ( C RPD × DIVA ) ------------------------------------------ or ( CRPD × DIVAB ) ---------------------------------------------MCK MCK If the waveform is center aligned then the output waveform period depends on the counter source clock and can be calculated: By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( 2 × X × CPRD ) -----------------------------------------MCK By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2 × CPRD × DIVA ) ----------------------------------------------------- or ( 2 × CPRD × DIVB ) ----------------------------------------------------MCK MCK • the waveform duty cycle. This channel parameter is defined in the CDTY field of the PWM_CDTYx register. If the waveform is left aligned then: ( period – 1 ⁄ fchannel_x_clock × CDTY ) duty cycle = ----------------------------------------------------------------------------------------------------------period If the waveform is center aligned, then: ( ( period ⁄ 2 ) – 1 ⁄ fchannel_x_clock × CDTY ) ) duty cycle = ----------------------------------------------------------------------------------------------------------------------------( period ⁄ 2 ) • the waveform polarity. At the beginning of the period, the signal can be at high or low level. This property is defined in the CPOL field of the PWM_CMRx register. By default the signal starts by a low level. • the waveform alignment. The output waveform can be left or center aligned. Center aligned waveforms can be used to generate non overlapped waveforms. This property is defined in the CALG field of the PWM_CMRx register. The default mode is left aligned. Figure 42-4. Non Overlapped Center Aligned Waveforms No overlap PWM0 PWM1 Period Note: 1. See Figure 42-5 on page 811 for a detailed description of center aligned waveforms. When center aligned, the internal channel counter increases up to CPRD and.decreases down to 0. This ends the period. When left aligned, the internal channel counter increases up to CPRD and is reset. This ends the period. 809 6289C–ATARM–28-May-09 Thus, for the same CPRD value, the period for a center aligned channel is twice the period for a left aligned channel. Waveforms are fixed at 0 when: • CDTY = CPRD and CPOL = 0 • CDTY = 0 and CPOL = 1 Waveforms are fixed at 1 (once the channel is enabled) when: • CDTY = 0 and CPOL = 0 • CDTY = CPRD and CPOL = 1 The waveform polarity must be set before enabling the channel. This immediately affects the channel output level. Changes on channel polarity are not taken into account while the channel is enabled. 810 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 42-5. Waveform Properties PWM_MCKx CHIDx(PWM_SR) CHIDx(PWM_ENA) CHIDx(PWM_DIS) Center Aligned CALG(PWM_CMRx) = 1 PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Period Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) PWM_CCNTx CPRD(PWM_CPRDx) CDTY(PWM_CDTYx) Left Aligned CALG(PWM_CMRx) = 0 Period Output Waveform PWMx CPOL(PWM_CMRx) = 0 Output Waveform PWMx CPOL(PWM_CMRx) = 1 CHIDx(PWM_ISR) 811 6289C–ATARM–28-May-09 42.5.3 42.5.3.1 PWM Controller Operations Initialization Before enabling the output channel, this channel must have been configured by the software application: • Configuration of the clock generator if DIVA and DIVB are required • Selection of the clock for each channel (CPRE field in the PWM_CMRx register) • Configuration of the waveform alignment for each channel (CALG field in the PWM_CMRx register) • Configuration of the period for each channel (CPRD in the PWM_CPRDx register). Writing in PWM_CPRDx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CPRDx as explained below. • Configuration of the duty cycle for each channel (CDTY in the PWM_CDTYx register). Writing in PWM_CDTYx Register is possible while the channel is disabled. After validation of the channel, the user must use PWM_CUPDx Register to update PWM_CDTYx as explained below. • Configuration of the output waveform polarity for each channel (CPOL in the PWM_CMRx register) • Enable Interrupts (Writing CHIDx in the PWM_IER register) • Enable the PWM channel (Writing CHIDx in the PWM_ENA register) It is possible to synchronize different channels by enabling them at the same time by means of writing simultaneously several CHIDx bits in the PWM_ENA register. • In such a situation, all channels may have the same clock selector configuration and the same period specified. 42.5.3.2 Source Clock Selection Criteria The large number of source clocks can make selection difficult. The relationship between the value in the Period Register (PWM_CPRDx) and the Duty Cycle Register (PWM_CDTYx) can help the user in choosing. The event number written in the Period Register gives the PWM accuracy. The Duty Cycle quantum cannot be lower than 1/PWM_CPRDx value. The higher the value of PWM_CPRDx, the greater the PWM accuracy. For example, if the user sets 15 (in decimal) in PWM_CPRDx, the user is able to set a value between 1 up to 14 in PWM_CDTYx Register. The resulting duty cycle quantum cannot be lower than 1/15 of the PWM period. 42.5.3.3 Changing the Duty Cycle or the Period It is possible to modulate the output waveform duty cycle or period. To prevent unexpected output waveform, the user must use the update register (PWM_CUPDx) to change waveform parameters while the channel is still enabled. The user can write a new period value or duty cycle value in the update register (PWM_CUPDx). This register holds the new value until the end of the current cycle and updates the value for the next cycle. Depending on the CPD field in the PWM_CMRx register, PWM_CUPDx either updates PWM_CPRDx or PWM_CDTYx. Note that even if the update register is used, the period must not be smaller than the duty cycle. 812 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 42-6. Synchronized Period or Duty Cycle Update User's Writing PWM_CUPDx Value 1 0 PWM_CMRx. CPD PWM_CPRDx PWM_CDTYx End of Cycle To prevent overwriting the PWM_CUPDx by software, the user can use status events in order to synchronize his software. Two methods are possible. In both, the user must enable the dedicated interrupt in PWM_IER at PWM Controller level. The first method (polling method) consists of reading the relevant status bit in PWM_ISR Register according to the enabled channel(s). See Figure 42-7. The second method uses an Interrupt Service Routine associated with the PWM channel. Note: Reading the PWM_ISR register automatically clears CHIDx flags. Figure 42-7. Polling Method PWM_ISR Read Acknowledgement and clear previous register state Writing in CPD field Update of the Period or Duty Cycle CHIDx = 1 YES Writing in PWM_CUPDx The last write has been taken into account Note: Polarity and alignment can be modified only when the channel is disabled. 813 6289C–ATARM–28-May-09 42.5.3.4 Interrupts Depending on the interrupt mask in the PWM_IMR register, an interrupt is generated at the end of the corresponding channel period. The interrupt remains active until a read operation in the PWM_ISR register occurs. A channel interrupt is enabled by setting the corresponding bit in the PWM_IER register. A channel interrupt is disabled by setting the corresponding bit in the PWM_IDR register. 814 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 42.6 Pulse Width Modulation (PWM) Controller User Interface PWM Controller Registers Register PWM Mode Register PWM Enable Register PWM Disable Register PWM Status Register PWM Interrupt Enable Register PWM Interrupt Disable Register PWM Interrupt Mask Register PWM Interrupt Status Register Reserved Reserved Channel 0 Mode Register Channel 0 Duty Cycle Register Channel 0 Period Register Channel 0 Counter Register Channel 0 Update Register Reserved Channel 1 Mode Register Channel 1 Duty Cycle Register Channel 1 Period Register Channel 1 Counter Register Channel 1 Update Register ... PWM_CMR1 PWM_CDTY1 PWM_CPRD1 PWM_CCNT1 PWM_CUPD1 ... Read/Write Read/Write Read/Write Read-only Write-only ... 0x0 0x0 0x0 0x0 ... PWM_CMR0 PWM_CDTY0 PWM_CPRD0 PWM_CCNT0 PWM_CUPD0 Read/Write Read/Write Read/Write Read-only Write-only 0x0 0x0 0x0 0x0 Name PWM_MR PWM_ENA PWM_DIS PWM_SR PWM_IER PWM_IDR PWM_IMR PWM_ISR – Access Read/Write Write-only Write-only Read-only Write-only Write-only Read-only Read-only – Peripheral Reset Value 0 0 0 0 – Table 42-2. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x4C - 0xFC 0x100 - 0x1FC 0x200 0x204 0x208 0x20C 0x210 ... 0x220 0x224 0x228 0x22C 0x230 ... 815 6289C–ATARM–28-May-09 42.6.1 PWM Mode Register Register Name: PWM_MR Access Type: 31 – 23 Read/Write 30 – 22 29 – 21 28 – 20 DIVB 27 26 PREB 19 18 17 16 25 24 15 – 7 14 – 6 13 – 5 12 – 4 DIVA 11 10 PREA 9 8 3 2 1 0 • DIVA, DIVB: CLKA, CLKB Divide Factor DIVA, DIVB 0 1 2-255 CLKA, CLKB CLKA, CLKB clock is turned off CLKA, CLKB clock is clock selected by PREA, PREB CLKA, CLKB clock is clock selected by PREA, PREB divided by DIVA, DIVB factor. • PREA, PREB PREA, PREB 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 1 0 0 0 Other 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK. MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 Reserved Divider Input Clock 816 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 42.6.2 PWM Enable Register Register Name: PWM_ENA Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Enable PWM output for channel x. 42.6.3 PWM Disable Register Register Name: PWM_DIS Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID 0 = No effect. 1 = Disable PWM output for channel x. 817 6289C–ATARM–28-May-09 42.6.4 PWM Status Register Register Name: PWM_SR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID 0 = PWM output for channel x is disabled. 1 = PWM output for channel x is enabled. 818 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 42.6.5 PWM Interrupt Enable Register Register Name: PWM_IER Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Enable interrupt for PWM channel x. 42.6.6 PWM Interrupt Disable Register Register Name: PWM_IDR Access Type: 31 – 23 – 15 – 7 – Write-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID. 0 = No effect. 1 = Disable interrupt for PWM channel x. 819 6289C–ATARM–28-May-09 42.6.7 PWM Interrupt Mask Register Register Name: PWM_IMR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID. 0 = Interrupt for PWM channel x is disabled. 1 = Interrupt for PWM channel x is enabled. 42.6.8 PWM Interrupt Status Register Register Name: PWM_ISR Access Type: 31 – 23 – 15 – 7 – Read-only 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 CHID3 26 – 18 – 10 – 2 CHID2 25 – 17 – 9 – 1 CHID1 24 – 16 – 8 – 0 CHID0 • CHIDx: Channel ID 0 = No new channel period has been achieved since the last read of the PWM_ISR register. 1 = At least one new channel period has been achieved since the last read of the PWM_ISR register. Note: Reading PWM_ISR automatically clears CHIDx flags. 820 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 42.6.9 PWM Channel Mode Register Register Name: PWM_CMRx Access Type: 31 – 23 – 15 – 7 – Read/Write 30 – 22 – 14 – 6 – 29 – 21 – 13 – 5 – 28 – 20 – 12 – 4 – 27 – 19 – 11 – 3 26 – 18 – 10 CPD 2 CPRE 25 – 17 – 9 CPOL 1 24 – 16 – 8 CALG 0 • CPRE: Channel Pre-scaler CPRE 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 Other 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 MCK MCK/2 MCK/4 MCK/8 MCK/16 MCK/32 MCK/64 MCK/128 MCK/256 MCK/512 MCK/1024 CLKA CLKB Reserved Channel Pre-scaler • CALG: Channel Alignment 0 = The period is left aligned. 1 = The period is center aligned. • CPOL: Channel Polarity 0 = The output waveform starts at a low level. 1 = The output waveform starts at a high level. • CPD: Channel Update Period 0 = Writing to the PWM_CUPDx will modify the duty cycle at the next period start event. 1 = Writing to the PWM_CUPDx will modify the period at the next period start event. 821 6289C–ATARM–28-May-09 42.6.10 PWM Channel Duty Cycle Register Register Name: PWM_CDTYx Access Type: 31 Read/Write 30 29 28 CDTY 27 26 25 24 23 22 21 20 CDTY 19 18 17 16 15 14 13 12 CDTY 11 10 9 8 7 6 5 4 CDTY 3 2 1 0 Only the first 16 bits (internal channel counter size) are significant. • CDTY: Channel Duty Cycle Defines the waveform duty cycle. This value must be defined between 0 and CPRD (PWM_CPRx). 822 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 42.6.11 PWM Channel Period Register Register Name: PWM_CPRDx Access Type: 31 Read/Write 30 29 28 CPRD 27 26 25 24 23 22 21 20 CPRD 19 18 17 16 15 14 13 12 CPRD 11 10 9 8 7 6 5 4 CPRD 3 2 1 0 Only the first 16 bits (internal channel counter size) are significant. • CPRD: Channel Period I f the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be calculated: – By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( X × CPRD ) ------------------------------MCK – By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( CRPD × DIVA ) ------------------------------------------ or ( CRPD × DIVAB ) ---------------------------------------------MCK MCK If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be calculated: – By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be: ( 2 × X × CPRD ) -----------------------------------------MCK – By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively: ( 2 × CPRD × DIVA ) ----------------------------------------------------- or ( 2 × CPRD × DIVB ) ----------------------------------------------------MCK MCK 823 6289C–ATARM–28-May-09 42.6.12 PWM Channel Counter Register Register Name: PWM_CCNTx Access Type: 31 Read-only 30 29 28 CNT 27 26 25 24 23 22 21 20 CNT 19 18 17 16 15 14 13 12 CNT 11 10 9 8 7 6 5 4 CNT 3 2 1 0 • CNT: Channel Counter Register Internal counter value. This register is reset when: • the channel is enabled (writing CHIDx in the PWM_ENA register). • the counter reaches CPRD value defined in the PWM_CPRDx register if the waveform is left aligned. 42.6.13 PWM Channel Update Register Register Name: PWM_CUPDx Access Type: 31 Write-only 30 29 28 CUPD 27 26 25 24 23 22 21 20 CUPD 19 18 17 16 15 14 13 12 CUPD 11 10 9 8 7 6 5 4 CUPD 3 2 1 0 This register acts as a double buffer for the period or the duty cycle. This prevents an unexpected waveform when modifying the waveform period or duty-cycle. Only the first 16 bits (internal channel counter size) are significant. CPD (PWM_CMRx Register) 0 1 The duty-cycle (CDTC in the PWM_CDRx register) is updated with the CUPD value at the beginning of the next period. The period (CPRD in the PWM_CPRx register) is updated with the CUPD value at the beginning of the next period. 824 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43. Touch Screen ADC Controller 43.1 Description The Touch Screen ADC Controller is based on a Successive Approximation Register (SAR) 10bit Analog-to-Digital Converter (ADC). It also integrates: • a 6-to-1 analog multiplexer for analog-to-digital conversions of up to 6 analog lines • 4 power switches that measure both axis positions on the resistive touch screen panel • 1 additional power switch and an embedded resistor that detects pen-interrupt and pen loss The conversions extend from 0V to TSADVREF. The TSADCC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register. Conversions can be started for all enabled channels, either by a software trigger, by detection of a rising edge on the external trigger pin TSADTRG or by an integrated programmable timer. When the Touch Screen is enabled, a timer-triggered sequencer automatically configures the power switches, performs the conversions and stores the results in dedicated registers. The TSADCC also integrates a Sleep Mode and a Pen-Detect Mode and connects with one PDC channel. These features reduce both power consumption and processor intervention. The TSADCC timings, like the Startup Time and Sample and Hold Time, are fully configurable. 825 6289C–ATARM–28-May-09 43.2 Block Diagram Figure 43-1. TSADCC Block Diagram TSADC VDDANA TSADCC Memory Controller ADTRG Trigger Selection Timer PDC PIO Touch Screen Sequencer ADC Control Logic User Interface Peripheral Bridge APB AD0XP Analog Multiplexer AD1XM AD2YP AD3YM GPAD4 .... Touch Screen Switches Successive Approximation Register Analog-to-Digital Converter TSADC Clock PMC GPADx ADVREF GND TSADC Interrupt AIC GPADx: last general-purpose ADC channel defined by the number of channels 826 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.3 Signal Description TSADCC Pin Description Description Analog power supply Reference voltage Analog input channel 0 or Touch Screen Top channel Analog input channel 1 or Touch Screen Bottom channel Analog input channel 2 or Touch Screen Right channel Analog input channel 3 or Touch Screen Left channel General-purpose analog input channels 4 to 5 External trigger Table 43-1. Pin Name VDDANA TSADVREF AD0XP AD1XM AD2YP AD3YM GPAD4 - GPAD5 TSADTRG 43.4 43.4.1 Product Dependencies Power Management The TSADC controller is not continuously clocked. The programmer must first enable the TSADC controller Clock in the Power Management Controller (PMC) before using the TSADC controller. However, if the application does not require TSADC controller operations, the TSADC controller clock can be stopped when not needed and be restarted later. Configuring the TSADC controller does not require the TSADC controller clock to be enabled. 43.4.2 Interrupt Sources The TSADCC interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the TSADCC interrupt requires the AIC to be programmed first. Analog Inputs The analog input pins can be multiplexed with PIO lines. In this case, the assignment of the TSADCC input is automatically done as soon as the corresponding channel is enabled by writing the register TSADCC_CHER. By default, after reset, the PIO lines are configured as input with its pull-up enabled and the TSADCC inputs are connected to the GND. 43.4.3 43.4.4 I/O Lines The pin TSADTRG may be shared with other peripheral functions through the PIO Controller. In this case, the PIO Controller should be set accordingly to assign the pin TSADTRG to the TSADCC function. 43.4.5 Conversion Performances For performance and electrical characteristics of the TSADCC, see the section “Electrical Characteristics” of the full datasheet. 827 6289C–ATARM–28-May-09 43.5 Analog-to-digital Converter Functional Description The TSADCC embeds a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The ADC supports 8-bit or 10-bit resolutions. The conversion is performed on a full range between 0V and the reference voltage pin TSADVREF. Analog inputs between these voltages convert to values based on a linear conversion. 43.5.1 ADC Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the TSADCC Mode Register. See Section 43.10.2 “TSADCC Mode Register” on page 840. By default, after a reset, the resolution is the highest and the DATA field in the “TSADCC Channel Data Register x (x = 0..5)” are fully used. By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers. The two highest bits of the DATA field in the corresponding TSADCC_CDR register and of the LDATA field in the TSADCC_LCDR register read 0. Moreover, when a PDC channel is connected to the TSADCC, 10-bit resolution sets the transfer request sizes to 16-bit. Setting the bit LOWRES automatically switches to 8-bit data transfers. In this case, the destination buffers are optimized. All the conversions for the Touch Screen forces the ADC in 10-bit resolution, regardless of the LOWRES setting. Further details are given in the section “Operating Modes” on page 835. 43.5.2 ADC Clock The TSADCC uses the ADC Clock to perform conversions. Converting a single analog value to a 10-bit digital data requires Sample and Hold Clock cycles as defined in the field SHTIM of the “TSADCC Mode Register” and 10 ADC Clock cycles. The ADC Clock frequency is selected in the PRESCAL field of the “TSADCC Mode Register”. The ADC clock range is between MCK/2, if PRESCAL is 0, and MCK/128, if PRESCAL is set to 63 (0x3F). PRESCAL must be programmed in order to provide an ADC clock frequency according to the maximum sampling rate parameter given in the Electrical Characteristics section. 43.5.3 Sleep Mode The TSADCC Sleep Mode maximizes power saving by automatically deactivating the Analog-toDigital Converter cell when it is not being used for conversions. Sleep Mode is enabled by setting the bit SLEEP in “TSADCC Mode Register”. The SLEEP of the ADC is automatically managed by the conversion sequencer, which can automatically process the conversions of all channels at lowest power consumption. When a trigger occurs, the Analog-to-Digital Converter cell is automatically activated. As the analog cell requires a start-up time, the logic waits during this time and then starts the conversion on the enabled channels. When all conversions are complete, the ADC is deactivated until the next trigger. 43.5.4 Startup Time The Touch Screen ADC has a minimal Startup Time when it exits the Sleep Mode. As the ADC Clock depends on the application, the user has to program the field STARTUP in the “TSADCC 828 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Mode Register”, which defines how many ADC Clock cycles to wait before performing the first conversion of the sequence. The field STARTUP can define a Startup Time between 8 and 1024 ADC Clock cycles by steps of 8. The user must assure that ADC Startup Time given in the section “Electrical Characteristics” is covered by this wait time. 43.5.5 Sample and Hold Time In the same way, a minimal Sample and Hold Time is necessary for the TSADCC to guarantee the best converted final value between selection of two channels. This time depends on the input impedance of the analog input, but also on the output impedance of the driver providing the signal to the analog input, as there is no input buffer amplifier. The Sample and Hold time has to be programmed through the bitfields SHTIM in the “TSADCC Mode Register” and TSSHTIM in the “TSADCC Touch Screen Register”. The field SHTIM defines the number of ADC Clock cycles for an analog input, while the field TSSHTIM defines the number of ADC Clock cycles for a Touch Screen input. These both fields can define a Sample and Hold time between 1 and 16 ADC Clock cycles. The field TSSHTIM defines also the time the power switches of the Touch Screen are closed when the TSADCC performs a conversion for the Touch Screen. 43.6 43.6.1 Touch Screen Resistive Touch Screen Principles A resistive touch screen is based on two resistive films, each one being fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. Between the two, there is a layer that acts as an insulator, but also enables contact when you press the screen. This is illustrated in Figure 43-2. 829 6289C–ATARM–28-May-09 Figure 43-2. Touch Screen Position Measurement Pen Contact XP YM YP XM XP VDD YP VDD YP XP Volt XM Vertical Position Detection YM Volt GND GND Horizontal Position Detection 43.6.2 Position Measurement Method As shown in Figure 43-2, to detect the position of a contact, a supply is first applied from top to bottom. Due to the linear resistance of the film, there is a voltage gradient from top to bottom. When a contact is performed on the screen, the voltage propagates at the point the two surfaces come into contact with the second film. If the input impedance on the right and left electrodes sense is high enough, the film does not affect this voltage, despite its resistive nature. For the horizontal direction, the same method is used, but by applying supply from left to right. The range depends on the supply voltage and on the loss in the switches that connect to the top and bottom electrodes. In an ideal world (linear, with no loss through switches), the horizontal position is equal to: VYM / VDD or VYP / VDD. The proposed implementation with on-chip power switches is shown in Figure 43-3. The voltage measurement at the output of the switch compensates for the switches loss. It is possible to correct for the switch loss by performing the operation: [VYP - VXM] / [VXP - VXM] . This requires additional measurements, as shown in Figure 43-3. 830 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 43-3. Touch Screen Switches Implementation XP VDDANA XM GND To the ADC VDDANA YP YM GND VDDANA Switch Resistor VDDANA Switch Resistor XP YP YP XP XM Switch Resistor YM Switch Resistor GND Horizontal Position Detection GND Vertical Position Detection 43.6.3 Pen Detect Method When there is no contact, it is not necessary to perform conversion. However, it is important to detect a contact by keeping the power consumption as low as possible. The proposed implementation polarizes the vertical panel by closing the switch on XP and ties the horizontal panel by an embedded resistor connected to YM. This resistor is enabled by a fifth switch. Since there is no contact, no current is flowing and there is no related power consumption. As soon as a contact occurs, a current is flowing in the touch screen and a schmitt trigger detects the voltage in the resistor. The Touch Screen Interrupt configuration is entered by programming the bit PENDET in the “TSADCC Mode Register”. If this bit is written at 1, the switch on XP and the switch on the resistor are both closed, except when a touch screen conversion is in progress. To complete the circuit, a programmable debouncer is placed at the output of the schmitt trigger. This debouncer is programmable at 1 ADC Clock period, useful when the system is running at Slow Clock, or at up to 2 15 ADC Clock periods, but better used to filter noise on the Touch 831 6289C–ATARM–28-May-09 Screen panel when the system is running at high speed. The debouncer length can be selected by programming the field PENDBC in “TSADCC Mode Register”. Figure 43-4. Touch Screen Pen Detect XP VDDANA XM GND To the ADC VDDANA YP YM GND PENDBC Debouncer Pen Interrupt GND The Touch Screen Pen Detect can be used to generate a TSADCC interrupt to wake up the system or it can be programmed to trig a conversion, so that a position can be measured as soon as a contact is detected if the TSADCC is programmed for an operating mode involving the Touch Screen. The Pen Detect generates two types of status, reported in the “TSADCC Status Register”: • the bit PENCNT is set as soon as a current flows for a time over the debouncing time as defined by PENDBC and remains set until TSADCC_SR is read. • the bit NOCNT is set as soon as no current flows for a time over the debouncing time as defined by PENDBC and remains set until TSADCC_SR is read. Both bits are automatically cleared as soon as the Status Register TSADCC_SR is read, and can generate an interrupt by writing accordingly the “TSADCC Interrupt Enable Register”. 43.7 Conversion Results When a conversion is completed, the resulting 8-bit or 10-bit digital value is right-aligned and stored in the “TSADCC Channel Data Register x (x = 0..5)” of the current channel and in the “TSADCC Last Converted Data Register”. The channel EOC bit and the bit DRDY in the “TSADCC Status Register” are both set. If the PDC channel is enabled, DRDY rising triggers a data transfer. In any case, either EOC and DRDY can trigger an interrupt. Reading one of the “TSADCC Channel Data Register x (x = 0..5)” registers clears the corresponding EOC bit. Reading “TSADCC Last Converted Data Register” clears the DRDY bit and the EOC bit corresponding to the last converted channel. 832 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Figure 43-5. EOCx and DRDY Flag Behavior Write the ADC_CR with START = 1 Read the ADC_CDRx Write the ADC_CR with START = 1 Read the ADC_LCDR CHx (ADC_CHSR) EOCx (ADC_SR) SHTIM Conversion Time SHTIM Conversion Time DRDY (ADC_SR) If the “TSADCC Channel Data Register x (x = 0..5)” is not read before further incoming data is converted, the corresponding Overrun Error (OVRE) flag is set in the “TSADCC Status Register”. In the same way, new data converted when DRDY is high sets the bit GOVRE (General Overrun Error) in the “TSADCC Status Register”. The OVRE and GOVRE flags are automatically cleared when the “TSADCC Status Register”is read. Figure 43-6. GOVRE and OVREx Flag Behavior Read ADC_SR ADTRG CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR ADC_CDR0 ADC_CDR1 Undefined Data Undefined Data Undefined Data Data A Data A Data B Data C Data C Data B EOC0 (ADC_SR) SHTIM Conversion SHTIM Conversion Read ADC_CDR0 EOC1 (ADC_SR) SHTIM Conversion Read ADC_CDR1 GOVRE (ADC_SR) DRDY (ADC_SR) OVRE0 (ADC_SR) 833 6289C–ATARM–28-May-09 Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in TSADCC_SR are unpredictable. 834 AT91SAM9R64/RL64 Preliminary 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.8 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the “TSADCC Control Register” with the bit START at 1. The hardware trigger can be selected by the filed TRGMOD in the TSADCC Trigger Register (TSADCC_TRGR) between: • an edge, either rising or falling or any, detected on the external trigger pin TSADTRG • the Pen Detect, depending on how the PENDET bit is set in the “TSADCC Mode Register” • a continuous trigger, meaning the TSADCC restarts the next sequence as soon as it finishes the current one, in this case, only one software trigger is required at the beginning • a periodic trigger, which is defined by programming the field TRGPER in the “TSADCC Trigger Register” Enabling hardware triggers does not disable the software trigger functionality. Thus, if a hardware trigger is selected, the start of a conversion can still be initiated by the software trigger. 43.9 Operating Modes The Touch Screen ADC Controller features several operating modes, each defining a conversion sequence: • The ADC Mode: at each trigger, all the enabled channels are converted • The Touch Screen Mode: at each trigger, the touch screen inputs are converted with the switches accordingly set and the results are processed and stored in the corresponding data registers The Operating Mode of the TSADCC is programmed in the field TSAMOD in the “TSADCC Mode Register”. The conversion sequences for each Operating Mode are described in the following paragraphs. The conversion sequencer, combined with the Sleep Modes, allows automatic processing with minimum processor intervention and optimized power consumption. In any case, the sequence starts with a trigger event. Note: The reference voltage pins always remain connected in normal mode as in sleep mode. 43.9.1 ADC Mode In the ADC Mode, the active channels are defined by the “TSADCC Channel Status Register”, which is defined by writing the “TSADCC Channel Enable Register” and “TSADCC Channel Disable Register”. The results are stored in the “TSADCC Channel Data Register x (x = 0..5)” and in the “TSADCC Last Converted Data Register”, so that data transfers by using the PDC are possible. At each trigger, the following sequence is performed: 4. If SLEEP is set, wake up the ADC cell and wait for the Startup Time. 5. If Channel 0 is enabled, convert Channel 0 and store result in both TSADCC_CDR0 and TSADCC_LCDR. 6. If Channel 1 is enabled, convert Channel 1 and store result in both TSADCC_CDR1 and TSADCC_LCDR. 835 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 7. If Channel 2 is enabled, convert Channel 2 and store result in both TSADCC_CDR2 and TSADCC_LCDR. 8. If Channel 3 is enabled, convert Channel 3 and store result in both TSADCC_CDR3 and TSADCC_LCDR. 9. If Channel 4 to Channel 5 are enabled, convert the Channels and store result in the corresponding TSADCC_CDRx and TSADCC_LCDR. 10. If SLEEP is set, sleep down the ADC cell. If the PDC is enabled, all the converted data are transferred contiguously in the memory buffer. The bit LOWRES defines which resolution is used, either 8-bit or 10-bit, and thus the width of the PDC memory buffer. 43.9.2 Touch Screen Mode Writing TSAMOD to “Touch Screen Only Mode” automatically enables the touch screen pins as analog inputs, and thus disables the digital function of the corresponding pins. In Touch Screen Mode, the channels 0 to 3 corresponding to the Touch Screen inputs are automatically activated and the bits CH0 to CH3 are automatically set in the “TSADCC Channel Status Register”. The remaining channels can be either enabled or disabled by the user and their conversions are performed at the end of each touch screen sequence. The resolution is forced to 10 bits, regardless of the LOWRES bit setting. At each trigger, the following sequence is performed: 1. If SLEEP is set, wake up the ADC cell and wait for the Startup Time. 2. Close the switches on the inputs XP and XM during the Sample and Hold Time. 3. Convert Channel XM and store the result in TSADCC_CDR1. 4. Close the switches on the inputs XP and XM during the Sample and Hold Time. 5. Convert Channel XP, subtract TSADCC_CDR1 from the result and store the subtraction result in both TSADCC_CDR0 and TSADCC_LCDR. 6. Close the switches on the inputs XP and XM during the Sample and Hold Time. 7. Convert Channel YP, subtract TSADCC_CDR1 from the result and store the subtraction result in both TSADCC_CDR1 and TSADCC_LCDR. 8. Close the switches on the inputs YP and YM during the Sample and Hold Time. 9. Convert Channel YM and store the result in TSADCC_CDR3. 10. Close the switches on the inputs YP and YM during the Sample and Hold Time. 11. Convert Channel YP, subtract TSADCC_CDR3 from the result and store the subtraction result in both TSADCC_CDR2 and TSADCC_LCDR. 12. Close the switches on the inputs YP and YM during the Sample and Hold Time. 13. Convert Channel XP, subtract TSADCC_CDR3 from the result and store the subtraction result in both TSADCC_CDR3 and TSADCC_LCDR. 14. If Channel 4 to Channel 5 are enabled, convert the Channels and store result in the corresponding TSADCC_CDRx and TSADCC_LCDR. 15. If SLEEP is set, sleep down the ADC cell. The resulting buffer is 16 bits wide and its structure stored in memory is: 1. XP - XM 2. YP - XM 836 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 3. YP - YM 4. XP - YM 5. AD4 to AD5 if enabled. The vertical position can be easily calculated by dividing the data at offset 0 (XP - XM) by the data at offset 1 (YP - XM). The horizontal position can be easily calculated by dividing the data at offset 2 (YP - YM) by the data at offset 3 (XP - YM). 837 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10 Touch Screen ADC Controller (TSADCC) User Interface Table 43-2. Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 - 0xFC Register Mapping Register Control Register Mode Register Trigger Register Touch Screen Register Channel Enable Register Channel Disable Register Channel Status Register Status Register Last Converted Data Register Interrupt Enable Register Interrupt Disable Register Interrupt Mask Register Channel Data Register 0 Channel Data Register 1 Channel Data Register 2 Channel Data Register 3 Channel Data Register 4 Channel Data Register 5 Reserved Name TSADCC_CR TSADCC_MR TSADCC_TRGR TSADCC_TSR TSADCC_CHER TSADCC_CHDR TSADCC_CHSR TSADCC_SR TSADCC_LCDR TSADCC_IER TSADCC_IDR TSADCC_IMR TSADCC_CDR0 TSADCC_CDR1 TSADCC_CDR2 TSADCC_CDR3 TSADCC_CDR4 TSADCC_CDR5 – Access Write-only Read-write Read-write Read-write Write-only Write-only Read-only Read-only Read-only Write-only Write-only Read-only Read-only Read-only Read-only Read-only Read-only Read-only – Reset – 0x0000_0000 0x0000_0000 0x0000_0000 – – 0x0000_0000 0x000C_0000 0x0000_0000 – – 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 0x0000_0000 – 838 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.1 TSADCC Control Register Register Name: TSADCC_CR Access Type: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – – START SWRST • SWRST: Software Reset 0 = No effect. 1 = Resets the TSADCC simulating a hardware reset. • START: Start Conversion 0 = No effect. 1 = Begins analog-to-digital conversion. 839 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.2 TSADCC Mode Register Register Name: TSADCC_MR Access Type: 31 Read/Write 30 29 28 27 26 25 24 PENDBC 23 22 21 20 19 18 SHTIM 17 16 – 15 14 13 12 STARTUP 11 10 9 8 – 7 – 6 5 4 3 PRESCAL 2 1 0 – PENDET SLEEP LOWRES – – TSAMOD • TSAMOD: Touch Screen ADC Mode TSAMOD 0 1 2 3 Touch Screen ADC Operating Mode ADC Mode Touch Screen Only Mode Reserved Reserved • LOWRES: Resolution Selection LOWRES 0 1 Selected Resolution 10-bit resolution 8-bit resolution This option is only valid in ADC mode. • SLEEP: Sleep Mode SLEEP 0 1 Selected Mode Normal Mode Sleep Mode • PRESCAL: Prescaler Rate Selection ADCCLK = MCK / ( (PRESCAL+1) * 2 ) • PENDET: Pen Detect Selection 0: Disable the Touch screen pins as analog inputs 1: enable the Touch screen pins as analog inputs • STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCCLK • SHTIM: Sample & Hold Time for ADC Channels 840 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary Programming 0 for SHTIM gives a Sample & Hold Time equal to (2/ADCCLK). Sample & Hold Time = (SHTIM+1) / ADCCLK • PENDBC: Pen Detect debouncing period Period = 2PENDBC/ADCCLK 841 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.3 TSADCC Trigger Register Register Name: TSADCC_TRGR Access Type: 31 Read/Write 30 29 28 27 26 25 24 TRGPER 23 22 21 20 19 18 17 16 TRGPER 15 14 13 12 11 10 9 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – TRGMOD • TRGMOD: Trigger Mode TRGMOD 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Selected Trigger Mode No trigger, only software trigger can start conversions External Trigger Rising Edge External Trigger Falling Edge External Trigger Any Edge Pen Detect Trigger (shall be selected only if PENDET is set and TSAMOD = Touch Screen only mode) Periodic Trigger (TRGPER shall be initiated appropriately) Continuous Mode Reserved • TRGPER: Trigger Period Effective only if TRGMOD defines a Periodic Trigger Defines the periodic trigger period, with the following equations: Trigger Period = (TRGPER+1) / ADCCLK 842 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.4 TSADCC Touch Screen Register Register Name: TSADCC_TSR Access Type: 31 Read/Write 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 19 18 TSSHTIM 17 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – – – – – – – • TSSHTIM: Sample & Hold Time for Touch Screen Channels Programming 0 for TSSHTIM gives a Touch Screen Sample & Hold Time equal to (2/ADCCLK). Touch Screen Sample & Hold Time = (TSSHTIM+1) / ADCCLK 43.10.5 TSADCC Channel Enable Register Register Name: TSADCC_CHER Access Type: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Enable 0 = No effect. 1 = Enables the corresponding channel. 843 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.6 TSADCC Channel Disable Register Register Name: TSADCC_CHDR Access Type: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Disable 0 = No effect. 1 = Disables the corresponding channel. Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conversion, its associated data and its corresponding EOC and OVRE flags in TSADCC_SR are unpredictable. 844 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.7 TSADCC Channel Status Register Register Name: TSADCC_CHSR Access Type: 31 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – – CH5 CH4 CH3 CH2 CH1 CH0 • CHx: Channel x Status 0 = Corresponding channel is disabled. 1 = Corresponding channel is enabled. 845 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.8 TSADCC Status Register Register Name: TSADCC_SR Access Type: 31 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 NOCNT 13 PENCNT 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 – 7 – 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 – – EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion x 0 = Corresponding analog channel is disabled, or the conversion is not finished. 1 = Corresponding analog channel is enabled and conversion is complete. • OVREx: Overrun Error x 0 = No overrun error on the corresponding channel since the last read of TSADCC_SR. 1 = There has been an overrun error on the corresponding channel since the last read of TSADCC_SR. • DRDY: Data Ready 0 = No data has been converted since the last read of TSADCC_LCDR. 1 = At least one data has been converted and is available in TSADCC_LCDR. • GOVRE: General Overrun Error 0 = No General Overrun Error occurred since the last read of TSADCC_SR. 1 = At least one General Overrun Error has occurred since the last read of TSADCC_SR. • ENDRX: End of RX Buffer 0 = The Receive Counter Register has not reached 0 since the last write in TSADCC_RCR or TSADCC_RNCR. 1 = The Receive Counter Register has reached 0 since the last write in TSADCC_RCR or TSADCC_RNCR. • RXBUFF: RX Buffer Full 0 = TSADCC_RCR or TSADCC_RNCR have a value other than 0. 1 = Both TSADCC_RCR and TSADCC_RNCR have a value of 0. • PENCNT: Pen Contact 0 = No contact has been detected since the last read of TSADCC_SR or PENDET is at 0. 1 = At least one contact has been detected since the last read of TSADCC_SR. • NOCNT: No Contact 0 = No contact loss has been detected since the last read of TSADCC_SR or PENDET is at 0. 1 = At least one contact loss has been detected since the last read of TSADCC_SR. 846 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.9 TSADCC Channel Data Register x (x = 0..5) Register Name: TSADCC_CDR0..TSADCC_CDR5 Access Type: 31 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 DATA 0 DATA • DATA: Channel Data The analog-to-digital conversion data is placed into this register at the end of a conversion of the corresponding channel and remains until a new conversion on the same channel is completed. 847 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.10 TSADCC Last Converted Data Register Register Name: TSADCC_LCDR Access Type: 31 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 LDATA 0 LDATA • LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion on any analog channel and remains until a new conversion on any analog channel is completed. 43.10.11 TSADCC Interrupt Enable Register Register Name: TSADCC_IER Access Type: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 NOCNT 13 PENCNT 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 – 7 – 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 – – EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion Interrupt Enable x • OVREx: Overrun Error Interrupt Enable x • DRDY: Data Ready Interrupt Enable • GOVRE: General Overrun Error Interrupt Enable • ENDRX: End of Receive Buffer Interrupt Enable • RXBUFF: Receive Buffer Full Interrupt Enable • PENCNT: Pen Contact • NOCNT: No Contact 0 = No effect. 1 = Enables the corresponding interrupt. 848 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.12 TSADCC Interrupt Disable Register Register Name: TSADCC_IDR Access Type: 31 Write-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 NOCNT 13 PENCNT 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 – 7 – 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 – – EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion Interrupt Disable x • OVREx: Overrun Error Interrupt Disable x • DRDY: Data Ready Interrupt Disable • GOVRE: General Overrun Error Interrupt Disable • ENDRX: End of Receive Buffer Interrupt Disable • RXBUFF: Receive Buffer Full Interrupt Disable • PENCNT: Pen Contact • NOCNT: No Contact 0 = No effect. 1 = Disables the corresponding interrupt. 849 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 43.10.13 TSADCC Interrupt Mask Register Register Name: TSADCC_IMR Access Type: 31 Read-only 30 29 28 27 26 25 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 NOCNT 13 PENCNT 12 RXBUFF 11 ENDRX 10 GOVRE 9 DRDY 8 – 7 – 6 OVRE5 5 OVRE4 4 OVRE3 3 OVRE2 2 OVRE1 1 OVRE0 0 – – EOC5 EOC4 EOC3 EOC2 EOC1 EOC0 • EOCx: End of Conversion Interrupt Mask x • OVREx: Overrun Error Interrupt Mask x • DRDY: Data Ready Interrupt Mask • GOVRE: General Overrun Error Interrupt Mask • ENDRX: End of Receive Buffer Interrupt Mask • RXBUFF: Receive Buffer Full Interrupt Mask • PENCNT: Pen Contact • NOCNT: No Contact 0 = The corresponding interrupt is disabled. 1 = The corresponding interrupt is enabled. 850 6289C–ATARM–28-May-09 AT91SAM9R64/RL64 Preliminary 44. AT91SAM9R64/RL64 Electrical Characteristics 44.1 Absolute Maximum Ratings Absolute Maximum Ratings *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 44-1. Operating Temperature (Industrial)...............-40° C to +85°C Storage Temperature .................................. -60°C to +150°C Voltage on Input Pins with Respect to Ground ................................. -0.3V to +4.0V Maximum Operating Voltage (VDDCORE and VDDBU).............................................. 1.5V Maximum Operating Voltage (VDDOSC, VDDPLL, VDDIOMx and VDDIOPx)............ 4.0V Total DC Output Current on all I/O lines ................... 500 mA 44.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified. Table 44-2. Symbol VVDDCORE VVDDBU VVDDPLLA VVDDPLLB ΔVVDDPLLB IVDDPLLB VVDDIOM VVDDIOP VVDDUTMII VVDDUTMIC VVDDANA DC Characteristics Parameter DC Supply Core DC Supply Backup DC Supply PLLA DC Supply PLLB Ripple on VVDDPLLB Current Supply DC Supply Memory I/Os DC Supply Peripheral I/Os USB UTMI+ Interface Power Supply USB UTMI+ Core Power Supply ADC Analog Power Supply Input Low-level Voltage VVDDIO from 3.0V to 3.6V VVDDIO from 1.65V to 1.95V rms value, from 10k Hz to 10 MHz Normal operating mode 1.65 Selectable by software in Bus Matrix 3.0 3.0 3.0 1.08 3.0 -0.3 -0.3 3.3 3.3 3.3 1.2 3.3 3.6 3.6 3.6 1.32 3.6 0.8 0.3 x VVDDIO V V V V V V V 1.8 Conditions Min 1.08 1.08 3.0 1.08 Typ 1.2 1.2 3.3 1.2 Max 1.32 1.32 3.6 1.32 10 30 1.95 Units V V V V mV mA V VIL 851 6289C–ATARM–28-May-09 Table 44-2. Symbol DC Characteristics (Continued) Parameter Conditions VVDDIO = VVDDIOM or VVDDIOP from 3.0V to 3.6V VVDDIO = VVDDIOM or VVDDIOP from 1.65V to 1.95V IO Max, VVDDIO from 3.0V to 3.6V Min 2.0 0.7 x VVDDIO Typ Max VVDDIO +0.3V VVDDIO +0.3V 0.4 0.1 0.4 VVDDIO 0.4 VVDDIO 0.1 VVDDIO 0.4 70 100 175 8 250 450 µA TA =85°C TA =25°C TA =85°C 4 4000 5 µA 30 kOhm mA Units V V V V V V V VIH Input High-level Voltage VOL Output Low-level Voltage CMOS (IO