AT93C56A-10PU-2.7

1. Features • Low-voltage and Standard-voltage Operation – 2.7 (VCC = 2.7V to 5.5V) – 1.8 (VCC = 1.8V to 5.5V) User-selectable Internal Organization – 2K: 256 x 8 or 128 x 16 – 4K: 512 x 8 or 256 x 16 Three-wire Serial Interface Sequential Read Operation 2 MHz Clock Rate (5V) Self-timed Write Cycle (10 ms Max) High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years Automotive Devices Available 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP and 8-ball dBGA2 Packages • • • • • • Three-wire Serial EEPROM 2K (256 x 8 or 128 x 16) 4K (512 x 8 or 256 x 16) • • 2. Description The AT93C56A/66A provides 2048/4096 bits of serial electrically erasable programmable read-only memory (EEPROM) organized as 128/256 words of 16 bits each (when the ORG pin is connected to VCC) and 256/512 words of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operations are essential. The AT93C56A/66A is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8lead EIAJ SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead TSSOP, and 8-ball dBGA2 packages. The AT93C56A/66A is enabled through the Chip Select pin (CS) and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a read instruction at DI, the address is decoded and the data is clocked out serially on the data output pin DO. The write cycle is completely self-timed and no separate erase cycle is required before write. The write cycle is only enabled when the part is in the Erase/Write Enable State. When CS is brought “high” following the initiation of a write cycle, the DO pin outputs the Ready/Busy status of the part. The AT93C56A/66A is available in 2.7V to 5.5V and 1.8V to 5.5V versions. AT93C56A AT93C66A 3378M–SEEPR–7/08 Table 2-1. Pin Name CS SK DI DO GND VCC ORG NC Pin Configurations Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Internal Organization No Connect 8-ball dBGA2 VCC NC ORG GND 8 7 6 5 1 2 3 4 8-lead SOIC CS SK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG GND CS SK DI DO Bottom view 8-lead Ultra Thin mini-MAP (MLP 2x3) VCC NC ORG GND 8 7 6 5 1 2 3 4 CS SK DI DO CS SK DI DO 8-lead PDIP 1 2 3 4 8 7 6 5 VCC NC ORG GND Bottom view 8-lead Ultra Lead Frame Land Grid Array (ULA) VCC NC ORG GND 8 7 6 5 1 2 3 4 CS SK DI DO CS SK DI DO 8-lead TSSOP 1 2 3 4 8 7 6 5 VCC NC ORG GND Bottom view 3. Absolute Maximum Ratings* Operating Temperature ......................................−55°C to +125°C Storage Temperature .........................................−65°C to +150°C Voltage on Any Pin with Respect to Ground ........................................ −1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A Figure 3-1. Block Diagram Note: When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the x 16 organization is selected. 3 3378M–SEEPR–7/08 Table 3-1. Pin Capacitance(Note:) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted) Symbol COUT CIN Note: Test Conditions Output Capacitance (DO) Input Capacitance (CS, SK, DI) 1. This parameter is characterized and is not 100% tested. Max 5 5 Units pF pF Conditions VOUT = 0V VIN = 0V Table 3-2. DC Characteristics Applicable over recommended operating range from: TAI = −40°C to +85°C, VCC = +1.8V to +5.5V, VCC = +1.8V to +5.5V (unless otherwise noted) Symbol VCC1 VCC2 VCC3 ICC ISB1 ISB2 ISB3 IIL IOL VIL1 VIH1(Note:) VIL2(Note:) VIH2(Note:) VOL1 VOH1 VOL2 VOH2 Note: (Note:) Parameter Supply Voltage Supply Voltage Supply Voltage Test Condition Min 1.8 2.7 4.5 READ at 1.0 MHz Typ Max 5.5 5.5 5.5 Unit V V V mA mA µA µA µA µA µA V V V V 0.5 0.5 0.4 6.0 10.0 0.1 0.1 −0.6 2.0 −0.6 VCC x 0.7 2.0 2.0 1.0 10.0 15.0 3.0 3.0 0.8 VCC + 1 VCC x 0.3 VCC + 1 0.4 Supply Current Standby Current Standby Current Standby Current Input Leakage Output Leakage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output Low Voltage Output High Voltage VCC = 5.0V VCC = 1.8V VCC = 2.7V VCC = 5.0V VIN = 0V to VCC VIN = 0V to VCC 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 2.7V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 2.7V WRITE at 1.0 MHz CS = 0V CS = 0V CS = 0V IOL = 2.1 mA IOH = −0.4 mA IOL = 0.15 mA IOH = −100 µA VCC − 0.2 2.4 0.2 V V 1. VIL min and VIH max are reference only and are not tested. 4 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A Table 3-3. AC Characteristics Applicable over recommended operating range from TAI = −40°C to + 85°C, VCC = As Specified, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Symbol fSK Parameter SK Clock Frequency SK High Time SK Low Time Minimum CS Low Time CS Setup Time DI Setup Time CS Hold Time DI Hold Time Output Delay to “1” Output Delay to “0” CS to Status Valid CS to DO in High Impedance Write Cycle Time (Note:) Test Condition 4.5V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V Relative to SK Relative to SK Relative to SK Relative to SK AC Test AC Test AC Test AC Test CS = VIL 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V 2.7V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 5.5V Min 0 0 0 250 1000 250 1000 250 1000 50 200 100 400 0 100 400 Typ Max 2 1 0.25 Units MHz tSKH tSKL tCS tCSS tDIS tCSH tDIH tPD1 tPD0 tSV tDF tWP Endurance ns ns ns ns ns ns ns 250 1000 250 1000 250 1000 150 400 ns ns ns ns ms Write Cycles 0.1 1M 3 10 5.0V, 25°C Note: 1. This parameter is characterized and is not 100% tested. 5 3378M–SEEPR–7/08 Table 3-4. Instruction Set for the AT93C56A and AT93C66A Op Code 10 00 11 01 00 Address x8 A8 – A0 11XXXXXXX A8 – A0 A8 – A0 10XXXXXXX x 16 A7 – A0 11XXXXXX A7 – A0 A7 – A0 10XXXXXX D7 – D0 D15 – D0 x8 Data x 16 Comments Reads data stored in memory, at specified address. Write enable must precede all programming modes. Erases memory location An – A0. Writes memory location An – A0. Erases all memory locations. Valid only at VCC = 4.5V to 5.5V. D7 – D0 D15 – D0 Writes all memory locations. Valid only at VCC = 5.0V ±10% and Disable Register cleared. Disables all programming instructions. Instruction READ EWEN ERASE WRITE ERAL SB 1 1 1 1 1 WRAL EWDS Note: 1 1 00 00 01XXXXXXX 00XXXXXXX 01XXXXXX 00XXXXXX The X’s in the address field represent don’t care values and must be clocked. 6 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A 4. Functional Description The AT93C56A/66A is accessed via a simple and versatile three-wire serial communication interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit (logic “1”) followed by the appropriate Op Code and the desired memory address location. READ (READ): The Read (READ) instruction contains the address code for the memory location to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A supports sequential read operations. The device will automatically increment the internal address pointer and clock out the next memory location as long as Chip Select (CS) is held high. In this case, the dummy bit (logic “0”) will not be clocked out between memory locations, thus allowing for a continuous stream of data to be read. ERASE/WRITE (EWEN): T o assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruction is executed or VCC power is removed from the part. ERASE (ERASE): The Erase instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO indicates that the selected memory location has been erased, and the part is ready for another instruction. WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle tWP starts after the last bit of data is received at serial data input pin DI. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). A logic “0” at DO indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the part is ready for further instructions. A READY/BUSY status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle tWP. ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The ERAL instruction is valid only at VCC = 5.0V ± 10%. WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (tCS). The WRAL instruction is valid only at VCC = 5.0V ± 10%. ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the READ instruction is independent of both the EWEN and EWDS instructions and can be executed at any time. 7 3378M–SEEPR–7/08 5. Timing Diagrams Figure 5-1. Synchronous Data Timing Note: 1. This is the minimum SK period. Table 5-1. Organization Key for Timing Diagrams AT93C56A (2K) AT93C66A (4K) x8 A8 D7 x 16 A7 D15 I/O AN DN Notes: x8 A8 (1) x 16 A7 (2) D7 D15 1. A8 is a DON’T CARE value, but the extra clock is required. 2. A7 is a DON’T CARE value, but the extra clock is required. Figure 5-2. READ Timing CS tCS SK DI DO High Impedance 8 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A Figure 5-3. EWEN Timing CS tCS SK DI 1 0 0 1 1 ... Figure 5-4. EWDS Timing CS tCS SK DI 1 0 0 0 0 ... Figure 5-5. WRITE Timing CS tCS SK DI 1 0 1 AN ... A0 DN ... D0 DO HIGH IMPEDANCE BUSY READY tWP 9 3378M–SEEPR–7/08 Figure 5-6. WRAL Timing(1) CS tCS SK DI 1 0 0 0 1 ... DN ... D0 DO HIGH IMPEDANCE BUSY READY tWP Note: 1. Valid only at VCC = 4.5V to 5.5V. Figure 5-7. ERASE Timing tCS CS CHECK STATUS STANDBY SK DI 1 1 1 AN AN-1 AN-2 ... A0 tSV tDF HIGH IMPEDANCE READY DO HIGH IMPEDANCE BUSY tWP 10 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A Figure 5-8. ERAL Timing(1) tCS CS CHECK STATUS STANDBY SK DI 1 0 0 1 0 tSV tDF HIGH IMPEDANCE READY DO HIGH IMPEDANCE BUSY tWP Note: 1. Valid only at VCC = 4.5V to 5.5V. 11 3378M–SEEPR–7/08 6. AT93C56A Ordering Information(1) Ordering Code AT93C56A-10PU-2.7 AT93C56A-10PU-1.8(2) AT93C56A-10SU-2.7(2) AT93C56A-10SU-1.8(2) AT93C56AW-10SU-2.7(2) AT93C56AW-10SU-1.8(2) AT93C56A-10TU-2.7(2) AT93C56A-10TU-1.8(2) AT93C56AU3-10UU-1.8(2) AT93C56AD3-10DH-1.8(3) AT93C56AY1-10YU-1.8(2) (Not recommended for new design) AT93C56AY6-10YH-1.8(3) AT93C56A-W1.8-11(4) Notes: (2) Package 8P3 8P3 8S1 8S1 8S2 8S2 8A2 8A2 8U3-1 8D3 8Y1 8Y6 Die Sales Operation Range Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) Industrial Temperature (−40°C to 85°C) 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. “U” designates Green package + RoHS compliant. 3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Marketing. Package Type 8P3 8S1 8S2 8A2 8U3-1 8Y1 8Y6 8D3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-ball, die Ball Grid Array Package (dBGA2) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm) 8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA) Options −2.7 −1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V) 12 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A 7. AT93C66A Ordering Information(1) Ordering Code AT93C66A-10PU-2.7 AT93C66A-10PU-1.8(2) AT93C66A-10SU-2.7(2) AT93C66A-10SU-1.8(2) AT93C66AW-10SU-2.7(2) AT93C66AW-10SU-1.8(2) AT93C66A-10TU-2.7(2) AT93C66A-10TU-1.8(2) AT93C66AU3-10UU-1.8(2) AT93C66AD3-10DH-1.8(3) AT93C66AY1-10YU-1.8(2) (Not recommended for new design) AT93C66AY6-10YH-1.8(3) AT93C66A-W1.8-11(4) Notes: (2) Package 8P3 8P3 8S1 8S1 8S2 8S2 8A2 8A2 8U3-1 8D3 8Y1 8Y6 Die Sale Operation Range Lead-free/Halogen-free/ Industrial Temperature (−40°C to 85°C) Industrial Temperature (−40°C to 85°C) 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics table. 2. “U” designates Green package + RoHS compliant. 3. “H” designates Green package + RoHS compliant, with NiPdAu Lead Finish. 4. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial EEPROM Marketing. Package Type 8P3 8S1 8S2 8A2 8U3-1 8Y1 8Y6 8D3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) 8-ball, die Ball Grid Array Package (dBGA2) 8-lead, 4.90 mm x 3.00 mm Body, Dual Footprint, Non-leaded, Miniature Array Package (MAP) 8-lead, 2.00 mm x 3.00 mm Body, 0.50 mm Pitch, Ultra Thin Mini-MAP, Dual No Lead package (DFN), (MLP 2x3 mm) 8-lead, 1.80 mm x 2.20 mm Body, Ultra Lead Frame Land Grid Array (ULA) Options −2.7 −1.8 Low-voltage (2.7V to 5.5V) Low-voltage (1.8V to 5.5V) 13 3378M–SEEPR–7/08 8. Packaging Information 8.1 8P3 – PDIP E E1 1 N Top View c eA End View D e D1 A2 A SYMBOL COMMON DIMENSIONS (Unit of Measure = inches) MIN NOM MAX NOTE A A2 b b2 b3 c D 0.115 0.014 0.045 0.030 0.008 0.355 0.005 0.300 0.240 0.310 0.250 0.100 BSC 0.300 BSC 0.115 0.130 0.130 0.018 0.060 0.039 0.010 0.365 0.210 0.195 0.022 0.070 0.045 0.014 0.400 2 5 6 6 3 3 b2 b3 4 PLCS L D1 E E1 e eA L b 0.325 0.280 4 3 Side View 4 0.150 2 Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information. 2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3. 3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch. 4. E and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion. 6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 01/09/02 2325 Orchard Parkway San Jose, CA 95131 TITLE 8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP) DRAWING NO. 8P3 REV. B R 14 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A 8.2 8S1 – JEDEC SOIC C 1 E E1 N ∅ L Top View End View e B A SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN 1.35 0.10 0.31 0.17 4.80 3.81 5.79 NOM – – – – – – – 1.27 BSC 0.40 0˚ – – 1.27 8˚ MAX 1.75 0.25 0.51 0.25 5.00 3.99 6.20 NOTE A1 A A1 b C D D E1 E Side View e L ∅ Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 10/7/03 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) DRAWING NO. 8S1 REV. B R 8.3 8S2 – EIAJ SOIC 15 3378M–SEEPR–7/08 8.3 8Y6 - Mini-MAP (MLP 2x3) A D2 b (8X) Pin 1 Index Area E2 E Pin 1 ID L (8X) D A2 A3 A1 e (6X) 1.50 REF. COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL D E D2 E2 A A1 A2 A3 L e b 0.20 0.20 1.40 0.0 MIN NOM 2.00 BSC 3.00 BSC 1.50 0.02 0.20 REF 0.30 0.50 BSC 0.25 0.30 2 0.40 1.60 1.40 0.60 0.05 0.55 MAX NOTE Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-229, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 8/26/05 2325 Orchard Parkway San Jose, CA 95131 DRAWING NO. TITLE 8Y6, 8-lead 2.0 x 3.0 mm Body, 0.50 mm Pitch, Utlra Thin Mini-Map, 8Y6 Dual No Lead Package (DFN) ,(MLP 2x3) REV. C R 16 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A 8.4 8A2 – TSSOP 3 21 Pin 1 indicator this corner E1 E L1 N L Top View End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN 2.90 NOM 3.00 6.40 BSC 4.30 – 0.80 0.19 4.40 – 1.00 – 0.65 BSC 0.45 0.60 1.00 REF 0.75 4.50 1.20 1.05 0.30 4 3, 5 MAX 3.10 NOTE 2, 5 b A D E E1 A e D A2 A2 b e Side View L L1 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 5/30/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 8A2 REV. B 17 3378M–SEEPR–7/08 8.5 8U3-1 – dBGA2 E D 1. b PIN 1 BALL PAD CORNER A1 A2 Top View PIN 1 BALL PAD CORNER A Side View 4 1 (d1) 2 3 d 8 e 7 6 5 COMMON DIMENSIONS (Unit of Measure = mm) (e1) SYMBOL MIN 0.713 0.09 0.40 0.20 NOM 0.79 0.14 0.45 0.25 1.50 BSC 2.00 BSC 0.50 BSC 0.25 REF 1.00 BSC 0.25 REF MAX 0.85 0.19 0.50 0.30 2 NOTE Bottom View 8 Solder Balls A A1 A2 b 1. This drawing is for general information only. 2. Dimension ‘b’ is measured at maximum solder ball diameter D E e e1 d d1 5/3/05 TITLE 1150E Cheyenne Mt. Blvd 8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch, Colorado Springs, CO 80906 Small Die Ball Grid Array Package (dBGA2) DRAWING NO. PO8U3-1 REV. b R 18 AT93C56A/66A 3378M–SEEPR–7/08 AT93C56A/66A 8.6 8D3 - ULA D 8 7 6 5 e1 b L PIN #1 ID E PIN #1 ID 0.10 0.15 1 2 3 4 A A1 e BOTTOM VIEW b TOP VIEW SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN – 0.00 1.70 2.10 0.15 NOM – – 1.80 2.20 0.20 0.40 TYP 1.20 REF MAX 0.40 0.05 1.90 2.30 0.25 NOTE A A1 D E b e e1 L 0.25 0.30 0.35 11/15/05 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE 8D3, 8-lead (1.80 x 2.20 mm Body) Ultra Leadframe Land Grid Array (ULLGA) D3 DRAWING NO. 8D3 REV. 0 R 19 3378M–SEEPR–7/08 9. Revision History Revision No. 3378M 3378L Date 7/2008 11/2007 Comments Updated Ordering Codes Updated to new template Added ULA package offering Removed DC/Don’t Connect and replaced with NC/No Conenct Adjusted size of Block diagram on pg. 2 Made all diagrams on pages 6-9 consistently the same size Corrected 8U3-1 3378K 12/2006 20 AT93C56A/66A 3378M–SEEPR–7/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support s_eeprom@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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