AT97SC3203S

1. Features • Full Trusted Computing Group (TCG) Trusted Platform Module (TPM) Version 1.2 • • • • • • • • • • • • Compatibility Single-chip Turnkey Solution Hardware Asymmetric Crypto Engine 2048-bit RSA® Sign in 500 ms AVR® RISC Microprocessor Internal EEPROM Storage for RSA Keys 100 kHz System Management Bus (SMBus™) Two-wire Interface Secure Hardware and Firmware Design and Chip Layout True Random Number Generator (RNG) - FIPS 140-2 Compliant NV Storage Space for 1280 bytes of user defined data 3.3V Supply Voltage 28-lead TSSOP Package or 40-lead QFN Package 0–70°C Temperature Range Trusted Platform Module AT97SC3203S SMBus Two-Wire Interface Summary Note: See the full datasheet for detailed design information. 2. Description The AT97SC3203S is a fully integrated security module designed to be integrated into embedded systems. It implements version 1.2 of the Trusted Computing Group (TCG) specification for Trusted Platform Modules (TPM). The TPM includes a cryptographic accelerator capable of computing a 2048-bit RSA signature in 500 ms and a 1024-bit RSA signature in 100 ms. Performance of the SHA-1 accelerator is 50 µs per 64-byte block. In most cases, TCG key generation operations will be completed using a proprietary mechanism in less than 1 msec. 5132BS–TPM–1/08 Note: This is a summary document. A complete document is available under NDA. For more information, please contact your local Atmel sales office. Figure 2-1. Pin Name VCC SB3V VBAT GND RESET# SMBDAT SMBCLK AVRCLK Xtall/32K in XtalO GPIO6 TestI TestBI ATest NC NBO Pin Configurations Description 3.3V Supply Voltage Standby 3.3V Supply Voltage 2.5–4.0V Battery Input Ground Reset Input Active Low SMBus Data Input/Output SMBus Clock Input 33-MHz AVR Clock Input 32.768 kHz Crystal Input 32.768 kHz Crystal Output General Purpose Input/Output Test Input (disabled) Test Input (disabled) Atmel Test Pin No Connect Not Bonded Out 28-pin TSSOP 6.1 mm x 9.7 mm Body 0.65 mm Pitch SMBCLK 40-pin QFN 6.0 mm x 6.0 mm Body 0.50 mm Pitch SMBDA T ATest ATest NBO NBO NBO NBO NBO ATest NBO 30 ATest 29 GND 28 VCC 27 ATest 26 ATest 25 AVRCLK 24 ATest 23 VCC 22 GND RESET# 5132BS–TPM–1/08 SMBDAT SMBCLK ATest GND SB3V GPIO6 NC TestI TestBI VCC GND VBAT Xtall/32K in XtalO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ATest ATest ATest GND VCC ATest ATest AVRCLK ATest VCC GND ATest RESET# ATest ATest GND SB3 V GPIO6 NC TestI TestBI VCC GND VBAT 1 2 3 4 5 6 7 8 9 40 39 38 37 36 35 34 33 32 31 10 21 ATest 11 12 13 14 15 16 17 18 19 20 XTALI/32K in NBO XTALO NBO NBO NBO NBO 2 AT97SC3203S NBO AT97SC3203S Figure 2-2. AT97SC3203S Block Diagram ROM Program EEPROM Program 33 MHz AVR Clock Input SMBDAT SMBCLK GPIO6 VBAT 32.768 kHz RTC (Optional) AVR 8-Bit RISC CPU SRAM SMBus Interface GPIO RNG EEPROM Data CRYPTO Engine Timer Physical Security Circuitry 2. Description (continued) Communication to and from the TPM occurs through a modified 100-kHz SMBus two-wire interface. The TPM includes a hardware random number generator, including a FIPS-approved Pseudo Random Number Generator, that is used for key generation and TCG protocol functions. The RNG is also available to the system to generate random numbers that may be needed during normal operation. The chip uses a dynamic internal memory management scheme to store multiple RSA keys. Other than the standard TCG commands (TPM_FlushSpecific, TPM_Loadkey2), no system intervention is required to manage this internal key cache. Full documentation for TCG primitives can be found on the TCG Web site located at www.trustedcomputinggroup.org . This specification includes only mechanical, electrical and SMBus protocol information. 3 5132BS–TPM–1/08 3. Ordering Information Table 3-1. Ordering Information Package 28A3 (28-pin TSSOP) 40ML1 (40-pin QFN) Lead-free, RoHS Lead-free, RoHS Operation Range Commercial (0° to 70° C) Commercial (0° to 70° C) (1) (1) Ordering Code AT97SC3203S AT97SC3203S Note: 1. Please see the AT97SC3203S datasheet addendum for the complete catalog number ordering code. 4 AT97SC3203S 5132BS–TPM–1/08 AT97SC3203S 4. Package Drawing 28A3 – TSSOP b L L1 E E1 e Top View End View COMMON DIMENSIONS (Unit of Measure = mm) A D A2 SYMBOL D E E1 MIN 9.60 NOM 9.70 8.10 BSC MAX 9.80 NOTE 2, 5 6.00 – 0.80 0.19 6.10 – 1.00 – 0.65 BSC 6.20 1.20 1.05 0.30 3, 5 Side View A A2 b e L L1 4 0.45 0.60 1.00 REF 0.75 Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation DB for additional information. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 1/8/02 R 2325 Orchard Parkway San Jose, CA 95131 TITLE 28A3, 28-lead, 6.1 x 9.7 mm Body, 0.65 pitch, Thin Shrink Small Outline Package (TSSOP) DRAWING NO. 28A3 REV. A 5 5132BS–TPM–1/08 40ML1 - QFN A D N A2 A3 1 2 3 E Pin 1 Indicator A1 Top View L 0 Side View D2 SYMBOL COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM 6.00 BSC 6.00 BSC 3.95 3.95 0.0 4.10 4.10 0.85 0.01 0.65 0.20 REF 0.30 0.40 0.50 BSC 0.18 0.23 0.30 2 0.50 4.25 4.25 0.90 0.05 0.70 MAX NOTE E2 D E D2 3 2 1 b E2 A A1 A2 Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-220, Variation WJJD-2, for proper dimensions, tolerances, datums, etc. 2. Dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. R 2325 Orchard Parkway San Jose, CA 95131 6 AT97SC3203S 5132BS–TPM–1/08 N e PIN1 ID A3 L e b Bottom View 9/27/07 TITLE 40ML1, 40-lead 6.0 x 6.0 mm Body, 0.50 mm Pitch, Molded Quad Flat No Lead Package (QFN) Punched DRAWING NO. 40ML1 REV. C AT97SC3203S Revision History Doc. Rev. 5132BS Date 1/2008 Comments Implemented revision history. 7 5132BS–TPM–1/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support pcsecurity@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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