ATA3742P3-TGSY

Features • IC Distinguishes the Signal Strength of Several Transmitters via RSSI (Received Signal Strength Indicator) Output • Minimal External Circuitry Requirements, No RF Components on the PC Board Except • • • • • • • • • • • • Matching to the Receiver Antenna High Sensitivity, Especially at Low Data Rates Sensitivity Reduction Possible Even While Receiving Fully Integrated VCO Low Power Consumption Due to Configurable Self-polling With a Programmable Time Frame Check Supply Voltage 4.5V to 5.5V Operating Temperature Range –40°C to +105°C Single-ended RF Input for Easy Adaptation to λ / 4 Antenna or Printed Antenna on PCB Low-cost Solution Due to High Integration Level ESD Protection According to MIL-STD. 883 (4 KV HBM) High Image Frequency Suppression Due to 1 MHz IF in Conjunction With a SAW Front-end Filter (Up to 40 dB Achievable With Newer SAWs) Communication to Microcontroller Possible via a Single, Bi-directional Data Line Power Management (Polling) is also Possible by Means of a Separate Pin via the Microcontroller UHF ASK/FSK Receiver ATA3742 1. Description The ATA3742 is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester or Bi-phase code. The receiver is well-suited to operate with Atmel®’s PLL RF transmitter IC U2741B. Its main applications in the area of wireless control are telemetering, security technology, tire-pressure monitoring and keyless-entry systems. It can be used in the frequency receiving range of f0 = 300 MHz to 450 MHz for ASK or FSK data transmission. All the statements made in this datasheet refer both to 433.92 MHz and 315 MHz applications. 4900B–RKE–11/07 Figure 1-1. System Block Diagram UHF ASK/FSK Remote control transmitter UHF ASK/FSK Remote control receiver ATA3742 1 to 3 Demod Encoder ATARx9x PLL Antenna XTO VCO Antenna PLL XTO Control Microcontroller 1 Li cell U2741B Keys Power amp. LNA VCO Figure 1-2. Block Diagram VS FSK/ASK CDEM RSSI FSK/ASK Dem_out Demodulator and Data Filter RSSI Limiter out ENABLE IF Amp AVCC AGND MODE DGND 4th Order FE CLK DVCC Sensitivity reduction Polling circuit and control logic TEST 50 kΩ DATA SENS LPF 3 MHz MIXVCC Standby Logic LFGND LNAGND IF Amp LFVCC LPF 3 MHz VCO XTO XTO f LNA_IN LNA :64 LF 2 ATA3742 4900B–RKE–11/07 ATA3742 2. Pin Configuration Figure 2-1. Pinning SO20 SENS FSK/ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN NC 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 DATA ENABLE TEST RSSI MODE DVCC XTO LFGND LF LFVCC Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Description Symbol SENS FSK/ASK CDEM AVCC AGND DGND MIXVCC LNAGND LNA_IN NC LFVCC LF LFGND XTO DVCC MODE RSSI TEST ENABLE DATA Function Sensitivity-control resistor Selecting FSK/ASK Low: FSK, High: ASK Lower cut-off frequency of the data filter Analog power supply Analog ground Digital ground Power supply mixer High-frequency ground LNA and mixer RF input Not connected Power supply VCO Loop filter Ground VCO Crystal oscillator Digital power supply Selecting 433.92 MHz/315 MHz Low: 4.90625 MHz (USA) High: 6.76438 (Europe) Output of the RSSI amplifier Test pin, during operation at GND Enables the polling mode Low: polling mode off (sleep mode) High: polling mode on (active mode) Data output/configuration input 3 4900B–RKE–11/07 3. RF Front End The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1 MHz IF signal. As seen in Figure 1-2 on page 2, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer and an RF amplifier. The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency fXTO. The VCO (voltage-controlled oscillator) generates the drive voltage frequency fLO for the mixer. fLO is dependent on the voltage at pin LF. fLO is divided by a factor of 64. The divided frequency is compared to fXTO by the phase frequency detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage VLF for the VCO. By means of that configuration, VLF is controlled in a way that fLO / 64 is equal to fXTO. If fLO is determined, fXTO can be calculated using the following formula: fXTO = fLO / 64 The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. The crystal should be connected to GND via the capacitor CL according to Figure 3-1. The value of that capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of fXTO and hereby of fLO. When designing the system in terms of receiving bandwidth, the accuracy of the crystal and the XTO must be considered. Figure 3-1. PLL Peripherals DVCC XTO LFGND LF LFVCC VS R1 820Ω VS CL C9 4.7 nF C10 1 nF The passive loop filter connected to pin LF is designed for a loop bandwidth of BLoop = 100 kHz. This value for BLoop exhibits the best possible noise performance of the LO. Figure 3-1 shows the appropriate loop filter components to achieve the desired loop bandwidth. If the filter components are changed for any reason, please note that the maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit check may no longer be possible since fLO cannot settle in time before the bit check starts to evaluate the incoming data stream. In that case, self-polling will also not work. fLO is determined by the RF input frequency f RF and the IF frequency fIF using the following formula: fLO = fRF – fIF 4 ATA3742 4900B–RKE–11/07 ATA3742 To determine fLO, the construction of the IF filter must be considered at this point. The nominal IF frequency is fIF = 1 MHz. To achieve a good accuracy of the filter's corner frequencies, the filter is tuned by the crystal frequency fXTO. This means that there is a fixed relation between fIF and fLO that depends on the logic level at pin MODE. This is described by the following formulas: f LO MODE = 0 (USA) f IF = --------314 f LO MODE = 1 (Europe) f IF = ----------------432.92 The relation is designed to achieve the nominal IF frequency of fIF = 1 MHz for most applications. For applications where f RF = 315 MHz, MODE must be set to “0”. In the case of fRF = 433.92 MHz, MODE must be set to “1”. For other RF frequencies, fIF is not equal to 1 MHz. fIF is then dependent on the logical level at pin MODE and on fRF. Table 3-1 summarizes the different conditions. The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of that pin is provided in the electrical parameters. The parasitic board inductances and capacitances also influence the input matching. The RF receiver ATA3742 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network. A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity. If a SAW is implemented into the input network, a mirror frequency suppression of ∆PRef = 40 dB can be achieved. There are SAWs available that exhibit a notch at ∆f = 2 MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used. Figure 3-2 on page 6 shows a typical input matching network for f RF = 315 MHz and fRF = 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates input matching to 50Ω without a SAW. The input matching networks shown in Figure 3-3 on page 6 are the reference networks for the parameters given in the “Electrical Characteristics” on page 26. Table 3-1. Conditions Calculation of LO and IF Frequency Local Oscillator Frequency fLO = 314 MHz fLO = 432.92 MHz f RF f LO = ------------------1 1 + --------314 f RF f LO = --------------------------1 1 + ----------------432.92 Intermediate Frequency fIF = 1 MHz fIF = 1 MHz f LO f IF = --------314 fRF = 315 MHz, MODE = 0 fRF = 433.92 MHz, MODE = 1 300 MHz < fRF < 365 MHz, MODE = 0 365 MHz < fRF < 450 MHz, MODE = 1 f LO f IF = ----------------432.92 5 4900B–RKE–11/07 Figure 3-2. Input Matching Network With SAW Filter 8 LNAGND 8 LNAGND ATA3742 C3 22 pF L 25 nH 9 LNA_IN C3 47 pF C16 100 pF C17 8.2 pF L3 27 nH TOKO® LL2012 F27NJ L 25 nH 9 ATA3742 LNA_IN C16 100 pF C17 22 pF L3 TOKO® LL2012 F47NJ fRF = 433.92 MHz fRF = 315 MHz 47 nH RFIN C2 8.2 pF TOKO® LL2012 F33NJ 1 L2 33 nH 2 RFIN IN IN_GND 3, 4 B3555 OUT OUT_GND 5 6 C2 10 pF TOKO® LL2012 F82NJ 1 L2 82 nH 2 IN IN_GND B3551 OUT OUT_GND 5 6 CASE_GND 7, 8 CASE_GND 3, 4 7, 8 Figure 3-3. Input Matching Network Without SAW Filter fRF = 433.92 MHz 8 fRF = 315 MHz LNAGND 8 LNAGND ATA3742 9 15 pF 25 nH LNA_IN 9 33 pF 25 nH ATA3742 LNA_IN RFIN 3.3 pF 22 nH 100 pF TOKO® LL2012 F22NJ RFIN 3.3 pF 39 nH 100 pF TOKO® LL2012 F39NJ Please note that for all coupling conditions (see Figure 3-2 and Figure 3-3), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily printed on the PCB. This configuration improves the sensitivity of the receiver by about 1 dB to 2 dB. 6 ATA3742 4900B–RKE–11/07 ATA3742 4. Analog Signal Processing 4.1 IF Amplifier The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is fIF = 1 MHz for applications where fRF = 315 MHz or fRF = 433.92 MHz is used. For other RF input frequencies, see Table 3-1 on page 5 to determine the center frequency. The receiver ATA3742-M3 employs an IF bandwidth of BIF = 600 kHz and can be used together with the U2741B in FSK and ASK mode. 4.2 RSSI Amplifier The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is ∆RRSSI = 60 dB. If the RSSI amplifier is operated within its linear range, the best signal-to-noise ratio (SNR) is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the SNR is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity. In FSK mode, the SNR is not affected by the dynamic range of the RSSI amplifier. The output voltage of the RSSI amplifier is internally compared to a threshold voltage VTh_red. VTh_red is determined by the value of the external resistor RSense. RSense is connected between pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. By this means, it is possible to operate the receiver at a lower sensitivity. 4.3 Pin RSSI The output voltage of the RSSI amplifier (VRSSI) is available at pin RSSI. Using the RSSI output signal, the signal strength of different transmitters can be distinguished. The usable input-power range PRef is –100 dBm to –55 dBm. The temperature coefficient TC of VRSSI is typically –2.2 mV/K. Due to TC and gain tolerance, it is not possible to find out the absolute level of each transmitter, but the level differences can be used to distinguish several transmitters. As illustrated in Figure 4-2 on page 8, the RSSI output voltage is not constant over the temperature range. Figure 4-1 illustrates an application that realizes a temperature compensation of VRSSI. 7 4900B–RKE–11/07 Figure 4-1. Temperature Compensation of VRSSI VRSSI_temp_comp. I ~ Ig(VLNA_IN) 180 kΩ RSSI 50 kΩ Bmin = 60 I VRSSI 47 kΩ ATA3742 Figure 4-2. RSSI Characteristic 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 -110 -100 -90 -80 -70 -60 -50 105°C -40°C 25°C min max VRSSI (V) PREF (dBm) If RSense is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity is defined by the value of RSense, the maximum sensitivity by the signal-to-noise ratio of the LNA input. The reduced sensitivity is dependent on the signal strength at the output of the RSSI amplifier. Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 3-3 on page 6 and exhibits the best possible sensitivity. 8 ATA3742 4900B–RKE–11/07 ATA3742 RSense can be connected to VS or GND via a microcontroller. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern shown in Figure 4-3 is issued at pin DATA to indicate that the receiver is still active. Figure 4-3. Steady L State Limited DATA Output Pattern DATA tmin2 tDATA_L_max 4.4 FSK/ASK Demodulator and Data Filter The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK. Logic “L” sets the demodulator to FSK mode; logic “H” sets it into ASK mode. In ASK mode, an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good signal-to-noise ratio is achieved. This circuit also implies the effective suppression of any kind of inband noise signals or competing transmitters. If the SNR exceeds 10 dB, the data signal can be detected properly. The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥ 20 kHz. Lower values may be used, but the sensitivity of the receiver will be reduced. The minimum usable deviation is dependent on the selected baud rate. In FSK mode, only BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be detected if the SNR exceeds 2 dB. The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the SNR as its pass band can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order high-pass and a 1st-order low-pass filter. The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula: 1 f cu_DF = -----------------------------------------------------------2 × π × 30 k Ω × CDEM In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in “Electrical Characteristics” on page 26. The values are slightly different for ASK and FSK mode. The cut-off frequency of the low-pass filter is defined by the selected baud rate range (BR_Range). BR_Range is defined in the OPMODE register (refer to Section “Configuration of the Receiver” on page 20). BR_Range must be set in accordance to the used baud rate. The ATA3742 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition. 9 4900B–RKE–11/07 Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (tee_sig). These limits are defined in the electrical characteristics. They should not be exceeded to maintain full sensitivity of the receiver. 4.5 Receiving Characteristics The RF receiver ATA3742 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 4-4 on page 10. This example relates to ASK mode. FSK mode exhibits similar behavior. Note that the mirror frequency is reduced by 40 dB. The plots are printed relatively to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered. When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA3742. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the ATA3742 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode. Figure 4-4. Receiving Frequency Response 0 -10 -20 -30 without SAW dP (dB) -40 -50 -60 -70 -80 -90 -100 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 with SAW df (mHz) 10 ATA3742 4900B–RKE–11/07 ATA3742 5. Polling Circuit and Control Logic The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time, the bit check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected does the receiver remain active and transfer the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time, resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time. All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate, etc. Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontroller, or it can be operated by up to three uni-directional ports. 5.1 Basic Clock Cycle of the Digital Circuitry The complete timing of the digital circuitry and the analog filtering is derived from one clock. According to Figure 5-1 on page 11, this clock cycle TClk is derived from the crystal oscillator (XTO) in combination with a divider. The division factor is controlled by the logical state at pin MODE. As described in Section “RF Front End” on page 4, the frequency of the crystal oscillator (fXTO) is defined by the RF input signal (fRFin), which also defines the operating frequency of the local oscillator (fLO). Figure 5-1. Generation of the Basic Clock Cycle TCLK MODE Divider :14/10 fXTO 16 L: USA (:10) H: Europe (:14) DVCC 15 XTO XTO 14 Pin MODE can now be set in accordance with the desired clock cycle TClk. TClk controls the following application-relevant parameters: • Timing of the polling circuit including bit check • Timing of the analog and digital signal processing • Timing of the register programming • Frequency of the reset marker • IF filter center frequency (fIF0) 11 4900B–RKE–11/07 Most applications are dominated by two transmission frequencies: fSend = 315 MHz is mainly used in the USA, fSend = 433.92 MHz in Europe. In order to ease the usage of all TClk-dependent parameters, the electrical characteristics display three conditions for each parameter. • Application USA (fXTO = 4.90625 MHz, MODE = L, TClk = 2.0383 µs) • Application Europe (fXTO = 6.76438 MHz, MODE = H, TClk = 2.0697 µs) • Other applications (TClk is dependent on fXTO and on the logical state of pin MODE. The electrical characteristic is given as a function of TClk). The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle TXClk is defined by the following formulas for further reference: BR_Range = BR_Range0: BR_Range1: BR_Range2: BR_Range3: TXClk = 8 × TClk TXClk = 4 × TClk TXClk = 2 × TClk TXClk = 1 × TClk 5.2 Polling Mode As seen in Figure 5-3 on page 15, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period TSleep while consuming low current of IS = ISoff. During the start-up period, TStartup, all signal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit by bit, looking for a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period TBitcheck. This period varies check by check as it is a statistical process. An average value for TBitcheck is given in the electrical characteristics. During TStartup and TBitcheck the current consumption is IS = ISon. The average current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as: I Soff × T Sleep + I Son × ( T Startup + T Bitcheck ) I Spoll = -----------------------------------------------------------------------------------------------------------T Sleep + T Startup + T Bitcheck During TSleep and TStartup, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst is dependent on the polling parameters TSleep, TStartup, TBitcheck and the startup time of a connected microcontroller (TStart,microcontroller). TBitcheck thus depends on the actual bit rate and the number of bits (NBitcheck) to be tested. The following formula indicates how to calculate the preburst length. TPreburst ≥ TSleep + TStartup + TBitcheck + TStart_microcontroller 12 ATA3742 4900B–RKE–11/07 ATA3742 5.2.1 Sleep Mode The length of period TSleep is defined by the 5-bit word Sleep of the OPMODE register, the extension factor X Sleep a ccording to Table 5-7 on page 22, and the basic clock cycle T Clk . It is calculated to be: TSleep = Sleep × XSleep × 1024 × TClk In US and European applications, the maximum value of TSleep is about 60 ms if XSleep is set to “1”. The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting XSleep to 8. XSleep can be set to 8 by bit XSleepStd or by bit XSleepTemp, resulting in a different mode of action as described below: XSleepStd = 1 implies the standard extension factor. The sleep time is always extended. XSleepTemp = 1 implies the temporary extension factor. The extended sleep time is used as long as every bit check is OK. If the bit check fails once, this bit is set back to “0”, automatically resulting in a regular sleep time. This functionality can be used to save current in the presence of a modulated disturber similar to an expected transmitter signal. The connected microcontroller is rarely activated in that condition. If the disturber disappears, the receiver switches back to regular polling and is again sensitive to appropriate transmitter signals. The highest register value of Sleep sets the receiver into a permanent sleep condition (see Table 5-6 on page 22). The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line. 5.2.2 Bit-check Mode In bit-check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of these edge-to-edge tests, before the receiver switches to receiving mode, is also programmable. Configuring the Bit Check Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one bit. This is valid for Manchester, bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable NBitcheck in the OPMODE register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If NBitcheck is set to a higher value, the receiver is less likely to switch to receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if NBitcheck is set to a lower value. In polling mode, the bit check time is not dependent on NBitcheck. Figure 5-1 on page 11 shows an example where 3 bits are tested successfully and the data signal is transferred to pin DATA. According to Figure 5-2, the time window for the bit check is defined by two separate time limits. If the edge-to-edge time tee is in between the lower bit check limit TLim_min and the upper bit check limit TLim_max, the check will be continued. If tee is smaller than TLim_min or tee exceeds TLim_max, the bit check will be terminated and the receiver switches to sleep mode. 5.2.3 13 4900B–RKE–11/07 Figure 5-2. Valid Time Window for Bit Check 1/fSig Dem_out Tee TLim_min TLim_max For best noise immunity it is recommended to use a low span between TLim_min and TLim_max. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A “11111...” or “10101...” sequence in Manchester or bi-phase is a good choice given this recommendation. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge time tee. Using preburst patterns that contain various edge-to-edge time periods, the bit check limits must be programmed according to the required span. The bit check limits are determined by means of the formula below: TLim_min = Lim_min × TXClk TLim_max = (Lim_max – 1) × TXClk Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register. Using the above formulas, Lim_min and Lim_max can be determined according to the required TLim_min, TLim_max and TXClk. The time resolution when defining TLim_min and TLim_max is TXClk. The minimum edge-to-edge time tee (tDATA_L_min, tDATA_H_min) is defined according to Section “Receiving Mode” on page 17. Due to this, the lower limit should be set to Lim_min ≥ 10. The maximum value of the upper limit is Lim_max = 63. 14 ATA3742 4900B–RKE–11/07 ATA3742 Figure 5-3. Polling Mode Flow Chart Sleep Mode: All circuits for signal processing are disabled. Only XTO and Polling logic are enabled. Output level on pin IC_ACTIVE = > low IS = ISoff TSleep = Sleep × XSleep × 1024 × TClk Sleep: 5-bit word defined by Sleep0 to Sleep4 in OPMODE register Extension factor defined by XSleepTemp according to Table 5-7 Basic clock cycle defined by fXTO and pin MODE Is defined by the selected baud-rate range and TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register. XSleep: Start-up Mode: The signal processing circuits are enabled. After the start-up time (TStartup) all circuits are in stable condition and ready to receive. Output level on pin IC_ACTIVE = > high IS = ISon TStartup TClk: TStartup: Bit-check Mode: The incoming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise it is set to Sleep mode. Output level on pin IC_ACTIVE = > high IS = ISon TBit-check NO Bit Check OK ? XBit-check: Depends on the result of the bit check. If the bit check is ok, TBit-check depends on the number of bits to be checked (NBit-check) and on the utilized data rate. If the bit check fails, the average time period for that check depends on the selected baud-rate range and on TClk. The baud-rate range is defined by Baud0 and Baud1 in the OPMODE register. YES Receiving Mode: The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via pin DATA or ENABLE IS = ISon OFF Command 15 4900B–RKE–11/07 Figure 5-4. Timing Diagram for Complete Successful Bit Check Bit check ok (Number of checked Bits: 3) Enable IC Bit check 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit Dem_out Data Startup mode Bit check mode Receiving mode Figure 5-5. Timing Diagram During Bit Check (Lim_min = 14, Lim_max = 24) Enable IC Bit check 1/2 Bit Dem_out Bit check counter 0 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 Bit check ok Bit check ok TStartup 1/2 Bit 1/2 Bit TXCLK Figure 5-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min) (Lim_min = 14, Lim_max = 24) Enable IC Bit check 1/2 Bit Dem_out Bit check counter 0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12 0 Bit check failed (CV_Lim_ < Lim_min) Startup mode Bit check mode Sleep mode Figure 5-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max) (Lim_min = 14, Lim_max = 24) Enable IC Bit check 1/2 Bit Dem_out Bit check counter 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 0 Bit check failed (CV_Lim_ ≥ Lim_max) Start up mode Bit check mode Sleep mode 16 ATA3742 4900B–RKE–11/07 ATA3742 Figure 5-5 on page 16 to Figure 5-7 illustrate the bit check for the default bit check limits Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during TStartup. The output of the ASK/FSK demodulator (Dem_out) is undefined during that period. When the bit check becomes active, the bit check counter is clocked with the cycle TXClk. Figure 5-5 on page 16 shows how the bit check proceeds if the bit check counter value CV_Lim is within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 5-6 on page 16, the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 5-7. 5.2.4 Duration of the Bit Check If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and TBitcheck varies for each check. Therefore, an average value for T Bitcheck i s given in the electrical characteristics. T Bitcheck depends on the selected baud rate range and on TClk. A higher baud rate range causes a lower value for TBitcheck resulting in a lower current consumption in polling mode. In the presence of a valid transmitter signal, TBitcheck is dependent on the frequency of that signal, fSig, and on the count of the checked bits, NBitcheck. A higher value for NBitcheck thereby results in a longer period for TBitcheck requiring a higher value for the transmitter preburst TPreburst. 5.3 Receiving Mode If the bit check is successful for all bits specified by NBitcheck, the receiver switches to receiving mode. As shown in Figure 5-4 on page 16, the internal data signal is switched to pin DATA in that case. A connected microcontroller can be woken up by the negative edge at pin DATA. The receiver stays in that condition until it is switched back to polling mode explicitly. 5.3.1 Digital Signal Processing The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud rate range (BR_Range). Figure 5-8 on page 18 illustrates how Dem_out is synchronized by the extended clock cycle TXClk. This clock is also used for the bit check counter. Data can change its state only after TXClk elapses. The edge-to-edge time period tee of the data signal as a result is always an integral multiple of TXClk. The minimum time period between two edges of the data signal is limited to tee ≥ TDATA_min. This implies an efficient suppression of spikes at the DATA output. At the same time, it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. TDATA_min is to some extent affected by the preceding edge-to-edge time interval tee as illustrated in Figure 5-9. If tee is in between the specified bit check limits, the following level is frozen for the time period TDATA_min = tmin1, in case of tee being outside that bit check limits TDATA_min = tmin2 is the relevant stable time period. The maximum time period for DATA to be Low is limited to TDATA_L_max. This function ensures a finite response time during programming or switching off the receiver via pin DATA. TDATA_L_max is thereby longer than the maximum time period indicated by the transmitter data stream. Figure 5-10 gives an example where Dem_out remains Low after the receiver is in receiving mode. 17 4900B–RKE–11/07 Figure 5-8. Synchronization of the Demodulator Output TXClk Clock bit check counter Dem_out DATA tee Figure 5-9. Debouncing of the Demodulator Output Dem_out DATA Lim_min ≤ CV_Lim < Lim_max tmin1 CV_Lim < Lim_min or CV_Lim ≥ Lim_max tee tmin2 tee Figure 5-10. Steady L State Limited DATA Output Pattern after Transmission Enable IC Bit check Dem_out DATA tmin2 Start-up mode Bit-check mode Receiving mode tDATA_L_max After the end of data transmission, the receiver remains active and random noise pulses appear at pin DATA. The edge-to-edge time period tee of the majority of these noise pulses is equal to or slightly higher than TDATA_min. 18 ATA3742 4900B–RKE–11/07 ATA3742 5.3.2 Switching the Receiver Back to Sleep Mode The receiver can be set back to polling mode via pin DATA or via pin ENABLE. When using pin DATA, this pin must be pulled to Low for the period t1 by the connected microcontroller. Figure 5-11 illustrates the timing of the OFF command (see also Figure 5-15 on page 24). The minimum value of t1 depends on BR_Range. The maximum value for t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. This item is explained in more detail in Section “Configuration of the Receiver” on page 20. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 of the OPMODE register to be “1”. Only one sync pulse (t3) is issued. The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command, the sleep time TSleep elapses. Note that the capacitive load at pin DATA is limited. The resulting time constant τ together with an optional external pull-up resistor may not be exceeded to ensure proper operation. If the receiver is set to polling mode via pin ENABLE, an “L” pulse (TDoze) must be issued at that pin. Figure 5-12 on page 20 illustrates the timing of that command. After the positive edge of this pulse, the sleep time TSleep elapses. The receiver remains in sleep mode as long as ENABLE is held to “L”. If the receiver is polled exclusively by a microcontroller, TSleep can be programmed to “0” to enable an instantaneous response time. This command is a faster option than via pin DATA, at the cost of an additional connection to the microcontroller. Figure 5-11. Timing Diagram of the OFF Command via Pin DATA t1 t2 t3 t4 t10 t5 Out1 (microcontroller) DATA (ATA3742) X t7 Serial bi-directional data line X Bit 1 ("1") (Start Bit) Receiving mode TSleep Startup mode OFF command 19 4900B–RKE–11/07 Figure 5-12. Timing Diagram of the OFF Command via Pin ENABLE TDoze toff TSleep ENABLE DATA (ATA3742) X Serial bi-directional data line X Receiving mode Startup mode 5.4 Configuration of the Receiver The ATA3742 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers. Table 5-2 on page 21 shows the structure of the registers. Refering to Table 5-1, bit 1 defines if the receiver is set back to polling mode via the OFF command (see Section “Receiving Mode” on page 17), or if it is programmed. Bit 2 represents the register address. It selects the appropriate register to be programmed. Table 5-1. Bit 1 1 0 0 Effect of Bit 1 and Bit 2 in Programming the Registers Bit 2 x 1 0 Action The receiver is set back to polling mode (OFF command) The OPMODE register is programmed The LIMIT register is programmed Table 5-3 on page 21 and the following illustrate the effect of the individual configuration words. The default configuration is highlighted for each word. BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim is used to define the bit check limits TLim_min and TLim_max as shown in Table 5-3 on page 21. 20 ATA3742 4900B–RKE–11/07 ATA3742 Table 5-2. Bit 1 Bit 2 OFF Command 1 OPMODE Register 0 0 1 1 BR_Range Baud1 0 Baud0 0 NBitcheck BitChk1 1 BitChk0 0 VPOUT POUT 0 Sleep4 0 Sleep3 1 Sleep Sleep2 0 Sleep1 1 Sleep0 1 XSleep XSleep Std 0 XSleep Temp 0 Effect of the Configuration Words Within the Registers Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 (Default) LIMIT Register 0 0 0 0 Lim_min Lim_max Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0 0 0 1 1 1 0 0 1 1 0 0 0 (Default) Table 5-3. Baud1 0 0 1 1 Effect of the Configuration Word BR_Range BR_Range Baud0 0 1 0 1 Baud Rate Range/Extension Factor for Bit Check Limits (XLim) BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default) XLim = 8 (Default) BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4 BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2 BR_Range3 (application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1 Table 5-4. Effect of the Configuration Word NBitcheck NBitcheck BitChk1 0 0 1 1 BitChk0 0 1 0 1 Number of Bits to be Checked 0 3 6 (Default) 9 Table 5-5. Effect of the Configuration Bit Reserved Reserved Bit 0 1 No Function (Reserved for Future Use) (Default) - 21 4900B–RKE–11/07 Table 5-6. Sleep4 0 0 0 0 . . . 0 . . . 1 1 1 Effect of the Configuration Word Sleep Sleep Sleep3 0 0 0 0 . . . 1 . . . 1 1 1 Sleep2 0 0 0 0 . . . 0 . . . 1 1 1 Sleep1 0 0 1 1 . . . 1 . . . 0 1 1 Sleep0 0 1 0 1 . . . 1 . . . 1 0 1 Start Value for Sleep Counter (TSleep = Sleep × XSleep × 1024 × TClk) 0 (Receiver is continuously polling until a valid signal occurs) 1 (TSleep ≈ 2 ms for XSleep = 1 in US/European applications) 2 3 . . . 11 (USA: TSleep = 22.96 ms, Europe: TSleep = 23.31 ms) (Default) . . . 29 30 31 (Permanent sleep mode) Table 5-7. Effect of the Configuration Word XSleep XSleep XSleepTemp 0 1 0 1 Extension Factor for Sleep Time (TSleep = Sleep × XSleep × 1024 × TClk) 1 (Default) 8 (XSleep is reset to 1 if bit check fails once) 8 (XSleep is set permanently) 8 (XSleep is set permanently) XSleepStd 0 0 1 1 Table 5-8. Effect of the Configuration Word Lim_min Lim_min Lim_min < 10 is not applicable Lower Limit Value for Bit Check (TLim_min = Lim_min × XLim × TClk) 0 1 0 1 0 . . . 1 0 1 10 11 12 13 14 (Default) (USA: TLim_min = 228 µs, Europe: TLim_min = 232 µs) . . . 61 62 63 1 1 0 0 1 . . . 0 1 1 0 0 0 0 0 . . . 1 1 1 0 0 0 0 0 . . . 1 1 1 1 1 1 1 1 . . . 1 1 1 0 0 1 1 1 . . . 1 1 1 22 ATA3742 4900B–RKE–11/07 ATA3742 Table 5-9. Effect of the Configuration Word Lim_max Lim_max Lim_max < 12 is not applicable 0 0 0 . . . 0 . . . 1 1 1 0 0 0 . . . 1 . . . 1 1 1 1 1 1 . . . 1 . . . 1 1 1 1 1 1 . . . 0 . . . 1 1 1 0 0 1 . . . 0 . . . 0 1 1 0 1 0 . . . 0 . . . 1 0 1 Upper Limit Value for Bit Check (TLim_max = (Lim_max – 1) × XLim × TClk) 12 13 14 . . . 24 (Default) = 375 µs, Europe: TLim_max = 381 µs) (USA: TLim_max . . . 61 62 63 5.4.1 Conservation of the Register Information The ATA3742 has an integrated power-on reset (POR) and brown-out detection circuitry to provide a mechanism to preserve the RAM register information. According to Figure 5-13, a power-on reset is generated if the supply voltage VS drops below the threshold voltage VThReset. The default parameters are programmed into the configuration registers in that condition. Once VS exceeds VThReset, the POR is canceled after the minimum reset period tRst. A POR is also generated when the supply voltage of the receiver is turned on. To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency fRM at a 50% duty cycle. RM can be canceled via an “L” pulse t1 at pin DATA. The RM implies the following characteristics: • fRM is lower than the lowest feasible frequency of a data signal. This means, RM cannot be misinterpreted by the connected microcontroller. • If the receiver is set back to polling mode via pin DATA, RM cannot be cancelled by accident if t1 is applied according to the proposal in the Section “Programming the Configuration Register” on page 24. By means of that mechanism, the receiver cannot lose its register information without communicating that condition via the reset marker RM. 23 4900B–RKE–11/07 Figure 5-13. Generation of the Power-on Reset VS VThreset POR tRst X DATA (ATA3742) 1/fRM Figure 5-14. Timing of the Register Programming t1 t2 t3 t4 t6 t7 t5 t9 t8 TSleep Out1 (microcontroller) DATA (ATA3742) X Serial bi-directional data line X Bit 1 ("0") (Start bit) Bit 2 ("1") (Register select) Programming frame Bit 13 ("0") (Poll 8) Bit 14 ("1") (Poll 8R) Receiving mode Startup mode 5.4.2 Programming the Configuration Register The configuration registers are programmed serially via the bi-directional data line according to Figure 5-14 and Figure 5-15. Figure 5-15. One-wire Connection to a Microcontroller ATA3742 Internal pull-up resistor Bi-directional data line DATA I/O Microcontroller DATA (ATA3742) Out1 (microcontroller) 24 ATA3742 4900B–RKE–11/07 ATA3742 To start programming, the serial data line DATA is pulled to “L” for the time period t1 by the microcontroller. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time period t7 during t5, the bit is set to “0”. If no programming pulse t7 is issued, this bit is set to “1”. All 14 bits are subsequently programmed in this way. The time frame to program a bit is defined by t6. Bit 14 is followed by the equivalent time window t9. During this window, the equivalent acknowledge pulse t8 (E_Ack) occurs if the just-programmed mode word is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case. Programming of a register is possible both during sleep and active mode of the receiver. During programming, the LNA, LO, low-pass filter, IF amplifier and the FSK/ASK Manchester demodulator are disabled. The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to “1”, it represents the OFF command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t1 , the following convention should be considered: • t1(min) < t1 < 1535 × TClk: [t1(min) is the minimum specified value for the relevant BR_Range] Programming (or the OFF command) is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming (or the OFF command) is not initiated, and the reset marker (RM) is still present at pin DATA. This period is generally used to switch the receiver to polling mode. In a reset condition, RM is not canceled by accident. • t1 > 5632 × TClk Programming (or the OFF command) is initiated in any case. RM is canceled if present. This period is used if the connected microcontroller detected RM. If a configuration register is programmed, this time period for t1 can generally be used. Note that the capacitive load at pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor may not be exceeded to ensure proper operation. 25 4900B–RKE–11/07 6. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Power dissipation Junction temperature Storage temperature Ambient temperature Maximum input level, input matched to 50Ω Symbol Ptot Tj Tstg Tamb Pin_max –55 –40 Min. Max. 450 150 +125 +105 10 Unit mW °C °C °C dBm 7. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 100 Unit K/W 8. Electrical Characteristics All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) 6.76438 Mhz Oscillator (Mode 1) Parameter Test Condition Symbol Min. Typ. Max. 4.90625 Mhz Oscillator (Mode 0) Min. Typ. Max. Min. Variable Oscillator Typ. Max. Unit Basic Clock Cycle of the Digital Circuitry Basic clock cycle Extended basic clock cycle Polling Mode Sleep and XSleep are defined in the OPMODE register BR_Range0 BR_Range1 BR_Range2 BR_Range3 Average bit-check time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3 Bit-check time for a valid input signal fSig NBitcheck = 0 NBitcheck = 3 NBitcheck = 6 NBitcheck = 9 Sleep × XSleep × 1024 × 2.0697 1855 1061 1061 663 Sleep × XSleep × 1024 × 2.0383 1827 1045 1045 653 Sleep × XSleep × 1024 × TClk 896.5 512.5 512.5 320.5 × TClk MODE = 0 (USA) MODE = 1 (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 TClk 2.0383 2.0697 16.6 8.3 4.1 2.1 16.3 8.2 4.1 2.0 1 / (fXTO / 10) 1 / (fXTO / 14) 8 × TClk 4 × TClk 2 × TClk 1 × TClk µs µs µs µs µs µs TXClk Sleep time TSleep ms Start-up time TStartup µs µs µs µs TBitcheck Time for Bit Check 0.45 0.24 0.14 0.14 0.47 0.26 0.16 0.15 ms ms ms ms TBitcheck 3 / fSig 6 / fSig 9 / fSig 3.5 / fSig 3 / fSig 6.5 / fSig 6 / fSig 9.5 / fSig 9 / fSig 3.5 / fSig 6.5 / fSig 9.5 / fSig TXClk 3 / fSig 6 / fSig 9 / fSig TXClk 3.5 / fSig 6.5 / fSig 9.5 / fSig ms ms ms ms 26 ATA3742 4900B–RKE–11/07 ATA3742 8. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) 6.76438 Mhz Oscillator (Mode 1) Parameter Test Condition Symbol Min. Typ. Max. 4.90625 Mhz Oscillator (Mode 0) Min. Typ. Max. Min. Variable Oscillator Typ. fXTO × 64 / 314 fXTO × 64 / 432.92 1.8 3.2 5.6 10.0 147 179 73 90 36.7 44.8 18.3 22.4 2136 1068 534 267 BR_Range0 × BR_Range1 × BR_Range2 × BR_Range3 × 2 µs / TClk 2 µs / TClk 2 µs / TClk 2 µs / TClk Max. Unit Receiving Mode Intermediate frequency Baud-rate range MODE=0 (USA) MODE=1 (Europe) BR_Range0 BR_Range1 BR_Range2 BR_Range3 BR_Range0 BR_Range1 BR_Range2 BR_Range3 fIF 1.0 1.8 3.2 5.6 149 182 75 91 37.3 45.5 18.6 22.8 2169 1085 542 271 1.0 1.0 1.8 3.2 5.6 10.0 1.0 1.8 3.2 5.6 MHz MHz kBaud kBaud kBaud kBaud µs µs µs µs µs µs µs µs µs µs µs µs BR_Range Minimum time period between edges at pin DATA (Figure 5-9 on page 18) Maximum low period at DATA (Figure 5-10 on page 18) OFF command at pin ENABLE (Figure 5-12 on page 20) TDATA_min tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk 9 × TXClk 11 × TXClk 131 × 131 × 131 × 131 × TXClk TXClk TXClk TXClk BR_Range0 BR_Range1 BR_Range2 BR_Range3 TDATA_L_max tDoze 3.1 3.05 1.5 × TClk µs Configuration of the Receiver Frequency of the reset marker (Figure 5-13 on page 24) BR_Range0 Programming BR_Range1 start pulse (Figure 5-11 BR_Range2 on page 19, Figure 5-14 on BR_Range3 page 24) after POR Programming delay period (Figure 5-11 on page 19, Figure 5-14 on page 24) 1 --------------------------------4096 × T CLK fRM 117.9 119.8 Hz 2188 1104 t1 561 290 11656 3176 3176 3176 3176 2155 1087 553 286 11479 3128 3128 3128 3128 1057 × TClk 533 × TClk 271 × TClk 140 × TClk 5632 × TClk 1535 × TClk 1535 × TClk 1535 × TClk 1535 × TClk µs t2 795 798 783 786 384.5 × TClk 385.5 × TClk µs 27 4900B–RKE–11/07 8. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) 6.76438 Mhz Oscillator (Mode 1) Parameter Synchroni-zati on pulse (Figure 5-11 on page 19, Figure 5-14 on page 24) Delay until the program window starts (Figure 5-11 on page 19, Figure 5-14 on page 24) Programming window (Figure 5-11 on page 19, Figure 5-14 on page 24) Time frame of a bit (Figure 5-14 on page 24) Programming pulse (Figure 5-11 on page 19, Figure 5-14 on page 24) Equivalent acknowledge pulse: E_Ack (Figure 5-14 on page 24) Equivalent time window (Figure 5-14 on page 24) OFF-bit programming window (Figure 5-11 on page 19) Test Condition Symbol Min. Typ. Max. 4.90625 Mhz Oscillator (Mode 0) Min. Typ. Max. Min. Variable Oscillator Typ. Max. Unit t3 265 261 128 × TClk µs t4 131 129 63.5 × TClk µs t5 530 522 256 × TClk µs t6 1060 1044 512 × TClk µs t7 133 529 131 521 64 × TClk 256 × TClk µs t8 265 261 128 × TClk µs t9 534 526 258 × TClk µs t10 930 916 449.5 × TClk µs 28 ATA3742 4900B–RKE–11/07 ATA3742 9. Electrical Characteristics All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Test Conditions Sleep mode (XTO and polling logic active) Current consumption IC active (start up, bit check, receiving mode) pin DATA = H LNA/mixer/IF amplifier input matched according to Figure 3-3 on page 6 Input matched according to Figure 3-3 on page 6, required according to I-ETS 300220 Input matching according to Figure 3-3 on page 6 at 433.92 MHz at 315 MHz Input matched according to Figure 3-3 on page 6, referred to RFin Input matched according to Figure 3-3 on page 6, BER ≤ 10-3, ASK mode Symbol ISoff ISon Min. Typ. 190 Max. 350 Unit µA 7.0 8.6 mA LNA Mixer Third-order intercept point IIP3 –28 dBm LO spurious emission at RFIn Noise figure LNA and mixer (DSB) LNA_IN input impedance 1 dB compression point (LNA, mixer, IF amplifier) ISLORF NF ZiLNA_IN IP1db –73 –57 dBm 7 1.0 || 1.56 1.3 || 1.0 –40 dB kΩ || pF kΩ || pF dBm Maximum input level Pin_max –28 –20 dBm dBm Local Oscillator Operating frequency range VCO Phase noise VCO/LO Spurious of the VCO VCO gain For best LO noise (design parameter) R1 = 820Ω C9 = 4.7 nF C10 = 1 nF The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to self-polling. XTO crystal frequency, appropriate load capacitance must be connected to XTAL 6.764375 MHz 4.90625 MHz Series resonance resistor of the crystal fXTO = 6.764 MHz 4.906 MHz fosc = 432.92 MHz at 1 MHz at 10 MHz at ±fXTO KVCO fVCO L (fm) 299 –93 –113 –55 190 449 –90 –110 –47 MHz dBC/Hz dBC/Hz dBC MHz/V Loop bandwidth of the PLL BLoop 100 kHz Capacitive load at pin LF CLF_tot 10 nF XTO operating frequency fXTO 6.764375 6.764375 6.764375 –30 ppm +30 ppm 4.90625 4.90625 4.90625 –30 ppm +30 ppm 150 220 MHz MHz Ω Ω RS 29 4900B–RKE–11/07 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Static capacitance of the crystal Analog Signal Processing Input matched according to Figure 3-3 on page 6 ASK (level of carrier) BER ≤ 10-3, fIF = 1 MHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5V BR_Range0 Input sensitivity ASK BR_Range1 BR_Range2 BR_Range3 Sensitivity variation ASK for the full operating range compared to Tamb = 25°C, VS = 5V Sensitivity variation ASK for full operating range including IF filter compared to Tamb = 25°C, VS = 5V fin = 433.92 MHz/315 MHz fIF = 1 MHz PASK = PRef_ASK + ∆PRef fin = 433.92 MHz/315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz PASK = PRef_ASK + ∆PRef Input matched according to Figure 3-3 on page 6, BER ≤ 10-3, fIF = 1 MHz fin = 433.92 MHz/315 MHz T = 25°C, VS = 5V BR_Range0 df ≥ ±20 kHz df ≥ ±30 kHz BR_Range1 df ≥ ±20 kHz df ≥ ±30 kHz fin = 433.92 MHz/315 MHz fIF = 1 MHz PFSK = PRef_FSK + ∆PRef fin = 433.92 MHz/315 MHz fIF = 0.86 MHz to 1.14 MHz fIF = 0.82 MHz to 1.18 MHz PFSK = PRef_FSK + ∆PRef The sensitivity of the receiver is higher for higher values of ∆fFSK BR_Range0 BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation ASK mode FSK mode ∆PRef ∆PRef Test Conditions Symbol Cxto Min. Typ. Max. 6.5 Unit pF Input sensitivity ASK PRef_ASK –108 –106.5 –106 –104 +2.5 –110 –108.5 –108 –106 –112 –110.5 –110 –108 –1.5 dBm dBm dBm dBm dB ∆PRef +5.5 +7.5 –1.5 –1.5 dB dB Input sensitivity FSK PRef_FSK Input sensitivity FSK –95.5 –96.5 –94.5 –95.5 +2.5 –97.5 –98.5 –96.5 –97.5 –99.5 –100.5 –98.5 –99.5 –1.5 dBm dBm dBm dBm dB Sensitivity variation FSK for the full operating range compared to Tamb = 25°C, VS = 5V Sensitivity variation FSK for full operating range including IF filter compared to Tamb = 25°C, VS = 5V ∆PRef +5.5 +7.5 –1.5 –1.5 dB dB FSK frequency deviation ∆fFSK 20 20 30 30 50 50 kHz kHz SNR to suppress inband noise signals Dynamic range RSSI amplifier SNRASK SNRFSK ∆RRSSI 10 2 60 12 3 dB dB dB 30 ATA3742 4900B–RKE–11/07 ATA3742 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Lower cut-off frequency of the data filter Test Conditions 1 f cu_DF = -----------------------------------------------------------2 × π × 30 k Ω × CDEM ASK mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 FSK mode BR_Range0 (Default) BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation Symbol fcu_DF Min. 0.11 Typ. 0.16 Max. 0.20 Unit kHz Recommended CDEM for best performance CDEM 39 22 12 8.2 27 15 nF nF nF nF nF nF Recommended CDEM for best performance CDEM BR_Range0 (Default) Maximum edge-to-edge time period of BR_Range1 the input data signal for full sensitivity BR_Range2 BR_Range3 Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3 tee_sig 1000 560 320 180 µs µs µs µs Upper cut-off frequency data filter fu 2.5 4.3 7.6 13.6 3.1 5.4 9.5 17.0 3.7 6.5 11.4 20.4 270 156 89 50 kHz kHz kHz kHz µs µs µs µs dBm (peak level) BR_Range0 (Default) Minimum edge-to-edge time period of BR_Range1 the input data signal for full sensitivity BR_Range2 BR_Range3 Reduced sensitivity RSense connected from pin Sens to VS, input matched according to Figure 3-3 on page 6 (VS = 5V, Tamb = 25°C) RSense = 56 kΩ, fin = 433.92 MHz, Reduced sensitivity RSense = 100 kΩ, fin = 433.92 MHz RSense = 56 kΩ, fin = 315 MHz RSense = 100 kΩ, fin = 315 MHz Reduced sensitivity variation over full operating range RSense = 56 kΩ RSense = 100 kΩ PRed = PRef_Red + ∆PRed Values relative to RSense = 56 kΩ RSense = 56 kΩ RSense = 68 kΩ RSense = 82 kΩ RSense = 100 kΩ RSense = 120 kΩ RSense = 150 kΩ PRed = PRef_Red + ∆PRed tee_sig PRef_Red –67 –76 –68 –77 ∆PRed 5 6 –72 –81 –73 –82 0 0 –77 –86 –78 –87 0 0 dBm dBm dBm dBm dB dB Reduced sensitivity variation for different values of RSense ∆PRed 0 –3.5 –6.0 –9.0 –11.0 –13.5 dB dB dB dB dB dB 31 4900B–RKE–11/07 9. Electrical Characteristics (Continued) All parameters refer to GND, Tamb = –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified. (VS = 5V, Tamb = 25°C) Parameters Threshold voltage for reset Digital Ports Data output - Saturation voltage LOW - Internal pull-up resistor - Maximum time constant - Maximum capacitive load FSK/ASK input - Low-level input voltage - High-level input voltage ENABLE input - Low-level input voltage - High-level input voltage MODE input - Low-level input voltage - High-level input voltage TEST input - Low-level input voltage Iol = 1 mA τ = CL (Rpup//RExt) without external pull-up resistor Rext = 5 kΩ FSK selected ASK selected Idle mode Active mode Division factor = 10 Division factor = 14 Test input must always be set to LOW VOI RPup τ CL CL VIl VIh VIl VIh VIl VIh VIl 39 0.08 50 0.3 61 2.5 41 540 0.2 × VS V kΩ µs pF pF V V V V V V V Test Conditions Symbol VThRESET Min. 1.95 Typ. 2.8 Max. 3.75 Unit V 0.8 × VS 0.8 × VS 0.2 × VS 0.8 × VS 0.2 × VS 0.2 × VS 32 ATA3742 4900B–RKE–11/07 ATA3742 10. Ordering Information Extended Type Number ATA3742P3-TGSY ATA3742P3-TGQY Package SO20 SO20 Remarks Tube, Pb-free Taped and reeled, Pb-free 11. Package Information Package SO20 Dimensions in mm 12.95 12.70 9.15 8.65 7.5 7.3 2.35 0.25 10.50 10.20 11 0.4 1.27 11.43 20 0.25 0.10 technical drawings according to DIN specifications 1 10 12. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4900B-RKE-11/07 History • Put datasheet in the newest template • Pb-free Logo on page 1 deleted 33 4900B–RKE–11/07 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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