Features
• PLL Transmitter IC with Single-ended Output • High Output Power (6 dBm) at 8.1 mA (315 MHz) and 8.5 mA (433 MHz) Typical Values • Divide by 24 (ATA5756) and 32 (ATA5757) Blocks for 13 MHz Crystal Frequencies and
for Low XTO Start-up Times
• Modulation Scheme ASK/FSK with Internal FSK Switch • Up to 20 kBaud Manchester Coding, Up to 40 kBaud NRZ Coding • Power-down Idle and Power-up Modes to Adjust Corresponding Current Consumption
through ASK/FSK/Enable Input Pins
• ENABLE Input for Parallel Usage of Controlling Pins in a 3-wire Bus System • CLK Output Switches ON if the Crystal Current Amplitude has Reached 35% to 80% of • • • •
its Final Value Crystal Oscillator Time Until CLK Output is Activated, Typically 0.6 ms Supply Voltage 2.0 V to 3.6 V in Operation Temperature Range of -40°C to +125°C ESD Protection at all Pins (4 kV HBM) Small Package TSSOP10
UHF ASK/FSK Transmitter ATA5756 ATA5757
Benefits
• Low Parasitic FSK Switch Integrated • Very Short and Reproducible Time to Transmit Typically < 0.85 ms • 13.125 MHz/13.56 MHz Crystals Give Opportunity for Small Package Sizes
1. Description
The ATA5756/ATA5757 is a PLL transmitter IC which has been developed for the demands of RF low-cost transmission systems at data rates up to 20 kBaud Manchester coding and 40 kBaud NRZ coding. The transmitting frequency range is 313 MHz to 317 MHz (ATA5756) and 432 MHz to 448 MHz (ATA5757), respectively. It can be used in both FSK and ASK systems. Due to its shorten crystal oscillator settling time it is well suited for Tire Pressure Monitoring (TPM) and for Passive Entry Go applications.
Figure 1-1.
System Block Diagram
UHF ASK/FSK TPM and Remote control transmitter UHF ASK/FSK Remote control receiver
1 Li cell
ATA5756/ ATA5757
PLL Antenna Antenna XTO VCO
Keys
Encoder ATARx9x
U3741B/ U3745B/ T5743/ T5744/
Demod.
Control
1...3
µC
IF Amp
PLL
XTO
Power amp.
LNA
VCO
4702J–RKE–09/08
2. Pin Configuration
Figure 2-1. Pinning TSSOP10
10
CLK ASK
1
ENABLE
2 ATA5756 ATA5757
9
GND
FSK
3
8
VS
ANT2
4
7
XTO1
ANT1
5
6
XTO2
Table 2-1.
Pin
Pin Description
Symbol Function Configuration
1
CLK
Clock output signal for the microcontroller. The clock output frequency is set by the crystal to fXTAL/8. The CLK output stays Low in power-down mode and after enabling of the PLL. The CLK output switches on if the oscillation amplitude of the crystal has reached a certain level.
VS
100 100 200k
CLK
ASK
50k
VRef = 1.1V
2
ASK
Switches on the power amplifier for ASK modulation and enables the PLL and XTO if the ENABLE pin is open
200k
20 µA
FSK
200k
VRef = 1.1V
3
FSK
Switches off the FSK switch (switch has high Z if signal at pin FSK is High) and enables the PLL and the XTO if the ENABLE pin is open
5 µA 200k
2
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
Table 2-1.
Pin 4
Pin Description (Continued)
Symbol ANT2 Function Emitter of antenna output stage
ANT1
Configuration
5
ANT1
Open collector antenna output
ANT2
6
XTO2
Diode switch, used for FSK modulation
(FSK < 0.25V) AND (ENABLE > 1.7V) XTO2
210 µA
VS 1.5k 1.2k
VS
7
XTO1
Connection for crystal
XTO1
182 µA
8 9
VS GND
Supply voltage Ground
See ESD protection circuitry (see Figure 4-9 on page 14) See ESD protection circuitry (see Figure 4-9 on page 14)
VS
ENABLE input If ENABLE is connected to GND and the ASK or FSK pin is High, the device stays in idle mode. In normal operation ENABLE is left open and ASK or FSK is used to enable the device.
30 µA (FSK >1.7 V ) OR (ASK > 1.7 V)
ENABLE 150k
10
ENABLE
250k
3
4702J–RKE–09/08
Figure 2-2.
Block Diagram
ATA5756 / ATA5757
Power up/down CLK EN
f 8
ENABLE
1
10 f
ASK
24/ 32
GND
2
OR FSK
9
PFD VS
3
CP Ampl. OK ANT2
8
XTO1
XTO LF
4
7
EN ANT1 XTO2
PA
5
VCO
6
PLL
3. General Description
This fully integrated PLL transmitter allows the design of simple, low-cost RF miniature transmitters for TPM and RKE applications. The VCO is locked to 24 × f X T A L /32 × f X T A L f or ATA 5 7 5 6 / ATA 5 7 5 7 . T h u s , a 1 3 . 1 2 5 M H z / 1 3 . 5 6 M H z c r y s t a l i s n e e d e d f o r a 315 MHz/433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance (current mode) oscillator. Only one capacitor and a crystal connected in series to GND are needed as external elements in an ASK system. The internal FSK switch, together with a second capacitor, can be used for FSK modulation. The crystal oscillator needs typically 0.6 ms until the CLK output is activated if a crystal as defined in the electrical characteristics is used (e.g., TPM crystal). For most crystals used in RKE systems, a shorter time will result. The CLK output is switched on if the amplitude of the current flowing through the crystal has reached 35% to 80% of its final value. This is synchronized with the 1.64/1.69 MHz CLK output. As a result, the first period of the CLK output is always a full period. The PLL is then locked 250 µs
ASK
CLK Power-down Power-up, PA off Power-up, Power-up, PA off PA on (fRF = High) (fRF = Low) Power-down
6
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
4.2
4.2.1
Transmission with ENABLE = High
FSK Mode The ATA5756/ATA5757 is activated by ENABLE = High, FSK = High and ASK = Low. The microcontroller is then switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (i.e., the microcontroller waits until the XTO and CLK are ready). After another time period of ≤250 µs, the PLL is locked and ready to transmit. The power amplifier is switched on with ASK = H. The ATA5756/ATA5757 is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the crystal load capacitor and GND by means of pin FSK, thus, changing the reference frequency of the PLL. IF FSK = L the output frequency is lower, if FSK = H output frequency is higher. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA5756/ATA5757 is switched to power-down mode with ENABLE = Low and FSK = Low. Figure 4-3. Timing FSK Mode with ENABLE Connected to the Microcontroller
ΔTXTO ENABLE > 250 µs
FSK
ASK
CLK Power-down Power-up, PA off Power-up, Power-up, PA on PA off (fRF = High) (fRF = Low) Power-down
4.2.2
ASK Mode The ATA5756/ATA5757 is activated by ENABLE = High, FSK = High and ASK = Low. After activation the microcontroller is switched to external clocking. After typically 0.6 ms, the CLK driver is activated automatically (the microcontroller waits until the XTO and CLK are ready). After another time period of ≤250 µs, the PLL is locked and ready to transmit. The output power can then be modulated by means of pin ASK. After transmission, ASK is switched to Low and the microcontroller returns back to internal clocking. Then, the ATA5756/ATA5757 is switched to power-down mode with ENABLE = Low and FSK = Low.
7
4702J–RKE–09/08
Figure 4-4.
Timing ASK Mode with ENABLE Connected to the Microcontroller
ΔTXTO > 250 µs
ENABLE
FSK
ASK
CLK Power-down Power-up, PA off Power-up, Power-up, PA on PA off (High) (Low) Power-down
4.3
Accuracy of Frequency Deviation
The accuracy of the frequency deviation using the XTAL pulling method is about ±20% if the following tolerances are considered. One important aspect is that the values of C0 and CM of typical crystals are strongly correlated which reduces the tolerance of the frequency deviation. Figure 4-5. Tolerances of Frequency Modulation
~
VS C Stray
XTAL
CM
LM C0
RS
C4 C5 CSwitch
Using a crystal with a motional capacitance of CM = 4.37 fF ±15%, a nominal load capacitance of C LNOM = 18 pF and a parallel capacitance of C 0 = 1.30 pF correlated with C M r esults in C0 = 297 × CM (the correlation has a tolerance of 10%, so C0 = 267 to 326 × CM). If using the internal FSK switch with CSwitch = 0.9 pF ±20% and estimated parasites of CStray = 0.7 pF ±10%, the resulting C4 and C5 values are C4 = 10 pF ±1% and C5 = 15 pF ±1% for a nominal frequency deviation of ±19.3 kHz with worst case tolerances of ±15.8 kHz to ±23.2 kHz.
8
ATA5756/ATA5757
4702J–RKE–09/08
~
Crystal equivalent circuit
ATA5756/ATA5757
4.4 Accuracy of the Center Frequency
The imaginary part of the impedance in large signal steady state oscillation IMXTO, seen into the pin 7 (XTO1), causes some additional frequency tolerances, due to pulling of the XTO oscillation frequency. These tolerances have to be added to the tolerances of the crystal itself (adjustment tolerance, temperature stability and ageing) and the influence to the center frequency due to tolerances of C 4, C5, CSwitch and CStray. The nominal value of IMXTO = 110 Ω, CSwitch and CStray should be absorbed into the C4 and C5 values by using a crystal with known frequency and choosing C4 and C5, so that the XTO center frequency equals the crystal frequency, and the frequency deviation is as expected. Then, from the nominal value, the IMXTO has ±90 Ω tolerances, using the pulling formula P = -IMXTO × CM × π × fXTO with fXTO = 13.56 MHz and CM = 4.4 fF an additional frequency tolerance of P = ±16.86 ppm results. If using crystals with other CM the additional frequency tolerance can be calculated in the same way. For example, a lower C M = 3.1 fF will reduce the frequency tolerance to 11.87 ppm, where a higher C M = 5.5 fF increases the tolerance to 21.07 ppm.
4.5
CLK Output
An output CLK signal of 1.64 MHz (ATA5756 operating at 315 MHz) and 1.69 MHz (ATA5757 operating at 433.92 MHz) is provided for a connected microcontroller. The delivered signal is CMOS-compatible with a High and Low time of >125 ns if the load capacitance is lower than 20 pF. The CLK output is Low in power-down mode due to an internal pull-down resistor. After enabling the PLL and XTO the signal stays Low until the amplitude of the crystal oscillator has reached 35% to 80% of its amplitude. Then, the CLK output is activated synchronously with its output signal so that the first period of the CLK output signal is a full period.
4.5.1
Clock Pulse Take-over by Microcontroller The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s ATARx9x microcontroller family provides the special feature of starting with an integrated RC oscillator to switch on the ATA5756/ATA5757’s external clocking and to wait automatically until the CLK output of the ATA5756/ATA5757 is activated. After a time period of 250 µs the message can be sent with crystal accuracy. Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad, opt = 380 Ω + j340 Ω ( ATA5756) at 315 MHz and ZLoad, opt = 280 Ω + j310 Ω (ATA5757) at 433.92 MHz. A low resistive path to VS is required to deliver the DC current (see Figure 4-6 on page 10). The power amplifier delivers a current pulse and the maximum output power is delivered to a resistive load if the 0.66 pF output capacitance of the power amplifier is compensated by the load impedance. At the ANT1 pin, the RF output amplitude is about VS - 0.5 V. The load impedance is defined as the impedance seen from the ATA5756’s ANT1, ANT2 into the matching network. Do not mix up this large-signal load impedance with a small-signal input impedance delivered as an input characteristic of RF amplifiers. The latter is measured from the application into the IC instead of from the IC into the application for a power amplifier.
4.5.2
9
4702J–RKE–09/08
The 0.66 pF output capacitance absorbed into the load impedance a real impedance of 684 Ω (ATA5756) at 315 MHz and 623 Ω (ATA5757) at 433.92 MHz should be measured with a network analyses at pin 5 (ANT1) with the ATA5756/ATA5757 soldered, an optimized antenna connected and the power amplifier switched off. Less output power is achieved by lowering the real parallel part where the parallel imaginary part should be kept constant. Lowering the real part of the load impedance also reduces the supply voltage dependency of the output power. Output power measurement can be done with the circuit as shown in Figure 4-6. Please note that the component values must be changed to compensate the individual board parasitics until the ATA5756/ATA5757 has the right load impedance. Also, the damping of the cable used to measure the output power must be calibrated. Figure 4-6. Output Power Measurement ATA5756/ATA5757
VS C1 = 1n
ANT1 Z Lopt ANT2
~
L1 = 68 nH/ 39 nH Z = 50 C2 = 2.2 pF/1.8 pF
Power meter Rin 50
~
Table 4-2 and Table 4-3 show the output power and the supply current versus temperature and supply voltage. Table 4-2. Output Power and Supply Current versus Temperature and Supply Voltage for the ATA5756 with ZLoad = 380 Ω + j340 Ω (Correlation Tested)
VS = 2.0 V (dBm/mA) 3.1 ±1.5 / 7.2 3.0 ±1.5 / 7.5 3.0 ±1.5 / 7.5 2.5 ±1.5 / 7.6 VS = 3.0 V (dBm/mA) 6.1 +2/-3 / 7.7 6.0 ±2 / 8.1 5.8 +2/-3 / 8.2 5.5 +2/-3 / 8.2 VS = 3.6 V (dBm/mA) 7.1 +2/-3 / 7.9 7.4 ±2 / 8.3 7.2 +2/-3 / 8.5 6.5 +2/-3 / 8.5
Ambient Temperature Tamb = -40°C Tamb = +25°C Tamb = +85°C Tamb = +125°C
Table 4-3.
Output Power and Supply Current versus Temperature and Supply Voltage for the ATA5757 with ZLoad = 280 Ω + j310 Ω (Correlation Tested)
VS = 2.0 V (dBm/mA) 3.3 ±1.5 / 7.6 3.0 ±1.5 / 8.0 2.8 ±1.5 / 8.0 2.7 ±1.5 / 8.1 VS = 3.0 V (dBm/mA) 6.2 +2/-3 / 8.1 6.0 ±2 / 8.5 5.7 +2/-3 / 8.6 5.5 +2/-3 / 8.7 VS = 3.6 V (dBm/mA) 7.1 +2/-3 / 8.4 7.5 ±2 / 8.8 6.8 +2/-3 / 8.8 6.6 +2/-3 / 8.9
Ambient Temperature Tamb = -40°C Tamb = +25°C Tamb = +85°C Tamb = +125°C
10
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
4.6 Application Circuits
For the supply voltage blocking capacitor C3, a value of 68 nF/X7R is recommended (see Figure 4-7 on page 12 and Figure 4-8 on page 13). C1 and C2 are used to match the loop antenna to the power amplifier. For C2, two capacitors in series should be used to achieve a better tolerance value and to enable it to realize ZLoad,opt by using capacitors with standard values. Together with the pins of ATA5756 and the PCB board wires, C1 forms a series resonance loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally, the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 (50 nH to 100 nH) can be printed on the PCB. C4 should be selected so that the XTO runs on the load resonance frequency of the crystal. Normally, a value of 10 pF results in a 12 pF load-capacitance crystal due to the board parasitic capacitances and the inductive impedance of the XTO1 pin.
11
4702J–RKE–09/08
Figure 4-7.
ASK Application Circuit
S1
BPXY
ATARx9x
VDD
1
VSS
20
VS
S2
BPXY
BPXY
OSC1
BPXY
7
ATA5756/ATA5757
Power up/down CLK
f 8
EN
ENABLE
1
10 f
ASK
24/ 32
GND
2
OR FSK
9 C3
VS
PFD
3
C2 ANT2 CP Ampl. OK
8
VS XTO1
XTAL
4
Loop Antenna
XTO LF
7 C4
C1
EN ANT1
XTO2
PA
5
L1
VCO PLL
6
VS
12
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
Figure 4-8. FSK Application Circuit
S1
BPXY
ATARx9x
VDD
1
VSS
20
VS
S2
BPXY
BPXY
OSC1
BPXY
7
ATA5756/ATA5757
Power up/down CLK
1
f 8
EN
ENABLE
10 f
ASK
24/ 32
GND
2
OR FSK
9 C3
VS
PFD
3
C2 ANT2 CP Ampl. OK
8
VS XTO1
XTAL
4
Loop Antenna
XTO LF
7
C1
EN ANT1
XTO2
PA
C5 C4
5
L1
VCO
6
PLL
VS
13
4702J–RKE–09/08
Figure 4-9.
VS
ESD Protection Circuit
ANT1
CLK
ASK
FSK
ANT2
XTO2
XTO1
ENABLE
GND
5. Absolute Maximum Ratings
Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Ambient temperature in power-down mode for 15 minutes without damage with VS ≤ 3.2 V VENABLE < 0.25 V or ENABLE is open, VASK < 0.25 V, VFSK < 0.25 V Input voltage Note: Symbol VS Ptot Tj Tstg Tamb1 Tamb2 VmaxASK -0.3 -55 -55 Minimum Maximum 5 100 150 125 125 Unit V mW °C °C °C
175 (VS + 0.3)(1)
°C
V
1. If VS + 0.3 is higher than 3.7 V, the maximum voltage will be reduced to 3.7 V.
6. Thermal Resistance
Parameters Junction ambient Symbol RthJA Value 170 Unit K/W
14
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
7. Electrical Characteristics
VS = 2.0 V to 3.6 V, Tamb = -40°C to 125°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 9).
CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60 Ω Parameters Supply current, power-down mode Test Conditions VENABLE < 0.25 V or ENABLE is open, VASK < 0.25 V, VFSK < 0.25 V Tamb = 25°C Tamb = -40°C to +85°C Tamb = -40°C to +125°C VENABLE < 0.25 V, VS ≤ 3.2 V ASK,FSK can be Low or High VS ≤ 3.2 V, VFSK > 1.7 V, VASK < 0.25 V ENABLE is open VS ≤ 3.2 V, CCLK ≤ 10 pF VFSK > 1.7 V, VASK > 1.7 V ENABLE is open Symbol Min. Typ. Max. Unit
IS_Off
1
100 350 7,000 100
nA nA nA µA mA
Supply current, idle mode Supply current, power-up, PA off, FSK switch High Z Supply current, power-up, PA on, FSK switch High Z
IS_IDLE IS 3.6
4.6
IS_Transmit1 8.1 8.5 9.8 10.5 mA mA
ATA5756 ATA5757
VS ≤ 3.2 V, CCLK ≤ 10 pF VFSK< 0.25 V, VASK > 1.7 V ENABLE is open
Supply current, power-up, PA on, FSK Low Z
IS_Transmit2 8.4 8.8 10.2 11.0 mA mA
ATA5756 ATA5757
VS = 3.0 V, Tamb = 25°C, f = 315 MHz for ATA5756, ZLoad, opt = (380 + j340) Ω f = 433.92 MHz for ATA5757, ZLoad, opt = (280 + j310) Ω Tamb = -40°C to +125°C, VS = 2.0 V to 3.2 V fCLK = fXT0/8 Load capacitance at pin CLK ≤ 20 pF f0 ± fCLK f0 ± fXT0 other spurious are lower With 50 Ω matching network according to Figure 4-6 on page 10 2nd 3rd fXTO = f0/24 ATA5756 fXTO = f0/32 ATA5757 fXTAL = resonant frequency of the XTAL, CM = 4.37 fF, load capacitance selected accordingly Tamb = -40°C to +85°C Tamb = -40°C to +125°C
Output power
POut
4
6
8
dBm
Output power for the full temperature and supply voltage range
POut
1
8.2
dBm
Spurious emission
Spour
-42 -60
dBc
Harmonics
-16 -15
dBc dBc
Oscillator frequency XTO (= phase comparator frequency)
ΔfXTO -14.0 -17.5 fXTAL fXTAL +14.0 +17.5 ppm ppm
15
4702J–RKE–09/08
7. Electrical Characteristics (Continued)
VS = 2.0 V to 3.6 V, Tamb = -40°C to 125°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 9).
CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60 Ω Parameters Imaginary part of XTO1 Impedance in steady state oscillation Real part of XTO1 impedance in small signal oscillation Test Conditions Since pulling P is P = -IMXTO × CM × π × fXTO ΔfXTO can be calculated out of IMXTO with CM = 4.37 fF This value is important for crystal oscillator start-up Time between ENABLE of the IC with FSK = H and activation of the CLK output. The CLK is activated synchronously to the output frequency if the current through the XTAL has reached 35% to 80% of its maximum amplitude. Crystal parameters: CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF, RS ≤ 60 Ω Current flowing through the crystal in steady state oscillation (peak-to-peak value) Time between the activation of CLK and when the PLL is locked (transmitter ready for data transmission) 25 kHz distance to carrier at 1 MHz at 36 MHz ATA5756 ATA5757 ATA5756 ATA5757 CLoad ≤ 20 pF, High = 0.8 × Vs, Low = 0.2 × VS, fCLK < 1.7 MHz For proper detection of the XTO amplitude Symbol IMXTO Min. j20 Typ. j110 Max. j200 Unit Ω
REXTO
-650
-1100
Ω
Crystal oscillator start-up time
ΔTXTO
0.6
1.4
ms
XTO drive current
IDXTO
300
µApp
Locking time of the PLL PLL loop bandwidth In loop phase noise PLL Phase noise VCO Frequency range of VCO Clock output frequency (CMOS microcontroller compatible) Clock output minimum High and Low time Series resonance resistance of the resonator seen from pin XTO1 Capacitive load at Pin XTO1 FSK modulation frequency rate FSK switch OFF resistance FSK switch OFF capacitance FSK switch ON resistance ASK modulation frequency rate
ΔTPLL fLoop_PLL LPLL Lat1M Lat36M fVCO fCLK TCLKLH Rs_max CL_max 125 310 432 f0/192 f0/256 250 -85 -90 -121
250
µs kHz
-76 -84 -115 317 448
dBc/Hz dBc/Hz dBc/Hz MHz MHz MHz ns
150 5 0 50 0.75 0.9 130 0 1.1 175 20 20
Ω pF kHz kΩ pF Ω kHz
This corresponds to 20 kBaud in Manchester coding and 40 kBaud in NRZ coding High Z High Z capacitance Low Z Duty cycle of the modulation signal = 50%, this corresponds to 20 kBaud in Manchester coding and 40 kBaud in NRZ coding
fMOD_FSK RSWIT_OFF CSWIT_OFF RSWIT_ON fMOD_ASK
16
ATA5756/ATA5757
4702J–RKE–09/08
ATA5756/ATA5757
7. Electrical Characteristics (Continued)
VS = 2.0 V to 3.6 V, Tamb = -40°C to 125°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (Pin 9).
CM = 4.37 fF, C0 = 1.3 pF, CLNOM = 18 pF, C4 = 10 pF, C5 = 15 pF and RS ≤ 60 Ω Parameters ASK input Test Conditions Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high Input current Low Symbol VIl VIh IIn VIl VIh IIn VIl VIh IInh IInl Min. 1.7 Typ. Max. 0.25 VS 30 0.25 VS 30 0.25 VS 40 40 Unit V V µA V V µA V V µA µA
FSK input
1.7
ENABLE input
1.7 -40 -40
17
4702J–RKE–09/08
8. Ordering Information
Extended Type Number ATA5756-6DQY ATA5756-6DPY ATA5757-6DQY ATA5757-6DPY Package TSSOP10 TSSOP10 Remarks Pb-free Pb-free
9. Package Information TSSOP10
Package: TSSOP 10 (acc. to JEDEC Standard MO-187) Dimensions in mm Not indicated tolerances ± 0.05
1.1 max
0.85±0.1
3±0.1
3±0.1
0.5 nom. 4 x 0.5 = 2 nom. 10 9 8 7 6
3.8±0.3 4.9±0.1
technical drawings according to DIN specifications
Drawing-No.: 6.543-5095.01-4 12345 Issue: 3; 16.09.05
18
ATA5756/ATA5757
4702J–RKE–09/08
0.15
0.25
ATA5756/ATA5757
10. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4702J-RKE-07/08 History • Put datasheet in a new template • Page1: PB-free logo deleted • Page 18: Ordering Information changed • Put datasheet in a new template • First page: Pb-free logo added • Page 18: Ordering Information and package drawing changed • Electrical Characteristics table, page 15, row “Output power for the full...”. -> maximum value changed • Electrical Characteristics table, page 15, row “Output power variation...”. -> the word “variation” deleted • Preliminary deleted • Abs. Max. Ratings table (page 14): row “Input voltage” added • Abs. Max. Ratings table (page 14): table note 1 added • El. Char. table (page 17): rows “ASK input”, “FSK input“, “ENABLE input” maximum values changed
4702I-RKE-11/05
4702H-RKE-09/04 4702G-RKE-08/04 4702F-RKE-08/04
4702E-RKE-07/04
19
4702J–RKE–09/08
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