ATA5773

General Features • Complete Key Fob IC Consisting of an AVR® Microcontroller and RF Transmitter PLL in a Single QFN24 5 mm × 5 mm Package (Pitch 0.65 mm) – f0 = 310 MHz to 350 MHz (ATA5773) – f0 = 429 MHz to 439 MHz (ATA5774) – f0 = 868 MHz to 928 MHz (ATA5771) Automotive Qualified Temperature Range –40° C to +85° C ESD Protection: HBM 2500V, MM 100V, CDM 1000V Supply voltage 2.0V to 4.0V for Single Li-cell Power Supply Low Power Consumption – Active Mode: Typical 9.8 mA at 3.0V and 4 MHz Microcontroller-clock – Power-down Mode: Typical 200 nA at 3.0V Modulation Scheme ASK/FSK Integrated PLL Loop Filter High Output Power (8 dBm at 315 MHz/7.5 dBm at 433 MHz/ 5.5 dBm at 868 MHz) High Performance, Low Power AVR 8-bit Microcontroller Advanced RISC Architecture Non-volatile Program and Data Memories – 4 KByte of In-system Programmable Program Memory Flash – 256 Bytes In-system Programmable EEPROM – 256 Bytes Internal SRAM Peripheral Features – Two Timer/Counter, 8- and 16-bit Counters with Two PWM Channels on Both – 10-bit ADC – Programmable Watchdog Timer with Separate On-chip Oscillator – Universal Serial Interface (USI) Special Microcontroller Features – debugWIRE On-chip Debug System – In-system Programmable via SPI Port – External and Internal Interrupt Sources – Pin Change Interrupt on 12 Pins – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator – On-chip Temperature Sensor 12 Programmable I/O Lines • • • • • • • • • • • Microcontroller with UHF ASK/FSK Transmitter ATA5771 ATA5773 ATA5774 • • • 1. General Description The ATA5771/ATA5773/ATA5774 is a single key fob IC containing the AVR microcontroller ATtiny44V and the UHF PLL transmitters T5750/53/54 build-up using a stacked die technique supplied in a QFN24 5 mm × 5 mm package. These devices have been specially developed for the demands of RF low-cost data transmission systems with data rates of up to 32 kBit/s. Its main applications are in the areas of Remote Keyless-Entry (RKE), Passive Entry Go (PEG), and Remote Start. It can be used in the frequency range of f 0 = 310 MHz to 350 MHz, f 0 = 429 MHz to 439 MHz or f0 = 868 MHz to 928 MHz for ASK or FSK data transmission. 9137B–RKE–02/09 Figure 1-1. ASK System Block Diagram UHF ASK/FSK Remote Control Transmitter ATA5771/73/74 S1 S1 S1 PXY PXY PXY PXY PXY PXY PXY ATtiny44V VDD GND PXY PXY PXY PXY PXY VS T5750 T5753 T5754 Power up/down ENABLE UHF ASK/FSK Remote Control Receiver ATA5760 ATA5761 ATA5723 ATA5724 ATA5728 ATA5745 ATA5746 Antenna PLL XTO CLK f/4 PLL GND_RF 1 to 6 Demod Control Microcontroller XTO VCO VCC_RF VS PA_ENABLE ANT2 Loop Antenna ANT1 PA LNA VCO VS 2 ATA5771/ATA5773/ATA5774 9137B–RKE–02/09 ATA5771/ATA5773/ATA5774 Figure 1-2. FSK System Block Diagram UHF ASK/FSK Remote Control Transmitter ATA5771/73/74 S1 S1 S1 PXY PXY PXY PXY PXY PXY PXY ATtiny44V VDD GND PXY PXY PXY PXY PXY VS T5750 T5753 T5754 Power up/down ENABLE UHF ASK/FSK Remote Control Receiver ATA5760 ATA5761 ATA5723 ATA5724 ATA5728 ATA5745 ATA5746 Antenna PLL XTO CLK f/4 PLL GND_RF 1 to 6 Demod Control Microcontroller XTO VCO VCC_RF VS PA_ENABLE ANT2 Loop Antenna ANT1 PA LNA VCO VS 3 9137B–RKE–02/09 2. Pin Configuration Figure 2-1. Pinning QFN24 5 mm x 5 mm GND_RF ENABLE VS_RF XTAL 20 GND 24 23 22 21 VCC PB0 PB1 PB3/RESET PB2 PA7 1 2 3 4 5 6 7 8 9 10 11 19 18 17 16 15 14 13 12 GND PA0 PA1 PA2 PA3/T0 PA4/USCK PA5/MISO GND PA_ENABLE CLK ANT2 Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Pin Description Symbol VCC PB0 PB1 PB3/RESET PB2 PA7 PA6 / MOSI CLK PA_ENABLE ANT2 ANT1 GND PA5/MISO PA4/SCK PA3/T0 PA2 PA1 PA0 GND XTAL VS_RF GND_RF ENABLE GND GND Function Microcontroller supply voltage Port B is a 4-bit bi-directional I/O port with internal pull-up resistor Port B is a 4-bit bi-directional I/O port with internal pull-up resistor Port B is a 4-bit bi-directional I/O port with internal pull-up resistor/reset input Port B is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Clock output signal for microcontroller. The clock output frequency is set by the crystal to fXTAL/4 Switches on power amplifier, used for ASK modulation Emitter of antenna output stage Open collector antenna output Ground Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Port A is a 4-bit bi-directional I/O port with internal pull-up resistor Microcontroller ground Connection for crystal Transmitter supply voltage Transmitter ground Enable input Ground Ground/backplane (exposed die pad) 4 ATA5771/ATA5773/ATA5774 9137B–RKE–02/09 PA6/MOSI ANT1 ATA5771/ATA5773/ATA5774 3. Functional Description For a typical key fob application 3-4 interconnections between the microcontroller and the transmitter are required (see Figure 1-1 on page 2 and Figure 1-2 on page 3). The CLK line is used to allow the microcontroller to generate an XTAL-based transmitter signal. The ENABLE line is used to start the XTO, PLL, and clock output of the transmitter. The PA_ENABLE line is used to enable the power amplifier in ASK and FSK mode. In FSK mode a 4th line is necessary to modulate the load capacity of the XTAL. To wake-up the system from standby mode at least one key input is required. After pressing the key, the microcontroller starts up with the internal RC oscillator. For TX operation user software must control ENABLE, PA_ENABLE and XTAL load capacity as described in the following section. If ENABLE = L and PA_ENABLE = L the transmitter and the microcontroller (MCU) are in standby mode, reducing the power consumption so that a lithium cell can be used as power supply for several years. If ENABLE = H and PA_ENABLE = L, the XTO, PLL and the CLK driver from the transmitter are activated. The crystal oscillator together with the PLL from the RF transmitter typically requires < 1 ms (ATA5773 < 3 ms) until the PLL is locked and the clock output (Pin 8) is stable. If ENABLE = H and PA_ENABLE = H, the XTO, PLL, CLK driver and the Power Amplifier (PA) are switched on. The ASK modulation is done by switching on/off the power amplifier via PA_ENABLE. The FSK modulation is done by switching on/off an additional capacitor between the XTAL load capacitor and GND, thus changing the reference frequency of the PLL. This is done using a MOS switch controlled by a microcontroller output. The power amplifier is switched on via PA_ENABLE = H. The MCU has to wait at least > 1 ms ATA5774 (> 3 ms ATA5773, > 4 ms ATA5771) after setting ENABLE = H, before the external clock can be used. The external clock is connected via the timer0 input pin that clocks the USI from the MCU to achieve an accurate data transfer. The frequency of the internal RC oscillator is affected by ambient temperature and operating voltage. The USI provides 2 two serial synchronous data transfer modes, with different physical I/O ports for the data output. The two wire mode is used for ASK and the three wire mode is used for FSK. Table 3-1. Type Typical Current Consumption in Active Mode at 3.0V and 25°C Transmitter 8.5 mA 9.0 mA 9.0 mA Microcontroller (4 MHz Internal RC Oscillator) 0.8 mA 0.8 mA 0.8 mA Total 9.3 mA 9.8 mA 9.8 mA ATA5771 ATA5773 ATA5774 Table 3-2. Current Consumption in Power-down Mode at 3.0V and –40°C to +85°C Microcontroller (Watchdog Timer Disabled) Typ. 200 nA Max. 24 µA(1) Type ATA5771 ATA5773 ATA5774 Note: Transmitter Typ. < 10 nA Max. 350 nA Total Typ. < 210 nA Max. 24.35 µA(1) 1. Maximum value measured in final test at 125°C. Value at 85°C: See Appendix 4, page 196, Figure 23-12 “Power Down Supply Current versus VCC” 5 9137B–RKE–02/09 4. UHF ASK/FSK Transmitter Block • Integrated PLL Loop Filter • Maximum Output Power (ATA5771: 5.5 dBm, ATA5773: 8.0 dBm, ATA5774: 7.5 dBm) with Low Supply Current • Modulation Scheme ASK/FSK – FSK Modulation is Achieved by Switching on/off an Additional Capacitor Between the XTAL Load Capacitor and GND. This is Done Using a MOS Switch Controlled by a Microcontroller Output. Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply Supply Voltage 2.0V to 4.0V in the Temperature Range of –40° C to +85° C Single-ended Antenna Output with High Efficient Power Amplifier External CLK Output for Clocking the Microcontroller • • • • More detailed information about the UHF ASK/FSK Transmitter Block can be found in Appendix 1, 2 and 3. ATA5771 ATA5773 ATA5774 see Appendix 1: see Appendix 2: see Appendix 3: Data sheet T5750 (868 MHz band) Data sheet T5753 (315 MHz band) Data sheet T5754 (433 MHz band) Table 4-1. Transmitter Pin Cross Reference List Pin Name CLK Pin Number T5750/53/54 1 2 3 4 5 6 7 8 Pin Number ATA5771/73/74 8 9 10 11 20 21 22 23 PA_ENABLE ANT2 ANT1 XTAL VS GND ENABLE Note: For the ATA5771/ATA5773/ATA5774 following points differs in the data sheets: - The temperature range is limited to –40° C to +85° C - ESD protection: HBM 2500V, MM 100V, CDM 1000V - Figure 4-1 on page 7: Two output power measurement - For FSK modulation an additional MOS switch is required 6 ATA5771/ATA5773/ATA5774 9137B–RKE–02/09 ATA5771/ATA5773/ATA5774 Figure 4-1. Output Power Measurement ATA5771/ATA5773/ATA5774 VS C1 = 1 nF L1 ANT1 ZLopt ANT2 C2 Z = 50Ω Rin 50Ω Power meter Table 4-2. Output Power Measurement ATA5771/ATA5773/ATA5774 Device ATA5771 ATA5773 ATA5774 L1 10 nH 47 nH 33 nH C2 0.5 pF 3.3 pF 2.4 pF 7 9137B–RKE–02/09 5. Microcontroller Block • High-performance Low-power AVR 8-bit Microcontroller • Advanced Risc Architecture • Non-volatile Program and Data Memory – 4KByte of In-system Programmable Program Flash – Endurance: 10.000 Write/Erase Cycles – 256 Bytes In-system Programmable EEPROM – Endurance: 100.000 Write/Erase Cycles – 256 Bytes Internal SRAM Programming Lock for Self-programming Flash Program and EEPROM Data Security Peripheral Features – Two Timer/Counter, 8- and 16-bit Counters with Two PWM Channels on Both Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator – Universal Serial Interface Special Microcontroller Features – Debug Wire On-chip Debug System – In-system Programmable via SPI Port – External and Internal Interrupt Sources – Pin Change Interrupt on 12 Pins – Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator – On-chip Temperature Sensor 12 Programmable I/O Lines Operating Voltage – 1.8V to 5.5V Speed Grade – 0 to 4 MHz at 2.0V to 4.0V Temperature Range – –40° C to +85° C Low Power Consumption – Active Mode: 4 MHz, 3V, 0.8 mA – Power-down Mode: 3V, 0.2 µA • • • • • • • • • • More detailed information about the Microcontroller Block can be found in Appendix 4 and 5. ATA5771, ATA5773, ATA5774 see Appendix 4: Datasheet ATtiny44 and Appendix 5: Appendix B - ATtiny44V 8 ATA5771/ATA5773/ATA5774 9137B–RKE–02/09 ATA5771/ATA5773/ATA5774 Table 5-1. Microcontroller Cross Reference List Pin Name VCC PB0 PB1 PB3/NRESET PB2 PA7 PA6/MOSI PA5/MISO PA4/USCK PA3/T0 PA2 PA1 PA0 GND Note: Pin Number ATtiny44V 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Pin Number ATA5771/ATA5773/ATA5774 1 2 3 4 5 6 7 13 14 15 16 17 18 19 For the ATA5771/ATA5773/ATA5774 following points differs in the data sheet ATtiny44V: - The temperature range is limited to –40° C to +85° C - The supply voltage range is limited from 2.0V to 4.0V 9 9137B–RKE–02/09 6. Application Figure 6-1. Typical ASK Application ATA5771/ATA5773/ATA5774 VCC 68 nF VCC 24 23 22 21 20 19 GND GND_RF 1 VCC 2 PB0 3 PB1 4 ENABLE VS_RF XTAL GND SW1 18 PA0 17 PA1 16 PA2 SW2 SW3 ATA577x PB3/RESET PA3/T0 15 14 5 PB2 PA4/SCK 6 PA7 PA_ENABLE PA6/MOSI 13 PA5/MISO ANT2 ANT1 11 7 8 9 10 GND 12 CLK VCC RF Choke 10 ATA5771/ATA5773/ATA5774 9137B–RKE–02/09 ATA5771/ATA5773/ATA5774 Figure 6-2. Typical FSK Application ATA5771/ATA5773/ATA5774 VCC 68 nF VCC 24 GND 23 ENABLE 22 GND_RF 21 VS_RF 20 XTAL 19 GND SW1 18 PA0 17 1 VCC 2 PB0 3 PB1 4 SW2 PA1 16 PA2 SW3 ATA577x PB3/RESET PA3/T0 15 14 5 PB2 PA6/MOSI 6 PA7 PA_ENABLE PA4/SCK 13 PA5/MISO ANT2 ANT1 11 GND 12 7 CLK 8 9 10 VCC RF Choke 11 9137B–RKE–02/09 7. Ordering Information Extended Type Number ATA5771-PXQW ATA5773-PXQW ATA5774-PXQW Package QFN24 5 mm x 5 mm QFN24 5 mm x 5 mm QFN24 5 mm x 5 mm Remarks Microcontroller with UHF Tx for 868 MHz to 928 MHz Microcontroller with UHF Tx for 310 MHz to 350 MHz Microcontroller with UHF Tx for 429 MHZ to 439 MHz 8. Package Information Package: QFN 24 - 5 x 5 Exposed pad 3.6 x 3.6 (acc. JEDEC OUTLINE No. MO-220) Dimensions in mm Not indicated tolerances ±0.05 0.9±0.1 0.05-0.05 24 1 0.4 18 19 +0 5 3.6 24 1 technical drawings according to DIN specifications 6 0.3 13 12 7 6 0.65 nom. Drawing-No.: 6.543-5122.01-4 Issue: 1; 15.11.05 3.25 12 ATA5771/ATA5773/ATA5774 9137B–RKE–02/09 ATA5771/ATA5773/ATA5774 9. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History • • • • • • Features on page 1 changed Figure 1-1 “ASK System Block Diagram” on page 2 changed Figure 1-2 “FSK System Block Diagram” on page 3 changed Section 3 “Functional Description” on page 5 changed Table 4-1 “Transmitter Pin Cross Reference List” on page 6 changed Section 5 “Microcontroller Block” on page 8 changed 9137B-RKE-02/09 13 9137B–RKE–02/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support car_access@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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Other terms and product names may be trademarks of others. 9137B–RKE–02/09 Features • Integrated PLL Loop Filter • ESD Protection also at ANT1/ANT2 (4 kV HBM/200V MM; Except Pin 2: 4 kV HBM/100V MM) • High Output Power (5.5 dBm) with Low Supply Current (8.5 mA) • Modulation Scheme ASK/FSK – FSK Modulation is Achieved by Connecting an Additional Capacitor Between the XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply Single Li-cell for Power Supply Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to +85°C/+125°C Package TSSOP8L Single-ended Antenna Output with High Efficient Power Amplifier CLK Output for Clocking the Microcontroller One-chip Solution with Minimum External Circuitry 125°C Operation for Tire Pressure Systems • • • • • • • • UHF ASK/FSK Transmitter T5750 1. Description The T5750 is a PLL transmitter IC which has been developed for the demands of RF low-cost transmission systems at data rates up to 32 kBaud. The transmitting frequency range is 868 MHz to 928 MHz. It can be used in both FSK and ASK systems. Figure 1-1. 1 Li cell System Block Diagram UHF ASK/FSK Remote control transmitter T5750 T5760/ T5761 Demod Control UHF ASK/FSK Remote control receiver 1 to 3 Microcontroller Keys Encoder ATARx9x PLL Antenna XTO VCO Antenna PLL XTO LNA LNA VCO 4546F–RKE–12/08 2. Pin Configuration Figure 2-1. Pinning TSSOP8L CLK PA_ENABLE ANT2 ANT1 1 2 3 4 8 7 6 5 ENABLE GND VS XTAL Table 2-1. Pin Pin Description Symbol Function Configuration VS 1 CLK Clock output signal for micro con roller The clock output frequency is set by the crystal to fXTAL/4 100Ω CLK 100Ω PA_ENABLE 50 kΩ UREF = 1.1V 2 PA_ENABLE Switches on power amplifier, used for ASK modulation 20 µA ANT1 3 4 ANT2 ANT1 Emitter of antenna output stage Open collector antenna output ANT2 2 T5750 4546F–RKE–12/08 T5750 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS VS 1.5 kΩ 1.2 kΩ 5 XTAL Connection for crystal XTAL 182 µA 6 7 VS GND Supply voltage Ground See ESD protection circuitry (see Figure 4-5 on page 9) See ESD protection circuitry (see Figure 4-5 on page 9) ENABLE 200 kΩ 8 ENABLE Enable input Figure 2-2. Block Diagram T5750 Power up/down f 1 4 8 CLK ENABLE f 64 PA_ENABLE 2 PDF 7 GND CP ANT2 3 LF 6 VS ANT1 4 PA PLL VCO XTO 5 XTAL 3 4546F–RKE–12/08 3. General Description This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The VCO is locked to 64 × fXTAL hence a 13.5672 MHz crystal is needed for a 868.3 MHz transmitter and a 14.2969 MHz crystal for a 915 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL needs typically < 1 ms until the PLL is locked and the CLK output is stable. There is a wait time of ≥ 4 ms must be used until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance. The delivered output power is hence controllable via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high power efficiency of η= Pout/(IS,PA × VS) of 24% for the power amplifier at 868.3 MHz results when an optimized load impedance of ZLoad = (166 + j226)Ω is used at 3V supply voltage. 4. Functional Description If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current, so that a lithium cell used as power supply can work for several years. With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The VCO locks to 64 times the XTO frequency. With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform the ASK modulation. 4.1 ASK Transmission The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of pin PA_ENABLE. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The T5750 is switched back to standby mode with ENABLE = L. 4.2 FSK Transmission The T5750 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥ 4 ms, then the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The T5750 is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are considered. 4 T5750 4546F–RKE–12/08 T5750 Figure 4-1. Tolerances of Frequency Modulation VS CStray1 LM XTAL CM RS CStray2 C4 C0 C5 CSwitch Using C4 = 9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capacitances on each side of the crystal of CStray1 = CStray2 = 1 pF ±10%, a parallel capacitance of the crystal of C0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an FSK deviation of ±21.5 kHz typical with worst case tolerances of ±16.8 kHz to ±28.0 kHz results. 4.3 CLK Output An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS compatible if the load capacitance is lower than 10 pF. 4.3.1 Clock Pulse Take-over The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel ® ’s ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on the T5750 with ENABLE = H, and after 4 ms to assume the clock signal of the transmission IC, so that the message can be sent with crystal accuracy. Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad,opt = (166 + j226)Ω at 868.3 MHz. There must be a low resistive path to VS to deliver the DC current. The delivered current pulse of the power amplifier is 7.7 mA and the maximum output power is delivered to a resistive load of 475Ω if the 0.53 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: Z Load = 475 Ω || j/(2 × p × f × 0.53 pF) = (166 + j226) Ω t hus results for the maximum output power of 5.5 dBm. The load impedance is defined as the impedance seen from the T5750’s ANT1, ANT2 into the matching network. Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 475Ω where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit of Figure 4-2 on page 6. Note that the component values must be changed to compensate the individual board parasitics until the T5750 has the right load impedance ZLoad,opt = (166 + j226)Ω at 868.3 MHz. Also the damping of the cable used to measure the output power must be calibrated out. 4.3.2 5 4546F–RKE–12/08 Figure 4-2. Output Power Measurement VS C1 1 nF L1 ANT1 ZLopt ANT2 10 nH C2 1.5 pF C3 Z = 50Ω Power meter Rin 2.7 pF 50Ω 4.4 Application Circuit For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is recommended (see Figure 4-3 on page 7 and Figure 4-4 on page 8). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 3.9 pF/NP0 and C2 is 1 pF/NP0; for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the ZLoad,opt by using standard valued capacitors. C1 forms together with the pins of T5750 and the PCB board wires a series resonance loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 (≈ 50 nH to 100 nH) can be printed on PCB. C4 should be selected so that the XTO runs on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF load-capacitance crystal. 6 T5750 4546F–RKE–12/08 T5750 Figure 4-3. ASK Application Circuit S1 BPXY ATARx9x 1 VDD VS VSS 20 S2 BPXY BPXY OSC1 7 BPXY T5750 Power up/down CLK 1 f 4 8 ENABLE f 64 PA_ENABLE 2 PDF 7 GND C3 CP ANT2 3 Loop Antenna C1 LF 6 VS VS C2 ANT1 4 L1 PA PLL VCO XTO 5 XTAL XTAL C4 VS 7 4546F–RKE–12/08 Figure 4-4. FSK Application Circuit S1 BPXY ATARx9x 1 VDD VS VSS 20 S2 BPXY BPXY 18 OSC1 7 BP42/T2O BPXY T5750 Power up/down CLK 1 f 4 8 ENABLE f 64 PA_ENABLE 2 PDF 7 GND C3 CP ANT2 3 Loop Antenna C1 LF 6 VS C5 ANT1 4 L1 PA PLL VCO XTO 5 C4 XTAL XTAL VS C2 VS 8 T5750 4546F–RKE–12/08 T5750 Figure 4-5. ESD Protection Circuit VS ANT1 CLK PA_ENABLE ANT2 XTAL ENABLE GND 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Input voltage Note: Symbol VS Ptot Tj Tstg Tamb VmaxPA_ENABLE –55 –55 –0.3 Minimum Maximum 5 100 150 125 125 (VS + 0.3) (1) Unit V mW °C °C °C V 1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V. 6. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 170 Unit K/W 7. Electrical Characteristics VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7). Parameters Test Conditions Power down, VENABLE < 0.25V, –40°C to 85°C VPA_ENABLE < 0.25V, –85°C to +125°C VPA_ENABLE < 0.25V, 25°C (100% correlation tested) Power up, PA off, VS = 3V, VENABLE > 1.7V, VPA_ENABLE < 0.25V Power up, VS = 3.0, VENABLE > 1.7V, VPA_ENABLE > 1.7V VS = 3.0V, Tamb = 25°C, f = 868.3 MHz, ZLoad = (166 + j226)Ω Symbol Min. Typ. Max. 350 7 1.7 V, VPA-ENABLE < 0.25 V Power up, VS = 3.0 V, VENABLE > 1.7 V, VPA-ENABLE > 1.7 V Symbol Min. Typ. Max. 350 7 < 10 Unit nA µA nA Supply current IS_Off Supply current Supply current Output power Note: IS IS_Transmit 6.0 3.7 9 8.0 4.8 11.6 10.5 mA mA dBm VS = 3.0V, Tamb = 25°C, PRef f = 315 MHz, ZLoad = (255 + j192)W 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 9 4510J–RKE–12/08 7. Electrical Characteristics (Continued) VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified. Typical values are given at VS = 3.0V and Tamb = 25°C. All parameters are referred to GND (pin 7). Parameters Output power variation for the full temperature range Test Conditions Tamb = –40°C to +85°C, VS = 3.0V VS = 2.0V Tamb = –40°C to +125°C, VS = 3.0V VS = 2.0V, POut = PRef + ΔPRef Selectable by load impedance fCLK = f0/128 Load capacitance at pin CLK = 10 pF fO ±1 × fCLK fO ±4 × fCLK other spurious are lower fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM ≤ 10 fF, load capacitance selected accordingly Tamb = –40°C to +85°C, Tamb = –40°C to +125°C Referred to fPC = fXT0, 25 kHz distance to carrier 25 kHz distance to carrier at 1 MHz at 36 MHz fVCO 310 f0/128 CLoad ≤ 10 pF V0h V0l Rs Duty cycle of the modulation signal = 50% Duty cycle of the modulation signal = 50% Low level input voltage High level input voltage Input current high VIl VIh IIn 0 0 1.7 20 1.7 0.25 VS(1) 5 VS × 0.8 VS × 0.2 110 7 32 32 0.25 Symbol ΔPRef ΔPRef ΔPRef ΔPRef POut_typ 0 Min. Typ. Max. –1.5 –4.0 –2.0 –4.5 8.0 Unit dB dB dB dB dBm Output power variation for the full temperature range Achievable output-power range Spurious emission –55 –52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO –30 –40 fXTAL 250 –116 –86 –94 –125 –110 –80 –90 –121 350 +30 +40 ppm ppm kHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz MHz V V Ω pF kHz kHz V V µA V V µA PLL loop bandwidth Phase noise of phase comparator In loop phase noise PLL Phase noise VCO Frequency range of VCO Clock output frequency (CMOS microcontroller compatible) Voltage swing at pin CLK Series resonance R of the crystal Capacitive load at pin XT0 FSK modulation frequency rate ASK modulation frequency rate ENABLE input PA_ENABLE input Note: Low level input voltage VIl VIh High level input voltage IIn Input current high 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 10 T5753 4510J–RKE–12/08 T5753 8. Ordering Information Extended Type Number T5753-6AQJ T5753-6APJ Note: 1. J Package TSSOP8L TSSOP8L = –40°C to +125°C + lead-free Remarks Taped and reeled, Marking: T573, Pb-free Taped and reeled, Marking: T573, small reel, Pb-free 9. Package Information Package: TSSOP 8L Dimensions in mm 0.85±0.05 1-0.15 +0.05 3±0.1 3±0.1 0.31-0.07 0.65 nom. 3 x 0.65 = 1.95 nom. 8 5 3.8±0.3 4.9±0.1 technical drawings according to DIN specifications Drawing-No.: 6.543-5083.01-4 Issue: 2; 15.03.04 1 4 5 0.15-0.02 +0.0 +0.06 0.1±0.05 11 4510J–RKE–12/08 10. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4510J-RKE-12/08 4510I-RKE-02/07 4510H-RKE-09/05 History • Put datasheet in the newest template • Section 4.3.1 “Clock Pulse Take-over” on page 5 changed • Put datasheet in the newest template • Pb-free Logo on page 1 deleted • Pb-free Logo on page 1 added • • • • • • • • • • Put datasheet in the newest template Section 1 “Description” on page 1 changed Figure title Figure 4-2 on page 6 changed Table “Electrical Characteristics” on pages 9 to 10 changed Table “Ordering Information” on page 11 changed Table “Absolute Maximum Ratings” (page 8): row “Input voltage” added Table “Absolute Maximum Ratings” (page 8): table note 1 added Table “Electrical Characteristics” (page 10): row “PA_ENABLE input“ changed Table “Electrical Characteristics” (page 10): table note 1 added Table “Ordering Information” (page 11): Remarks changed 4510G-RKE-02/05 4510F-RKE-02/05 12 T5753 4510J–RKE–12/08 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2008 Atmel Corporation. All rights reserved. A tmel®, logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4510J–RKE–12/08 Features • Integrated PLL Loop Filter • ESD Protection also at ANT1/ANT2 (4 kV HBM/200V MM; Except Pin 2: 4 kV HBM/100V MM) • High Output Power (7.5 dBm) with Low Supply Current (9.0 mA) • Modulation Scheme ASK/ FSK – FSK Modulation is Achieved by Connecting an Additional Capacitor Between the XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply Single Li-cell for Power Supply Supply Voltage 2.0V to 4.0V in the Temperature Range of –40°C to 85°C/125°C Package TSSOP8L Single-ended Antenna Output with High Efficient Power Amplifier CLK Output for Clocking the Microcontroller One-chip Solution with Minimum External Circuitry 125° C Operation for Tire Pressure Systems • • • • • • • • UHF ASK/FSK Transmitter T5754 1. Description The T5754 is a PLL transmitter IC which has been developed for the demands of RF low-cost transmission systems at data rates up to 32 kBaud. The transmitting frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK systems. Figure 1-1. 1 Li cell System Block Diagram UHF ASK/FSK Remote control transmitter T5754 U3741B/ U3745B/ T5743/ T5744 PLL Antenna XTO VCO Antenna PLL XTO UHF ASK/FSK Remote control receiver 1 to 3 Demod Control Microcontroller Keys Encoder ATARx9x Power amp. LNA VCO 4511I–RKE–02/07 2. Pin Configuration Figure 2-1. Pinning TSSOP8L CLK PA_ENABLE ANT2 ANT1 1 2 3 4 8 7 6 5 ENABLE GND VS XTAL Table 2-1. Pin Pin Description Symbol Function Configuration VS 1 CLK Clock output signal for micro con roller The clock output frequency is set by the crystal to fXTAL/4 100Ω CLK 100Ω PA_ENABLE 50 kΩ UREF = 1.1V 2 PA_ENABLE Switches on power amplifier, used for ASK modulation 20 µA ANT1 3 4 ANT2 ANT1 Emitter of antenna output stage Open collector antenna output ANT2 2 T5754 4511I–RKE–02/07 T5754 Table 2-1. Pin Pin Description (Continued) Symbol Function Configuration VS VS 1.5 kΩ 1.2 kΩ 5 XTAL Connection for crystal XTAL 182 µA 6 7 VS GND Supply voltage Ground See ESD protection circuitry (see Figure 4-5 on page 9) See ESD protection circuitry (see Figure 4-5 on page 9) ENABLE 200 kΩ 8 ENABLE Enable input Figure 2-2. Block Diagram T5754 Power up/down f 1 4 8 CLK ENABLE f 32 PA_ENABLE 2 PDF 7 GND CP ANT2 3 LF 6 VS ANT1 4 PA PLL VCO XTO 5 XTAL 3 4511I–RKE–02/07 3. General Description This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature transmitters to be assembled. The VCO is locked to 32 fXTAL hence a 13.56 MHz crystal is needed for a 433.92 MHz transmitter. All other PLL and VCO peripheral elements are integrated. The XTO is a series resonance oscillator so that only one capacitor together with a crystal connected in series to GND are needed as external elements. The crystal oscillator together with the PLL needs typically < 1 ms until the PLL is locked and the CLK output is stable. There is a wait time of ≥ 1 ms until the CLK is used for the microcontroller and the PA is switched on. The power amplifier is an open-collector output delivering a current pulse which is nearly independent from the load impedance. The delivered output power is hence controllable via the connected load impedance. This output configuration enables a simple matching to any kind of antenna or to 50Ω. A high power efficiency of η= Pout/(IS,PA VS) of 36% for the power amplifier results when an optimized load impedance of ZLoad = (166 + j223)Ω is used at 3V supply voltage. 4. Functional Description If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only a very small amount of current so that a lithium cell used as power supply can work for several years. With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE remains L only the PLL and the XTO is running and the CLK signal is delivered to the microcontroller. The VCO locks to 32 times the XTO frequency. With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power amplifier are on. With PA_ENABLE the power amplifier can be switched on and off, which is used to perform the ASK modulation. 4.1 ASK Transmission The T5754 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then the CLK signal can be taken to clock the microcontroller and the output power can be modulated by means of pin PA_ENABLE. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The T5754 is switched back to standby mode with ENABLE = L. 4.2 FSK Transmission The T5754 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then the CLK signal can be taken to clock the microcontroller and the power amplifier is switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The microcontroller starts to switch on and off the capacitor between the XTAL load capacitor and GND with an open-drain output port, thus changing the reference frequency of the PLL. If the switch is closed, the output frequency is lower than if the switch is open. After transmission PA_ENABLE is switched to L and the microcontroller switches back to internal clocking. The T5754 is switched back to standby mode with ENABLE = L. The accuracy of the frequency deviation with XTAL pulling method is about ±25% when the following tolerances are considered. 4 T5754 4511I–RKE–02/07 T5754 Figure 4-1. Tolerances of Frequency Modulation VS CStray1 LM XTAL CM RS CStray2 C4 C0 Crystal equivalent circuit C5 CSwitch Using C4 = 9.2 pF ±2%, C5 = 6.8 pF ±5%, a switch port with CSwitch = 3 pF ±10%, stray capacitances on each side of the crystal of CStray1 = CStray2 = 1 pF ±10%, a parallel capacitance of the crystal of C0 = 3.2 pF ±10% and a crystal with CM = 13 fF ±10%, an FSK deviation of ±21 kHz typical with worst case tolerances of ±16.3 kHz to ±28.8 kHz results. 4.3 CLK Output An output CLK signal is provided for a connected microcontroller, the delivered signal is CMOS compatible if the load capacitance is lower than 10 pF. 4.3.1 Clock Pulse Take-over The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel ® ’s ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on the T5754 with ENABLE = H, and after 1 ms to assume the clock signal of the transmission IC, so that the message can be sent with crystal accuracy. Output Matching and Power Setting The output power is set by the load impedance of the antenna. The maximum output power is achieved with a load impedance of ZLoad,opt = (166 + j223)Ω. There must be a low resistive path to VS to deliver the DC current. The delivered current pulse of the power amplifier is 9 mA and the maximum output power is delivered to a resistive load of 465Ω if the 1.0 pF output capacitance of the power amplifier is compensated by the load impedance. An optimum load impedance of: ZLoad = 465Ω || j/(2 × π 1.0 pF) = (166 + j223)Ω thus results for the maximum output power of 7.5 dBm. The load impedance is defined as the impedance seen from the T5754’s ANT1, ANT2 into the matching network. Do not confuse this large signal load impedance with a small signal input impedance delivered as input characteristic of RF amplifiers and measured from the application into the IC instead of from the IC into the application for a power amplifier. Less output power is achieved by lowering the real parallel part of 465Ω where the parallel imaginary part should be kept constant. Output power measurement can be done with the circuit of Figure 4-2 on page 6. Note that the component values must be changed to compensate the individual board parasitics until the T5754 has the right load impedance ZLoad,opt = (166 + j223)Ω. Also the damping of the cable used to measure the output power must be calibrated out. 4.3.2 5 4511I–RKE–02/07 Figure 4-2. Output Power Measurement VS C1 1 nF L1 ANT1 ZLopt ANT2 33 nH C2 2.2 pF Z = 50Ω Power meter Rin 50Ω 4.4 Application Circuit For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is recommended (see Figure 4-3 on page 7 and Figure 4-4 on page 8). C1 and C2 are used to match the loop antenna to the power amplifier where C1 typically is 8.2 pF/NP0 and C2 is 6 pF/NP0 (10 pF + 15 pF in series); for C2 two capacitors in series should be used to achieve a better tolerance value and to have the possibility to realize the ZLoad,opt by using standard valued capacitors. C1 forms together with the pins of T5754 and the PCB board wires a series resonance loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important. Normally the best suppression is achieved when C1 is placed as close as possible to the pins ANT1 and ANT2. The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the loop antenna is too high. L1 ([50 nH to 100 nH) can be printed on PCB. C4 should be selected that the XTO runs on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a 15 pF load-capacitance crystal. 6 T5754 4511I–RKE–02/07 T5754 Figure 4-3. ASK Application Circuit S1 BPXY ATARx9x 1 VDD VS VSS 20 S2 BPXY BPXY OSC1 7 BPXY T5754 Power up/down CLK 1 f 4 8 ENABLE f 32 PA_ENABLE 2 PDF 7 GND C3 CP ANT2 3 Loop Antenna C1 LF 6 VS VS C2 ANT1 4 L1 PA PLL VCO XTO 5 XTAL XTAL C4 VS 7 4511I–RKE–02/07 Figure 4-4. FSK Application Circuit S1 BPXY ATARx9x 1 VDD VS VSS 20 S2 BPXY BPXY 18 OSC1 7 BP42/T2O BPXY T5754 Power up/down CLK 1 f 4 8 ENABLE f 32 PA_ENABLE 2 PDF 7 GND C3 CP ANT2 3 Loop Antenna C1 LF 6 VS C5 ANT1 4 L1 PA PLL VCO XTO 5 C4 XTAL XTAL VS C2 VS 8 T5754 4511I–RKE–02/07 T5754 Figure 4-5. ESD Protection Circuit VS ANT1 CLK PA_ENABLE ANT2 XTAL ENABLE GND 5. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Power dissipation Junction temperature Storage temperature Ambient temperature Input voltage Note: Symbol VS Ptot Tj Tstg Tamb VmaxPA_ENABLE –55 –55 –0.3 Minimum Maximum 5 100 150 125 125 (VS + 0.3) (1) Unit V mW °C °C °C V 1. If VS + 0.3 is higher than 3.7V, the maximum voltage will be reduced to 3.7V. 6. Thermal Resistance Parameters Junction ambient Symbol RthJA Value 170 Unit K/W 7. Electrical Characteristics VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (pin 7). Parameters Test Conditions Power down VENABLE < 0.25V, –40°C to 85°C VPA-ENABLE < 0.25V, –40°C to +125°C VPA-ENABLE < 0.25V, 25°C (100% correlation tested) Power up, PA off, VS = 3V, VENABLE > 1.7V, VPA-ENABLE < 0.25V Power up, VS = 3.0V, VENABLE > 1.7V, VPA-ENABLE > 1.7V VS = 3.0V, Tamb = 25°C, f = 433.92 MHz, ZLoad = (166 + j233)Ω Symbol Min. Typ. Max. 350 7 < 10 Unit nA µA nA Supply current IS_Off Supply current Supply current Output power Note: IS IS_Transmit PRef 5.5 3.7 9 7.5 4.8 11.6 10 mA mA dBm 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 9 4511I–RKE–02/07 7. Electrical Characteristics (Continued) VS = 2.0V to 4.0V, Tamb = –40°C to 125°C unless otherwise specified. Typical values are given at VS = 3.0 V and Tamb = 25°C. All parameters are referred to GND (pin 7). Parameters Output power variation for the full temperature range Test Conditions Tamb = –40°C to +85°C, VS = 3.0V VS = 2.0V Tamb = –40°C to +125°C, VS = 3.0V VS = 2.0V POut = PRef + ∆PRef Selectable by load impedance fCLK = f0/128 Load capacitance at pin CLK = 10 pF fO ±1 × fCLK fO ±4 × fCLK other spurious are lower fXTO = f0/32 fXTAL = resonant frequency of the XTAL, CM ≤ 10 fF, load capacitance selected accordingly Tamb = –40°C to +85°C Tamb = –40°C to +125°C Referred to fPC = fXT0, 25 kHz distance to carrier 25 kHz distance to carrier at 1 MHz at 36 MHz fVCO 429 f0/128 CLoad ≤10 pF V0h V0l Rs Duty cycle of the modulation signal = 50% Duty cycle of the modulation signal = 50% Low level input voltage High level input voltage Input current high Low level input voltage High level input voltage Input current high VIl VIh IIn VIl VIh IIn 0 0 1.7 20 1.7 0.25 VS(1) 5 VS × 0.8 VS × 0.2 110 7 32 32 0.25 Symbol ∆PRef ∆PRef ∆PRef ∆PRef POut_typ 0 Min. Typ. Max. –1.5 –4.0 –2.0 –4.5 7.5 Unit dB dB dB dB dBm Output power variation for the full temperature range Achievable output-power range Spurious emission –55 –52 dBc dBc Oscillator frequency XTO (= phase comparator frequency) fXTO –30 –40 fXTAL 250 –116 –86 –94 –125 –110 –80 –90 –121 439 +30 +40 ppm ppm kHz dBc/Hz dBc/Hz dBc/Hz dBc/Hz MHz MHz V V Ω pF kHz kHz V V µA V V µA PLL loop bandwidth Phase noise of phase comparator In loop phase noise PLL Phase noise VCO Frequency range of VCO Clock output frequency (CMOS microcontroller compatible) Voltage swing at pin CLK Series resonance R of the crystal Capacitive load at pin XT0 FSK modulation frequency rate ASK modulation frequency rate ENABLE input PA_ENABLE input Note: 1. If VS is higher than 3.6V, the maximum voltage will be reduced to 3.6V. 10 T5754 4511I–RKE–02/07 T5754 8. Ordering Information Extended Type Number T5754-6AQJ T5754-6APJ Package TSSOP8L TSSOP8L Remarks Taped and reeled, Marking: T574, Pb-free Taped and reeled, Marking: T574, small reel, Pb-free 9. Package Information Package: TSSOP 8L Dimensions in mm 0.85±0.05 1-0.15 +0.05 3±0.1 3±0.1 0.31-0.07 0.65 nom. 3 x 0.65 = 1.95 nom. 8 5 3.8±0.3 4.9±0.1 technical drawings according to DIN specifications Drawing-No.: 6.543-5083.01-4 Issue: 2; 15.03.04 1 4 5 0.15-0.02 +0.0 +0.06 0.1±0.05 11 4511I–RKE–02/07 10. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4711I-RKE-02/07 4711H-RKE-09/05 History • Put datasheet in a new template • Pb-free logo on page 1 deleted • Pb-free logo on page 1 added • Ordering Information on page 11 changed • Put datasheet in a new template • Package Information (page 11): Replace old package drawing through current version • • • • • Abs. Max. Ratings table (page 9): row “Input voltage” added Abs. Max. Ratings table (page 9): table note 1 added El. Char. table (pages 9 to 10): row “PA_ENABLE input“ changed El. Char. table (pages 9 to 10): table note 1 added Ordering Information table (page 11): Remarks changed 4711G-RKE-05/05 4711F-RKE-07/04 12 T5754 4511I–RKE–02/07 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. A tmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2007 Atmel Corporation. A ll rights reserved. A tmel ®, logo and combinations thereof, Everywhere You Are® a nd others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. 4511I–RKE–02/07 Features • High Performance, Low Power AVR® 8-Bit Microcontroller • Advanced RISC Architecture – 120 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Non-volatile Program and Data Memories – 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny24/44/84) Endurance: 10,000 Write/Erase Cycles – 128/256/512 Bytes In-System Programmable EEPROM (ATtiny24/44/84) Endurance: 100,000 Write/Erase Cycles – 128/256/512 Bytes Internal SRAM (ATtiny24/44/84) – Programming Lock for Self-Programming Flash Program and EEPROM Data Security Peripheral Features – Two Timer/Counters, 8- and 16-bit counters with two PWM Channels on both – 10-bit ADC 8 single-ended channels 12 differential ADC channel pairs with programmable gain (1x, 20x) Temperature Measurement – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Universal Serial Interface Special Microcontroller Features – debugWIRE On-chip Debug System – In-System Programmable via SPI Port – External and Internal Interrupt Sources – Pin Change Interrupt on 12 pins – Low Power Idle, ADC Noise Reduction, Standby and Power-down Modes – Enhanced Power-on Reset Circuit – Programmable Brown-out Detection Circuit – Internal Calibrated Oscillator – On-chip Temperature Sensor I/O and Packages – 14-pin SOIC, 20-pin QFN/MLF: Twelve Programmable I/O Lines Operating Voltage: – 2.7 - 5.5V for ATtiny24/44/84 Speed Grade – ATtiny24/44/84: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V Automotive Temperature Range Low Power Consumption – Active Mode: 1 MHz, 2.7V: 800 µA – Power-down Mode: 2.7V: 2.0 µA • • 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash ATtiny24/44/84 Automotive Preliminary • • • • • • Rev. 7701C–AVR–12/08 1. Pin Configurations Figure 1-1. Pinout ATtiny24/44/84 SOIC VCC (PCINT8/XTAL1) PB0 (PCINT9/XTAL2) PB1 (PCINT11/RESET/dW) PB3 (PCINT10/INT0/OC0A/CKOUT) PB2 (PCINT7/ICP/OC0B/ADC7) PA7 (PCINT6/OC1A/SDA/MOSI/ADC6) PA6 1 2 3 4 5 6 7 14 13 12 11 10 9 8 GND PA0 (ADC0/AREF/PCINT0) PA1 (ADC1/AIN0/PCINT1) PA2 (ADC2/AIN1/PCINT2) PA3 (ADC3/T0/PCINT3) PA4 (ADC4/USCK/SCL/T1/PCINT4) PA5 (ADC5/DO/MISO/OC1B/PCINT5) QFN/MLF Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/ADC6) Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5) PA7 (PCINT7/ICP/OC0B/ADC7) PB2 (PCINT10/INT0/OC0A/CKOUT) PB3 (PCINT11/RESET/dW) PB1 (PCINT9/XTAL2) PB0 (PCINT8/XTAL1) PA5 DNC DNC DNC PA6 NOTE Bottom pad should be soldered to ground. DNC: Do Not Connect 1.1 Disclaimer Typical values contained in this data sheet are based on simulations and characterization of actual ATtiny24/44/84 AVR microcontrollers manufactured on the typical process technology. Applicable Automotive Min. and Max. values will be available after devices representative of the whole process excursion (corner run) have been characterized. 2 ATtiny24/44/84 7701C–AVR–12/08 DNC DNC GND VCC DNC 6 7 8 9 10 (ADC4/USCK/SCL/T1/PCINT4) PA4 (ADC3/T0/PCINT3) PA3 (ADC2/AIN1/PCINT2) PA2 (ADC1/AIN0/PCINT1) PA1 (ADC0/AREF/PCINT0) PA0 1 2 3 4 5 20 19 18 17 16 15 14 13 12 11 ATtiny24/44/84 2. Overview The ATtiny24/44/84 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny24/44/84 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1. VCC 8-BIT DATABUS INTERNAL OSCILLATOR GND PROGRAM COUNTER STACK POINTER Block Diagram INTERNAL CALIBRATED OSCILLATOR WATCHDOG TIMER MCU CONTROL REGISTER TIMING AND CONTROL PROGRAM FLASH SRAM INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z MCU STATUS REGISTER TIMER/ COUNTER0 TIMER/ COUNTER1 INSTRUCTION DECODER CONTROL LINES ALU STATUS REGISTER INTERRUPT UNIT PROGRAMMING LOGIC ISP INTERFACE EEPROM OSCILLATORS ANALOG COMPARATOR DATA REGISTER PORT A DATA DIR. REG.PORT A ADC DATA REGISTER PORT B DATA DIR. REG.PORT B + - PORT A DRIVERS PORT B DRIVERS PA7-PA0 PB3-PB0 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent 3 7701C–AVR–12/08 registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATtiny24/44/84 provides the following features: 2/4/8K byte of In-System Programmable Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 12 general purpose I/O lines, 32 general purpose working registers, a 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC, programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable Watchdog Timer with internal Oscillator, internal calibrated oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The Power-down mode saves the register contents, disabling all chip functions until the next Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured ng Atmel’s high density non-volatile memory technology. The Onchip ISP Flash allows the Program memory to be re-programmed In-System through an SPI serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code running on the AVR core. The ATtiny24/44/84 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits. 2.2 Automotive Quality Grade The ATtiny24/44/84 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949 grade 1. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATtiny24/44/84 have been verified during regular product qualification as per AEC-Q100. As indicated in the ordering information paragraph, the product is available in only one temperature grade, Table 2-1. Temperature -40 ; +125 Temperature Grade Identification for Automotive Products Temperature Identifier Z Comments Full AutomotiveTemperature Range 4 ATtiny24/44/84 7701C–AVR–12/08 ATtiny24/44/84 2.3 2.3.1 Pin Descriptions VCC Supply voltage. 2.3.2 GND Ground. 2.3.3 Port B (PB3...PB0) Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability except PB3 which has the RESET capability. To use pin PB3 as an I/O pin, instead of RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port B also serves the functions of various special features of the ATtiny24/44/84 as listed on Section 12.3 ”Alternate Port Functions” on page 61. 2.3.4 RESET Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page 41. Shorter pulses are not guaranteed to generate a reset. 2.3.5 Port A (PA7...PA0) Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A has an alternate functions as analog inputs for the ADC, analog comparator, timer/counter, SPI and pin change interrupt as described in ”Alternate Port Functions” on page 61 5 7701C–AVR–12/08 3. Resources A comprehensive set of development tools, drivers and application notes, and datasheets are available for download on http://www.atmel.com/avr. 4. About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. 6 ATtiny24/44/84 7701C–AVR–12/08 ATtiny24/44/84 5. CPU Core 5.1 Overview This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 5.2 Architectural Overview Figure 5-1. Block Diagram of the AVR Architecture Data Bus 8-bit Flash Program Memory Program Counter Status and Control Instruction Register 32 x 8 General Purpose Registrers Interrupt Unit Watchdog Timer Indirect Addressing Instruction Decoder Direct Addressing ALU Control Lines Analog Comparator Timer/Counter 0 Data SRAM Timer/Counter 1 Universal Serial Interface EEPROM I/O Lines In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables instructions to be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash memory. 7 7701C–AVR–12/08 The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash Program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. 5.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. 5.4 Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. 8 ATtiny24/44/84 7701C–AVR–12/08 ATtiny24/44/84 5.4.1 SREG – AVR Status Register Bit 0x3F (0x5F) Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕ V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 9 7701C–AVR–12/08 5.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 5-2 on page 10 shows the structure of the 32 general purpose working registers in the CPU. Figure 5-2. AVR CPU General Purpose Working Registers 7 R0 R1 R2 … R13 General Purpose Working Registers R14 R15 R16 R17 … R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Addr. 0x00 0x01 0x02 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 5-2, each register is also assigned a Data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 5.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 5-3 on page 11. 10 ATtiny24/44/84 7701C–AVR–12/08 ATtiny24/44/84 Figure 5-3. The X-, Y-, and Z-registers 15 X-register 7 R27 (0x1B) XH 0 7 R26 (0x1A) XL 0 0 15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F) YH 0 7 R28 (0x1C) ZH 0 7 R30 (0x1E) YL 0 0 ZL 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 5.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. 5.6.1 SPH and SPL – Stack Pointer High and Low Bit 0x3E (0x5E) 0x3D (0x5D) 15 SP15 SP7 7 14 SP14 SP6 6 R/W R/W 0 0 13 SP13 SP5 5 R/W R/W 0 0 12 SP12 SP4 4 R/W R/W 0 0 11 SP11 SP3 3 R/W R/W 0 0 10 SP10 SP2 2 R/W R/W 0 0 9 SP9 SP1 1 R/W R/W 0 0 8 SP8 SP0 0 R/W R/W 0 0 SPH SPL Read/Write R/W R/W Initial Value 0 0 11 7701C–AVR–12/08 5.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 5-4 on page 12 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 5-4. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 5-5 on page 12 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. Figure 5-5. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 5.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. The lowest addresses in the Program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 50. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. 12 ATtiny24/44/84 7701C–AVR–12/08 ATtiny24/44/84 When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.. Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; start EEPROM write ; disable interrupts during timed sequence C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1