ATA6612

General Features • Single-package Fully-integrated Atmel® AVR® 8-bit Microcontroller with LIN • • • • • • Transceiver, 5V Regulator and Watchdog Very Low Current Consumption in Sleep Mode 8 Kbytes/16 Kbytes Flash Memory for Application Program (ATA6612/ATA6613) Supply Voltage Up to 40V Operating Voltage: 5V to 27V Temperature Range: Tcase –40°C to +125°C QFN48, 7 mm × 7 mm Package 1. Description ATA6612/ATA6613 is a System-in-Package (SiP) product, which is particularly suited for complete LIN-bus slave-node applications. It supports highly integrated solutions for in-vehicle LIN networks. The first chip is the LIN-system-basis-chip (LIN-SBC) ATA6624, which has an integrated LIN transceiver, a 5V regulator and a window watchdog. The second chip is an automotive microcontroller from Atmel’s series of Atmel AVR 8-bit microcontroller with advanced RISC architecture. The ATA6612 consists of the LIN-SBC ATA6624 and the ATmega88 with 8 Kbytes flash. The ATA6613 consists of the LIN-SBC ATA6624 and the ATmega168 with 16 Kbytes flash. All pins of the LIN System Basis Chip as well as all pins of the Atmel AVR microcontroller are bonded out to provide customers the same flexibility for their applications as they have when using discrete parts. In section 2 you will find the pin configuration for the complete SiP. In sections 3 to 5 the LIN SBC is described, and in sections 6 to 7 the Atmel AVR is described in detail. Figure 1-1. Application Diagram LIN Bus Microcontroller with LIN Transceiver, 5V Regulator and Watchdog ATA6612 ATA6613 ATA6612/ATA6613 MCU ATmega88 or ATmega168 LIN-SBC ATA6624 9111G–AUTO–05/10 2. Pin Configuration Figure 2-1. Pinning QFN48, 7 mm × 7 mm PB4 PB3 PB2 PB1 PB0 PD7 PD6 PD5 PB7 PB6 MCUVDD2 GND2 PB5 MCUAVDD ADC6 AREF GND4 ADC7 PC0 PC1 PC2 PC3 PC4 PC5 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 31 6 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 PC6 PD0 PD1 PD2 RXD INH TXD NRES WD_OSC TM MODE KL_15 MCUVDD1 GND1 PD4 PD3 LIN GND WAKE NTRIG EN VS VCC PVCC Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 (1) Pin Description Symbol PB5 MCUAVDD ADC6 AREF GND4 ADC7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PD0 PD1 PD2 RXD INH TXD Function Port B 5 I/O line (SCK / PCINT5) Microcontroller ADC-unit supply voltage ADC input channel 6 Analog reference voltage input Ground ADC input channel 7 Port C 0 I/O line (ADC0/PCINT8) Port C 1 I/O line (ADC1/PCINT9) Port C 2 I/O line (ADC2/PCINT10) Port C 3 I/O line (ADC3/PCINT11) Port C 4 I/O line (ADC4/SDA/PCINT12) Port C 5 I/O line (ADC5/SCL/PCINT13) Port C 6 I/O line (RESET/PCINT14) Port D 0 I/O line (RXD/PCINT16) Port D 1 I/O line (TXD/PCINT17) Port D 2 I/O line (INT0/PCINT18) Receive data output High side switch output for controlling an external voltage regulator Transmit data input / active low output after a local wake up request 18(1) 19(1) Note: 1. This identifies the pins of the LIN SBC ATA6624 2 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 Table 2-1. Pin 20 21 23 24 25 27 28 29 (1) (1) Pin Description (Continued) Symbol NRES WD_OSC TM MODE KL_15 PVCC VCC VS EN NTRIG WAKE GND LIN PD3 PD4 GND1 MCUVDD1 GND2 MCUVDD2 PB6 PB7 PD5 PD6 PD7 PB0 PB1 PB2 PB3 PB4 Function Watchdog and undervoltage reset output (open drain) External resistor for adjustable watchdog timing Tie to Ground – for factory use only Connect to GND for normal watchdog operation or connect to VCC for debug mode Ignition detection (edge sensitive) Voltage regulator sense input Voltage regulator output Battery connection LIN-transceiver enable input Watchdog trigger input (negative edge) System-basis-chip external wake-up input Analog system GND LIN-bus input/output Port D 3 I/O line (INT1 OC2B/PCINT19) Port D 4 I/O line (T0/XCK/PCINT20) Ground Microcontroller supply voltage Ground Microcontroller supply voltage Port B 6 I/O line (TOSC1/XTAL1/PCINT6) Port B 7 I/O line (TOSC2/XTAL2/PCINT7) Port D 5 I/O line (T1/OC0B/PCINT21) Port D 6 I/O line (AIN0/OC0A PCINT22) Port D 7 I/O line (AIN1/PCINT23) Port B 0 I/O line (ICP1/CLKO/PCINT0) Port B 1 I/O line (OC1A/PCINT1) Port B 2 I/O line (OC1B/SS/PCINT2) Port B 3 I/O line (MOSI/OC2A/PCINT3) Port B 4 I/O line (MISO/PCINT4) Heat slug is connected to GND 22(1) (1) (1) (1) 26(1) (1) (1) (1) 30(1) 31(1) 32 (1) 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Backside Note: 1. This identifies the pins of the LIN SBC ATA6624 3 9111G–AUTO–05/10 Table 2-2. Maximum Ratings of the SiP Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) CDM ESD STM 5.3.1 Storage temperature Operating temperature(1) Thermal resistance junction to heat slug Thermal resistance junctiion to ambient Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Note: Ts Tcase Rthjc Rthja 150 150 Symbol Min. Typ. Max. Unit ±2 KV ±750 –55 –40 6 30 165 165 10 170 170 +150 +125 V °C °C K/W K/W °C °C °C 1. Tcase means the temperature of the heat slug (backside). It is mandatory that this backside temperature is ≤ 125°C in the application. 4 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 3. LIN System-basis-chip Block 3.1 Features • • • • • • • • • • • • • • • • • • • • Master and Slave Operation Possible Supply Voltage up to 40V Operating voltage VS = 5V to 27V Typically 10 µA Supply Current During Sleep Mode Typically 57 µA Supply Current in Silent Mode Linear Low-drop Voltage Regulator: Normal, Fail-safe, and Silent Mode VCC = 5.0V ±2% In Sleep Mode VCC is Switched Off VCC- Undervoltage Detection (4 ms Reset Time) and Watchdog Reset Logical Combined at Open Drain Output NRES Negative Trigger Input for Watchdog Boosting the Voltage Regulator Possible with an External NPN Transistor LIN Physical Layer According to LIN 2.0, 2.1 Specification and SAEJ2602-2 Wake-up Capability via LIN-bus, Wake Pin, or Kl_15 Pin INH Output to Control an External Voltage Regulator or to Switch off the Master Pull Up Resistor TXD Time-out Timer Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery Adjustable Watchdog Time via External Resistor Advanced EMC and ESD Performance ESD HBM 8 kV at Pins LIN and VS According to STM5.1 3.2 Description The LIN-SBC is a fully integrated LIN transceiver, which complies with the LIN 2.1 and SAEJ2602-2 specifications. It has a low-drop voltage regulator for 5V/50 mA output and a window watchdog. The LIN-SBC are designed to handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver ensures secure data communication up to 20 kBaud. Sleep Mode and Silent Mode guarantee very low current consumption. 5 9111G–AUTO–05/10 Figure 3-1. Block Diagram VS Normal and Fail-safe Mode PVCC Receiver INH RXD Normal Mode + RF Filter WAKE KL_15 PVCC Edge Detection Wake-up Bus Timer LIN TXD TXD Time-out Timer Slew Rate Control Short Circuit and Overtemperature Protection Control Unit EN Debounce Time Mode Select Normal/Silent/ Fail-safe Mode 3.3/5V /50 mA/±2% Undervoltage Reset VCC PVCC NRES Internal Testing Unit GND PVCC OUT Watchdog Adjustable Watchdog Oscillator WD_OSC MODE TM NTRIG 6 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 3.3 3.3.1 Functional Description Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.1 can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions. Supply Pin (VS) The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS falls below VSth < 4V in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the voltage regulator is switched on (i.e., output capability). The supply current is typically 10 µA in Sleep Mode and 57 µA in Silent Mode. 3.3.2 3.3.3 Ground Pin (GND) The IC is neutral on the LIN pin in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS. The mandatory system ground is pin 5. Voltage Regulator Output Pin (VCC) The internal voltage regulator is capable of driving loads with up to 50 mA. It is able to supply the microcontroller and other ICs on the PCB and is protected against overloads by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used, with its base connected to the VCC pin and its emitter connected to PVCC. Voltage Regulator Sense Pin (PVCC) The PVCC is the sense input pin of the voltage regulator. For normal applications (i.e., when only using the internal output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor, i.e., its emitter terminal. Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN 2.1 specification are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN bus to VS are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the LIN protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state are slope controlled. 3.3.4 3.3.5 3.3.6 7 9111G–AUTO–05/10 3.3.7 Input/Output Pin (TXD) In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to ground in order to have a low LIN-bus. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8 mA. and is latched to low if the last wake-up event was from pin WAKE or KL_15. TXD Dominant Time-out Function The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in dominant state. If TXD is forced to low for longer than tDOM > 6 ms, the LIN-bus driver is switched to recessive state. To reactivate the LIN bus driver, switch TXD to high (> 10 µs). 3.3.8 3.3.9 Output Pin (RXD) The Output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5 kΩ to VCC. The AC characteristics can be defined with an external load capacitor of 20 pF. The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V). 3.3.10 Enable Input Pin (EN) The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with output capability. If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and the current consumption is reduced to IVS typ. 57 µA. The VCC regulator has its full functionality. If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the voltage regulator is switched off. 3.3.11 Wake Input Pin (WAKE) The Wake Input pin is a high-voltage input used to wake up the device from Sleep Mode or Silent Mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10 µA, is implemented. If a local wake-up is not needed for the application, connect the Wake pin directly to the VS pin. 3.3.12 Mode Input Pin (MODE) Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of the connected microcontroller, connect MODE pin and the watchdog is switched off. TM Input Pin The TM pin is used for final production measurements at Atmel. In normal application, it has to be always connected to GND. 3.3.13 8 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 3.3.14 KL_15 Pin The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It is an edge sensitive pin (low-to-high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on. Although KL_15 pin isat high voltage (VBatt), it is possible to switch the IC into Sleep or Silent Mode. Connect the KL_15 pin directly to GND if you do not need it. A debounce timer with a typical Tdb Kl_15 of 160 µs is implemented. The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin against voltage transients, a serial resistor of 47 kΩ and a ceramic capacitor of 100 nF are recommended. With this RC combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition Kl.15. You can also increase the wake-up time using external capacitors with higher values. 3.3.15 INH Output Pin The INH Output pin is used to switch an external voltage regulator on during Normal or Fail-safe Mode. The INH pin is switched off in Sleep or Silent Mode. It is possible to switch off the external 1 kΩ master resistor via the INH pin for master node applications. The INH pin is switched off during VCC undervoltage reset. Reset Output Pin (NRES) The Reset Output pin, an open drain output, switches to low during VCC undervoltage or a watchdog failure. WD_OSC Output Pin The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34 kΩ and 120 kΩ to adjust the watchdog oscillator time. NTRIG Input Pin The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger. Wake-up Events from Sleep or Silent Mode • LIN-bus • WAKE pin • EN pin • KL_15 3.3.16 3.3.17 3.3.18 3.3.19 9 9111G–AUTO–05/10 3.3.20 Modes of Operation Modes of Operation Unpowered Mode VBatt = 0V b a b b c+d+e a: VS > 5V b: VS < 4V c: Bus wake-up event d: Wake up from WAKE or KL_15 pin e: NRES switches to low Figure 3-2. Fail-safe Mode b e EN = 1 Go to silent command VCC: With undervoltage monitoring Communication: OFF Watchdog: ON EN = 1 c+d Silent Mode Local wake-up event EN = 0 TXD = 1 Normal Mode VCC: With undervoltage monitoring Communication: ON Watchdog: ON Go to sleep command EN = 1 VCC: With undervoltage monitoring Communication: OFF Watchdog: OFF EN = 0 TXD = 0 Sleep Mode VCC: switched off Communication: OFF Watchdog: OFF Table 3-1. Mode of Operation Fail-safe Normal Silent Sleep Table of Modes Transceiver Off On Off Off VCC 3.3V/5V 3.3V/5V 3.3V/5V 0V Watchdog WD_OSC INH On On Off Off 1.23V 1.23V 0V 0V On On Off Off RXD LIN High, Recessive except after wake-up LIN depending High 0V TXD depending Recessive Recessive 10 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 3.3.20.1 Normal Mode This is the normal transmitting and receiving mode at the LIN interface in accordance with the LIN specification LIN 2.1. The voltage regulator is active and can source up to 50 mA. The undervoltage detection is activated. The watchdog needs a trigger signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode. Silent Mode A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the Mode Select window (see Figure 3-3 on page 11). The transmission path is disabled in Silent Mode. The overall supply current from VBatt is a combination of the IVSsi 57 µA plus the VCC regulator output current IVCC. The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. The internal slave termination between the LIN pin and the VS pin is disabled in Silent Mode, only a weak pull-up current (typically 10 µA) between the LIN pin and the VS pin is present. Silent Mode can be activated independently from the actual level on the LIN, WAKE, or KL_15 pins. If an undervoltage condition occurs, NRES is switched to low, and the IC changes its state to Fail-safe Mode. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. Figure 3-3. Switch to Silent Mode Normal Mode Silent Mode 3.3.20.2 EN TXD Mode select window td = 3.2 µs NRES VCC Delay time silent mode td_sleep = maximum 20 µs LIN LIN switches directly to recessive mode 11 9111G–AUTO–05/10 A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (tbus) and the following rising edge at the LIN pin (see Figure 3-4 on page 12) result in a remote wake-up request. The device switches from Silent Mode to Fail-safe Mode. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 3-4 on page 12). EN high can be used to switch directly to Normal Mode. Figure 3-4. LIN Wake-up from Silent Mode Bus wake-up filtering time tbus Fail-safe mode Normal mode LIN bus Node in silent mode RXD High Low High TXD Watchdog Watchdog off Start watchdog lead time td VCC voltage regulator Silent mode 3.3V/5V/50 mA Fail safe mode 3.3V/5V/50 mA Normal mode EN High EN NRES Undervoltage detection active 3.3.20.3 Sleep Mode A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode Select window (Figure 3-5 on page 13). In order to avoid any influence to the LIN-pin during switching into sleep mode it is possible to switch the EN up to 3.2 µs earlier to LOW than the TXD. Therefore, the best and easiest way are two falling edges at TXD and EN at the same time.The transmission path is disabled in Sleep Mode. The supply current IVSsleep from VBatt is typically 10 µA. 12 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 The VCC regulator is switched off. NRES and RXD are low. The internal slave termination between the LIN pin and VS pin is disabled, only a weak pull-up current (typically 10 µA) between the LIN pin and the VS pin is present. Sleep Mode can be activated independently from the current level on the LIN, WAKE, or KL_15 pin. A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the internal slave termination between the LIN pin and the VS pin. A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (tbus) and a following rising edge at pin LIN results in a remote wake-up request. The device switches from Sleep Mode to Fail-safe Mode. The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see Figure 3-6 on page 14). EN high can be used to switch directly from Sleep/Silent to Fail-safe Mode. If EN is still high after VCC ramp up and undervoltage reset time, the IC switches to the Normal Mode. Figure 3-5. Switch to Sleep Mode Normal Mode Sleep Mode EN Mode select window TXD td = 3.2 µs NRES VCC Delay time sleep mode td_sleep = maximum 20 µs LIN LIN switches directly to recessive mode 3.3.20.4 Fail-safe Mode The device automatically switches to Fail-safe Mode at system power-up. The voltage regulator is switched on (VCC = 50 mA) (see Figure 3-7 on page 17). The NRES output switches to low for tres = 4 ms and gives a reset to the microcontroller. LIN communication is switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal Mode. A power down of VBatt (VS < 4V) during Silent or Sleep Mode switches the IC into Fail-safe Mode after power up. A low at NRES switches into Fail-safe Mode directly. During Fail-safe Mode the TXD pin is an output and signals the last wake-up source. 13 9111G–AUTO–05/10 3.3.20.5 Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see Figure 3-7 on page 17). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the VCC capacitor and the load. The NRES is low for the reset time delay treset . During this time, treset, no mode change is possible. Figure 3-6. LIN Wake-up from Sleep Mode Bus wake-up filtering time tbus Fail-safe Mode Normal Mode LIN bus RXD Low or floating Low TXD VCC voltage regulator On state Off state Regulator wake-up time EN High EN Reset time NRES Floating Microcontroller start-up time delay Watchdog Watchdog off Start watchdog lead time td 14 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 3.3.21 3.3.21.1 Wake-up Scenarios from Silent to Sleep Mode Remote Wake-up via Dominant Bus State A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver. A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (tBUS) and a rising edge at pin LIN result in a remote wake-up request. The device switches from Silent or Sleep Mode to Fail-safe Mode. The VCC voltage regulator is/remains activated, the INH pin is switched to high, and remote wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller. A low level at the LIN pin in the Normal Mode starts the bus wake-up filtering time, and if the IC is switched to Silent or Sleep Mode, it will receive a wake-up after a positive edge at the LIN pin. 3.3.21.2 Local Wake-up via Pin Wake A falling edge at the WAKE pin followed by a low level maintained for a certain time period (tWAKE) results in a local wake-up request. The device switches to Fail-safe Mode. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt in the microcontroller and a strong pull down at TXD. When the Wake pin is low, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to high > 10 µs before the negative edge at WAKE starts a new local wake-up request. Local Wake-up via Pin KL_15 A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15) results in a local wake-up request. The device switches into the Fail-safe Mode. The extra long wake-up time ensures that no transients at KL_15 create a wake up. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller and a strong pull down at TXD. During high-level voltage at pin KL_15, it is possible to switch to Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to low > 250 µs before the positive edge at KL_15 starts a new local wake-up request. With external RC combination, the time is even longer. Wake-up Source Recognition The device can distinguish between a local wake-up request (Wake or KL_15 pins) and a remote wake-up request (dominant LIN bus state). The wake-up source can be read on the TXD pin in Fail-safe Mode. A high level indicates a remote wake-up request (weak pull up at the TXD pin); a low level indicates a local wake-up request (strong pull down at the TXD pin). The wake-up request flag (signalled on the RXD pin), as well as the wake-up source flag (signalled on the TXD pin), is immediately reset if the microcontroller sets the EN pin to high (see Figure 3-3 on page 11 and Figure 3-4 on page 12) and the IC is in Normal Mode. The last wake-up source flag is stored and signalled in Fail-safe Mode at the TXD pin. 3.3.21.3 3.3.21.4 15 9111G–AUTO–05/10 3.3.22 Fail-safe Features • During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator works independently. • During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode. If the short-circuit disappears, the IC starts with a remote wake-up. • The reverse current is very low < 15 µA at the LIN pin during loss of VBatt or GND. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. • During a short circuit at VCC, the output limits the output current to IVCCn. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of the Fail-safe Mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can start with its normal operation. • EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. • RXD pin is set floating if VBatt is disconnected. • TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. • If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE after tdom > 20 ms. • If the WD_OSC pin has a short-circuit to GND or the resistor is disconnected, the watchdog runs with an internal oscillator and guarantees a reset after the second NTRIG signal at the latest. 3.3.23 Voltage Regulator The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. The main power dissipation of the IC is created from the VCC output current IVCC , which is needed for the application. 16 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 Figure 3-7. VCC Voltage Regulator: Ramp Up and Undervoltage Detection VS 12V 5.5V/3.8V t VCC 5V/3.3V Vthun TVCC NRES 5V/3.3V TReset Tres_f t t Figure 3-8. Power Dissipation: Safe Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures Due to Rthja = 35 K/W 60 Tamb = 105°C Tamb = 125°C 50 IVCC (mA) 40 30 20 10 0 3 5 7 9 11 13 15 17 19 VS (V) For programming purposes of the microcontroller it is potentially necessary to supply the VCC output via an external power supply while the VS Pin of the system basis chip is disconnected. This behavior is no problem for the system basis chip. For programming purposes of the microcontroller it is potentially neccessary to supply the VCC output via an external power supply while the VS Pin of the system basis chip is disconnected. This behavior is no problem for the system basis chip. 17 9111G–AUTO–05/10 3.3.24 Watchdog The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window of T w d . The trigger signal must exceed a minimum time ttrigmin > 200 ns. If a triggering signal is not received, a reset signal will be generated at output NRES. After a watchdog reset the IC starts with the lead time. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is adjustable via the external resistor Rwd_osc (34 kΩ to 120 kΩ). During Silent or Sleep Mode the watchdog is switched off to reduce current consumption. The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as lead time td. After wake up from Sleep or Silent Mode, the lead time td starts with the negative edge of the RXD output. 3.3.24.1 Typical Timing Sequence with RWD_OSC = 51 kΩ The trigger signal T wd i s adjustable between 20 ms and 64 ms using the external resistor RWD_OSC. For example, with an external resistor of RWD_OSC = 51 kΩ ±1%, the typical parameters of the watchdog are as follows: tosc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)2 (RWD_OSC in kΩ; tosc in µs) tOSC = 19.6 µs due to 51 kΩ td = 7895 × 19.6 µs = 155 ms t1 = 1053 × 19.6 µs = 20.6 ms t2 = 1105 × 19.6 µs = 21.6 ms tnres = constant = 4 ms After ramping up the battery voltage, the 3.3V/5V regulator is switched on. The reset output NRES stays low for the time treset (typically 4 ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead time, td, follows the reset and is td = 155 ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a watchdog reset with tNRES = 4 ms will reset the microcontroller after td = 155 ms. The times t1 and t2 have a fixed relationship between each other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6 ms. To avoid false triggering from glitches, the trigger pulse must be longer than tTRIG,min > 200 ns. This slope serves to restart the watchdog sequence. If the triggering signal fails in this open window t2, the NRES output will be drawn to ground. A triggering signal during the closed window t1 immediately switches NRES to low. 18 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 Figure 3-9. Timing Sequence with RWD_OSC = 51 kΩ VCC Undervoltage Reset NRES treset = 4 ms Watchdog Reset tnres = 4 ms td = 155 ms t1 = 20.6 ms twd t2 = 21 ms t1 t2 NTRIG ttrig > 200 ns 3.3.24.2 Worst Case Calculation with RWO_OSC = 51 kΩ The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%. The worst case calculation for the watchdog period twd is calculated as follows. The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2. t1,min = 0.8 × t1 = 16.5 ms, t1,max = 1.2 × t1 = 24.8 ms t2,min = 0.8 × t2 = 17.3 ms, t2,max = 1.2 × t2 = 26 ms twdmax = t1min + t2min = 16.5 ms + 17.3 ms = 33.8 ms twdmin = t1max = 24.8 ms twd = 29.3 ms ±4.5 ms (±15%) A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs correctly. Table 3-2. RWD_OSC kΩ 34 51 91 120 Typical Watchdog Timings Oscillator Period tosc/µs 13.3 19.61 33.54 42.84 Lead Time td/ms 105 154.8 264.80 338.22 Closed Window t1/ms 14.0 20.64 35.32 45.11 Open Window t2/ms 14.7 21.67 37.06 47.34 Trigger Period from Microcontroller Reset Time twd/ms tnres/ms 19.9 29.32 50.14 64.05 4 4 4 4 19 9111G–AUTO–05/10 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage VS Pulse time ≤ 500 ms; Ta = 25°C Output current IVCC ≤ 50 mA Pulse time ≤ 2 min; Ta = 25°C Output current IVCC ≤ 50 mA WAKE (with 33 kΩ serial resistor) KL_15 (with 50 kΩ/100 nF) DC voltage Transient voltage due to ISO7637 (coupling 1 nF) INH - DC voltage LIN - DC voltage Logic pins (RxD, TxD, EN, NRES, NTRIG, WD_OSC, MODE, TM) Output current NRES PVCC DC voltage VCC DC voltage ESD according to IBEE LIN EMC Test Spec. 1.0 following IEC 61000-4-2 - Pin VS, LIN to GND - Pin WAKE (33 kΩ serial resistor) to GND ESD HBM following STM5.1 with 1.5 kΩ 100 pF - Pin VS, LIN, WAKE to GND HBM ESD ANSI/ESD-STM5.1 JESD22-A114 AEC-Q100 (002) CDM ESD STM 5.3.1 Machine Model ESD AEC-Q100-RevF(003) Junction temperature Storage temperature Tj Ts INRES –0.3 –0.3 Symbol VS VS VS –1 –150 Min. –0.3 Typ. Max. +40 +40 27 Unit V V V +40 +100 V V –0.3 –27 –0.3 VS + 0.3 +40 +5.5 +2 +5.5 +6.5 V V V mA V V ±6 ±5 ±8 KV KV KV ±3 KV ±750 ±200 –40 –55 +150 +150 V V °C °C 5. Thermal Characteristics Parameters Thermal resistance junction to heat slug Thermal resistance junction to ambient, where heat slug is soldered to PCB Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Symbol Rthjc Rthja 150 150 35 165 165 10 170 170 Min. Typ. Max. 10 Unit K/W K/W °C °C °C 20 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 6. Electrical Characteristics 5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. 1 1.1 Parameters VS Pin Nominal DC voltage range Sleep Mode VLIN > VS – 0.5V VS < 14V (Tj = 25°C) Sleep Mode VLIN > VS – 0.5V VS < 14V (Tj = 125°C) Bus recessive VS < 14V (Tj = 25°C) Without load at VCC Bus recessive VS < 14V (Tj = 125°C) Without load at VCC VS VS IVSsleep 5 27 V A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* VS 3 10 14 µA A 1.2 Supply current in Sleep Mode VS IVSsleep 5 11 16 µA A VS IVSsi 47 57 67 µA A 1.3 Supply current in Silent Mode VS IVSsi 56 66 76 µA A 1.4 Bus recessive Supply current in Normal VS < 14V Mode Without load at VCC Bus dominant Supply current in Normal VS < 14V Mode VCC load current 50 mA Supply current in Fail-safe Mode VS undervoltage threshold VS undervoltage threshold hysteresis RXD Output Pin Low-level output sink current Normal Mode VLIN = 0V VRXD = 0.4V Bus recessive VS < 14V Without load at VCC VS IVSrec 0.3 0.8 mA A 1.5 VS IVSdom 50 53 mA A 1.6 VS IVSfail VSth VSth_hys 250 550 µA A 1.7 1.8 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 VS VS 4.0 4.5 0.2 5 V V A A RXD RXD RXD TXD TXD IRXD VRXDL RRXD VTXDL VTXDH RTXD ITXD 1.3 2.5 8 0.4 mA V kΩ V V kΩ µA A A A A A A A Low-level output voltage IRXD = 1 mA Internal resistor to VCC TXD Input/Output Pin Low-level voltage input High-level voltage input Pull-up resistor High-level leakage current VTXD = 0V VTXD = VCC 3 –0.3 2 125 –3 5 7 +0.8 VCC + 0.3V TXD TXD 250 400 +3 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 21 9111G–AUTO–05/10 6. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Fail-safe Mode Low-level output sink VLIN = VS current at local wake-up VWAKE = 0V request VTXD = 0.4V EN Input Pin Low-level voltage input High-level voltage input Pull-down resistor Low-level input current Low-level voltage input High-level voltage input Pull-up resistor High-level leakage current Mode Input Pin Low-level voltage input High-level voltage input High-level leakage current INH Output Pin High-level voltage Switch-on resistance between VS and INH Leakage current Sleep Mode VINH = 0V/27V, VS = 27V IINH = –15 mA INH INH INH VINHH RINH IINHL –3 VS – 0.8 30 VS 50 +3 V Ω µA A A A VMODE = VCC or VMODE = 0V MODE MODE MODE VMODEL VMODEH IMODE –0.3 2 –3 +0.8 VCC + 0.3V +3 V V µA A A A VNTRIG = 0V VNTRIG = VCC VEN = VCC VEN = 0V EN EN EN EN NTRIG NTRIG NTRIG NTRIG VENL VENH REN IEN VNTRIGL VNTRIGH RNTRIG INTRIG –0.3 2 50 –3 –0.3 2 125 –3 250 125 +0.8 VCC + 0.3V 200 +3 +0.8 VCC + 0.3V 400 +3 V V kΩ µA V V kΩ µA A A A A A A A A 3.5 TXD ITXDwake 2 2.5 8 mA A 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 6 6.1 6.2 6.3 7 7.1 7.2 7.3 NTRIG Watchdog Input Pin 8 LIN Bus Driver: Bus Load Conditions: Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; Internal Pull-up RRXD = 5 kΩ; CRXD = 20 pF Load 3 (Medium): 6.8 nF, 660Ω, Characterized on Samples 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 kBit/s and 10.8 and 10.9 at 10.4 kBit/s Driver recessive output voltage Driver dominant voltage Driver dominant voltage Driver dominant voltage Driver dominant voltage Load1/Load2 VVS = 7V Rload = 500 Ω VVS = 18V Rload = 500 Ω VVS = 7.0V Rload = 1000 Ω VVS = 18V Rload = 1000 Ω LIN LIN LIN LIN LIN VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k 0.6 0.8 0.9 × VS VS 1.2 2 V V V V V A A A A A 8.1 8.2 8.3 8.4 8.5 *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 22 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 6. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. 8.6 8.7 8.8 Parameters Pull-up resistor to VS Test Conditions The serial diode is mandatory Pin LIN LIN LIN Input leakage current Driver off VBUS = 0V VBatt = 12V Driver off 8V < VBatt < 18V 8V < VBUS < 18V VBUS VBatt Symbol RLIN VSerDiode IBUS_LIM Min. 20 0.4 40 120 Typ. 30 Max. 60 1.0 200 Unit kΩ V mA Type* A D A Voltage drop at the serial In pull-up path with Rslave diodes ISerDiode = 10 mA LIN current limitation VBUS = VBatt_max Input leakage current at the receiver including pull-up resistor as specified Leakage current LIN recessive 8.9 LIN IBUS_PAS_dom –1 –0.35 mA A 8.10 LIN IBUS_PAS_rec 10 20 µA A 8.11 Leakage current when control unit disconnected from ground. GNDDevice = VS VBatt = 12V Loss of local ground 0V < VBUS < 18V must not affect communication in the residual network. Leakage current at a disconnected battery. Node has to sustain the VBatt disconnected current that can flow VSUP_Device = GND under this condition. Bus 0V < VBUS < 18V must remain operational under this condition. LIN Bus Receiver Center of receiver threshold VBUS_CNT = (Vth_dom + Vth_rec)/2 LIN IBUS_NO_gnd –10 +0.5 +10 µA A 8.12 LIN IBUS_NO_bat 0.1 2 µA A 9 9.1 9.2 9.3 9.4 9.5 9.6 10 10.1 LIN LIN LIN LIN LIN LIN VBUS_CNT VBUSdom VBUSrec VBUShys VLINH VLINL 0.475 × VS 0.6 × VS 0.028 × VS VS – 2V –27 0.5 × VS 0.525 × VS 0.4 × VS 0.175 × VS VS + 0.3V VS – 3.3V V V V A A A A A A Receiver dominant state VEN = 5V Receiver recessive state VEN = 5V Receiver input hysteresis Pre_Wake detection LIN High-level input voltage Pre_Wake detection LIN Activates the LIN receiver Low-level input voltage Internal Timers Dominant time for wake-up via LIN bus Time delay for mode change from Fail-safe into Normal Mode via EN pin VLIN = 0V Vhys = Vth_rec – Vth_dom 0.1 × VS V V V LIN tbus 30 90 150 µs A 10.2 VEN = 5V EN tnorm 5 15 20 µs A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 23 9111G–AUTO–05/10 6. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Time delay for mode change from Normal V = 0V Mode to Sleep Mode via EN EN pin TXD dominant time-out time VTXD = 0V 10.3 EN tsleep 2 7 12 µs A 10.4 TXD tdom 6 13 20 ms A 10.5 Time delay for mode change from Silent V = 5V Mode into Normal Mode EN via EN THRec(max) = 0.744 × VS THDom(max) = 0.581 × VS VS = 7.0V to 18V tBit = 50 µs D1 = tbus_rec(min)/(2 × tBit) THRec(min) = 0.422 × VS THDom(min) = 0.284 × VS VS = 7.6V to 18V tBit = 50 µs D2 = tbus_rec(max)/(2 × tBit) THRec(max) = 0.778 × VS THDom(max) = 0.616 × VS VS = 7.0V to 18V tBit = 96 µs D3 = tbus_rec(min)/(2 × tBit) THRec(min) = 0.389 × VS THDom(min) = 0.251 × VS VS = 7.6V to 18V tBit = 96 µs D4 = tbus_rec(max)/(2 × tBit) VS = 7.0V to 18V EN ts_n 5 15 40 µs A 10.6 Duty cycle 1 LIN D1 0.396 A 10.7 Duty cycle 2 LIN D2 0.581 A 10.8 Duty cycle 3 LIN D3 0.417 A 10.9 Duty cycle 4 LIN D4 0.590 A 10.10 11 Slope time falling and rising edge at LIN LIN tSLOPE_fall tSLOPE_rise 3.5 22.5 µs A Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions (CRXD): 20 pF Propagation delay of receiver (Figure 6-1 on page 27) VS = 7.0V to 18V trx_pd = max(trx_pdr, trx_pdf) RXD trx_pd 6 µs A 11.1 11.2 12 12.1 Symmetry of receiver VS = 7.0V to 18V propagation delay rising =t –t t edge minus falling edge rx_sym rx_pdr rx_pdf NRES Open Drain Output Pin VS ≥ 5.5V Low-level output voltage INRES = 1 mA INRES = 250 µA Low-level output low Undervoltage reset time 10 kΩ to VCC VCC = 0V VS ≥ 5.5V CNRES = 20 pF RXD trx_sym –2 +2 µs A NRES VNRESL VNRESLL treset 2 4 0.2 0.14 0.2 6 V V V ms A 12.2 12.3 NRES NRES A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 24 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 6. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. 12.4 13 13.1 13.2 13.3 13.4 13.5 13.6 14 14.1 14.2 14.3 14.4 15 15.1 15.2 15.3 15.4 15.5 16 16.1 16.2 16.3 16.4 16.5 Parameters Test Conditions Pin NRES Symbol tres_f Min. 1.5 Typ. Max. 10 Unit µs Type* A Reset debounce time for VS ≥ 5.5V falling edge CNRES = 20 pF Watchdog Oscillator Voltage at WD_OSC in Normal Mode Possible values of resistor Oscillator period Oscillator period Oscillator period Oscillator period Watchdog lead time after Reset Watchdog closed window Watchdog open window Watchdog reset time NRES KL_15 Pin High-level input voltage RV = 47 kΩ Low-level input voltage RV = 47 kΩ KL_15 pull-down current Internal debounce time KL_15 wake-up time WAKE Pin High-level input voltage Low-level input voltage WAKE pull-up current High-level leakage current Time of low pulse for wake-up via WAKE pin Initializes a wake-up signal VS < 27V VWAKE = 0V VS = 27V VWAKE = 27V VWAKE = 0V WAKE WAKE WAKE WAKE WAKE VWAKEH VWAKEL IWAKE IWAKEL IWAKEL VS – 1V –1 –30 –5 30 70 –10 +5 150 VS + 0.3V VS – 3.3V V V µA µA µs A A A A A VS < 27V VKL_15 = 27V Without external capacitor RV = 47 kΩ, C = 100 nF Positive edge initializes a wake-up KL_15 KL_15 KL_15 KL_15 KL_15 VKL_15H VKL_15L IKL_15 TdbKL_15 TwKL_15 80 0.4 4 –1 50 160 2 VS + 0.3V +2 65 250 4.5 V V µA µs ms A A A A C NRES ROSC = 34 kΩ ROSC = 51 kΩ ROSC = 91 kΩ ROSC = 120 kΩ IWD_OSC = –200 µA VVS 4V WD_ OSC WD_ OSC VWD_OSC ROSC tOSC tOSC tOSC tOSC 1.13 34 10.65 15.68 26.83 34.2 13.3 19.6 33.5 42.8 1.23 1.33 120 15.97 23.52 40.24 51.4 V kΩ µs µs µs µs A A A A A A Watchdog Timing Relative to tOSC td t1 t2 tnres 3.2 7895 1053 1105 4 4.8 cycles cycles cycles ms A A A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 25 9111G–AUTO–05/10 6. Electrical Characteristics (Continued) 5V < VS < 27V, –40°C < Tcase < 125°C, –40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins No. 18 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 Parameters VCC Voltage Regulator Output voltage VCC Output voltage VCC at low VS Regulator drop voltage Regulator drop voltage Regulator drop voltage Line regulation Load regulation Power supply ripple rejection 5.5V < VS < 18V (0 mA to 50 mA) 4V < VS < 5.5V VS > 4V IVCC = –20 mA VS > 4V IVCC = –50 mA VS > 3.3V IVCC = –15 mA 5.5V < VS < 18V 5 mA < IVCC < 50 mA 10 Hz to 100 kHz CVCC = 10 µF VS = 14V, IVCC = –15 mA 0.2Ω < ESR < 5Ω at 100 kHz Referred to VCC VS > 5.5V Referred to VCC VS > 5.5V VCC VCC VS, VCC VS, VCC VS, VCC VCC VCC VCC VCC VCC VCC VCC VCC IVCClim VthunN VthunN Vhysthun tVCC VCCnor VCClow VD1 VD2 VD3 VCCline VCCload 50 –240 1.8 4.2 250 130 300 –130 10 4.8 0.5 400 4.9 VS – VD 5.1 5.1 250 600 200 1 2 V V mV mV mV % % dB mA µF V mV µs A A A A A A A A A D A A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* Output current limitation VS > 5.5V 18.10 Load capacity 18.11 18.12 18.13 VCC undervoltage threshold Hysteresis of undervoltage threshold Ramp-up time VS > 5.5V CVCC = 2.2 µF to VCC = 5V Iload = –5 mA at VCC *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 26 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 Figure 6-1. Definition of Bus Timing Parameters tBit TXD (Input to transmitting node) tBit tBit tBus_dom(max) tBus_rec(min) THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min) Thresholds of receiving node1 Thresholds of receiving node2 tBus_dom(min) tBus_rec(max) RXD (Output of receiving node1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving node2) trx_pdr(2) trx_pdf(2) 27 9111G–AUTO–05/10 7. Microcontroller Block 7.1 Features • High Performance, Low Power Atmel AVR 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions - Most Single Clock Cycle Execution – 32 × 8 General Purpose Working Register – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier Non-volatile Program and Data Memories – 8/16 Kbytes of In-System Self-programmable Flash (ATA6612/ATA6613) Endurance: 75,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation – 512 Bytes EEPROM Endurance: 100,000 Write/Erase Cycles – 1 Kbyte Internal SRAM – Programming Lock for Software Security Peripheral Features – Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Byte-oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change Special Microcontroller Features – Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and Standby I/O – 23 Programmable I/O Lines Operating Voltage – 2.7V to 5.5V Speed Grade – 0 to 8 MHz at 2.7V to 5.5V, 0 to 16 MHz at 4.5V to 5.5V Low Power Consumption – Active Mode: • 4 MHz, 3.0V: 1.8 mA – Power-down Mode: • 5 µA at 3.0V • • • • • • • 28 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 7.2 Overview The ATA6612/ATA6613 uses a low-power CMOS 8-bit microcontroller based on the Atmel AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATA6612/ATA6613 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. 7.2.1 Block Diagram Block Diagram GND VCC Figure 7-1. Watchdog Timer Power Supervision POR / BOD and Reset debugWIRE Watchdog Oscillator Program Logic Flash Oscillator Circuits / Clock Generation SRAM AVR CPU EEPROM AVCC AREF GND 8 bit T/C 0 16 bit T/C 1 A/D Converter 2 DATABUS 8 bit T/C 2 Analog Compensation Internal Bandgap 6 USART 0 SPI TWI Port D (8) Port B (8) Port C (7) RESET XTAL[1..2] PD[0..7] PB[0..7] PC[0..6] ADC[6..7] 29 9111G–AUTO–05/10 The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The ATA6612/ATA6613 provides the following features: 8K/16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1 Kbyte SRAM, 23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN packages), a programmable Watchdog Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the Atmel AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATA6612/ATA6613 uses a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATA6612/ATA6613 Atmel AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulator, and Evaluation kits. 7.2.2 Automotive Quality Grade The ATA6612 and ATA6613 have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949 grade 1. This data sheet contains limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the ATA6612 and ATA6613 have been verified during regular product qualification as per AEC-Q100. 30 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 7.2.3 Comparison Between ATA6612/ATA6613 The ATA6612 and ATA6613 differ only in memory sizes, boot loader support, and interrupt vector sizes. Table 7-1 summarizes the different memory and interrupt vector sizes for the two devices. Table 7-1. Device ATA6612 ATA6613 Memory Size Summary Flash 8 Kbytes 16 Kbytes EEPROM 512 Bytes 512 Bytes RAM 1 Kbyte 1 Kbyte Interrupt Vector Size 1 instruction word/vector 2 instruction words/vector ATA6612 and ATA6613 support a real Read-While-Write Self-Programming mechanism. There is a separate Boot Loader Section, and the SPM instruction can only execute from there. 7.2.4 7.2.4.1 Pin Descriptions VCC Digital supply voltage. 7.2.4.2 GND Ground. 7.2.4.3 Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2 Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running. Depending on the clock selection fuse settings, PB6 can be used as input to the inverting oscillator amplifier. Depending on the clock selection fuse settings, PB7 can be used as input to the inverting oscillator amplifier. If the internal calibrated RC oscillator is used as chip clock source, PB7..6 is used as TOSC2..1 input for the asynchronous Timer/Counter2 if the AS2 bit in ASSR is set. The various special features of Port B are elaborated in “Alternate Functions of Port B” on page 97 and “System Clock and Clock Options” on page 51. 31 9111G–AUTO–05/10 7.2.4.4 Port C (PC5:0) Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5..0 output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running. PC6/RESET If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in Table 7-3 on page 47. Shorter pulses are not guaranteed to generate a Reset. The various special features of Port C are elaborated in “Alternate Functions of Port C” on page 101. 7.2.4.5 7.2.4.6 Port D (PD7:0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. The various special features of Port D are elaborated in “Alternate Functions of Port D” on page 104. 7.2.4.7 AVCC AVCC is the supply voltage pin for the A/D converter, PC3:0, and ADC7:6. I should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through a low-pass filter. Note that PC6..4 use digital supply voltage, VCC. 7.2.4.8 AREF AREF is the analog reference pin for the A/D converter. 7.2.4.9 ADC7:6 (TQFP and QFN Package Only) In the TQFP and QFN package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered from the analog supply and serve as 10-bit ADC channels. 32 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 7.3 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header file and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details. 7.4 7.4.1 AVR CPU Core Introduction This section discusses the Atmel AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 7.4.2 Architectural Overview Block Diagram of the Atmel AVR Architecture Data Bus 8-bit Figure 7-2. Flash program memory Program counter Status and control Instruction register 32 × 8 general purpose registers Interrupt unit SPI unit Instruction decoder Watchdog timer Indirect addressing Direct addressing Control lines ALU Analog comparator I/O Module 1 DATA SRAM I/O Module 2 I/O Module n EEPROM I/O lines 33 9111G–AUTO–05/10 In order to maximize performance and parallelism, the Atmel AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory. The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section. The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation. Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section. During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATA6612/ATA6613 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. 34 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 7.4.3 ALU – Arithmetic Logic Unit The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description. Status Register The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software. The AVR Status Register – SREG – is defined as: 7.4.4 Bit Read/Write Initial Value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG • Bit 7 – I: Global Interrupt Enable The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference. • Bit 6 – T: Bit Copy Storage The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction. • Bit 5 – H: Half Carry Flag The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information. • Bit 4 – S: Sign Bit, S = N ⊕V The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information. 35 9111G–AUTO–05/10 • Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 7.4.5 General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output operand and one 8-bit result input • Two 8-bit output operands and one 8-bit result input • Two 8-bit output operands and one 16-bit result input • One 16-bit output operand and one 16-bit result input Figure 7-3 shows the structure of the 32 general purpose working registers in the CPU. Figure 7-3. AVR CPU General Purpose Working Registers 7 R0 R1 R2 ... R13 R14 General Purpose Working Registers R15 R16 R17 ... R26 R27 R28 R29 R30 R31 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F X-register Low Byte X-register High Byte Y-register Low Byte Y-register High Byte Z-register Low Byte Z-register High Byte 0x0D 0x0E 0x0F 0x10 0x11 0 Address 0x00 0x01 0x02 36 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions. As shown in Figure 7-3 on page 36, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file. 7.4.5.1 The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 7-4. Figure 7-4. The X-, Y-, and Z-registers 15 X-register 7 R27 (0x1B) XH 0 XL 7 R26 (0x1A) 0 0 15 Y-register 7 R29 (0x1D) 15 Z-register 7 R31 (0x1F) YH 0 YL 7 R28 (0x1C) 0 0 ZH 0 ZL 7 R30 (0x1E) 0 0 In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 7.4.6 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer. The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100, preferably RAMEND. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI. 37 9111G–AUTO–05/10 The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present. Bit 15 SP15 SP7 7 Read/Write R/W R/W Initial Value 14 SP14 SP6 6 R/W R/W 13 SP13 SP5 5 R/W R/W 12 SP12 SP4 4 R/W R/W 11 SP11 SP3 3 R/W R/W 10 SP10 SP2 2 R/W R/W 9 SP9 SP1 1 R/W R/W 8 SP8 SP0 0 R/W R/W SPH SPL RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND 7.4.7 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used. Figure 7-5 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. Figure 7-5. The Parallel Instruction Fetches and Instruction Executions T1 T2 T3 T4 clkCPU 1st Instruction Fetch 1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch Figure 7-6 on page 39 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register. 38 ATA6612/ATA6613 9111G–AUTO–05/10 ATA6612/ATA6613 Figure 7-6. Single Cycle ALU Operation T1 T2 T3 T4 clkCPU Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back 7.4.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See section “Memory Programming” on page 300 for details. The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 79. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 79 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse (see “Boot Loader Support – Read-While-Write Self-Programming, ATA6612 and ATA6613” on page 284). When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed. There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority. The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered. When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. 39 9111G–AUTO–05/10 Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software. When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 ; restore SREG value (I-bit) ; store SREG value ; start EEPROM write ; disable interrupts during timed sequence C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1