ATA6620N_09

Features • • • • • Supply Voltage up to 40V Operating Voltage VS = 5V to 18V Typically 10 µA Supply Current During Sleep Mode Typically 40 µA Supply Current in Silent Mode Linear Low-drop Voltage Regulator: – Normal Mode: VCC = 5V ±2%/50 mA – Silent Mode: VCC = 5V ±7%/50 mA – Sleep Mode: VCC is Switched Off VCC Undervoltage Detection with Reset Output NRES (10 ms Reset Time) Voltage Regulator is Short-circuit and Over-temperature Protected LIN Physical Layer According to LIN Specification Revision 2.0 Wake-up Capability via LIN Bus (90 µs Dominant) TXD Time-out Timer (9 ms) 60V Load-dump Protection at LIN Pin Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery High EMC Level 5V CMOS-compatible I/O Pins to MCU ESD HBM 6 kV at Pins LIN and VS Interference and Damage Protection According to ISO/CD7637 Package: SO8 • • • • • • • • • • • • LIN Bus Transceiver with Integrated Voltage Regulator ATA6620N 1. Description ATA6620N is a fully integrated LIN transceiver, designed according to the LIN specification 2.0, with a low-drop voltage regulator (5V/50 mA). The combination of voltage regulator and bus transceiver makes it possible to develop simple, but powerful, slave nodes in LIN Bus systems. ATA6620N is designed to handle the low-speed data communication in vehicles (for example, in convenience electronics). Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud with an RC oscillator for the protocol handling. The bus output is designed to withstand high voltage. Sleep mode (voltage regulator switched off) and Silent mode (communication off; VCC voltage on) guarantee minimized current consumption. 4850I–AUTO–09/09 Figure 1-1. Block Diagram VCC ATA6620N Receiver Normal and Pre-normal Mode 1 VS RXD 5 4 Filter LIN VCC Wake-up Bus Timer TXD 6 TXD Time-out Timer Slew Rate Control Short Circuit and Overtemperature Protection 8 Sleep Mode VCC Undervoltage Reset Switched Silent Mode Off Voltage Regulator 5V/50 mA/7% Normal Mode Voltage Regulator 5V/50 mA/2% VCC EN 2 Control Unit 7 NRES GND 3 2. Pin Configuration Figure 2-1. Pinning SO8 VS EN GND LIN 1 2 3 4 8 7 6 5 VCC NRES TXD RXD Table 2-1. Pin 1 2 3 4 5 6 7 8 Pin Description Symbol VS EN GND LIN RXD TXD NRES VCC Function Battery supply Enables Normal mode if the input is high Ground LIN bus line input/output Receive data output Transmit data input, active low output Output undervoltage reset, low at reset Output voltage regulator 5V/50 mA 2 ATA6620N 4850I–AUTO–09/09 ATA6620N 3. Functional Description 3.1 Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions. 3.2 Supply Pin (VS) LIN operating voltage is VS = 5V to 18V. After switching on VS, the IC starts with the Pre-normal mode and the voltage regulator is switched on (that is, 5V/50 mA output capability). The supply current in Sleep mode is typically 10 µA and 40 µA in Silent mode. 3.3 Ground Pin (GND) The IC is neutral on the LIN pin in case of GND disconnection. It is able to handle a ground shift up to 3V for supply voltage above 9V at the VS pin. 3.4 Voltage Regulator Output Pin (VCC) The internal 5V voltage regulator is capable of driving loads with up to 50 mA, supplying the microcontroller and other ICs on the PCB. It is protected against overload by means of current limitation and overtemperature shut-down. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun. 3.5 Undervoltage Reset Output (NRES) This push-pull output is supplied from the VCC voltage. If the VCC voltage falls below the undervoltage detection threshold of Vthun, NRES switches to low after tres_f (see Figure 4-7 on page 11) except the IC is switched into Sleep mode. Even if VCC = 0V the NRES stays low, because it is internally driven from the V S v oltage. If V S v oltage ramps down, NRES stays low until VS < 1.5V and then becomes highly resistive. The implemented undervoltage delay keeps NRES low for tReset = 10 ms after VCC reaches its nominal value. 3.6 Bus Pin (LIN) A low-side driver with internal current limitation and thermal shutdown, as well as an internal pull-up resistor according to LIN specification 2.0 is implemented. The voltage range is from –40V to +60V. This pin exhibits no reverse current from the LIN bus to VS, even in the case of a GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN protocol specification. The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are slope controlled. The output has a short-circuit limitation. This is a self-adapting current limitation; that is, during current limitation, as the chip temperature increases, the current decreases. 3 4850I–AUTO–09/09 3.7 Input/Output Pin (TXD) This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive state. 3.8 Dominant Time-out Function (TXD) The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than tDOM > 4 ms, the LIN bus driver is switched to the recessive state. To reset this dominant time-out mode, TXD must be switched to high (> 10 µs) before normal data transmission can be started. 3.9 Output Pin (RXD) This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up structure with typically 5 kΩ to VCC. The AC characteristics are measured with an external load capacitor of 20 pF. The output is short-circuit protected. In unpowered mode (that is, VS = 0V), RXD is switched off. 3.10 Enable Input Pin (EN) This pin controls the operation mode of the interface. After power up of V S (battery), the IC switches to Pre-normal mode, even if EN is low or unconnected (internal pull-down resistor). If EN is high, the interface is in Normal mode. A falling edge at EN while TXD is still high forces the device to Silent mode. A falling edge at EN while TXD is low forces the device to Sleep mode. 4 ATA6620N 4850I–AUTO–09/09 ATA6620N 4. Mode of Operation Figure 4-1. Mode of Operation Unpowered Mode VBatt = 0 a: VS > 5V b: VS < 4V c: Bus wake-up event d: NRES switches to low b a Pre-normal Mode b d EN = 1 Go to silent command EN = 0 TXD = 1 Normal Mode EN = 1 VCC: 5V/2%/50 mA with undervoltage monitoring Communication: ON Go to sleep command Local wake-up event VCC: 5V/2%/50 mA with undervoltage monitoring Communication: OFF b c+d c b Silent Mode VCC: 5V/7%/50 mA with undervoltage monitoring Communication: OFF EN = 0 TXD = 0 Local wake-up event EN = 1 Sleep Mode VCC: switched off Communication: OFF Table 4-1. Mode of Operation Mode of Operation Communication OFF ON OFF OFF VCC 5V 5V 5V 0V RXD 5V 5V 5V 0V LIN Recessive Recessive Recessive Recessive Pre-normal Normal Silent Sleep 4.1 Normal Mode This is the normal transmitting and receiving mode of the LIN Interface, in accordance with LIN specification 2.0. The VCC voltage regulator operates with a 5V output voltage, with a low tolerance of ±2% and a maximum output current of 50 mA. If an undervoltage condition occurs, NRES is switched to low and the ATA6620N changes state to Pre-normal mode. All features are available. 5 4850I–AUTO–09/09 4.2 4.2.1 Modes of Reduced Current Consumption Silent Mode A falling edge at EN while TXD is high switches the IC into Silent mode. The TXD Signal has to be logic high during the Mode Select window (see Figure 4-2 on page 6). For EN and TXD either two independent outputs can be used, or two outputs from the same microcontroller port; in the second case, the mode change is only one command. In Silent mode the transmission path is disabled. Supply current from V Batt i s typically IVSsi = 40 µA with no load at the VCC regulator. The overall supply current from VBatt is the result of 40 µA plus the VCC regulator output current IVCCs. The 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source up to 50 mA. In Silent mode the internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. The Silent mode voltage is sufficient to run an external microcontroller on the ECU, for example in Power Down mode. The undervoltage reset is VCCthS < 4.4V. If an undervoltage condition occurs, NRES is switched to low and the ATA6620N changes state to Pre-normal mode. A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period (tbus) results in a remote wake-up request. The device switches from Silent mode to Pre-normal mode, then the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller and a high level at pin TXD (see Figure 4-3 on page 7). With EN high, ATA6620N switches directly from Silent- via Pre-normal to Normal mode. Figure 4-2. Switch to Silent Mode Normal Mode Silent Mode EN TXD Mode select window td = 3.2 µs NRES VCC LIN Delay time silent mode td_sleep = maximum 20 µs LIN switches directly to recessive mode 6 ATA6620N 4850I–AUTO–09/09 ATA6620N Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode Pre-normal Mode Normal Mode LIN Bus VLIN < 0.4 VS TXD High RXD High Bus wake-up filtering time tbus Low VCC Silent mode Pre-normal mode Normal mode Regulator Wake-up Time EN Node ln silent mode EN High NRES If undervoltage switch to pre-normal mode Undervoltage detection active 7 4850I–AUTO–09/09 4.2.2 Sleep Mode A falling edge at EN while TXD is low switches the IC into Sleep mode. The TXD Signal has to be logic low during the Mode Select window (see Figure 4-4). We recommend using the same microcontroller port for EN as for TXD; in this case the mode change is only one command. In Sleep mode the transmission path is disabled. Supply current from V Batt i s typically IVSsleep = 10 µA. The VCC regulator is switched off; NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is short-circuited to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period (tbus) results in a remote wake-up request. The device switches from Sleep mode to Pre-normal mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller and a high level at pin TXD (see Figure 4-5 on page 9). With EN high you can switch directly from Silent to Normal mode. In the application where the ATA6620N supplies the microcontroller, the wake-up from Sleep mode is only possible via pin LIN. If the device is switched into Sleep mode, VCC ramps down without generating an undervoltage reset at pin NRES. Figure 4-4. Switch to Sleep Mode Normal Mode Sleep Mode EN Mode select window TXD td = 3.2 µs NRES VCC LIN Delay time sleep mode td_sleep = maximum 20 µs LIN switches directly to recessive mode 8 ATA6620N 4850I–AUTO–09/09 ATA6620N Figure 4-5. LIN Wake-up Diagram from Sleep Mode Pre-normal Mode Normal Mode LIN Bus VLIN < 0.4 VS TXD RXD Low or floating Bus wake-up filtering time tbus Low VCC On state Off state Regulator wake-up time EN High EN Node in sleep mode Reset time NRES Low or floating Microcontroller start-up time delay 4.2.3 Wake Up from Sleep/Silent Mode at an Insufficient Falling Edge at Pin LIN If the ATA6620N is in Sleep mode or Silent mode and the voltage at the LIN Bus falls to a value lower than VLINL < VS – 3.3V (see “Electrical Characteristics” numbers 9.5 and 9.6) but higher than 0.6 × VS, then a wake up is detected and the circuit switches to pre-normal mode and the internal NMOS- transistor connected to the pin TXD is switched on and pulls down the pin TXD to Ground. The following figure shows the corresponding diagram for the wake-up from silent mode. The wake-up process from Sleep mode works analogue to this. 9 4850I–AUTO–09/09 Figure 4-6. Wake Up from Silent Mode at an Insufficient Falling Edge at Pin LIN Pre-normal Mode Normal Mode LIN Bus VLIN < VS - 1V and VLIN > 0.6 VS TXD High Low RXD High Wake-up filtering time t WAKE Low VCC Silent mode Pre-normal mode Normal mode Regulator Wake-up Time EN Node ln silent mode EN High NRES If undervoltage switch to pre-normal mode Undervoltage detection active When designing the complete system it has to be considered, that in this case (only in pre-normal mode) the pin TXD of the ATA6620N works as an output. 4.3 Pre-normal Mode At system power-up the device automatically switches to Pre-normal mode. The voltage regulator is switched on (VCC = 5V/50 mA) (see Figure 4-7 on page 11) after typically tVCC > 300 µs. The NRES output switches to low for tres = 10 ms and sends a reset to the microcontroller. LIN communication is switched off, and the undervoltage detection is active. A power-down of VBatt (VS < 4.15V) during Silent or Sleep mode switches into Pre-normal mode after powering up the IC. During this mode the TXD pin is an output. 10 ATA6620N 4850I–AUTO–09/09 ATA6620N 4.4 Unpowered Mode If battery voltage is connected to the application circuit (see Figure 4-7), the voltage at the VS pin increases due to the block capacitor. When VS is higher than the VS undervoltage threshold, V Sth , the IC-mode changes from Unpowered to Pre-normal mode. The VCC o utput voltage reaches nominal value after tVCC. This time depends on the VCC capacitor and the load. NRES is low for the reset time delay tReset; no mode change is possible during this time. Figure 4-7. VCC Voltage Regulator: Ramp Up and Undervoltage VS 12V 5.5V 3V VCC 5V Vthun NRES 5V tVCC tres tes_f 5. Fail-safe Features • During a short circuit at LIN, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip temperature exceeds tLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of thys, switches the output on again. During LIN overtemperature switch-off, the VCC regulator works independently. • There are now reverse currents < 3 µA at pin LIN during loss of VBatt or GND. This is optimal behavior for bus systems where some slave nodes are supplied from battery or ignition. • During a short circuit at VCC, the output limits the output current to IVCCn. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Pre–normal mode. If the chip temperature exceeds the value tVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of thys, switches the output on again. Because of Pre-normal mode, the VCC voltage will switch on again although EN is switched off from the microcontroller.The microcontroller can then start with normal operation. • Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. • Pin RXD is set floating if VBatt is disconnected. • Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. 11 4850I–AUTO–09/09 6. Voltage Regulator The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the microcontroller. It is recommend to use an tantalum capacitor with C > 10 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. During mode change from Silent to Normal mode, the voltage regulator ramps up to 6V for only a few microseconds before it drops back to 5V. This behavior depends on the value of the load capacitor. With 4.7 µF, the overshoot voltage has its greatest value. This voltage decreases with higher or lower load capacitors. With this special SO8 package (fused lead frame to pin3) an Rthja of 80 K/W is achieved. Therefore it is recommended to connect pin 3 with a wide GND plate on the printed board to get a good heat sink. The main power dissipation of the IC is created from the V CC o utput current IVCC , which is needed for the application. Figure 6-1 shows the safe operating area of the ATA6620N. Figure 6-1. Save Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures with Rthja = 80 K/W 60.00 Iout_85: Tamb = 85˚C Iout_95: Tamb = 95˚C Iout_105: Tamb = 105˚C 30.00 50.00 IVCC (mA) 40.00 20.00 10.00 0.00 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VS (V) For programming purposes of the microcontroller it is potentially necessary to supply the VCC output via an external power supply while the VS pin of the system basis chip is disconnected. This behavior is no problem for the system basis chip. 12 ATA6620N 4850I–AUTO–09/09 ATA6620N 7. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage VS Pulse time ≤ 500 ms T = 25°C Output current IVCC ≤ 50 mA Pulse time ≤ 2 min T = 25°C Output current IVCC ≤ 50 mA Logic pins (RXD, TXD, EN, NRES) Output current NRES LIN - DC voltage - Transient voltage VCC - DC voltage ESD (DIN EN 6100–4–2) Pin LIN, VS versus GND according to LIN specification EMC Evaluation V 1.3 HBM ESD S5.1 – all pins CDM ESD STM 5.3.1–1999 - All pins Junction temperature Storage temperature Operating ambient temperature Thermal resistance junction to ambient (free air) Special heat sink at GND (pin 3) on PCB Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Tj Ts Ta Rthja Rthja TVCCoff TLINoff Thys 150 150 80 160 160 10 170 170 INRES Symbol VS VS Min. –0.3 Typ. Max. +40 +40 Unit V V VS –0.3 –2 –40 –150 –0.3 –6 –3 –1000 –40 –55 –40 27 +6.5 +2 +60 +100 +6.5 +6 +3 +1000 +150 +150 +125 145 V V mA V V V kV kV V °C °C °C K/W K/W °C °C °C 13 4850I–AUTO–09/09 8. Electrical Characteristics 5V < VS < 18V, Tamb = –40°C to 125°C No. 1 1.1 Parameters VS Pin Nominal DC voltage range Sleep mode Supply current in Sleep Vlin > VBatt – 0.5V mode VBatt < 14V (25°C to 125°C) Bus recessive; Supply current in Silent VBatt < 14V mode (25°C to 125°C) Without load at VCC Supply current in Normal mode Supply current in Normal mode Power On Reset threshold Power On Reset threshold hysteresis VS undervoltage threshold VS undervoltage threshold hysteresis RXD Output Pin Low level input current Normal mode; VLIN = 0V VRXD = 0.4V RXD RXD RXD TXD TXD VTXD = 0V VTXD = 5V Pre-normal mode VTXD = 0.4V to 5V TXD TXD TXD IRXD VRXDL RRXD VTXDL VTXDH RTXD ITXD ITXDwake 3 –0.3 3.5 125 –3 2 5 250 5 2 5 8 0.3 7 +1.5 VCC + 0.3V 600 +3 8 mA V kΩ V V kΩ µA mA A A A A A A A A Bus recessive Without load at VCC Bus dominant VCC load current 50 mA VS VS 5 13.5 18 V A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 1.2 VS IVSsleep 10 20 µA A 1.3 VS IVSsi 40 50 µA A 1.4 1.5 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 4.4 VS VS VS VS VS VS IVSrec IVSdom PORth PORhys VSth VSth_hys 4.15 3 0.1 4.5 0.2 4 55 3.3 mA mA V V A A D D A C 5 V V Low level output voltage IRXD = 1 mA Internal resistor to VCC TXD Input/Output Pin Low level voltage input High level voltage input Pull-up resistor High level leakage current Low-level output current EN Input Pin Low level voltage input High level voltage input Pull-down resistor Low level input current VEN = 5V VEN = 0V EN EN EN EN VENL VENH REN IEN –0.3 3.5 125 –3 250 +1.5 VCC + 0.3V 600 +3 V V kΩ µA A A A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 14 ATA6620N 4850I–AUTO–09/09 ATA6620N 8. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. 5 5.1 Parameters NRES Output Pin High level output voltage VS ≥ 5.5V; INRES = –1 mA NRES VNRESH VNRESL VNRESL VNRESLL tReset tres_f 7 4.5 V A Test Conditions Pin Symbol Min. Typ. Max. Unit Type* 5.2 VS ≥ 5.5V; Low level output voltage INRES = +1 mA INRES = +250 µA Low level output low Undervoltage reset time 10 kΩ to VCC; VCC = 0.8V VVS ≥ 5.5V CNRES = 20 pF NRES 0.2 0.14 0.2 13 3 V V V ms µs A A A A A 5.3 5.4 5.5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 7.1 7.2 7.3 NRES NRES NRES Reset debounce time for VVS ≥ 5.5V CNRES = 20 pF falling edge 5.5V < VS < 18V (0 mA – 50 mA) 3.3V < VS < 5.5V VS > 4.0V, IVCC = –20 mA VS > 4.0V, IVCC = –50 mA VS > 3.3V, IVCC = –15 mA VS > 3V 1Ω < ESR < 5Ω at 100 kHz Referred to VCC VS > 5.5V Referred to VCC VS > 5.5V Voltage Regulator VCC Pin in Normal and Pre-normal Mode Output voltage VCC Output voltage VCC at low VS Regulator drop voltage Regulator drop voltage Regulator drop voltage Output current VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCCnor VCClow VD VD VD IVCC IVCCs Cload VthunN Vhysthun tVCC –50 –200 1.8 4.4 30 300 –130 2.2 4.8 4.9 VVS – VD 5.1 5.1 250 500 200 V V mV mV mV mA mA µF V mV µs A A A A A A A D A A A Output current limitation VS > 0V Load capacity VCC undervoltage threshold Hysteresis of undervoltage threshold Ramp up time VS > 5.5V CVCC = 4.7 µF to VCC > 4.9V No load Voltage Regulator VCC Pin in Silent Mode Output voltage VCC Output voltage VCC at low VS Regulator drop voltage At VCC undervoltage threshold the state switches back to Pre-normal mode Hysteresis of undervoltage threshold 5.5V < VS < 18V (0 mA – 50 mA) 3.3V < VS < 5.5V (0 mA – 50 mA) VS > 3.3V, IVCC = 15 mA Referred to VCC VS > 5.5 Referred to VCC VS > 5.5V VCC VCC VCC VCCnor VCClow VD VthunS 4.65 VVS – VD 5.35 5.1 200 V V mV A A A 7.4 VCC 3.9 4.4 V A 7.5 7.6 VCC VCC Vhysthun IVCCs 40 –200 –130 mV mA D A Output current limitation VS > 0V *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 15 4850I–AUTO–09/09 8. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. 8 Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type* LIN Bus Driver: Bus Load Conditions: Load 1 (Small): 1 nF, 1 kΩ; Load 2 (Large): 10 nF, 500Ω; RRXD = 5 kΩ; CRXD = 20 pF 10.5, 10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 Kbps Driver recessive output voltage Driver dominant voltage Driver dominant voltage Driver dominant voltage Driver dominant voltage Pull–up resistor to VS Self-adapting current limitation VBUS = VBatt_max Input leakage current at the receiver including pull–up resistor as specified Leakage current LIN recessive Leakage current when control unit disconnected from ground. Loss of local ground must not affect communication in the residual network Load1/Load2 VVS = 7V Rload = 500 Ω VVS = 18V Rload = 500 Ω VVS = 7V Rload = 1000 Ω VVS = 18V Rload = 1000 Ω The serial diode is mandatory Tj = 125°C Tj = 27°C Tj = –40°C Input Leakage current Driver off VBUS = 0V VBatt = 12V Driver off 8V < VBatt < 18V 8V < VBUS < 18V VBUS ≥ VBatt LIN LIN LIN LIN LIN LIN VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k RLIN IBUS_LIM 0.6 0.8 20 52 100 120 30 60 110 170 230 0.9 × VS VS 1.2 2 V V V V V kΩ mA mA mA A A A A A A 8.1 8.2 8.3 8.4 8.5 8.6 8.7 LIN A 8.8 LIN IBUS_PAS_dom –1 mA A 8.9 LIN IBUS_PAS_rec 15 20 µA A 8.10 GNDDevice = VS VBatt = 12V 0V < VBUS < 18V LIN IBUS_NO_gnd –10 +0.5 +10 µA A 8.11 Node has to sustain the current that can flow VBatt disconnected under this condition. VSUP_Device = GND Bus must remain 0V < VBUS < 18V operational under this condition LIN Bus Receiver Center of receiver threshold VBUS_CNT = (Vth_dom + Vth_rec)/2 LIN IBUS 0.5 3 µA A 9 9.1 9.2 9.3 9.4 LIN LIN LIN LIN VBUS_CNT VBUSdom VBUSrec VBUShys 0.475 × VS –27 0.6 × VS 0.028 × VS 0.5 × VS 0.525 × VS 0.4 × VS 40 0.175 × VS V V V V A A A A Receiver dominant state VEN = 5V Receiver recessive state VEN = 5V Receiver input hysteresis Vhys = Vth_rec – Vth_dom 0.1 × VS *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 16 ATA6620N 4850I–AUTO–09/09 ATA6620N 8. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to 125°C No. 9.5 9.6 10 10.1 Parameters Wake detection LIN High level input voltage Wake detection LIN Low level input voltage Internal Timers Dominant time for wake–up via LIN bus VLIN = 0V tbus 30 90 150 µs A ILIN = typically –3 mA Test Conditions Pin LIN LIN Symbol VLINH VLINL Min. VS – 1V –27 Typ. Max. VS + 0.3V VS – 3.3V Unit V V Type* A A 10.2 Time delay for mode change from Pre-normal VEN = 5V into Normal mode via pin EN Time delay for mode change from Normal V = 0V mode to Sleep mode via EN pin EN TXD dominant time out timer VTXD = 0V THRec(max) = 0.744 × VS; THDom(max) = 0.581 × VS; VS = 7.0V to 18V; tBit = 50 ms D1 = tbus_rec(min)/(2 × tBit) THRec(min) = 0.422 × VS; THDom(min) = 0.284 × VS; VS = 7.0V to 18V; tBit = 50ms D2 = tbus_rec(max)/(2 × tBit) tnorm 5 20 µs A 10.3 tsleep 2 7 15 µs A 10.4 tdom 6 10 20 ms A 10.5 Duty cycle 1 D1 0.396 A 10.6 Duty cycle 2 D2 0.581 A 10.7 Slope time falling and rising edge at LIN Time delay for mode change from Silent- into VEN = 5V Normal mode via EN tSLOPE_fall tSLOPE_rise ts_n 3.5 22.5 µs A 10.8 5 15 40 µs A 11 Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions (CRXD): 20 pF; Rpull-up = 2.4 kΩ Propagation delay of receiver Switch to Sleep = max(trx_pdr, trx_pdf) t mode (see Figure 8-1 on rx_pd page 18) Symmetry of receiver propagation delay rising trx_sym = trx_pdr – trx_pdf edge minus falling edge trx_pd 6 µs A 11.1 11.2 trx_sym –2 +2 µs A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 17 4850I–AUTO–09/09 Figure 8-1. Definition of Bus Timing Characteristics tBit tBit tBit TXD (Input to transmitting Node) tBus_dom(max) tBus_rec(min) THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min) Thresholds of receiving node 1 Thresholds of receiving node 2 tBus_dom(min) tBus_rec(max) RXD (Output of receiving Node1) trx_pdf(1) trx_pdr(1) RXD (Output of receiving Node2) trx_pdr(2) trx_pdf(2) 18 ATA6620N 4850I–AUTO–09/09 ATA6620N Figure 8-2. Application Circuit VCC RXD 5 ATA6620N Receiver Normal and Pre-normal Mode 1 VS 100 nF LIN VBAT 22 µF 4 Filter LIN-BUS 220 pF Microcontroller VCC Wake Up Bus Timer TXD TXD Time-out Timer Slew Rate Control Short-circuit and Overtemperature Protection 6 8 Sleep Mode VCC Undervoltage Reset Switched Silent Mode Off Voltage Regulator 5V/50 mA/7% Normal Mode Voltage Regulator 5V/50 mA/2% VCC EN 2 Control Unit 7 NRES GND 3 100 nF 10 µF 19 4850I–AUTO–09/09 9. Ordering Information Extended Type Number ATA6620N-TAQY Package SO8 Remarks LIN system basis chip, Pb-free, 4k, taped and reeled 10. Package Information Package: SO 8 Dimensions in mm 4.9±0.1 5±0.2 3.7±0.1 0.2 0.1+0.15 1.4 0.4 1.27 3.81 3.8±0.1 6±0.2 8 5 technical drawings according to DIN specifications 1 Drawing-No.: 6.541-5031.01-4 Issue: 1; 15.08.06 4 20 ATA6620N 4850I–AUTO–09/09 ATA6620N 11. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4850I-AUTO-09/09 History • Put datasheet in newest template • Heading 3.2: Supply Pin (VS): text changed • El. Characteristics table: row 1.9 changed 4850H-AUTO-12/07 • Section 3.1 “Physical Layer Compatibility” on page 3 added 4850G-AUTO-10/07 • Section 9 “Ordering Information” on page 20 changed • • • • 4850F-AUTO-07/07 • • • • • • • • • 4850E-AUTO-04/07 • • • Put datasheet in a new template Capital T for time generally changed in a lower case t Section 3.4 “Undervoltage Reset Output (NRES) on page 3 changed Section 4.2.2 “Sleep Mode” on page 8 changed Section 6 “Voltage Regulator” on page 12 changed Section 7 “Absolute Maximum Ratings” on page 13 changed Section 8 “Electrical Characteristics” numbers 5.2, 5.3 and 6.8 on page 15 changed Put datasheet in a new template ATA6620 in ATA6620N renamed Figure 1-1 “Block Diagram” on page 2 changed Table 2-1 “Pin Description” on page 2 changed Section 4-2 “Modes of Reduced Current Consumption” on page 6 changed Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page 7 changed Section 4.2.2 “Sleep Mode” on page 8 changed Figure 4-5 “LIN Wake-up Diagram from Sleep Mode” changed Section 4.2.3 “Wake-up from Sleep/Silent Mode at an Insufficient Falling Edge at pin LIN” on page 9 added • Section 4.3 “Pre-normal Mode” on page 10 changed • Section 8 “Electrical Characteristics” on pages 14 to 17 changed • Figure 8-2 “Application Circuit” on page 19 changed • • • • 4850D-AUTO-02/06 • • Section 3.5 “Bus Pin (LIN)” on page 3 changed Figure 4-1 “Mode of Operation” on page 4 changed Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page 6 changed Section 4.4 “Pre-normal Mode” on page 7 changed Section 6 “Voltage Regulator” on page 10 changed Figure 6-1 “Save Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures” on page 10 changed • Table “Absolute Maximum Ratings” on page 11 changed • Table “Electrical Characteristics” from pages 12 to 15 changed 21 4850I–AUTO–09/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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