ATA6621N-PGPW

Features • • • • • • Supply Voltage up to 40V Operating Voltage VS = 5V to 18V Slew Rate Control according to LIN Specification 2.0 Supply Current during Sleep Mode Typically 10 µA Supply Current in Silent Mode Typically 40 µA Linear Low-drop Voltage Regulator: – Normal Mode: VCC = 5V ±2%/50 mA – Silent Mode: VCC = 5V ±7%/50 mA – Sleep Mode: VCC is Switched Off VCC Undervoltage Detection (10 ms Reset time) and Watchdog Reset Logically Combined at Output NRES Possibility of Boosting the Voltage Regulator with an External NPN Transistor LIN Physical Layer according to LIN Specification 2.0 Wake-up Capability via LIN Bus or WAKE Pin Wake-up Recognition TXD Time-out Timer Debug Mode Watchdog Is Switched Off 60V Load Dump Protection at LIN Pin Bus Pin is Overtemperature and Short Circuit Protected versus GND and Battery Adjustable Watchdog Time via External Resistor Positive and Negative Trigger Input for Watchdog 5V CMOS Compatible I/O Pins to MCU Analog Temperature Monitor Output High EMC and ESD Level Package: QFN 5 × 5 with 20 Pins • • • • • • • • • • • • • • • LIN Transceiver with 5V Regulator and Watchdog ATA6621N 1. Description The ATA6621N is a fully integrated LIN transceiver, complying with the LIN specification, and with a low-drop voltage regulator for 5V/50 mA output and a window watchdog adjustable via an external resistor. In this QFN20 package, the voltage regulator is able to source 50 mA at VS = 18V even at an ambient temperature of 105°C. The output current of the regulator can be boosted by using an external NPN transistor. This combination makes it possible to develop simple, but powerful and cheap, slave nodes in LIN bus systems. ATA6621N is designed to handle the low speed data communication in vehicles, for example, in convenience electronics. Improved slope control at the LIN driver ensures secure data communication up to 20 kBaud. The bus output is capable of withstanding 60V. Sleep mode and Silent mode guarantee a very low current consumption. 4887I–AUTO–09/09 Figure 1-1. Block Diagram 20 VS VCC 9 RXD Receiver Normal Mode VS 7 Filter LIN 4 WAKE VCC Wake-up Bus Timer 11 TXD TXD Time-out Timer Slew Rate Control Short Circuit and Overtemperature Protection Control Unit 1 5 VCC EN GND Debounce Time Standby Mode Normal Mode 5V ± 2%/50 mA Silent Mode 5V ± 7%/50 mA Undervoltage Reset 19 18 VCC PVCC 12 NRES TEMP 17 OUT Watchdog VCC 15 MODE 14 TM 2 PTRIG 3 NTRIG Adjustable Watchdog Oscillator 13 WD_OSC 16 GND Internal Testing Unit 2 ATA6621N 4887I–AUTO–09/09 ATA6621N 2. Pin Configuration Figure 2-1. Pinning QFN20 TEMP 17 PVCC GND 16 15 MODE TM WD_OSC NRES TXD 14 MLP 5 mm × 5 mm 0.65 mm pitch 20 lead 13 12 11 6 NC 7 LIN 8 NC 9 RXD 10 NC VCC 19 VS 20 EN PTRIG NTRIG WAKE GND 1 18 ATA6621N 2 3 4 5 Table 2-1. Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin Description Symbol EN PTRIG NTRIG WAKE GND NC LIN NC RXD NC TXD NRES WD_OSC TM MODE GND TEMP PVCC VCC VS Backside Function Enables the device into Normal mode High-level watchdog trigger input from microcontroller; if not needed, leave open or connect to GND Low-level watchdog trigger input from microcontroller; if not needed, leave open or connect to VCC High-voltage input for local wake-up request; if not needed, connect to VS System ground Not connected LIN bus line input/output Not connected Receive data output Not connected Transmit data input; active low output (strong pull down) after a local wake-up request Output undervoltage and watchdog reset External resistor for adjustable watchdog timing For factory testing only (tie to ground) For debug mode, high watchdog off, low watchdog on Additional ground Chip temperature output pin; if not needed connect to GND 5V regulator sense input pin 5V regulator output/driver pin Battery supply Heat slug is connected to GND (pin 5) 3 4887I–AUTO–09/09 3. Functional Description 3.1 Physical Layer Compatibility Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical layer according to revision 2.0 can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3), are without any restrictions. 3.2 Supply Pin (VS) The LIN operating voltage is V S = 5V to 18V. After switching on VS, the IC starts with the Pre-normal mode and the voltage regulator is switched on (that is, 5V/50 mA output capability). The supply current in Sleep mode is typically 10 µA, and 40 µA in Silent mode. 3.3 Ground Pin (GND) The IC is neutral on the LIN pin in case of GND disconnection; it can handle a ground shift up to 3V for supply voltage at the VS pin above 9V. 3.4 Undervoltage Reset Output (NRES) This push-pull output is supplied from the VCC voltage. If the VCC voltage falls below the undervoltage detection threshold of Vthun, NRES switches to low after tres_f (Figure 3-7 on page 13) except the IC is switched into Sleep mode. Even if VCC = 0V the NRES stays low, because it is internally driven from the VS voltage. If VS voltage ramps down, NRES stays until VS < 1.5V and then becomes highly resistant. The implemented undervoltage delay keeps NRES low for tReset = 10 ms after VCC reaches its normal value. 3.5 Voltage Regulator Output Pin (VCC) The internal 5V voltage regulator is capable of driving loads with up to 50 mA of current consumption; it is able to supply the microcontroller and other ICs on the PCB. It is protected against overloads by means of current limitation and overtemperature shutdown. Furthermore, the output voltage is monitored and will cause a reset signal at the NRES output pin if the output voltage drops below a defined threshold Vthun. To boost up the maximum load current, an external NPN transistor may be used with its base connected to the VCC pin and its emitter connected to PVCC. 3.6 Voltage Regulator Sense Pin (PVCC) This is the sense input pin of the 5V voltage regulator. For normal applications (that is, when only using the internal output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be connected to the output of this transistor, its emitter terminal. 4 ATA6621N 4887I–AUTO–09/09 ATA6621N 3.7 Bus Pin (LIN) A low side driver with internal current limitation and thermal shutdown, and an internal pull-up resistor in compliance with LIN specification 2.0 is implemented. This is a self-adapting current limitation; that is, during current limitation, as the chip temperature increases, the current decreases. The allowed voltage range is between –40V and +60V. Reverse currents from the LIN bus to VS are suppressed, even in case of ground shifts or battery disconnection. LIN receiver thresholds are compatible to the LIN protocol specification. The fall time from recessive bus state to dominant, and the rise time from dominant bus state to recessive are slope controlled. 3.8 Input/Output Pin (TXD) This pin is the microcontroller interface to control the state of the LIN output. TXD must be pulled to ground in order to have the LIN bus low. If TXD is high, the LIN output transistor is turned off and the bus is in the recessive state, pulled up by the internal resistor. 3.9 TXD Dominant Time-out Function The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in the dominant state. If TXD is forced to low longer than tDOM > 6 ms, the LIN bus driver is switched to the recessive state. To reset this dominant time-out mode, TXD must be switched to high (> 10 µs) before normal data transmission can be started. 3.10 Output Pin (RXD) This pin reports the state of the LIN bus to the microcontroller. LIN high (recessive state) is reported by a high level at RXD, LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up structure with typically 5 kΩ to VCC. The AC characteristics can be defined with an external load capacitor of 20 pF. The output is short-circuit protected. In Unpowered mode (that is, VS = 0V), RXD is switched off. 3.11 Enable Input Pin (EN) This pin controls the operation mode of the interface. If EN is high, the interface is in Normal mode, with transmission paths from TXD to LIN and from LIN to RXD both being active. The VCC voltage regulator is operating with 5V ±2%/50 mA output capability. If EN is switched to low while TXD is still high, the device is forced to Silent mode. No data transmission is then possible and the current consumption is reduced to IVS = 50 µA. The current capability of the VCC regulator is also 50 mA, but the VCC tolerance is between 4.65V and 5.35V. If EN is switched to low while TXD is low, the device is forced to Sleep mode. No data transmission is possible and the voltage regulator is switched off. 3.12 Wake Input Pin (WAKE) This pin is a high voltage input used to wake the device up from Sleep mode. It is usually connected to an external switch in the application to generate a local wake-up. A pull-up current source with typically 10 µA is implemented. If you don’t need a local wake-up in your application, connect pin WAKE directly to pin VS. 5 4887I–AUTO–09/09 3.13 MODE Input Pin For normal watchdog operation connect pin MODE via an external resistor to GND (see Figure 5-2 on page 24). For debugging your software you can connect pin MODE to 5V and the watchdog is switched off. 3.14 TM Input Pin Pin TM is used in final production measurement at Atmel®. In the application it is always connected to GND. 3.15 Modes of Operation Modes of Operation Unpowered Mode VBatt = 0 a: VS > 5V b: VS < 4V c: Bus wake-up event d: NRES switches to low e: Wake-up from wake-up switch Figure 3-1. b a Pre-normal Mode b d EN = 1 Go to silent command EN = 0 TXD = 1 Normal Mode VCC: 5V ±2%/50 mA with undervoltage monitoring Communication: ON EN = 1 Go to sleep command Local wake-up event VCC: 5V/50 mA with undervoltage monitoring Communication: OFF b c+d+e c+e b Silent Mode VCC: 5V ±7%/50 mA with undervoltage monitoring Communication: OFF EN = 0 TXD = 0 Local wake-up event EN = 1 Sleep Mode VCC: switched off Communication: OFF 3.15.1 Normal Mode This is the normal transmitting and receiving mode. The voltage regulator is in normal mode and can source 50 mA. The undervoltage detection is activated. The watchdog needs a trigger signal from PTRIG or NTRIG to avoid resets at NRES. 3.15.2 Silent Mode A falling edge at EN while TXD is high switches the IC into Silent mode. The TXD signal has to be logic high during the Mode Select window (Figure 3-2 on page 7). For EN and TXD either two independent outputs can be used, or two outputs from the same microcontroller port; in the second case, the mode change is only one command. In Silent mode, the transmission path is disabled. Supply current from VBat is typically IVSsi = 40 µA with no load at the VCC regulator. 6 ATA6621N 4887I–AUTO–09/09 ATA6621N The overall supply current from VBat is the addition of 40 µA plus the VCC regulator output current IVCCs. In Silent mode, the 5V regulator is in low tolerance mode (4.65V to 5.35V) and can source up to 50 mA. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is shorted to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. The Silent mode voltage tolerance is sufficient to run the internal timers of the microcontroller. The undervoltage reset is now VccthS < 4.4V. If an undervoltage condition occurs, the NRES is switched to low and the ATA6621N changes state to Pre-normal mode. A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period (tbus) results in a remote wake-up request. The device switches from Silent mode to Pre-normal mode. The internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (see Figure 3-3 on page 8). With EN high, you can switch directly from Silent mode to Normal mode. Figure 3-2. Switch to Silent Mode Silent Mode EN TXD Mode Select window td = 3.2 µs NRES VCC Delay time Silent Mode td_sleep = maximum 15 µs LIN LIN switches directly to recessive mode 7 4887I–AUTO–09/09 Figure 3-3. LIN Wake-up Waveform Diagram from Silent Mode Pre-normal Mode Normal Mode LIN Bus VLIN < 0.4 VS TXD High RXD High Bus wake-up filtering time tbus Low VCC Silent mode Pre-normal mode Normal mode Regulator Wake-up time EN Node in Silent mode EN High NRES If undervoltage, switch to Pre-normal Mode Undervoltage detection active 8 ATA6621N 4887I–AUTO–09/09 ATA6621N 3.15.3 Sleep Mode The falling edge at EN has to occur not more than tDOMmin = 6 ms after or 3.2 µs before the falling edge at TXD in order to switch the IC into Sleep mode. The TXD Signal has to stay logic low during the Mode Select window (see Figure 3-4, see also section “Silent Mode” on page 6). In Sleep mode the transmission path is disabled. Supply current from V Bat i s typically IVSsleep = 10 µA. The VCC regulator is switched off. NRES and RXD are low. The internal slave termination between pin LIN and pin VS is disabled to minimize the power dissipation in case pin LIN is shorted to GND. Only a weak pull-up current (typically 10 µA) between pin LIN and pin VS is present. A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period (tbus) results in a remote wake-up request. The device switches from Sleep mode to Pre-normal mode. The VCC regulator is activated and the internal LIN slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to interrupt the microcontroller (see Figure 3-5 on page 10). With EN high you can switch directly from Silent mode to Normal mode. In the application where the ATA6621N supplies the microcontroller, wake-up from Sleep mode is only possible via LIN or pin WAKE. If the device is switched into Sleep mode, VCC ramps down without generating an undervoltage reset at pin NRES. Figure 3-4. Switch to Sleep Mode Sleep Mode EN TXD Mode Select window td = 3.2 µs NRES VCC Delay time Sleep Mode td_sleep = maximum 15 µs LIN LIN switches directly to recessive mode 9 4887I–AUTO–09/09 Figure 3-5. LIN Wake-up Waveform Diagram from Sleep Mode Pre-normal Mode Normal Mode LIN Bus VLIN < 0.4 VS TXD RXD Low or floating Bus wake-up filtering time tbus Low VCC On state Off state Regulator wake-up time EN High EN Node in sleep mode Reset time NRES Low or floating Microcontroller start-up time delay 3.15.4 Pre-normal Mode At system power-up the device automatically switches to Pre-normal mode. The voltage regulator is switched on VCC = 5V ±2%/50 mA (see Figure 3-7 on page 13). The NRES output switches to low for tres = 10 ms and sends a reset to the microcontroller. LIN communication is switched off and the watchdog is active. The ATA6621N stays in this mode until EN is switched to high. If VBattery (VS < 4V) is powered down during Silent mode or Sleep mode, the IC powers up into Pre-normal mode. During this mode the TXD pin is an output. 3.15.5 Unpowered Mode If you connect battery voltage to the application circuit, the voltage at the VS pin increases due to the block capacitor (see Figure 3-7 on page 13). When VS becomes higher than the VS undervoltage threshold VS_th, the IC mode changes from Unpowered mode to Pre-normal mode. The VCC output voltage reaches its nominal value after tVCC. This time depends on the VCC capacitor and the load. The NRES is low for the reset time delay treset. During this time, no mode change is possible. 10 ATA6621N 4887I–AUTO–09/09 ATA6621N 3.15.6 Debug Mode The watchdog is switched off with pin MODE high (5V) and in normal operation if it is tied to GND (see Figure 5-2 on page 24). Table 3-1. Mode of Operation Pre-normal Normal Silent Sleep Table of Modes Transceiver Off On Off Off VCC 5V 5V 5V 0V WD_OSC 2.5V 2.5V 0V 0V TEMP 2V 2V 0V 0V RXD 5V 5V 5V 0V LIN RECESSIVE RECESSIVE RECESSIVE RECESSIVE 3.16 3.16.1 Wake-up Scenarios from Silent or Sleep Mode Remote Wake-up via Dominant Bus State A falling edge at pin LIN followed by a dominant bus level maintained for a certain time period (tBUS) results in a remote wake-up request. The device switches to Pre-normal mode. The VCC voltage regulator is activated, and the internal slave termination resistor is switched on. The remote wake-up request is indicated by a low level at pin RXD to generate an interrupt in the microcontroller and a high level at pin TXD. The watchdog needs a trigger signal from PTRIG or NTRIG within the lead time tD to avoid resets at NRES (see Figure 3-3 on page 8). Local Wake-up via Pin Wake A falling edge at pin WAKE followed by a low level maintained for a certain time period (tWAKE) results in a local wake-up request. The extra long wake-up time (tWAKE) ensures that no transients as defined in ISO7637 create a wake-up. The device switches to Pre-normal mode. The internal slave termination resistor is switched on. The local wake-up request is indicated by a low level at pin RXD to generate an interrupt in the microcontroller and a low level at pin TXD. The watchdog needs a trigger signal from PTRIG or NTRIG within the lead time tD to avoid resets at NRES. Wake-up Source Recognition The device can distinguish between a local wake-up request (pin WAKE) and a remote wake-up request (dominant LIN bus state). The wake-up source can be read on pin TXD in Pre-normal mode. A high level indicates a remote wake-up request and a low level indicates a local wake-up request. The wake-up request flag (signalled on pin RXD) as well as the wake-up source flag (signalled on pin TXD) are reset immediately, if the microcontroller sets pin EN to high (see Figure 3-3 on page 8). If the ATA6621N is in Sleep mode or Silent mode and the voltage at the LIN Bus falls to a value lower than VLINL < V S – 3.3V) (see “Electrical Characteristics” numbers 9.5 and 9.6) but remains higher than 0.6 × VS, a local wake-up is indicated after the time tWAKE by a low level at the pins RXD and TXD (see Figure 3-6 on page 12). 3.16.2 3.16.3 11 4887I–AUTO–09/09 Figure 3-6. Wake Up from Sleep/Silent Mode at an Insufficient Falling Edge at Pin LIN Pre-normal Mode Normal Mode LIN Bus VLIN < VS - 1V and VLIN > 0.6 VS TXD High Low RXD High Wake-up filtering time tWAKE Low VCC Silent mode Pre-normal mode Normal mode Regulator Wake-up time EN Node in Silent mode EN High NRES If undervoltage, switch to Pre-normal Mode Undervoltage detection active 3.17 Fail-safe Features • During a short circuit at LIN, the output limits the output current to IBUS_LIM. Due to the power dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off. The chip cools down and after a hysteresis of Thys, switches the output on again. During LIN overtemperature switch-off, the VCC regulator works independently. • The reverse current at pin LIN is very low (< 3 µA) during loss of VBAT or GND. This is optimal behavior for bus systems where some slave modes are supplied from battery or ignition. • During a short circuit at VCC, the output limits the output current to IVCCn. Because of undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC switches into Pre-normal mode. If the chip temperature exceeds the value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on again. Because of Pre-normal mode, the VCC voltage will switch on again although EN is switched off from the microcontroller. The microcontroller can start its normal operation. • Pin EN provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected. • Pin RXD is connected with 5 kΩ to VCC, if VBatt is disconnected VCC is at GND level • Pin TXD provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected. 12 ATA6621N 4887I–AUTO–09/09 ATA6621N • If the WD_OSC pin has a short circuit to GND or the resistor is disconnected, the watchdog oscillator runs with a high frequency and guarantees a reset. In order to activate this feature in any condition it is recommended to enter the Silent mode (via the Normal mode) directly after power up. • The WD_OSC pin is a constant voltage regulator which supplies 2.5V for the external resistor ROSC to adjust the watchdog timing. This output is short circuit protected. A short circuit to GND causes a reset a pin NRES after typically 4 ms. An open circuit causes a reset at pin NRES after typically 7 ms. 3.18 Voltage Regulator The voltage regulator needs an external capacitor for compensation and to smooth the disturbances from the microcontroller. It is recommend to use an tantalum capacitor with C > 10 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be varied by the customer, depending on the application. During mode change from Silent to Normal mode, the voltage regulator ramps up to 6V for only a few microseconds before it drops back to 5V. This behavior depends on the value of the load capacitor. With 4.7 µF, the overshoot voltage has its greatest value. This voltage decreases with higher or lower load capacitors. The main power dissipation of the IC is created from the V CC o utput current IVCC , which is needed for the application. In Figure 3-8 on page 14 you see the safe operating range of the ATA6621N. Figure 3-7. VS 12V VCC Voltage Regulator: Ramp Up and Undervoltage 5.5V 3V t VCC 5V Vthun tvcc tres tres_f t NRES 5V t 13 4887I–AUTO–09/09 Figure 3-8. Power Dissipation: Safe Operating Area versus VCC Output Current and Supply Voltage VS at Different Ambient Temperatures with Rthja = 35 K/W 55 50 45 40 Tamb = 105˚C IVCC (mA) Tamb = 125˚C 35 30 25 20 15 10 5 0 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 VS (V) For programming purposes at the microcontroller it is potentially necessary to supply the VCC output via an external supply while the VS pin of the system basis chip is disconnected. This behavior is no problem for the system basis chip. 3.19 Watchdog The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) or the PTRIG (positive edge) input within a period time window of twd. The trigger signal must exceed a minimum time ttrigmin > 3 µs. If a triggering signal is not received, a reset signal will be generated at output NRES. The timing basis of the watchdog is provided by the internal oscillator, of which the time period Tosc is adjustable via the external resistor Rwd_osc (10 kΩ to 120 kΩ). In Silent or Sleep mode, the watchdog is switched off to reduce current consumption. Minimum time for first watchdog pulse is required after the undervoltage reset at NRES disappears and is defined as lead time td. 3.19.1 Typical Timing Sequence with Rwd_osc = 51 kΩ The trigger signal Twd is adjustable between 2.9 ms and 33 ms via the external resistor Rwd_osc. For example, with an external resistor of Rwd_oscSC = 51 kΩ ±1%, the typical parameters of the watchdog come out as follows: tOSC = 12.5 µs due to 51 kΩ td = 3922 × 12.5 µs = 49 ms t1 = 800 × 12.5 µs = 10 ms t2 = 840 × 12.5 µs = 10.5 ms tnres = 157 × 12.5 µs = 1.96 ms After every reset the watchdog always starts with the lead time. 14 ATA6621N 4887I–AUTO–09/09 ATA6621N After ramping up the battery voltage V S o r wake up from Sleep mode, the 5V regulator is switched on. The reset output NRES stays low for the time t reset ( typically 10 ms), then it switches to high and the watchdog waits for the watchdog sequence from the microcontroller. This lead time td follows after the reset and is td = 49 ms. After wake up from Silent mode the RXD switches to low. The lead time td follows the negative edge of this RXD signal. In this time, the first watchdog pulse from the microcontroller is required. If the trigger pulse NTRIG (or PTRIG, as the case may be) occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a watchdog reset with tNRES = 1.96 ms will reset the microcontroller after td = 49 ms. The times t1 and t2 have a fixed relationship with each other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 10.5 ms. To avoid false triggering from glitches, the trigger pulse must be longer than ttrigg > 3 µs. This slope serves to restart the watchdog sequence. Should the triggering signal fail in this open window t2, the NRES output will be drawn to ground after t2. A triggering signal during the closed window t1 causes NRES to immediately switch low. Figure 3-9. VCC = 5V Undervoltage Reset NRES treset = 10 ms Watchdog Reset tnres = 1.9 ms Timing Sequence with RWD_OSC = 51 kΩ td = 49 ms t1 = 10 ms twd t2 = 10.5 ms t1 t2 NTRIG PTRIG ttrigg > 3 µs 3.19.2 Worst Case Calculation with RWO_OSC = 51 kΩ The internal oscillator has a tolerance of ±20%. This means that t1 and t2 can also vary by ±20%. The worst case calculation for the watchdog period Twd the microcontroller has to provide is calculated as follows. The ideal watchdog time twd is between (t1maximum) and (t1 minimum plus t2 minimum). t1,min = 0.8 × t1 = 8 ms, t1,max = 1.2 × t1 = 12 ms t2,min = 0.8 × t2 = 8.4 ms, t2,max = 1.2 × t2 = 12.6 ms Twdmax = t1min + t2min = 8 ms + 8.4 ms = 16.4 ms Twdmin = t1max = 12 ms Twd = 14.2 ms ±2.2 ms (±15%) 15 4887I–AUTO–09/09 A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs correctly within the time period of twd = 14.2 ms (±15%) in an application with Rwd_osc = 51 kΩ. Table 3-2. Rwd_osc kΩ 10 51 91 120 Table of Watchdog Timings Oscillator Period tosc/µs 2.6 12.5 22.4 29 Lead Time td/ms 10.2 49.4 87.8 113.7 Closed Window t1/ms 2.08 10 17.92 23.2 Open Window t2/ms 2.18 10.5 18.82 24.36 Trigger Period from microcontroller Reset time twd/ms tnres/ms 2.90 14.2 25.45 32.94 0.41 1.96 3.52 4.55 3.20 Temperature Monitor at Pin TEMP In addition to the internal temperature monitoring of the voltage regulator, an additional sensor measures the junction temperature and provides a linearized voltage at the TEMP pin. Together with the analog functions of the microcontroller (for example, the analog comparator and the Analog-to-digital converter (ADC)), this enables the application to detect overload conditions and to take corresponding measures in order to prevent damage. An external capacitor buffers the voltage due to the input current of the ADC. The sensor itself is built out of three diodes which are supplied by an internal BIAS current in Pre-normal mode and Normal mode. The typical voltage at T = 27°C is Vtemp = 2.2V with a typical negative temperature coefficient of VTC,TEMP = –5.05 mV/k. In silent and sleep mode the 20 µA current source is switched off. Figure 3-10. Temperature Monitor VCC 20 µA TEMP 16 ATA6621N 4887I–AUTO–09/09 ATA6621N 4. Absolute Maximum Ratings Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage VS Pulse time ≤ 500 ms T = 25°C Output current IVCC ≤ 50 mA Pulse time ≤ 2 min T = 25°C Output current IVCC ≤ 50 mA WAKE DC and transient voltage (with 33 kΩ serial resistor) Transient voltage due to ISO7637 (coupling 1 nF) Logic pins (RXD, TXD, EN, NRES, PTRIG, NTRIG, VCC, PVCC, WD_OSC, TEMP) Output current NRES LIN - DC voltage - Transient voltage VCC DC voltage ESD (DIN EN 6100-4-2) According LIN EMC Test Specification 1.3 - Pin VS, LIN to GND - Pin WAKE (33 kΩ serial resistor) ESD HBM - All pins according to ESD S 5.1 CDM ESD STM 5.3.1-1999 - All pins Junction temperature Storage temperature Operating ambient temperature Thermal resistance junction to heat slug Thermal resistance junction to ambient, where heat slug is soldered to PCB Thermal shutdown of VCC regulator Thermal shutdown of LIN output Thermal shutdown hysteresis Tj Ts Ta Rthjc Rthja 150 150 35 165 165 10 170 170 INRES Symbol VS VS Min –0.3 Typ Max +40 +40 Unit V V VS 27 V –40 –150 –0.3 –2 –40 –150 –0.3 +40 +100 +6.5 +2 +60 +100 6.5 V V mA V V ±6 ±5 ±2 ±1 –40 –55 –40 +150 +150 +125 10 KV KV KV KV °C °C °C K/W K/W °C °C °C 17 4887I–AUTO–09/09 5. Electrical Characteristics 5V < VS < 18V, Tamb = –40°C to +125°C No. 1 1.1 Parameters VS Pin Nominal DC voltage range Supply current in Sleep mode Supply current in Silent mode Sleep mode Vlin >VBat – 0.5V VBat < 14V (25°C to 125°C) Bus recessive; VBat < 14V (25°C to 125°C) Without load at VCC VS IVSsleep 5 18 V A Test Conditions Pin Symbol Min Typ Max Unit Type* 1.2 10 20 µA A 1.3 IVSsi IVSrec IVSdom VSth VSth_hys 4.15 40 50 µA A 1.4 1.5 1.6 1.7 2 2.1 2.2 2.3 3 3.1 3.2 3.3 3.4 3.5 4 4.1 4.2 4.3 4.4 Supply current in Normal Bus recessive mode Without load at VCC Supply current in Normal Bus dominant mode VCC load current 50 mA VS undervoltage threshold VS undervoltage threshold hysteresis RXD Output Pin Low-level input current Normal mode; VLIN = 0V VRXD = 0.4V 4 55 4.5 0.2 5 mA mA V V A A A C IRXD VRXDL RRXD 2 5 8 0.3 mA V kΩ A A A Low-level output voltage IRXD = 1 mA Internal 5 kΩ resistor to VCC TXD Pin Low-level voltage input High-level voltage input Pull-up resistor High-level leakage current VTXD = 0V VTXD = 5V 3 7 VTXDL VTXDH RTXD ITXD ITXDwake –0.3 3.5 125 –3 2 5 250 +1.5 VCC + 0.3V 600 +3 8 V V kΩ µA mA A A A A A Low-level output current Pre-normal mode; at local wake-up VTXD = 0.4V to 5V EN Input Pin Low-level voltage input High-level voltage input Pull-down resistor Low-level input current VEN = 5V VEN = 0V VENL VENH REN IEN –0.3 3.5 125 –3 250 +1.5 VCC + 0.3V 600 +3 V V kΩ µA A A A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 18 ATA6621N 4887I–AUTO–09/09 ATA6621N 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. 5 5.1 Parameters NRES Output Pin High-level output voltage VS ≥ 5.5V; Inres = –1 mA VNRESH VNRESL VNRESLL treset tres_f 7 4.5 V A Test Conditions Pin Symbol Min Typ Max Unit Type* 5.2 VS ≥ 5.5V; Low-level output voltage Inres = +1 mA Inres = +250 µA Low-level output low Undervoltage reset time 10 kΩ to VCC; VCC = 0.8V VVS ≥ 5.5V CNRES = 20 pF 0.2 0.14 0.3 13 3 V V V ms µs A A A A A 5.3 5.4 5.5 6 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 7 7.1 7.2 7.3 Reset debounce time for VVS ≥ 5.5V CNRES = 20 pF falling edge Voltage Regulator VCC Pin in Normal and Pre-normal Mode Output voltage VCC Output voltage VCC at low VS Regulator drop voltage Regulator drop voltage Regulator drop voltage Output current Load capacity VCC undervoltage threshold Hysteresis of undervoltage threshold 5.5V < VS < 18V (0 mA to 50 mA) 3.3V < VS < 5.5V VS > 4.0V, IVCC = –20 mA VS > 4.0V, IVCC = –50 mA VS > 3.3V, IVCC = –15 mA VS > 3 V 1Ω < ESR < 5Ω at 100 kHz Referred to VCC VS > 5.5V Referred to VCC VS > 5.5V VCCnor VCClow VD1 VD2 VD3 IVCC IVCCs Cload VthunN Vhysthun tVCC 4.9 VVS – VD 5.1 5.1 250 500 200 V V mV mV mV mA mA µF A A A A A A A D A A A –50 –200 1.8 4.4 30 300 –130 2.2 4.8 Output current limitation VS > 0V V mV µs Ramp up time VS > 5.5V CVCC = 4.7 µF to VCC > 4.9V No load Voltage Regulator VCC Pin in Silent Mode Output voltage VCC Output voltage VCC at low VS Regulator drop voltage At VCC undervoltage threshold the state switches back to Pre-normal mode Hysteresis of undervoltage threshold 5.5V < VS < 18V (0 mA to 50 mA) 3.3V < VS < 5.5V VS > 3.3V, IVCC = –15 mA Referred to VCC VS > 5.5 Referred to VCC VS > 5.5V VCCnor VCClow VD VthunS 4.65 VVS – VD 5.35 5.1 200 V V mV A A A 7.4 3.9 4.4 V A 7.5 7.6 Vhysthun IVCCs 40 –200 –130 mV mA D A Output current limitation VS > 0V *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 19 4887I–AUTO–09/09 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. 8 Parameters Test Conditions Pin Symbol Min Typ Max Unit Type* LIN Bus Driver: Bus Load Conditions: Load1 (Small): 1 nF, 1 kΩ; Load2 (Large): 10 nF, 500Ω; RRXD = 5 kΩ; CRXD = 20 pF 10.5, 10.6 and 10.7 Specify the Timing Parameters for Proper Operation at 20 Kbps Driver recessive output voltage Driver dominant voltage Driver dominant voltage Driver dominant voltage VBUSdom_DRV_LoSUP Driver dominant voltage Pull-up resistor to VS Self-adapting current limitation VBus = VBatt_max Input leakage current at the receiver including pull-up resistor as specified Leakage current LIN recessive Load1 / Load2 VVS = 7V Rload = 500Ω VVS = 18V Rload = 500Ω VVS = 7V Rload = 1000Ω VVS = 18V Rload = 1000Ω The serial diode is mandatory Tj = 125°C Tj = 27°C Tj = –40°C Input leakage current Driver off VBUS = 0V VBattery = 12V Driver off 8V < VBattery < 18V 8V < VBUS < 18V VBUS ≥ VBatt VBUSrec V_LoSUP V_HiSUP V_LoSUP_1k V_HiSUP_1k_ RLIN IBUS_LIM 0.6 0.8 20 52 100 120 30 60 110 170 230 0.9 VS VS 1.2 2 V V V V V kΩ mA mA mA A A A A A A A 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 IBUS_PAS_dom –1 mA A 8.9 IBUS_PAS_rec 15 20 µA A 8.10 Leakage current when control unit disconnected GNDDevice = VS from ground. Loss of VBattery = 12V local ground must not 0V < VBUS < 18V affect communication in the residual network Node has to sustain the current that can flow VBattery disconnected under this condition. Bus VSUP_Device = GND must remain operational 0V < VBUS < 18V under this condition LIN Bus Receiver Center of receiver threshold VBUS_CNT = (Vth_dom + Vth_rec) / 2 IBUS_NO_gnd –10 0.5 10 µA A 8.11 IBUS 0.5 3 µA A 9 9.1 9.2 9.3 9.4 9.5 9.6 VBUS_CNT VBUSdom VBUSrec VBUShys VLINH 0.475 VS –27 0.6 VS 0.028 VS VS – 1V –27 0.5 VS 0.525 – VS 0.4 VS 40 V V V V V V A A A A A A Receiver dominant state VEN = 5V Receiver recessive state VEN = 5V Receiver input hysteresis VHYS = Vth_rec – Vth_dom Wake detection LIN High-level input voltage Wake detection LIN Low-level input voltage Initializes a wake-up signal 0.1 VS 0.175 VS VS + 0.3V VS – 3.3V VLINL *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 20 ATA6621N 4887I–AUTO–09/09 ATA6621N 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. 10 10.1 Parameters Internal Timers Dominant time for wake-up via LIN bus VLIN = 0V tbus 30 90 150 µs A Test Conditions Pin Symbol Min Typ Max Unit Type* 10.2 Time delay for mode change from Pre-normal VEN = 5V to Normal mode via pin EN Time delay for mode change from Normal into VEN = 0V Sleep mode via pin EN TXD dominant time-out timer VTXD = 0V THRec(max) = 0.744 × VS; THDom(max) = 0.581 × VS; VS = 7.0V to 18V; tBit = 50 µs D1 = tbus_rec(min) / (2 × tBit) THRec(min) = 0.422 × VS; THDom(min) = 0.284 × VS; VS = 7.0V to 18V; tBit = 50 µs D2 = tbus_rec(max) / (2 × tBit) Slope time dominant and recessive edges VWAKE = 0V tnorm 5 15 20 µs A 10.3 tsleep tdom 2 7 15 µs A 10.4 6 10 20 ms A 10.5 Duty cycle 1 D1 0.396 A 10.6 Duty cycle 2 D2 0.581 A 10.7 10.8 11 11.1 Slope time falling and rising edge at LIN Time of low pulse for wake-up via pin WAKE tSLOPE_fall tSLOPE_rise tWAKE 3.5 60 130 22.5 200 µs µs A A Internal Receiver Electrical AC Parameters of the LIN Physical Layer LIN Receiver, RXD Load Conditions (CRXD): 20 pF Propagation delay of receiver (see Figure 5-1 trec_pd = max(trx_pdr, trx_pdf) on page 23) Symmetry of receiver propagation delay rising trx_sym = trx_pdr – trx_pdf edge minus falling edge Watchdog Input PTRIG and NTRIG Watchdog input high-level threshold Watchdog input low threshold Internal pull down PTRIG Internal pull down PTRIG V_HPTRIG V_LPTRIG RpdPTRIG RpuNTRIG 250 3.5 1.5 600 V V kΩ A A A trx_pd 6 µs A 11.2 12 12.1 12.2 12.3 trx_sym –2 +2 µs A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 21 4887I–AUTO–09/09 5. Electrical Characteristics (Continued) 5V < VS < 18V, Tamb = –40°C to +125°C No. 13 13.1 13.2 13.3 13.4 13.5 13.6 14 14.1 14.2 14.3 14.4 15 15.1 Parameters Watchdog Oscillator Voltage at WD_OSC in Normal mode Possible values of resistor Oscillator period Oscillator period Oscillator period Oscillator period Watchdog lead time after reset Watchdog closed window Watchdog open window Watchdog reset time NRES Temperature Monitor at Pin TEMP Voltage at TEMP in Normal mode (T = –40°C) ITEMP = ±3 µA VTEMP VTEMP VTEMP ITEMP VTC,TEMP VWAKEH Initializes a wake-up signal VS < 27V, VWake = 0V VS = 27V; VWake = 27V VWAKEL IWAKE IWAKEL 2.35 2.7 V A ROSC = 10 kΩ ROSC = 51 kΩ ROSC = 91 kΩ ROSC = 120 kΩ IWD_OSC = –250 µA VWD_OSC ROSC tOSC tOSC tOSC tOSC 2.3 10 2.1 10 17.9 23.2 2.6 12.5 22.4 29 2.5 2.7 120 3.1 15 26.8 34.8 V kΩ µs µs µs µs A D A A A A Test Conditions Pin Symbol Min Typ Max Unit Type* Watchdog Timing Relative to tOSC td t1 t2 tnres 3922 800 840 157 cycles cycles cycles cycles A A A A 15.1 Voltage at TEMP in = ±3 µA I Normal mode (T = 27°C) TEMP Voltage at TEMP in Normal mode (T = 125°C) Short current at TEMP Temperature gradient Wake Pin High-level input voltage Low-level input voltage Wake pull-up current High-level leakage current Mode Input Pin Low-level voltage input High-level voltage input High-level leakage current VMODE = VCC or VMODE = 0V ITEMP = ±3 µA VTEMP = 0V 2.0 2.35 V A 15.1 15.2 15.3 16 16.1 16.2 16.3 16.4 17 17.1 17.2 17.3 1.4 –30 4.8 VS – 1V –27 –30 –5 –10 5.05 1.9 –15 5.3 VS + 0.3V VS – 3.3V V µA mV/k V V µA A A C A A A A +5 µA VMODEL VMODEH IMODE –0.3 2 –3 +0.8V VS + 0.3V +3 V V µA A A A *) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter 22 ATA6621N 4887I–AUTO–09/09 ATA6621N Figure 5-1. Definition of Bus Timing Parameters tBit TXD (input to transmitting node) tBit tBit tBus_dom(max) tBus_rec(min) THRec(max) VS (Transceiver supply of transmitting node) THDom(max) LIN Bus Signal THRec(min) THDom(min) Thresholds of receiving node1 Thresholds of receiving node2 tBus_dom(min) tBus_rec(max) RXD (output of receiving node1) trx_pdf(1) trx_pdr(1) RXD (output of receiving node2) trx_pdr(2) trx_pdf(2) 23 4887I–AUTO–09/09 Figure 5-2. Application Circuit VBattery 22 µF + 100 nF 1 nF PVCC TEMP Master node pull-up VS 100 nF + 10 µF GND VCC 10 kΩ debug 1 kΩ 20 19 18 17 16 15 EN VCC PTRIG NTRIG 1 MODE TM WD_OSC NRES TXD 10 kΩ LIN sub bus 220 pF 4887I–AUTO–09/09 ATA6621N 2 3 4 5 6 7 8 9 10 MLP 5 mm × 5 mm 0.65 mm pitch 20 lead 14 13 12 11 10 kΩ Microcontroller 33 kΩ WAKE GND EN PTRIG Wake-up switch NC LIN NC NTRIG RXD TXD GND RESET 24 ATA6621N RXD NC ATA6621N Figure 5-3. Application Circuit with External NPN VBattery 22 µF + 100 nF MJD31C + Master node pull-up 1 nF 2.2 µF 100 nF + 10 µF PVCC TEMP VS 10 kΩ GND VCC 3Ω 1 kΩ debug 20 19 18 17 16 15 EN VCC PTRIG NTRIG 1 MODE TM WD_OSC NRES TXD 10 kΩ LIN sub bus 220 pF 10 kΩ ATA6621N 2 3 4 5 6 7 8 9 10 MLP 5 mm × 5 mm 0.65 mm pitch 20 lead 14 13 12 11 Microcontroller 33 kΩ WAKE GND EN PTRIG Wake-up switch RXD NC LIN NC NTRIG RXD TXD GND RESET NC 25 4887I–AUTO–09/09 6. Ordering Information Extended Type Number ATA6621N-PGPW ATA6621N-PGQW Package QFN20 QFN20 Remarks Pb-free, 1.5k, taped and reeled Pb-free, 6k, taped and reeled 7. Package Information Package: QFN 20 - 5 x 5 Exposed pad 3.1 x 3.1 Dimensions in mm Not indicated tolerances ± 0.05 0.9±0.1 0.05-0.05 20 1 15 16 +0 5 3.1 20 1 technical drawings according to DIN specifications 5 0.28 0.6 11 10 6 5 0.65 nom. Drawing-No.: 6.543-5094.01-4 Issue: 1; 19.12.02 2.6 26 ATA6621N 4887I–AUTO–09/09 ATA6621N 8. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4887I-AUTO-09/09 History • Put datasheet in newest template • Heading 3.2: Supply Pin (VS): text changed • El. Characteristics table: row 1.7 changed 4887H-AUTO-12/07 • Section 3.1 “Physical Layer Compatibility” on page 3 added 4887G-AUTO-10/07 • Section 6 “Ordering Information” on page 26 changed • • • • 4887F-AUTO-07/07 • • • • • • • • • • • 4887E-AUTO-04/07 • • • • • • • • • • • • • 4887D-AUTO-12/06 • • • Put datasheet in a new template Capital T for time generally changed in a lower case t Section 3.3 “Undervoltage Reset Output (NRES)” on page 4 added Section 3.14.3 “Sleep Mode” on page 9 changed Section 3.16 “Fail-safe Features” on page 13 changed Section 3.17 “Voltage Regulator” on page 14 changed Section 3.18 “Watchdog” on page 14 changed Section 4 “Absolute Maximum Ratings” on page 17 changed Section 5 “Electrical Characteristics” numbers 5.1 and 6.8 changed Section title 3.6 on page 4 renamed Section 3.7 “TXD Dominant Time-out Function” on page 5 changed Figure 3-3 “LIN Wake-up Waveform Diagram from Silent Mode on page 8 changed Section 3.13.4 “Pre-normal Mode” on page 9 changed Figure 3-5 “LIN Wake-up Waveform Diagram from Sleep Mode” on page 10 changed Section 3.14.1 “Remote Wake-up via Dominant Bus State” on page 11 changed Section 3.14.2 “Local Wake-up via Pin Wake” on page 11 changed Section 3.14.3 “Wake-up Source Recognition” on page 11 changed Figure 3-6 “Wake-up from Sleep/Silent Mode at an Insufficient Falling Edge at Pin LIN” on page 12 changed Figure title 3-8 on page 14 renamed Section 5 “Electrical Characteristics” number 3.5 on page 18 changed Figure 5-2 “Application Circuit” on page 24 changed Figure 5-3 “Application Circuit with External NPN” on page 25 changed Put datasheet in a new template Table 2-1 “Pin Description” on page 3 changed Section 3.1 “Supply Pin (VS)” on page 4 changed Section 3.7 “TXD Dominant Time-out Function” on page 5 changed Section 3.13.3 “Sleep Mode” on page 8 changed Section 3.14 in “Wake-up Scenarios from Silent or Sleep Mode” renamed Section 3.15 “Fail-safe Features” on page 11 changed Section 3.18 “Temperature Monitor at Pin TEMP” changed Table “Electrical Characteristics” numbers 10.4, 13.2 and 15.3 on pages 20 to 21 changed • Table “Electrical Characteristics” numbers 17.1, 17.2 and 17.3 on page 22 added • Section 6 “Ordering Information” on page 25 changed 27 4887I–AUTO–09/09 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 International Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-en-Yvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Product Contact Web Site www.atmel.com Technical Support auto_control@atmel.com Sales Contact www.atmel.com/contacts Literature Requests www.atmel.com/literature Disclaimer: T he information in this document is provided in connection with Atmel products. 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